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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.23 97.89 95.77 93.31 100.00 98.55 99.00 96.11


Total test records in report: 998
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T812 /workspace/coverage/default/39.lc_ctrl_security_escalation.677613543 May 30 02:12:24 PM PDT 24 May 30 02:12:38 PM PDT 24 3000021917 ps
T813 /workspace/coverage/default/39.lc_ctrl_volatile_unlock_smoke.2869054076 May 30 02:12:09 PM PDT 24 May 30 02:12:11 PM PDT 24 40601324 ps
T814 /workspace/coverage/default/24.lc_ctrl_stress_all.3373220841 May 30 02:11:25 PM PDT 24 May 30 02:12:11 PM PDT 24 3047508846 ps
T815 /workspace/coverage/default/9.lc_ctrl_jtag_access.2485495171 May 30 02:10:36 PM PDT 24 May 30 02:10:38 PM PDT 24 83625428 ps
T816 /workspace/coverage/default/10.lc_ctrl_security_escalation.3406270146 May 30 02:10:33 PM PDT 24 May 30 02:10:42 PM PDT 24 446259983 ps
T817 /workspace/coverage/default/32.lc_ctrl_sec_mubi.4040629816 May 30 02:11:51 PM PDT 24 May 30 02:12:01 PM PDT 24 232453063 ps
T818 /workspace/coverage/default/0.lc_ctrl_prog_failure.3972650754 May 30 02:09:38 PM PDT 24 May 30 02:09:44 PM PDT 24 103343646 ps
T819 /workspace/coverage/default/10.lc_ctrl_jtag_smoke.536917485 May 30 02:10:38 PM PDT 24 May 30 02:10:44 PM PDT 24 312303119 ps
T820 /workspace/coverage/default/30.lc_ctrl_stress_all.4264271074 May 30 02:11:49 PM PDT 24 May 30 02:14:13 PM PDT 24 24769283119 ps
T821 /workspace/coverage/default/44.lc_ctrl_smoke.381778548 May 30 02:12:23 PM PDT 24 May 30 02:12:27 PM PDT 24 135137826 ps
T822 /workspace/coverage/default/2.lc_ctrl_state_failure.3744251391 May 30 02:09:53 PM PDT 24 May 30 02:10:19 PM PDT 24 2953068563 ps
T823 /workspace/coverage/default/13.lc_ctrl_sec_token_mux.543418040 May 30 02:10:57 PM PDT 24 May 30 02:11:08 PM PDT 24 1010292286 ps
T824 /workspace/coverage/default/49.lc_ctrl_errors.4070816384 May 30 02:12:46 PM PDT 24 May 30 02:13:00 PM PDT 24 447094184 ps
T825 /workspace/coverage/default/34.lc_ctrl_sec_token_mux.3122405308 May 30 02:12:02 PM PDT 24 May 30 02:12:11 PM PDT 24 1154418095 ps
T826 /workspace/coverage/default/8.lc_ctrl_prog_failure.4243852076 May 30 02:10:17 PM PDT 24 May 30 02:10:21 PM PDT 24 200574685 ps
T827 /workspace/coverage/default/31.lc_ctrl_sec_token_digest.1347945590 May 30 02:11:50 PM PDT 24 May 30 02:12:10 PM PDT 24 803871027 ps
T828 /workspace/coverage/default/0.lc_ctrl_jtag_prog_failure.968219479 May 30 02:09:39 PM PDT 24 May 30 02:09:47 PM PDT 24 350214984 ps
T829 /workspace/coverage/default/26.lc_ctrl_security_escalation.3506593712 May 30 02:11:39 PM PDT 24 May 30 02:11:48 PM PDT 24 854825747 ps
T830 /workspace/coverage/default/15.lc_ctrl_sec_token_mux.1687257775 May 30 02:10:55 PM PDT 24 May 30 02:11:04 PM PDT 24 741855825 ps
T831 /workspace/coverage/default/48.lc_ctrl_volatile_unlock_smoke.3241154583 May 30 02:12:39 PM PDT 24 May 30 02:12:41 PM PDT 24 12203179 ps
T832 /workspace/coverage/default/31.lc_ctrl_prog_failure.3721515983 May 30 02:11:47 PM PDT 24 May 30 02:11:50 PM PDT 24 70336343 ps
T833 /workspace/coverage/default/7.lc_ctrl_jtag_priority.1191382596 May 30 02:10:21 PM PDT 24 May 30 02:10:27 PM PDT 24 143731695 ps
T834 /workspace/coverage/default/8.lc_ctrl_stress_all.2418903994 May 30 02:10:21 PM PDT 24 May 30 02:15:41 PM PDT 24 9654256106 ps
T835 /workspace/coverage/default/12.lc_ctrl_sec_mubi.3133477469 May 30 02:10:39 PM PDT 24 May 30 02:10:56 PM PDT 24 1327752783 ps
T836 /workspace/coverage/default/4.lc_ctrl_jtag_priority.4109293371 May 30 02:09:52 PM PDT 24 May 30 02:09:58 PM PDT 24 1510205358 ps
T837 /workspace/coverage/default/14.lc_ctrl_stress_all.163200086 May 30 02:10:52 PM PDT 24 May 30 02:15:13 PM PDT 24 9041090540 ps
T838 /workspace/coverage/default/43.lc_ctrl_jtag_access.378791436 May 30 02:12:23 PM PDT 24 May 30 02:12:26 PM PDT 24 435232907 ps
T839 /workspace/coverage/default/23.lc_ctrl_prog_failure.2538740712 May 30 02:11:29 PM PDT 24 May 30 02:11:32 PM PDT 24 48009130 ps
T840 /workspace/coverage/default/48.lc_ctrl_state_failure.1459542885 May 30 02:12:36 PM PDT 24 May 30 02:13:00 PM PDT 24 2307016361 ps
T841 /workspace/coverage/default/11.lc_ctrl_sec_token_mux.3196329961 May 30 02:10:36 PM PDT 24 May 30 02:10:50 PM PDT 24 2513276550 ps
T842 /workspace/coverage/default/36.lc_ctrl_smoke.2861876470 May 30 02:12:00 PM PDT 24 May 30 02:12:04 PM PDT 24 580478444 ps
T843 /workspace/coverage/default/8.lc_ctrl_errors.2483025599 May 30 02:10:17 PM PDT 24 May 30 02:10:33 PM PDT 24 779016896 ps
T844 /workspace/coverage/default/20.lc_ctrl_sec_token_mux.1683111695 May 30 02:11:16 PM PDT 24 May 30 02:11:24 PM PDT 24 708649971 ps
T845 /workspace/coverage/default/25.lc_ctrl_state_post_trans.854615730 May 30 02:11:29 PM PDT 24 May 30 02:11:34 PM PDT 24 122597942 ps
T846 /workspace/coverage/default/7.lc_ctrl_sec_token_digest.4126818768 May 30 02:10:20 PM PDT 24 May 30 02:10:32 PM PDT 24 225158080 ps
T847 /workspace/coverage/default/3.lc_ctrl_smoke.214095422 May 30 02:09:49 PM PDT 24 May 30 02:09:51 PM PDT 24 73999571 ps
T848 /workspace/coverage/default/29.lc_ctrl_security_escalation.3520152113 May 30 02:11:48 PM PDT 24 May 30 02:12:04 PM PDT 24 778321240 ps
T849 /workspace/coverage/default/13.lc_ctrl_sec_token_digest.2287754672 May 30 02:10:53 PM PDT 24 May 30 02:11:08 PM PDT 24 371058369 ps
T850 /workspace/coverage/default/23.lc_ctrl_state_post_trans.3492467266 May 30 02:11:27 PM PDT 24 May 30 02:11:38 PM PDT 24 221237964 ps
T851 /workspace/coverage/default/12.lc_ctrl_jtag_prog_failure.3905218015 May 30 02:10:38 PM PDT 24 May 30 02:11:01 PM PDT 24 2952390223 ps
T852 /workspace/coverage/default/6.lc_ctrl_alert_test.2230228302 May 30 02:10:20 PM PDT 24 May 30 02:10:22 PM PDT 24 45437270 ps
T853 /workspace/coverage/default/20.lc_ctrl_state_failure.756903786 May 30 02:11:10 PM PDT 24 May 30 02:11:39 PM PDT 24 1102261106 ps
T854 /workspace/coverage/default/8.lc_ctrl_jtag_access.4083924337 May 30 02:10:22 PM PDT 24 May 30 02:10:34 PM PDT 24 2687798257 ps
T855 /workspace/coverage/default/27.lc_ctrl_sec_token_digest.286690206 May 30 02:11:41 PM PDT 24 May 30 02:11:53 PM PDT 24 4766869859 ps
T856 /workspace/coverage/default/5.lc_ctrl_errors.1066365984 May 30 02:10:09 PM PDT 24 May 30 02:10:20 PM PDT 24 793893990 ps
T857 /workspace/coverage/default/3.lc_ctrl_jtag_access.163249348 May 30 02:09:53 PM PDT 24 May 30 02:09:59 PM PDT 24 411423283 ps
T858 /workspace/coverage/default/29.lc_ctrl_sec_token_digest.2464559184 May 30 02:11:46 PM PDT 24 May 30 02:11:58 PM PDT 24 658811189 ps
T859 /workspace/coverage/default/33.lc_ctrl_prog_failure.2105744544 May 30 02:11:59 PM PDT 24 May 30 02:12:04 PM PDT 24 75705857 ps
T860 /workspace/coverage/default/38.lc_ctrl_sec_mubi.267846178 May 30 02:12:24 PM PDT 24 May 30 02:12:39 PM PDT 24 2085975352 ps
T861 /workspace/coverage/default/8.lc_ctrl_jtag_errors.1481893869 May 30 02:10:19 PM PDT 24 May 30 02:10:52 PM PDT 24 8522928822 ps
T862 /workspace/coverage/default/31.lc_ctrl_volatile_unlock_smoke.695522625 May 30 02:12:00 PM PDT 24 May 30 02:12:02 PM PDT 24 72376297 ps
T863 /workspace/coverage/default/25.lc_ctrl_volatile_unlock_smoke.3540645144 May 30 02:11:31 PM PDT 24 May 30 02:11:33 PM PDT 24 34792131 ps
T864 /workspace/coverage/default/45.lc_ctrl_state_post_trans.1975334994 May 30 02:12:38 PM PDT 24 May 30 02:12:49 PM PDT 24 94561948 ps
T865 /workspace/coverage/default/25.lc_ctrl_sec_mubi.4141349395 May 30 02:11:26 PM PDT 24 May 30 02:11:39 PM PDT 24 310453324 ps
T866 /workspace/coverage/default/27.lc_ctrl_stress_all.3902702837 May 30 02:11:41 PM PDT 24 May 30 02:19:36 PM PDT 24 12850455395 ps
T867 /workspace/coverage/default/34.lc_ctrl_smoke.1454339942 May 30 02:11:50 PM PDT 24 May 30 02:11:54 PM PDT 24 311257965 ps
T868 /workspace/coverage/default/37.lc_ctrl_errors.3417906276 May 30 02:12:00 PM PDT 24 May 30 02:12:18 PM PDT 24 1611461341 ps
T869 /workspace/coverage/default/39.lc_ctrl_smoke.2163405127 May 30 02:12:11 PM PDT 24 May 30 02:12:13 PM PDT 24 22314392 ps
T870 /workspace/coverage/default/40.lc_ctrl_jtag_access.739890160 May 30 02:12:11 PM PDT 24 May 30 02:12:15 PM PDT 24 148352152 ps
T871 /workspace/coverage/default/17.lc_ctrl_errors.4266986480 May 30 02:11:02 PM PDT 24 May 30 02:11:15 PM PDT 24 320347585 ps
T872 /workspace/coverage/default/29.lc_ctrl_state_failure.1193550347 May 30 02:11:47 PM PDT 24 May 30 02:12:16 PM PDT 24 455409241 ps
T873 /workspace/coverage/default/44.lc_ctrl_sec_mubi.2454621498 May 30 02:12:33 PM PDT 24 May 30 02:12:49 PM PDT 24 2419288971 ps
T874 /workspace/coverage/default/15.lc_ctrl_jtag_prog_failure.2722330242 May 30 02:10:59 PM PDT 24 May 30 02:11:07 PM PDT 24 476698786 ps
T136 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.2561551670 May 30 02:05:53 PM PDT 24 May 30 02:05:55 PM PDT 24 71434970 ps
T137 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.1833724973 May 30 02:07:14 PM PDT 24 May 30 02:07:17 PM PDT 24 16328792 ps
T127 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.3655777914 May 30 02:07:01 PM PDT 24 May 30 02:07:04 PM PDT 24 71642426 ps
T128 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.2209194621 May 30 02:07:13 PM PDT 24 May 30 02:07:16 PM PDT 24 14325511 ps
T159 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.1110504442 May 30 02:05:54 PM PDT 24 May 30 02:06:02 PM PDT 24 767410811 ps
T124 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.1450285486 May 30 02:07:16 PM PDT 24 May 30 02:07:21 PM PDT 24 87245447 ps
T215 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.3582132156 May 30 02:05:54 PM PDT 24 May 30 02:05:56 PM PDT 24 20454737 ps
T125 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.767443026 May 30 02:07:14 PM PDT 24 May 30 02:07:18 PM PDT 24 70010530 ps
T875 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.3870702099 May 30 02:07:16 PM PDT 24 May 30 02:07:18 PM PDT 24 82698237 ps
T126 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.3423733354 May 30 02:05:52 PM PDT 24 May 30 02:05:56 PM PDT 24 403169670 ps
T132 /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.4246669288 May 30 02:05:52 PM PDT 24 May 30 02:05:54 PM PDT 24 23027121 ps
T157 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1889337646 May 30 02:06:59 PM PDT 24 May 30 02:07:03 PM PDT 24 102875549 ps
T129 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.2243747514 May 30 02:07:11 PM PDT 24 May 30 02:07:14 PM PDT 24 659109321 ps
T158 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3796490026 May 30 02:07:04 PM PDT 24 May 30 02:07:09 PM PDT 24 103470340 ps
T876 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.3955776868 May 30 02:06:55 PM PDT 24 May 30 02:06:58 PM PDT 24 126151791 ps
T130 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.195322148 May 30 02:07:10 PM PDT 24 May 30 02:07:14 PM PDT 24 244249974 ps
T154 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.2529049871 May 30 02:05:43 PM PDT 24 May 30 02:05:49 PM PDT 24 328548491 ps
T877 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.2831202718 May 30 02:06:58 PM PDT 24 May 30 02:07:02 PM PDT 24 205353889 ps
T878 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.3725869143 May 30 02:06:55 PM PDT 24 May 30 02:06:57 PM PDT 24 195617148 ps
T131 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.1266716726 May 30 02:06:55 PM PDT 24 May 30 02:07:00 PM PDT 24 234378025 ps
T208 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.4179984165 May 30 02:05:52 PM PDT 24 May 30 02:05:54 PM PDT 24 37221777 ps
T155 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.3268988205 May 30 02:06:56 PM PDT 24 May 30 02:07:01 PM PDT 24 121899898 ps
T139 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.269831248 May 30 02:07:10 PM PDT 24 May 30 02:07:15 PM PDT 24 131207372 ps
T133 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.2167795175 May 30 02:07:11 PM PDT 24 May 30 02:07:14 PM PDT 24 194812515 ps
T879 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.3510988077 May 30 02:05:52 PM PDT 24 May 30 02:05:53 PM PDT 24 95138042 ps
T194 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.906114913 May 30 02:05:54 PM PDT 24 May 30 02:05:55 PM PDT 24 14761607 ps
T880 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.4266231436 May 30 02:06:59 PM PDT 24 May 30 02:07:02 PM PDT 24 84933465 ps
T881 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.2695852599 May 30 02:05:52 PM PDT 24 May 30 02:06:00 PM PDT 24 7000710275 ps
T156 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.3060949692 May 30 02:07:03 PM PDT 24 May 30 02:07:05 PM PDT 24 55787589 ps
T882 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.1745684133 May 30 02:05:54 PM PDT 24 May 30 02:05:57 PM PDT 24 66590097 ps
T173 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.2771550657 May 30 02:05:52 PM PDT 24 May 30 02:05:54 PM PDT 24 47242116 ps
T209 /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.3611994050 May 30 02:05:55 PM PDT 24 May 30 02:05:57 PM PDT 24 26328081 ps
T883 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.1520633413 May 30 02:06:55 PM PDT 24 May 30 02:06:57 PM PDT 24 41110232 ps
T174 /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.1665328291 May 30 02:06:58 PM PDT 24 May 30 02:07:01 PM PDT 24 25839270 ps
T210 /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.361614891 May 30 02:07:16 PM PDT 24 May 30 02:07:19 PM PDT 24 81646619 ps
T884 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.2125033033 May 30 02:06:59 PM PDT 24 May 30 02:07:02 PM PDT 24 50804770 ps
T211 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.2908933206 May 30 02:06:55 PM PDT 24 May 30 02:06:57 PM PDT 24 27359911 ps
T175 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.622065952 May 30 02:07:12 PM PDT 24 May 30 02:07:14 PM PDT 24 48779620 ps
T885 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.162043636 May 30 02:06:56 PM PDT 24 May 30 02:06:59 PM PDT 24 303184206 ps
T176 /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.1292608684 May 30 02:06:54 PM PDT 24 May 30 02:06:56 PM PDT 24 63065113 ps
T886 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.430849925 May 30 02:06:57 PM PDT 24 May 30 02:07:00 PM PDT 24 61797234 ps
T212 /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.3264633527 May 30 02:07:14 PM PDT 24 May 30 02:07:17 PM PDT 24 57432656 ps
T143 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.2164960515 May 30 02:06:55 PM PDT 24 May 30 02:06:58 PM PDT 24 34972844 ps
T887 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.3114153656 May 30 02:05:55 PM PDT 24 May 30 02:05:57 PM PDT 24 34107074 ps
T888 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.1755948757 May 30 02:06:58 PM PDT 24 May 30 02:07:10 PM PDT 24 446597102 ps
T195 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.292244485 May 30 02:07:02 PM PDT 24 May 30 02:07:05 PM PDT 24 17495451 ps
T889 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.3381391048 May 30 02:06:58 PM PDT 24 May 30 02:07:01 PM PDT 24 67157023 ps
T890 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.3484270445 May 30 02:06:22 PM PDT 24 May 30 02:06:24 PM PDT 24 113888565 ps
T891 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.824501370 May 30 02:07:06 PM PDT 24 May 30 02:07:08 PM PDT 24 276288100 ps
T140 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.3993123056 May 30 02:07:12 PM PDT 24 May 30 02:07:17 PM PDT 24 388582998 ps
T892 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3864171847 May 30 02:05:53 PM PDT 24 May 30 02:05:56 PM PDT 24 373186537 ps
T893 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.2073270893 May 30 02:06:55 PM PDT 24 May 30 02:06:57 PM PDT 24 106260437 ps
T152 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.1800835870 May 30 02:07:00 PM PDT 24 May 30 02:07:05 PM PDT 24 86280437 ps
T147 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.495914746 May 30 02:07:14 PM PDT 24 May 30 02:07:19 PM PDT 24 93030780 ps
T894 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.1816562522 May 30 02:05:51 PM PDT 24 May 30 02:05:54 PM PDT 24 41600867 ps
T895 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.3398860984 May 30 02:07:14 PM PDT 24 May 30 02:07:17 PM PDT 24 21164141 ps
T151 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.1871317801 May 30 02:05:52 PM PDT 24 May 30 02:05:57 PM PDT 24 207583315 ps
T138 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.3867193938 May 30 02:07:12 PM PDT 24 May 30 02:07:16 PM PDT 24 102107254 ps
T142 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.2039667268 May 30 02:07:09 PM PDT 24 May 30 02:07:13 PM PDT 24 449917678 ps
T213 /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.4197574777 May 30 02:06:59 PM PDT 24 May 30 02:07:02 PM PDT 24 23593133 ps
T896 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1536863272 May 30 02:06:55 PM PDT 24 May 30 02:06:59 PM PDT 24 424933879 ps
T897 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.426944086 May 30 02:07:16 PM PDT 24 May 30 02:07:20 PM PDT 24 29098178 ps
T898 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.3856777963 May 30 02:06:58 PM PDT 24 May 30 02:07:11 PM PDT 24 3170979016 ps
T134 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.2394055414 May 30 02:07:13 PM PDT 24 May 30 02:07:17 PM PDT 24 123632888 ps
T899 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.863720998 May 30 02:06:55 PM PDT 24 May 30 02:06:57 PM PDT 24 44835203 ps
T900 /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.4292123970 May 30 02:07:06 PM PDT 24 May 30 02:07:08 PM PDT 24 17376136 ps
T901 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.2819824650 May 30 02:07:12 PM PDT 24 May 30 02:07:14 PM PDT 24 67649729 ps
T902 /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.2840308044 May 30 02:06:58 PM PDT 24 May 30 02:07:01 PM PDT 24 39877519 ps
T903 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.1784819593 May 30 02:06:58 PM PDT 24 May 30 02:07:06 PM PDT 24 489267906 ps
T904 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.1359788986 May 30 02:05:53 PM PDT 24 May 30 02:06:04 PM PDT 24 803936388 ps
T905 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.1593220809 May 30 02:06:24 PM PDT 24 May 30 02:06:41 PM PDT 24 2856019033 ps
T906 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.2762060183 May 30 02:07:04 PM PDT 24 May 30 02:07:07 PM PDT 24 134245643 ps
T907 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.1447727734 May 30 02:07:13 PM PDT 24 May 30 02:07:16 PM PDT 24 37024638 ps
T196 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.2122851280 May 30 02:06:25 PM PDT 24 May 30 02:06:27 PM PDT 24 65236043 ps
T908 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.1338911690 May 30 02:06:22 PM PDT 24 May 30 02:06:24 PM PDT 24 225740907 ps
T909 /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.3201589404 May 30 02:07:14 PM PDT 24 May 30 02:07:17 PM PDT 24 21300846 ps
T910 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.547653377 May 30 02:07:13 PM PDT 24 May 30 02:07:15 PM PDT 24 43172675 ps
T911 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.631422163 May 30 02:06:57 PM PDT 24 May 30 02:07:01 PM PDT 24 516609939 ps
T912 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.3875916532 May 30 02:06:57 PM PDT 24 May 30 02:06:59 PM PDT 24 70242117 ps
T913 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.3988186197 May 30 02:05:51 PM PDT 24 May 30 02:05:53 PM PDT 24 57640371 ps
T150 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.2280046439 May 30 02:06:58 PM PDT 24 May 30 02:07:02 PM PDT 24 259040081 ps
T914 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1210352026 May 30 02:05:50 PM PDT 24 May 30 02:05:54 PM PDT 24 90378186 ps
T197 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.3639295802 May 30 02:06:22 PM PDT 24 May 30 02:06:23 PM PDT 24 23137709 ps
T915 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.2634520236 May 30 02:07:16 PM PDT 24 May 30 02:07:19 PM PDT 24 14029390 ps
T916 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.301809800 May 30 02:06:20 PM PDT 24 May 30 02:06:22 PM PDT 24 57096695 ps
T917 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.4056925632 May 30 02:06:22 PM PDT 24 May 30 02:06:28 PM PDT 24 2501432872 ps
T918 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.896335920 May 30 02:07:14 PM PDT 24 May 30 02:07:17 PM PDT 24 31688368 ps
T919 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.3880242251 May 30 02:05:52 PM PDT 24 May 30 02:05:55 PM PDT 24 137171903 ps
T920 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.3979469112 May 30 02:05:52 PM PDT 24 May 30 02:05:55 PM PDT 24 140388160 ps
T921 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.2086727372 May 30 02:05:41 PM PDT 24 May 30 02:05:44 PM PDT 24 242389939 ps
T922 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.3192774099 May 30 02:07:00 PM PDT 24 May 30 02:07:03 PM PDT 24 51992172 ps
T198 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.1007097465 May 30 02:07:16 PM PDT 24 May 30 02:07:19 PM PDT 24 47899978 ps
T923 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.1413416644 May 30 02:05:53 PM PDT 24 May 30 02:05:55 PM PDT 24 31471869 ps
T924 /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.1401904252 May 30 02:06:58 PM PDT 24 May 30 02:07:00 PM PDT 24 226573587 ps
T925 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.1603490734 May 30 02:06:54 PM PDT 24 May 30 02:07:12 PM PDT 24 699268799 ps
T926 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.3046038326 May 30 02:06:57 PM PDT 24 May 30 02:07:00 PM PDT 24 62461670 ps
T927 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.3063191922 May 30 02:06:51 PM PDT 24 May 30 02:06:54 PM PDT 24 98362607 ps
T928 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.3329591451 May 30 02:07:13 PM PDT 24 May 30 02:07:18 PM PDT 24 517068908 ps
T929 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.2319224689 May 30 02:07:06 PM PDT 24 May 30 02:07:09 PM PDT 24 127744129 ps
T930 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.3990812029 May 30 02:06:55 PM PDT 24 May 30 02:06:58 PM PDT 24 237340665 ps
T204 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.2672680075 May 30 02:06:56 PM PDT 24 May 30 02:06:59 PM PDT 24 28794845 ps
T931 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.2996792076 May 30 02:06:57 PM PDT 24 May 30 02:07:00 PM PDT 24 18186696 ps
T932 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.1099416672 May 30 02:07:11 PM PDT 24 May 30 02:07:14 PM PDT 24 62385387 ps
T933 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.1769533713 May 30 02:06:55 PM PDT 24 May 30 02:06:59 PM PDT 24 86566884 ps
T934 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.142529585 May 30 02:06:57 PM PDT 24 May 30 02:06:59 PM PDT 24 13882941 ps
T199 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.724090762 May 30 02:06:59 PM PDT 24 May 30 02:07:02 PM PDT 24 44051654 ps
T935 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.3540918193 May 30 02:06:59 PM PDT 24 May 30 02:07:13 PM PDT 24 951466405 ps
T936 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.3451904510 May 30 02:06:58 PM PDT 24 May 30 02:07:03 PM PDT 24 559758371 ps
T153 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.1964764657 May 30 02:05:58 PM PDT 24 May 30 02:06:01 PM PDT 24 56236832 ps
T937 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.2034527019 May 30 02:07:16 PM PDT 24 May 30 02:07:19 PM PDT 24 58954640 ps
T938 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.1690210433 May 30 02:05:54 PM PDT 24 May 30 02:05:57 PM PDT 24 81264663 ps
T939 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.2773160375 May 30 02:07:01 PM PDT 24 May 30 02:07:03 PM PDT 24 144286889 ps
T940 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.2306369994 May 30 02:06:56 PM PDT 24 May 30 02:07:12 PM PDT 24 2348155631 ps
T146 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.1051404851 May 30 02:07:14 PM PDT 24 May 30 02:07:17 PM PDT 24 45223792 ps
T941 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.3719765691 May 30 02:07:11 PM PDT 24 May 30 02:07:14 PM PDT 24 216401465 ps
T942 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.4247659034 May 30 02:07:02 PM PDT 24 May 30 02:07:05 PM PDT 24 91005208 ps
T943 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.1363429068 May 30 02:07:13 PM PDT 24 May 30 02:07:17 PM PDT 24 129298542 ps
T944 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.1690460626 May 30 02:05:54 PM PDT 24 May 30 02:05:56 PM PDT 24 14884590 ps
T945 /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.298255629 May 30 02:07:11 PM PDT 24 May 30 02:07:13 PM PDT 24 23996989 ps
T946 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.2136611635 May 30 02:06:55 PM PDT 24 May 30 02:06:58 PM PDT 24 1219341705 ps
T947 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.20919565 May 30 02:07:01 PM PDT 24 May 30 02:07:04 PM PDT 24 103613271 ps
T948 /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.911981701 May 30 02:07:16 PM PDT 24 May 30 02:07:19 PM PDT 24 28592029 ps
T949 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.1473081656 May 30 02:06:23 PM PDT 24 May 30 02:06:25 PM PDT 24 194580384 ps
T950 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.1619294311 May 30 02:06:59 PM PDT 24 May 30 02:07:03 PM PDT 24 129283602 ps
T951 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3456145542 May 30 02:06:58 PM PDT 24 May 30 02:07:01 PM PDT 24 113206859 ps
T952 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.1839080151 May 30 02:07:11 PM PDT 24 May 30 02:07:13 PM PDT 24 15584243 ps
T953 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.4131233177 May 30 02:07:00 PM PDT 24 May 30 02:07:10 PM PDT 24 11555814867 ps
T954 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.3460964776 May 30 02:05:52 PM PDT 24 May 30 02:05:56 PM PDT 24 168960381 ps
T955 /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.2127814178 May 30 02:06:24 PM PDT 24 May 30 02:06:26 PM PDT 24 39965075 ps
T956 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.1537198531 May 30 02:06:55 PM PDT 24 May 30 02:06:58 PM PDT 24 285844754 ps
T957 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.2742643024 May 30 02:05:54 PM PDT 24 May 30 02:06:01 PM PDT 24 261863296 ps
T958 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.3983034939 May 30 02:07:13 PM PDT 24 May 30 02:07:16 PM PDT 24 35937582 ps
T959 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.1074123498 May 30 02:05:54 PM PDT 24 May 30 02:06:08 PM PDT 24 3509163898 ps
T144 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.1927783259 May 30 02:06:58 PM PDT 24 May 30 02:07:03 PM PDT 24 419434704 ps
T960 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.2281346666 May 30 02:07:06 PM PDT 24 May 30 02:07:17 PM PDT 24 1653710849 ps
T135 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.1212310834 May 30 02:07:06 PM PDT 24 May 30 02:07:11 PM PDT 24 77885818 ps
T961 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.2694171194 May 30 02:05:54 PM PDT 24 May 30 02:05:56 PM PDT 24 27501124 ps
T962 /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.236602826 May 30 02:07:14 PM PDT 24 May 30 02:07:17 PM PDT 24 93887656 ps
T963 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.650969622 May 30 02:07:00 PM PDT 24 May 30 02:07:03 PM PDT 24 61618460 ps
T964 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3526679910 May 30 02:05:54 PM PDT 24 May 30 02:05:57 PM PDT 24 58118448 ps
T965 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.752700351 May 30 02:06:58 PM PDT 24 May 30 02:07:00 PM PDT 24 150019255 ps
T966 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.2770640397 May 30 02:06:55 PM PDT 24 May 30 02:06:57 PM PDT 24 59066227 ps
T967 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.925678242 May 30 02:06:56 PM PDT 24 May 30 02:06:59 PM PDT 24 26426911 ps
T968 /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.1129844019 May 30 02:07:04 PM PDT 24 May 30 02:07:06 PM PDT 24 498308537 ps
T969 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.509513249 May 30 02:06:57 PM PDT 24 May 30 02:07:00 PM PDT 24 177145273 ps
T970 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.1222624363 May 30 02:06:55 PM PDT 24 May 30 02:07:00 PM PDT 24 87219289 ps
T971 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.1192404006 May 30 02:07:00 PM PDT 24 May 30 02:07:03 PM PDT 24 21220153 ps
T972 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.3200660481 May 30 02:07:13 PM PDT 24 May 30 02:07:16 PM PDT 24 46994115 ps
T973 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.321407281 May 30 02:07:16 PM PDT 24 May 30 02:07:19 PM PDT 24 26400028 ps
T974 /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.2094672134 May 30 02:07:14 PM PDT 24 May 30 02:07:17 PM PDT 24 25634333 ps
T200 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.2698060495 May 30 02:06:56 PM PDT 24 May 30 02:06:59 PM PDT 24 37869165 ps
T975 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.3583703569 May 30 02:05:59 PM PDT 24 May 30 02:06:00 PM PDT 24 109562797 ps
T976 /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.1713859075 May 30 02:07:16 PM PDT 24 May 30 02:07:20 PM PDT 24 42353745 ps
T977 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.1861551416 May 30 02:05:54 PM PDT 24 May 30 02:05:59 PM PDT 24 357176570 ps
T978 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.557168946 May 30 02:06:50 PM PDT 24 May 30 02:06:52 PM PDT 24 78990216 ps
T201 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.28580423 May 30 02:06:55 PM PDT 24 May 30 02:06:58 PM PDT 24 349807423 ps
T979 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.367971067 May 30 02:06:56 PM PDT 24 May 30 02:07:25 PM PDT 24 1288625130 ps
T149 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.1370402081 May 30 02:06:59 PM PDT 24 May 30 02:07:04 PM PDT 24 117362802 ps
T980 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.4099682773 May 30 02:07:00 PM PDT 24 May 30 02:07:04 PM PDT 24 142823016 ps
T981 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.4225315541 May 30 02:05:51 PM PDT 24 May 30 02:05:53 PM PDT 24 96225815 ps
T202 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.2111798351 May 30 02:06:55 PM PDT 24 May 30 02:06:57 PM PDT 24 22441615 ps
T982 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.361869975 May 30 02:06:55 PM PDT 24 May 30 02:07:00 PM PDT 24 108992677 ps
T207 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.1466465770 May 30 02:07:10 PM PDT 24 May 30 02:07:12 PM PDT 24 76520852 ps
T983 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.2723527928 May 30 02:07:14 PM PDT 24 May 30 02:07:17 PM PDT 24 20300878 ps
T984 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.12887058 May 30 02:05:52 PM PDT 24 May 30 02:05:54 PM PDT 24 16538711 ps
T205 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.3512389327 May 30 02:06:58 PM PDT 24 May 30 02:07:01 PM PDT 24 16057363 ps
T203 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.479522970 May 30 02:06:58 PM PDT 24 May 30 02:07:00 PM PDT 24 14281087 ps
T985 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.2218694696 May 30 02:05:56 PM PDT 24 May 30 02:05:57 PM PDT 24 22452227 ps
T986 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.2988368749 May 30 02:05:54 PM PDT 24 May 30 02:05:57 PM PDT 24 861516415 ps
T987 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1038177028 May 30 02:06:41 PM PDT 24 May 30 02:06:46 PM PDT 24 399823019 ps
T988 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.118891969 May 30 02:07:10 PM PDT 24 May 30 02:07:13 PM PDT 24 90087287 ps
T989 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.2997730417 May 30 02:06:56 PM PDT 24 May 30 02:07:00 PM PDT 24 30292444 ps
T141 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.2350985554 May 30 02:07:16 PM PDT 24 May 30 02:07:21 PM PDT 24 151080499 ps
T990 /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.979889240 May 30 02:07:14 PM PDT 24 May 30 02:07:18 PM PDT 24 243029800 ps
T991 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.4058168344 May 30 02:07:04 PM PDT 24 May 30 02:07:07 PM PDT 24 114975203 ps
T992 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.3946518661 May 30 02:07:13 PM PDT 24 May 30 02:07:20 PM PDT 24 517872243 ps
T993 /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.3538181036 May 30 02:07:14 PM PDT 24 May 30 02:07:17 PM PDT 24 71023632 ps
T206 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.2388104831 May 30 02:07:14 PM PDT 24 May 30 02:07:17 PM PDT 24 15100145 ps
T994 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.1317001353 May 30 02:05:54 PM PDT 24 May 30 02:05:56 PM PDT 24 107743882 ps
T995 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.868517661 May 30 02:05:53 PM PDT 24 May 30 02:05:55 PM PDT 24 91638869 ps
T996 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.3752030983 May 30 02:06:55 PM PDT 24 May 30 02:07:00 PM PDT 24 2131944833 ps
T997 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.1118027657 May 30 02:07:04 PM PDT 24 May 30 02:07:11 PM PDT 24 8254675894 ps
T145 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.3497523964 May 30 02:06:55 PM PDT 24 May 30 02:06:59 PM PDT 24 278395621 ps
T998 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.2022726268 May 30 02:06:55 PM PDT 24 May 30 02:07:07 PM PDT 24 4489964632 ps
T148 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.2754344365 May 30 02:07:13 PM PDT 24 May 30 02:07:20 PM PDT 24 1666097450 ps

Test location /workspace/coverage/default/29.lc_ctrl_sec_mubi.2617377725
Short name T2
Test name
Test status
Simulation time 878651694 ps
CPU time 19.96 seconds
Started May 30 02:11:46 PM PDT 24
Finished May 30 02:12:07 PM PDT 24
Peak memory 218944 kb
Host smart-8e57acab-81c0-457d-8fc9-e699cacb04a0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617377725 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_mubi.2617377725
Directory /workspace/29.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_errors.3305271043
Short name T22
Test name
Test status
Simulation time 12995724893 ps
CPU time 40.29 seconds
Started May 30 02:10:14 PM PDT 24
Finished May 30 02:10:55 PM PDT 24
Peak memory 219388 kb
Host smart-667683ec-5775-43f9-a62b-6f4593ff2fe3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305271043 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_er
rors.3305271043
Directory /workspace/5.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/20.lc_ctrl_security_escalation.443766289
Short name T50
Test name
Test status
Simulation time 5088848873 ps
CPU time 11.58 seconds
Started May 30 02:11:10 PM PDT 24
Finished May 30 02:11:23 PM PDT 24
Peak memory 218256 kb
Host smart-29d86b43-45f4-4635-b9aa-83f13db05f29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443766289 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_security_escalation.443766289
Directory /workspace/20.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all.3295715380
Short name T43
Test name
Test status
Simulation time 20295301379 ps
CPU time 185.42 seconds
Started May 30 02:09:39 PM PDT 24
Finished May 30 02:12:46 PM PDT 24
Peak memory 283804 kb
Host smart-90693d33-4705-45af-9b39-8caad2a8611d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295715380 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.lc_ctrl_stress_all.3295715380
Directory /workspace/0.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_mux.3275824756
Short name T26
Test name
Test status
Simulation time 572179200 ps
CPU time 11.26 seconds
Started May 30 02:09:56 PM PDT 24
Finished May 30 02:10:08 PM PDT 24
Peak memory 218004 kb
Host smart-3de03278-e05b-477e-af25-9a03a634451d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275824756 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_mux.3
275824756
Directory /workspace/3.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all_with_rand_reset.834557240
Short name T100
Test name
Test status
Simulation time 17399646805 ps
CPU time 422.74 seconds
Started May 30 02:12:46 PM PDT 24
Finished May 30 02:19:51 PM PDT 24
Peak memory 348856 kb
Host smart-81088f08-3a95-41e7-be9e-687970366f29
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=834557240 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_stress_all_with_rand_reset.834557240
Directory /workspace/48.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_cm.2809046578
Short name T51
Test name
Test status
Simulation time 440778244 ps
CPU time 20.52 seconds
Started May 30 02:09:49 PM PDT 24
Finished May 30 02:10:10 PM PDT 24
Peak memory 281296 kb
Host smart-9b04a3f9-4929-4ca8-8f93-8f32068eb77c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809046578 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_cm.2809046578
Directory /workspace/2.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/43.lc_ctrl_volatile_unlock_smoke.2035187687
Short name T46
Test name
Test status
Simulation time 14780574 ps
CPU time 0.99 seconds
Started May 30 02:12:23 PM PDT 24
Finished May 30 02:12:26 PM PDT 24
Peak memory 208632 kb
Host smart-24b69f40-a0f4-4bc7-b80d-bbec2b4036b5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035187687 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_c
trl_volatile_unlock_smoke.2035187687
Directory /workspace/43.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.1450285486
Short name T124
Test name
Test status
Simulation time 87245447 ps
CPU time 2.75 seconds
Started May 30 02:07:16 PM PDT 24
Finished May 30 02:07:21 PM PDT 24
Peak memory 218136 kb
Host smart-057aeeaa-97a6-4295-a68b-174116cd5c36
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450285486 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_errors.1450285486
Directory /workspace/12.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_security_escalation.455688149
Short name T220
Test name
Test status
Simulation time 1496809814 ps
CPU time 15.05 seconds
Started May 30 02:09:51 PM PDT 24
Finished May 30 02:10:08 PM PDT 24
Peak memory 225660 kb
Host smart-d7d434f6-5f1c-4b75-a71c-34f9f51b126e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455688149 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_security_escalation.455688149
Directory /workspace/2.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/28.lc_ctrl_stress_all_with_rand_reset.4111205273
Short name T56
Test name
Test status
Simulation time 127123150152 ps
CPU time 2196.2 seconds
Started May 30 02:11:41 PM PDT 24
Finished May 30 02:48:19 PM PDT 24
Peak memory 308528 kb
Host smart-7eda2a7d-7356-49f3-878b-d369894a5812
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4111205273 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_stress_all_with_rand_reset.4111205273
Directory /workspace/28.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.3423733354
Short name T126
Test name
Test status
Simulation time 403169670 ps
CPU time 3.9 seconds
Started May 30 02:05:52 PM PDT 24
Finished May 30 02:05:56 PM PDT 24
Peak memory 218076 kb
Host smart-af27398d-5dd5-4109-a8db-f05c487e4b3b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423733354 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_intg_
err.3423733354
Directory /workspace/2.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/25.lc_ctrl_stress_all_with_rand_reset.86514606
Short name T112
Test name
Test status
Simulation time 6010688934 ps
CPU time 205.2 seconds
Started May 30 02:11:44 PM PDT 24
Finished May 30 02:15:11 PM PDT 24
Peak memory 305196 kb
Host smart-d25946e9-5492-4fef-b46f-ff0b5ace35fc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=86514606 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_stress_all_with_rand_reset.86514606
Directory /workspace/25.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.lc_ctrl_security_escalation.2757016378
Short name T177
Test name
Test status
Simulation time 397393753 ps
CPU time 11.04 seconds
Started May 30 02:12:35 PM PDT 24
Finished May 30 02:12:48 PM PDT 24
Peak memory 218136 kb
Host smart-b17fc90e-a5e9-4b00-889c-056d414e02f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757016378 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_security_escalation.2757016378
Directory /workspace/48.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_access.2140542759
Short name T31
Test name
Test status
Simulation time 1051244412 ps
CPU time 4.98 seconds
Started May 30 02:10:58 PM PDT 24
Finished May 30 02:11:04 PM PDT 24
Peak memory 209464 kb
Host smart-e369ceef-107a-4148-af95-81aa06a90fc2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140542759 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_access.2140542759
Directory /workspace/15.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/15.lc_ctrl_smoke.1656888483
Short name T14
Test name
Test status
Simulation time 47119578 ps
CPU time 3.42 seconds
Started May 30 02:10:54 PM PDT 24
Finished May 30 02:10:59 PM PDT 24
Peak memory 217772 kb
Host smart-a23417b0-b4a5-4120-961a-93fb0fd1de91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1656888483 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_smoke.1656888483
Directory /workspace/15.lc_ctrl_smoke/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.2529049871
Short name T154
Test name
Test status
Simulation time 328548491 ps
CPU time 6.06 seconds
Started May 30 02:05:43 PM PDT 24
Finished May 30 02:05:49 PM PDT 24
Peak memory 211444 kb
Host smart-32b5c9f9-11ac-4f7a-91f5-b953d5ee7004
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529049871 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_hw_reset.2529049871
Directory /workspace/0.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.2698060495
Short name T200
Test name
Test status
Simulation time 37869165 ps
CPU time 1.25 seconds
Started May 30 02:06:56 PM PDT 24
Finished May 30 02:06:59 PM PDT 24
Peak memory 212172 kb
Host smart-a96e8be3-2e7f-498e-9a64-175aa0afeab3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698060495 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_hw_rese
t.2698060495
Directory /workspace/3.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/default/29.lc_ctrl_stress_all_with_rand_reset.3063360075
Short name T101
Test name
Test status
Simulation time 59659077830 ps
CPU time 495.6 seconds
Started May 30 02:11:47 PM PDT 24
Finished May 30 02:20:04 PM PDT 24
Peak memory 329768 kb
Host smart-6c50ca90-f5fe-4810-b24b-4ff16a60cac8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3063360075 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_stress_all_with_rand_reset.3063360075
Directory /workspace/29.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.lc_ctrl_alert_test.2677575705
Short name T234
Test name
Test status
Simulation time 28591499 ps
CPU time 0.93 seconds
Started May 30 02:10:27 PM PDT 24
Finished May 30 02:10:29 PM PDT 24
Peak memory 208732 kb
Host smart-abac22d9-a556-441e-ac6a-34b6b6743009
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677575705 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_alert_test.2677575705
Directory /workspace/10.lc_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.2039667268
Short name T142
Test name
Test status
Simulation time 449917678 ps
CPU time 3.67 seconds
Started May 30 02:07:09 PM PDT 24
Finished May 30 02:07:13 PM PDT 24
Peak memory 222796 kb
Host smart-051ba43f-6f7b-4436-a3d9-1bd648f6f0e5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039667268 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_intg
_err.2039667268
Directory /workspace/11.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_failure.3653614237
Short name T20
Test name
Test status
Simulation time 3811112587 ps
CPU time 46.16 seconds
Started May 30 02:11:02 PM PDT 24
Finished May 30 02:11:49 PM PDT 24
Peak memory 250976 kb
Host smart-092b81d3-daae-4cda-85fa-bb31c084622e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653614237 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jt
ag_state_failure.3653614237
Directory /workspace/17.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.1927783259
Short name T144
Test name
Test status
Simulation time 419434704 ps
CPU time 4.49 seconds
Started May 30 02:06:58 PM PDT 24
Finished May 30 02:07:03 PM PDT 24
Peak memory 218180 kb
Host smart-b505288d-dcec-47fe-952f-07353139d1e6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927783259 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_intg_
err.1927783259
Directory /workspace/4.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.1370402081
Short name T149
Test name
Test status
Simulation time 117362802 ps
CPU time 3.09 seconds
Started May 30 02:06:59 PM PDT 24
Finished May 30 02:07:04 PM PDT 24
Peak memory 222132 kb
Host smart-9ad77d76-178f-4025-b842-7a057b9e3006
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370402081 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_intg_
err.1370402081
Directory /workspace/3.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/3.lc_ctrl_prog_failure.4161709524
Short name T17
Test name
Test status
Simulation time 256303729 ps
CPU time 3.58 seconds
Started May 30 02:10:00 PM PDT 24
Finished May 30 02:10:04 PM PDT 24
Peak memory 218024 kb
Host smart-7cccce23-cdab-49f3-b347-30a1fe3a57be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161709524 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_prog_failure.4161709524
Directory /workspace/3.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.2754344365
Short name T148
Test name
Test status
Simulation time 1666097450 ps
CPU time 5.49 seconds
Started May 30 02:07:13 PM PDT 24
Finished May 30 02:07:20 PM PDT 24
Peak memory 218152 kb
Host smart-0ee52a61-b038-4f79-b1a4-d76a6c6a465e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754344365 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_intg
_err.2754344365
Directory /workspace/18.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.4179984165
Short name T208
Test name
Test status
Simulation time 37221777 ps
CPU time 1.2 seconds
Started May 30 02:05:52 PM PDT 24
Finished May 30 02:05:54 PM PDT 24
Peak memory 209616 kb
Host smart-924d2632-15e2-4851-a53a-cfcfc6636d97
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179984165 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.lc_ctrl_jtag_same_csr_outstanding.4179984165
Directory /workspace/0.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.2350985554
Short name T141
Test name
Test status
Simulation time 151080499 ps
CPU time 2.93 seconds
Started May 30 02:07:16 PM PDT 24
Finished May 30 02:07:21 PM PDT 24
Peak memory 222632 kb
Host smart-9d9c2591-d845-45cc-b7f6-0219d4c236a9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350985554 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_intg
_err.2350985554
Directory /workspace/19.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/1.lc_ctrl_claim_transition_if.3736741458
Short name T216
Test name
Test status
Simulation time 13495613 ps
CPU time 0.82 seconds
Started May 30 02:09:42 PM PDT 24
Finished May 30 02:09:44 PM PDT 24
Peak memory 208604 kb
Host smart-47714a55-9f2d-4b41-a50b-c650aa3e101c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736741458 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_claim_transition_if.3736741458
Directory /workspace/1.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/2.lc_ctrl_claim_transition_if.470985509
Short name T218
Test name
Test status
Simulation time 19162225 ps
CPU time 0.81 seconds
Started May 30 02:09:58 PM PDT 24
Finished May 30 02:10:00 PM PDT 24
Peak memory 208724 kb
Host smart-57783ffa-ef23-4bc3-90d0-495c030eeec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470985509 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_claim_transition_if.470985509
Directory /workspace/2.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/4.lc_ctrl_claim_transition_if.335760004
Short name T219
Test name
Test status
Simulation time 12677264 ps
CPU time 0.98 seconds
Started May 30 02:09:54 PM PDT 24
Finished May 30 02:09:56 PM PDT 24
Peak memory 208724 kb
Host smart-82650d6e-225b-453c-b40e-69abcca8a978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335760004 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_claim_transition_if.335760004
Directory /workspace/4.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.1816562522
Short name T894
Test name
Test status
Simulation time 41600867 ps
CPU time 2.49 seconds
Started May 30 02:05:51 PM PDT 24
Finished May 30 02:05:54 PM PDT 24
Peak memory 218340 kb
Host smart-88b5f822-9095-4e65-adcf-0729a632446a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816562522 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_errors.1816562522
Directory /workspace/0.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.1964764657
Short name T153
Test name
Test status
Simulation time 56236832 ps
CPU time 2.05 seconds
Started May 30 02:05:58 PM PDT 24
Finished May 30 02:06:01 PM PDT 24
Peak memory 221904 kb
Host smart-e01b6b65-3875-4632-b0a7-f6b8a980e7b2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964764657 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_intg_
err.1964764657
Directory /workspace/1.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.3867193938
Short name T138
Test name
Test status
Simulation time 102107254 ps
CPU time 2.85 seconds
Started May 30 02:07:12 PM PDT 24
Finished May 30 02:07:16 PM PDT 24
Peak memory 222916 kb
Host smart-8b6b664f-5c3b-4beb-a316-94c396b0e019
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867193938 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_intg
_err.3867193938
Directory /workspace/12.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.2167795175
Short name T133
Test name
Test status
Simulation time 194812515 ps
CPU time 2.01 seconds
Started May 30 02:07:11 PM PDT 24
Finished May 30 02:07:14 PM PDT 24
Peak memory 222532 kb
Host smart-c259fc7f-c965-4a2f-9a8b-94c86046d193
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167795175 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_intg
_err.2167795175
Directory /workspace/13.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/12.lc_ctrl_stress_all.885324803
Short name T60
Test name
Test status
Simulation time 13325436585 ps
CPU time 254.64 seconds
Started May 30 02:10:35 PM PDT 24
Finished May 30 02:14:51 PM PDT 24
Peak memory 220976 kb
Host smart-348564ee-3dce-4367-b6cc-b4b5a577904d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885324803 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.lc_ctrl_stress_all.885324803
Directory /workspace/12.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.lc_ctrl_errors.4210579521
Short name T61
Test name
Test status
Simulation time 514216525 ps
CPU time 17.81 seconds
Started May 30 02:12:23 PM PDT 24
Finished May 30 02:12:42 PM PDT 24
Peak memory 218076 kb
Host smart-3ebfe754-2d61-4d26-8585-53d4d194b928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4210579521 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_errors.4210579521
Directory /workspace/43.lc_ctrl_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_prog_failure.2210003744
Short name T28
Test name
Test status
Simulation time 106714696 ps
CPU time 2.07 seconds
Started May 30 02:09:53 PM PDT 24
Finished May 30 02:09:56 PM PDT 24
Peak memory 218144 kb
Host smart-5e2656c2-daa4-4cec-b844-ee534ab22292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210003744 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_prog_failure.2210003744
Directory /workspace/2.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_mux.2151952542
Short name T16
Test name
Test status
Simulation time 376381451 ps
CPU time 8.03 seconds
Started May 30 02:09:38 PM PDT 24
Finished May 30 02:09:48 PM PDT 24
Peak memory 217424 kb
Host smart-60bb7ab6-2785-4fc1-b5b6-ea6b45a9ff72
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151952542 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_mux.2
151952542
Directory /workspace/0.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.4225315541
Short name T981
Test name
Test status
Simulation time 96225815 ps
CPU time 1.19 seconds
Started May 30 02:05:51 PM PDT 24
Finished May 30 02:05:53 PM PDT 24
Peak memory 209860 kb
Host smart-7de1d767-79b8-4162-b4eb-a0a876486b28
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225315541 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_aliasin
g.4225315541
Directory /workspace/0.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.3510988077
Short name T879
Test name
Test status
Simulation time 95138042 ps
CPU time 1.1 seconds
Started May 30 02:05:52 PM PDT 24
Finished May 30 02:05:53 PM PDT 24
Peak memory 209800 kb
Host smart-3b16af3c-ea4a-4ead-8a6c-119ea4d9bbc8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510988077 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_bit_bas
h.3510988077
Directory /workspace/0.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.2561551670
Short name T136
Test name
Test status
Simulation time 71434970 ps
CPU time 1.06 seconds
Started May 30 02:05:53 PM PDT 24
Finished May 30 02:05:55 PM PDT 24
Peak memory 219464 kb
Host smart-f7be5786-fd25-4c84-bfc1-7036b7351801
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561551670 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_hw_rese
t.2561551670
Directory /workspace/0.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.3988186197
Short name T913
Test name
Test status
Simulation time 57640371 ps
CPU time 1.17 seconds
Started May 30 02:05:51 PM PDT 24
Finished May 30 02:05:53 PM PDT 24
Peak memory 218240 kb
Host smart-861bd5b2-17d9-421c-9fee-4df66411cd28
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988186197 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 0.lc_ctrl_csr_mem_rw_with_rand_reset.3988186197
Directory /workspace/0.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.2218694696
Short name T985
Test name
Test status
Simulation time 22452227 ps
CPU time 0.9 seconds
Started May 30 02:05:56 PM PDT 24
Finished May 30 02:05:57 PM PDT 24
Peak memory 209888 kb
Host smart-7bb28f04-d7b8-45cb-a798-d719df87da7a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218694696 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_rw.2218694696
Directory /workspace/0.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.3583703569
Short name T975
Test name
Test status
Simulation time 109562797 ps
CPU time 0.98 seconds
Started May 30 02:05:59 PM PDT 24
Finished May 30 02:06:00 PM PDT 24
Peak memory 209628 kb
Host smart-30b305ba-6d9c-4f8d-9eb7-e99c773262d8
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583703569 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.lc_ctrl_jtag_alert_test.3583703569
Directory /workspace/0.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.2742643024
Short name T957
Test name
Test status
Simulation time 261863296 ps
CPU time 6.46 seconds
Started May 30 02:05:54 PM PDT 24
Finished May 30 02:06:01 PM PDT 24
Peak memory 209476 kb
Host smart-9049867a-9754-46c7-98b9-747c76d08c20
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742643024 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_aliasing.2742643024
Directory /workspace/0.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.1861551416
Short name T977
Test name
Test status
Simulation time 357176570 ps
CPU time 4.44 seconds
Started May 30 02:05:54 PM PDT 24
Finished May 30 02:05:59 PM PDT 24
Peak memory 209520 kb
Host smart-806d691a-51ca-4fd9-9261-77e075832a3e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861551416 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_bit_bash.1861551416
Directory /workspace/0.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3864171847
Short name T892
Test name
Test status
Simulation time 373186537 ps
CPU time 2.4 seconds
Started May 30 02:05:53 PM PDT 24
Finished May 30 02:05:56 PM PDT 24
Peak memory 219720 kb
Host smart-bc2ec637-f69f-4ff4-b346-fb18c27d3523
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386417
1847 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3864171847
Directory /workspace/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.2086727372
Short name T921
Test name
Test status
Simulation time 242389939 ps
CPU time 2.07 seconds
Started May 30 02:05:41 PM PDT 24
Finished May 30 02:05:44 PM PDT 24
Peak memory 209784 kb
Host smart-b6538b1d-a2e4-4695-94a9-8bd3fdb5882d
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086727372 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.lc_ctrl_jtag_csr_rw.2086727372
Directory /workspace/0.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.4246669288
Short name T132
Test name
Test status
Simulation time 23027121 ps
CPU time 1.05 seconds
Started May 30 02:05:52 PM PDT 24
Finished May 30 02:05:54 PM PDT 24
Peak memory 217708 kb
Host smart-a2fff965-368f-42d9-be22-82eed100f87d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246669288 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl
_same_csr_outstanding.4246669288
Directory /workspace/0.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.1871317801
Short name T151
Test name
Test status
Simulation time 207583315 ps
CPU time 3.94 seconds
Started May 30 02:05:52 PM PDT 24
Finished May 30 02:05:57 PM PDT 24
Peak memory 218112 kb
Host smart-dbc5dcbf-c57f-4161-9097-71d62b5c8a7e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871317801 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_intg_
err.1871317801
Directory /workspace/0.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.3114153656
Short name T887
Test name
Test status
Simulation time 34107074 ps
CPU time 1.35 seconds
Started May 30 02:05:55 PM PDT 24
Finished May 30 02:05:57 PM PDT 24
Peak memory 209856 kb
Host smart-f4f99db6-f293-46a8-b9b3-437718ba2d81
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114153656 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_aliasin
g.3114153656
Directory /workspace/1.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.3582132156
Short name T215
Test name
Test status
Simulation time 20454737 ps
CPU time 1.2 seconds
Started May 30 02:05:54 PM PDT 24
Finished May 30 02:05:56 PM PDT 24
Peak memory 209716 kb
Host smart-3c3dd4e4-a404-41c8-baad-9829790952da
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582132156 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_bit_bas
h.3582132156
Directory /workspace/1.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.12887058
Short name T984
Test name
Test status
Simulation time 16538711 ps
CPU time 1.15 seconds
Started May 30 02:05:52 PM PDT 24
Finished May 30 02:05:54 PM PDT 24
Peak memory 219764 kb
Host smart-7b79a32e-9bfb-40fb-ac9b-9318dc89574a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12887058 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_hw_reset.12887058
Directory /workspace/1.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.1413416644
Short name T923
Test name
Test status
Simulation time 31471869 ps
CPU time 1.19 seconds
Started May 30 02:05:53 PM PDT 24
Finished May 30 02:05:55 PM PDT 24
Peak memory 218240 kb
Host smart-4d74ff37-cf18-45e4-8b43-d8d57052982b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413416644 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 1.lc_ctrl_csr_mem_rw_with_rand_reset.1413416644
Directory /workspace/1.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.1690460626
Short name T944
Test name
Test status
Simulation time 14884590 ps
CPU time 1.05 seconds
Started May 30 02:05:54 PM PDT 24
Finished May 30 02:05:56 PM PDT 24
Peak memory 209348 kb
Host smart-c43174c9-bed5-4b8a-a51c-61c9001c5ae1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690460626 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_rw.1690460626
Directory /workspace/1.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.868517661
Short name T995
Test name
Test status
Simulation time 91638869 ps
CPU time 0.97 seconds
Started May 30 02:05:53 PM PDT 24
Finished May 30 02:05:55 PM PDT 24
Peak memory 209680 kb
Host smart-1799d7da-2c96-4b4f-a564-774b70e0d86f
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868517661 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 1.lc_ctrl_jtag_alert_test.868517661
Directory /workspace/1.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.2695852599
Short name T881
Test name
Test status
Simulation time 7000710275 ps
CPU time 7.72 seconds
Started May 30 02:05:52 PM PDT 24
Finished May 30 02:06:00 PM PDT 24
Peak memory 217148 kb
Host smart-f6824a1b-842d-416d-b639-13933d75968d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695852599 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_aliasing.2695852599
Directory /workspace/1.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.1074123498
Short name T959
Test name
Test status
Simulation time 3509163898 ps
CPU time 13.61 seconds
Started May 30 02:05:54 PM PDT 24
Finished May 30 02:06:08 PM PDT 24
Peak memory 209936 kb
Host smart-5730b0ce-53d8-46ed-b216-be88f5988ff1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074123498 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_bit_bash.1074123498
Directory /workspace/1.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.3880242251
Short name T919
Test name
Test status
Simulation time 137171903 ps
CPU time 2.03 seconds
Started May 30 02:05:52 PM PDT 24
Finished May 30 02:05:55 PM PDT 24
Peak memory 211328 kb
Host smart-ed0d29ea-c887-4be8-a027-229cf592c86f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880242251 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_hw_reset.3880242251
Directory /workspace/1.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3526679910
Short name T964
Test name
Test status
Simulation time 58118448 ps
CPU time 2.31 seconds
Started May 30 02:05:54 PM PDT 24
Finished May 30 02:05:57 PM PDT 24
Peak memory 218676 kb
Host smart-2e0e636e-233e-41a7-9fc9-00b80333f62a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352667
9910 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3526679910
Directory /workspace/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.1745684133
Short name T882
Test name
Test status
Simulation time 66590097 ps
CPU time 2.25 seconds
Started May 30 02:05:54 PM PDT 24
Finished May 30 02:05:57 PM PDT 24
Peak memory 217228 kb
Host smart-636be6c3-d036-4be6-b401-aeef9a202ad5
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745684133 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.lc_ctrl_jtag_csr_rw.1745684133
Directory /workspace/1.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.2771550657
Short name T173
Test name
Test status
Simulation time 47242116 ps
CPU time 2.03 seconds
Started May 30 02:05:52 PM PDT 24
Finished May 30 02:05:54 PM PDT 24
Peak memory 209900 kb
Host smart-c0f01b64-2566-4698-b7c6-bf380e15d598
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771550657 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.lc_ctrl_jtag_same_csr_outstanding.2771550657
Directory /workspace/1.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.3611994050
Short name T209
Test name
Test status
Simulation time 26328081 ps
CPU time 1.1 seconds
Started May 30 02:05:55 PM PDT 24
Finished May 30 02:05:57 PM PDT 24
Peak memory 209896 kb
Host smart-266ffd2d-a89c-44b1-bc9c-c9cb5f4524c1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611994050 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl
_same_csr_outstanding.3611994050
Directory /workspace/1.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.1690210433
Short name T938
Test name
Test status
Simulation time 81264663 ps
CPU time 1.83 seconds
Started May 30 02:05:54 PM PDT 24
Finished May 30 02:05:57 PM PDT 24
Peak memory 218232 kb
Host smart-bf28321e-524d-48d1-b970-309cb8aab1ef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690210433 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_errors.1690210433
Directory /workspace/1.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.2723527928
Short name T983
Test name
Test status
Simulation time 20300878 ps
CPU time 1.55 seconds
Started May 30 02:07:14 PM PDT 24
Finished May 30 02:07:17 PM PDT 24
Peak memory 218332 kb
Host smart-abdd969c-381e-416a-a8d8-bf7e45fb1cb3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723527928 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 10.lc_ctrl_csr_mem_rw_with_rand_reset.2723527928
Directory /workspace/10.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.3870702099
Short name T875
Test name
Test status
Simulation time 82698237 ps
CPU time 0.83 seconds
Started May 30 02:07:16 PM PDT 24
Finished May 30 02:07:18 PM PDT 24
Peak memory 209692 kb
Host smart-7c8bd969-7f55-47e8-ace8-5e80b8d868f4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870702099 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_csr_rw.3870702099
Directory /workspace/10.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.361614891
Short name T210
Test name
Test status
Simulation time 81646619 ps
CPU time 1.21 seconds
Started May 30 02:07:16 PM PDT 24
Finished May 30 02:07:19 PM PDT 24
Peak memory 211872 kb
Host smart-50f649fb-5591-4d7e-94bc-ed5437dd8028
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361614891 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl
_same_csr_outstanding.361614891
Directory /workspace/10.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.269831248
Short name T139
Test name
Test status
Simulation time 131207372 ps
CPU time 3.86 seconds
Started May 30 02:07:10 PM PDT 24
Finished May 30 02:07:15 PM PDT 24
Peak memory 218172 kb
Host smart-7dd2cda9-04b7-4118-b534-179ea6aae414
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269831248 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_errors.269831248
Directory /workspace/10.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.1099416672
Short name T932
Test name
Test status
Simulation time 62385387 ps
CPU time 2.03 seconds
Started May 30 02:07:11 PM PDT 24
Finished May 30 02:07:14 PM PDT 24
Peak memory 221868 kb
Host smart-be588b46-a449-44c7-b2b4-cf179ab91c05
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099416672 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_intg
_err.1099416672
Directory /workspace/10.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.118891969
Short name T988
Test name
Test status
Simulation time 90087287 ps
CPU time 2.05 seconds
Started May 30 02:07:10 PM PDT 24
Finished May 30 02:07:13 PM PDT 24
Peak memory 219816 kb
Host smart-a03e165c-354e-4f84-a8a2-8099c102ff31
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118891969 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 11.lc_ctrl_csr_mem_rw_with_rand_reset.118891969
Directory /workspace/11.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.1466465770
Short name T207
Test name
Test status
Simulation time 76520852 ps
CPU time 0.98 seconds
Started May 30 02:07:10 PM PDT 24
Finished May 30 02:07:12 PM PDT 24
Peak memory 209852 kb
Host smart-290c482e-fc2e-4fb7-882d-759d92906414
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466465770 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_csr_rw.1466465770
Directory /workspace/11.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.911981701
Short name T948
Test name
Test status
Simulation time 28592029 ps
CPU time 1.12 seconds
Started May 30 02:07:16 PM PDT 24
Finished May 30 02:07:19 PM PDT 24
Peak memory 217772 kb
Host smart-6c436958-46b5-4ee8-b98c-d3e71f8ad0e7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911981701 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl
_same_csr_outstanding.911981701
Directory /workspace/11.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.195322148
Short name T130
Test name
Test status
Simulation time 244249974 ps
CPU time 2.93 seconds
Started May 30 02:07:10 PM PDT 24
Finished May 30 02:07:14 PM PDT 24
Peak memory 217680 kb
Host smart-3f303efb-0d2f-4e10-987a-e94fb454df02
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195322148 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_errors.195322148
Directory /workspace/11.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.2819824650
Short name T901
Test name
Test status
Simulation time 67649729 ps
CPU time 1.24 seconds
Started May 30 02:07:12 PM PDT 24
Finished May 30 02:07:14 PM PDT 24
Peak memory 219180 kb
Host smart-5e0d40a0-65f0-4950-8ff3-c06c573846a2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819824650 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 12.lc_ctrl_csr_mem_rw_with_rand_reset.2819824650
Directory /workspace/12.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.1447727734
Short name T907
Test name
Test status
Simulation time 37024638 ps
CPU time 0.94 seconds
Started May 30 02:07:13 PM PDT 24
Finished May 30 02:07:16 PM PDT 24
Peak memory 209852 kb
Host smart-296563b3-4da7-4c58-a55e-acbdca22135f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447727734 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_csr_rw.1447727734
Directory /workspace/12.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.298255629
Short name T945
Test name
Test status
Simulation time 23996989 ps
CPU time 1.2 seconds
Started May 30 02:07:11 PM PDT 24
Finished May 30 02:07:13 PM PDT 24
Peak memory 209876 kb
Host smart-bb47f0ff-7091-4805-8b05-2ef403adc22f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298255629 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl
_same_csr_outstanding.298255629
Directory /workspace/12.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.3983034939
Short name T958
Test name
Test status
Simulation time 35937582 ps
CPU time 1.03 seconds
Started May 30 02:07:13 PM PDT 24
Finished May 30 02:07:16 PM PDT 24
Peak memory 218172 kb
Host smart-64d9edaf-8c05-4d36-940f-e68312eaccd1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983034939 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 13.lc_ctrl_csr_mem_rw_with_rand_reset.3983034939
Directory /workspace/13.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.1839080151
Short name T952
Test name
Test status
Simulation time 15584243 ps
CPU time 1.03 seconds
Started May 30 02:07:11 PM PDT 24
Finished May 30 02:07:13 PM PDT 24
Peak memory 209808 kb
Host smart-9b39838b-346e-4045-aa66-133852887602
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839080151 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_csr_rw.1839080151
Directory /workspace/13.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.1713859075
Short name T976
Test name
Test status
Simulation time 42353745 ps
CPU time 1.44 seconds
Started May 30 02:07:16 PM PDT 24
Finished May 30 02:07:20 PM PDT 24
Peak memory 211992 kb
Host smart-0e5b98af-bd0d-45d9-b7af-d7472e141fac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713859075 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctr
l_same_csr_outstanding.1713859075
Directory /workspace/13.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.3719765691
Short name T941
Test name
Test status
Simulation time 216401465 ps
CPU time 2.55 seconds
Started May 30 02:07:11 PM PDT 24
Finished May 30 02:07:14 PM PDT 24
Peak memory 218136 kb
Host smart-747637ee-d138-41cf-988b-f6ba1f67ce35
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719765691 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_errors.3719765691
Directory /workspace/13.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.896335920
Short name T918
Test name
Test status
Simulation time 31688368 ps
CPU time 1.03 seconds
Started May 30 02:07:14 PM PDT 24
Finished May 30 02:07:17 PM PDT 24
Peak memory 218180 kb
Host smart-5c2c11b4-2b3c-44ca-9f98-693d31fbcc85
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896335920 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 14.lc_ctrl_csr_mem_rw_with_rand_reset.896335920
Directory /workspace/14.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.2388104831
Short name T206
Test name
Test status
Simulation time 15100145 ps
CPU time 1.07 seconds
Started May 30 02:07:14 PM PDT 24
Finished May 30 02:07:17 PM PDT 24
Peak memory 209788 kb
Host smart-24121405-fdef-4a53-930e-54629052d50c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388104831 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_csr_rw.2388104831
Directory /workspace/14.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.979889240
Short name T990
Test name
Test status
Simulation time 243029800 ps
CPU time 1.66 seconds
Started May 30 02:07:14 PM PDT 24
Finished May 30 02:07:18 PM PDT 24
Peak memory 212096 kb
Host smart-96829c2f-7e88-4d43-8a13-e1bf15f424ec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979889240 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl
_same_csr_outstanding.979889240
Directory /workspace/14.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.1363429068
Short name T943
Test name
Test status
Simulation time 129298542 ps
CPU time 2.25 seconds
Started May 30 02:07:13 PM PDT 24
Finished May 30 02:07:17 PM PDT 24
Peak memory 218200 kb
Host smart-2a8861c9-840a-4f29-a408-b9902dd0fc84
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363429068 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_errors.1363429068
Directory /workspace/14.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.1051404851
Short name T146
Test name
Test status
Simulation time 45223792 ps
CPU time 1.65 seconds
Started May 30 02:07:14 PM PDT 24
Finished May 30 02:07:17 PM PDT 24
Peak memory 222228 kb
Host smart-165bd02d-286f-4bf0-8c5c-b8ee5c96cadc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051404851 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_intg
_err.1051404851
Directory /workspace/14.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.321407281
Short name T973
Test name
Test status
Simulation time 26400028 ps
CPU time 1.04 seconds
Started May 30 02:07:16 PM PDT 24
Finished May 30 02:07:19 PM PDT 24
Peak memory 218188 kb
Host smart-dd78b1ed-6a89-4104-ad5b-b04ef64b9066
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321407281 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 15.lc_ctrl_csr_mem_rw_with_rand_reset.321407281
Directory /workspace/15.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.622065952
Short name T175
Test name
Test status
Simulation time 48779620 ps
CPU time 0.99 seconds
Started May 30 02:07:12 PM PDT 24
Finished May 30 02:07:14 PM PDT 24
Peak memory 209836 kb
Host smart-9ee6ff58-646b-4159-b6cc-67f9a28b34d2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622065952 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_csr_rw.622065952
Directory /workspace/15.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.3264633527
Short name T212
Test name
Test status
Simulation time 57432656 ps
CPU time 1.2 seconds
Started May 30 02:07:14 PM PDT 24
Finished May 30 02:07:17 PM PDT 24
Peak memory 209736 kb
Host smart-507303e6-d094-4bd4-a260-b366731ee18f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264633527 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctr
l_same_csr_outstanding.3264633527
Directory /workspace/15.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.3993123056
Short name T140
Test name
Test status
Simulation time 388582998 ps
CPU time 3.64 seconds
Started May 30 02:07:12 PM PDT 24
Finished May 30 02:07:17 PM PDT 24
Peak memory 218116 kb
Host smart-08733d84-1222-4cbc-8655-072df3d6a04d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993123056 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_errors.3993123056
Directory /workspace/15.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.2243747514
Short name T129
Test name
Test status
Simulation time 659109321 ps
CPU time 2.53 seconds
Started May 30 02:07:11 PM PDT 24
Finished May 30 02:07:14 PM PDT 24
Peak memory 218188 kb
Host smart-42161b0f-659c-4a63-91a0-21bed73498e5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243747514 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_intg
_err.2243747514
Directory /workspace/15.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.426944086
Short name T897
Test name
Test status
Simulation time 29098178 ps
CPU time 1.29 seconds
Started May 30 02:07:16 PM PDT 24
Finished May 30 02:07:20 PM PDT 24
Peak memory 221332 kb
Host smart-6b9493ae-aa6f-4ef9-8a94-820bad1f13f5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426944086 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 16.lc_ctrl_csr_mem_rw_with_rand_reset.426944086
Directory /workspace/16.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.3398860984
Short name T895
Test name
Test status
Simulation time 21164141 ps
CPU time 1.01 seconds
Started May 30 02:07:14 PM PDT 24
Finished May 30 02:07:17 PM PDT 24
Peak memory 209852 kb
Host smart-eebbc262-cc17-4549-9b6a-e09b9f02bd45
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398860984 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_csr_rw.3398860984
Directory /workspace/16.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.3538181036
Short name T993
Test name
Test status
Simulation time 71023632 ps
CPU time 1.3 seconds
Started May 30 02:07:14 PM PDT 24
Finished May 30 02:07:17 PM PDT 24
Peak memory 209916 kb
Host smart-66dfce2d-4934-4c41-a029-901378f27d53
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538181036 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctr
l_same_csr_outstanding.3538181036
Directory /workspace/16.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.495914746
Short name T147
Test name
Test status
Simulation time 93030780 ps
CPU time 3.81 seconds
Started May 30 02:07:14 PM PDT 24
Finished May 30 02:07:19 PM PDT 24
Peak memory 218108 kb
Host smart-9a56bae6-a602-40c7-8c9e-8ddece328f9d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495914746 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_errors.495914746
Directory /workspace/16.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.767443026
Short name T125
Test name
Test status
Simulation time 70010530 ps
CPU time 2.73 seconds
Started May 30 02:07:14 PM PDT 24
Finished May 30 02:07:18 PM PDT 24
Peak memory 218112 kb
Host smart-94976d09-05af-4618-9480-6c8e51eb2cc7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767443026 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_intg_
err.767443026
Directory /workspace/16.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.2209194621
Short name T128
Test name
Test status
Simulation time 14325511 ps
CPU time 1.29 seconds
Started May 30 02:07:13 PM PDT 24
Finished May 30 02:07:16 PM PDT 24
Peak memory 218216 kb
Host smart-3e088e31-a866-4aec-a36f-df86e66d7c3a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209194621 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 17.lc_ctrl_csr_mem_rw_with_rand_reset.2209194621
Directory /workspace/17.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.2634520236
Short name T915
Test name
Test status
Simulation time 14029390 ps
CPU time 0.86 seconds
Started May 30 02:07:16 PM PDT 24
Finished May 30 02:07:19 PM PDT 24
Peak memory 209624 kb
Host smart-a04b0e20-07c2-4895-8549-193fb07deb10
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634520236 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_csr_rw.2634520236
Directory /workspace/17.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.2094672134
Short name T974
Test name
Test status
Simulation time 25634333 ps
CPU time 1.31 seconds
Started May 30 02:07:14 PM PDT 24
Finished May 30 02:07:17 PM PDT 24
Peak memory 211764 kb
Host smart-4898bd3f-0e02-4c84-bd5b-7ddd7c9b7c5b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094672134 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctr
l_same_csr_outstanding.2094672134
Directory /workspace/17.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.3200660481
Short name T972
Test name
Test status
Simulation time 46994115 ps
CPU time 1.94 seconds
Started May 30 02:07:13 PM PDT 24
Finished May 30 02:07:16 PM PDT 24
Peak memory 219364 kb
Host smart-ad748d4a-331b-4b39-a5a4-836654a22fae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200660481 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_errors.3200660481
Directory /workspace/17.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.2394055414
Short name T134
Test name
Test status
Simulation time 123632888 ps
CPU time 2.9 seconds
Started May 30 02:07:13 PM PDT 24
Finished May 30 02:07:17 PM PDT 24
Peak memory 222620 kb
Host smart-f3a4714c-b765-4670-9c70-74147e459b8f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394055414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_intg
_err.2394055414
Directory /workspace/17.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.547653377
Short name T910
Test name
Test status
Simulation time 43172675 ps
CPU time 1.38 seconds
Started May 30 02:07:13 PM PDT 24
Finished May 30 02:07:15 PM PDT 24
Peak memory 219952 kb
Host smart-f3e567fd-ca3e-4296-a1fa-d0d4b3e93db1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547653377 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 18.lc_ctrl_csr_mem_rw_with_rand_reset.547653377
Directory /workspace/18.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.1833724973
Short name T137
Test name
Test status
Simulation time 16328792 ps
CPU time 0.95 seconds
Started May 30 02:07:14 PM PDT 24
Finished May 30 02:07:17 PM PDT 24
Peak memory 209472 kb
Host smart-f99822b5-1e2b-4374-bae9-f09ac367649f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833724973 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_csr_rw.1833724973
Directory /workspace/18.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.236602826
Short name T962
Test name
Test status
Simulation time 93887656 ps
CPU time 1.46 seconds
Started May 30 02:07:14 PM PDT 24
Finished May 30 02:07:17 PM PDT 24
Peak memory 218052 kb
Host smart-a682ace3-adc9-4133-b07e-62897b4e2e3b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236602826 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl
_same_csr_outstanding.236602826
Directory /workspace/18.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.3329591451
Short name T928
Test name
Test status
Simulation time 517068908 ps
CPU time 3.61 seconds
Started May 30 02:07:13 PM PDT 24
Finished May 30 02:07:18 PM PDT 24
Peak memory 218224 kb
Host smart-125be00f-804f-401f-9e27-132a3d703f8b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329591451 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_errors.3329591451
Directory /workspace/18.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.2034527019
Short name T937
Test name
Test status
Simulation time 58954640 ps
CPU time 1.63 seconds
Started May 30 02:07:16 PM PDT 24
Finished May 30 02:07:19 PM PDT 24
Peak memory 218104 kb
Host smart-ec0cd336-5201-422d-bdba-a3653404972d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034527019 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 19.lc_ctrl_csr_mem_rw_with_rand_reset.2034527019
Directory /workspace/19.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.1007097465
Short name T198
Test name
Test status
Simulation time 47899978 ps
CPU time 1 seconds
Started May 30 02:07:16 PM PDT 24
Finished May 30 02:07:19 PM PDT 24
Peak memory 209812 kb
Host smart-02147e72-75ed-4def-9ee8-991fd4f280de
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007097465 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_csr_rw.1007097465
Directory /workspace/19.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.3201589404
Short name T909
Test name
Test status
Simulation time 21300846 ps
CPU time 1.36 seconds
Started May 30 02:07:14 PM PDT 24
Finished May 30 02:07:17 PM PDT 24
Peak memory 211972 kb
Host smart-dd121d9e-fdd8-4765-b5b6-01f58e619ec7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201589404 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctr
l_same_csr_outstanding.3201589404
Directory /workspace/19.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.3946518661
Short name T992
Test name
Test status
Simulation time 517872243 ps
CPU time 5.07 seconds
Started May 30 02:07:13 PM PDT 24
Finished May 30 02:07:20 PM PDT 24
Peak memory 218104 kb
Host smart-b8c3e9ed-1276-443e-bd91-f7c6c6e1ea64
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946518661 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_errors.3946518661
Directory /workspace/19.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.2122851280
Short name T196
Test name
Test status
Simulation time 65236043 ps
CPU time 1.64 seconds
Started May 30 02:06:25 PM PDT 24
Finished May 30 02:06:27 PM PDT 24
Peak memory 209904 kb
Host smart-b386ca8b-18ea-462f-9d0a-a68f5d248937
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122851280 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_aliasin
g.2122851280
Directory /workspace/2.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.3484270445
Short name T890
Test name
Test status
Simulation time 113888565 ps
CPU time 1.54 seconds
Started May 30 02:06:22 PM PDT 24
Finished May 30 02:06:24 PM PDT 24
Peak memory 209852 kb
Host smart-8766c246-bb7d-415a-a2ae-2b6a34adfe11
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484270445 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_bit_bas
h.3484270445
Directory /workspace/2.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.906114913
Short name T194
Test name
Test status
Simulation time 14761607 ps
CPU time 0.99 seconds
Started May 30 02:05:54 PM PDT 24
Finished May 30 02:05:55 PM PDT 24
Peak memory 210992 kb
Host smart-24026537-fab8-4595-9490-2de289a6a94b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906114913 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_hw_reset
.906114913
Directory /workspace/2.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.1473081656
Short name T949
Test name
Test status
Simulation time 194580384 ps
CPU time 1.72 seconds
Started May 30 02:06:23 PM PDT 24
Finished May 30 02:06:25 PM PDT 24
Peak memory 219704 kb
Host smart-728a295d-1512-4348-a2d9-4fde06b19d1e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473081656 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 2.lc_ctrl_csr_mem_rw_with_rand_reset.1473081656
Directory /workspace/2.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.3639295802
Short name T197
Test name
Test status
Simulation time 23137709 ps
CPU time 0.95 seconds
Started May 30 02:06:22 PM PDT 24
Finished May 30 02:06:23 PM PDT 24
Peak memory 209848 kb
Host smart-8256b167-75e0-48cd-bc21-fdbd30b82082
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639295802 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_rw.3639295802
Directory /workspace/2.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.2694171194
Short name T961
Test name
Test status
Simulation time 27501124 ps
CPU time 1.29 seconds
Started May 30 02:05:54 PM PDT 24
Finished May 30 02:05:56 PM PDT 24
Peak memory 209716 kb
Host smart-1f0c914c-b2b1-4d22-947b-8831b8a4f26f
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694171194 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.lc_ctrl_jtag_alert_test.2694171194
Directory /workspace/2.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.1359788986
Short name T904
Test name
Test status
Simulation time 803936388 ps
CPU time 10.37 seconds
Started May 30 02:05:53 PM PDT 24
Finished May 30 02:06:04 PM PDT 24
Peak memory 217096 kb
Host smart-f05285a9-08d2-40f4-b1d5-7928e377a162
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359788986 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_aliasing.1359788986
Directory /workspace/2.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.1110504442
Short name T159
Test name
Test status
Simulation time 767410811 ps
CPU time 6.55 seconds
Started May 30 02:05:54 PM PDT 24
Finished May 30 02:06:02 PM PDT 24
Peak memory 209364 kb
Host smart-5fc419f0-e723-43bd-a0e0-fc80da04b589
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110504442 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_bit_bash.1110504442
Directory /workspace/2.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.3460964776
Short name T954
Test name
Test status
Simulation time 168960381 ps
CPU time 2.61 seconds
Started May 30 02:05:52 PM PDT 24
Finished May 30 02:05:56 PM PDT 24
Peak memory 211172 kb
Host smart-71973e67-06e6-4b45-91ef-6cf3b7a8f68c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460964776 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_hw_reset.3460964776
Directory /workspace/2.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1210352026
Short name T914
Test name
Test status
Simulation time 90378186 ps
CPU time 3.08 seconds
Started May 30 02:05:50 PM PDT 24
Finished May 30 02:05:54 PM PDT 24
Peak memory 218200 kb
Host smart-b7b84428-a650-4dcd-aa18-cadc65c3778a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121035
2026 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1210352026
Directory /workspace/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.1317001353
Short name T994
Test name
Test status
Simulation time 107743882 ps
CPU time 1.25 seconds
Started May 30 02:05:54 PM PDT 24
Finished May 30 02:05:56 PM PDT 24
Peak memory 209708 kb
Host smart-9af10aea-437f-4b22-a3e6-32eb695df2bf
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317001353 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.lc_ctrl_jtag_csr_rw.1317001353
Directory /workspace/2.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.3979469112
Short name T920
Test name
Test status
Simulation time 140388160 ps
CPU time 1.68 seconds
Started May 30 02:05:52 PM PDT 24
Finished May 30 02:05:55 PM PDT 24
Peak memory 211876 kb
Host smart-d87adb49-4bb2-49fe-a633-6db5a5b970f7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979469112 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.lc_ctrl_jtag_same_csr_outstanding.3979469112
Directory /workspace/2.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.2127814178
Short name T955
Test name
Test status
Simulation time 39965075 ps
CPU time 1.38 seconds
Started May 30 02:06:24 PM PDT 24
Finished May 30 02:06:26 PM PDT 24
Peak memory 209888 kb
Host smart-e1f6d36e-1a7b-4d9a-a8bf-9b1505f6c6a9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127814178 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl
_same_csr_outstanding.2127814178
Directory /workspace/2.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.2988368749
Short name T986
Test name
Test status
Simulation time 861516415 ps
CPU time 2.14 seconds
Started May 30 02:05:54 PM PDT 24
Finished May 30 02:05:57 PM PDT 24
Peak memory 218172 kb
Host smart-b7fada36-337c-4101-bc90-97bb4fb8f3a5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988368749 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_errors.2988368749
Directory /workspace/2.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.1537198531
Short name T956
Test name
Test status
Simulation time 285844754 ps
CPU time 1.03 seconds
Started May 30 02:06:55 PM PDT 24
Finished May 30 02:06:58 PM PDT 24
Peak memory 209800 kb
Host smart-8ac28c98-b82b-413c-b217-57ec935659ae
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537198531 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_aliasin
g.1537198531
Directory /workspace/3.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.2672680075
Short name T204
Test name
Test status
Simulation time 28794845 ps
CPU time 1.84 seconds
Started May 30 02:06:56 PM PDT 24
Finished May 30 02:06:59 PM PDT 24
Peak memory 209340 kb
Host smart-12b5d7f6-763d-48d4-ad2c-5823f1a1ba8e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672680075 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_bit_bas
h.2672680075
Directory /workspace/3.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.430849925
Short name T886
Test name
Test status
Simulation time 61797234 ps
CPU time 1.51 seconds
Started May 30 02:06:57 PM PDT 24
Finished May 30 02:07:00 PM PDT 24
Peak memory 219132 kb
Host smart-3c5e04d6-2f69-4c7e-b1f2-7d87f186b5fa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430849925 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 3.lc_ctrl_csr_mem_rw_with_rand_reset.430849925
Directory /workspace/3.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.142529585
Short name T934
Test name
Test status
Simulation time 13882941 ps
CPU time 1 seconds
Started May 30 02:06:57 PM PDT 24
Finished May 30 02:06:59 PM PDT 24
Peak memory 209836 kb
Host smart-fbca5ff7-6ca6-47b0-8f2e-b3b31e7cc84a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142529585 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_rw.142529585
Directory /workspace/3.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.3725869143
Short name T878
Test name
Test status
Simulation time 195617148 ps
CPU time 1.79 seconds
Started May 30 02:06:55 PM PDT 24
Finished May 30 02:06:57 PM PDT 24
Peak memory 208956 kb
Host smart-d718eb6a-7c2e-4e83-ac3d-fa6ac945b19a
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725869143 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.lc_ctrl_jtag_alert_test.3725869143
Directory /workspace/3.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.1593220809
Short name T905
Test name
Test status
Simulation time 2856019033 ps
CPU time 16.55 seconds
Started May 30 02:06:24 PM PDT 24
Finished May 30 02:06:41 PM PDT 24
Peak memory 209840 kb
Host smart-90cfe8cc-58b9-4959-ba5a-cc92a3772894
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593220809 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_aliasing.1593220809
Directory /workspace/3.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.4056925632
Short name T917
Test name
Test status
Simulation time 2501432872 ps
CPU time 5.86 seconds
Started May 30 02:06:22 PM PDT 24
Finished May 30 02:06:28 PM PDT 24
Peak memory 209716 kb
Host smart-5b4da56b-3389-4934-86fe-1ccf92f090fa
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056925632 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_bit_bash.4056925632
Directory /workspace/3.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.1338911690
Short name T908
Test name
Test status
Simulation time 225740907 ps
CPU time 2.04 seconds
Started May 30 02:06:22 PM PDT 24
Finished May 30 02:06:24 PM PDT 24
Peak memory 211200 kb
Host smart-4fa83f18-87d5-459f-9299-afd752f9b33d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338911690 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_hw_reset.1338911690
Directory /workspace/3.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1536863272
Short name T896
Test name
Test status
Simulation time 424933879 ps
CPU time 2.32 seconds
Started May 30 02:06:55 PM PDT 24
Finished May 30 02:06:59 PM PDT 24
Peak memory 219280 kb
Host smart-95de2871-c691-4e2b-b75d-1583b246296b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153686
3272 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1536863272
Directory /workspace/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.301809800
Short name T916
Test name
Test status
Simulation time 57096695 ps
CPU time 1.22 seconds
Started May 30 02:06:20 PM PDT 24
Finished May 30 02:06:22 PM PDT 24
Peak memory 209752 kb
Host smart-c47450c3-0b08-4b67-846b-d8398870a7db
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301809800 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.lc_ctrl_jtag_csr_rw.301809800
Directory /workspace/3.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.752700351
Short name T965
Test name
Test status
Simulation time 150019255 ps
CPU time 1.44 seconds
Started May 30 02:06:58 PM PDT 24
Finished May 30 02:07:00 PM PDT 24
Peak memory 211940 kb
Host smart-b1e03861-27f1-4dbc-9b44-95ce0f0b75f7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752700351 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.lc_ctrl_jtag_same_csr_outstanding.752700351
Directory /workspace/3.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.1292608684
Short name T176
Test name
Test status
Simulation time 63065113 ps
CPU time 1.25 seconds
Started May 30 02:06:54 PM PDT 24
Finished May 30 02:06:56 PM PDT 24
Peak memory 217732 kb
Host smart-aa809a1b-0213-4748-aab8-34bfcda9a4b4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292608684 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl
_same_csr_outstanding.1292608684
Directory /workspace/3.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.1266716726
Short name T131
Test name
Test status
Simulation time 234378025 ps
CPU time 2.86 seconds
Started May 30 02:06:55 PM PDT 24
Finished May 30 02:07:00 PM PDT 24
Peak memory 218104 kb
Host smart-fd1cf0d0-72b4-4c63-9f59-34740b89057f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266716726 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_errors.1266716726
Directory /workspace/3.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.28580423
Short name T201
Test name
Test status
Simulation time 349807423 ps
CPU time 1.28 seconds
Started May 30 02:06:55 PM PDT 24
Finished May 30 02:06:58 PM PDT 24
Peak memory 209780 kb
Host smart-30cd110a-0e12-4da8-ac41-275bd8f2dd29
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28580423 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_aliasing.28580423
Directory /workspace/4.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.2997730417
Short name T989
Test name
Test status
Simulation time 30292444 ps
CPU time 1.83 seconds
Started May 30 02:06:56 PM PDT 24
Finished May 30 02:07:00 PM PDT 24
Peak memory 209764 kb
Host smart-f993c809-dd5f-4511-81ef-af24dbb33283
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997730417 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_bit_bas
h.2997730417
Directory /workspace/4.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.3512389327
Short name T205
Test name
Test status
Simulation time 16057363 ps
CPU time 1.23 seconds
Started May 30 02:06:58 PM PDT 24
Finished May 30 02:07:01 PM PDT 24
Peak memory 211868 kb
Host smart-faf930b5-6114-4831-ad0d-40957a629e10
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512389327 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_hw_rese
t.3512389327
Directory /workspace/4.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.3875916532
Short name T912
Test name
Test status
Simulation time 70242117 ps
CPU time 1.35 seconds
Started May 30 02:06:57 PM PDT 24
Finished May 30 02:06:59 PM PDT 24
Peak memory 223308 kb
Host smart-54f8b7c8-2d10-43ee-a919-c2f6def80c20
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875916532 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 4.lc_ctrl_csr_mem_rw_with_rand_reset.3875916532
Directory /workspace/4.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.2111798351
Short name T202
Test name
Test status
Simulation time 22441615 ps
CPU time 0.86 seconds
Started May 30 02:06:55 PM PDT 24
Finished May 30 02:06:57 PM PDT 24
Peak memory 209292 kb
Host smart-e63f59b9-ee27-4fe7-a4b4-c4161268273b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111798351 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_rw.2111798351
Directory /workspace/4.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.2073270893
Short name T893
Test name
Test status
Simulation time 106260437 ps
CPU time 1 seconds
Started May 30 02:06:55 PM PDT 24
Finished May 30 02:06:57 PM PDT 24
Peak memory 208968 kb
Host smart-b12fac93-318b-4fa4-a56b-4a556aead928
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073270893 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.lc_ctrl_jtag_alert_test.2073270893
Directory /workspace/4.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.2306369994
Short name T940
Test name
Test status
Simulation time 2348155631 ps
CPU time 14.86 seconds
Started May 30 02:06:56 PM PDT 24
Finished May 30 02:07:12 PM PDT 24
Peak memory 209668 kb
Host smart-f1066c52-b37a-4173-89b7-b7d8da983bc4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306369994 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_aliasing.2306369994
Directory /workspace/4.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.1784819593
Short name T903
Test name
Test status
Simulation time 489267906 ps
CPU time 6.38 seconds
Started May 30 02:06:58 PM PDT 24
Finished May 30 02:07:06 PM PDT 24
Peak memory 217148 kb
Host smart-f086dd6b-206d-4d0d-8908-b98a8a9ef395
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784819593 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_bit_bash.1784819593
Directory /workspace/4.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.2831202718
Short name T877
Test name
Test status
Simulation time 205353889 ps
CPU time 3.05 seconds
Started May 30 02:06:58 PM PDT 24
Finished May 30 02:07:02 PM PDT 24
Peak memory 211280 kb
Host smart-a5cf61b3-63ef-426b-b0c7-ba280b717f05
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831202718 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_hw_reset.2831202718
Directory /workspace/4.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.509513249
Short name T969
Test name
Test status
Simulation time 177145273 ps
CPU time 1.52 seconds
Started May 30 02:06:57 PM PDT 24
Finished May 30 02:07:00 PM PDT 24
Peak memory 218624 kb
Host smart-90ac93ba-bef3-4ff4-96ee-ac6309af0058
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509513
249 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.509513249
Directory /workspace/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.3990812029
Short name T930
Test name
Test status
Simulation time 237340665 ps
CPU time 1.21 seconds
Started May 30 02:06:55 PM PDT 24
Finished May 30 02:06:58 PM PDT 24
Peak memory 209648 kb
Host smart-127d7064-cbd4-41b0-bc79-264812ce176f
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990812029 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.lc_ctrl_jtag_csr_rw.3990812029
Directory /workspace/4.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.2908933206
Short name T211
Test name
Test status
Simulation time 27359911 ps
CPU time 1.19 seconds
Started May 30 02:06:55 PM PDT 24
Finished May 30 02:06:57 PM PDT 24
Peak memory 209632 kb
Host smart-7886c651-699f-4a7d-b27f-503c949c68f0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908933206 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.lc_ctrl_jtag_same_csr_outstanding.2908933206
Directory /workspace/4.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.1665328291
Short name T174
Test name
Test status
Simulation time 25839270 ps
CPU time 1.43 seconds
Started May 30 02:06:58 PM PDT 24
Finished May 30 02:07:01 PM PDT 24
Peak memory 209900 kb
Host smart-667fb127-0550-4e19-93d5-81dab413a916
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665328291 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl
_same_csr_outstanding.1665328291
Directory /workspace/4.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.1222624363
Short name T970
Test name
Test status
Simulation time 87219289 ps
CPU time 3.5 seconds
Started May 30 02:06:55 PM PDT 24
Finished May 30 02:07:00 PM PDT 24
Peak memory 218252 kb
Host smart-14117a82-a8fc-4e65-8b86-c01ce95fa001
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222624363 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_errors.1222624363
Directory /workspace/4.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.2164960515
Short name T143
Test name
Test status
Simulation time 34972844 ps
CPU time 1.34 seconds
Started May 30 02:06:55 PM PDT 24
Finished May 30 02:06:58 PM PDT 24
Peak memory 218248 kb
Host smart-35673755-4999-4254-99ab-9bcc5bf43f77
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164960515 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 5.lc_ctrl_csr_mem_rw_with_rand_reset.2164960515
Directory /workspace/5.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.479522970
Short name T203
Test name
Test status
Simulation time 14281087 ps
CPU time 1.06 seconds
Started May 30 02:06:58 PM PDT 24
Finished May 30 02:07:00 PM PDT 24
Peak memory 209524 kb
Host smart-460f04bd-4dfd-4f7a-9191-b3dd88d19365
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479522970 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_csr_rw.479522970
Directory /workspace/5.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.863720998
Short name T899
Test name
Test status
Simulation time 44835203 ps
CPU time 0.95 seconds
Started May 30 02:06:55 PM PDT 24
Finished May 30 02:06:57 PM PDT 24
Peak memory 208960 kb
Host smart-9cfec5a9-6fd9-46e7-9d86-935cf3c267ca
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863720998 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 5.lc_ctrl_jtag_alert_test.863720998
Directory /workspace/5.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.2022726268
Short name T998
Test name
Test status
Simulation time 4489964632 ps
CPU time 9.86 seconds
Started May 30 02:06:55 PM PDT 24
Finished May 30 02:07:07 PM PDT 24
Peak memory 209668 kb
Host smart-e2660e4a-ad50-41e1-a2a4-56c49423db16
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022726268 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_aliasing.2022726268
Directory /workspace/5.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.3856777963
Short name T898
Test name
Test status
Simulation time 3170979016 ps
CPU time 10.95 seconds
Started May 30 02:06:58 PM PDT 24
Finished May 30 02:07:11 PM PDT 24
Peak memory 209084 kb
Host smart-417ddcd2-5a1b-48cb-825c-ce895688f62f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856777963 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_bit_bash.3856777963
Directory /workspace/5.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.3268988205
Short name T155
Test name
Test status
Simulation time 121899898 ps
CPU time 3.5 seconds
Started May 30 02:06:56 PM PDT 24
Finished May 30 02:07:01 PM PDT 24
Peak memory 211376 kb
Host smart-dd9e4be4-27ec-4102-b0eb-0d5df883fac9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268988205 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_hw_reset.3268988205
Directory /workspace/5.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1038177028
Short name T987
Test name
Test status
Simulation time 399823019 ps
CPU time 3.77 seconds
Started May 30 02:06:41 PM PDT 24
Finished May 30 02:06:46 PM PDT 24
Peak memory 219232 kb
Host smart-bba12191-5780-40d3-8d96-59dafd6cd312
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103817
7028 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1038177028
Directory /workspace/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.4266231436
Short name T880
Test name
Test status
Simulation time 84933465 ps
CPU time 1.52 seconds
Started May 30 02:06:59 PM PDT 24
Finished May 30 02:07:02 PM PDT 24
Peak memory 209812 kb
Host smart-c0c2d78c-34fd-4dcb-bfae-7cf8a8f3e455
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266231436 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.lc_ctrl_jtag_csr_rw.4266231436
Directory /workspace/5.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.3046038326
Short name T926
Test name
Test status
Simulation time 62461670 ps
CPU time 1.33 seconds
Started May 30 02:06:57 PM PDT 24
Finished May 30 02:07:00 PM PDT 24
Peak memory 209984 kb
Host smart-24f14bc2-58c9-41dd-ab93-a6d7641411d4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046038326 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.lc_ctrl_jtag_same_csr_outstanding.3046038326
Directory /workspace/5.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.2840308044
Short name T902
Test name
Test status
Simulation time 39877519 ps
CPU time 1.91 seconds
Started May 30 02:06:58 PM PDT 24
Finished May 30 02:07:01 PM PDT 24
Peak memory 211728 kb
Host smart-ffac2799-107f-41cb-8b90-bd8024b7993c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840308044 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl
_same_csr_outstanding.2840308044
Directory /workspace/5.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.3381391048
Short name T889
Test name
Test status
Simulation time 67157023 ps
CPU time 2.5 seconds
Started May 30 02:06:58 PM PDT 24
Finished May 30 02:07:01 PM PDT 24
Peak memory 218176 kb
Host smart-2c84b3be-e360-4157-a9a6-ea5cf03f774a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381391048 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_errors.3381391048
Directory /workspace/5.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.3497523964
Short name T145
Test name
Test status
Simulation time 278395621 ps
CPU time 3.02 seconds
Started May 30 02:06:55 PM PDT 24
Finished May 30 02:06:59 PM PDT 24
Peak memory 222672 kb
Host smart-a2905711-9d2f-498e-b2c0-4c56e0046bb7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497523964 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_intg_
err.3497523964
Directory /workspace/5.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.557168946
Short name T978
Test name
Test status
Simulation time 78990216 ps
CPU time 1.12 seconds
Started May 30 02:06:50 PM PDT 24
Finished May 30 02:06:52 PM PDT 24
Peak memory 219400 kb
Host smart-5c89725b-7f1f-4a9a-9fd7-4408c6148b4a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557168946 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 6.lc_ctrl_csr_mem_rw_with_rand_reset.557168946
Directory /workspace/6.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.2770640397
Short name T966
Test name
Test status
Simulation time 59066227 ps
CPU time 0.88 seconds
Started May 30 02:06:55 PM PDT 24
Finished May 30 02:06:57 PM PDT 24
Peak memory 209844 kb
Host smart-35be3164-b4a2-400c-b809-7c61e2da09b6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770640397 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_csr_rw.2770640397
Directory /workspace/6.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.3955776868
Short name T876
Test name
Test status
Simulation time 126151791 ps
CPU time 0.9 seconds
Started May 30 02:06:55 PM PDT 24
Finished May 30 02:06:58 PM PDT 24
Peak memory 208972 kb
Host smart-26699215-c509-44f7-96a5-4b8ff5b443b7
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955776868 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.lc_ctrl_jtag_alert_test.3955776868
Directory /workspace/6.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.3752030983
Short name T996
Test name
Test status
Simulation time 2131944833 ps
CPU time 4.37 seconds
Started May 30 02:06:55 PM PDT 24
Finished May 30 02:07:00 PM PDT 24
Peak memory 209460 kb
Host smart-a3a3c228-3f02-48d4-85cd-b40c5751f5e0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752030983 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_aliasing.3752030983
Directory /workspace/6.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.1603490734
Short name T925
Test name
Test status
Simulation time 699268799 ps
CPU time 17.47 seconds
Started May 30 02:06:54 PM PDT 24
Finished May 30 02:07:12 PM PDT 24
Peak memory 209720 kb
Host smart-c4fb18c9-548a-4a14-9f78-f0701ce2517d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603490734 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_bit_bash.1603490734
Directory /workspace/6.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.631422163
Short name T911
Test name
Test status
Simulation time 516609939 ps
CPU time 2.57 seconds
Started May 30 02:06:57 PM PDT 24
Finished May 30 02:07:01 PM PDT 24
Peak memory 211224 kb
Host smart-c4f64194-cf15-428a-a752-ee491e7c12f2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631422163 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 6.lc_ctrl_jtag_csr_hw_reset.631422163
Directory /workspace/6.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.162043636
Short name T885
Test name
Test status
Simulation time 303184206 ps
CPU time 1.51 seconds
Started May 30 02:06:56 PM PDT 24
Finished May 30 02:06:59 PM PDT 24
Peak memory 219440 kb
Host smart-4d7f56cf-ec56-4341-89c1-6b95df95e13a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162043
636 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.162043636
Directory /workspace/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.1769533713
Short name T933
Test name
Test status
Simulation time 86566884 ps
CPU time 2.45 seconds
Started May 30 02:06:55 PM PDT 24
Finished May 30 02:06:59 PM PDT 24
Peak memory 217804 kb
Host smart-511f3dd1-3df2-4128-a03d-22ed138f4542
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769533713 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.lc_ctrl_jtag_csr_rw.1769533713
Directory /workspace/6.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.925678242
Short name T967
Test name
Test status
Simulation time 26426911 ps
CPU time 1.18 seconds
Started May 30 02:06:56 PM PDT 24
Finished May 30 02:06:59 PM PDT 24
Peak memory 209928 kb
Host smart-24e2f868-156e-41e8-a212-21d04cfa7371
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925678242 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.lc_ctrl_jtag_same_csr_outstanding.925678242
Directory /workspace/6.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.4197574777
Short name T213
Test name
Test status
Simulation time 23593133 ps
CPU time 1.43 seconds
Started May 30 02:06:59 PM PDT 24
Finished May 30 02:07:02 PM PDT 24
Peak memory 209356 kb
Host smart-d6790531-4aad-42e9-b54b-c1c2b45088e3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197574777 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl
_same_csr_outstanding.4197574777
Directory /workspace/6.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.3451904510
Short name T936
Test name
Test status
Simulation time 559758371 ps
CPU time 3.52 seconds
Started May 30 02:06:58 PM PDT 24
Finished May 30 02:07:03 PM PDT 24
Peak memory 218172 kb
Host smart-56dcb10b-2f3f-4b21-b1ab-9cb7ed63a7c6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451904510 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_errors.3451904510
Directory /workspace/6.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.361869975
Short name T982
Test name
Test status
Simulation time 108992677 ps
CPU time 2.99 seconds
Started May 30 02:06:55 PM PDT 24
Finished May 30 02:07:00 PM PDT 24
Peak memory 222836 kb
Host smart-280dae13-a9ae-4ce9-a9ee-f0195d96a4b8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361869975 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_intg_e
rr.361869975
Directory /workspace/6.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.1192404006
Short name T971
Test name
Test status
Simulation time 21220153 ps
CPU time 1.58 seconds
Started May 30 02:07:00 PM PDT 24
Finished May 30 02:07:03 PM PDT 24
Peak memory 219180 kb
Host smart-b1744fbe-648f-43c3-b96f-568892b9137d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192404006 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 7.lc_ctrl_csr_mem_rw_with_rand_reset.1192404006
Directory /workspace/7.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.724090762
Short name T199
Test name
Test status
Simulation time 44051654 ps
CPU time 1.01 seconds
Started May 30 02:06:59 PM PDT 24
Finished May 30 02:07:02 PM PDT 24
Peak memory 209576 kb
Host smart-8cb712b3-6257-45e5-8f7c-f7a775d4312d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724090762 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_csr_rw.724090762
Directory /workspace/7.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.2773160375
Short name T939
Test name
Test status
Simulation time 144286889 ps
CPU time 0.97 seconds
Started May 30 02:07:01 PM PDT 24
Finished May 30 02:07:03 PM PDT 24
Peak memory 209660 kb
Host smart-74b5a769-c255-4030-bae0-b5a4f0969ab8
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773160375 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.lc_ctrl_jtag_alert_test.2773160375
Directory /workspace/7.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.1755948757
Short name T888
Test name
Test status
Simulation time 446597102 ps
CPU time 9.99 seconds
Started May 30 02:06:58 PM PDT 24
Finished May 30 02:07:10 PM PDT 24
Peak memory 209520 kb
Host smart-5cd09e24-1bf8-42bf-93f7-be2b85b2f38c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755948757 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_aliasing.1755948757
Directory /workspace/7.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.367971067
Short name T979
Test name
Test status
Simulation time 1288625130 ps
CPU time 27.44 seconds
Started May 30 02:06:56 PM PDT 24
Finished May 30 02:07:25 PM PDT 24
Peak memory 208940 kb
Host smart-12004678-6240-40a8-8848-e44bf3db73bb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367971067 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 7.lc_ctrl_jtag_csr_bit_bash.367971067
Directory /workspace/7.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.3063191922
Short name T927
Test name
Test status
Simulation time 98362607 ps
CPU time 2.87 seconds
Started May 30 02:06:51 PM PDT 24
Finished May 30 02:06:54 PM PDT 24
Peak memory 217880 kb
Host smart-8d30ea2b-da3e-4398-8493-b6a908fa69f9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063191922 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_hw_reset.3063191922
Directory /workspace/7.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3456145542
Short name T951
Test name
Test status
Simulation time 113206859 ps
CPU time 1.49 seconds
Started May 30 02:06:58 PM PDT 24
Finished May 30 02:07:01 PM PDT 24
Peak memory 218164 kb
Host smart-ab8fdc02-367a-4342-be1a-abd26e0b59a8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345614
5542 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3456145542
Directory /workspace/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.2136611635
Short name T946
Test name
Test status
Simulation time 1219341705 ps
CPU time 1.52 seconds
Started May 30 02:06:55 PM PDT 24
Finished May 30 02:06:58 PM PDT 24
Peak memory 217760 kb
Host smart-cebcc8c2-5679-46f0-8c77-dd3714c528c7
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136611635 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.lc_ctrl_jtag_csr_rw.2136611635
Directory /workspace/7.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.2996792076
Short name T931
Test name
Test status
Simulation time 18186696 ps
CPU time 1.25 seconds
Started May 30 02:06:57 PM PDT 24
Finished May 30 02:07:00 PM PDT 24
Peak memory 209944 kb
Host smart-f7cd1096-2aae-4cd6-be41-f008b0858fa8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996792076 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.lc_ctrl_jtag_same_csr_outstanding.2996792076
Directory /workspace/7.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.1401904252
Short name T924
Test name
Test status
Simulation time 226573587 ps
CPU time 1.13 seconds
Started May 30 02:06:58 PM PDT 24
Finished May 30 02:07:00 PM PDT 24
Peak memory 217668 kb
Host smart-16f36734-e34c-4e54-92fa-de1b55616a7b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401904252 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl
_same_csr_outstanding.1401904252
Directory /workspace/7.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.1619294311
Short name T950
Test name
Test status
Simulation time 129283602 ps
CPU time 2.31 seconds
Started May 30 02:06:59 PM PDT 24
Finished May 30 02:07:03 PM PDT 24
Peak memory 218252 kb
Host smart-18d6b93c-05d9-450a-8faf-a1c55ebc3a25
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619294311 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_errors.1619294311
Directory /workspace/7.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.2280046439
Short name T150
Test name
Test status
Simulation time 259040081 ps
CPU time 1.96 seconds
Started May 30 02:06:58 PM PDT 24
Finished May 30 02:07:02 PM PDT 24
Peak memory 222180 kb
Host smart-8236676b-e658-4ef5-bd42-d3a5a8180352
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280046439 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_intg_
err.2280046439
Directory /workspace/7.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.4058168344
Short name T991
Test name
Test status
Simulation time 114975203 ps
CPU time 1.42 seconds
Started May 30 02:07:04 PM PDT 24
Finished May 30 02:07:07 PM PDT 24
Peak memory 219236 kb
Host smart-9c70284e-fbd9-45d9-b01c-3366beb4bbfe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058168344 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 8.lc_ctrl_csr_mem_rw_with_rand_reset.4058168344
Directory /workspace/8.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.2125033033
Short name T884
Test name
Test status
Simulation time 50804770 ps
CPU time 0.88 seconds
Started May 30 02:06:59 PM PDT 24
Finished May 30 02:07:02 PM PDT 24
Peak memory 209688 kb
Host smart-10025a63-3aa2-4f15-a278-72914db116e7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125033033 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_csr_rw.2125033033
Directory /workspace/8.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.1520633413
Short name T883
Test name
Test status
Simulation time 41110232 ps
CPU time 1.34 seconds
Started May 30 02:06:55 PM PDT 24
Finished May 30 02:06:57 PM PDT 24
Peak memory 209684 kb
Host smart-9b60ee1f-35d2-46f2-976f-fd7938d83509
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520633413 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.lc_ctrl_jtag_alert_test.1520633413
Directory /workspace/8.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.3540918193
Short name T935
Test name
Test status
Simulation time 951466405 ps
CPU time 12.05 seconds
Started May 30 02:06:59 PM PDT 24
Finished May 30 02:07:13 PM PDT 24
Peak memory 209752 kb
Host smart-e9b0b73a-2023-4c1c-b641-fedd4a84ab57
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540918193 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_aliasing.3540918193
Directory /workspace/8.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.4131233177
Short name T953
Test name
Test status
Simulation time 11555814867 ps
CPU time 8.1 seconds
Started May 30 02:07:00 PM PDT 24
Finished May 30 02:07:10 PM PDT 24
Peak memory 217212 kb
Host smart-1077ed06-105e-42a4-bde0-2c994c4d7aef
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131233177 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_bit_bash.4131233177
Directory /workspace/8.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.20919565
Short name T947
Test name
Test status
Simulation time 103613271 ps
CPU time 1.41 seconds
Started May 30 02:07:01 PM PDT 24
Finished May 30 02:07:04 PM PDT 24
Peak memory 211116 kb
Host smart-cf5936fa-9287-4c66-ae04-918ae82563f4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20919565 -assert nopostproc +UVM_TESTNAME=lc_ctrl_bas
e_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 8.lc_ctrl_jtag_csr_hw_reset.20919565
Directory /workspace/8.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1889337646
Short name T157
Test name
Test status
Simulation time 102875549 ps
CPU time 1.74 seconds
Started May 30 02:06:59 PM PDT 24
Finished May 30 02:07:03 PM PDT 24
Peak memory 218176 kb
Host smart-5dce1543-3d49-4760-80b6-e96287f16d91
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188933
7646 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1889337646
Directory /workspace/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.650969622
Short name T963
Test name
Test status
Simulation time 61618460 ps
CPU time 1.5 seconds
Started May 30 02:07:00 PM PDT 24
Finished May 30 02:07:03 PM PDT 24
Peak memory 209736 kb
Host smart-d7a66d0a-9719-4366-878e-b90541ddda45
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650969622 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.lc_ctrl_jtag_csr_rw.650969622
Directory /workspace/8.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.4099682773
Short name T980
Test name
Test status
Simulation time 142823016 ps
CPU time 1.77 seconds
Started May 30 02:07:00 PM PDT 24
Finished May 30 02:07:04 PM PDT 24
Peak memory 217828 kb
Host smart-432c8ca0-4aa8-4da7-87b3-87811c330e4b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099682773 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.lc_ctrl_jtag_same_csr_outstanding.4099682773
Directory /workspace/8.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.1129844019
Short name T968
Test name
Test status
Simulation time 498308537 ps
CPU time 2 seconds
Started May 30 02:07:04 PM PDT 24
Finished May 30 02:07:06 PM PDT 24
Peak memory 209888 kb
Host smart-00a49732-8a0e-4eab-81b5-c9e7b66f135a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129844019 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl
_same_csr_outstanding.1129844019
Directory /workspace/8.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.3192774099
Short name T922
Test name
Test status
Simulation time 51992172 ps
CPU time 1.77 seconds
Started May 30 02:07:00 PM PDT 24
Finished May 30 02:07:03 PM PDT 24
Peak memory 218220 kb
Host smart-118e93ad-a916-4a8d-b5be-091517be0c18
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192774099 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_errors.3192774099
Directory /workspace/8.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.1800835870
Short name T152
Test name
Test status
Simulation time 86280437 ps
CPU time 3.18 seconds
Started May 30 02:07:00 PM PDT 24
Finished May 30 02:07:05 PM PDT 24
Peak memory 218040 kb
Host smart-4467d8ed-cc2d-4fdb-849e-0dc113793b1c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800835870 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_intg_
err.1800835870
Directory /workspace/8.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.3655777914
Short name T127
Test name
Test status
Simulation time 71642426 ps
CPU time 1.17 seconds
Started May 30 02:07:01 PM PDT 24
Finished May 30 02:07:04 PM PDT 24
Peak memory 218216 kb
Host smart-b23f5e7d-041f-4e22-a170-4eec496e5156
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655777914 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 9.lc_ctrl_csr_mem_rw_with_rand_reset.3655777914
Directory /workspace/9.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.292244485
Short name T195
Test name
Test status
Simulation time 17495451 ps
CPU time 1.14 seconds
Started May 30 02:07:02 PM PDT 24
Finished May 30 02:07:05 PM PDT 24
Peak memory 209860 kb
Host smart-bca7be52-80f4-4e49-9922-ec514339eef8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292244485 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_csr_rw.292244485
Directory /workspace/9.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.824501370
Short name T891
Test name
Test status
Simulation time 276288100 ps
CPU time 1.02 seconds
Started May 30 02:07:06 PM PDT 24
Finished May 30 02:07:08 PM PDT 24
Peak memory 209696 kb
Host smart-67f03e87-3157-40ba-aa3a-aeae0273fba7
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824501370 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 9.lc_ctrl_jtag_alert_test.824501370
Directory /workspace/9.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.1118027657
Short name T997
Test name
Test status
Simulation time 8254675894 ps
CPU time 6.3 seconds
Started May 30 02:07:04 PM PDT 24
Finished May 30 02:07:11 PM PDT 24
Peak memory 209788 kb
Host smart-c094fee4-1952-4774-83df-ad9e15f389a4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118027657 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_aliasing.1118027657
Directory /workspace/9.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.2281346666
Short name T960
Test name
Test status
Simulation time 1653710849 ps
CPU time 10.36 seconds
Started May 30 02:07:06 PM PDT 24
Finished May 30 02:07:17 PM PDT 24
Peak memory 209504 kb
Host smart-4f40ceeb-7d6f-439a-b4f1-4804af9847ed
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281346666 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_bit_bash.2281346666
Directory /workspace/9.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.2762060183
Short name T906
Test name
Test status
Simulation time 134245643 ps
CPU time 1.94 seconds
Started May 30 02:07:04 PM PDT 24
Finished May 30 02:07:07 PM PDT 24
Peak memory 217984 kb
Host smart-bce4f983-114f-41a3-89ab-86bcfdcdb2c2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762060183 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_hw_reset.2762060183
Directory /workspace/9.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3796490026
Short name T158
Test name
Test status
Simulation time 103470340 ps
CPU time 3.65 seconds
Started May 30 02:07:04 PM PDT 24
Finished May 30 02:07:09 PM PDT 24
Peak memory 219624 kb
Host smart-62efa5ec-7b54-4be5-a94b-7a71824f161a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379649
0026 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3796490026
Directory /workspace/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.3060949692
Short name T156
Test name
Test status
Simulation time 55787589 ps
CPU time 1.35 seconds
Started May 30 02:07:03 PM PDT 24
Finished May 30 02:07:05 PM PDT 24
Peak memory 209744 kb
Host smart-a0e90f0a-88f6-4fb4-8a28-87acbb5438d9
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060949692 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.lc_ctrl_jtag_csr_rw.3060949692
Directory /workspace/9.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.4247659034
Short name T942
Test name
Test status
Simulation time 91005208 ps
CPU time 1.6 seconds
Started May 30 02:07:02 PM PDT 24
Finished May 30 02:07:05 PM PDT 24
Peak memory 212056 kb
Host smart-1415f1a0-e098-485d-b48d-542b3217f75a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247659034 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.lc_ctrl_jtag_same_csr_outstanding.4247659034
Directory /workspace/9.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.4292123970
Short name T900
Test name
Test status
Simulation time 17376136 ps
CPU time 1.15 seconds
Started May 30 02:07:06 PM PDT 24
Finished May 30 02:07:08 PM PDT 24
Peak memory 209916 kb
Host smart-f842895b-53b6-4d97-8179-e8923a02943f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292123970 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl
_same_csr_outstanding.4292123970
Directory /workspace/9.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.2319224689
Short name T929
Test name
Test status
Simulation time 127744129 ps
CPU time 2.11 seconds
Started May 30 02:07:06 PM PDT 24
Finished May 30 02:07:09 PM PDT 24
Peak memory 219192 kb
Host smart-31d7be8a-0a1d-445e-9651-b00bff4f269f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319224689 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_errors.2319224689
Directory /workspace/9.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.1212310834
Short name T135
Test name
Test status
Simulation time 77885818 ps
CPU time 3.5 seconds
Started May 30 02:07:06 PM PDT 24
Finished May 30 02:07:11 PM PDT 24
Peak memory 218200 kb
Host smart-5b3c1d36-f856-485b-b2d9-eaa59e42df15
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212310834 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_intg_
err.1212310834
Directory /workspace/9.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_alert_test.2179446214
Short name T340
Test name
Test status
Simulation time 28576790 ps
CPU time 0.88 seconds
Started May 30 02:09:39 PM PDT 24
Finished May 30 02:09:41 PM PDT 24
Peak memory 208736 kb
Host smart-b6bc4e5e-7d26-43a2-9549-73adeed9811c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179446214 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_alert_test.2179446214
Directory /workspace/0.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.lc_ctrl_claim_transition_if.1552508567
Short name T81
Test name
Test status
Simulation time 22025838 ps
CPU time 0.85 seconds
Started May 30 02:09:39 PM PDT 24
Finished May 30 02:09:42 PM PDT 24
Peak memory 208584 kb
Host smart-33786d99-007f-450f-b7c7-14e84a0b931b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552508567 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_claim_transition_if.1552508567
Directory /workspace/0.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/0.lc_ctrl_errors.2411958696
Short name T616
Test name
Test status
Simulation time 2208439292 ps
CPU time 8.85 seconds
Started May 30 02:09:42 PM PDT 24
Finished May 30 02:09:52 PM PDT 24
Peak memory 217820 kb
Host smart-b6897952-d9f3-4b4b-ab23-a1acfc522124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411958696 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_errors.2411958696
Directory /workspace/0.lc_ctrl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_access.3778756237
Short name T8
Test name
Test status
Simulation time 1054502352 ps
CPU time 4.2 seconds
Started May 30 02:09:42 PM PDT 24
Finished May 30 02:09:48 PM PDT 24
Peak memory 209232 kb
Host smart-2488066c-19f6-4c9e-bf55-eb0d0f35ec51
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778756237 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_access.3778756237
Directory /workspace/0.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_errors.3963281106
Short name T96
Test name
Test status
Simulation time 2532160273 ps
CPU time 41 seconds
Started May 30 02:09:41 PM PDT 24
Finished May 30 02:10:23 PM PDT 24
Peak memory 219040 kb
Host smart-f1722fc8-77c3-4206-850b-7b33a4107661
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963281106 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_er
rors.3963281106
Directory /workspace/0.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_priority.4238902731
Short name T292
Test name
Test status
Simulation time 978382375 ps
CPU time 9.83 seconds
Started May 30 02:09:37 PM PDT 24
Finished May 30 02:09:47 PM PDT 24
Peak memory 217008 kb
Host smart-8b730f57-e5fd-4fe2-97e5-c5bef012c75d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238902731 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_priority.4
238902731
Directory /workspace/0.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_prog_failure.968219479
Short name T828
Test name
Test status
Simulation time 350214984 ps
CPU time 5.54 seconds
Started May 30 02:09:39 PM PDT 24
Finished May 30 02:09:47 PM PDT 24
Peak memory 217980 kb
Host smart-fa1724c6-77af-4e90-a91b-e69e9ec34e8b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968219479 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_
prog_failure.968219479
Directory /workspace/0.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_regwen_during_op.1974923747
Short name T381
Test name
Test status
Simulation time 1308183863 ps
CPU time 18.57 seconds
Started May 30 02:09:36 PM PDT 24
Finished May 30 02:09:55 PM PDT 24
Peak memory 217680 kb
Host smart-cba5aed0-42c4-4133-bbb4-a70a81725b79
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974923747 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_regwen_during_op.1974923747
Directory /workspace/0.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_smoke.3640025844
Short name T77
Test name
Test status
Simulation time 271382975 ps
CPU time 8.52 seconds
Started May 30 02:09:38 PM PDT 24
Finished May 30 02:09:47 PM PDT 24
Peak memory 217676 kb
Host smart-6b297fe0-2c66-419b-b597-fa9f59e71c16
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640025844 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_smoke.
3640025844
Directory /workspace/0.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_failure.2276063547
Short name T23
Test name
Test status
Simulation time 3837133757 ps
CPU time 37.15 seconds
Started May 30 02:09:38 PM PDT 24
Finished May 30 02:10:16 PM PDT 24
Peak memory 251008 kb
Host smart-fc2154c2-d187-4861-96fe-ce004e3f1202
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276063547 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jta
g_state_failure.2276063547
Directory /workspace/0.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_post_trans.2949214116
Short name T436
Test name
Test status
Simulation time 2379771320 ps
CPU time 13.36 seconds
Started May 30 02:09:38 PM PDT 24
Finished May 30 02:09:53 PM PDT 24
Peak memory 249736 kb
Host smart-8f453aaa-bab7-41ab-9928-7a8b4655f294
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949214116 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_state_post_trans.2949214116
Directory /workspace/0.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_prog_failure.3972650754
Short name T818
Test name
Test status
Simulation time 103343646 ps
CPU time 3.43 seconds
Started May 30 02:09:38 PM PDT 24
Finished May 30 02:09:44 PM PDT 24
Peak memory 218040 kb
Host smart-8d67a730-f1db-459c-9a9d-b931f36811ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972650754 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_prog_failure.3972650754
Directory /workspace/0.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_regwen_during_op.1398541101
Short name T111
Test name
Test status
Simulation time 612353797 ps
CPU time 12.67 seconds
Started May 30 02:09:39 PM PDT 24
Finished May 30 02:09:53 PM PDT 24
Peak memory 217740 kb
Host smart-316ab580-99e7-4e9a-89d3-8267a224f32d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398541101 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_regwen_during_op.1398541101
Directory /workspace/0.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_cm.296775387
Short name T66
Test name
Test status
Simulation time 453464844 ps
CPU time 32.04 seconds
Started May 30 02:09:40 PM PDT 24
Finished May 30 02:10:13 PM PDT 24
Peak memory 284576 kb
Host smart-e6a34777-5183-49d3-bc60-a8262632d40f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296775387 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_cm.296775387
Directory /workspace/0.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_mubi.2328778601
Short name T57
Test name
Test status
Simulation time 949539634 ps
CPU time 26.83 seconds
Started May 30 02:09:38 PM PDT 24
Finished May 30 02:10:06 PM PDT 24
Peak memory 226144 kb
Host smart-bfbdbd7b-5da8-43fd-ac5a-c0738b978018
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328778601 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_mubi.2328778601
Directory /workspace/0.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_digest.2295716511
Short name T704
Test name
Test status
Simulation time 350957424 ps
CPU time 14.5 seconds
Started May 30 02:09:41 PM PDT 24
Finished May 30 02:09:57 PM PDT 24
Peak memory 217884 kb
Host smart-cfb76d3d-7009-4586-92b6-40d1ee3dd498
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295716511 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_di
gest.2295716511
Directory /workspace/0.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/0.lc_ctrl_security_escalation.3110889580
Short name T423
Test name
Test status
Simulation time 1573272601 ps
CPU time 15.07 seconds
Started May 30 02:09:40 PM PDT 24
Finished May 30 02:09:57 PM PDT 24
Peak memory 218216 kb
Host smart-846926af-dc4b-4cd3-9dc5-845dbd3cb838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110889580 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_security_escalation.3110889580
Directory /workspace/0.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/0.lc_ctrl_smoke.1688270518
Short name T690
Test name
Test status
Simulation time 17037063 ps
CPU time 1.27 seconds
Started May 30 02:09:38 PM PDT 24
Finished May 30 02:09:41 PM PDT 24
Peak memory 217772 kb
Host smart-9a138673-b982-47ed-b233-1608808e02bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688270518 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_smoke.1688270518
Directory /workspace/0.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_failure.1746098168
Short name T790
Test name
Test status
Simulation time 659031147 ps
CPU time 27.59 seconds
Started May 30 02:09:42 PM PDT 24
Finished May 30 02:10:11 PM PDT 24
Peak memory 250912 kb
Host smart-05b64cfc-b213-4798-b08c-b56f125685a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746098168 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_failure.1746098168
Directory /workspace/0.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_post_trans.2184779004
Short name T312
Test name
Test status
Simulation time 42551799 ps
CPU time 7.32 seconds
Started May 30 02:09:40 PM PDT 24
Finished May 30 02:09:49 PM PDT 24
Peak memory 250912 kb
Host smart-85a3ea52-9532-414f-91dc-02fcfd645f07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184779004 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_post_trans.2184779004
Directory /workspace/0.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all_with_rand_reset.3000529600
Short name T160
Test name
Test status
Simulation time 151984057633 ps
CPU time 325.27 seconds
Started May 30 02:09:40 PM PDT 24
Finished May 30 02:15:07 PM PDT 24
Peak memory 286188 kb
Host smart-78c2f26f-e717-4f8a-b8af-10ac7c7ccbd9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3000529600 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_stress_all_with_rand_reset.3000529600
Directory /workspace/0.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.lc_ctrl_volatile_unlock_smoke.489415779
Short name T286
Test name
Test status
Simulation time 32396664 ps
CPU time 0.92 seconds
Started May 30 02:09:39 PM PDT 24
Finished May 30 02:09:41 PM PDT 24
Peak memory 211500 kb
Host smart-f7599859-7c57-4411-84f4-e044c4137401
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489415779 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctr
l_volatile_unlock_smoke.489415779
Directory /workspace/0.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_alert_test.1760854883
Short name T394
Test name
Test status
Simulation time 23002200 ps
CPU time 0.96 seconds
Started May 30 02:09:56 PM PDT 24
Finished May 30 02:09:58 PM PDT 24
Peak memory 209528 kb
Host smart-8266a15f-8056-40d1-a914-07861e21d437
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760854883 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_alert_test.1760854883
Directory /workspace/1.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.lc_ctrl_errors.4124493856
Short name T391
Test name
Test status
Simulation time 1454267755 ps
CPU time 16.16 seconds
Started May 30 02:09:40 PM PDT 24
Finished May 30 02:09:57 PM PDT 24
Peak memory 217976 kb
Host smart-4bd5e0c4-8a12-4622-a40d-4f63daf87418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124493856 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_errors.4124493856
Directory /workspace/1.lc_ctrl_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_access.1338156587
Short name T480
Test name
Test status
Simulation time 222838099 ps
CPU time 3.97 seconds
Started May 30 02:09:49 PM PDT 24
Finished May 30 02:09:54 PM PDT 24
Peak memory 217096 kb
Host smart-367653c8-ba23-4df6-b9ba-bc0e2f2494bf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338156587 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_access.1338156587
Directory /workspace/1.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_errors.937127371
Short name T97
Test name
Test status
Simulation time 3132316464 ps
CPU time 40.41 seconds
Started May 30 02:09:54 PM PDT 24
Finished May 30 02:10:36 PM PDT 24
Peak memory 219120 kb
Host smart-ce24caa9-179b-4cc6-94bc-c3de68ecb279
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937127371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_err
ors.937127371
Directory /workspace/1.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_priority.4114345526
Short name T346
Test name
Test status
Simulation time 777341596 ps
CPU time 4 seconds
Started May 30 02:09:58 PM PDT 24
Finished May 30 02:10:03 PM PDT 24
Peak memory 217244 kb
Host smart-7ad77b1f-ade2-4d63-bd07-07a19ccac9fe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114345526 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_priority.4
114345526
Directory /workspace/1.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_prog_failure.2545891262
Short name T441
Test name
Test status
Simulation time 319110509 ps
CPU time 8.57 seconds
Started May 30 02:09:50 PM PDT 24
Finished May 30 02:10:00 PM PDT 24
Peak memory 217980 kb
Host smart-4c0b6f37-257e-486a-b58b-a833346effe9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545891262 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag
_prog_failure.2545891262
Directory /workspace/1.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_regwen_during_op.1983496113
Short name T794
Test name
Test status
Simulation time 5956488698 ps
CPU time 38.91 seconds
Started May 30 02:09:54 PM PDT 24
Finished May 30 02:10:34 PM PDT 24
Peak memory 217740 kb
Host smart-b1313737-2e96-45a6-ad58-02f5f37f0926
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983496113 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_regwen_during_op.1983496113
Directory /workspace/1.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_smoke.1967125695
Short name T788
Test name
Test status
Simulation time 481097382 ps
CPU time 4.4 seconds
Started May 30 02:09:38 PM PDT 24
Finished May 30 02:09:44 PM PDT 24
Peak memory 217684 kb
Host smart-fc495da8-01cd-48b9-8804-cd5dc1cab5c6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967125695 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_smoke.
1967125695
Directory /workspace/1.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_failure.211042993
Short name T278
Test name
Test status
Simulation time 1501671096 ps
CPU time 36.82 seconds
Started May 30 02:09:39 PM PDT 24
Finished May 30 02:10:17 PM PDT 24
Peak memory 275588 kb
Host smart-bf82067a-e144-42e4-bdfb-6c3d0db4afc2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211042993 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag
_state_failure.211042993
Directory /workspace/1.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_post_trans.3433156004
Short name T343
Test name
Test status
Simulation time 619753934 ps
CPU time 5.95 seconds
Started May 30 02:09:52 PM PDT 24
Finished May 30 02:09:59 PM PDT 24
Peak memory 221720 kb
Host smart-07bc8135-0fa0-4773-9857-013905e791de
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433156004 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_state_post_trans.3433156004
Directory /workspace/1.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_prog_failure.1367187858
Short name T598
Test name
Test status
Simulation time 48284167 ps
CPU time 2.92 seconds
Started May 30 02:09:39 PM PDT 24
Finished May 30 02:09:44 PM PDT 24
Peak memory 218052 kb
Host smart-2478d090-f9a3-424c-b878-516de4e5f49f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367187858 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_prog_failure.1367187858
Directory /workspace/1.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_regwen_during_op.1528618807
Short name T496
Test name
Test status
Simulation time 2664068780 ps
CPU time 27.44 seconds
Started May 30 02:09:39 PM PDT 24
Finished May 30 02:10:08 PM PDT 24
Peak memory 214956 kb
Host smart-92e36d1d-b040-4a54-bb49-4bc4b5eb8528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528618807 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_regwen_during_op.1528618807
Directory /workspace/1.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_cm.1644958209
Short name T122
Test name
Test status
Simulation time 128429396 ps
CPU time 22.87 seconds
Started May 30 02:09:54 PM PDT 24
Finished May 30 02:10:18 PM PDT 24
Peak memory 282048 kb
Host smart-deb593b0-23cf-47ce-91d3-1943143f4b8e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644958209 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_cm.1644958209
Directory /workspace/1.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_mubi.1868171124
Short name T402
Test name
Test status
Simulation time 1638154264 ps
CPU time 18.21 seconds
Started May 30 02:09:50 PM PDT 24
Finished May 30 02:10:09 PM PDT 24
Peak memory 226156 kb
Host smart-d07acff3-8ebf-4520-b43d-66d4b37c8d75
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868171124 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_mubi.1868171124
Directory /workspace/1.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_digest.2560116380
Short name T260
Test name
Test status
Simulation time 483962109 ps
CPU time 18.48 seconds
Started May 30 02:09:50 PM PDT 24
Finished May 30 02:10:10 PM PDT 24
Peak memory 217984 kb
Host smart-358dbbc7-4e54-4536-9c1e-501140733b52
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560116380 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_di
gest.2560116380
Directory /workspace/1.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_mux.2739834359
Short name T237
Test name
Test status
Simulation time 4336719514 ps
CPU time 8.78 seconds
Started May 30 02:09:55 PM PDT 24
Finished May 30 02:10:05 PM PDT 24
Peak memory 218140 kb
Host smart-7d01354d-7ebc-4a9b-8407-0b481b0e5302
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739834359 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_mux.2
739834359
Directory /workspace/1.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/1.lc_ctrl_security_escalation.2268465307
Short name T68
Test name
Test status
Simulation time 234717691 ps
CPU time 6.2 seconds
Started May 30 02:09:38 PM PDT 24
Finished May 30 02:09:46 PM PDT 24
Peak memory 218104 kb
Host smart-519fec9d-5853-4e99-beec-09ad6731b438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268465307 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_security_escalation.2268465307
Directory /workspace/1.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/1.lc_ctrl_smoke.403709977
Short name T108
Test name
Test status
Simulation time 69440313 ps
CPU time 1.35 seconds
Started May 30 02:09:41 PM PDT 24
Finished May 30 02:09:44 PM PDT 24
Peak memory 213576 kb
Host smart-0b0fbd4c-8413-4d73-a6f1-9ba6fe75b43f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403709977 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_smoke.403709977
Directory /workspace/1.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_failure.1747537730
Short name T628
Test name
Test status
Simulation time 5229115080 ps
CPU time 25.37 seconds
Started May 30 02:09:40 PM PDT 24
Finished May 30 02:10:07 PM PDT 24
Peak memory 250996 kb
Host smart-fdbf829f-99eb-41c8-87eb-97a606edc758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747537730 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_failure.1747537730
Directory /workspace/1.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_post_trans.1921025082
Short name T110
Test name
Test status
Simulation time 441037345 ps
CPU time 8.54 seconds
Started May 30 02:09:41 PM PDT 24
Finished May 30 02:09:51 PM PDT 24
Peak memory 246780 kb
Host smart-ccca8bd2-9f28-42c6-b6b7-0ffb8187572b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921025082 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_post_trans.1921025082
Directory /workspace/1.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_stress_all.3738080276
Short name T667
Test name
Test status
Simulation time 10056076417 ps
CPU time 90.17 seconds
Started May 30 02:09:50 PM PDT 24
Finished May 30 02:11:22 PM PDT 24
Peak memory 283752 kb
Host smart-59f258c3-bc65-4b90-85cc-a9ff6aeac578
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738080276 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.lc_ctrl_stress_all.3738080276
Directory /workspace/1.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.lc_ctrl_stress_all_with_rand_reset.673096606
Short name T683
Test name
Test status
Simulation time 29910571861 ps
CPU time 1021.72 seconds
Started May 30 02:09:49 PM PDT 24
Finished May 30 02:26:52 PM PDT 24
Peak memory 316080 kb
Host smart-3e94e3ba-84ed-4f12-bc6b-95661ea4d392
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=673096606 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_stress_all_with_rand_reset.673096606
Directory /workspace/1.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.lc_ctrl_volatile_unlock_smoke.2025607708
Short name T570
Test name
Test status
Simulation time 28714136 ps
CPU time 0.78 seconds
Started May 30 02:09:39 PM PDT 24
Finished May 30 02:09:41 PM PDT 24
Peak memory 208420 kb
Host smart-86becac0-6c5e-436d-977c-5f13b5cbbb1c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025607708 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ct
rl_volatile_unlock_smoke.2025607708
Directory /workspace/1.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_errors.3669773882
Short name T223
Test name
Test status
Simulation time 2312484161 ps
CPU time 17.62 seconds
Started May 30 02:10:23 PM PDT 24
Finished May 30 02:10:42 PM PDT 24
Peak memory 218060 kb
Host smart-ce2c91c9-c4e9-4cbd-832d-cdc9f2698e25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669773882 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_errors.3669773882
Directory /workspace/10.lc_ctrl_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_access.2466796550
Short name T33
Test name
Test status
Simulation time 221899922 ps
CPU time 6.54 seconds
Started May 30 02:10:24 PM PDT 24
Finished May 30 02:10:32 PM PDT 24
Peak memory 209556 kb
Host smart-50ca65e1-144e-4641-b117-c29756be7e0f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466796550 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_access.2466796550
Directory /workspace/10.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_errors.118669720
Short name T437
Test name
Test status
Simulation time 5348548272 ps
CPU time 41.34 seconds
Started May 30 02:10:29 PM PDT 24
Finished May 30 02:11:11 PM PDT 24
Peak memory 218724 kb
Host smart-9f23fd10-6fe6-4eba-9f9a-0d878e191aac
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118669720 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_er
rors.118669720
Directory /workspace/10.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_prog_failure.2134404062
Short name T341
Test name
Test status
Simulation time 347052441 ps
CPU time 3.85 seconds
Started May 30 02:10:24 PM PDT 24
Finished May 30 02:10:29 PM PDT 24
Peak memory 217920 kb
Host smart-76ad9349-2849-485a-a315-89d877a8587a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134404062 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jta
g_prog_failure.2134404062
Directory /workspace/10.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_smoke.536917485
Short name T819
Test name
Test status
Simulation time 312303119 ps
CPU time 4.86 seconds
Started May 30 02:10:38 PM PDT 24
Finished May 30 02:10:44 PM PDT 24
Peak memory 217684 kb
Host smart-96d6e23a-2b2b-4ae1-80cc-d13c6b97fd03
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536917485 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_smoke.
536917485
Directory /workspace/10.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_failure.2420969567
Short name T468
Test name
Test status
Simulation time 1173109009 ps
CPU time 30.13 seconds
Started May 30 02:10:24 PM PDT 24
Finished May 30 02:10:55 PM PDT 24
Peak memory 251056 kb
Host smart-04410983-819a-4ad8-b7cd-3c47baf0fc32
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420969567 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jt
ag_state_failure.2420969567
Directory /workspace/10.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_post_trans.3939895591
Short name T18
Test name
Test status
Simulation time 1685698667 ps
CPU time 18.26 seconds
Started May 30 02:10:24 PM PDT 24
Finished May 30 02:10:44 PM PDT 24
Peak memory 250952 kb
Host smart-914d68a0-f6a7-40bb-bf24-e77f2d5594c5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939895591 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl
_jtag_state_post_trans.3939895591
Directory /workspace/10.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_prog_failure.4258929997
Short name T185
Test name
Test status
Simulation time 68165444 ps
CPU time 2.62 seconds
Started May 30 02:10:24 PM PDT 24
Finished May 30 02:10:28 PM PDT 24
Peak memory 218124 kb
Host smart-f511b7aa-c34c-4119-9b0d-c1fad2bf1d51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258929997 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_prog_failure.4258929997
Directory /workspace/10.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_mubi.2238336235
Short name T514
Test name
Test status
Simulation time 983525161 ps
CPU time 14.63 seconds
Started May 30 02:10:24 PM PDT 24
Finished May 30 02:10:40 PM PDT 24
Peak memory 218992 kb
Host smart-82dd3ab6-4ed6-42a4-b99d-d5745318efe2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238336235 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_mubi.2238336235
Directory /workspace/10.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_digest.1871477794
Short name T720
Test name
Test status
Simulation time 230308981 ps
CPU time 10.18 seconds
Started May 30 02:10:35 PM PDT 24
Finished May 30 02:10:46 PM PDT 24
Peak memory 217956 kb
Host smart-5bb64cb5-3ab4-49ed-9092-47a3201c9bb9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871477794 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_d
igest.1871477794
Directory /workspace/10.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_mux.1764274351
Short name T791
Test name
Test status
Simulation time 255925981 ps
CPU time 7.31 seconds
Started May 30 02:10:25 PM PDT 24
Finished May 30 02:10:34 PM PDT 24
Peak memory 218052 kb
Host smart-87f801a4-9578-4952-b985-da663b5303d3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764274351 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_mux.
1764274351
Directory /workspace/10.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/10.lc_ctrl_security_escalation.3406270146
Short name T816
Test name
Test status
Simulation time 446259983 ps
CPU time 8.66 seconds
Started May 30 02:10:33 PM PDT 24
Finished May 30 02:10:42 PM PDT 24
Peak memory 218104 kb
Host smart-42589115-8ebd-45f3-9451-6649a632add6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406270146 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_security_escalation.3406270146
Directory /workspace/10.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/10.lc_ctrl_smoke.4276729414
Short name T89
Test name
Test status
Simulation time 29433302 ps
CPU time 2.4 seconds
Started May 30 02:10:24 PM PDT 24
Finished May 30 02:10:28 PM PDT 24
Peak memory 214224 kb
Host smart-0ca4e1d1-d8cd-4fd8-bd5a-250f1378ac5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276729414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_smoke.4276729414
Directory /workspace/10.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_failure.1214672525
Short name T651
Test name
Test status
Simulation time 1284394868 ps
CPU time 24.47 seconds
Started May 30 02:10:35 PM PDT 24
Finished May 30 02:11:00 PM PDT 24
Peak memory 251008 kb
Host smart-b706361c-4364-4dda-8a60-03ceb2423727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214672525 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_failure.1214672525
Directory /workspace/10.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_post_trans.3396445744
Short name T736
Test name
Test status
Simulation time 261382295 ps
CPU time 2.78 seconds
Started May 30 02:10:33 PM PDT 24
Finished May 30 02:10:36 PM PDT 24
Peak memory 226424 kb
Host smart-595594f0-1d47-4b2d-bf6d-478de11782b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396445744 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_post_trans.3396445744
Directory /workspace/10.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all.3661327345
Short name T336
Test name
Test status
Simulation time 15258474209 ps
CPU time 471.11 seconds
Started May 30 02:10:32 PM PDT 24
Finished May 30 02:18:24 PM PDT 24
Peak memory 270848 kb
Host smart-f122ddd1-a9bc-496b-87cb-ec350cd66e2b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661327345 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.lc_ctrl_stress_all.3661327345
Directory /workspace/10.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.lc_ctrl_volatile_unlock_smoke.97654572
Short name T625
Test name
Test status
Simulation time 33073595 ps
CPU time 0.8 seconds
Started May 30 02:10:25 PM PDT 24
Finished May 30 02:10:27 PM PDT 24
Peak memory 208452 kb
Host smart-0d17d9e9-bcf2-41fe-9cc5-c066832e96b8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97654572 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vol
atile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctr
l_volatile_unlock_smoke.97654572
Directory /workspace/10.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_alert_test.4171137975
Short name T522
Test name
Test status
Simulation time 44553379 ps
CPU time 0.91 seconds
Started May 30 02:10:38 PM PDT 24
Finished May 30 02:10:40 PM PDT 24
Peak memory 208668 kb
Host smart-14d07cf2-d58d-476b-a933-8d0cb54cdb46
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171137975 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_alert_test.4171137975
Directory /workspace/11.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.lc_ctrl_errors.3302550971
Short name T519
Test name
Test status
Simulation time 1300172812 ps
CPU time 12.58 seconds
Started May 30 02:10:38 PM PDT 24
Finished May 30 02:10:52 PM PDT 24
Peak memory 218020 kb
Host smart-5cbe10a5-d848-47a5-aff0-898dfc217077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302550971 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_errors.3302550971
Directory /workspace/11.lc_ctrl_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_access.3971475718
Short name T642
Test name
Test status
Simulation time 1845453886 ps
CPU time 20.94 seconds
Started May 30 02:10:40 PM PDT 24
Finished May 30 02:11:02 PM PDT 24
Peak memory 209464 kb
Host smart-aa8cec46-4dbe-462d-bc88-3b359fc358da
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971475718 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_access.3971475718
Directory /workspace/11.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_errors.2765038678
Short name T434
Test name
Test status
Simulation time 1941317440 ps
CPU time 51.2 seconds
Started May 30 02:10:36 PM PDT 24
Finished May 30 02:11:28 PM PDT 24
Peak memory 217956 kb
Host smart-affaad25-5c3d-4220-8f4d-2294f445553c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765038678 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_e
rrors.2765038678
Directory /workspace/11.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_prog_failure.457372452
Short name T264
Test name
Test status
Simulation time 932868176 ps
CPU time 25.71 seconds
Started May 30 02:10:38 PM PDT 24
Finished May 30 02:11:05 PM PDT 24
Peak memory 217996 kb
Host smart-f6e58524-99e4-4323-92e2-74c3508349fc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457372452 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag
_prog_failure.457372452
Directory /workspace/11.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_smoke.1434351552
Short name T775
Test name
Test status
Simulation time 6954410311 ps
CPU time 10.74 seconds
Started May 30 02:10:42 PM PDT 24
Finished May 30 02:10:54 PM PDT 24
Peak memory 217792 kb
Host smart-2b8dfc40-2f81-497d-a23a-ca25709271b4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434351552 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_smoke
.1434351552
Directory /workspace/11.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_failure.3067543532
Short name T691
Test name
Test status
Simulation time 775494996 ps
CPU time 36.56 seconds
Started May 30 02:10:37 PM PDT 24
Finished May 30 02:11:15 PM PDT 24
Peak memory 250936 kb
Host smart-2470bc50-0a7b-42b1-bdbe-7297e240ff80
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067543532 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jt
ag_state_failure.3067543532
Directory /workspace/11.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_post_trans.1544693600
Short name T536
Test name
Test status
Simulation time 1562593693 ps
CPU time 15.37 seconds
Started May 30 02:10:37 PM PDT 24
Finished May 30 02:10:54 PM PDT 24
Peak memory 250996 kb
Host smart-cedb970f-ef11-4fdd-8c9b-4944b350083e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544693600 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl
_jtag_state_post_trans.1544693600
Directory /workspace/11.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_prog_failure.4047570866
Short name T117
Test name
Test status
Simulation time 324257834 ps
CPU time 4.35 seconds
Started May 30 02:10:38 PM PDT 24
Finished May 30 02:10:44 PM PDT 24
Peak memory 218032 kb
Host smart-0e589419-253c-4a79-9927-33dcecf4b682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047570866 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_prog_failure.4047570866
Directory /workspace/11.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_mubi.4054960706
Short name T711
Test name
Test status
Simulation time 2180768492 ps
CPU time 13.56 seconds
Started May 30 02:10:37 PM PDT 24
Finished May 30 02:10:52 PM PDT 24
Peak memory 226212 kb
Host smart-82e85197-b9a1-48ee-8255-a52a59b73b9b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054960706 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_mubi.4054960706
Directory /workspace/11.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_digest.3638098161
Short name T569
Test name
Test status
Simulation time 964180125 ps
CPU time 11.3 seconds
Started May 30 02:10:38 PM PDT 24
Finished May 30 02:10:51 PM PDT 24
Peak memory 226036 kb
Host smart-e99b7456-5cd3-4d0e-8eed-9227b7388275
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638098161 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_d
igest.3638098161
Directory /workspace/11.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_mux.3196329961
Short name T841
Test name
Test status
Simulation time 2513276550 ps
CPU time 13.36 seconds
Started May 30 02:10:36 PM PDT 24
Finished May 30 02:10:50 PM PDT 24
Peak memory 218088 kb
Host smart-ca01a847-3e8c-405d-9468-aa679148e80b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196329961 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_mux.
3196329961
Directory /workspace/11.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/11.lc_ctrl_security_escalation.1994497694
Short name T746
Test name
Test status
Simulation time 2107761925 ps
CPU time 7.77 seconds
Started May 30 02:10:35 PM PDT 24
Finished May 30 02:10:44 PM PDT 24
Peak memory 218100 kb
Host smart-ad1d7c3f-a0e9-4e21-b3d0-f2b50cb468a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1994497694 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_security_escalation.1994497694
Directory /workspace/11.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/11.lc_ctrl_smoke.2059505161
Short name T810
Test name
Test status
Simulation time 275897760 ps
CPU time 3.09 seconds
Started May 30 02:10:25 PM PDT 24
Finished May 30 02:10:29 PM PDT 24
Peak memory 217792 kb
Host smart-3eaa9cd6-0eb7-4d96-8bad-b1e8170fdaec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059505161 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_smoke.2059505161
Directory /workspace/11.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_failure.1336594230
Short name T537
Test name
Test status
Simulation time 1214505166 ps
CPU time 26.41 seconds
Started May 30 02:10:33 PM PDT 24
Finished May 30 02:11:00 PM PDT 24
Peak memory 250900 kb
Host smart-efbdb823-6a10-4cc5-8baf-6dfb073dcef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336594230 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_failure.1336594230
Directory /workspace/11.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_post_trans.3296863090
Short name T433
Test name
Test status
Simulation time 231009128 ps
CPU time 7.08 seconds
Started May 30 02:10:38 PM PDT 24
Finished May 30 02:10:46 PM PDT 24
Peak memory 250592 kb
Host smart-a16dad88-e798-40e9-9d95-cd3b6906420b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296863090 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_post_trans.3296863090
Directory /workspace/11.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_stress_all.2843316811
Short name T586
Test name
Test status
Simulation time 7136752392 ps
CPU time 140.14 seconds
Started May 30 02:10:37 PM PDT 24
Finished May 30 02:12:58 PM PDT 24
Peak memory 283404 kb
Host smart-3bdb3e3f-58b1-4770-af77-76f99b9a008e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843316811 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.lc_ctrl_stress_all.2843316811
Directory /workspace/11.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.lc_ctrl_stress_all_with_rand_reset.2583712455
Short name T164
Test name
Test status
Simulation time 289107912182 ps
CPU time 720.34 seconds
Started May 30 02:10:37 PM PDT 24
Finished May 30 02:22:39 PM PDT 24
Peak memory 561620 kb
Host smart-32939fdd-38b2-4626-aada-2969a76b7700
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2583712455 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_stress_all_with_rand_reset.2583712455
Directory /workspace/11.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.lc_ctrl_volatile_unlock_smoke.3147456921
Short name T754
Test name
Test status
Simulation time 68767514 ps
CPU time 0.83 seconds
Started May 30 02:10:32 PM PDT 24
Finished May 30 02:10:34 PM PDT 24
Peak memory 208600 kb
Host smart-c9c31a1f-9b99-482f-b6ff-30f5fd623ea4
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147456921 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_c
trl_volatile_unlock_smoke.3147456921
Directory /workspace/11.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_alert_test.3205464456
Short name T738
Test name
Test status
Simulation time 59245728 ps
CPU time 1.18 seconds
Started May 30 02:10:38 PM PDT 24
Finished May 30 02:10:40 PM PDT 24
Peak memory 208684 kb
Host smart-4cacfdf4-2a19-4412-aef3-ec711473739f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205464456 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_alert_test.3205464456
Directory /workspace/12.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.lc_ctrl_errors.1841242567
Short name T781
Test name
Test status
Simulation time 387896668 ps
CPU time 12.84 seconds
Started May 30 02:10:37 PM PDT 24
Finished May 30 02:10:51 PM PDT 24
Peak memory 217988 kb
Host smart-87da8777-6c57-4268-9488-4fdb324167c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841242567 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_errors.1841242567
Directory /workspace/12.lc_ctrl_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_access.2818228249
Short name T32
Test name
Test status
Simulation time 3409666625 ps
CPU time 5.12 seconds
Started May 30 02:10:42 PM PDT 24
Finished May 30 02:10:48 PM PDT 24
Peak memory 217612 kb
Host smart-93f71f26-ad59-4ddb-87df-152fd681ae97
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818228249 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_access.2818228249
Directory /workspace/12.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_errors.1397099711
Short name T252
Test name
Test status
Simulation time 1635333957 ps
CPU time 26.48 seconds
Started May 30 02:10:43 PM PDT 24
Finished May 30 02:11:10 PM PDT 24
Peak memory 218036 kb
Host smart-87ffdf3a-7d15-4434-8c36-d5a3265ded7b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397099711 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_e
rrors.1397099711
Directory /workspace/12.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_prog_failure.3905218015
Short name T851
Test name
Test status
Simulation time 2952390223 ps
CPU time 21.43 seconds
Started May 30 02:10:38 PM PDT 24
Finished May 30 02:11:01 PM PDT 24
Peak memory 217988 kb
Host smart-28427db9-42b0-45f2-8941-422d0efec553
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905218015 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jta
g_prog_failure.3905218015
Directory /workspace/12.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_smoke.2700966675
Short name T86
Test name
Test status
Simulation time 197177483 ps
CPU time 3.37 seconds
Started May 30 02:10:37 PM PDT 24
Finished May 30 02:10:41 PM PDT 24
Peak memory 217696 kb
Host smart-d7e8213b-ce14-45d5-a0dd-6dcccd5548d0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700966675 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_smoke
.2700966675
Directory /workspace/12.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_failure.3187624045
Short name T452
Test name
Test status
Simulation time 7555145863 ps
CPU time 114.09 seconds
Started May 30 02:10:37 PM PDT 24
Finished May 30 02:12:32 PM PDT 24
Peak memory 267404 kb
Host smart-c44e492c-ac41-4608-8e30-30139578b19e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187624045 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jt
ag_state_failure.3187624045
Directory /workspace/12.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_post_trans.1997465621
Short name T474
Test name
Test status
Simulation time 1602244782 ps
CPU time 16.93 seconds
Started May 30 02:10:40 PM PDT 24
Finished May 30 02:10:58 PM PDT 24
Peak memory 250564 kb
Host smart-96e68c17-3d25-49e1-a3d4-45e0f8a66c9b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997465621 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl
_jtag_state_post_trans.1997465621
Directory /workspace/12.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_prog_failure.2454239298
Short name T319
Test name
Test status
Simulation time 269333477 ps
CPU time 3.03 seconds
Started May 30 02:10:36 PM PDT 24
Finished May 30 02:10:39 PM PDT 24
Peak memory 218040 kb
Host smart-33f0ba37-8e9f-448e-bd5d-ef07b9c82b76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454239298 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_prog_failure.2454239298
Directory /workspace/12.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_mubi.3133477469
Short name T835
Test name
Test status
Simulation time 1327752783 ps
CPU time 15.98 seconds
Started May 30 02:10:39 PM PDT 24
Finished May 30 02:10:56 PM PDT 24
Peak memory 218228 kb
Host smart-764abbf2-89e8-494b-86a9-10b541463c67
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133477469 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_mubi.3133477469
Directory /workspace/12.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_digest.1851569951
Short name T401
Test name
Test status
Simulation time 396835178 ps
CPU time 9.88 seconds
Started May 30 02:10:39 PM PDT 24
Finished May 30 02:10:50 PM PDT 24
Peak memory 217924 kb
Host smart-de8ba3dc-e1e5-4782-8a99-56fe7f6e75eb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851569951 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_d
igest.1851569951
Directory /workspace/12.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_mux.701395726
Short name T227
Test name
Test status
Simulation time 1171795268 ps
CPU time 9.26 seconds
Started May 30 02:10:39 PM PDT 24
Finished May 30 02:10:49 PM PDT 24
Peak memory 218076 kb
Host smart-e202f0db-90d9-4482-89a3-fba727e14224
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701395726 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_mux.701395726
Directory /workspace/12.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/12.lc_ctrl_security_escalation.2151570412
Short name T408
Test name
Test status
Simulation time 249885817 ps
CPU time 7.33 seconds
Started May 30 02:10:36 PM PDT 24
Finished May 30 02:10:44 PM PDT 24
Peak memory 218056 kb
Host smart-57d97374-21dd-47cc-8186-1b26bb816e12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151570412 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_security_escalation.2151570412
Directory /workspace/12.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/12.lc_ctrl_smoke.828496308
Short name T390
Test name
Test status
Simulation time 101293106 ps
CPU time 3.73 seconds
Started May 30 02:10:38 PM PDT 24
Finished May 30 02:10:43 PM PDT 24
Peak memory 217860 kb
Host smart-325d61af-3e13-4dad-96fd-99b84986ebd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828496308 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_smoke.828496308
Directory /workspace/12.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_failure.863694011
Short name T188
Test name
Test status
Simulation time 325970739 ps
CPU time 25.52 seconds
Started May 30 02:10:37 PM PDT 24
Finished May 30 02:11:03 PM PDT 24
Peak memory 250928 kb
Host smart-ed5e6577-9759-464a-99fd-95d7b0dafffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863694011 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_failure.863694011
Directory /workspace/12.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_post_trans.3106338182
Short name T389
Test name
Test status
Simulation time 168765508 ps
CPU time 9.48 seconds
Started May 30 02:10:38 PM PDT 24
Finished May 30 02:10:49 PM PDT 24
Peak memory 250956 kb
Host smart-0982d1d9-5a11-4df9-83c2-8aa7daaf70c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106338182 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_post_trans.3106338182
Directory /workspace/12.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_volatile_unlock_smoke.1634946800
Short name T508
Test name
Test status
Simulation time 20646557 ps
CPU time 0.83 seconds
Started May 30 02:10:40 PM PDT 24
Finished May 30 02:10:42 PM PDT 24
Peak memory 208752 kb
Host smart-6122af87-278c-4bce-8522-f4b1c8bd7097
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634946800 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_c
trl_volatile_unlock_smoke.1634946800
Directory /workspace/12.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_alert_test.361648751
Short name T641
Test name
Test status
Simulation time 92876214 ps
CPU time 0.97 seconds
Started May 30 02:10:57 PM PDT 24
Finished May 30 02:11:00 PM PDT 24
Peak memory 208708 kb
Host smart-298453b8-96e7-4802-9cb8-3ce1fc4388f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361648751 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_alert_test.361648751
Directory /workspace/13.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.lc_ctrl_errors.52401474
Short name T347
Test name
Test status
Simulation time 206023721 ps
CPU time 11.05 seconds
Started May 30 02:10:52 PM PDT 24
Finished May 30 02:11:04 PM PDT 24
Peak memory 218112 kb
Host smart-04b1ad4f-49f9-40c5-96dd-1719d452e6ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52401474 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_errors.52401474
Directory /workspace/13.lc_ctrl_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_access.224451219
Short name T527
Test name
Test status
Simulation time 1746533569 ps
CPU time 11.83 seconds
Started May 30 02:10:52 PM PDT 24
Finished May 30 02:11:04 PM PDT 24
Peak memory 209564 kb
Host smart-2956b209-d17d-4f26-b7ca-e8a31ee3a278
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224451219 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_access.224451219
Directory /workspace/13.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_errors.1971059493
Short name T797
Test name
Test status
Simulation time 11369819260 ps
CPU time 40.87 seconds
Started May 30 02:10:52 PM PDT 24
Finished May 30 02:11:34 PM PDT 24
Peak memory 218052 kb
Host smart-06181fea-c4b4-4454-8901-c0359467da57
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971059493 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_e
rrors.1971059493
Directory /workspace/13.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_prog_failure.2444897272
Short name T789
Test name
Test status
Simulation time 134765527 ps
CPU time 3.21 seconds
Started May 30 02:10:53 PM PDT 24
Finished May 30 02:10:57 PM PDT 24
Peak memory 218136 kb
Host smart-45a1757a-9b78-406f-afb3-7e3c038fb448
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444897272 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jta
g_prog_failure.2444897272
Directory /workspace/13.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_smoke.1775562957
Short name T6
Test name
Test status
Simulation time 612643548 ps
CPU time 9.17 seconds
Started May 30 02:10:51 PM PDT 24
Finished May 30 02:11:01 PM PDT 24
Peak memory 217700 kb
Host smart-de091fa3-b057-4ad7-a0a6-210ef6e2bcf7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775562957 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_smoke
.1775562957
Directory /workspace/13.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_failure.1579429564
Short name T631
Test name
Test status
Simulation time 11259207133 ps
CPU time 107.57 seconds
Started May 30 02:10:54 PM PDT 24
Finished May 30 02:12:42 PM PDT 24
Peak memory 283712 kb
Host smart-a24ac8cc-cd7f-4592-93b9-e02d5fc90fd9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579429564 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jt
ag_state_failure.1579429564
Directory /workspace/13.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_post_trans.1957381011
Short name T19
Test name
Test status
Simulation time 8665491003 ps
CPU time 16.44 seconds
Started May 30 02:10:52 PM PDT 24
Finished May 30 02:11:10 PM PDT 24
Peak memory 249828 kb
Host smart-813cb4c3-e68d-4047-90b6-b6382310fe51
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957381011 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl
_jtag_state_post_trans.1957381011
Directory /workspace/13.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_prog_failure.1779552957
Short name T276
Test name
Test status
Simulation time 41935199 ps
CPU time 2.25 seconds
Started May 30 02:10:55 PM PDT 24
Finished May 30 02:10:58 PM PDT 24
Peak memory 217992 kb
Host smart-f3235dbd-d292-4c71-9fb3-18671abc4e90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779552957 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_prog_failure.1779552957
Directory /workspace/13.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_mubi.3667943263
Short name T665
Test name
Test status
Simulation time 378866489 ps
CPU time 16.6 seconds
Started May 30 02:10:53 PM PDT 24
Finished May 30 02:11:11 PM PDT 24
Peak memory 226152 kb
Host smart-cd1e5a56-5ae3-4df0-ae36-b06fdc31e515
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667943263 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_mubi.3667943263
Directory /workspace/13.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_digest.2287754672
Short name T849
Test name
Test status
Simulation time 371058369 ps
CPU time 14.31 seconds
Started May 30 02:10:53 PM PDT 24
Finished May 30 02:11:08 PM PDT 24
Peak memory 226092 kb
Host smart-1dcae880-b9a8-448f-af6d-ddfd5f686565
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287754672 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_d
igest.2287754672
Directory /workspace/13.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_mux.543418040
Short name T823
Test name
Test status
Simulation time 1010292286 ps
CPU time 9.88 seconds
Started May 30 02:10:57 PM PDT 24
Finished May 30 02:11:08 PM PDT 24
Peak memory 218052 kb
Host smart-63acc51e-2f3b-4594-b6ee-5b39803f8296
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543418040 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_mux.543418040
Directory /workspace/13.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/13.lc_ctrl_security_escalation.3804314390
Short name T379
Test name
Test status
Simulation time 187641921 ps
CPU time 6.23 seconds
Started May 30 02:10:53 PM PDT 24
Finished May 30 02:11:00 PM PDT 24
Peak memory 218128 kb
Host smart-60f848b9-2f9f-42d9-ad23-faad8a60caf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804314390 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_security_escalation.3804314390
Directory /workspace/13.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/13.lc_ctrl_smoke.1093657171
Short name T564
Test name
Test status
Simulation time 224320257 ps
CPU time 3.28 seconds
Started May 30 02:10:39 PM PDT 24
Finished May 30 02:10:43 PM PDT 24
Peak memory 217716 kb
Host smart-c4e2ce3e-cd1a-4952-ab68-0e6198e7bc34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093657171 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_smoke.1093657171
Directory /workspace/13.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_failure.2993929235
Short name T637
Test name
Test status
Simulation time 875406613 ps
CPU time 20.76 seconds
Started May 30 02:10:39 PM PDT 24
Finished May 30 02:11:01 PM PDT 24
Peak memory 251024 kb
Host smart-3fcbd3c1-dde2-433a-800f-0bee34dcfa69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993929235 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_failure.2993929235
Directory /workspace/13.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_post_trans.1662183895
Short name T107
Test name
Test status
Simulation time 545861880 ps
CPU time 6.43 seconds
Started May 30 02:10:53 PM PDT 24
Finished May 30 02:11:01 PM PDT 24
Peak memory 246780 kb
Host smart-4dcc529c-45af-4ca4-ad8b-0ac9cfd4a39c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662183895 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_post_trans.1662183895
Directory /workspace/13.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all.1938900201
Short name T526
Test name
Test status
Simulation time 3324611198 ps
CPU time 66.42 seconds
Started May 30 02:10:54 PM PDT 24
Finished May 30 02:12:01 PM PDT 24
Peak memory 226500 kb
Host smart-0aae59bc-937a-4e3f-ae04-a5ab4d2892d1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938900201 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.lc_ctrl_stress_all.1938900201
Directory /workspace/13.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.lc_ctrl_volatile_unlock_smoke.899541602
Short name T301
Test name
Test status
Simulation time 12728015 ps
CPU time 0.82 seconds
Started May 30 02:10:39 PM PDT 24
Finished May 30 02:10:41 PM PDT 24
Peak memory 208572 kb
Host smart-b6d78438-b39e-4072-9d0d-3ffa5a87f1d2
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899541602 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ct
rl_volatile_unlock_smoke.899541602
Directory /workspace/13.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_alert_test.2955010092
Short name T320
Test name
Test status
Simulation time 27828540 ps
CPU time 1.03 seconds
Started May 30 02:10:54 PM PDT 24
Finished May 30 02:10:57 PM PDT 24
Peak memory 209496 kb
Host smart-ad817746-2c02-46f4-91ff-d621801ad69f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955010092 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_alert_test.2955010092
Directory /workspace/14.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.lc_ctrl_errors.3521546839
Short name T592
Test name
Test status
Simulation time 845580961 ps
CPU time 29 seconds
Started May 30 02:10:58 PM PDT 24
Finished May 30 02:11:28 PM PDT 24
Peak memory 217960 kb
Host smart-2f9f05f0-5813-4f9c-9b5c-a00d33f822b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521546839 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_errors.3521546839
Directory /workspace/14.lc_ctrl_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_access.2013342469
Short name T387
Test name
Test status
Simulation time 436609551 ps
CPU time 5.93 seconds
Started May 30 02:10:56 PM PDT 24
Finished May 30 02:11:03 PM PDT 24
Peak memory 209576 kb
Host smart-674d9510-e537-424b-bdc7-613e92808433
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013342469 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_access.2013342469
Directory /workspace/14.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_errors.2098857936
Short name T58
Test name
Test status
Simulation time 1646948981 ps
CPU time 54.36 seconds
Started May 30 02:10:53 PM PDT 24
Finished May 30 02:11:49 PM PDT 24
Peak memory 217988 kb
Host smart-b78f1c23-211e-483f-b7e0-e7ba6b5e4e17
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098857936 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_e
rrors.2098857936
Directory /workspace/14.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_prog_failure.3872726881
Short name T688
Test name
Test status
Simulation time 723638023 ps
CPU time 10.18 seconds
Started May 30 02:10:51 PM PDT 24
Finished May 30 02:11:02 PM PDT 24
Peak memory 217904 kb
Host smart-bcc08148-63fb-480f-8207-3fb6c9d00f82
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872726881 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jta
g_prog_failure.3872726881
Directory /workspace/14.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_smoke.557911276
Short name T630
Test name
Test status
Simulation time 5803642350 ps
CPU time 16.08 seconds
Started May 30 02:10:51 PM PDT 24
Finished May 30 02:11:08 PM PDT 24
Peak memory 217720 kb
Host smart-7c61cbb7-fcbf-4913-bf93-d593b44c01de
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557911276 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_smoke.
557911276
Directory /workspace/14.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_failure.1127220655
Short name T618
Test name
Test status
Simulation time 8961696429 ps
CPU time 41.48 seconds
Started May 30 02:10:52 PM PDT 24
Finished May 30 02:11:35 PM PDT 24
Peak memory 269040 kb
Host smart-920a08e8-8069-4568-bb02-1dab803b1c61
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127220655 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jt
ag_state_failure.1127220655
Directory /workspace/14.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_post_trans.3369946361
Short name T246
Test name
Test status
Simulation time 1200819607 ps
CPU time 12.57 seconds
Started May 30 02:10:52 PM PDT 24
Finished May 30 02:11:06 PM PDT 24
Peak memory 251008 kb
Host smart-77a1169a-5f2b-4de5-ad75-6fafd197b4df
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369946361 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl
_jtag_state_post_trans.3369946361
Directory /workspace/14.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_prog_failure.269748791
Short name T464
Test name
Test status
Simulation time 87917098 ps
CPU time 3.27 seconds
Started May 30 02:10:54 PM PDT 24
Finished May 30 02:10:58 PM PDT 24
Peak memory 218096 kb
Host smart-979f7aa1-6893-4596-9d90-3d8f79b256b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269748791 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_prog_failure.269748791
Directory /workspace/14.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_mubi.2802823784
Short name T653
Test name
Test status
Simulation time 778373459 ps
CPU time 8.14 seconds
Started May 30 02:10:54 PM PDT 24
Finished May 30 02:11:04 PM PDT 24
Peak memory 226148 kb
Host smart-f174d473-8a7f-4eef-8d97-aac002e85c17
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802823784 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_mubi.2802823784
Directory /workspace/14.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_digest.1397073531
Short name T431
Test name
Test status
Simulation time 443571757 ps
CPU time 11.07 seconds
Started May 30 02:10:57 PM PDT 24
Finished May 30 02:11:10 PM PDT 24
Peak memory 217964 kb
Host smart-5c7218e8-31b0-4dab-b745-6146f78bd3fd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397073531 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_d
igest.1397073531
Directory /workspace/14.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_mux.1184974133
Short name T295
Test name
Test status
Simulation time 1259553222 ps
CPU time 8.8 seconds
Started May 30 02:10:52 PM PDT 24
Finished May 30 02:11:02 PM PDT 24
Peak memory 218060 kb
Host smart-6f725b1f-2823-4779-9d71-a481d9f46f54
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184974133 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_mux.
1184974133
Directory /workspace/14.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/14.lc_ctrl_security_escalation.613475852
Short name T392
Test name
Test status
Simulation time 679176509 ps
CPU time 7.57 seconds
Started May 30 02:10:53 PM PDT 24
Finished May 30 02:11:02 PM PDT 24
Peak memory 218060 kb
Host smart-128d2c26-56fe-4b3d-81bf-4489eea157f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613475852 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_security_escalation.613475852
Directory /workspace/14.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/14.lc_ctrl_smoke.481189902
Short name T123
Test name
Test status
Simulation time 59007687 ps
CPU time 2.07 seconds
Started May 30 02:10:54 PM PDT 24
Finished May 30 02:10:57 PM PDT 24
Peak memory 217744 kb
Host smart-87cb6b48-ab34-4741-b71c-262f9ffd7d34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481189902 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_smoke.481189902
Directory /workspace/14.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_failure.2431152404
Short name T421
Test name
Test status
Simulation time 648705248 ps
CPU time 21.09 seconds
Started May 30 02:10:57 PM PDT 24
Finished May 30 02:11:20 PM PDT 24
Peak memory 251016 kb
Host smart-e93b407d-9eb2-4b4d-9a8b-0704810242f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431152404 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_failure.2431152404
Directory /workspace/14.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_post_trans.891177124
Short name T168
Test name
Test status
Simulation time 48184780 ps
CPU time 3.13 seconds
Started May 30 02:10:54 PM PDT 24
Finished May 30 02:10:58 PM PDT 24
Peak memory 222452 kb
Host smart-fc40bf09-34d3-4ce4-a1e3-42e2f16e495e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891177124 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_post_trans.891177124
Directory /workspace/14.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_stress_all.163200086
Short name T837
Test name
Test status
Simulation time 9041090540 ps
CPU time 259.55 seconds
Started May 30 02:10:52 PM PDT 24
Finished May 30 02:15:13 PM PDT 24
Peak memory 275644 kb
Host smart-a2340c4a-855d-4967-b4e6-88b4a62cb0e0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163200086 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.lc_ctrl_stress_all.163200086
Directory /workspace/14.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.lc_ctrl_volatile_unlock_smoke.1205065843
Short name T52
Test name
Test status
Simulation time 95299569 ps
CPU time 0.96 seconds
Started May 30 02:10:54 PM PDT 24
Finished May 30 02:10:57 PM PDT 24
Peak memory 211560 kb
Host smart-22e0579b-0ebf-40fe-a3ff-81eec60b967c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205065843 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_c
trl_volatile_unlock_smoke.1205065843
Directory /workspace/14.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_alert_test.1263857182
Short name T771
Test name
Test status
Simulation time 32774665 ps
CPU time 0.85 seconds
Started May 30 02:10:56 PM PDT 24
Finished May 30 02:10:58 PM PDT 24
Peak memory 209564 kb
Host smart-211e0ee6-f60c-441a-8c5b-2af93381dcd3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263857182 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_alert_test.1263857182
Directory /workspace/15.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.lc_ctrl_errors.1551468629
Short name T541
Test name
Test status
Simulation time 1256285040 ps
CPU time 14.44 seconds
Started May 30 02:10:55 PM PDT 24
Finished May 30 02:11:10 PM PDT 24
Peak memory 218124 kb
Host smart-cc94ddb7-6e0d-425f-a4f6-37a1fc736732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551468629 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_errors.1551468629
Directory /workspace/15.lc_ctrl_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_errors.1088155339
Short name T357
Test name
Test status
Simulation time 3975487155 ps
CPU time 19.56 seconds
Started May 30 02:10:56 PM PDT 24
Finished May 30 02:11:17 PM PDT 24
Peak memory 218032 kb
Host smart-6763dacb-58c5-4bba-bb33-b035d9c12d78
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088155339 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_e
rrors.1088155339
Directory /workspace/15.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_prog_failure.2722330242
Short name T874
Test name
Test status
Simulation time 476698786 ps
CPU time 6.86 seconds
Started May 30 02:10:59 PM PDT 24
Finished May 30 02:11:07 PM PDT 24
Peak memory 217880 kb
Host smart-cbb5326e-d163-4096-9696-517be968f916
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722330242 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jta
g_prog_failure.2722330242
Directory /workspace/15.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_smoke.2675475171
Short name T74
Test name
Test status
Simulation time 484182844 ps
CPU time 7.48 seconds
Started May 30 02:10:56 PM PDT 24
Finished May 30 02:11:04 PM PDT 24
Peak memory 217700 kb
Host smart-8c99f114-8e45-4fc5-a7de-c73af17bf3e1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675475171 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_smoke
.2675475171
Directory /workspace/15.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_failure.3908211042
Short name T266
Test name
Test status
Simulation time 1025351590 ps
CPU time 42.98 seconds
Started May 30 02:10:52 PM PDT 24
Finished May 30 02:11:36 PM PDT 24
Peak memory 250944 kb
Host smart-1e1cb8b8-e0c2-4344-85c4-c13c8fffee71
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908211042 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jt
ag_state_failure.3908211042
Directory /workspace/15.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_post_trans.2316642411
Short name T773
Test name
Test status
Simulation time 524538604 ps
CPU time 20.86 seconds
Started May 30 02:10:52 PM PDT 24
Finished May 30 02:11:14 PM PDT 24
Peak memory 250948 kb
Host smart-7dc34ca6-2a58-4198-bfcc-1ea068065f3f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316642411 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl
_jtag_state_post_trans.2316642411
Directory /workspace/15.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_prog_failure.2163742641
Short name T770
Test name
Test status
Simulation time 118414165 ps
CPU time 2.96 seconds
Started May 30 02:10:52 PM PDT 24
Finished May 30 02:10:56 PM PDT 24
Peak memory 218132 kb
Host smart-8aea280d-e47e-487e-b3d7-f97cf80a7b98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163742641 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_prog_failure.2163742641
Directory /workspace/15.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_mubi.296849677
Short name T476
Test name
Test status
Simulation time 416461141 ps
CPU time 10.1 seconds
Started May 30 02:10:54 PM PDT 24
Finished May 30 02:11:06 PM PDT 24
Peak memory 218032 kb
Host smart-9d236f55-c7e2-4bd8-a948-07d025653f00
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296849677 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_mubi.296849677
Directory /workspace/15.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_digest.888150686
Short name T374
Test name
Test status
Simulation time 344525540 ps
CPU time 15.02 seconds
Started May 30 02:10:54 PM PDT 24
Finished May 30 02:11:11 PM PDT 24
Peak memory 226052 kb
Host smart-8a487f3e-b87a-4c16-96db-7102faa36334
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888150686 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_di
gest.888150686
Directory /workspace/15.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_mux.1687257775
Short name T830
Test name
Test status
Simulation time 741855825 ps
CPU time 8 seconds
Started May 30 02:10:55 PM PDT 24
Finished May 30 02:11:04 PM PDT 24
Peak memory 218024 kb
Host smart-fc43fcad-c73e-4b00-927a-b79d4465c2ce
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687257775 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_mux.
1687257775
Directory /workspace/15.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/15.lc_ctrl_security_escalation.3860289792
Short name T632
Test name
Test status
Simulation time 280174621 ps
CPU time 11.49 seconds
Started May 30 02:10:53 PM PDT 24
Finished May 30 02:11:06 PM PDT 24
Peak memory 226152 kb
Host smart-2af160d3-8648-4f15-b900-4838db2f9ba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860289792 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_security_escalation.3860289792
Directory /workspace/15.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_failure.3734876569
Short name T351
Test name
Test status
Simulation time 3444603790 ps
CPU time 35.88 seconds
Started May 30 02:10:52 PM PDT 24
Finished May 30 02:11:28 PM PDT 24
Peak memory 251076 kb
Host smart-d88cf20b-6434-49ac-a81d-e3f05372743a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734876569 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_failure.3734876569
Directory /workspace/15.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_post_trans.1830724945
Short name T635
Test name
Test status
Simulation time 179492295 ps
CPU time 6.93 seconds
Started May 30 02:10:51 PM PDT 24
Finished May 30 02:10:59 PM PDT 24
Peak memory 250588 kb
Host smart-76b3deda-f221-4afd-a617-bae0f1419b79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830724945 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_post_trans.1830724945
Directory /workspace/15.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all.419705673
Short name T640
Test name
Test status
Simulation time 5508008206 ps
CPU time 85.92 seconds
Started May 30 02:10:55 PM PDT 24
Finished May 30 02:12:22 PM PDT 24
Peak memory 279992 kb
Host smart-d9e89a83-79da-47a8-91c2-753bc54f7a3c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419705673 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.lc_ctrl_stress_all.419705673
Directory /workspace/15.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.lc_ctrl_volatile_unlock_smoke.2276828951
Short name T309
Test name
Test status
Simulation time 24026979 ps
CPU time 0.95 seconds
Started May 30 02:10:56 PM PDT 24
Finished May 30 02:10:58 PM PDT 24
Peak memory 208664 kb
Host smart-242bc3b6-ff84-4b3c-bbba-8af00e18580e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276828951 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_c
trl_volatile_unlock_smoke.2276828951
Directory /workspace/15.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_alert_test.131453332
Short name T289
Test name
Test status
Simulation time 17414729 ps
CPU time 1.15 seconds
Started May 30 02:11:02 PM PDT 24
Finished May 30 02:11:04 PM PDT 24
Peak memory 209568 kb
Host smart-b9a5f017-680a-462f-acdf-b8e7f4777c5b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131453332 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_alert_test.131453332
Directory /workspace/16.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.lc_ctrl_errors.4244487171
Short name T685
Test name
Test status
Simulation time 1690543309 ps
CPU time 12.23 seconds
Started May 30 02:10:59 PM PDT 24
Finished May 30 02:11:13 PM PDT 24
Peak memory 218016 kb
Host smart-e07b7f4e-ace4-48ad-b7f6-6007495dab8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244487171 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_errors.4244487171
Directory /workspace/16.lc_ctrl_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_access.1780259442
Short name T321
Test name
Test status
Simulation time 180511817 ps
CPU time 3.12 seconds
Started May 30 02:11:02 PM PDT 24
Finished May 30 02:11:06 PM PDT 24
Peak memory 209608 kb
Host smart-735bd276-1fc9-4e92-b4af-490e003b79b6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780259442 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_access.1780259442
Directory /workspace/16.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_errors.1744916252
Short name T59
Test name
Test status
Simulation time 13943998985 ps
CPU time 46.58 seconds
Started May 30 02:11:05 PM PDT 24
Finished May 30 02:11:53 PM PDT 24
Peak memory 219528 kb
Host smart-0c322eea-3a88-479c-8c37-0720e5a66438
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744916252 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_e
rrors.1744916252
Directory /workspace/16.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_prog_failure.16922496
Short name T120
Test name
Test status
Simulation time 593037710 ps
CPU time 6.84 seconds
Started May 30 02:11:02 PM PDT 24
Finished May 30 02:11:10 PM PDT 24
Peak memory 218064 kb
Host smart-26cc3cb2-7268-4218-b0da-c18d7aa4f815
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16922496 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_p
rog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_
prog_failure.16922496
Directory /workspace/16.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_smoke.2712104289
Short name T238
Test name
Test status
Simulation time 917242348 ps
CPU time 6.5 seconds
Started May 30 02:11:05 PM PDT 24
Finished May 30 02:11:13 PM PDT 24
Peak memory 217704 kb
Host smart-3cf802a8-8950-49b9-8ac3-f315803303ed
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712104289 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_smoke
.2712104289
Directory /workspace/16.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_failure.3593481239
Short name T490
Test name
Test status
Simulation time 1341169626 ps
CPU time 41.98 seconds
Started May 30 02:10:59 PM PDT 24
Finished May 30 02:11:42 PM PDT 24
Peak memory 252792 kb
Host smart-457712af-211e-48f6-a0d0-3977cfc2e487
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593481239 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jt
ag_state_failure.3593481239
Directory /workspace/16.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_post_trans.679229763
Short name T269
Test name
Test status
Simulation time 1804525039 ps
CPU time 14.29 seconds
Started May 30 02:11:05 PM PDT 24
Finished May 30 02:11:20 PM PDT 24
Peak memory 251024 kb
Host smart-47410d06-c69c-444c-a120-fc7f45448b1f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679229763 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_
jtag_state_post_trans.679229763
Directory /workspace/16.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_prog_failure.31879217
Short name T243
Test name
Test status
Simulation time 60676945 ps
CPU time 2.87 seconds
Started May 30 02:10:54 PM PDT 24
Finished May 30 02:10:59 PM PDT 24
Peak memory 218052 kb
Host smart-990c9633-7be9-49dd-b696-fc2c3d750a2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31879217 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_prog_failure.31879217
Directory /workspace/16.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_mubi.2284497793
Short name T304
Test name
Test status
Simulation time 722782467 ps
CPU time 14.28 seconds
Started May 30 02:11:00 PM PDT 24
Finished May 30 02:11:16 PM PDT 24
Peak memory 218000 kb
Host smart-2c7d8b01-695d-49b8-8a5c-7aee7479e5f2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284497793 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_mubi.2284497793
Directory /workspace/16.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_digest.4179168278
Short name T364
Test name
Test status
Simulation time 6824240345 ps
CPU time 12.17 seconds
Started May 30 02:11:00 PM PDT 24
Finished May 30 02:11:14 PM PDT 24
Peak memory 218160 kb
Host smart-2e378b20-f749-4ebd-bf9a-f565a8fc7be2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179168278 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_d
igest.4179168278
Directory /workspace/16.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_mux.135653018
Short name T731
Test name
Test status
Simulation time 303247747 ps
CPU time 8.09 seconds
Started May 30 02:11:02 PM PDT 24
Finished May 30 02:11:11 PM PDT 24
Peak memory 218068 kb
Host smart-07861d5d-c483-4421-815e-5407f5a3c78c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135653018 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_mux.135653018
Directory /workspace/16.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/16.lc_ctrl_security_escalation.3344407032
Short name T606
Test name
Test status
Simulation time 256259195 ps
CPU time 7.35 seconds
Started May 30 02:11:00 PM PDT 24
Finished May 30 02:11:09 PM PDT 24
Peak memory 218188 kb
Host smart-5aadbb11-e7c9-48fa-8125-6f9579225100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344407032 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_security_escalation.3344407032
Directory /workspace/16.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/16.lc_ctrl_smoke.4059944335
Short name T78
Test name
Test status
Simulation time 88093785 ps
CPU time 4.99 seconds
Started May 30 02:10:55 PM PDT 24
Finished May 30 02:11:01 PM PDT 24
Peak memory 217768 kb
Host smart-3a39843d-8c87-4b38-a257-21c925595704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059944335 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_smoke.4059944335
Directory /workspace/16.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_failure.2386625721
Short name T25
Test name
Test status
Simulation time 348451419 ps
CPU time 31.54 seconds
Started May 30 02:10:52 PM PDT 24
Finished May 30 02:11:24 PM PDT 24
Peak memory 250860 kb
Host smart-382c288d-ab09-4c49-ba2e-0a02a6e4f94a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386625721 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_failure.2386625721
Directory /workspace/16.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_post_trans.3813053469
Short name T369
Test name
Test status
Simulation time 50574299 ps
CPU time 6.48 seconds
Started May 30 02:10:54 PM PDT 24
Finished May 30 02:11:02 PM PDT 24
Peak memory 246524 kb
Host smart-e7405420-42e6-4725-9ae4-48c53bbc2e94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813053469 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_post_trans.3813053469
Directory /workspace/16.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_stress_all.1214473698
Short name T486
Test name
Test status
Simulation time 4438347042 ps
CPU time 87.06 seconds
Started May 30 02:11:07 PM PDT 24
Finished May 30 02:12:35 PM PDT 24
Peak memory 226172 kb
Host smart-43a2b7d7-5360-4ebe-8ab2-6eaf978e86c3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214473698 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.lc_ctrl_stress_all.1214473698
Directory /workspace/16.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.lc_ctrl_volatile_unlock_smoke.3789632345
Short name T348
Test name
Test status
Simulation time 51676979 ps
CPU time 1.09 seconds
Started May 30 02:10:59 PM PDT 24
Finished May 30 02:11:01 PM PDT 24
Peak memory 212572 kb
Host smart-f1d07b19-281e-4eb8-8856-89b3093143d9
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789632345 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_c
trl_volatile_unlock_smoke.3789632345
Directory /workspace/16.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_alert_test.964928186
Short name T779
Test name
Test status
Simulation time 16945512 ps
CPU time 1.08 seconds
Started May 30 02:10:59 PM PDT 24
Finished May 30 02:11:01 PM PDT 24
Peak memory 208740 kb
Host smart-44ef893c-734d-4870-9e53-120e72552c19
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964928186 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_alert_test.964928186
Directory /workspace/17.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.lc_ctrl_errors.4266986480
Short name T871
Test name
Test status
Simulation time 320347585 ps
CPU time 12.05 seconds
Started May 30 02:11:02 PM PDT 24
Finished May 30 02:11:15 PM PDT 24
Peak memory 218056 kb
Host smart-6b73fd21-cb3b-41f2-8ec0-ba848d6a20ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266986480 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_errors.4266986480
Directory /workspace/17.lc_ctrl_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_access.3424365797
Short name T35
Test name
Test status
Simulation time 429834034 ps
CPU time 5.42 seconds
Started May 30 02:11:02 PM PDT 24
Finished May 30 02:11:09 PM PDT 24
Peak memory 209540 kb
Host smart-d4c85b5d-b58a-4ade-a80c-b55c73a21913
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424365797 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_access.3424365797
Directory /workspace/17.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_errors.1120815709
Short name T425
Test name
Test status
Simulation time 1477923955 ps
CPU time 42.38 seconds
Started May 30 02:10:59 PM PDT 24
Finished May 30 02:11:43 PM PDT 24
Peak memory 217976 kb
Host smart-f835e7ca-f106-4486-b65b-c8360234ccef
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120815709 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_e
rrors.1120815709
Directory /workspace/17.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_prog_failure.1882845173
Short name T475
Test name
Test status
Simulation time 643522947 ps
CPU time 14.81 seconds
Started May 30 02:11:00 PM PDT 24
Finished May 30 02:11:17 PM PDT 24
Peak memory 217992 kb
Host smart-9af509e6-2ba0-4e08-b3f2-f011bea296db
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882845173 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jta
g_prog_failure.1882845173
Directory /workspace/17.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_smoke.2837059762
Short name T513
Test name
Test status
Simulation time 250347096 ps
CPU time 2.51 seconds
Started May 30 02:10:59 PM PDT 24
Finished May 30 02:11:03 PM PDT 24
Peak memory 217760 kb
Host smart-182f07f0-4d1b-4c19-bb19-cd2f0a32912b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837059762 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_smoke
.2837059762
Directory /workspace/17.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_post_trans.3017991702
Short name T727
Test name
Test status
Simulation time 1535714528 ps
CPU time 16.49 seconds
Started May 30 02:11:05 PM PDT 24
Finished May 30 02:11:23 PM PDT 24
Peak memory 247812 kb
Host smart-ffc6b67f-53a9-4a0b-a20e-0b150ea541bc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017991702 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl
_jtag_state_post_trans.3017991702
Directory /workspace/17.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_prog_failure.2067017499
Short name T282
Test name
Test status
Simulation time 59690390 ps
CPU time 2.71 seconds
Started May 30 02:11:01 PM PDT 24
Finished May 30 02:11:05 PM PDT 24
Peak memory 218144 kb
Host smart-98a25951-56d3-4419-9165-9e9557d30199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067017499 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_prog_failure.2067017499
Directory /workspace/17.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_mubi.3537216718
Short name T439
Test name
Test status
Simulation time 1270845083 ps
CPU time 15.44 seconds
Started May 30 02:10:59 PM PDT 24
Finished May 30 02:11:16 PM PDT 24
Peak memory 219036 kb
Host smart-a9b84d42-3eb1-4b64-8984-d4fd01bb5987
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537216718 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_mubi.3537216718
Directory /workspace/17.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_digest.1642548621
Short name T594
Test name
Test status
Simulation time 1099119555 ps
CPU time 16.15 seconds
Started May 30 02:11:02 PM PDT 24
Finished May 30 02:11:19 PM PDT 24
Peak memory 226036 kb
Host smart-b9f3e4db-546a-447d-834e-1fafd2e87d4f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642548621 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_d
igest.1642548621
Directory /workspace/17.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_mux.2315042098
Short name T27
Test name
Test status
Simulation time 275854547 ps
CPU time 11.67 seconds
Started May 30 02:11:00 PM PDT 24
Finished May 30 02:11:13 PM PDT 24
Peak memory 218072 kb
Host smart-c9a4c01c-25cf-493e-be1a-84419ef423c6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315042098 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_mux.
2315042098
Directory /workspace/17.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/17.lc_ctrl_security_escalation.3978269705
Short name T804
Test name
Test status
Simulation time 249784728 ps
CPU time 7.94 seconds
Started May 30 02:10:59 PM PDT 24
Finished May 30 02:11:08 PM PDT 24
Peak memory 218068 kb
Host smart-bfd68b85-ec71-4376-a059-6cda0297e53b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978269705 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_security_escalation.3978269705
Directory /workspace/17.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/17.lc_ctrl_smoke.1005731672
Short name T707
Test name
Test status
Simulation time 82023010 ps
CPU time 3.08 seconds
Started May 30 02:11:06 PM PDT 24
Finished May 30 02:11:10 PM PDT 24
Peak memory 217764 kb
Host smart-70c43307-da90-40af-ac42-f62243fc5661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005731672 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_smoke.1005731672
Directory /workspace/17.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_failure.3301170202
Short name T489
Test name
Test status
Simulation time 179388081 ps
CPU time 20.29 seconds
Started May 30 02:11:08 PM PDT 24
Finished May 30 02:11:29 PM PDT 24
Peak memory 251032 kb
Host smart-0c187a26-6f3a-4cb1-9855-5f9b1deb69d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301170202 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_failure.3301170202
Directory /workspace/17.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_post_trans.3020618931
Short name T166
Test name
Test status
Simulation time 65552268 ps
CPU time 6.71 seconds
Started May 30 02:11:04 PM PDT 24
Finished May 30 02:11:12 PM PDT 24
Peak memory 247068 kb
Host smart-c94add03-0303-431a-93bb-1f6d77f221e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020618931 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_post_trans.3020618931
Directory /workspace/17.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all.89374152
Short name T546
Test name
Test status
Simulation time 71063673823 ps
CPU time 423.25 seconds
Started May 30 02:10:59 PM PDT 24
Finished May 30 02:18:04 PM PDT 24
Peak memory 251116 kb
Host smart-ebbd9931-701f-4ae4-879c-8fee1962dd09
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89374152 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_T
EST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
7.lc_ctrl_stress_all.89374152
Directory /workspace/17.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all_with_rand_reset.3414522177
Short name T180
Test name
Test status
Simulation time 14795952357 ps
CPU time 401.36 seconds
Started May 30 02:11:07 PM PDT 24
Finished May 30 02:17:49 PM PDT 24
Peak memory 316812 kb
Host smart-bb5704c0-a1f9-403d-ad16-25151d899f20
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3414522177 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_stress_all_with_rand_reset.3414522177
Directory /workspace/17.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.lc_ctrl_volatile_unlock_smoke.839205437
Short name T49
Test name
Test status
Simulation time 12626641 ps
CPU time 0.95 seconds
Started May 30 02:10:59 PM PDT 24
Finished May 30 02:11:01 PM PDT 24
Peak memory 208636 kb
Host smart-702e14b1-1f20-43cf-ae6e-479fcea748a2
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839205437 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ct
rl_volatile_unlock_smoke.839205437
Directory /workspace/17.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_alert_test.3960669173
Short name T442
Test name
Test status
Simulation time 39103773 ps
CPU time 0.89 seconds
Started May 30 02:11:11 PM PDT 24
Finished May 30 02:11:14 PM PDT 24
Peak memory 209536 kb
Host smart-1157bba9-aad3-4257-b722-404d8fa13f96
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960669173 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_alert_test.3960669173
Directory /workspace/18.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.lc_ctrl_errors.3349829812
Short name T724
Test name
Test status
Simulation time 308375388 ps
CPU time 14.54 seconds
Started May 30 02:11:00 PM PDT 24
Finished May 30 02:11:16 PM PDT 24
Peak memory 218044 kb
Host smart-ea41873c-abef-4d89-b47b-e3ad104ff36e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349829812 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_errors.3349829812
Directory /workspace/18.lc_ctrl_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_access.2398888077
Short name T398
Test name
Test status
Simulation time 411445086 ps
CPU time 5.78 seconds
Started May 30 02:11:10 PM PDT 24
Finished May 30 02:11:18 PM PDT 24
Peak memory 209572 kb
Host smart-ea7fd13a-97d7-440a-b161-f869126c5c5d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398888077 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_access.2398888077
Directory /workspace/18.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_errors.1945682744
Short name T362
Test name
Test status
Simulation time 2765127606 ps
CPU time 24.06 seconds
Started May 30 02:11:07 PM PDT 24
Finished May 30 02:11:32 PM PDT 24
Peak memory 218028 kb
Host smart-42f31cab-fa78-4b3e-bad0-5225acfeda63
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945682744 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_e
rrors.1945682744
Directory /workspace/18.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_prog_failure.3805015736
Short name T672
Test name
Test status
Simulation time 401075605 ps
CPU time 11.61 seconds
Started May 30 02:11:08 PM PDT 24
Finished May 30 02:11:20 PM PDT 24
Peak memory 218036 kb
Host smart-e1e160f0-4f5c-40c2-ac2a-dca29efa00d2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805015736 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jta
g_prog_failure.3805015736
Directory /workspace/18.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_smoke.329179151
Short name T725
Test name
Test status
Simulation time 291376179 ps
CPU time 2.07 seconds
Started May 30 02:11:02 PM PDT 24
Finished May 30 02:11:05 PM PDT 24
Peak memory 217652 kb
Host smart-d3b79771-3746-408e-ba73-be3633756d0c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329179151 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_smoke.
329179151
Directory /workspace/18.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_failure.2301716518
Short name T805
Test name
Test status
Simulation time 1140491085 ps
CPU time 44.66 seconds
Started May 30 02:10:59 PM PDT 24
Finished May 30 02:11:45 PM PDT 24
Peak memory 251020 kb
Host smart-9caf0fd2-5e28-490c-b751-2084d728c6b6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301716518 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jt
ag_state_failure.2301716518
Directory /workspace/18.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_post_trans.3247214316
Short name T588
Test name
Test status
Simulation time 914167556 ps
CPU time 12.77 seconds
Started May 30 02:10:59 PM PDT 24
Finished May 30 02:11:13 PM PDT 24
Peak memory 251008 kb
Host smart-4d98e7c0-9cfc-41e7-ac74-9118d9e3239c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247214316 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl
_jtag_state_post_trans.3247214316
Directory /workspace/18.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_prog_failure.818287520
Short name T767
Test name
Test status
Simulation time 59779039 ps
CPU time 2.62 seconds
Started May 30 02:10:59 PM PDT 24
Finished May 30 02:11:03 PM PDT 24
Peak memory 218088 kb
Host smart-aa8f7b46-8ae7-4dca-8075-f15bb3d02021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818287520 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_prog_failure.818287520
Directory /workspace/18.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_mubi.845386551
Short name T226
Test name
Test status
Simulation time 1080790796 ps
CPU time 10.75 seconds
Started May 30 02:11:16 PM PDT 24
Finished May 30 02:11:28 PM PDT 24
Peak memory 218244 kb
Host smart-ccaa1b51-aec3-4a69-ba2c-02190f940861
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845386551 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_mubi.845386551
Directory /workspace/18.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_digest.1881589635
Short name T696
Test name
Test status
Simulation time 3145513319 ps
CPU time 22.95 seconds
Started May 30 02:11:13 PM PDT 24
Finished May 30 02:11:38 PM PDT 24
Peak memory 218972 kb
Host smart-b559edf6-31f2-4b1f-b34b-b2d067b4896c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881589635 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_d
igest.1881589635
Directory /workspace/18.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_mux.3436856214
Short name T302
Test name
Test status
Simulation time 1358967575 ps
CPU time 7.86 seconds
Started May 30 02:11:13 PM PDT 24
Finished May 30 02:11:22 PM PDT 24
Peak memory 218052 kb
Host smart-2903f6c0-985e-4831-892c-439fbe868ea9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436856214 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_mux.
3436856214
Directory /workspace/18.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/18.lc_ctrl_security_escalation.2462807781
Short name T699
Test name
Test status
Simulation time 794220814 ps
CPU time 9.25 seconds
Started May 30 02:11:07 PM PDT 24
Finished May 30 02:11:17 PM PDT 24
Peak memory 218092 kb
Host smart-64127641-e676-45fa-b015-02f1ae8b5f84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462807781 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_security_escalation.2462807781
Directory /workspace/18.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/18.lc_ctrl_smoke.764849581
Short name T288
Test name
Test status
Simulation time 1217103764 ps
CPU time 4.52 seconds
Started May 30 02:10:59 PM PDT 24
Finished May 30 02:11:05 PM PDT 24
Peak memory 217764 kb
Host smart-748a4a03-d92c-4b26-af6a-373584e2374f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764849581 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_smoke.764849581
Directory /workspace/18.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_failure.887098973
Short name T505
Test name
Test status
Simulation time 214962842 ps
CPU time 32.98 seconds
Started May 30 02:11:04 PM PDT 24
Finished May 30 02:11:39 PM PDT 24
Peak memory 250944 kb
Host smart-f07efb50-27f7-47c5-856b-a35fe565ac73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887098973 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_failure.887098973
Directory /workspace/18.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_post_trans.3515502132
Short name T406
Test name
Test status
Simulation time 65932741 ps
CPU time 4.21 seconds
Started May 30 02:10:59 PM PDT 24
Finished May 30 02:11:04 PM PDT 24
Peak memory 226460 kb
Host smart-d7f73c13-f665-402a-a4d3-d2e459734dc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515502132 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_post_trans.3515502132
Directory /workspace/18.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all.3246467779
Short name T372
Test name
Test status
Simulation time 63242447964 ps
CPU time 389.42 seconds
Started May 30 02:11:14 PM PDT 24
Finished May 30 02:17:45 PM PDT 24
Peak memory 282020 kb
Host smart-0d665b13-9141-4e11-a1ec-30a74ab713ee
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246467779 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.lc_ctrl_stress_all.3246467779
Directory /workspace/18.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.lc_ctrl_volatile_unlock_smoke.1792936299
Short name T680
Test name
Test status
Simulation time 36515435 ps
CPU time 0.89 seconds
Started May 30 02:11:05 PM PDT 24
Finished May 30 02:11:07 PM PDT 24
Peak memory 208624 kb
Host smart-41af71ed-42c8-46f7-a836-dcef40cfbb19
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792936299 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_c
trl_volatile_unlock_smoke.1792936299
Directory /workspace/18.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_alert_test.914880519
Short name T335
Test name
Test status
Simulation time 38616442 ps
CPU time 1 seconds
Started May 30 02:11:09 PM PDT 24
Finished May 30 02:11:12 PM PDT 24
Peak memory 208692 kb
Host smart-9893d316-7330-447a-88e5-a8f1685f3e43
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914880519 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_alert_test.914880519
Directory /workspace/19.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.lc_ctrl_errors.2725854125
Short name T482
Test name
Test status
Simulation time 305404165 ps
CPU time 13.96 seconds
Started May 30 02:11:09 PM PDT 24
Finished May 30 02:11:25 PM PDT 24
Peak memory 217932 kb
Host smart-55e78885-c0f5-4689-8c66-a57a0b7056d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725854125 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_errors.2725854125
Directory /workspace/19.lc_ctrl_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_access.58390137
Short name T191
Test name
Test status
Simulation time 765826094 ps
CPU time 10.87 seconds
Started May 30 02:11:10 PM PDT 24
Finished May 30 02:11:23 PM PDT 24
Peak memory 209564 kb
Host smart-be3539b5-9093-46f6-9890-b318636465a8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58390137 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_access.58390137
Directory /workspace/19.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_errors.3221490185
Short name T509
Test name
Test status
Simulation time 2491577797 ps
CPU time 64.84 seconds
Started May 30 02:11:10 PM PDT 24
Finished May 30 02:12:16 PM PDT 24
Peak memory 218992 kb
Host smart-74d5cc29-9e5d-44d9-934e-cbdd16db104b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221490185 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_e
rrors.3221490185
Directory /workspace/19.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_prog_failure.142891841
Short name T241
Test name
Test status
Simulation time 827391572 ps
CPU time 11 seconds
Started May 30 02:11:17 PM PDT 24
Finished May 30 02:11:29 PM PDT 24
Peak memory 217944 kb
Host smart-04812534-1c33-4e8a-b2e9-55ca407fa981
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142891841 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag
_prog_failure.142891841
Directory /workspace/19.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_smoke.2996031967
Short name T87
Test name
Test status
Simulation time 291799667 ps
CPU time 3.07 seconds
Started May 30 02:11:10 PM PDT 24
Finished May 30 02:11:15 PM PDT 24
Peak memory 217712 kb
Host smart-0e9b0a3c-8b73-465b-aace-1e2594bda1cc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996031967 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_smoke
.2996031967
Directory /workspace/19.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_failure.2258918333
Short name T386
Test name
Test status
Simulation time 1805665546 ps
CPU time 41.71 seconds
Started May 30 02:11:10 PM PDT 24
Finished May 30 02:11:53 PM PDT 24
Peak memory 250904 kb
Host smart-6a1be3a3-12ef-4478-aece-6baa80ec348c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258918333 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jt
ag_state_failure.2258918333
Directory /workspace/19.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_post_trans.2181528145
Short name T663
Test name
Test status
Simulation time 1834904973 ps
CPU time 26.04 seconds
Started May 30 02:11:10 PM PDT 24
Finished May 30 02:11:38 PM PDT 24
Peak memory 226380 kb
Host smart-b45c83c5-3396-4177-a2e8-ffaa2ab0b5b1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181528145 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl
_jtag_state_post_trans.2181528145
Directory /workspace/19.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_prog_failure.4263394306
Short name T501
Test name
Test status
Simulation time 150206580 ps
CPU time 3.32 seconds
Started May 30 02:11:14 PM PDT 24
Finished May 30 02:11:19 PM PDT 24
Peak memory 218048 kb
Host smart-a5ecd047-887d-40a6-8a6d-e6cdf891e7d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263394306 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_prog_failure.4263394306
Directory /workspace/19.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_mubi.1575814673
Short name T229
Test name
Test status
Simulation time 902777140 ps
CPU time 13.97 seconds
Started May 30 02:11:13 PM PDT 24
Finished May 30 02:11:28 PM PDT 24
Peak memory 226144 kb
Host smart-f58bf25a-545d-46fb-ada8-13389f3ba3dc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575814673 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_mubi.1575814673
Directory /workspace/19.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_digest.1725991777
Short name T224
Test name
Test status
Simulation time 1186723424 ps
CPU time 20.66 seconds
Started May 30 02:11:11 PM PDT 24
Finished May 30 02:11:33 PM PDT 24
Peak memory 217988 kb
Host smart-7789e5bd-6614-4062-ba42-423c0ac3c680
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725991777 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_d
igest.1725991777
Directory /workspace/19.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_mux.4114972260
Short name T543
Test name
Test status
Simulation time 2160727910 ps
CPU time 13.31 seconds
Started May 30 02:11:11 PM PDT 24
Finished May 30 02:11:25 PM PDT 24
Peak memory 218176 kb
Host smart-17e4f45f-1392-483d-8e1f-056c9cc0332a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114972260 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_mux.
4114972260
Directory /workspace/19.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/19.lc_ctrl_security_escalation.1003566960
Short name T427
Test name
Test status
Simulation time 708028865 ps
CPU time 13.26 seconds
Started May 30 02:11:11 PM PDT 24
Finished May 30 02:11:26 PM PDT 24
Peak memory 218192 kb
Host smart-b84d3bfc-1ec6-42c5-a035-d0dc36feb4bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003566960 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_security_escalation.1003566960
Directory /workspace/19.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/19.lc_ctrl_smoke.878060067
Short name T614
Test name
Test status
Simulation time 64592127 ps
CPU time 3.17 seconds
Started May 30 02:11:17 PM PDT 24
Finished May 30 02:11:21 PM PDT 24
Peak memory 214488 kb
Host smart-1f9c30f0-647d-45e3-9dbc-3e5e080452f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878060067 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_smoke.878060067
Directory /workspace/19.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_failure.510121439
Short name T732
Test name
Test status
Simulation time 1685842205 ps
CPU time 20.98 seconds
Started May 30 02:11:15 PM PDT 24
Finished May 30 02:11:37 PM PDT 24
Peak memory 250780 kb
Host smart-07ff0dca-8105-495c-9932-028930326700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510121439 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_failure.510121439
Directory /workspace/19.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_post_trans.1913611738
Short name T739
Test name
Test status
Simulation time 117019844 ps
CPU time 2.95 seconds
Started May 30 02:11:16 PM PDT 24
Finished May 30 02:11:21 PM PDT 24
Peak memory 222480 kb
Host smart-d23935fa-c7b5-45fd-9a60-d3c6a0a2ee0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913611738 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_post_trans.1913611738
Directory /workspace/19.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all.5994140
Short name T328
Test name
Test status
Simulation time 1216028091 ps
CPU time 33.88 seconds
Started May 30 02:11:12 PM PDT 24
Finished May 30 02:11:47 PM PDT 24
Peak memory 226056 kb
Host smart-d34b2df1-e9e6-4b60-a96c-25cb7bef87be
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5994140 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TE
ST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19
.lc_ctrl_stress_all.5994140
Directory /workspace/19.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all_with_rand_reset.2897332458
Short name T161
Test name
Test status
Simulation time 15037989850 ps
CPU time 200.69 seconds
Started May 30 02:11:08 PM PDT 24
Finished May 30 02:14:30 PM PDT 24
Peak memory 242764 kb
Host smart-66b4afc2-8c38-42f8-b5bf-339965f3ec4b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2897332458 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_stress_all_with_rand_reset.2897332458
Directory /workspace/19.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.lc_ctrl_volatile_unlock_smoke.771927473
Short name T769
Test name
Test status
Simulation time 13402770 ps
CPU time 0.94 seconds
Started May 30 02:11:13 PM PDT 24
Finished May 30 02:11:16 PM PDT 24
Peak memory 208812 kb
Host smart-e735ce26-9fad-45b0-a579-846d526e7dc8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771927473 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ct
rl_volatile_unlock_smoke.771927473
Directory /workspace/19.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_alert_test.2762945325
Short name T518
Test name
Test status
Simulation time 77607881 ps
CPU time 0.93 seconds
Started May 30 02:09:48 PM PDT 24
Finished May 30 02:09:50 PM PDT 24
Peak memory 208716 kb
Host smart-40cb1a0e-6f69-441c-a973-581bffe47bcd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762945325 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_alert_test.2762945325
Directory /workspace/2.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.lc_ctrl_errors.3977326372
Short name T458
Test name
Test status
Simulation time 203759428 ps
CPU time 10.55 seconds
Started May 30 02:09:51 PM PDT 24
Finished May 30 02:10:03 PM PDT 24
Peak memory 218012 kb
Host smart-8164a578-4166-4f3e-873b-8e2dd94e6c03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977326372 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_errors.3977326372
Directory /workspace/2.lc_ctrl_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_access.106567738
Short name T275
Test name
Test status
Simulation time 211174557 ps
CPU time 1.31 seconds
Started May 30 02:09:53 PM PDT 24
Finished May 30 02:09:56 PM PDT 24
Peak memory 209552 kb
Host smart-72f4504b-e856-4ba7-8530-771a3ff67608
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106567738 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_access.106567738
Directory /workspace/2.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_errors.342598727
Short name T675
Test name
Test status
Simulation time 13289125943 ps
CPU time 44.64 seconds
Started May 30 02:09:58 PM PDT 24
Finished May 30 02:10:44 PM PDT 24
Peak memory 218912 kb
Host smart-395830df-4be8-4e42-b66e-be5a4781b53e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342598727 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_err
ors.342598727
Directory /workspace/2.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_priority.1289889218
Short name T638
Test name
Test status
Simulation time 1381404411 ps
CPU time 4.66 seconds
Started May 30 02:09:50 PM PDT 24
Finished May 30 02:09:56 PM PDT 24
Peak memory 217748 kb
Host smart-75495be2-70e0-4719-9208-0810b7da8a76
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289889218 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_priority.1
289889218
Directory /workspace/2.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_prog_failure.1326363638
Short name T595
Test name
Test status
Simulation time 1986956037 ps
CPU time 14.58 seconds
Started May 30 02:09:55 PM PDT 24
Finished May 30 02:10:11 PM PDT 24
Peak memory 217924 kb
Host smart-c44923de-0ba7-4b1b-a1e1-4f991939b765
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326363638 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag
_prog_failure.1326363638
Directory /workspace/2.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_regwen_during_op.1540147365
Short name T255
Test name
Test status
Simulation time 1090494524 ps
CPU time 29.68 seconds
Started May 30 02:09:50 PM PDT 24
Finished May 30 02:10:21 PM PDT 24
Peak memory 217696 kb
Host smart-11266414-73e9-4c2a-9ad6-78753ded4e9a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540147365 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_regwen_during_op.1540147365
Directory /workspace/2.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_smoke.3777263417
Short name T705
Test name
Test status
Simulation time 910442326 ps
CPU time 3.32 seconds
Started May 30 02:09:50 PM PDT 24
Finished May 30 02:09:55 PM PDT 24
Peak memory 217640 kb
Host smart-e713ea4f-115e-4720-9bc4-2107d80c63f3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777263417 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_smoke.
3777263417
Directory /workspace/2.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_failure.1996300834
Short name T684
Test name
Test status
Simulation time 2068491496 ps
CPU time 38.39 seconds
Started May 30 02:09:54 PM PDT 24
Finished May 30 02:10:33 PM PDT 24
Peak memory 250940 kb
Host smart-72905283-b2b5-481e-8858-cd20d961d73a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996300834 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jta
g_state_failure.1996300834
Directory /workspace/2.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_post_trans.608582828
Short name T534
Test name
Test status
Simulation time 1565067099 ps
CPU time 17.06 seconds
Started May 30 02:09:49 PM PDT 24
Finished May 30 02:10:08 PM PDT 24
Peak memory 250496 kb
Host smart-8a987663-a151-4192-9d97-5e001b3ad80a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608582828 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_j
tag_state_post_trans.608582828
Directory /workspace/2.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_regwen_during_op.2155441900
Short name T214
Test name
Test status
Simulation time 247745365 ps
CPU time 13.46 seconds
Started May 30 02:09:55 PM PDT 24
Finished May 30 02:10:10 PM PDT 24
Peak memory 217860 kb
Host smart-1be2cab8-18b5-46ce-97ac-7bf819add879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155441900 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_regwen_during_op.2155441900
Directory /workspace/2.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_mubi.1109905941
Short name T602
Test name
Test status
Simulation time 791802137 ps
CPU time 17.27 seconds
Started May 30 02:09:58 PM PDT 24
Finished May 30 02:10:16 PM PDT 24
Peak memory 226132 kb
Host smart-a992e5f1-66f6-41e7-9178-122465271390
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109905941 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_mubi.1109905941
Directory /workspace/2.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_digest.3155087077
Short name T189
Test name
Test status
Simulation time 719148780 ps
CPU time 8.93 seconds
Started May 30 02:09:51 PM PDT 24
Finished May 30 02:10:02 PM PDT 24
Peak memory 217988 kb
Host smart-1a56452f-416f-4436-affc-a0017d352286
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155087077 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_di
gest.3155087077
Directory /workspace/2.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_mux.1615483005
Short name T467
Test name
Test status
Simulation time 1717633217 ps
CPU time 9.61 seconds
Started May 30 02:09:52 PM PDT 24
Finished May 30 02:10:03 PM PDT 24
Peak memory 218068 kb
Host smart-c7a21fd9-f355-4835-bca4-8a761b5b3d19
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615483005 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_mux.1
615483005
Directory /workspace/2.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/2.lc_ctrl_smoke.772895508
Short name T94
Test name
Test status
Simulation time 112318975 ps
CPU time 2.11 seconds
Started May 30 02:09:54 PM PDT 24
Finished May 30 02:09:57 PM PDT 24
Peak memory 213876 kb
Host smart-e12b3486-4f83-43b7-963e-23e58f3ca0df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772895508 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_smoke.772895508
Directory /workspace/2.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_failure.3744251391
Short name T822
Test name
Test status
Simulation time 2953068563 ps
CPU time 24.56 seconds
Started May 30 02:09:53 PM PDT 24
Finished May 30 02:10:19 PM PDT 24
Peak memory 251128 kb
Host smart-bd04edf7-9c0a-4310-89f3-a74fadc1e423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744251391 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_failure.3744251391
Directory /workspace/2.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_post_trans.1432128569
Short name T420
Test name
Test status
Simulation time 251188166 ps
CPU time 7.46 seconds
Started May 30 02:09:51 PM PDT 24
Finished May 30 02:10:00 PM PDT 24
Peak memory 250508 kb
Host smart-ae092c66-4c2d-4eff-95d6-dbf35054f9ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432128569 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_post_trans.1432128569
Directory /workspace/2.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all.3705948587
Short name T24
Test name
Test status
Simulation time 4974603686 ps
CPU time 30.93 seconds
Started May 30 02:09:58 PM PDT 24
Finished May 30 02:10:30 PM PDT 24
Peak memory 226140 kb
Host smart-c8dab786-e0c7-47a9-be5e-d3f7466e0ecb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705948587 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.lc_ctrl_stress_all.3705948587
Directory /workspace/2.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.lc_ctrl_volatile_unlock_smoke.236070781
Short name T712
Test name
Test status
Simulation time 43807904 ps
CPU time 0.76 seconds
Started May 30 02:09:59 PM PDT 24
Finished May 30 02:10:01 PM PDT 24
Peak memory 208504 kb
Host smart-fe17d5fd-f3f4-43f8-822d-ac705d2c585e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236070781 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctr
l_volatile_unlock_smoke.236070781
Directory /workspace/2.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_alert_test.988450279
Short name T80
Test name
Test status
Simulation time 75227516 ps
CPU time 1.26 seconds
Started May 30 02:11:10 PM PDT 24
Finished May 30 02:11:13 PM PDT 24
Peak memory 208716 kb
Host smart-e846d409-8795-4e99-a6ef-c7e9ec3ba7e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988450279 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_alert_test.988450279
Directory /workspace/20.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.lc_ctrl_errors.416896011
Short name T733
Test name
Test status
Simulation time 2426694568 ps
CPU time 16.69 seconds
Started May 30 02:11:16 PM PDT 24
Finished May 30 02:11:34 PM PDT 24
Peak memory 218044 kb
Host smart-526986d8-1843-448a-9e29-cd8c370c8767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416896011 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_errors.416896011
Directory /workspace/20.lc_ctrl_errors/latest

Test location /workspace/coverage/default/20.lc_ctrl_jtag_access.825581285
Short name T248
Test name
Test status
Simulation time 69466006 ps
CPU time 1.19 seconds
Started May 30 02:11:08 PM PDT 24
Finished May 30 02:11:10 PM PDT 24
Peak memory 216848 kb
Host smart-50067ecf-4a96-487d-8784-aa28114e69eb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825581285 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_jtag_access.825581285
Directory /workspace/20.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/20.lc_ctrl_prog_failure.2412512384
Short name T571
Test name
Test status
Simulation time 70452458 ps
CPU time 2.28 seconds
Started May 30 02:11:11 PM PDT 24
Finished May 30 02:11:14 PM PDT 24
Peak memory 217972 kb
Host smart-d78553c7-d303-40d2-95b4-dc202a7260fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412512384 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_prog_failure.2412512384
Directory /workspace/20.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_mubi.1069445438
Short name T650
Test name
Test status
Simulation time 1390139333 ps
CPU time 28.16 seconds
Started May 30 02:11:08 PM PDT 24
Finished May 30 02:11:37 PM PDT 24
Peak memory 218976 kb
Host smart-cb0120a9-db16-47a7-a149-3d6eb3946b81
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069445438 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_mubi.1069445438
Directory /workspace/20.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_digest.2479085985
Short name T313
Test name
Test status
Simulation time 912139915 ps
CPU time 20.43 seconds
Started May 30 02:11:13 PM PDT 24
Finished May 30 02:11:35 PM PDT 24
Peak memory 217968 kb
Host smart-fff13dad-d1ce-42ea-b817-f09aa95db877
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479085985 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_d
igest.2479085985
Directory /workspace/20.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_mux.1683111695
Short name T844
Test name
Test status
Simulation time 708649971 ps
CPU time 7.03 seconds
Started May 30 02:11:16 PM PDT 24
Finished May 30 02:11:24 PM PDT 24
Peak memory 218012 kb
Host smart-56e8bf56-5fb2-4cae-bd8b-03e9b4e6824b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683111695 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_mux.
1683111695
Directory /workspace/20.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/20.lc_ctrl_smoke.576153920
Short name T737
Test name
Test status
Simulation time 34137289 ps
CPU time 2.91 seconds
Started May 30 02:11:16 PM PDT 24
Finished May 30 02:11:21 PM PDT 24
Peak memory 214504 kb
Host smart-c3468834-b380-43e5-9fd8-cbe5607f900f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576153920 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_smoke.576153920
Directory /workspace/20.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_failure.756903786
Short name T853
Test name
Test status
Simulation time 1102261106 ps
CPU time 26.72 seconds
Started May 30 02:11:10 PM PDT 24
Finished May 30 02:11:39 PM PDT 24
Peak memory 250968 kb
Host smart-0385f33c-bc3b-43f7-97f8-b0bb588868f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756903786 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_failure.756903786
Directory /workspace/20.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_post_trans.2195861105
Short name T796
Test name
Test status
Simulation time 157090326 ps
CPU time 6.77 seconds
Started May 30 02:11:17 PM PDT 24
Finished May 30 02:11:25 PM PDT 24
Peak memory 247184 kb
Host smart-82d9f4c6-12e5-4842-b8cc-f2b50fbf5e9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195861105 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_post_trans.2195861105
Directory /workspace/20.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/20.lc_ctrl_stress_all.2133662935
Short name T521
Test name
Test status
Simulation time 20140879712 ps
CPU time 368.5 seconds
Started May 30 02:11:09 PM PDT 24
Finished May 30 02:17:19 PM PDT 24
Peak memory 270144 kb
Host smart-21326da7-2ce6-4c4c-b128-a8f94b2e4d3c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133662935 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.lc_ctrl_stress_all.2133662935
Directory /workspace/20.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.lc_ctrl_volatile_unlock_smoke.3939558458
Short name T90
Test name
Test status
Simulation time 16180607 ps
CPU time 1.14 seconds
Started May 30 02:11:11 PM PDT 24
Finished May 30 02:11:14 PM PDT 24
Peak memory 211468 kb
Host smart-611b79e6-c961-4ed5-8a0a-3389b10e2c66
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939558458 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_c
trl_volatile_unlock_smoke.3939558458
Directory /workspace/20.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_alert_test.360391482
Short name T801
Test name
Test status
Simulation time 54642868 ps
CPU time 0.85 seconds
Started May 30 02:11:16 PM PDT 24
Finished May 30 02:11:18 PM PDT 24
Peak memory 208512 kb
Host smart-779e6f80-fa63-41ce-bd41-bb69ce841653
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360391482 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_alert_test.360391482
Directory /workspace/21.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.lc_ctrl_errors.1016509175
Short name T504
Test name
Test status
Simulation time 293896680 ps
CPU time 10.51 seconds
Started May 30 02:11:16 PM PDT 24
Finished May 30 02:11:28 PM PDT 24
Peak memory 217996 kb
Host smart-290db91f-d8a3-4c22-a229-6194cde81107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016509175 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_errors.1016509175
Directory /workspace/21.lc_ctrl_errors/latest

Test location /workspace/coverage/default/21.lc_ctrl_jtag_access.1554235994
Short name T192
Test name
Test status
Simulation time 82078297 ps
CPU time 1.6 seconds
Started May 30 02:11:13 PM PDT 24
Finished May 30 02:11:17 PM PDT 24
Peak memory 209568 kb
Host smart-5634924f-d969-4809-bf70-03a29faceb4c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554235994 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_jtag_access.1554235994
Directory /workspace/21.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/21.lc_ctrl_prog_failure.1810402567
Short name T339
Test name
Test status
Simulation time 20244348 ps
CPU time 1.65 seconds
Started May 30 02:11:09 PM PDT 24
Finished May 30 02:11:12 PM PDT 24
Peak memory 218072 kb
Host smart-ffa72de3-6ab5-4e99-a12f-e4fac5bb657c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810402567 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_prog_failure.1810402567
Directory /workspace/21.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_mubi.3438060013
Short name T511
Test name
Test status
Simulation time 2968299150 ps
CPU time 19.69 seconds
Started May 30 02:11:10 PM PDT 24
Finished May 30 02:11:31 PM PDT 24
Peak memory 226216 kb
Host smart-cfac31dd-41a2-4655-a92d-8f25655abe8a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438060013 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_mubi.3438060013
Directory /workspace/21.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_digest.2290882011
Short name T583
Test name
Test status
Simulation time 281547182 ps
CPU time 10.86 seconds
Started May 30 02:11:10 PM PDT 24
Finished May 30 02:11:22 PM PDT 24
Peak memory 217976 kb
Host smart-a0b22b10-aa12-478e-98e4-64f8fbdabfe5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290882011 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_d
igest.2290882011
Directory /workspace/21.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_mux.3093671356
Short name T453
Test name
Test status
Simulation time 553040702 ps
CPU time 8.61 seconds
Started May 30 02:11:10 PM PDT 24
Finished May 30 02:11:20 PM PDT 24
Peak memory 217996 kb
Host smart-b01c7498-4225-4ac1-abe9-00a7396c9a4a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093671356 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_mux.
3093671356
Directory /workspace/21.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/21.lc_ctrl_security_escalation.2408996860
Short name T221
Test name
Test status
Simulation time 5996680378 ps
CPU time 14.13 seconds
Started May 30 02:11:11 PM PDT 24
Finished May 30 02:11:27 PM PDT 24
Peak memory 226188 kb
Host smart-05f9c02f-2a2e-4a01-8dca-199b44840973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408996860 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_security_escalation.2408996860
Directory /workspace/21.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/21.lc_ctrl_smoke.3941772055
Short name T668
Test name
Test status
Simulation time 42973697 ps
CPU time 2.21 seconds
Started May 30 02:11:16 PM PDT 24
Finished May 30 02:11:20 PM PDT 24
Peak memory 213872 kb
Host smart-2cd50532-899a-4b4c-be4f-fe7ba2f661a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941772055 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_smoke.3941772055
Directory /workspace/21.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_failure.316635328
Short name T315
Test name
Test status
Simulation time 308488230 ps
CPU time 30.43 seconds
Started May 30 02:11:09 PM PDT 24
Finished May 30 02:11:41 PM PDT 24
Peak memory 251028 kb
Host smart-56d666c3-e2b6-4bd0-b9a6-14cea82ade8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316635328 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_failure.316635328
Directory /workspace/21.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_post_trans.1359120785
Short name T448
Test name
Test status
Simulation time 81636258 ps
CPU time 7.15 seconds
Started May 30 02:11:08 PM PDT 24
Finished May 30 02:11:17 PM PDT 24
Peak memory 247324 kb
Host smart-2f313551-65db-4450-b0a3-9fe703c269a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359120785 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_post_trans.1359120785
Directory /workspace/21.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/21.lc_ctrl_stress_all.633546002
Short name T679
Test name
Test status
Simulation time 32283594907 ps
CPU time 498.31 seconds
Started May 30 02:11:13 PM PDT 24
Finished May 30 02:19:34 PM PDT 24
Peak memory 250976 kb
Host smart-83867fd6-eed3-48ae-bfe2-ba632c355002
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633546002 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.lc_ctrl_stress_all.633546002
Directory /workspace/21.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.lc_ctrl_volatile_unlock_smoke.560362585
Short name T265
Test name
Test status
Simulation time 18091099 ps
CPU time 0.91 seconds
Started May 30 02:11:10 PM PDT 24
Finished May 30 02:11:13 PM PDT 24
Peak memory 208584 kb
Host smart-a7be3d6f-08e0-4aa6-9def-0eaf49d7dbec
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560362585 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ct
rl_volatile_unlock_smoke.560362585
Directory /workspace/21.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_alert_test.1259309588
Short name T76
Test name
Test status
Simulation time 19452900 ps
CPU time 1.18 seconds
Started May 30 02:11:28 PM PDT 24
Finished May 30 02:11:31 PM PDT 24
Peak memory 208720 kb
Host smart-e9aeb87c-50e1-44cf-8e09-6b38a6a4fbdb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259309588 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_alert_test.1259309588
Directory /workspace/22.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.lc_ctrl_errors.3974548031
Short name T479
Test name
Test status
Simulation time 1619525789 ps
CPU time 14.28 seconds
Started May 30 02:11:12 PM PDT 24
Finished May 30 02:11:28 PM PDT 24
Peak memory 218084 kb
Host smart-9f327c86-351b-4c6e-97a4-6397bb048240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974548031 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_errors.3974548031
Directory /workspace/22.lc_ctrl_errors/latest

Test location /workspace/coverage/default/22.lc_ctrl_jtag_access.250234241
Short name T262
Test name
Test status
Simulation time 75008926 ps
CPU time 2.45 seconds
Started May 30 02:11:11 PM PDT 24
Finished May 30 02:11:15 PM PDT 24
Peak memory 209512 kb
Host smart-0de750ed-d241-48c1-acfa-0bdd696a3f17
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250234241 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_jtag_access.250234241
Directory /workspace/22.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/22.lc_ctrl_prog_failure.3600980577
Short name T551
Test name
Test status
Simulation time 184002925 ps
CPU time 2.32 seconds
Started May 30 02:11:13 PM PDT 24
Finished May 30 02:11:16 PM PDT 24
Peak memory 218112 kb
Host smart-fe4b9d83-9816-4302-99d2-9f4bb166fffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600980577 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_prog_failure.3600980577
Directory /workspace/22.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_mubi.4254138621
Short name T358
Test name
Test status
Simulation time 3423709966 ps
CPU time 17.36 seconds
Started May 30 02:11:27 PM PDT 24
Finished May 30 02:11:46 PM PDT 24
Peak memory 219812 kb
Host smart-69a84506-547e-464f-9386-0c166ecb21c7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254138621 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_mubi.4254138621
Directory /workspace/22.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_digest.3548565681
Short name T566
Test name
Test status
Simulation time 2483143937 ps
CPU time 18.97 seconds
Started May 30 02:11:25 PM PDT 24
Finished May 30 02:11:45 PM PDT 24
Peak memory 218000 kb
Host smart-202abc51-85da-431e-aaf1-2a9e08c25b1a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548565681 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_d
igest.3548565681
Directory /workspace/22.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_mux.1323126980
Short name T225
Test name
Test status
Simulation time 365994389 ps
CPU time 7.86 seconds
Started May 30 02:11:25 PM PDT 24
Finished May 30 02:11:34 PM PDT 24
Peak memory 218036 kb
Host smart-1926462b-92a5-4904-b0ed-d55f27297b9d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323126980 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_mux.
1323126980
Directory /workspace/22.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/22.lc_ctrl_security_escalation.1852032983
Short name T179
Test name
Test status
Simulation time 402744785 ps
CPU time 9.42 seconds
Started May 30 02:11:11 PM PDT 24
Finished May 30 02:11:22 PM PDT 24
Peak memory 218132 kb
Host smart-bc9c93af-e537-4439-9f58-2a8b3fc793be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852032983 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_security_escalation.1852032983
Directory /workspace/22.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/22.lc_ctrl_smoke.150013306
Short name T73
Test name
Test status
Simulation time 159806065 ps
CPU time 2.05 seconds
Started May 30 02:11:14 PM PDT 24
Finished May 30 02:11:17 PM PDT 24
Peak memory 214036 kb
Host smart-a38b614e-3cf6-4fba-8573-0b4a149d1313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150013306 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_smoke.150013306
Directory /workspace/22.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_failure.471440732
Short name T516
Test name
Test status
Simulation time 983541381 ps
CPU time 31.61 seconds
Started May 30 02:11:11 PM PDT 24
Finished May 30 02:11:44 PM PDT 24
Peak memory 251032 kb
Host smart-09bef2b0-9ac6-4911-9105-12c414b4c0e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471440732 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_failure.471440732
Directory /workspace/22.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_post_trans.1772723088
Short name T422
Test name
Test status
Simulation time 54186725 ps
CPU time 8.47 seconds
Started May 30 02:11:15 PM PDT 24
Finished May 30 02:11:25 PM PDT 24
Peak memory 250984 kb
Host smart-92129532-69ea-4353-b2cb-767e1c5da573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772723088 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_post_trans.1772723088
Directory /workspace/22.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/22.lc_ctrl_stress_all.372539899
Short name T334
Test name
Test status
Simulation time 26929634632 ps
CPU time 851.71 seconds
Started May 30 02:11:26 PM PDT 24
Finished May 30 02:25:39 PM PDT 24
Peak memory 261228 kb
Host smart-396316f5-cd9c-42be-a2b0-135758fa7724
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372539899 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.lc_ctrl_stress_all.372539899
Directory /workspace/22.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.lc_ctrl_stress_all_with_rand_reset.2703732414
Short name T766
Test name
Test status
Simulation time 3786922842 ps
CPU time 98.47 seconds
Started May 30 02:11:31 PM PDT 24
Finished May 30 02:13:10 PM PDT 24
Peak memory 274780 kb
Host smart-fa5b4d09-914f-4cbb-b2bc-5c12c3404040
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2703732414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_stress_all_with_rand_reset.2703732414
Directory /workspace/22.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.lc_ctrl_volatile_unlock_smoke.848693270
Short name T244
Test name
Test status
Simulation time 25173845 ps
CPU time 1.06 seconds
Started May 30 02:11:17 PM PDT 24
Finished May 30 02:11:19 PM PDT 24
Peak memory 211620 kb
Host smart-8ac57eac-9b4e-4cb4-9bbe-054f3615c427
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848693270 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ct
rl_volatile_unlock_smoke.848693270
Directory /workspace/22.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_alert_test.961928071
Short name T44
Test name
Test status
Simulation time 24341358 ps
CPU time 1 seconds
Started May 30 02:11:29 PM PDT 24
Finished May 30 02:11:31 PM PDT 24
Peak memory 208724 kb
Host smart-2e9a5f6c-1325-4665-9b96-66177fd5000a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961928071 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_alert_test.961928071
Directory /workspace/23.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.lc_ctrl_errors.1951025122
Short name T565
Test name
Test status
Simulation time 1242547541 ps
CPU time 10.44 seconds
Started May 30 02:11:30 PM PDT 24
Finished May 30 02:11:41 PM PDT 24
Peak memory 218076 kb
Host smart-fce6c6da-361a-449a-aed8-9d0c6ff2df6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951025122 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_errors.1951025122
Directory /workspace/23.lc_ctrl_errors/latest

Test location /workspace/coverage/default/23.lc_ctrl_jtag_access.646738637
Short name T284
Test name
Test status
Simulation time 220819269 ps
CPU time 2.09 seconds
Started May 30 02:11:26 PM PDT 24
Finished May 30 02:11:29 PM PDT 24
Peak memory 209508 kb
Host smart-b99e88f0-e088-47f8-b922-e5c5cad29902
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646738637 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_jtag_access.646738637
Directory /workspace/23.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/23.lc_ctrl_prog_failure.2538740712
Short name T839
Test name
Test status
Simulation time 48009130 ps
CPU time 1.78 seconds
Started May 30 02:11:29 PM PDT 24
Finished May 30 02:11:32 PM PDT 24
Peak memory 218016 kb
Host smart-8b6a452d-73fa-4314-a7fc-db3a5e489871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538740712 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_prog_failure.2538740712
Directory /workspace/23.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_mubi.2710273720
Short name T231
Test name
Test status
Simulation time 5579945669 ps
CPU time 11.43 seconds
Started May 30 02:11:26 PM PDT 24
Finished May 30 02:11:38 PM PDT 24
Peak memory 220208 kb
Host smart-38d3f445-7a22-4a77-9176-e603619291c3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710273720 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_mubi.2710273720
Directory /workspace/23.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_digest.1809756674
Short name T411
Test name
Test status
Simulation time 323697685 ps
CPU time 10.03 seconds
Started May 30 02:11:25 PM PDT 24
Finished May 30 02:11:36 PM PDT 24
Peak memory 217960 kb
Host smart-436fb49f-2831-411a-80c1-f7f4225f7e61
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809756674 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_d
igest.1809756674
Directory /workspace/23.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_mux.2740270686
Short name T547
Test name
Test status
Simulation time 462539620 ps
CPU time 10.36 seconds
Started May 30 02:11:24 PM PDT 24
Finished May 30 02:11:35 PM PDT 24
Peak memory 218044 kb
Host smart-6a8eed41-ec69-4e7c-ab69-db90d9b33429
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740270686 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_mux.
2740270686
Directory /workspace/23.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/23.lc_ctrl_security_escalation.3068774300
Short name T761
Test name
Test status
Simulation time 887034895 ps
CPU time 10.62 seconds
Started May 30 02:11:28 PM PDT 24
Finished May 30 02:11:40 PM PDT 24
Peak memory 218104 kb
Host smart-c359cb93-5719-477a-8b7d-5decc1b09174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068774300 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_security_escalation.3068774300
Directory /workspace/23.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/23.lc_ctrl_smoke.279948832
Short name T451
Test name
Test status
Simulation time 302675866 ps
CPU time 2.82 seconds
Started May 30 02:11:27 PM PDT 24
Finished May 30 02:11:31 PM PDT 24
Peak memory 217744 kb
Host smart-cc4cf9ca-d10c-42ed-aab3-d613838297bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279948832 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_smoke.279948832
Directory /workspace/23.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_failure.658795346
Short name T723
Test name
Test status
Simulation time 978005837 ps
CPU time 35.88 seconds
Started May 30 02:11:24 PM PDT 24
Finished May 30 02:12:01 PM PDT 24
Peak memory 251032 kb
Host smart-da3afe9d-b673-4e91-aee9-27f77f7dce72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658795346 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_failure.658795346
Directory /workspace/23.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_post_trans.3492467266
Short name T850
Test name
Test status
Simulation time 221237964 ps
CPU time 8.91 seconds
Started May 30 02:11:27 PM PDT 24
Finished May 30 02:11:38 PM PDT 24
Peak memory 251004 kb
Host smart-dbbc3588-602f-4e62-a003-8630bf3231e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492467266 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_post_trans.3492467266
Directory /workspace/23.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all.3485981836
Short name T783
Test name
Test status
Simulation time 34854912458 ps
CPU time 145.33 seconds
Started May 30 02:11:26 PM PDT 24
Finished May 30 02:13:53 PM PDT 24
Peak memory 283772 kb
Host smart-b17dd83b-7e48-436d-a549-4c09b14e259c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485981836 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.lc_ctrl_stress_all.3485981836
Directory /workspace/23.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all_with_rand_reset.1081185422
Short name T172
Test name
Test status
Simulation time 44005549400 ps
CPU time 4202.9 seconds
Started May 30 02:11:41 PM PDT 24
Finished May 30 03:21:46 PM PDT 24
Peak memory 677192 kb
Host smart-c057c93e-03c3-4f5e-a489-2dd0b98765e3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1081185422 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_stress_all_with_rand_reset.1081185422
Directory /workspace/23.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.lc_ctrl_volatile_unlock_smoke.1649038861
Short name T645
Test name
Test status
Simulation time 25300807 ps
CPU time 0.96 seconds
Started May 30 02:11:29 PM PDT 24
Finished May 30 02:11:31 PM PDT 24
Peak memory 208640 kb
Host smart-3924a02e-268c-412c-be05-045c1f46306f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649038861 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_c
trl_volatile_unlock_smoke.1649038861
Directory /workspace/23.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_alert_test.665623707
Short name T627
Test name
Test status
Simulation time 29353387 ps
CPU time 1.1 seconds
Started May 30 02:11:27 PM PDT 24
Finished May 30 02:11:29 PM PDT 24
Peak memory 208676 kb
Host smart-006438c1-cee2-4530-abb5-8a958b788597
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665623707 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_alert_test.665623707
Directory /workspace/24.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.lc_ctrl_errors.3037009968
Short name T494
Test name
Test status
Simulation time 1263872099 ps
CPU time 14.3 seconds
Started May 30 02:11:27 PM PDT 24
Finished May 30 02:11:42 PM PDT 24
Peak memory 217968 kb
Host smart-bf5a7e8e-f912-44e3-af92-93da936d2a77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037009968 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_errors.3037009968
Directory /workspace/24.lc_ctrl_errors/latest

Test location /workspace/coverage/default/24.lc_ctrl_jtag_access.3957966115
Short name T36
Test name
Test status
Simulation time 797835122 ps
CPU time 6.41 seconds
Started May 30 02:11:27 PM PDT 24
Finished May 30 02:11:34 PM PDT 24
Peak memory 217088 kb
Host smart-101e02b8-54ec-4d9e-8d23-651d445cf4dc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957966115 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_jtag_access.3957966115
Directory /workspace/24.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/24.lc_ctrl_prog_failure.924055163
Short name T572
Test name
Test status
Simulation time 285742619 ps
CPU time 1.73 seconds
Started May 30 02:11:27 PM PDT 24
Finished May 30 02:11:30 PM PDT 24
Peak memory 218048 kb
Host smart-35f89a9f-9ea5-4662-b0f7-a8033e1870b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924055163 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_prog_failure.924055163
Directory /workspace/24.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_mubi.458072214
Short name T306
Test name
Test status
Simulation time 535095214 ps
CPU time 12.52 seconds
Started May 30 02:11:25 PM PDT 24
Finished May 30 02:11:39 PM PDT 24
Peak memory 219008 kb
Host smart-08abc8e5-a7fa-49f2-ad8e-49476d757255
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458072214 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_mubi.458072214
Directory /workspace/24.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_digest.1254896094
Short name T493
Test name
Test status
Simulation time 889143659 ps
CPU time 12.01 seconds
Started May 30 02:11:25 PM PDT 24
Finished May 30 02:11:38 PM PDT 24
Peak memory 217992 kb
Host smart-3f47b2c7-8fec-4d03-8903-97244d2e75c0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254896094 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_d
igest.1254896094
Directory /workspace/24.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_mux.195350308
Short name T734
Test name
Test status
Simulation time 572925483 ps
CPU time 8.48 seconds
Started May 30 02:11:24 PM PDT 24
Finished May 30 02:11:33 PM PDT 24
Peak memory 218036 kb
Host smart-0270580c-904c-45ae-b209-3af5848e10ce
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195350308 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_mux.195350308
Directory /workspace/24.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/24.lc_ctrl_security_escalation.1934251197
Short name T759
Test name
Test status
Simulation time 487850386 ps
CPU time 7.76 seconds
Started May 30 02:11:25 PM PDT 24
Finished May 30 02:11:34 PM PDT 24
Peak memory 218164 kb
Host smart-4b27bf75-8267-4946-933b-c472f4ca6adb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934251197 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_security_escalation.1934251197
Directory /workspace/24.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/24.lc_ctrl_smoke.3521485661
Short name T171
Test name
Test status
Simulation time 95612080 ps
CPU time 1.74 seconds
Started May 30 02:11:27 PM PDT 24
Finished May 30 02:11:30 PM PDT 24
Peak memory 217788 kb
Host smart-2c8f52fd-7509-46bc-ac43-cc711ad1aa3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521485661 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_smoke.3521485661
Directory /workspace/24.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_failure.1952690331
Short name T582
Test name
Test status
Simulation time 434864539 ps
CPU time 23.93 seconds
Started May 30 02:11:28 PM PDT 24
Finished May 30 02:11:54 PM PDT 24
Peak memory 251020 kb
Host smart-ca55c9ee-de01-464c-ada7-ccbc369d389f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952690331 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_failure.1952690331
Directory /workspace/24.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_post_trans.3413132708
Short name T718
Test name
Test status
Simulation time 94823271 ps
CPU time 3.76 seconds
Started May 30 02:11:24 PM PDT 24
Finished May 30 02:11:28 PM PDT 24
Peak memory 222788 kb
Host smart-9af789ac-187b-4884-96d8-9440ddb4b8c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413132708 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_post_trans.3413132708
Directory /workspace/24.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all.3373220841
Short name T814
Test name
Test status
Simulation time 3047508846 ps
CPU time 44.43 seconds
Started May 30 02:11:25 PM PDT 24
Finished May 30 02:12:11 PM PDT 24
Peak memory 251056 kb
Host smart-ffccc9a9-ebb6-4ac2-9a5c-a98dad2e32de
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373220841 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.lc_ctrl_stress_all.3373220841
Directory /workspace/24.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all_with_rand_reset.1063153111
Short name T676
Test name
Test status
Simulation time 21782001501 ps
CPU time 270.04 seconds
Started May 30 02:11:28 PM PDT 24
Finished May 30 02:15:59 PM PDT 24
Peak memory 422208 kb
Host smart-bd75efd3-6bfa-47c7-9601-52f303512e7a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1063153111 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_stress_all_with_rand_reset.1063153111
Directory /workspace/24.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.lc_ctrl_volatile_unlock_smoke.1525556593
Short name T1
Test name
Test status
Simulation time 20245430 ps
CPU time 1.08 seconds
Started May 30 02:11:27 PM PDT 24
Finished May 30 02:11:29 PM PDT 24
Peak memory 212672 kb
Host smart-6a6b4cc3-cec1-4282-825b-bb7e644bfe40
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525556593 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_c
trl_volatile_unlock_smoke.1525556593
Directory /workspace/24.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_alert_test.3877334993
Short name T438
Test name
Test status
Simulation time 23684647 ps
CPU time 0.81 seconds
Started May 30 02:11:38 PM PDT 24
Finished May 30 02:11:40 PM PDT 24
Peak memory 209408 kb
Host smart-fce3df7f-19fc-4e98-ac28-ab9ef40afe3c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877334993 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_alert_test.3877334993
Directory /workspace/25.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.lc_ctrl_errors.4789047
Short name T721
Test name
Test status
Simulation time 301585401 ps
CPU time 13.52 seconds
Started May 30 02:11:29 PM PDT 24
Finished May 30 02:11:44 PM PDT 24
Peak memory 217960 kb
Host smart-142af7ca-1c2e-430f-85cb-6cfcb4de9122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4789047 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_errors.4789047
Directory /workspace/25.lc_ctrl_errors/latest

Test location /workspace/coverage/default/25.lc_ctrl_jtag_access.946692400
Short name T673
Test name
Test status
Simulation time 221201499 ps
CPU time 2.19 seconds
Started May 30 02:11:30 PM PDT 24
Finished May 30 02:11:33 PM PDT 24
Peak memory 209576 kb
Host smart-220ff3d1-70a5-41a1-99e2-4742ac4f3a7a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946692400 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_jtag_access.946692400
Directory /workspace/25.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/25.lc_ctrl_prog_failure.1920032067
Short name T307
Test name
Test status
Simulation time 91239590 ps
CPU time 3.22 seconds
Started May 30 02:11:29 PM PDT 24
Finished May 30 02:11:33 PM PDT 24
Peak memory 218104 kb
Host smart-a856c760-3ec9-4d0a-a680-548e2e6d539a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920032067 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_prog_failure.1920032067
Directory /workspace/25.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_mubi.4141349395
Short name T865
Test name
Test status
Simulation time 310453324 ps
CPU time 12.21 seconds
Started May 30 02:11:26 PM PDT 24
Finished May 30 02:11:39 PM PDT 24
Peak memory 226132 kb
Host smart-2f9a37bf-6aab-478f-98e7-33d5a149b7b6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141349395 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_mubi.4141349395
Directory /workspace/25.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_digest.690574614
Short name T729
Test name
Test status
Simulation time 211230123 ps
CPU time 9.25 seconds
Started May 30 02:11:29 PM PDT 24
Finished May 30 02:11:40 PM PDT 24
Peak memory 226084 kb
Host smart-867df0f6-b36b-47f5-817d-c515aa58a34c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690574614 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_di
gest.690574614
Directory /workspace/25.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_mux.3714476447
Short name T717
Test name
Test status
Simulation time 7040223438 ps
CPU time 13.29 seconds
Started May 30 02:11:30 PM PDT 24
Finished May 30 02:11:44 PM PDT 24
Peak memory 218208 kb
Host smart-79f178d7-5203-463a-b9d6-62e39ed69feb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714476447 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_mux.
3714476447
Directory /workspace/25.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/25.lc_ctrl_security_escalation.2944840504
Short name T760
Test name
Test status
Simulation time 2508339527 ps
CPU time 13.28 seconds
Started May 30 02:11:30 PM PDT 24
Finished May 30 02:11:44 PM PDT 24
Peak memory 218176 kb
Host smart-b0ede26a-bcbf-4b61-9b5f-2a709874fbc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944840504 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_security_escalation.2944840504
Directory /workspace/25.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/25.lc_ctrl_smoke.2042751141
Short name T253
Test name
Test status
Simulation time 26765741 ps
CPU time 1.26 seconds
Started May 30 02:11:24 PM PDT 24
Finished May 30 02:11:27 PM PDT 24
Peak memory 213464 kb
Host smart-843f142a-f141-4386-a72a-807b3bcc55f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042751141 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_smoke.2042751141
Directory /workspace/25.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_failure.2549970856
Short name T563
Test name
Test status
Simulation time 622995305 ps
CPU time 34.72 seconds
Started May 30 02:11:29 PM PDT 24
Finished May 30 02:12:05 PM PDT 24
Peak memory 251044 kb
Host smart-35d2602f-9586-448c-b818-50d329d2ddd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2549970856 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_failure.2549970856
Directory /workspace/25.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_post_trans.854615730
Short name T845
Test name
Test status
Simulation time 122597942 ps
CPU time 3.5 seconds
Started May 30 02:11:29 PM PDT 24
Finished May 30 02:11:34 PM PDT 24
Peak memory 222824 kb
Host smart-63f90315-bbe6-4897-a6e7-e808748393d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854615730 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_post_trans.854615730
Directory /workspace/25.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/25.lc_ctrl_stress_all.1327440559
Short name T674
Test name
Test status
Simulation time 7456632089 ps
CPU time 75.86 seconds
Started May 30 02:11:31 PM PDT 24
Finished May 30 02:12:48 PM PDT 24
Peak memory 259324 kb
Host smart-c71a5b15-5144-4f3e-accb-503579de4612
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327440559 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.lc_ctrl_stress_all.1327440559
Directory /workspace/25.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.lc_ctrl_volatile_unlock_smoke.3540645144
Short name T863
Test name
Test status
Simulation time 34792131 ps
CPU time 0.96 seconds
Started May 30 02:11:31 PM PDT 24
Finished May 30 02:11:33 PM PDT 24
Peak memory 211696 kb
Host smart-c0cc4aa7-4960-4348-8c2d-9906635cd384
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540645144 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_c
trl_volatile_unlock_smoke.3540645144
Directory /workspace/25.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_alert_test.3141855675
Short name T710
Test name
Test status
Simulation time 27797033 ps
CPU time 1.06 seconds
Started May 30 02:11:42 PM PDT 24
Finished May 30 02:11:45 PM PDT 24
Peak memory 208708 kb
Host smart-faa152d8-2c8d-45d8-874b-ec2d26f29fe7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141855675 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_alert_test.3141855675
Directory /workspace/26.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.lc_ctrl_errors.1721724409
Short name T484
Test name
Test status
Simulation time 1310744153 ps
CPU time 14.96 seconds
Started May 30 02:11:41 PM PDT 24
Finished May 30 02:11:56 PM PDT 24
Peak memory 218032 kb
Host smart-c0d9f18d-0167-4282-a29b-73ca7a998287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721724409 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_errors.1721724409
Directory /workspace/26.lc_ctrl_errors/latest

Test location /workspace/coverage/default/26.lc_ctrl_jtag_access.103345675
Short name T695
Test name
Test status
Simulation time 1101648468 ps
CPU time 3.96 seconds
Started May 30 02:11:42 PM PDT 24
Finished May 30 02:11:47 PM PDT 24
Peak memory 209564 kb
Host smart-a5e56f22-1554-4005-8947-8c90b2c9afa9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103345675 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_jtag_access.103345675
Directory /workspace/26.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/26.lc_ctrl_prog_failure.586901542
Short name T730
Test name
Test status
Simulation time 115811934 ps
CPU time 1.76 seconds
Started May 30 02:11:39 PM PDT 24
Finished May 30 02:11:42 PM PDT 24
Peak memory 218092 kb
Host smart-56b5b4ef-18ed-4a04-a2a5-9a62f1780241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=586901542 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_prog_failure.586901542
Directory /workspace/26.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_mubi.448484520
Short name T416
Test name
Test status
Simulation time 290801373 ps
CPU time 11.85 seconds
Started May 30 02:11:41 PM PDT 24
Finished May 30 02:11:54 PM PDT 24
Peak memory 218952 kb
Host smart-979c54d4-3f05-4562-a60f-ddd20c7a1c33
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448484520 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_mubi.448484520
Directory /workspace/26.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_digest.1535277992
Short name T105
Test name
Test status
Simulation time 245732731 ps
CPU time 8.17 seconds
Started May 30 02:11:41 PM PDT 24
Finished May 30 02:11:50 PM PDT 24
Peak memory 226056 kb
Host smart-d3711b6b-62f8-45eb-ae5e-eea8f882b691
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535277992 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_d
igest.1535277992
Directory /workspace/26.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_mux.3569895871
Short name T548
Test name
Test status
Simulation time 382428672 ps
CPU time 12.37 seconds
Started May 30 02:11:40 PM PDT 24
Finished May 30 02:11:53 PM PDT 24
Peak memory 218136 kb
Host smart-401a17b1-37e8-4126-88a5-a2c47abc5903
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569895871 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_mux.
3569895871
Directory /workspace/26.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/26.lc_ctrl_security_escalation.3506593712
Short name T829
Test name
Test status
Simulation time 854825747 ps
CPU time 7.73 seconds
Started May 30 02:11:39 PM PDT 24
Finished May 30 02:11:48 PM PDT 24
Peak memory 218100 kb
Host smart-24010058-a64f-4589-889b-ca0c0f79c401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506593712 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_security_escalation.3506593712
Directory /workspace/26.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/26.lc_ctrl_smoke.815368221
Short name T13
Test name
Test status
Simulation time 118907555 ps
CPU time 1.65 seconds
Started May 30 02:11:39 PM PDT 24
Finished May 30 02:11:42 PM PDT 24
Peak memory 213736 kb
Host smart-c8093e2d-d3ad-43b1-9e3e-3d271bcab2c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815368221 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_smoke.815368221
Directory /workspace/26.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_failure.1752110428
Short name T538
Test name
Test status
Simulation time 1150611140 ps
CPU time 22.25 seconds
Started May 30 02:11:41 PM PDT 24
Finished May 30 02:12:04 PM PDT 24
Peak memory 250924 kb
Host smart-bb40d6a4-2333-454d-ac0f-010ee513952e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752110428 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_failure.1752110428
Directory /workspace/26.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_post_trans.3006274598
Short name T327
Test name
Test status
Simulation time 638186340 ps
CPU time 6.25 seconds
Started May 30 02:11:38 PM PDT 24
Finished May 30 02:11:46 PM PDT 24
Peak memory 247104 kb
Host smart-99185c31-02c9-47d4-a6b0-07e9b54e899e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3006274598 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_post_trans.3006274598
Directory /workspace/26.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all.125600342
Short name T762
Test name
Test status
Simulation time 14761738270 ps
CPU time 92.16 seconds
Started May 30 02:11:41 PM PDT 24
Finished May 30 02:13:15 PM PDT 24
Peak memory 283852 kb
Host smart-1f501828-e1c0-453f-8ed5-9235eb054caa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125600342 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.lc_ctrl_stress_all.125600342
Directory /workspace/26.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.lc_ctrl_volatile_unlock_smoke.2636386403
Short name T322
Test name
Test status
Simulation time 41819770 ps
CPU time 0.92 seconds
Started May 30 02:11:41 PM PDT 24
Finished May 30 02:11:43 PM PDT 24
Peak memory 212740 kb
Host smart-014bbf0f-e484-4f13-b1c1-8d453141780f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636386403 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_c
trl_volatile_unlock_smoke.2636386403
Directory /workspace/26.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_alert_test.4214868379
Short name T400
Test name
Test status
Simulation time 43612452 ps
CPU time 0.81 seconds
Started May 30 02:11:39 PM PDT 24
Finished May 30 02:11:41 PM PDT 24
Peak memory 208484 kb
Host smart-bf291764-6fb1-4a2b-a814-16714c57120f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214868379 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_alert_test.4214868379
Directory /workspace/27.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.lc_ctrl_errors.940212127
Short name T344
Test name
Test status
Simulation time 4617465913 ps
CPU time 10.76 seconds
Started May 30 02:11:40 PM PDT 24
Finished May 30 02:11:52 PM PDT 24
Peak memory 218164 kb
Host smart-cc3c4043-5e40-4e6d-887e-5e287c1a28a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940212127 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_errors.940212127
Directory /workspace/27.lc_ctrl_errors/latest

Test location /workspace/coverage/default/27.lc_ctrl_jtag_access.846534193
Short name T670
Test name
Test status
Simulation time 226861994 ps
CPU time 2.88 seconds
Started May 30 02:11:40 PM PDT 24
Finished May 30 02:11:44 PM PDT 24
Peak memory 216840 kb
Host smart-3dfca671-555a-434b-8079-dc2617182a2d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846534193 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_jtag_access.846534193
Directory /workspace/27.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/27.lc_ctrl_prog_failure.3303171963
Short name T506
Test name
Test status
Simulation time 66271221 ps
CPU time 3.04 seconds
Started May 30 02:11:39 PM PDT 24
Finished May 30 02:11:43 PM PDT 24
Peak memory 218064 kb
Host smart-34bbfe7d-17e6-4ee3-8665-dd1e692479cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3303171963 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_prog_failure.3303171963
Directory /workspace/27.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_mubi.1769914761
Short name T281
Test name
Test status
Simulation time 476426324 ps
CPU time 11.63 seconds
Started May 30 02:11:42 PM PDT 24
Finished May 30 02:11:55 PM PDT 24
Peak memory 218276 kb
Host smart-7d4e773e-448f-405a-8c88-2bf0583547fa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769914761 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_mubi.1769914761
Directory /workspace/27.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_digest.286690206
Short name T855
Test name
Test status
Simulation time 4766869859 ps
CPU time 10.23 seconds
Started May 30 02:11:41 PM PDT 24
Finished May 30 02:11:53 PM PDT 24
Peak memory 218180 kb
Host smart-ae4cad2d-b230-47f0-b6be-e377f5b15cca
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286690206 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_di
gest.286690206
Directory /workspace/27.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_mux.1732667040
Short name T669
Test name
Test status
Simulation time 270822688 ps
CPU time 10.59 seconds
Started May 30 02:11:41 PM PDT 24
Finished May 30 02:11:53 PM PDT 24
Peak memory 218040 kb
Host smart-7da14e1f-0465-46b8-92d0-4569b6f57b07
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732667040 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_mux.
1732667040
Directory /workspace/27.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/27.lc_ctrl_security_escalation.1853806395
Short name T785
Test name
Test status
Simulation time 1170979112 ps
CPU time 6.93 seconds
Started May 30 02:11:39 PM PDT 24
Finished May 30 02:11:47 PM PDT 24
Peak memory 218048 kb
Host smart-d798ad02-3997-46f2-bef1-26bef34ab195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853806395 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_security_escalation.1853806395
Directory /workspace/27.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/27.lc_ctrl_smoke.2812027767
Short name T615
Test name
Test status
Simulation time 1032541507 ps
CPU time 9.6 seconds
Started May 30 02:11:42 PM PDT 24
Finished May 30 02:11:53 PM PDT 24
Peak memory 217648 kb
Host smart-86a4c7f7-7f64-4c61-83b0-ef33ad8fa0b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812027767 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_smoke.2812027767
Directory /workspace/27.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_failure.522430022
Short name T795
Test name
Test status
Simulation time 272667885 ps
CPU time 36.49 seconds
Started May 30 02:11:44 PM PDT 24
Finished May 30 02:12:22 PM PDT 24
Peak memory 250676 kb
Host smart-865017db-606b-4d3e-bfc0-2c40c1e3f36d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522430022 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_failure.522430022
Directory /workspace/27.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_post_trans.3995047366
Short name T419
Test name
Test status
Simulation time 111730606 ps
CPU time 7.26 seconds
Started May 30 02:11:39 PM PDT 24
Finished May 30 02:11:47 PM PDT 24
Peak memory 250532 kb
Host smart-ea53dd02-2bb1-4820-b3ac-44df5c58ab2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995047366 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_post_trans.3995047366
Directory /workspace/27.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all.3902702837
Short name T866
Test name
Test status
Simulation time 12850455395 ps
CPU time 473.73 seconds
Started May 30 02:11:41 PM PDT 24
Finished May 30 02:19:36 PM PDT 24
Peak memory 282176 kb
Host smart-80d9b7ec-8efd-43b9-9004-f002f0fb15a1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902702837 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.lc_ctrl_stress_all.3902702837
Directory /workspace/27.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.lc_ctrl_volatile_unlock_smoke.663960938
Short name T715
Test name
Test status
Simulation time 56489100 ps
CPU time 1.04 seconds
Started May 30 02:11:41 PM PDT 24
Finished May 30 02:11:44 PM PDT 24
Peak memory 212612 kb
Host smart-5d495625-fd13-4a56-81b9-73bc5a6e3f82
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663960938 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ct
rl_volatile_unlock_smoke.663960938
Directory /workspace/27.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_alert_test.145897662
Short name T751
Test name
Test status
Simulation time 20342147 ps
CPU time 1.15 seconds
Started May 30 02:11:48 PM PDT 24
Finished May 30 02:11:50 PM PDT 24
Peak memory 208472 kb
Host smart-042ff6b9-d302-450a-9dee-0e4e54162e3a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145897662 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_alert_test.145897662
Directory /workspace/28.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.lc_ctrl_errors.3021437554
Short name T235
Test name
Test status
Simulation time 348395300 ps
CPU time 12.96 seconds
Started May 30 02:11:43 PM PDT 24
Finished May 30 02:11:57 PM PDT 24
Peak memory 217992 kb
Host smart-f4ce5501-5122-4f40-9892-0591fc662a8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021437554 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_errors.3021437554
Directory /workspace/28.lc_ctrl_errors/latest

Test location /workspace/coverage/default/28.lc_ctrl_jtag_access.2962520471
Short name T459
Test name
Test status
Simulation time 891704654 ps
CPU time 3.82 seconds
Started May 30 02:11:42 PM PDT 24
Finished May 30 02:11:47 PM PDT 24
Peak memory 217016 kb
Host smart-5f4a6627-6ee7-4dce-b81e-0fb094b8346e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962520471 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_jtag_access.2962520471
Directory /workspace/28.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/28.lc_ctrl_prog_failure.3194756415
Short name T181
Test name
Test status
Simulation time 119243808 ps
CPU time 1.85 seconds
Started May 30 02:11:41 PM PDT 24
Finished May 30 02:11:44 PM PDT 24
Peak memory 218148 kb
Host smart-c3de14ca-b93b-484f-916e-67ff908bc8a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194756415 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_prog_failure.3194756415
Directory /workspace/28.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_mubi.379499923
Short name T515
Test name
Test status
Simulation time 348627980 ps
CPU time 12.2 seconds
Started May 30 02:11:42 PM PDT 24
Finished May 30 02:11:55 PM PDT 24
Peak memory 226160 kb
Host smart-6a5caf35-9470-41da-b4e7-abf103d9e9ce
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379499923 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_mubi.379499923
Directory /workspace/28.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_digest.2897030881
Short name T512
Test name
Test status
Simulation time 506271610 ps
CPU time 12.89 seconds
Started May 30 02:11:42 PM PDT 24
Finished May 30 02:11:56 PM PDT 24
Peak memory 226028 kb
Host smart-3b02651b-6a1e-4424-9c17-57425d081376
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897030881 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_d
igest.2897030881
Directory /workspace/28.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_mux.3626697807
Short name T552
Test name
Test status
Simulation time 342513260 ps
CPU time 9.52 seconds
Started May 30 02:11:48 PM PDT 24
Finished May 30 02:11:59 PM PDT 24
Peak memory 217888 kb
Host smart-1fcca6ac-8781-4e58-bb93-f8a72a90fcf5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626697807 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_mux.
3626697807
Directory /workspace/28.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/28.lc_ctrl_security_escalation.3610022994
Short name T758
Test name
Test status
Simulation time 237915171 ps
CPU time 10.43 seconds
Started May 30 02:11:41 PM PDT 24
Finished May 30 02:11:52 PM PDT 24
Peak memory 218192 kb
Host smart-ddb8d726-067a-4b1f-8643-9a06596681a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610022994 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_security_escalation.3610022994
Directory /workspace/28.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/28.lc_ctrl_smoke.1285842029
Short name T652
Test name
Test status
Simulation time 28684360 ps
CPU time 1 seconds
Started May 30 02:11:41 PM PDT 24
Finished May 30 02:11:43 PM PDT 24
Peak memory 211932 kb
Host smart-f8b2c6c6-d293-4e50-8b76-2d8f7771146b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285842029 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_smoke.1285842029
Directory /workspace/28.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_failure.1124945313
Short name T449
Test name
Test status
Simulation time 1158884320 ps
CPU time 29.18 seconds
Started May 30 02:11:41 PM PDT 24
Finished May 30 02:12:12 PM PDT 24
Peak memory 250912 kb
Host smart-7a068614-231b-4bf2-862e-cd7472ab81a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124945313 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_failure.1124945313
Directory /workspace/28.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_post_trans.1677816043
Short name T251
Test name
Test status
Simulation time 232126294 ps
CPU time 7.82 seconds
Started May 30 02:11:43 PM PDT 24
Finished May 30 02:11:52 PM PDT 24
Peak memory 251044 kb
Host smart-291cd0e5-3156-4a47-9f40-3040422d8121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677816043 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_post_trans.1677816043
Directory /workspace/28.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/28.lc_ctrl_stress_all.1086134146
Short name T323
Test name
Test status
Simulation time 32225148016 ps
CPU time 499.08 seconds
Started May 30 02:11:42 PM PDT 24
Finished May 30 02:20:02 PM PDT 24
Peak memory 283804 kb
Host smart-d618c24c-3b2c-4fe3-b09b-9893c06266d9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086134146 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.lc_ctrl_stress_all.1086134146
Directory /workspace/28.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.lc_ctrl_volatile_unlock_smoke.1494084699
Short name T605
Test name
Test status
Simulation time 46175553 ps
CPU time 0.8 seconds
Started May 30 02:11:41 PM PDT 24
Finished May 30 02:11:43 PM PDT 24
Peak memory 208736 kb
Host smart-6122c7f7-3fa3-48b9-843c-a4610116d7bb
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494084699 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_c
trl_volatile_unlock_smoke.1494084699
Directory /workspace/28.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_alert_test.3923042635
Short name T316
Test name
Test status
Simulation time 19382837 ps
CPU time 1.17 seconds
Started May 30 02:11:42 PM PDT 24
Finished May 30 02:11:44 PM PDT 24
Peak memory 208784 kb
Host smart-d4d1d2f4-f30b-4ea2-9287-b9859ddca9ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923042635 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_alert_test.3923042635
Directory /workspace/29.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.lc_ctrl_errors.1279355817
Short name T545
Test name
Test status
Simulation time 4146870037 ps
CPU time 11.5 seconds
Started May 30 02:11:43 PM PDT 24
Finished May 30 02:11:56 PM PDT 24
Peak memory 218452 kb
Host smart-f625e61f-4035-4914-86b0-05c33e10e120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279355817 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_errors.1279355817
Directory /workspace/29.lc_ctrl_errors/latest

Test location /workspace/coverage/default/29.lc_ctrl_jtag_access.1460495070
Short name T30
Test name
Test status
Simulation time 868213090 ps
CPU time 20.2 seconds
Started May 30 02:11:47 PM PDT 24
Finished May 30 02:12:08 PM PDT 24
Peak memory 217136 kb
Host smart-290e81c6-b10f-4bf7-88d6-cf450f138bf2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460495070 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_jtag_access.1460495070
Directory /workspace/29.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/29.lc_ctrl_prog_failure.1496773530
Short name T573
Test name
Test status
Simulation time 112003087 ps
CPU time 2.51 seconds
Started May 30 02:11:46 PM PDT 24
Finished May 30 02:11:50 PM PDT 24
Peak memory 217992 kb
Host smart-8e426af2-d1c5-4517-885a-6e359ddd0f51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496773530 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_prog_failure.1496773530
Directory /workspace/29.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_digest.2464559184
Short name T858
Test name
Test status
Simulation time 658811189 ps
CPU time 11.29 seconds
Started May 30 02:11:46 PM PDT 24
Finished May 30 02:11:58 PM PDT 24
Peak memory 226152 kb
Host smart-4e03a1a5-3d67-43bb-850b-45396ead35d3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464559184 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_d
igest.2464559184
Directory /workspace/29.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_mux.202370266
Short name T488
Test name
Test status
Simulation time 1511556521 ps
CPU time 10.12 seconds
Started May 30 02:11:44 PM PDT 24
Finished May 30 02:11:55 PM PDT 24
Peak memory 217996 kb
Host smart-53a76fd1-8d0d-4241-8bcb-09ffd58ab4bb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202370266 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_mux.202370266
Directory /workspace/29.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/29.lc_ctrl_security_escalation.3520152113
Short name T848
Test name
Test status
Simulation time 778321240 ps
CPU time 14.58 seconds
Started May 30 02:11:48 PM PDT 24
Finished May 30 02:12:04 PM PDT 24
Peak memory 224896 kb
Host smart-b6e9936c-0307-4f11-9daa-28bda839f3cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520152113 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_security_escalation.3520152113
Directory /workspace/29.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/29.lc_ctrl_smoke.3457661501
Short name T92
Test name
Test status
Simulation time 2008605916 ps
CPU time 3.73 seconds
Started May 30 02:11:43 PM PDT 24
Finished May 30 02:11:48 PM PDT 24
Peak memory 217756 kb
Host smart-95903fd9-d57b-49c9-971c-7a0ea0b14791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457661501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_smoke.3457661501
Directory /workspace/29.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_failure.1193550347
Short name T872
Test name
Test status
Simulation time 455409241 ps
CPU time 28.4 seconds
Started May 30 02:11:47 PM PDT 24
Finished May 30 02:12:16 PM PDT 24
Peak memory 250984 kb
Host smart-1ac0265f-8247-4061-ada7-f7c7dafa2d85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193550347 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_failure.1193550347
Directory /workspace/29.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_post_trans.4190421531
Short name T182
Test name
Test status
Simulation time 62422377 ps
CPU time 2.9 seconds
Started May 30 02:11:42 PM PDT 24
Finished May 30 02:11:46 PM PDT 24
Peak memory 222340 kb
Host smart-b1ce85c2-30de-4f64-9e8e-ffca6ccae169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190421531 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_post_trans.4190421531
Directory /workspace/29.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/29.lc_ctrl_stress_all.1098392217
Short name T629
Test name
Test status
Simulation time 5307706359 ps
CPU time 190.04 seconds
Started May 30 02:11:44 PM PDT 24
Finished May 30 02:14:56 PM PDT 24
Peak memory 251876 kb
Host smart-6b33f99d-203a-4fa2-8fe7-1da63a66fd76
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098392217 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.lc_ctrl_stress_all.1098392217
Directory /workspace/29.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.lc_ctrl_volatile_unlock_smoke.3304453727
Short name T491
Test name
Test status
Simulation time 14042858 ps
CPU time 1.11 seconds
Started May 30 02:11:48 PM PDT 24
Finished May 30 02:11:50 PM PDT 24
Peak memory 211460 kb
Host smart-10567fcb-110a-4591-9cb6-d75673eb9fc4
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304453727 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_c
trl_volatile_unlock_smoke.3304453727
Directory /workspace/29.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_alert_test.1065344015
Short name T528
Test name
Test status
Simulation time 58307885 ps
CPU time 0.94 seconds
Started May 30 02:09:54 PM PDT 24
Finished May 30 02:09:56 PM PDT 24
Peak memory 209512 kb
Host smart-897d8eff-d6c5-4ec0-bf6d-71ce698d9239
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065344015 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_alert_test.1065344015
Directory /workspace/3.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.lc_ctrl_claim_transition_if.1509384223
Short name T559
Test name
Test status
Simulation time 71437264 ps
CPU time 0.85 seconds
Started May 30 02:09:55 PM PDT 24
Finished May 30 02:09:57 PM PDT 24
Peak memory 208752 kb
Host smart-0dfd1743-7030-44e7-98d7-6281be49a4a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509384223 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_claim_transition_if.1509384223
Directory /workspace/3.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/3.lc_ctrl_errors.3393253268
Short name T331
Test name
Test status
Simulation time 2013844949 ps
CPU time 15.26 seconds
Started May 30 02:09:52 PM PDT 24
Finished May 30 02:10:09 PM PDT 24
Peak memory 218104 kb
Host smart-766a62e9-8c5a-4f43-9dd8-6512b5c7ca98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393253268 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_errors.3393253268
Directory /workspace/3.lc_ctrl_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_access.163249348
Short name T857
Test name
Test status
Simulation time 411423283 ps
CPU time 5.12 seconds
Started May 30 02:09:53 PM PDT 24
Finished May 30 02:09:59 PM PDT 24
Peak memory 209576 kb
Host smart-c58b980a-ce5d-48b3-b6d5-a96a1650aad2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163249348 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_access.163249348
Directory /workspace/3.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_errors.4210469068
Short name T287
Test name
Test status
Simulation time 5095174851 ps
CPU time 36.42 seconds
Started May 30 02:09:54 PM PDT 24
Finished May 30 02:10:32 PM PDT 24
Peak memory 218976 kb
Host smart-59a6dc03-0a2a-4ada-b40d-4b9d45f12dec
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210469068 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_er
rors.4210469068
Directory /workspace/3.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_priority.4046199095
Short name T21
Test name
Test status
Simulation time 3004692696 ps
CPU time 64.36 seconds
Started May 30 02:09:55 PM PDT 24
Finished May 30 02:11:00 PM PDT 24
Peak memory 217804 kb
Host smart-ba27dbbe-0e9e-41be-b506-ff0b87718203
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046199095 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_priority.4
046199095
Directory /workspace/3.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_prog_failure.1628151798
Short name T544
Test name
Test status
Simulation time 575724072 ps
CPU time 4.16 seconds
Started May 30 02:09:56 PM PDT 24
Finished May 30 02:10:01 PM PDT 24
Peak memory 217968 kb
Host smart-d1fc421a-fffe-4942-8581-d0365beda290
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628151798 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag
_prog_failure.1628151798
Directory /workspace/3.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_regwen_during_op.134555177
Short name T782
Test name
Test status
Simulation time 3688478669 ps
CPU time 14.91 seconds
Started May 30 02:09:53 PM PDT 24
Finished May 30 02:10:09 PM PDT 24
Peak memory 217740 kb
Host smart-9e8ab170-57d1-45ce-8d03-3db32b0f3f4e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134555177 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_j
tag_regwen_during_op.134555177
Directory /workspace/3.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_smoke.3920344324
Short name T317
Test name
Test status
Simulation time 356162643 ps
CPU time 9.91 seconds
Started May 30 02:09:56 PM PDT 24
Finished May 30 02:10:07 PM PDT 24
Peak memory 217760 kb
Host smart-02b89cc5-724a-4b0f-8228-efe9497c5c01
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920344324 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_smoke.
3920344324
Directory /workspace/3.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_failure.4010800255
Short name T412
Test name
Test status
Simulation time 13336740556 ps
CPU time 52.28 seconds
Started May 30 02:09:52 PM PDT 24
Finished May 30 02:10:46 PM PDT 24
Peak memory 281800 kb
Host smart-2fe20cbe-5b25-4025-aef5-6c2eab62db79
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010800255 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jta
g_state_failure.4010800255
Directory /workspace/3.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_post_trans.3115048860
Short name T793
Test name
Test status
Simulation time 2629558252 ps
CPU time 17.22 seconds
Started May 30 02:09:59 PM PDT 24
Finished May 30 02:10:17 PM PDT 24
Peak memory 246268 kb
Host smart-f8de5847-458c-4a9d-8742-8289b0ff9464
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115048860 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_state_post_trans.3115048860
Directory /workspace/3.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_regwen_during_op.57865473
Short name T29
Test name
Test status
Simulation time 419866627 ps
CPU time 12.53 seconds
Started May 30 02:09:49 PM PDT 24
Finished May 30 02:10:03 PM PDT 24
Peak memory 217752 kb
Host smart-0a391c8a-8c30-4dcd-b9dc-21dc8fd1c84c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57865473 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_regwen_during_op.57865473
Directory /workspace/3.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_cm.2833687311
Short name T82
Test name
Test status
Simulation time 116729291 ps
CPU time 23.5 seconds
Started May 30 02:09:59 PM PDT 24
Finished May 30 02:10:24 PM PDT 24
Peak memory 281720 kb
Host smart-0aec248b-7df4-4596-b5f2-249e0943b99a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833687311 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_cm.2833687311
Directory /workspace/3.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_mubi.2938260530
Short name T403
Test name
Test status
Simulation time 341879056 ps
CPU time 14.99 seconds
Started May 30 02:10:00 PM PDT 24
Finished May 30 02:10:16 PM PDT 24
Peak memory 218976 kb
Host smart-4efedc5a-cd8b-475e-ac36-c93dffcf445a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938260530 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_mubi.2938260530
Directory /workspace/3.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_digest.1152593926
Short name T619
Test name
Test status
Simulation time 1497027878 ps
CPU time 15.43 seconds
Started May 30 02:09:55 PM PDT 24
Finished May 30 02:10:12 PM PDT 24
Peak memory 226040 kb
Host smart-fa8ed64b-3fcd-4500-996a-750d6aa5bc8e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152593926 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_di
gest.1152593926
Directory /workspace/3.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/3.lc_ctrl_security_escalation.14183766
Short name T405
Test name
Test status
Simulation time 1584115676 ps
CPU time 10.06 seconds
Started May 30 02:09:54 PM PDT 24
Finished May 30 02:10:05 PM PDT 24
Peak memory 218232 kb
Host smart-5f9e8145-1d18-486c-ad26-5241bfbc4861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14183766 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_security_escalation.14183766
Directory /workspace/3.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/3.lc_ctrl_smoke.214095422
Short name T847
Test name
Test status
Simulation time 73999571 ps
CPU time 0.98 seconds
Started May 30 02:09:49 PM PDT 24
Finished May 30 02:09:51 PM PDT 24
Peak memory 217648 kb
Host smart-af078e12-1e3d-4372-be98-d3492dd88160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214095422 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_smoke.214095422
Directory /workspace/3.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_failure.2143330640
Short name T352
Test name
Test status
Simulation time 581650607 ps
CPU time 28.1 seconds
Started May 30 02:09:51 PM PDT 24
Finished May 30 02:10:20 PM PDT 24
Peak memory 251040 kb
Host smart-0ccf7bf9-82a5-42df-b16c-da229b694495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143330640 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_failure.2143330640
Directory /workspace/3.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_post_trans.658778495
Short name T247
Test name
Test status
Simulation time 369355181 ps
CPU time 7.09 seconds
Started May 30 02:09:52 PM PDT 24
Finished May 30 02:10:01 PM PDT 24
Peak memory 248612 kb
Host smart-24b406ea-2022-4c1f-a856-3bf79280cbeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658778495 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_post_trans.658778495
Directory /workspace/3.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_stress_all.2821748999
Short name T85
Test name
Test status
Simulation time 4680318650 ps
CPU time 167.43 seconds
Started May 30 02:09:56 PM PDT 24
Finished May 30 02:12:45 PM PDT 24
Peak memory 251152 kb
Host smart-b1e32804-cac4-4454-929f-4cba8a952137
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821748999 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.lc_ctrl_stress_all.2821748999
Directory /workspace/3.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.lc_ctrl_volatile_unlock_smoke.4066594256
Short name T393
Test name
Test status
Simulation time 36854549 ps
CPU time 0.88 seconds
Started May 30 02:09:59 PM PDT 24
Finished May 30 02:10:01 PM PDT 24
Peak memory 208596 kb
Host smart-ec24d4a0-1394-415b-85f1-665f37b28eb6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066594256 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ct
rl_volatile_unlock_smoke.4066594256
Directory /workspace/3.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_alert_test.2868414700
Short name T114
Test name
Test status
Simulation time 11599221 ps
CPU time 0.8 seconds
Started May 30 02:11:49 PM PDT 24
Finished May 30 02:11:51 PM PDT 24
Peak memory 208508 kb
Host smart-6bc4dd26-2e30-4bbb-82a2-264f50fb427c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868414700 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_alert_test.2868414700
Directory /workspace/30.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.lc_ctrl_errors.1865115338
Short name T643
Test name
Test status
Simulation time 374555011 ps
CPU time 12.41 seconds
Started May 30 02:12:00 PM PDT 24
Finished May 30 02:12:13 PM PDT 24
Peak memory 217360 kb
Host smart-457d940c-e34d-48dc-9cfe-059f723e5136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865115338 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_errors.1865115338
Directory /workspace/30.lc_ctrl_errors/latest

Test location /workspace/coverage/default/30.lc_ctrl_jtag_access.219111164
Short name T568
Test name
Test status
Simulation time 191126432 ps
CPU time 1.95 seconds
Started May 30 02:11:49 PM PDT 24
Finished May 30 02:11:52 PM PDT 24
Peak memory 209544 kb
Host smart-f6c421f7-9a0e-4e28-92e7-a0a3a39611e8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219111164 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_jtag_access.219111164
Directory /workspace/30.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/30.lc_ctrl_prog_failure.3747871711
Short name T698
Test name
Test status
Simulation time 70792161 ps
CPU time 3.05 seconds
Started May 30 02:11:39 PM PDT 24
Finished May 30 02:11:43 PM PDT 24
Peak memory 218108 kb
Host smart-91dcdef3-fe3f-4f07-b32a-194f1b1bad17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747871711 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_prog_failure.3747871711
Directory /workspace/30.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_mubi.456715748
Short name T353
Test name
Test status
Simulation time 436753038 ps
CPU time 9.1 seconds
Started May 30 02:11:47 PM PDT 24
Finished May 30 02:11:58 PM PDT 24
Peak memory 218320 kb
Host smart-fef11d61-10bc-4451-9a2c-cf9d97b42a46
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456715748 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_mubi.456715748
Directory /workspace/30.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_digest.1323406213
Short name T233
Test name
Test status
Simulation time 525451154 ps
CPU time 13.03 seconds
Started May 30 02:11:49 PM PDT 24
Finished May 30 02:12:03 PM PDT 24
Peak memory 226148 kb
Host smart-6d4dce49-0e72-456d-800c-ef6234f2d5c7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323406213 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_d
igest.1323406213
Directory /workspace/30.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_mux.3149188722
Short name T71
Test name
Test status
Simulation time 696138787 ps
CPU time 9.18 seconds
Started May 30 02:12:02 PM PDT 24
Finished May 30 02:12:13 PM PDT 24
Peak memory 218084 kb
Host smart-23b89119-a70e-4f7f-ba31-44a8e4c11dfa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149188722 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_mux.
3149188722
Directory /workspace/30.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/30.lc_ctrl_security_escalation.1715059751
Short name T444
Test name
Test status
Simulation time 314171155 ps
CPU time 9.78 seconds
Started May 30 02:11:49 PM PDT 24
Finished May 30 02:12:00 PM PDT 24
Peak memory 218080 kb
Host smart-bbc11c58-d6e8-4bfe-b12d-1b6e5d2b9384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715059751 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_security_escalation.1715059751
Directory /workspace/30.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/30.lc_ctrl_smoke.578581449
Short name T686
Test name
Test status
Simulation time 28266891 ps
CPU time 2.05 seconds
Started May 30 02:11:46 PM PDT 24
Finished May 30 02:11:49 PM PDT 24
Peak memory 214008 kb
Host smart-9bf0f555-4ae1-412c-ae2b-5a1fd0ae0884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578581449 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_smoke.578581449
Directory /workspace/30.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_failure.3821212083
Short name T581
Test name
Test status
Simulation time 343435268 ps
CPU time 39.92 seconds
Started May 30 02:11:43 PM PDT 24
Finished May 30 02:12:24 PM PDT 24
Peak memory 250884 kb
Host smart-4c48be05-6ed0-4b53-84c4-7031d95ca58b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821212083 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_failure.3821212083
Directory /workspace/30.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_post_trans.371950534
Short name T355
Test name
Test status
Simulation time 63487374 ps
CPU time 8.78 seconds
Started May 30 02:11:46 PM PDT 24
Finished May 30 02:11:55 PM PDT 24
Peak memory 251000 kb
Host smart-99a07411-3c46-4776-83ac-434709268857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371950534 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_post_trans.371950534
Directory /workspace/30.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all.4264271074
Short name T820
Test name
Test status
Simulation time 24769283119 ps
CPU time 142.68 seconds
Started May 30 02:11:49 PM PDT 24
Finished May 30 02:14:13 PM PDT 24
Peak memory 267440 kb
Host smart-9d38abc9-290c-495d-9f37-8a44458c40cd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264271074 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.lc_ctrl_stress_all.4264271074
Directory /workspace/30.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all_with_rand_reset.897196709
Short name T626
Test name
Test status
Simulation time 44431029401 ps
CPU time 522.27 seconds
Started May 30 02:12:00 PM PDT 24
Finished May 30 02:20:43 PM PDT 24
Peak memory 496304 kb
Host smart-a0745981-46ad-4f25-85be-579ebe3f6436
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=897196709 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_stress_all_with_rand_reset.897196709
Directory /workspace/30.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.lc_ctrl_volatile_unlock_smoke.2329226523
Short name T590
Test name
Test status
Simulation time 48110293 ps
CPU time 0.91 seconds
Started May 30 02:11:45 PM PDT 24
Finished May 30 02:11:47 PM PDT 24
Peak memory 211592 kb
Host smart-403fcd00-fdc9-41f3-92e7-f20ef652b0a5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329226523 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_c
trl_volatile_unlock_smoke.2329226523
Directory /workspace/30.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_alert_test.3228095530
Short name T500
Test name
Test status
Simulation time 32691248 ps
CPU time 0.94 seconds
Started May 30 02:11:54 PM PDT 24
Finished May 30 02:11:57 PM PDT 24
Peak memory 208720 kb
Host smart-2a917b14-baef-42fe-b4a9-b1b8fd1e14b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228095530 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_alert_test.3228095530
Directory /workspace/31.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.lc_ctrl_errors.3695018157
Short name T706
Test name
Test status
Simulation time 631587853 ps
CPU time 19.95 seconds
Started May 30 02:11:47 PM PDT 24
Finished May 30 02:12:09 PM PDT 24
Peak memory 217992 kb
Host smart-1681fc83-6319-477b-ba01-4d23803745f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695018157 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_errors.3695018157
Directory /workspace/31.lc_ctrl_errors/latest

Test location /workspace/coverage/default/31.lc_ctrl_jtag_access.1168184839
Short name T314
Test name
Test status
Simulation time 514453355 ps
CPU time 1.56 seconds
Started May 30 02:12:00 PM PDT 24
Finished May 30 02:12:02 PM PDT 24
Peak memory 209536 kb
Host smart-d3a44e19-cce4-4ce8-be28-97133f2a37e2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168184839 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_jtag_access.1168184839
Directory /workspace/31.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/31.lc_ctrl_prog_failure.3721515983
Short name T832
Test name
Test status
Simulation time 70336343 ps
CPU time 1.45 seconds
Started May 30 02:11:47 PM PDT 24
Finished May 30 02:11:50 PM PDT 24
Peak memory 218080 kb
Host smart-7c7ce8db-fc36-470f-b8c2-f9ba57e0e23f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721515983 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_prog_failure.3721515983
Directory /workspace/31.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_mubi.1718105640
Short name T497
Test name
Test status
Simulation time 639528700 ps
CPU time 14.33 seconds
Started May 30 02:11:55 PM PDT 24
Finished May 30 02:12:10 PM PDT 24
Peak memory 218980 kb
Host smart-1036773a-20c2-40d2-914b-86d62c870f1f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718105640 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_mubi.1718105640
Directory /workspace/31.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_digest.1347945590
Short name T827
Test name
Test status
Simulation time 803871027 ps
CPU time 18.42 seconds
Started May 30 02:11:50 PM PDT 24
Finished May 30 02:12:10 PM PDT 24
Peak memory 226020 kb
Host smart-99d03896-904c-4b8c-8e88-d0e9c59bdb07
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347945590 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_d
igest.1347945590
Directory /workspace/31.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_mux.1137044554
Short name T303
Test name
Test status
Simulation time 316988771 ps
CPU time 11.33 seconds
Started May 30 02:11:47 PM PDT 24
Finished May 30 02:11:59 PM PDT 24
Peak memory 218072 kb
Host smart-f45f6bd3-0979-4f17-b0c4-ab750a7655ca
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137044554 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_mux.
1137044554
Directory /workspace/31.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/31.lc_ctrl_security_escalation.3239784743
Short name T714
Test name
Test status
Simulation time 733023635 ps
CPU time 12.76 seconds
Started May 30 02:11:50 PM PDT 24
Finished May 30 02:12:04 PM PDT 24
Peak memory 218192 kb
Host smart-d8919a2f-9840-4ecf-8970-2995d6ed84dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239784743 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_security_escalation.3239784743
Directory /workspace/31.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/31.lc_ctrl_smoke.2164752866
Short name T366
Test name
Test status
Simulation time 330634228 ps
CPU time 3.22 seconds
Started May 30 02:12:02 PM PDT 24
Finished May 30 02:12:07 PM PDT 24
Peak memory 217752 kb
Host smart-e365a61f-e54e-477d-ac7c-e05b94cad9bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164752866 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_smoke.2164752866
Directory /workspace/31.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_failure.2832719602
Short name T609
Test name
Test status
Simulation time 195782061 ps
CPU time 22.07 seconds
Started May 30 02:11:49 PM PDT 24
Finished May 30 02:12:12 PM PDT 24
Peak memory 251104 kb
Host smart-1918f1fe-8c21-4546-a1e3-24296b54f6fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832719602 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_failure.2832719602
Directory /workspace/31.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_post_trans.1777666299
Short name T354
Test name
Test status
Simulation time 65510076 ps
CPU time 8.47 seconds
Started May 30 02:11:56 PM PDT 24
Finished May 30 02:12:05 PM PDT 24
Peak memory 251012 kb
Host smart-4494418d-751c-455e-b1ba-95f7b5be08e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777666299 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_post_trans.1777666299
Directory /workspace/31.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/31.lc_ctrl_stress_all.193699221
Short name T585
Test name
Test status
Simulation time 3399941398 ps
CPU time 82.1 seconds
Started May 30 02:11:49 PM PDT 24
Finished May 30 02:13:13 PM PDT 24
Peak memory 268944 kb
Host smart-04ece77a-3b7f-4734-8b29-0c7b5dfb40d1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193699221 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.lc_ctrl_stress_all.193699221
Directory /workspace/31.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.lc_ctrl_volatile_unlock_smoke.695522625
Short name T862
Test name
Test status
Simulation time 72376297 ps
CPU time 0.9 seconds
Started May 30 02:12:00 PM PDT 24
Finished May 30 02:12:02 PM PDT 24
Peak memory 207940 kb
Host smart-b38c3f1e-6095-4ee7-9e0b-b3df7152aece
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695522625 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ct
rl_volatile_unlock_smoke.695522625
Directory /workspace/31.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_alert_test.704666329
Short name T579
Test name
Test status
Simulation time 33561837 ps
CPU time 0.93 seconds
Started May 30 02:11:49 PM PDT 24
Finished May 30 02:11:51 PM PDT 24
Peak memory 208680 kb
Host smart-2aab0186-ee87-4568-9aa4-c72431c85d99
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704666329 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_alert_test.704666329
Directory /workspace/32.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.lc_ctrl_errors.629502154
Short name T424
Test name
Test status
Simulation time 1571770010 ps
CPU time 17.99 seconds
Started May 30 02:11:48 PM PDT 24
Finished May 30 02:12:08 PM PDT 24
Peak memory 218000 kb
Host smart-85ac47a8-da77-4ecc-97ed-0b393cf1de6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629502154 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_errors.629502154
Directory /workspace/32.lc_ctrl_errors/latest

Test location /workspace/coverage/default/32.lc_ctrl_jtag_access.2097876683
Short name T363
Test name
Test status
Simulation time 601687843 ps
CPU time 3.53 seconds
Started May 30 02:11:48 PM PDT 24
Finished May 30 02:11:53 PM PDT 24
Peak memory 209576 kb
Host smart-bf55aa20-06dc-4de8-9048-65e9039725e2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097876683 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_jtag_access.2097876683
Directory /workspace/32.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/32.lc_ctrl_prog_failure.152039208
Short name T639
Test name
Test status
Simulation time 424664165 ps
CPU time 2.36 seconds
Started May 30 02:11:52 PM PDT 24
Finished May 30 02:11:55 PM PDT 24
Peak memory 218084 kb
Host smart-c42b76d8-2f24-4bbf-aff4-a36b3fd2618e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152039208 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_prog_failure.152039208
Directory /workspace/32.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_mubi.4040629816
Short name T817
Test name
Test status
Simulation time 232453063 ps
CPU time 8.08 seconds
Started May 30 02:11:51 PM PDT 24
Finished May 30 02:12:01 PM PDT 24
Peak memory 225532 kb
Host smart-dd1e0039-b7d4-40e8-8efd-20cbc05118d4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040629816 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_mubi.4040629816
Directory /workspace/32.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_digest.2398711202
Short name T413
Test name
Test status
Simulation time 1717065924 ps
CPU time 10.97 seconds
Started May 30 02:12:02 PM PDT 24
Finished May 30 02:12:14 PM PDT 24
Peak memory 217976 kb
Host smart-cf4244c6-8612-4d35-8189-f3579629df90
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398711202 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_d
igest.2398711202
Directory /workspace/32.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_mux.2301332214
Short name T469
Test name
Test status
Simulation time 266077007 ps
CPU time 7.77 seconds
Started May 30 02:11:50 PM PDT 24
Finished May 30 02:11:59 PM PDT 24
Peak memory 218128 kb
Host smart-e0812161-1bbe-440a-bbb1-5e0fa38d9eee
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301332214 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_mux.
2301332214
Directory /workspace/32.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/32.lc_ctrl_security_escalation.2520602632
Short name T517
Test name
Test status
Simulation time 486017049 ps
CPU time 10.63 seconds
Started May 30 02:11:54 PM PDT 24
Finished May 30 02:12:06 PM PDT 24
Peak memory 218132 kb
Host smart-0f89ebfe-9e01-4b86-863d-48455889a266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520602632 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_security_escalation.2520602632
Directory /workspace/32.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/32.lc_ctrl_smoke.2496831206
Short name T232
Test name
Test status
Simulation time 93018703 ps
CPU time 1.79 seconds
Started May 30 02:11:51 PM PDT 24
Finished May 30 02:11:54 PM PDT 24
Peak memory 214016 kb
Host smart-8fc68b4c-3119-432f-a241-614824c4cc8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496831206 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_smoke.2496831206
Directory /workspace/32.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_failure.3944731958
Short name T267
Test name
Test status
Simulation time 922562020 ps
CPU time 33.68 seconds
Started May 30 02:11:53 PM PDT 24
Finished May 30 02:12:28 PM PDT 24
Peak memory 251132 kb
Host smart-dc4e2b40-a4b7-40c0-b0aa-7932de292287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944731958 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_failure.3944731958
Directory /workspace/32.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_post_trans.2126778088
Short name T601
Test name
Test status
Simulation time 93095825 ps
CPU time 7.81 seconds
Started May 30 02:11:54 PM PDT 24
Finished May 30 02:12:04 PM PDT 24
Peak memory 251032 kb
Host smart-33afda70-5fc2-4bb8-963c-37303150032f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126778088 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_post_trans.2126778088
Directory /workspace/32.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all.3280381282
Short name T648
Test name
Test status
Simulation time 13456535255 ps
CPU time 233.89 seconds
Started May 30 02:11:55 PM PDT 24
Finished May 30 02:15:50 PM PDT 24
Peak memory 283828 kb
Host smart-77952ec7-4aea-4a3d-b105-ceadfbedceed
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280381282 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.lc_ctrl_stress_all.3280381282
Directory /workspace/32.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.lc_ctrl_volatile_unlock_smoke.322404627
Short name T498
Test name
Test status
Simulation time 16883971 ps
CPU time 0.86 seconds
Started May 30 02:11:52 PM PDT 24
Finished May 30 02:11:54 PM PDT 24
Peak memory 208588 kb
Host smart-385a6085-34e3-4380-bc80-fff7f047c8bf
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322404627 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ct
rl_volatile_unlock_smoke.322404627
Directory /workspace/32.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_alert_test.1149992149
Short name T454
Test name
Test status
Simulation time 26342505 ps
CPU time 0.96 seconds
Started May 30 02:11:55 PM PDT 24
Finished May 30 02:11:57 PM PDT 24
Peak memory 208708 kb
Host smart-136a879a-3e6e-40ce-8e50-d2c25cf277ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149992149 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_alert_test.1149992149
Directory /workspace/33.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.lc_ctrl_errors.4021491222
Short name T55
Test name
Test status
Simulation time 414519807 ps
CPU time 13.73 seconds
Started May 30 02:11:54 PM PDT 24
Finished May 30 02:12:09 PM PDT 24
Peak memory 217992 kb
Host smart-a2777233-f277-4044-929d-3c38f5240181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021491222 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_errors.4021491222
Directory /workspace/33.lc_ctrl_errors/latest

Test location /workspace/coverage/default/33.lc_ctrl_jtag_access.3251904864
Short name T5
Test name
Test status
Simulation time 308155379 ps
CPU time 1.45 seconds
Started May 30 02:11:50 PM PDT 24
Finished May 30 02:11:53 PM PDT 24
Peak memory 209584 kb
Host smart-c31f7ad5-1071-49f9-a93c-d2e6b6e9a12c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251904864 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_jtag_access.3251904864
Directory /workspace/33.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/33.lc_ctrl_prog_failure.2105744544
Short name T859
Test name
Test status
Simulation time 75705857 ps
CPU time 3.8 seconds
Started May 30 02:11:59 PM PDT 24
Finished May 30 02:12:04 PM PDT 24
Peak memory 218032 kb
Host smart-0437af5d-142d-4c7d-8267-76c9cf62ba84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105744544 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_prog_failure.2105744544
Directory /workspace/33.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_mubi.1885478982
Short name T15
Test name
Test status
Simulation time 5196305868 ps
CPU time 11.69 seconds
Started May 30 02:11:50 PM PDT 24
Finished May 30 02:12:03 PM PDT 24
Peak memory 219252 kb
Host smart-be28f8b1-7331-4745-aa56-dc68e1aa7e84
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885478982 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_mubi.1885478982
Directory /workspace/33.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_digest.1601476375
Short name T702
Test name
Test status
Simulation time 1408603720 ps
CPU time 14.19 seconds
Started May 30 02:11:52 PM PDT 24
Finished May 30 02:12:07 PM PDT 24
Peak memory 217992 kb
Host smart-7200ea99-e24d-4db7-aba3-f4b15e304730
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601476375 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_d
igest.1601476375
Directory /workspace/33.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_mux.896110288
Short name T481
Test name
Test status
Simulation time 4018230770 ps
CPU time 8.63 seconds
Started May 30 02:11:54 PM PDT 24
Finished May 30 02:12:04 PM PDT 24
Peak memory 218112 kb
Host smart-cde36f9a-102b-46d2-9464-9e33da2d67b9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896110288 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_mux.896110288
Directory /workspace/33.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/33.lc_ctrl_security_escalation.705909007
Short name T414
Test name
Test status
Simulation time 1678821291 ps
CPU time 9.57 seconds
Started May 30 02:11:52 PM PDT 24
Finished May 30 02:12:03 PM PDT 24
Peak memory 218212 kb
Host smart-3a435ad1-b5fd-4a47-a8d7-4a0980b21175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705909007 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_security_escalation.705909007
Directory /workspace/33.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/33.lc_ctrl_smoke.2663331366
Short name T116
Test name
Test status
Simulation time 155719165 ps
CPU time 4.52 seconds
Started May 30 02:11:49 PM PDT 24
Finished May 30 02:11:55 PM PDT 24
Peak memory 217828 kb
Host smart-25987957-22b1-447a-8c26-92a2fe78fc15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663331366 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_smoke.2663331366
Directory /workspace/33.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_failure.2597497550
Short name T236
Test name
Test status
Simulation time 2074993176 ps
CPU time 18.65 seconds
Started May 30 02:12:00 PM PDT 24
Finished May 30 02:12:20 PM PDT 24
Peak memory 251068 kb
Host smart-57f7d3e5-62e7-45df-b057-2b1adafcbeeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597497550 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_failure.2597497550
Directory /workspace/33.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_post_trans.2665648083
Short name T540
Test name
Test status
Simulation time 55855669 ps
CPU time 9.71 seconds
Started May 30 02:11:56 PM PDT 24
Finished May 30 02:12:06 PM PDT 24
Peak memory 251024 kb
Host smart-46d43ed4-7cb7-4bd9-ba16-8cbe20b10948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665648083 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_post_trans.2665648083
Directory /workspace/33.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all.1916688652
Short name T802
Test name
Test status
Simulation time 3298551032 ps
CPU time 74.06 seconds
Started May 30 02:12:02 PM PDT 24
Finished May 30 02:13:17 PM PDT 24
Peak memory 251076 kb
Host smart-a6e75111-35dd-412a-a9cc-91013533ad6e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916688652 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.lc_ctrl_stress_all.1916688652
Directory /workspace/33.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.lc_ctrl_volatile_unlock_smoke.86567013
Short name T567
Test name
Test status
Simulation time 18071820 ps
CPU time 0.93 seconds
Started May 30 02:11:56 PM PDT 24
Finished May 30 02:11:57 PM PDT 24
Peak memory 211620 kb
Host smart-fd327410-e048-4524-b489-96fabd66de55
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86567013 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vol
atile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctr
l_volatile_unlock_smoke.86567013
Directory /workspace/33.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_alert_test.1463939140
Short name T371
Test name
Test status
Simulation time 101778094 ps
CPU time 1.05 seconds
Started May 30 02:11:54 PM PDT 24
Finished May 30 02:11:56 PM PDT 24
Peak memory 208688 kb
Host smart-1fa114d8-5344-4c6e-a469-24fd97b336fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463939140 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_alert_test.1463939140
Directory /workspace/34.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.lc_ctrl_errors.1973693976
Short name T681
Test name
Test status
Simulation time 1684964625 ps
CPU time 10.09 seconds
Started May 30 02:11:53 PM PDT 24
Finished May 30 02:12:05 PM PDT 24
Peak memory 217992 kb
Host smart-c445c65f-fb1e-4560-9a97-7d61fdf177dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973693976 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_errors.1973693976
Directory /workspace/34.lc_ctrl_errors/latest

Test location /workspace/coverage/default/34.lc_ctrl_jtag_access.3288834070
Short name T11
Test name
Test status
Simulation time 416393011 ps
CPU time 3.51 seconds
Started May 30 02:11:53 PM PDT 24
Finished May 30 02:11:58 PM PDT 24
Peak memory 216952 kb
Host smart-e8403c94-e599-4998-8d92-27d398c830ee
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288834070 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_jtag_access.3288834070
Directory /workspace/34.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/34.lc_ctrl_prog_failure.2005996268
Short name T460
Test name
Test status
Simulation time 75217659 ps
CPU time 2.81 seconds
Started May 30 02:12:02 PM PDT 24
Finished May 30 02:12:06 PM PDT 24
Peak memory 218036 kb
Host smart-ae5586ec-977a-4992-8358-fdd5fbc23f9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005996268 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_prog_failure.2005996268
Directory /workspace/34.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_mubi.4242558278
Short name T290
Test name
Test status
Simulation time 201880490 ps
CPU time 9.52 seconds
Started May 30 02:11:54 PM PDT 24
Finished May 30 02:12:04 PM PDT 24
Peak memory 226128 kb
Host smart-b8a637a4-b858-4dd2-9f2a-eb78cf46be24
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242558278 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_mubi.4242558278
Directory /workspace/34.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_digest.3117907589
Short name T525
Test name
Test status
Simulation time 249740030 ps
CPU time 9.05 seconds
Started May 30 02:11:54 PM PDT 24
Finished May 30 02:12:04 PM PDT 24
Peak memory 217932 kb
Host smart-d821169b-5dbd-42f9-98d2-712da4a162c0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117907589 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_d
igest.3117907589
Directory /workspace/34.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_mux.3122405308
Short name T825
Test name
Test status
Simulation time 1154418095 ps
CPU time 8.35 seconds
Started May 30 02:12:02 PM PDT 24
Finished May 30 02:12:11 PM PDT 24
Peak memory 218120 kb
Host smart-4dbd493f-fac7-4e76-885c-ec6bb1661c59
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122405308 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_mux.
3122405308
Directory /workspace/34.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/34.lc_ctrl_security_escalation.3854096856
Short name T697
Test name
Test status
Simulation time 994748864 ps
CPU time 7.51 seconds
Started May 30 02:11:53 PM PDT 24
Finished May 30 02:12:02 PM PDT 24
Peak memory 218060 kb
Host smart-18c706b2-f2e0-470d-9014-fd23ca855483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3854096856 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_security_escalation.3854096856
Directory /workspace/34.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/34.lc_ctrl_smoke.1454339942
Short name T867
Test name
Test status
Simulation time 311257965 ps
CPU time 2.62 seconds
Started May 30 02:11:50 PM PDT 24
Finished May 30 02:11:54 PM PDT 24
Peak memory 214252 kb
Host smart-e5833889-5208-4d7b-bdc1-b5a5d6030e17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454339942 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_smoke.1454339942
Directory /workspace/34.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_failure.3844996106
Short name T37
Test name
Test status
Simulation time 158578072 ps
CPU time 21.15 seconds
Started May 30 02:11:53 PM PDT 24
Finished May 30 02:12:16 PM PDT 24
Peak memory 251044 kb
Host smart-e0b7fa41-a501-4925-9342-b3e3b7ffb403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844996106 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_failure.3844996106
Directory /workspace/34.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_post_trans.3723123125
Short name T659
Test name
Test status
Simulation time 438503798 ps
CPU time 7.37 seconds
Started May 30 02:11:51 PM PDT 24
Finished May 30 02:11:59 PM PDT 24
Peak memory 250988 kb
Host smart-265441c5-4667-4468-8b8c-b8b43ed4b926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723123125 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_post_trans.3723123125
Directory /workspace/34.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all.1331296284
Short name T193
Test name
Test status
Simulation time 1840512620 ps
CPU time 60.41 seconds
Started May 30 02:11:54 PM PDT 24
Finished May 30 02:12:55 PM PDT 24
Peak memory 269688 kb
Host smart-2ed09f90-7299-4407-a709-b9a021e25a16
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331296284 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.lc_ctrl_stress_all.1331296284
Directory /workspace/34.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.lc_ctrl_volatile_unlock_smoke.15563710
Short name T47
Test name
Test status
Simulation time 17665674 ps
CPU time 1.21 seconds
Started May 30 02:11:53 PM PDT 24
Finished May 30 02:11:55 PM PDT 24
Peak memory 212612 kb
Host smart-f5b758d4-20ae-41ed-ad41-26c587cefd33
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15563710 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vol
atile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctr
l_volatile_unlock_smoke.15563710
Directory /workspace/34.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_alert_test.3000030220
Short name T359
Test name
Test status
Simulation time 45891090 ps
CPU time 1.01 seconds
Started May 30 02:12:01 PM PDT 24
Finished May 30 02:12:05 PM PDT 24
Peak memory 208792 kb
Host smart-d4748194-e188-4464-be86-446de94163bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000030220 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_alert_test.3000030220
Directory /workspace/35.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.lc_ctrl_errors.3076395794
Short name T744
Test name
Test status
Simulation time 2609074138 ps
CPU time 18.63 seconds
Started May 30 02:11:57 PM PDT 24
Finished May 30 02:12:17 PM PDT 24
Peak memory 218096 kb
Host smart-e83f5757-9312-4340-b282-be3c30560c62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076395794 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_errors.3076395794
Directory /workspace/35.lc_ctrl_errors/latest

Test location /workspace/coverage/default/35.lc_ctrl_jtag_access.3946655072
Short name T722
Test name
Test status
Simulation time 1101746479 ps
CPU time 26.98 seconds
Started May 30 02:12:00 PM PDT 24
Finished May 30 02:12:28 PM PDT 24
Peak memory 209520 kb
Host smart-1b7e0be7-7abb-4c71-b108-020a709193d5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946655072 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_jtag_access.3946655072
Directory /workspace/35.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/35.lc_ctrl_prog_failure.3073782358
Short name T735
Test name
Test status
Simulation time 68186421 ps
CPU time 2.71 seconds
Started May 30 02:11:58 PM PDT 24
Finished May 30 02:12:02 PM PDT 24
Peak memory 218132 kb
Host smart-8e9969cc-0d5e-4c08-bf72-3b6a6dfc18b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073782358 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_prog_failure.3073782358
Directory /workspace/35.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_mubi.763764080
Short name T38
Test name
Test status
Simulation time 1398026516 ps
CPU time 11.63 seconds
Started May 30 02:12:05 PM PDT 24
Finished May 30 02:12:17 PM PDT 24
Peak memory 218952 kb
Host smart-3464c912-8dd1-4a69-8bc3-564fdcac0b24
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763764080 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_mubi.763764080
Directory /workspace/35.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_digest.1803431571
Short name T187
Test name
Test status
Simulation time 389864315 ps
CPU time 14.92 seconds
Started May 30 02:12:02 PM PDT 24
Finished May 30 02:12:18 PM PDT 24
Peak memory 217996 kb
Host smart-f4a0328e-9af7-44fe-bf7d-b90faed75875
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803431571 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_d
igest.1803431571
Directory /workspace/35.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_mux.2775071770
Short name T432
Test name
Test status
Simulation time 778092404 ps
CPU time 16 seconds
Started May 30 02:12:01 PM PDT 24
Finished May 30 02:12:18 PM PDT 24
Peak memory 218148 kb
Host smart-cbae75a4-1936-45d8-8c51-f8910d686100
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775071770 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_mux.
2775071770
Directory /workspace/35.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/35.lc_ctrl_security_escalation.3783632017
Short name T67
Test name
Test status
Simulation time 582316088 ps
CPU time 11.68 seconds
Started May 30 02:12:02 PM PDT 24
Finished May 30 02:12:14 PM PDT 24
Peak memory 218120 kb
Host smart-9439270e-bd16-4f85-bcfc-8563e9978201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783632017 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_security_escalation.3783632017
Directory /workspace/35.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/35.lc_ctrl_smoke.3602095382
Short name T337
Test name
Test status
Simulation time 162406632 ps
CPU time 2.34 seconds
Started May 30 02:11:49 PM PDT 24
Finished May 30 02:11:52 PM PDT 24
Peak memory 213880 kb
Host smart-4e00ec86-0cf5-4ae0-8e59-3afd36d81437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602095382 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_smoke.3602095382
Directory /workspace/35.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_failure.451465933
Short name T443
Test name
Test status
Simulation time 1441818339 ps
CPU time 16.63 seconds
Started May 30 02:12:01 PM PDT 24
Finished May 30 02:12:19 PM PDT 24
Peak memory 251064 kb
Host smart-90a12589-6405-4cca-b1b5-c01073a9b307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451465933 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_failure.451465933
Directory /workspace/35.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_post_trans.3681103393
Short name T350
Test name
Test status
Simulation time 60255831 ps
CPU time 3.03 seconds
Started May 30 02:12:03 PM PDT 24
Finished May 30 02:12:07 PM PDT 24
Peak memory 217968 kb
Host smart-708ea6db-c79b-4f6c-bc07-9018de269296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681103393 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_post_trans.3681103393
Directory /workspace/35.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all.3218634965
Short name T713
Test name
Test status
Simulation time 7867089992 ps
CPU time 69.94 seconds
Started May 30 02:12:06 PM PDT 24
Finished May 30 02:13:17 PM PDT 24
Peak memory 267372 kb
Host smart-73043c2f-9cd5-4fce-96ad-c5c5b4e7409b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218634965 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.lc_ctrl_stress_all.3218634965
Directory /workspace/35.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.lc_ctrl_volatile_unlock_smoke.3144688344
Short name T48
Test name
Test status
Simulation time 37548563 ps
CPU time 0.82 seconds
Started May 30 02:12:02 PM PDT 24
Finished May 30 02:12:04 PM PDT 24
Peak memory 208416 kb
Host smart-379654c8-7572-40e3-80b9-242cc866747d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144688344 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_c
trl_volatile_unlock_smoke.3144688344
Directory /workspace/35.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_alert_test.610468606
Short name T84
Test name
Test status
Simulation time 74773517 ps
CPU time 1.14 seconds
Started May 30 02:12:06 PM PDT 24
Finished May 30 02:12:08 PM PDT 24
Peak memory 208624 kb
Host smart-b1116aa9-38ea-4083-a6a6-686a9a5f1a1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610468606 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_alert_test.610468606
Directory /workspace/36.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.lc_ctrl_errors.74717986
Short name T332
Test name
Test status
Simulation time 1583854395 ps
CPU time 14.9 seconds
Started May 30 02:12:00 PM PDT 24
Finished May 30 02:12:16 PM PDT 24
Peak memory 217980 kb
Host smart-98d8915b-391c-476e-91ac-f28a370c048f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74717986 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_errors.74717986
Directory /workspace/36.lc_ctrl_errors/latest

Test location /workspace/coverage/default/36.lc_ctrl_jtag_access.805395592
Short name T435
Test name
Test status
Simulation time 2219251379 ps
CPU time 13.67 seconds
Started May 30 02:11:58 PM PDT 24
Finished May 30 02:12:13 PM PDT 24
Peak memory 209560 kb
Host smart-1b72616d-7df0-4f78-ab42-cc0ff654040e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805395592 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_jtag_access.805395592
Directory /workspace/36.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/36.lc_ctrl_prog_failure.2273107072
Short name T510
Test name
Test status
Simulation time 170457268 ps
CPU time 3.99 seconds
Started May 30 02:11:59 PM PDT 24
Finished May 30 02:12:04 PM PDT 24
Peak memory 218124 kb
Host smart-b2e3704c-5f12-4cc8-b77c-019103cbb226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273107072 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_prog_failure.2273107072
Directory /workspace/36.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_mubi.2288846770
Short name T703
Test name
Test status
Simulation time 3975027473 ps
CPU time 11.38 seconds
Started May 30 02:12:03 PM PDT 24
Finished May 30 02:12:16 PM PDT 24
Peak memory 220180 kb
Host smart-a5506059-6254-4ea7-a36c-74e214c665e3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288846770 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_mubi.2288846770
Directory /workspace/36.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_digest.3839519293
Short name T560
Test name
Test status
Simulation time 1672533879 ps
CPU time 16.27 seconds
Started May 30 02:12:00 PM PDT 24
Finished May 30 02:12:17 PM PDT 24
Peak memory 226076 kb
Host smart-c2834856-83e8-4228-97b0-851ff87e5011
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839519293 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_d
igest.3839519293
Directory /workspace/36.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_mux.2820420129
Short name T310
Test name
Test status
Simulation time 400097918 ps
CPU time 10.54 seconds
Started May 30 02:12:10 PM PDT 24
Finished May 30 02:12:22 PM PDT 24
Peak memory 218044 kb
Host smart-8be17975-d2d9-4372-84f5-0e4916dfef65
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820420129 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_mux.
2820420129
Directory /workspace/36.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/36.lc_ctrl_security_escalation.4217663217
Short name T755
Test name
Test status
Simulation time 1586873792 ps
CPU time 6.95 seconds
Started May 30 02:12:01 PM PDT 24
Finished May 30 02:12:09 PM PDT 24
Peak memory 218068 kb
Host smart-6fea9b35-069a-48cc-9e80-33acac3dc2a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217663217 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_security_escalation.4217663217
Directory /workspace/36.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/36.lc_ctrl_smoke.2861876470
Short name T842
Test name
Test status
Simulation time 580478444 ps
CPU time 3.7 seconds
Started May 30 02:12:00 PM PDT 24
Finished May 30 02:12:04 PM PDT 24
Peak memory 214896 kb
Host smart-b399ef58-2be3-4fa9-92cf-fc4aa2ad1b4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861876470 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_smoke.2861876470
Directory /workspace/36.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_failure.2150269468
Short name T272
Test name
Test status
Simulation time 234552773 ps
CPU time 23.92 seconds
Started May 30 02:11:59 PM PDT 24
Finished May 30 02:12:24 PM PDT 24
Peak memory 250980 kb
Host smart-1e3ed538-6847-416b-916b-b45ba93fd3a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150269468 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_failure.2150269468
Directory /workspace/36.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_post_trans.4262250783
Short name T298
Test name
Test status
Simulation time 212316420 ps
CPU time 3.25 seconds
Started May 30 02:12:05 PM PDT 24
Finished May 30 02:12:09 PM PDT 24
Peak memory 222220 kb
Host smart-ee308a39-a8c5-4bfe-a9d8-04fa63ecdd5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262250783 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_post_trans.4262250783
Directory /workspace/36.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all.2660687177
Short name T800
Test name
Test status
Simulation time 11483389394 ps
CPU time 429.32 seconds
Started May 30 02:12:01 PM PDT 24
Finished May 30 02:19:11 PM PDT 24
Peak memory 275780 kb
Host smart-a09b8af5-e509-490a-939f-cdf247efbaa6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660687177 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.lc_ctrl_stress_all.2660687177
Directory /workspace/36.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.lc_ctrl_volatile_unlock_smoke.53972661
Short name T700
Test name
Test status
Simulation time 41335142 ps
CPU time 1.03 seconds
Started May 30 02:11:59 PM PDT 24
Finished May 30 02:12:01 PM PDT 24
Peak memory 211620 kb
Host smart-137937ca-66ec-4fbf-b332-75f8c16175d3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53972661 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vol
atile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctr
l_volatile_unlock_smoke.53972661
Directory /workspace/36.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_alert_test.3326262242
Short name T365
Test name
Test status
Simulation time 25650447 ps
CPU time 0.99 seconds
Started May 30 02:12:01 PM PDT 24
Finished May 30 02:12:03 PM PDT 24
Peak memory 208708 kb
Host smart-54e15552-9f08-4bc0-afab-247695244847
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326262242 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_alert_test.3326262242
Directory /workspace/37.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.lc_ctrl_errors.3417906276
Short name T868
Test name
Test status
Simulation time 1611461341 ps
CPU time 17.11 seconds
Started May 30 02:12:00 PM PDT 24
Finished May 30 02:12:18 PM PDT 24
Peak memory 218100 kb
Host smart-933dba29-e6e6-42cd-9954-b654cd5af2c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417906276 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_errors.3417906276
Directory /workspace/37.lc_ctrl_errors/latest

Test location /workspace/coverage/default/37.lc_ctrl_jtag_access.946450504
Short name T503
Test name
Test status
Simulation time 1502291733 ps
CPU time 11.65 seconds
Started May 30 02:11:59 PM PDT 24
Finished May 30 02:12:11 PM PDT 24
Peak memory 209580 kb
Host smart-4df995fd-3bcf-4446-8646-5e23cd7bd425
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946450504 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_jtag_access.946450504
Directory /workspace/37.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/37.lc_ctrl_prog_failure.980102806
Short name T3
Test name
Test status
Simulation time 107924657 ps
CPU time 2.62 seconds
Started May 30 02:12:02 PM PDT 24
Finished May 30 02:12:05 PM PDT 24
Peak memory 218076 kb
Host smart-a376b523-e8f9-4194-b850-7f89f3cd54ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980102806 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_prog_failure.980102806
Directory /workspace/37.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_mubi.2597673547
Short name T647
Test name
Test status
Simulation time 1664078980 ps
CPU time 13.96 seconds
Started May 30 02:12:06 PM PDT 24
Finished May 30 02:12:21 PM PDT 24
Peak memory 217964 kb
Host smart-81904650-e381-42f2-a4b5-16bd6bbb616f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597673547 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_mubi.2597673547
Directory /workspace/37.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_digest.3081063536
Short name T426
Test name
Test status
Simulation time 1585104208 ps
CPU time 13.86 seconds
Started May 30 02:12:06 PM PDT 24
Finished May 30 02:12:20 PM PDT 24
Peak memory 217920 kb
Host smart-24a6ef15-7e42-4e29-b8ec-4e728ce55943
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081063536 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_d
igest.3081063536
Directory /workspace/37.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_mux.3559835116
Short name T664
Test name
Test status
Simulation time 1086357139 ps
CPU time 24.2 seconds
Started May 30 02:12:05 PM PDT 24
Finished May 30 02:12:29 PM PDT 24
Peak memory 218008 kb
Host smart-accc2b3b-0453-4956-b9e0-0bafeb754dec
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559835116 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_mux.
3559835116
Directory /workspace/37.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/37.lc_ctrl_security_escalation.1283266334
Short name T809
Test name
Test status
Simulation time 1488455563 ps
CPU time 13.16 seconds
Started May 30 02:12:06 PM PDT 24
Finished May 30 02:12:20 PM PDT 24
Peak memory 218076 kb
Host smart-df6203e9-c121-4f60-acb1-30055d921734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283266334 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_security_escalation.1283266334
Directory /workspace/37.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/37.lc_ctrl_smoke.513563066
Short name T689
Test name
Test status
Simulation time 186949718 ps
CPU time 3.97 seconds
Started May 30 02:12:01 PM PDT 24
Finished May 30 02:12:06 PM PDT 24
Peak memory 217856 kb
Host smart-ec6ae427-0d01-4368-9d2e-020d4b3285f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513563066 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_smoke.513563066
Directory /workspace/37.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_failure.2634043779
Short name T768
Test name
Test status
Simulation time 711721375 ps
CPU time 30.59 seconds
Started May 30 02:12:01 PM PDT 24
Finished May 30 02:12:32 PM PDT 24
Peak memory 251016 kb
Host smart-cf396aca-917c-489d-9320-0778cf929389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634043779 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_failure.2634043779
Directory /workspace/37.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_post_trans.299033128
Short name T578
Test name
Test status
Simulation time 131391771 ps
CPU time 7.18 seconds
Started May 30 02:12:05 PM PDT 24
Finished May 30 02:12:14 PM PDT 24
Peak memory 250976 kb
Host smart-b0868432-7a35-4081-817a-af60cc268d90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299033128 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_post_trans.299033128
Directory /workspace/37.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all.2861888956
Short name T644
Test name
Test status
Simulation time 2963001674 ps
CPU time 132.72 seconds
Started May 30 02:11:58 PM PDT 24
Finished May 30 02:14:12 PM PDT 24
Peak memory 275172 kb
Host smart-ca38b21d-7c43-414f-9ba2-d7611babfb6f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861888956 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.lc_ctrl_stress_all.2861888956
Directory /workspace/37.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.lc_ctrl_volatile_unlock_smoke.1211897525
Short name T798
Test name
Test status
Simulation time 12333363 ps
CPU time 0.91 seconds
Started May 30 02:11:59 PM PDT 24
Finished May 30 02:12:01 PM PDT 24
Peak memory 211568 kb
Host smart-5a479be3-9ba9-4d4a-bebc-af35103d4abf
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211897525 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_c
trl_volatile_unlock_smoke.1211897525
Directory /workspace/37.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_alert_test.2645225741
Short name T450
Test name
Test status
Simulation time 21362274 ps
CPU time 0.97 seconds
Started May 30 02:12:10 PM PDT 24
Finished May 30 02:12:12 PM PDT 24
Peak memory 209576 kb
Host smart-dbc0e409-b061-4539-b9ea-e1c008724a25
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645225741 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_alert_test.2645225741
Directory /workspace/38.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.lc_ctrl_errors.3952414314
Short name T271
Test name
Test status
Simulation time 7098998135 ps
CPU time 16.91 seconds
Started May 30 02:12:10 PM PDT 24
Finished May 30 02:12:28 PM PDT 24
Peak memory 218028 kb
Host smart-d828fbe8-ee27-457f-bfe5-3665ba2a8854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952414314 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_errors.3952414314
Directory /workspace/38.lc_ctrl_errors/latest

Test location /workspace/coverage/default/38.lc_ctrl_jtag_access.1370586266
Short name T603
Test name
Test status
Simulation time 1537741840 ps
CPU time 9.08 seconds
Started May 30 02:12:08 PM PDT 24
Finished May 30 02:12:18 PM PDT 24
Peak memory 217072 kb
Host smart-d349be4d-81ca-4c01-9a44-56980ff63941
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370586266 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_jtag_access.1370586266
Directory /workspace/38.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/38.lc_ctrl_prog_failure.773715786
Short name T258
Test name
Test status
Simulation time 382893760 ps
CPU time 2.9 seconds
Started May 30 02:12:01 PM PDT 24
Finished May 30 02:12:06 PM PDT 24
Peak memory 218004 kb
Host smart-455bc338-23ed-48ba-8595-3a157e644faf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773715786 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_prog_failure.773715786
Directory /workspace/38.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_mubi.267846178
Short name T860
Test name
Test status
Simulation time 2085975352 ps
CPU time 12.68 seconds
Started May 30 02:12:24 PM PDT 24
Finished May 30 02:12:39 PM PDT 24
Peak memory 218108 kb
Host smart-bd39926f-5354-4972-93ab-e0c30754610f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267846178 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_mubi.267846178
Directory /workspace/38.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_digest.1919261067
Short name T611
Test name
Test status
Simulation time 1026708112 ps
CPU time 10.42 seconds
Started May 30 02:12:08 PM PDT 24
Finished May 30 02:12:20 PM PDT 24
Peak memory 217932 kb
Host smart-b21cf3a5-c200-4a58-b6f8-0eb1afae1001
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919261067 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_d
igest.1919261067
Directory /workspace/38.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_mux.2506130048
Short name T325
Test name
Test status
Simulation time 1218277403 ps
CPU time 19.63 seconds
Started May 30 02:12:12 PM PDT 24
Finished May 30 02:12:32 PM PDT 24
Peak memory 218072 kb
Host smart-33d61d63-d713-4db2-be44-c128abda8f2f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506130048 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_mux.
2506130048
Directory /workspace/38.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/38.lc_ctrl_security_escalation.2222947163
Short name T529
Test name
Test status
Simulation time 522827337 ps
CPU time 12.1 seconds
Started May 30 02:12:00 PM PDT 24
Finished May 30 02:12:14 PM PDT 24
Peak memory 218164 kb
Host smart-15e6165a-a480-4129-9603-2ab897af0e75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222947163 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_security_escalation.2222947163
Directory /workspace/38.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/38.lc_ctrl_smoke.2547032683
Short name T72
Test name
Test status
Simulation time 54957692 ps
CPU time 2.22 seconds
Started May 30 02:12:02 PM PDT 24
Finished May 30 02:12:06 PM PDT 24
Peak memory 217724 kb
Host smart-b59827f5-9e39-40ce-8194-032abfe18b7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547032683 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_smoke.2547032683
Directory /workspace/38.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_failure.3440903248
Short name T297
Test name
Test status
Simulation time 400583152 ps
CPU time 25.7 seconds
Started May 30 02:12:02 PM PDT 24
Finished May 30 02:12:28 PM PDT 24
Peak memory 251024 kb
Host smart-4cb5b140-ad3d-4445-a922-f4ecf420e5d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440903248 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_failure.3440903248
Directory /workspace/38.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_post_trans.3838101561
Short name T580
Test name
Test status
Simulation time 632614266 ps
CPU time 9.52 seconds
Started May 30 02:12:03 PM PDT 24
Finished May 30 02:12:13 PM PDT 24
Peak memory 251004 kb
Host smart-087f2902-96f8-400d-9763-f691409bd34d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838101561 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_post_trans.3838101561
Directory /workspace/38.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all.2044802544
Short name T119
Test name
Test status
Simulation time 18649360454 ps
CPU time 193.71 seconds
Started May 30 02:12:09 PM PDT 24
Finished May 30 02:15:23 PM PDT 24
Peak memory 316016 kb
Host smart-b2895763-bde3-4e2c-b4ba-1abe50924d6e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044802544 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.lc_ctrl_stress_all.2044802544
Directory /workspace/38.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.lc_ctrl_volatile_unlock_smoke.4108990768
Short name T620
Test name
Test status
Simulation time 25119972 ps
CPU time 1.01 seconds
Started May 30 02:11:59 PM PDT 24
Finished May 30 02:12:01 PM PDT 24
Peak memory 208672 kb
Host smart-c81a87ec-3da2-4b08-9741-65e9e41c3659
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108990768 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_c
trl_volatile_unlock_smoke.4108990768
Directory /workspace/38.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_alert_test.1131953677
Short name T305
Test name
Test status
Simulation time 62929460 ps
CPU time 0.91 seconds
Started May 30 02:12:16 PM PDT 24
Finished May 30 02:12:17 PM PDT 24
Peak memory 208692 kb
Host smart-3b02c934-31e5-44c5-b174-0c488ecf6f9f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131953677 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_alert_test.1131953677
Directory /workspace/39.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.lc_ctrl_errors.3298473870
Short name T655
Test name
Test status
Simulation time 701771505 ps
CPU time 11.54 seconds
Started May 30 02:12:09 PM PDT 24
Finished May 30 02:12:22 PM PDT 24
Peak memory 217976 kb
Host smart-2da0e95e-3d38-4f54-834a-5f3c37656209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298473870 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_errors.3298473870
Directory /workspace/39.lc_ctrl_errors/latest

Test location /workspace/coverage/default/39.lc_ctrl_jtag_access.3758698584
Short name T806
Test name
Test status
Simulation time 430847307 ps
CPU time 3.51 seconds
Started May 30 02:12:23 PM PDT 24
Finished May 30 02:12:28 PM PDT 24
Peak memory 209536 kb
Host smart-9f85b5dd-5ba0-4945-845f-7d3090153c50
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758698584 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_jtag_access.3758698584
Directory /workspace/39.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/39.lc_ctrl_prog_failure.2761506152
Short name T429
Test name
Test status
Simulation time 74717626 ps
CPU time 1.81 seconds
Started May 30 02:12:10 PM PDT 24
Finished May 30 02:12:12 PM PDT 24
Peak memory 218056 kb
Host smart-5bcb9441-31bf-40dd-94ce-ffe8b0256ea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761506152 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_prog_failure.2761506152
Directory /workspace/39.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_mubi.1877596934
Short name T69
Test name
Test status
Simulation time 646420277 ps
CPU time 15.42 seconds
Started May 30 02:12:24 PM PDT 24
Finished May 30 02:12:41 PM PDT 24
Peak memory 218032 kb
Host smart-4d8b403c-349d-4d2b-bff8-14730763d00c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877596934 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_mubi.1877596934
Directory /workspace/39.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_digest.3473462488
Short name T273
Test name
Test status
Simulation time 1137530798 ps
CPU time 9.56 seconds
Started May 30 02:12:09 PM PDT 24
Finished May 30 02:12:20 PM PDT 24
Peak memory 217956 kb
Host smart-01de6a8d-ca72-446d-bbab-fc6372c4de29
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473462488 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_d
igest.3473462488
Directory /workspace/39.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_mux.1023569792
Short name T473
Test name
Test status
Simulation time 1362291647 ps
CPU time 6 seconds
Started May 30 02:12:22 PM PDT 24
Finished May 30 02:12:29 PM PDT 24
Peak memory 217984 kb
Host smart-999b7d0c-9633-4eef-b570-6aabcdae12ff
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023569792 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_mux.
1023569792
Directory /workspace/39.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/39.lc_ctrl_security_escalation.677613543
Short name T812
Test name
Test status
Simulation time 3000021917 ps
CPU time 12.21 seconds
Started May 30 02:12:24 PM PDT 24
Finished May 30 02:12:38 PM PDT 24
Peak memory 226180 kb
Host smart-dd6394d4-cdfe-41d9-878a-b2408e17e368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677613543 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_security_escalation.677613543
Directory /workspace/39.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/39.lc_ctrl_smoke.2163405127
Short name T869
Test name
Test status
Simulation time 22314392 ps
CPU time 1.6 seconds
Started May 30 02:12:11 PM PDT 24
Finished May 30 02:12:13 PM PDT 24
Peak memory 217716 kb
Host smart-6436e3c8-f7ca-4843-ad73-813cde17f352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163405127 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_smoke.2163405127
Directory /workspace/39.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_failure.2650166967
Short name T553
Test name
Test status
Simulation time 452988067 ps
CPU time 21.26 seconds
Started May 30 02:12:12 PM PDT 24
Finished May 30 02:12:34 PM PDT 24
Peak memory 251020 kb
Host smart-804fc972-4713-4424-a83b-a59b627781b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650166967 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_failure.2650166967
Directory /workspace/39.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_post_trans.2949385996
Short name T257
Test name
Test status
Simulation time 82886470 ps
CPU time 7.9 seconds
Started May 30 02:12:08 PM PDT 24
Finished May 30 02:12:17 PM PDT 24
Peak memory 250548 kb
Host smart-d7b94af2-c262-459a-a6d8-f6e691a5b043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949385996 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_post_trans.2949385996
Directory /workspace/39.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all.1499180849
Short name T103
Test name
Test status
Simulation time 20430986383 ps
CPU time 55.72 seconds
Started May 30 02:12:24 PM PDT 24
Finished May 30 02:13:21 PM PDT 24
Peak memory 278208 kb
Host smart-527883a3-797f-416e-9091-e95d0aac41a7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499180849 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.lc_ctrl_stress_all.1499180849
Directory /workspace/39.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.lc_ctrl_volatile_unlock_smoke.2869054076
Short name T813
Test name
Test status
Simulation time 40601324 ps
CPU time 0.78 seconds
Started May 30 02:12:09 PM PDT 24
Finished May 30 02:12:11 PM PDT 24
Peak memory 208412 kb
Host smart-4078a205-dee9-4759-a098-7e17c3f77f3a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869054076 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_c
trl_volatile_unlock_smoke.2869054076
Directory /workspace/39.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_alert_test.4080786195
Short name T772
Test name
Test status
Simulation time 29092285 ps
CPU time 1.08 seconds
Started May 30 02:10:12 PM PDT 24
Finished May 30 02:10:14 PM PDT 24
Peak memory 209620 kb
Host smart-6059bb7a-0783-485c-a5ca-16bdfe7d9d3a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080786195 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_alert_test.4080786195
Directory /workspace/4.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.lc_ctrl_errors.3179711748
Short name T776
Test name
Test status
Simulation time 5717985454 ps
CPU time 19.27 seconds
Started May 30 02:09:54 PM PDT 24
Finished May 30 02:10:15 PM PDT 24
Peak memory 218056 kb
Host smart-b8542f6c-ff2b-4cd8-b903-9736d63e4fc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179711748 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_errors.3179711748
Directory /workspace/4.lc_ctrl_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_access.1037652599
Short name T456
Test name
Test status
Simulation time 607596648 ps
CPU time 15.08 seconds
Started May 30 02:09:51 PM PDT 24
Finished May 30 02:10:07 PM PDT 24
Peak memory 209584 kb
Host smart-b9c41453-25ea-4cb2-a2c1-bf75aee8e9d4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037652599 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_access.1037652599
Directory /workspace/4.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_errors.3934068791
Short name T612
Test name
Test status
Simulation time 1960692649 ps
CPU time 34.47 seconds
Started May 30 02:09:56 PM PDT 24
Finished May 30 02:10:32 PM PDT 24
Peak memory 218100 kb
Host smart-baf645bc-7956-4cd0-8809-c6c5babf1597
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934068791 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_er
rors.3934068791
Directory /workspace/4.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_priority.4109293371
Short name T836
Test name
Test status
Simulation time 1510205358 ps
CPU time 5.08 seconds
Started May 30 02:09:52 PM PDT 24
Finished May 30 02:09:58 PM PDT 24
Peak memory 217080 kb
Host smart-94b2c55c-380b-461e-a3e2-89c4286aa889
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109293371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_priority.4
109293371
Directory /workspace/4.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_prog_failure.3184914017
Short name T430
Test name
Test status
Simulation time 574611953 ps
CPU time 4.86 seconds
Started May 30 02:09:57 PM PDT 24
Finished May 30 02:10:03 PM PDT 24
Peak memory 217968 kb
Host smart-bbf68bcd-4294-4061-bcee-0c6f3518bf86
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184914017 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag
_prog_failure.3184914017
Directory /workspace/4.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_regwen_during_op.1793943461
Short name T786
Test name
Test status
Simulation time 2269780578 ps
CPU time 34.09 seconds
Started May 30 02:09:57 PM PDT 24
Finished May 30 02:10:32 PM PDT 24
Peak memory 217728 kb
Host smart-b770cc66-892c-415a-9b42-c69df3ab0bf6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793943461 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_regwen_during_op.1793943461
Directory /workspace/4.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_smoke.1762705248
Short name T274
Test name
Test status
Simulation time 595980845 ps
CPU time 9.19 seconds
Started May 30 02:09:50 PM PDT 24
Finished May 30 02:10:00 PM PDT 24
Peak memory 217668 kb
Host smart-2cdcc251-3bd9-40ec-9063-c7ee0bef0126
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762705248 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_smoke.
1762705248
Directory /workspace/4.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_failure.2238373550
Short name T279
Test name
Test status
Simulation time 2552623599 ps
CPU time 89.64 seconds
Started May 30 02:09:56 PM PDT 24
Finished May 30 02:11:27 PM PDT 24
Peak memory 276944 kb
Host smart-4631ccc9-3b9c-40c8-9fd3-8b31256a43dd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238373550 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jta
g_state_failure.2238373550
Directory /workspace/4.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_post_trans.535842340
Short name T596
Test name
Test status
Simulation time 1640552107 ps
CPU time 13.33 seconds
Started May 30 02:09:51 PM PDT 24
Finished May 30 02:10:06 PM PDT 24
Peak memory 224044 kb
Host smart-00366684-4191-405b-9a6d-8064cbc55935
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535842340 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_j
tag_state_post_trans.535842340
Directory /workspace/4.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_prog_failure.3249501646
Short name T561
Test name
Test status
Simulation time 81910552 ps
CPU time 3.83 seconds
Started May 30 02:10:00 PM PDT 24
Finished May 30 02:10:04 PM PDT 24
Peak memory 218024 kb
Host smart-03334795-e21d-4a25-b0f8-fcb1a23af830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249501646 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_prog_failure.3249501646
Directory /workspace/4.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_regwen_during_op.149236071
Short name T75
Test name
Test status
Simulation time 1241293897 ps
CPU time 12.51 seconds
Started May 30 02:09:53 PM PDT 24
Finished May 30 02:10:07 PM PDT 24
Peak memory 217728 kb
Host smart-477f5e1e-669b-413f-ba8a-94ca32dd80ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149236071 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_regwen_during_op.149236071
Directory /workspace/4.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_cm.1764934092
Short name T98
Test name
Test status
Simulation time 144257002 ps
CPU time 26.75 seconds
Started May 30 02:10:01 PM PDT 24
Finished May 30 02:10:28 PM PDT 24
Peak memory 269904 kb
Host smart-f4d6db20-9977-4ca8-8dac-86e00a5cfd2d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764934092 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_cm.1764934092
Directory /workspace/4.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_mubi.169278672
Short name T741
Test name
Test status
Simulation time 894689036 ps
CPU time 13.94 seconds
Started May 30 02:09:57 PM PDT 24
Finished May 30 02:10:12 PM PDT 24
Peak memory 226132 kb
Host smart-b6fde631-8bc1-4c41-9e57-be35851b694f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169278672 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_mubi.169278672
Directory /workspace/4.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_digest.194859135
Short name T492
Test name
Test status
Simulation time 570601308 ps
CPU time 20.22 seconds
Started May 30 02:09:58 PM PDT 24
Finished May 30 02:10:19 PM PDT 24
Peak memory 217964 kb
Host smart-a8eb5285-f282-4891-ad8b-f2ea2baf6f1c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194859135 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_dig
est.194859135
Directory /workspace/4.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_mux.4154040489
Short name T470
Test name
Test status
Simulation time 248292681 ps
CPU time 9.58 seconds
Started May 30 02:09:52 PM PDT 24
Finished May 30 02:10:03 PM PDT 24
Peak memory 218052 kb
Host smart-e7bf2745-d453-45ac-8e08-e0bbb70cba43
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154040489 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_mux.4
154040489
Directory /workspace/4.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/4.lc_ctrl_security_escalation.586917204
Short name T63
Test name
Test status
Simulation time 1350380052 ps
CPU time 10 seconds
Started May 30 02:09:54 PM PDT 24
Finished May 30 02:10:05 PM PDT 24
Peak memory 218192 kb
Host smart-3a018cf0-0904-4c0c-991d-65d946deb3e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=586917204 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_security_escalation.586917204
Directory /workspace/4.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/4.lc_ctrl_smoke.1491152704
Short name T461
Test name
Test status
Simulation time 45364036 ps
CPU time 3.22 seconds
Started May 30 02:09:54 PM PDT 24
Finished May 30 02:09:58 PM PDT 24
Peak memory 214796 kb
Host smart-1ba4b305-e32c-416f-a175-884c09591e3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491152704 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_smoke.1491152704
Directory /workspace/4.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_failure.1654981357
Short name T95
Test name
Test status
Simulation time 305710578 ps
CPU time 30.66 seconds
Started May 30 02:09:54 PM PDT 24
Finished May 30 02:10:25 PM PDT 24
Peak memory 250992 kb
Host smart-4c015e7f-6c12-4496-ad62-eafda8fae108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654981357 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_failure.1654981357
Directory /workspace/4.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_post_trans.3579043764
Short name T299
Test name
Test status
Simulation time 264926621 ps
CPU time 2.8 seconds
Started May 30 02:10:00 PM PDT 24
Finished May 30 02:10:03 PM PDT 24
Peak memory 222428 kb
Host smart-00e58bd8-2a15-4715-a58f-3d3424931dd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579043764 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_post_trans.3579043764
Directory /workspace/4.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_stress_all.4244863489
Short name T763
Test name
Test status
Simulation time 17306376973 ps
CPU time 189.24 seconds
Started May 30 02:10:01 PM PDT 24
Finished May 30 02:13:11 PM PDT 24
Peak memory 267300 kb
Host smart-d9aca61d-9c9b-477b-b8de-2984c5b8e5c9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244863489 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.lc_ctrl_stress_all.4244863489
Directory /workspace/4.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.lc_ctrl_volatile_unlock_smoke.213509512
Short name T777
Test name
Test status
Simulation time 11884884 ps
CPU time 1.05 seconds
Started May 30 02:09:59 PM PDT 24
Finished May 30 02:10:01 PM PDT 24
Peak memory 211596 kb
Host smart-034e0b40-ccb1-44de-8296-c15b7ce5a7cf
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213509512 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctr
l_volatile_unlock_smoke.213509512
Directory /workspace/4.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_alert_test.2245267856
Short name T778
Test name
Test status
Simulation time 31092745 ps
CPU time 0.91 seconds
Started May 30 02:12:10 PM PDT 24
Finished May 30 02:12:12 PM PDT 24
Peak memory 208796 kb
Host smart-efdd86be-385e-4c84-93b2-01121d81627c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245267856 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_alert_test.2245267856
Directory /workspace/40.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.lc_ctrl_errors.436277302
Short name T671
Test name
Test status
Simulation time 373084306 ps
CPU time 10.26 seconds
Started May 30 02:12:10 PM PDT 24
Finished May 30 02:12:22 PM PDT 24
Peak memory 218108 kb
Host smart-6f3844a6-e0ed-4714-873d-402dd7dbd901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436277302 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_errors.436277302
Directory /workspace/40.lc_ctrl_errors/latest

Test location /workspace/coverage/default/40.lc_ctrl_jtag_access.739890160
Short name T870
Test name
Test status
Simulation time 148352152 ps
CPU time 2.53 seconds
Started May 30 02:12:11 PM PDT 24
Finished May 30 02:12:15 PM PDT 24
Peak memory 216932 kb
Host smart-cd513b34-fdfe-4b6f-994b-de00d8392430
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739890160 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_jtag_access.739890160
Directory /workspace/40.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/40.lc_ctrl_prog_failure.1782638634
Short name T562
Test name
Test status
Simulation time 56436233 ps
CPU time 2.95 seconds
Started May 30 02:12:10 PM PDT 24
Finished May 30 02:12:15 PM PDT 24
Peak memory 218120 kb
Host smart-ac242cb0-d1f5-4a48-9703-a99bcf91482d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782638634 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_prog_failure.1782638634
Directory /workspace/40.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_mubi.4017171220
Short name T277
Test name
Test status
Simulation time 229789508 ps
CPU time 11.65 seconds
Started May 30 02:12:11 PM PDT 24
Finished May 30 02:12:24 PM PDT 24
Peak memory 218072 kb
Host smart-005f4a62-1895-48ec-8449-b5473f759e9d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017171220 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_mubi.4017171220
Directory /workspace/40.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_digest.3000323252
Short name T259
Test name
Test status
Simulation time 345472758 ps
CPU time 9.49 seconds
Started May 30 02:12:10 PM PDT 24
Finished May 30 02:12:21 PM PDT 24
Peak memory 218024 kb
Host smart-e908fac3-d2bb-4e0c-a4f3-c1f92cfc73df
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000323252 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_d
igest.3000323252
Directory /workspace/40.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_mux.2916326348
Short name T808
Test name
Test status
Simulation time 2885035285 ps
CPU time 8.67 seconds
Started May 30 02:12:10 PM PDT 24
Finished May 30 02:12:20 PM PDT 24
Peak memory 218096 kb
Host smart-bd2eb0a8-f91a-4ad3-ad57-ee1970c3a078
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916326348 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_mux.
2916326348
Directory /workspace/40.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/40.lc_ctrl_security_escalation.4022261100
Short name T678
Test name
Test status
Simulation time 2697544592 ps
CPU time 16.98 seconds
Started May 30 02:12:11 PM PDT 24
Finished May 30 02:12:29 PM PDT 24
Peak memory 218152 kb
Host smart-dd3efb9e-d480-4749-b382-4f87f1da6b90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022261100 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_security_escalation.4022261100
Directory /workspace/40.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/40.lc_ctrl_smoke.4131841597
Short name T121
Test name
Test status
Simulation time 57239841 ps
CPU time 1.31 seconds
Started May 30 02:12:11 PM PDT 24
Finished May 30 02:12:13 PM PDT 24
Peak memory 213436 kb
Host smart-4af15489-71c9-4d46-84d2-ac1c48f3d1e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131841597 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_smoke.4131841597
Directory /workspace/40.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_failure.3475734139
Short name T256
Test name
Test status
Simulation time 197995340 ps
CPU time 24.97 seconds
Started May 30 02:12:23 PM PDT 24
Finished May 30 02:12:50 PM PDT 24
Peak memory 251096 kb
Host smart-2c68ae63-5661-4ee3-9252-58af923d92ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475734139 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_failure.3475734139
Directory /workspace/40.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_post_trans.596194570
Short name T745
Test name
Test status
Simulation time 100837195 ps
CPU time 3.65 seconds
Started May 30 02:12:09 PM PDT 24
Finished May 30 02:12:14 PM PDT 24
Peak memory 217964 kb
Host smart-7cad29cd-9d60-424c-b5fe-183a3307a6e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596194570 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_post_trans.596194570
Directory /workspace/40.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/40.lc_ctrl_stress_all.2517711890
Short name T658
Test name
Test status
Simulation time 5690152338 ps
CPU time 145.96 seconds
Started May 30 02:12:25 PM PDT 24
Finished May 30 02:14:53 PM PDT 24
Peak memory 267924 kb
Host smart-2615ebc0-d6ca-4bb8-855a-3d1b175bc462
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517711890 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.lc_ctrl_stress_all.2517711890
Directory /workspace/40.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.lc_ctrl_volatile_unlock_smoke.3106658220
Short name T792
Test name
Test status
Simulation time 27696840 ps
CPU time 0.92 seconds
Started May 30 02:12:23 PM PDT 24
Finished May 30 02:12:26 PM PDT 24
Peak memory 208640 kb
Host smart-56ab0e6d-ea33-41c6-bc98-291671359396
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106658220 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_c
trl_volatile_unlock_smoke.3106658220
Directory /workspace/40.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_alert_test.1106111543
Short name T99
Test name
Test status
Simulation time 16931246 ps
CPU time 1.11 seconds
Started May 30 02:12:22 PM PDT 24
Finished May 30 02:12:24 PM PDT 24
Peak memory 209564 kb
Host smart-8af189c2-2e24-436b-a983-987c1f65eb6d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106111543 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_alert_test.1106111543
Directory /workspace/41.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.lc_ctrl_errors.922259506
Short name T42
Test name
Test status
Simulation time 1960658838 ps
CPU time 14.23 seconds
Started May 30 02:12:23 PM PDT 24
Finished May 30 02:12:38 PM PDT 24
Peak memory 218000 kb
Host smart-ed3539be-7f00-4b8f-9521-f51d1731d0f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922259506 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_errors.922259506
Directory /workspace/41.lc_ctrl_errors/latest

Test location /workspace/coverage/default/41.lc_ctrl_jtag_access.1921853189
Short name T600
Test name
Test status
Simulation time 116986276 ps
CPU time 1.58 seconds
Started May 30 02:12:09 PM PDT 24
Finished May 30 02:12:12 PM PDT 24
Peak memory 216884 kb
Host smart-5a9d07f9-89a0-45d6-8d24-bfc3dee22020
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921853189 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_jtag_access.1921853189
Directory /workspace/41.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/41.lc_ctrl_prog_failure.2743635600
Short name T487
Test name
Test status
Simulation time 27236562 ps
CPU time 2.17 seconds
Started May 30 02:12:09 PM PDT 24
Finished May 30 02:12:12 PM PDT 24
Peak memory 218036 kb
Host smart-dfbe7bba-6e18-474d-a048-2c3051121baf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743635600 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_prog_failure.2743635600
Directory /workspace/41.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_mubi.3815614944
Short name T682
Test name
Test status
Simulation time 1122088159 ps
CPU time 13.65 seconds
Started May 30 02:12:10 PM PDT 24
Finished May 30 02:12:24 PM PDT 24
Peak memory 219096 kb
Host smart-fc7ebf2b-b6ba-41cb-ad3a-12af72278f88
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815614944 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_mubi.3815614944
Directory /workspace/41.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_digest.2953940897
Short name T556
Test name
Test status
Simulation time 322964613 ps
CPU time 13.9 seconds
Started May 30 02:12:20 PM PDT 24
Finished May 30 02:12:35 PM PDT 24
Peak memory 226092 kb
Host smart-e18a2d3c-2585-4ed4-992d-020160318c77
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953940897 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_d
igest.2953940897
Directory /workspace/41.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_mux.2382607920
Short name T599
Test name
Test status
Simulation time 238097379 ps
CPU time 8.76 seconds
Started May 30 02:12:22 PM PDT 24
Finished May 30 02:12:32 PM PDT 24
Peak memory 218040 kb
Host smart-1934f58a-15f6-4503-8362-4e9791f08002
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382607920 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_mux.
2382607920
Directory /workspace/41.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/41.lc_ctrl_security_escalation.1520598052
Short name T621
Test name
Test status
Simulation time 367304364 ps
CPU time 7.82 seconds
Started May 30 02:12:11 PM PDT 24
Finished May 30 02:12:20 PM PDT 24
Peak memory 218020 kb
Host smart-c2fc553c-c528-4694-8411-f72bae2cea94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520598052 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_security_escalation.1520598052
Directory /workspace/41.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/41.lc_ctrl_smoke.3182427600
Short name T623
Test name
Test status
Simulation time 87384038 ps
CPU time 1.65 seconds
Started May 30 02:12:09 PM PDT 24
Finished May 30 02:12:12 PM PDT 24
Peak memory 217748 kb
Host smart-89e605f7-5ded-47f4-a2e0-91dc31a9eadc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182427600 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_smoke.3182427600
Directory /workspace/41.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_failure.2031168028
Short name T380
Test name
Test status
Simulation time 1142067957 ps
CPU time 26.17 seconds
Started May 30 02:12:24 PM PDT 24
Finished May 30 02:12:52 PM PDT 24
Peak memory 250884 kb
Host smart-7cb327f3-825d-4ab7-987c-db3343f0c2ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031168028 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_failure.2031168028
Directory /workspace/41.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_post_trans.535924244
Short name T308
Test name
Test status
Simulation time 122811648 ps
CPU time 8.41 seconds
Started May 30 02:12:12 PM PDT 24
Finished May 30 02:12:21 PM PDT 24
Peak memory 251012 kb
Host smart-1e005255-f8c2-4b37-9841-c30cc56450a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=535924244 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_post_trans.535924244
Directory /workspace/41.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all.3679524708
Short name T83
Test name
Test status
Simulation time 7377317361 ps
CPU time 156.31 seconds
Started May 30 02:12:23 PM PDT 24
Finished May 30 02:15:02 PM PDT 24
Peak memory 281992 kb
Host smart-d0045d23-d9af-42c9-8941-403a9427c9f1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679524708 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.lc_ctrl_stress_all.3679524708
Directory /workspace/41.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all_with_rand_reset.2250420124
Short name T163
Test name
Test status
Simulation time 30025477260 ps
CPU time 2099.44 seconds
Started May 30 02:12:23 PM PDT 24
Finished May 30 02:47:25 PM PDT 24
Peak memory 982080 kb
Host smart-12629f5f-dfc0-4388-9121-820cef18fde8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2250420124 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_stress_all_with_rand_reset.2250420124
Directory /workspace/41.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.lc_ctrl_volatile_unlock_smoke.3947953900
Short name T646
Test name
Test status
Simulation time 60580645 ps
CPU time 0.96 seconds
Started May 30 02:12:08 PM PDT 24
Finished May 30 02:12:10 PM PDT 24
Peak memory 211564 kb
Host smart-89b6f6c8-51ca-4cd4-9833-a8e521fe041e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947953900 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_c
trl_volatile_unlock_smoke.3947953900
Directory /workspace/41.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_alert_test.3906990972
Short name T495
Test name
Test status
Simulation time 20870399 ps
CPU time 1.2 seconds
Started May 30 02:12:23 PM PDT 24
Finished May 30 02:12:27 PM PDT 24
Peak memory 208732 kb
Host smart-88e9d6ca-aa86-4368-bf6b-9197f980ad54
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906990972 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_alert_test.3906990972
Directory /workspace/42.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.lc_ctrl_errors.1121704007
Short name T624
Test name
Test status
Simulation time 1019563490 ps
CPU time 13.45 seconds
Started May 30 02:12:26 PM PDT 24
Finished May 30 02:12:41 PM PDT 24
Peak memory 217980 kb
Host smart-7f45df71-f72e-41d7-9ab1-3afbd5ebe673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121704007 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_errors.1121704007
Directory /workspace/42.lc_ctrl_errors/latest

Test location /workspace/coverage/default/42.lc_ctrl_jtag_access.3234793490
Short name T693
Test name
Test status
Simulation time 2708540321 ps
CPU time 4.68 seconds
Started May 30 02:12:21 PM PDT 24
Finished May 30 02:12:27 PM PDT 24
Peak memory 217296 kb
Host smart-074b26e2-092a-48ce-bd8d-70cd4a0c6a8a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234793490 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_jtag_access.3234793490
Directory /workspace/42.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/42.lc_ctrl_prog_failure.2724406872
Short name T370
Test name
Test status
Simulation time 38236689 ps
CPU time 1.87 seconds
Started May 30 02:12:23 PM PDT 24
Finished May 30 02:12:26 PM PDT 24
Peak memory 218000 kb
Host smart-9221b5a1-7bf1-458e-b857-f4cfa63829f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724406872 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_prog_failure.2724406872
Directory /workspace/42.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_mubi.308693462
Short name T694
Test name
Test status
Simulation time 2057491131 ps
CPU time 14.3 seconds
Started May 30 02:12:23 PM PDT 24
Finished May 30 02:12:39 PM PDT 24
Peak memory 226024 kb
Host smart-196eef7f-d06d-485c-a8ab-8b701e8435e0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308693462 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_mubi.308693462
Directory /workspace/42.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_digest.1786892065
Short name T748
Test name
Test status
Simulation time 474221788 ps
CPU time 11.46 seconds
Started May 30 02:12:23 PM PDT 24
Finished May 30 02:12:36 PM PDT 24
Peak memory 225548 kb
Host smart-24002306-0664-4be7-8eab-77edd4e5ba6c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786892065 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_d
igest.1786892065
Directory /workspace/42.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_mux.2170333428
Short name T404
Test name
Test status
Simulation time 1111664218 ps
CPU time 19.6 seconds
Started May 30 02:12:21 PM PDT 24
Finished May 30 02:12:42 PM PDT 24
Peak memory 218072 kb
Host smart-0a6cc053-58b3-46be-a4ff-63de26c4237b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170333428 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_mux.
2170333428
Directory /workspace/42.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/42.lc_ctrl_security_escalation.3281008240
Short name T373
Test name
Test status
Simulation time 1227379365 ps
CPU time 7.4 seconds
Started May 30 02:12:21 PM PDT 24
Finished May 30 02:12:30 PM PDT 24
Peak memory 218084 kb
Host smart-83b0da13-5d57-4a44-814f-eaabca36b0c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281008240 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_security_escalation.3281008240
Directory /workspace/42.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/42.lc_ctrl_smoke.2728853141
Short name T472
Test name
Test status
Simulation time 41295086 ps
CPU time 1.18 seconds
Started May 30 02:12:25 PM PDT 24
Finished May 30 02:12:28 PM PDT 24
Peak memory 217728 kb
Host smart-461670cc-c45c-4d82-83d3-cdb6b289b37b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728853141 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_smoke.2728853141
Directory /workspace/42.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_failure.2315840871
Short name T409
Test name
Test status
Simulation time 189024513 ps
CPU time 29.78 seconds
Started May 30 02:12:23 PM PDT 24
Finished May 30 02:12:54 PM PDT 24
Peak memory 250992 kb
Host smart-8b56099c-305d-459d-84a9-d6c9a15df1c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315840871 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_failure.2315840871
Directory /workspace/42.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_post_trans.3396366153
Short name T633
Test name
Test status
Simulation time 297830593 ps
CPU time 6.23 seconds
Started May 30 02:12:21 PM PDT 24
Finished May 30 02:12:28 PM PDT 24
Peak memory 246484 kb
Host smart-6ec6e025-1bd5-40f9-89e5-c3f66b9d3ea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396366153 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_post_trans.3396366153
Directory /workspace/42.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/42.lc_ctrl_stress_all.1684672637
Short name T608
Test name
Test status
Simulation time 14344654604 ps
CPU time 149.64 seconds
Started May 30 02:12:24 PM PDT 24
Finished May 30 02:14:55 PM PDT 24
Peak memory 283872 kb
Host smart-d1d4cc63-0d24-4824-8dfd-e0e99a62f435
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684672637 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.lc_ctrl_stress_all.1684672637
Directory /workspace/42.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.lc_ctrl_volatile_unlock_smoke.2082610332
Short name T557
Test name
Test status
Simulation time 13841727 ps
CPU time 1.12 seconds
Started May 30 02:12:23 PM PDT 24
Finished May 30 02:12:25 PM PDT 24
Peak memory 211568 kb
Host smart-a1413116-d802-4374-8681-c5e057a40307
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082610332 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_c
trl_volatile_unlock_smoke.2082610332
Directory /workspace/42.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_alert_test.2647249506
Short name T249
Test name
Test status
Simulation time 20248339 ps
CPU time 1.25 seconds
Started May 30 02:12:24 PM PDT 24
Finished May 30 02:12:27 PM PDT 24
Peak memory 208856 kb
Host smart-7764c6b3-9291-40c1-86da-baceb3030e7b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647249506 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_alert_test.2647249506
Directory /workspace/43.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.lc_ctrl_jtag_access.378791436
Short name T838
Test name
Test status
Simulation time 435232907 ps
CPU time 1.71 seconds
Started May 30 02:12:23 PM PDT 24
Finished May 30 02:12:26 PM PDT 24
Peak memory 209508 kb
Host smart-fbe77fa0-37a2-48f7-93e8-958847f664c3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378791436 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_jtag_access.378791436
Directory /workspace/43.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/43.lc_ctrl_prog_failure.2853662929
Short name T550
Test name
Test status
Simulation time 192422121 ps
CPU time 2.73 seconds
Started May 30 02:12:21 PM PDT 24
Finished May 30 02:12:25 PM PDT 24
Peak memory 218104 kb
Host smart-ba26f066-c0f5-4ae7-9ffa-97549766852c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853662929 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_prog_failure.2853662929
Directory /workspace/43.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_mubi.864758343
Short name T757
Test name
Test status
Simulation time 840050883 ps
CPU time 13.1 seconds
Started May 30 02:12:23 PM PDT 24
Finished May 30 02:12:37 PM PDT 24
Peak memory 219004 kb
Host smart-8eaf263c-beac-4906-8e28-4c20731ad2d4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864758343 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_mubi.864758343
Directory /workspace/43.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_digest.2250639298
Short name T554
Test name
Test status
Simulation time 1024736548 ps
CPU time 14.73 seconds
Started May 30 02:12:24 PM PDT 24
Finished May 30 02:12:40 PM PDT 24
Peak memory 226100 kb
Host smart-ab265236-e667-4f19-adc7-22da744ed9af
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250639298 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_d
igest.2250639298
Directory /workspace/43.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_mux.4001345366
Short name T811
Test name
Test status
Simulation time 576259838 ps
CPU time 14.28 seconds
Started May 30 02:12:25 PM PDT 24
Finished May 30 02:12:41 PM PDT 24
Peak memory 218076 kb
Host smart-34e4df14-2430-4fd9-a534-c1a23af64bc1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001345366 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_mux.
4001345366
Directory /workspace/43.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/43.lc_ctrl_security_escalation.3168194217
Short name T388
Test name
Test status
Simulation time 1007843282 ps
CPU time 7.2 seconds
Started May 30 02:12:21 PM PDT 24
Finished May 30 02:12:29 PM PDT 24
Peak memory 218180 kb
Host smart-595368f4-c7de-40e1-9cd6-69adb0eca0e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168194217 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_security_escalation.3168194217
Directory /workspace/43.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/43.lc_ctrl_smoke.829780421
Short name T40
Test name
Test status
Simulation time 94596226 ps
CPU time 1.2 seconds
Started May 30 02:12:21 PM PDT 24
Finished May 30 02:12:24 PM PDT 24
Peak memory 213444 kb
Host smart-03c71b70-fa4e-4364-88aa-f584e5e94033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829780421 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_smoke.829780421
Directory /workspace/43.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_failure.2989174928
Short name T610
Test name
Test status
Simulation time 5070909229 ps
CPU time 30.9 seconds
Started May 30 02:12:21 PM PDT 24
Finished May 30 02:12:53 PM PDT 24
Peak memory 250836 kb
Host smart-b14b3362-9081-4418-b4ee-ae270339f573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989174928 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_failure.2989174928
Directory /workspace/43.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_post_trans.2961016471
Short name T747
Test name
Test status
Simulation time 95040553 ps
CPU time 10.57 seconds
Started May 30 02:12:24 PM PDT 24
Finished May 30 02:12:36 PM PDT 24
Peak memory 250928 kb
Host smart-b5ffe874-d0cc-434a-8f68-36a9dd80152a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961016471 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_post_trans.2961016471
Directory /workspace/43.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all.68638582
Short name T410
Test name
Test status
Simulation time 1298352782 ps
CPU time 76.86 seconds
Started May 30 02:12:25 PM PDT 24
Finished May 30 02:13:44 PM PDT 24
Peak memory 270092 kb
Host smart-536e7500-2b64-4b4e-b05b-ada8d45f3239
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68638582 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_T
EST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
3.lc_ctrl_stress_all.68638582
Directory /workspace/43.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all_with_rand_reset.701691251
Short name T589
Test name
Test status
Simulation time 14567194532 ps
CPU time 385.1 seconds
Started May 30 02:12:20 PM PDT 24
Finished May 30 02:18:46 PM PDT 24
Peak memory 268260 kb
Host smart-316e055c-09d8-4846-b3e9-73dd168997d3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=701691251 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_stress_all_with_rand_reset.701691251
Directory /workspace/43.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.lc_ctrl_alert_test.673479299
Short name T657
Test name
Test status
Simulation time 39312669 ps
CPU time 1.22 seconds
Started May 30 02:12:35 PM PDT 24
Finished May 30 02:12:38 PM PDT 24
Peak memory 208752 kb
Host smart-4adfd864-f1ac-42dd-9616-ff26159ef5d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673479299 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_alert_test.673479299
Directory /workspace/44.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.lc_ctrl_errors.3801834967
Short name T613
Test name
Test status
Simulation time 1203875623 ps
CPU time 11.97 seconds
Started May 30 02:12:36 PM PDT 24
Finished May 30 02:12:49 PM PDT 24
Peak memory 218120 kb
Host smart-459a031a-e834-40a8-9b00-d68dc6831e2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3801834967 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_errors.3801834967
Directory /workspace/44.lc_ctrl_errors/latest

Test location /workspace/coverage/default/44.lc_ctrl_jtag_access.1218553493
Short name T345
Test name
Test status
Simulation time 297036419 ps
CPU time 4.35 seconds
Started May 30 02:12:36 PM PDT 24
Finished May 30 02:12:42 PM PDT 24
Peak memory 209484 kb
Host smart-27c68305-2ee1-4763-8d95-9b1318d71948
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218553493 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_jtag_access.1218553493
Directory /workspace/44.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/44.lc_ctrl_prog_failure.1973137317
Short name T591
Test name
Test status
Simulation time 38390927 ps
CPU time 1.57 seconds
Started May 30 02:12:35 PM PDT 24
Finished May 30 02:12:38 PM PDT 24
Peak memory 218100 kb
Host smart-696539f5-601d-4d9d-b517-06f1ee45d15f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973137317 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_prog_failure.1973137317
Directory /workspace/44.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_mubi.2454621498
Short name T873
Test name
Test status
Simulation time 2419288971 ps
CPU time 14.29 seconds
Started May 30 02:12:33 PM PDT 24
Finished May 30 02:12:49 PM PDT 24
Peak memory 226304 kb
Host smart-05ad2612-3ccf-4bca-ae65-2b50f0c4b3f7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454621498 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_mubi.2454621498
Directory /workspace/44.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_digest.1605234768
Short name T463
Test name
Test status
Simulation time 5681328679 ps
CPU time 14.89 seconds
Started May 30 02:12:35 PM PDT 24
Finished May 30 02:12:52 PM PDT 24
Peak memory 218052 kb
Host smart-771716ed-25a2-4dc7-9ad1-d2f984f7cffa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605234768 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_d
igest.1605234768
Directory /workspace/44.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_mux.3133265424
Short name T285
Test name
Test status
Simulation time 1113715486 ps
CPU time 9.03 seconds
Started May 30 02:12:33 PM PDT 24
Finished May 30 02:12:44 PM PDT 24
Peak memory 218072 kb
Host smart-41c322b0-3c24-4727-a76e-7933c5fa2650
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133265424 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_mux.
3133265424
Directory /workspace/44.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/44.lc_ctrl_security_escalation.3039738779
Short name T178
Test name
Test status
Simulation time 367174536 ps
CPU time 10.6 seconds
Started May 30 02:12:34 PM PDT 24
Finished May 30 02:12:46 PM PDT 24
Peak memory 218120 kb
Host smart-4c362827-b6da-4b50-adc3-1f33492601ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039738779 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_security_escalation.3039738779
Directory /workspace/44.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/44.lc_ctrl_smoke.381778548
Short name T821
Test name
Test status
Simulation time 135137826 ps
CPU time 1.89 seconds
Started May 30 02:12:23 PM PDT 24
Finished May 30 02:12:27 PM PDT 24
Peak memory 217808 kb
Host smart-0dba3e32-e941-4eb3-9577-ca9fd65c2420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381778548 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_smoke.381778548
Directory /workspace/44.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_failure.684644936
Short name T587
Test name
Test status
Simulation time 361685908 ps
CPU time 28.07 seconds
Started May 30 02:12:21 PM PDT 24
Finished May 30 02:12:50 PM PDT 24
Peak memory 251108 kb
Host smart-bf67433c-d9d9-434b-a77c-1fcfe38dc8e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684644936 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_failure.684644936
Directory /workspace/44.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_post_trans.3820195912
Short name T532
Test name
Test status
Simulation time 576691297 ps
CPU time 9.52 seconds
Started May 30 02:12:24 PM PDT 24
Finished May 30 02:12:35 PM PDT 24
Peak memory 250984 kb
Host smart-8955e4e7-f799-4e4b-a240-6322d0b9d9de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3820195912 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_post_trans.3820195912
Directory /workspace/44.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/44.lc_ctrl_stress_all.1951177782
Short name T784
Test name
Test status
Simulation time 3677694788 ps
CPU time 120.69 seconds
Started May 30 02:12:36 PM PDT 24
Finished May 30 02:14:38 PM PDT 24
Peak memory 270380 kb
Host smart-70cd5405-5a15-4d57-92e9-137e2aba8356
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951177782 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.lc_ctrl_stress_all.1951177782
Directory /workspace/44.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.lc_ctrl_volatile_unlock_smoke.3689579508
Short name T91
Test name
Test status
Simulation time 37095708 ps
CPU time 1.01 seconds
Started May 30 02:12:22 PM PDT 24
Finished May 30 02:12:24 PM PDT 24
Peak memory 211604 kb
Host smart-1f922761-cc81-42f1-a6fc-f045289ead03
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689579508 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_c
trl_volatile_unlock_smoke.3689579508
Directory /workspace/44.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_alert_test.242248462
Short name T415
Test name
Test status
Simulation time 17083527 ps
CPU time 0.95 seconds
Started May 30 02:12:34 PM PDT 24
Finished May 30 02:12:36 PM PDT 24
Peak memory 208684 kb
Host smart-a8d6eaa3-509c-4229-af16-c760c6949349
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242248462 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_alert_test.242248462
Directory /workspace/45.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.lc_ctrl_errors.2516910046
Short name T70
Test name
Test status
Simulation time 569155402 ps
CPU time 13.75 seconds
Started May 30 02:12:38 PM PDT 24
Finished May 30 02:12:54 PM PDT 24
Peak memory 217988 kb
Host smart-956ac270-109c-4800-b461-e75a95d451d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516910046 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_errors.2516910046
Directory /workspace/45.lc_ctrl_errors/latest

Test location /workspace/coverage/default/45.lc_ctrl_jtag_access.2373336396
Short name T399
Test name
Test status
Simulation time 623425557 ps
CPU time 2.36 seconds
Started May 30 02:12:37 PM PDT 24
Finished May 30 02:12:42 PM PDT 24
Peak memory 209520 kb
Host smart-0c8f7cb8-5e2c-4698-96e3-2c2aede6898e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373336396 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_jtag_access.2373336396
Directory /workspace/45.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/45.lc_ctrl_prog_failure.2308017532
Short name T692
Test name
Test status
Simulation time 21321278 ps
CPU time 1.85 seconds
Started May 30 02:12:36 PM PDT 24
Finished May 30 02:12:39 PM PDT 24
Peak memory 218052 kb
Host smart-2ddfc317-3878-4efa-b5d2-5fe9206a7adf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308017532 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_prog_failure.2308017532
Directory /workspace/45.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_mubi.1153088166
Short name T523
Test name
Test status
Simulation time 1208723438 ps
CPU time 12.59 seconds
Started May 30 02:12:35 PM PDT 24
Finished May 30 02:12:49 PM PDT 24
Peak memory 225860 kb
Host smart-bf7f5ed5-f7be-4d9b-932e-e038884ebdc2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153088166 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_mubi.1153088166
Directory /workspace/45.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_digest.2081510967
Short name T115
Test name
Test status
Simulation time 1290969840 ps
CPU time 11.29 seconds
Started May 30 02:12:35 PM PDT 24
Finished May 30 02:12:48 PM PDT 24
Peak memory 226080 kb
Host smart-ece28bdc-acea-4f83-9ce0-2743d50d1374
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081510967 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_d
igest.2081510967
Directory /workspace/45.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_mux.2511716684
Short name T382
Test name
Test status
Simulation time 1432205117 ps
CPU time 13.02 seconds
Started May 30 02:12:34 PM PDT 24
Finished May 30 02:12:49 PM PDT 24
Peak memory 218100 kb
Host smart-18708c15-1518-4f6f-be4a-6e479011e148
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511716684 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_mux.
2511716684
Directory /workspace/45.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/45.lc_ctrl_security_escalation.305682272
Short name T65
Test name
Test status
Simulation time 348939670 ps
CPU time 7.74 seconds
Started May 30 02:12:35 PM PDT 24
Finished May 30 02:12:45 PM PDT 24
Peak memory 218124 kb
Host smart-1fc12459-d736-451f-bc01-65076bf677f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305682272 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_security_escalation.305682272
Directory /workspace/45.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/45.lc_ctrl_smoke.1067049352
Short name T356
Test name
Test status
Simulation time 68316797 ps
CPU time 1.58 seconds
Started May 30 02:12:36 PM PDT 24
Finished May 30 02:12:39 PM PDT 24
Peak memory 218272 kb
Host smart-677ca587-8564-4ae8-8b58-58840e1e31cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067049352 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_smoke.1067049352
Directory /workspace/45.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_failure.3550094176
Short name T261
Test name
Test status
Simulation time 1063940828 ps
CPU time 18.37 seconds
Started May 30 02:12:34 PM PDT 24
Finished May 30 02:12:53 PM PDT 24
Peak memory 251048 kb
Host smart-67505548-f53e-423d-a7be-7cb068f1027e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550094176 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_failure.3550094176
Directory /workspace/45.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_post_trans.1975334994
Short name T864
Test name
Test status
Simulation time 94561948 ps
CPU time 8.53 seconds
Started May 30 02:12:38 PM PDT 24
Finished May 30 02:12:49 PM PDT 24
Peak memory 251048 kb
Host smart-14810ff4-cc65-4922-9dc3-d18b28b20c7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1975334994 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_post_trans.1975334994
Directory /workspace/45.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/45.lc_ctrl_stress_all.2083551592
Short name T634
Test name
Test status
Simulation time 1689248304 ps
CPU time 27.91 seconds
Started May 30 02:12:33 PM PDT 24
Finished May 30 02:13:02 PM PDT 24
Peak memory 247748 kb
Host smart-499be976-a368-433d-b113-36f45269f7d9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083551592 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.lc_ctrl_stress_all.2083551592
Directory /workspace/45.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.lc_ctrl_stress_all_with_rand_reset.538397150
Short name T102
Test name
Test status
Simulation time 25768868724 ps
CPU time 397.63 seconds
Started May 30 02:12:35 PM PDT 24
Finished May 30 02:19:14 PM PDT 24
Peak memory 283944 kb
Host smart-cf5354f2-1c6a-4242-a1da-1b8705a5328d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=538397150 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_stress_all_with_rand_reset.538397150
Directory /workspace/45.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.lc_ctrl_volatile_unlock_smoke.669408683
Short name T113
Test name
Test status
Simulation time 59041376 ps
CPU time 1.07 seconds
Started May 30 02:12:34 PM PDT 24
Finished May 30 02:12:37 PM PDT 24
Peak memory 211672 kb
Host smart-de4f479e-8aca-4ee4-ae00-c70410c30b81
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669408683 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ct
rl_volatile_unlock_smoke.669408683
Directory /workspace/45.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_alert_test.3714006232
Short name T109
Test name
Test status
Simulation time 15989518 ps
CPU time 0.84 seconds
Started May 30 02:12:36 PM PDT 24
Finished May 30 02:12:38 PM PDT 24
Peak memory 208512 kb
Host smart-1d7200a1-1e3f-439e-b803-5b45f6559bf9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714006232 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_alert_test.3714006232
Directory /workspace/46.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.lc_ctrl_errors.3655243346
Short name T254
Test name
Test status
Simulation time 1818752064 ps
CPU time 11.83 seconds
Started May 30 02:12:34 PM PDT 24
Finished May 30 02:12:48 PM PDT 24
Peak memory 217952 kb
Host smart-61f6536c-924d-4189-94c0-d37675004ed0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655243346 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_errors.3655243346
Directory /workspace/46.lc_ctrl_errors/latest

Test location /workspace/coverage/default/46.lc_ctrl_jtag_access.3300067451
Short name T10
Test name
Test status
Simulation time 659417337 ps
CPU time 4.38 seconds
Started May 30 02:12:36 PM PDT 24
Finished May 30 02:12:42 PM PDT 24
Peak memory 209524 kb
Host smart-aafc4d8e-6a63-435a-bdff-ea5afe078703
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300067451 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_jtag_access.3300067451
Directory /workspace/46.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/46.lc_ctrl_prog_failure.422185703
Short name T455
Test name
Test status
Simulation time 29045672 ps
CPU time 1.67 seconds
Started May 30 02:12:35 PM PDT 24
Finished May 30 02:12:39 PM PDT 24
Peak memory 218116 kb
Host smart-ab7d49c1-412a-40ae-9a2a-3831ec377ccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422185703 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_prog_failure.422185703
Directory /workspace/46.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_mubi.2257727765
Short name T333
Test name
Test status
Simulation time 328009624 ps
CPU time 13.62 seconds
Started May 30 02:12:36 PM PDT 24
Finished May 30 02:12:51 PM PDT 24
Peak memory 219004 kb
Host smart-4add1ac3-6652-40eb-b182-f117ac1ccd1d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257727765 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_mubi.2257727765
Directory /workspace/46.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_digest.3226383536
Short name T12
Test name
Test status
Simulation time 404464229 ps
CPU time 16.03 seconds
Started May 30 02:12:37 PM PDT 24
Finished May 30 02:12:55 PM PDT 24
Peak memory 226036 kb
Host smart-e3d1f51b-bfbe-4192-9070-98d115df724d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226383536 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_d
igest.3226383536
Directory /workspace/46.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_mux.423076864
Short name T230
Test name
Test status
Simulation time 803482029 ps
CPU time 10.24 seconds
Started May 30 02:12:35 PM PDT 24
Finished May 30 02:12:47 PM PDT 24
Peak memory 218124 kb
Host smart-8665f126-34e7-40b1-9e99-606985cfeef9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423076864 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_mux.423076864
Directory /workspace/46.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/46.lc_ctrl_security_escalation.2009832075
Short name T62
Test name
Test status
Simulation time 472692293 ps
CPU time 11.06 seconds
Started May 30 02:12:39 PM PDT 24
Finished May 30 02:12:52 PM PDT 24
Peak memory 217736 kb
Host smart-e5733480-97cd-49d3-8204-71b54d87873f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009832075 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_security_escalation.2009832075
Directory /workspace/46.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/46.lc_ctrl_smoke.3563976423
Short name T574
Test name
Test status
Simulation time 139505213 ps
CPU time 3.42 seconds
Started May 30 02:12:34 PM PDT 24
Finished May 30 02:12:39 PM PDT 24
Peak memory 217736 kb
Host smart-62f45b38-99ea-417c-874b-b73d1259454f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563976423 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_smoke.3563976423
Directory /workspace/46.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_failure.908845332
Short name T378
Test name
Test status
Simulation time 315333204 ps
CPU time 32.17 seconds
Started May 30 02:12:37 PM PDT 24
Finished May 30 02:13:11 PM PDT 24
Peak memory 251020 kb
Host smart-b16586e3-9370-45bd-ae78-f0d2a99cc8d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908845332 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_failure.908845332
Directory /workspace/46.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_post_trans.1499285615
Short name T165
Test name
Test status
Simulation time 388123118 ps
CPU time 7.97 seconds
Started May 30 02:12:36 PM PDT 24
Finished May 30 02:12:45 PM PDT 24
Peak memory 250860 kb
Host smart-492482e6-63ad-4d40-b152-0dea88b46b55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1499285615 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_post_trans.1499285615
Directory /workspace/46.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all.3599108029
Short name T728
Test name
Test status
Simulation time 5496836285 ps
CPU time 171.77 seconds
Started May 30 02:12:34 PM PDT 24
Finished May 30 02:15:27 PM PDT 24
Peak memory 421996 kb
Host smart-7a8bd764-6a31-4a74-9e30-c0325d24ef05
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599108029 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.lc_ctrl_stress_all.3599108029
Directory /workspace/46.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.lc_ctrl_volatile_unlock_smoke.2880198067
Short name T465
Test name
Test status
Simulation time 16101676 ps
CPU time 1.22 seconds
Started May 30 02:12:33 PM PDT 24
Finished May 30 02:12:36 PM PDT 24
Peak memory 211656 kb
Host smart-3cf6c5c9-d98d-4fe0-9b30-6160fa1ce8cf
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880198067 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_c
trl_volatile_unlock_smoke.2880198067
Directory /workspace/46.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_alert_test.1058352788
Short name T445
Test name
Test status
Simulation time 18201740 ps
CPU time 1.14 seconds
Started May 30 02:12:39 PM PDT 24
Finished May 30 02:12:42 PM PDT 24
Peak memory 208780 kb
Host smart-741cca8c-abc3-4283-9a0e-a30465162b53
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058352788 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_alert_test.1058352788
Directory /workspace/47.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.lc_ctrl_errors.1734283438
Short name T774
Test name
Test status
Simulation time 1225073749 ps
CPU time 15.44 seconds
Started May 30 02:12:36 PM PDT 24
Finished May 30 02:12:53 PM PDT 24
Peak memory 218072 kb
Host smart-53e93115-65d9-4961-9c56-cb3d63ab2665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734283438 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_errors.1734283438
Directory /workspace/47.lc_ctrl_errors/latest

Test location /workspace/coverage/default/47.lc_ctrl_jtag_access.2002030912
Short name T524
Test name
Test status
Simulation time 736451585 ps
CPU time 4.57 seconds
Started May 30 02:12:39 PM PDT 24
Finished May 30 02:12:45 PM PDT 24
Peak memory 209572 kb
Host smart-bd073a3a-27ac-4992-a9cc-83c42b105867
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002030912 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_jtag_access.2002030912
Directory /workspace/47.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/47.lc_ctrl_prog_failure.1324641169
Short name T462
Test name
Test status
Simulation time 218411645 ps
CPU time 2.81 seconds
Started May 30 02:12:35 PM PDT 24
Finished May 30 02:12:39 PM PDT 24
Peak memory 218016 kb
Host smart-97b319cd-2a6b-4f83-8d84-20d4befd646a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324641169 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_prog_failure.1324641169
Directory /workspace/47.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_mubi.2841276
Short name T376
Test name
Test status
Simulation time 4859646322 ps
CPU time 12.58 seconds
Started May 30 02:12:38 PM PDT 24
Finished May 30 02:12:53 PM PDT 24
Peak memory 226104 kb
Host smart-6d0c8f2c-22e5-4310-8a95-18b9aae961e5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841276 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_mubi.2841276
Directory /workspace/47.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_digest.3737274065
Short name T167
Test name
Test status
Simulation time 1222868430 ps
CPU time 10.7 seconds
Started May 30 02:12:38 PM PDT 24
Finished May 30 02:12:51 PM PDT 24
Peak memory 217976 kb
Host smart-70be221a-816f-489d-9eb0-ed9c94bc1977
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737274065 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_d
igest.3737274065
Directory /workspace/47.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_mux.644475949
Short name T296
Test name
Test status
Simulation time 2304018243 ps
CPU time 12.75 seconds
Started May 30 02:12:37 PM PDT 24
Finished May 30 02:12:52 PM PDT 24
Peak memory 218180 kb
Host smart-04e6d7cf-0190-4a6f-857f-ce1f7ba1f99f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644475949 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_mux.644475949
Directory /workspace/47.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/47.lc_ctrl_security_escalation.2922010204
Short name T64
Test name
Test status
Simulation time 424668270 ps
CPU time 10.74 seconds
Started May 30 02:12:37 PM PDT 24
Finished May 30 02:12:50 PM PDT 24
Peak memory 218064 kb
Host smart-3198645f-d9de-4762-b45f-1a5e91d36cc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922010204 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_security_escalation.2922010204
Directory /workspace/47.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/47.lc_ctrl_smoke.91041143
Short name T520
Test name
Test status
Simulation time 48047991 ps
CPU time 2.92 seconds
Started May 30 02:12:36 PM PDT 24
Finished May 30 02:12:40 PM PDT 24
Peak memory 217772 kb
Host smart-01b76c78-a8a8-4acf-b063-e9adfb41ef2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91041143 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_smoke.91041143
Directory /workspace/47.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_failure.365549579
Short name T385
Test name
Test status
Simulation time 599055328 ps
CPU time 19.42 seconds
Started May 30 02:12:36 PM PDT 24
Finished May 30 02:12:57 PM PDT 24
Peak memory 251036 kb
Host smart-f492402a-b42a-4292-a0a8-c9d1836db904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365549579 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_failure.365549579
Directory /workspace/47.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_post_trans.4001637339
Short name T39
Test name
Test status
Simulation time 97888184 ps
CPU time 8.38 seconds
Started May 30 02:12:36 PM PDT 24
Finished May 30 02:12:46 PM PDT 24
Peak memory 250992 kb
Host smart-13dff3de-6463-41cf-85cc-627d0c6168f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001637339 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_post_trans.4001637339
Directory /workspace/47.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/47.lc_ctrl_stress_all.3946030969
Short name T361
Test name
Test status
Simulation time 2521225725 ps
CPU time 112.82 seconds
Started May 30 02:12:39 PM PDT 24
Finished May 30 02:14:33 PM PDT 24
Peak memory 271432 kb
Host smart-7c081e9d-5df9-456c-828b-4dc54f955eab
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946030969 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.lc_ctrl_stress_all.3946030969
Directory /workspace/47.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.lc_ctrl_stress_all_with_rand_reset.3181766386
Short name T740
Test name
Test status
Simulation time 53913823076 ps
CPU time 254.13 seconds
Started May 30 02:12:39 PM PDT 24
Finished May 30 02:16:55 PM PDT 24
Peak memory 316420 kb
Host smart-e98059a2-5538-4216-a72e-cc7337eaa671
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3181766386 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_stress_all_with_rand_reset.3181766386
Directory /workspace/47.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.lc_ctrl_volatile_unlock_smoke.374534953
Short name T342
Test name
Test status
Simulation time 31048522 ps
CPU time 1.09 seconds
Started May 30 02:12:38 PM PDT 24
Finished May 30 02:12:41 PM PDT 24
Peak memory 212636 kb
Host smart-0e3e2fac-2375-436a-99d2-653a1865b8d2
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374534953 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ct
rl_volatile_unlock_smoke.374534953
Directory /workspace/47.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_alert_test.1218340938
Short name T349
Test name
Test status
Simulation time 61617279 ps
CPU time 1.09 seconds
Started May 30 02:12:46 PM PDT 24
Finished May 30 02:12:48 PM PDT 24
Peak memory 208716 kb
Host smart-51b2bb6f-9075-4ee4-893b-6c90560b35ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218340938 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_alert_test.1218340938
Directory /workspace/48.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.lc_ctrl_errors.4208986370
Short name T104
Test name
Test status
Simulation time 188031280 ps
CPU time 7.35 seconds
Started May 30 02:12:37 PM PDT 24
Finished May 30 02:12:47 PM PDT 24
Peak memory 218036 kb
Host smart-d29cd015-4835-4a0a-b77e-bb30851509d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208986370 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_errors.4208986370
Directory /workspace/48.lc_ctrl_errors/latest

Test location /workspace/coverage/default/48.lc_ctrl_jtag_access.3963565418
Short name T709
Test name
Test status
Simulation time 187600316 ps
CPU time 3.04 seconds
Started May 30 02:12:37 PM PDT 24
Finished May 30 02:12:41 PM PDT 24
Peak memory 217008 kb
Host smart-4610ce81-8c6f-4ec8-bd22-50ef6faf9c73
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963565418 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_jtag_access.3963565418
Directory /workspace/48.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/48.lc_ctrl_prog_failure.2465898383
Short name T250
Test name
Test status
Simulation time 180315264 ps
CPU time 3.21 seconds
Started May 30 02:12:37 PM PDT 24
Finished May 30 02:12:43 PM PDT 24
Peak memory 218120 kb
Host smart-5f526160-9a81-45dd-939d-a7216d10e7d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465898383 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_prog_failure.2465898383
Directory /workspace/48.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_mubi.3694758674
Short name T558
Test name
Test status
Simulation time 1501645377 ps
CPU time 12.88 seconds
Started May 30 02:12:37 PM PDT 24
Finished May 30 02:12:52 PM PDT 24
Peak memory 218992 kb
Host smart-deba1a02-e5a4-4e89-9568-94f8aecd2904
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694758674 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_mubi.3694758674
Directory /workspace/48.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_digest.2352715242
Short name T803
Test name
Test status
Simulation time 1032808580 ps
CPU time 9.57 seconds
Started May 30 02:12:46 PM PDT 24
Finished May 30 02:12:57 PM PDT 24
Peak memory 217948 kb
Host smart-77917542-42e5-48f5-94f8-44c9828cf45e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352715242 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_d
igest.2352715242
Directory /workspace/48.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_mux.1079532231
Short name T555
Test name
Test status
Simulation time 548135954 ps
CPU time 9.43 seconds
Started May 30 02:12:37 PM PDT 24
Finished May 30 02:12:48 PM PDT 24
Peak memory 218052 kb
Host smart-9abd7c2a-93a1-44a9-a219-67385ec7ae22
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079532231 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_mux.
1079532231
Directory /workspace/48.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/48.lc_ctrl_smoke.479810100
Short name T531
Test name
Test status
Simulation time 296517159 ps
CPU time 3.66 seconds
Started May 30 02:12:37 PM PDT 24
Finished May 30 02:12:43 PM PDT 24
Peak memory 217748 kb
Host smart-b17f7c62-0c27-421e-b464-a501d431b55e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479810100 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_smoke.479810100
Directory /workspace/48.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_failure.1459542885
Short name T840
Test name
Test status
Simulation time 2307016361 ps
CPU time 22.52 seconds
Started May 30 02:12:36 PM PDT 24
Finished May 30 02:13:00 PM PDT 24
Peak memory 250992 kb
Host smart-d0461dad-0857-4091-84f1-17371767838a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459542885 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_failure.1459542885
Directory /workspace/48.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_post_trans.924374899
Short name T360
Test name
Test status
Simulation time 231367496 ps
CPU time 2.84 seconds
Started May 30 02:12:40 PM PDT 24
Finished May 30 02:12:44 PM PDT 24
Peak memory 222160 kb
Host smart-51a7b7d1-418b-4ae4-83d0-ca9c0a9d5cda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924374899 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_post_trans.924374899
Directory /workspace/48.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all.4136411606
Short name T54
Test name
Test status
Simulation time 28123585142 ps
CPU time 124.62 seconds
Started May 30 02:12:45 PM PDT 24
Finished May 30 02:14:50 PM PDT 24
Peak memory 267476 kb
Host smart-f40272f1-70f7-4c95-8a8c-761709101272
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136411606 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.lc_ctrl_stress_all.4136411606
Directory /workspace/48.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.lc_ctrl_volatile_unlock_smoke.3241154583
Short name T831
Test name
Test status
Simulation time 12203179 ps
CPU time 0.81 seconds
Started May 30 02:12:39 PM PDT 24
Finished May 30 02:12:41 PM PDT 24
Peak memory 208196 kb
Host smart-d0f5f448-e096-4a45-9eb6-0342bd7c9c60
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241154583 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_c
trl_volatile_unlock_smoke.3241154583
Directory /workspace/48.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_alert_test.2370967846
Short name T291
Test name
Test status
Simulation time 74020931 ps
CPU time 1.13 seconds
Started May 30 02:12:49 PM PDT 24
Finished May 30 02:12:52 PM PDT 24
Peak memory 208732 kb
Host smart-88b8f20a-a732-4c53-9ee9-0bab5a21e684
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370967846 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_alert_test.2370967846
Directory /workspace/49.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.lc_ctrl_errors.4070816384
Short name T824
Test name
Test status
Simulation time 447094184 ps
CPU time 13.65 seconds
Started May 30 02:12:46 PM PDT 24
Finished May 30 02:13:00 PM PDT 24
Peak memory 218048 kb
Host smart-2db42c07-6fd3-495f-afe9-588f1aafe84e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070816384 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_errors.4070816384
Directory /workspace/49.lc_ctrl_errors/latest

Test location /workspace/coverage/default/49.lc_ctrl_jtag_access.2604256922
Short name T535
Test name
Test status
Simulation time 2198264093 ps
CPU time 16.37 seconds
Started May 30 02:12:44 PM PDT 24
Finished May 30 02:13:02 PM PDT 24
Peak memory 209604 kb
Host smart-3b36da37-d59b-4a78-ab55-73530a8ab68e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604256922 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_jtag_access.2604256922
Directory /workspace/49.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/49.lc_ctrl_prog_failure.390573733
Short name T716
Test name
Test status
Simulation time 208408407 ps
CPU time 3.73 seconds
Started May 30 02:12:44 PM PDT 24
Finished May 30 02:12:49 PM PDT 24
Peak memory 218132 kb
Host smart-bb1db855-9444-4116-a62b-323ba0d39700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390573733 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_prog_failure.390573733
Directory /workspace/49.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_mubi.2161077895
Short name T597
Test name
Test status
Simulation time 1764838408 ps
CPU time 17.88 seconds
Started May 30 02:12:50 PM PDT 24
Finished May 30 02:13:09 PM PDT 24
Peak memory 226048 kb
Host smart-c882a640-0ca8-4747-9f79-ba43671f6f3a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161077895 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_mubi.2161077895
Directory /workspace/49.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_digest.1149434914
Short name T719
Test name
Test status
Simulation time 1129422712 ps
CPU time 13.59 seconds
Started May 30 02:12:46 PM PDT 24
Finished May 30 02:13:01 PM PDT 24
Peak memory 217992 kb
Host smart-550723a9-7c27-4cb4-8422-71eec5bed18c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149434914 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_d
igest.1149434914
Directory /workspace/49.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_mux.1441480130
Short name T604
Test name
Test status
Simulation time 868339913 ps
CPU time 9.71 seconds
Started May 30 02:12:47 PM PDT 24
Finished May 30 02:12:58 PM PDT 24
Peak memory 218068 kb
Host smart-8778f827-6454-409a-abce-b7219a0ad59d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441480130 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_mux.
1441480130
Directory /workspace/49.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/49.lc_ctrl_security_escalation.76304480
Short name T576
Test name
Test status
Simulation time 551961940 ps
CPU time 12.19 seconds
Started May 30 02:12:46 PM PDT 24
Finished May 30 02:12:59 PM PDT 24
Peak memory 218128 kb
Host smart-d9054cba-4b52-4cff-8668-372d10f375f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76304480 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_security_escalation.76304480
Directory /workspace/49.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/49.lc_ctrl_smoke.11800512
Short name T539
Test name
Test status
Simulation time 44720508 ps
CPU time 1.31 seconds
Started May 30 02:12:49 PM PDT 24
Finished May 30 02:12:52 PM PDT 24
Peak memory 213528 kb
Host smart-2a9f96f2-979b-4505-92b9-0bafe2c84408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11800512 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_smoke.11800512
Directory /workspace/49.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_failure.2282941782
Short name T169
Test name
Test status
Simulation time 257954863 ps
CPU time 25.48 seconds
Started May 30 02:12:45 PM PDT 24
Finished May 30 02:13:11 PM PDT 24
Peak memory 251032 kb
Host smart-35f27ba4-9785-44a3-8195-29c2bc210a7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282941782 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_failure.2282941782
Directory /workspace/49.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_post_trans.2633164628
Short name T502
Test name
Test status
Simulation time 137452891 ps
CPU time 10.01 seconds
Started May 30 02:12:44 PM PDT 24
Finished May 30 02:12:55 PM PDT 24
Peak memory 251028 kb
Host smart-dd63d854-21e1-49fa-b3df-a7d22c355c53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633164628 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_post_trans.2633164628
Directory /workspace/49.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/49.lc_ctrl_stress_all.2812665226
Short name T636
Test name
Test status
Simulation time 28735857928 ps
CPU time 534.01 seconds
Started May 30 02:12:46 PM PDT 24
Finished May 30 02:21:41 PM PDT 24
Peak memory 282672 kb
Host smart-6267476a-d15c-4a70-b759-c779e7a9a32e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812665226 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.lc_ctrl_stress_all.2812665226
Directory /workspace/49.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.lc_ctrl_volatile_unlock_smoke.1361040523
Short name T407
Test name
Test status
Simulation time 11889089 ps
CPU time 0.96 seconds
Started May 30 02:12:48 PM PDT 24
Finished May 30 02:12:50 PM PDT 24
Peak memory 208640 kb
Host smart-9a0b07da-37d1-44bd-9a23-699e41a456b2
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361040523 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_c
trl_volatile_unlock_smoke.1361040523
Directory /workspace/49.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_alert_test.1924890882
Short name T549
Test name
Test status
Simulation time 13253041 ps
CPU time 0.88 seconds
Started May 30 02:10:02 PM PDT 24
Finished May 30 02:10:04 PM PDT 24
Peak memory 208464 kb
Host smart-8a8800e5-b7c3-46a6-a009-a008f5899d60
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924890882 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_alert_test.1924890882
Directory /workspace/5.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.lc_ctrl_claim_transition_if.182418658
Short name T41
Test name
Test status
Simulation time 11807668 ps
CPU time 1 seconds
Started May 30 02:10:03 PM PDT 24
Finished May 30 02:10:05 PM PDT 24
Peak memory 208712 kb
Host smart-faa36a89-71be-4268-8603-7c28f53dd028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182418658 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_claim_transition_if.182418658
Directory /workspace/5.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/5.lc_ctrl_errors.1066365984
Short name T856
Test name
Test status
Simulation time 793893990 ps
CPU time 10.31 seconds
Started May 30 02:10:09 PM PDT 24
Finished May 30 02:10:20 PM PDT 24
Peak memory 218048 kb
Host smart-2a6fb357-8339-4260-95f5-355aef252540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066365984 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_errors.1066365984
Directory /workspace/5.lc_ctrl_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_access.3970587452
Short name T34
Test name
Test status
Simulation time 1899917040 ps
CPU time 12.37 seconds
Started May 30 02:10:14 PM PDT 24
Finished May 30 02:10:27 PM PDT 24
Peak memory 209520 kb
Host smart-5f05f7f6-b48f-4a18-abf8-1213ce4c0f9e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970587452 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_access.3970587452
Directory /workspace/5.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_priority.2907489288
Short name T440
Test name
Test status
Simulation time 3371022356 ps
CPU time 13.09 seconds
Started May 30 02:10:14 PM PDT 24
Finished May 30 02:10:28 PM PDT 24
Peak memory 217724 kb
Host smart-846d4d8f-7311-4133-a631-5544083f3038
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907489288 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_priority.2
907489288
Directory /workspace/5.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_prog_failure.2315978157
Short name T753
Test name
Test status
Simulation time 2661184850 ps
CPU time 10.21 seconds
Started May 30 02:10:08 PM PDT 24
Finished May 30 02:10:19 PM PDT 24
Peak memory 218120 kb
Host smart-fd3147a4-31d9-4d67-8bb0-49d299228bf8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315978157 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag
_prog_failure.2315978157
Directory /workspace/5.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_regwen_during_op.4049729758
Short name T787
Test name
Test status
Simulation time 6535565999 ps
CPU time 39.4 seconds
Started May 30 02:10:11 PM PDT 24
Finished May 30 02:10:52 PM PDT 24
Peak memory 217816 kb
Host smart-207b0643-891e-412b-be78-a33e09463836
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049729758 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_regwen_during_op.4049729758
Directory /workspace/5.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_smoke.3200006296
Short name T418
Test name
Test status
Simulation time 465678393 ps
CPU time 2.63 seconds
Started May 30 02:10:04 PM PDT 24
Finished May 30 02:10:07 PM PDT 24
Peak memory 217684 kb
Host smart-38aaec56-ce5d-43e9-b356-e68f7897f1dd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200006296 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_smoke.
3200006296
Directory /workspace/5.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_failure.3999777933
Short name T7
Test name
Test status
Simulation time 27690615356 ps
CPU time 51.32 seconds
Started May 30 02:10:08 PM PDT 24
Finished May 30 02:11:00 PM PDT 24
Peak memory 279940 kb
Host smart-3a593a2d-e608-4264-9c9e-8e8bf2f2f221
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999777933 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jta
g_state_failure.3999777933
Directory /workspace/5.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_post_trans.2570325806
Short name T656
Test name
Test status
Simulation time 704922820 ps
CPU time 16.03 seconds
Started May 30 02:10:12 PM PDT 24
Finished May 30 02:10:29 PM PDT 24
Peak memory 250632 kb
Host smart-03249730-9aa5-426d-a716-2820d2a7f2dd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570325806 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_state_post_trans.2570325806
Directory /workspace/5.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_prog_failure.4208705990
Short name T764
Test name
Test status
Simulation time 342409248 ps
CPU time 3.97 seconds
Started May 30 02:10:14 PM PDT 24
Finished May 30 02:10:19 PM PDT 24
Peak memory 218084 kb
Host smart-0f2a6ef7-f4ca-447f-98de-ee195c722702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208705990 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_prog_failure.4208705990
Directory /workspace/5.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_regwen_during_op.3740886933
Short name T765
Test name
Test status
Simulation time 1004913180 ps
CPU time 16.39 seconds
Started May 30 02:10:01 PM PDT 24
Finished May 30 02:10:18 PM PDT 24
Peak memory 217764 kb
Host smart-6c87603c-5cf7-4fa3-bbbd-c6c89dff3d9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740886933 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_regwen_during_op.3740886933
Directory /workspace/5.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_mubi.2240971912
Short name T477
Test name
Test status
Simulation time 271612909 ps
CPU time 9.65 seconds
Started May 30 02:10:03 PM PDT 24
Finished May 30 02:10:13 PM PDT 24
Peak memory 218984 kb
Host smart-df82e21e-e6c1-48d1-b26b-7591ee4e8414
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240971912 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_mubi.2240971912
Directory /workspace/5.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_digest.4159067156
Short name T447
Test name
Test status
Simulation time 1195637042 ps
CPU time 9.43 seconds
Started May 30 02:10:10 PM PDT 24
Finished May 30 02:10:20 PM PDT 24
Peak memory 218052 kb
Host smart-c4d20f97-83b5-4590-80ea-504bf845b483
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159067156 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_di
gest.4159067156
Directory /workspace/5.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_mux.1522336864
Short name T661
Test name
Test status
Simulation time 955175287 ps
CPU time 18.03 seconds
Started May 30 02:10:08 PM PDT 24
Finished May 30 02:10:27 PM PDT 24
Peak memory 218064 kb
Host smart-578bcf88-c45b-4a10-b14e-f2e76bb88f34
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522336864 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_mux.1
522336864
Directory /workspace/5.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/5.lc_ctrl_security_escalation.2949611456
Short name T584
Test name
Test status
Simulation time 721275822 ps
CPU time 8.14 seconds
Started May 30 02:10:13 PM PDT 24
Finished May 30 02:10:22 PM PDT 24
Peak memory 218176 kb
Host smart-a4c158ff-39a0-4db7-b655-df864f26680a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949611456 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_security_escalation.2949611456
Directory /workspace/5.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/5.lc_ctrl_smoke.659029822
Short name T242
Test name
Test status
Simulation time 169474088 ps
CPU time 2.49 seconds
Started May 30 02:10:08 PM PDT 24
Finished May 30 02:10:11 PM PDT 24
Peak memory 217768 kb
Host smart-1cfe8a83-6e12-4be3-b15b-93696161cd22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659029822 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_smoke.659029822
Directory /workspace/5.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_failure.636977223
Short name T708
Test name
Test status
Simulation time 276514738 ps
CPU time 28.89 seconds
Started May 30 02:10:01 PM PDT 24
Finished May 30 02:10:31 PM PDT 24
Peak memory 251024 kb
Host smart-416bab5d-9f42-4846-babb-e8af73e04e48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636977223 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_failure.636977223
Directory /workspace/5.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_post_trans.400068978
Short name T622
Test name
Test status
Simulation time 321548960 ps
CPU time 11.49 seconds
Started May 30 02:10:04 PM PDT 24
Finished May 30 02:10:16 PM PDT 24
Peak memory 250936 kb
Host smart-8f616542-7dbd-4715-b96b-8af82286190e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400068978 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_post_trans.400068978
Directory /workspace/5.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_stress_all.3902353655
Short name T326
Test name
Test status
Simulation time 11428890688 ps
CPU time 245.95 seconds
Started May 30 02:10:05 PM PDT 24
Finished May 30 02:14:11 PM PDT 24
Peak memory 332952 kb
Host smart-72382ffe-e87c-4609-a543-5976070b9b3d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902353655 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.lc_ctrl_stress_all.3902353655
Directory /workspace/5.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.lc_ctrl_volatile_unlock_smoke.273295171
Short name T280
Test name
Test status
Simulation time 33258471 ps
CPU time 0.89 seconds
Started May 30 02:10:05 PM PDT 24
Finished May 30 02:10:06 PM PDT 24
Peak memory 208572 kb
Host smart-82e533eb-6ed4-4085-b15b-a0eaca97fe0e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273295171 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctr
l_volatile_unlock_smoke.273295171
Directory /workspace/5.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_alert_test.2230228302
Short name T852
Test name
Test status
Simulation time 45437270 ps
CPU time 0.9 seconds
Started May 30 02:10:20 PM PDT 24
Finished May 30 02:10:22 PM PDT 24
Peak memory 209512 kb
Host smart-4ec73406-a3fd-484a-8a65-14b8c4b9feb6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230228302 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_alert_test.2230228302
Directory /workspace/6.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.lc_ctrl_claim_transition_if.1340527232
Short name T217
Test name
Test status
Simulation time 13094059 ps
CPU time 0.99 seconds
Started May 30 02:10:04 PM PDT 24
Finished May 30 02:10:06 PM PDT 24
Peak memory 208736 kb
Host smart-b5b32cb2-2e0e-4cb4-960b-03bd5661f1fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340527232 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_claim_transition_if.1340527232
Directory /workspace/6.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/6.lc_ctrl_errors.551354264
Short name T293
Test name
Test status
Simulation time 681128055 ps
CPU time 15.74 seconds
Started May 30 02:10:02 PM PDT 24
Finished May 30 02:10:19 PM PDT 24
Peak memory 218052 kb
Host smart-a1f3afdb-1b4d-4272-8185-9731968ee36c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551354264 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_errors.551354264
Directory /workspace/6.lc_ctrl_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_access.77629994
Short name T466
Test name
Test status
Simulation time 702664489 ps
CPU time 17.94 seconds
Started May 30 02:10:05 PM PDT 24
Finished May 30 02:10:24 PM PDT 24
Peak memory 209504 kb
Host smart-30843679-9ef7-42d6-b4ea-7f22d107a148
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77629994 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_access.77629994
Directory /workspace/6.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_errors.2875509200
Short name T118
Test name
Test status
Simulation time 7134932160 ps
CPU time 57.79 seconds
Started May 30 02:10:12 PM PDT 24
Finished May 30 02:11:11 PM PDT 24
Peak memory 218048 kb
Host smart-d74d0c89-5cdb-4314-9f19-1c031a5c4efb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875509200 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_er
rors.2875509200
Directory /workspace/6.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_priority.3119503986
Short name T780
Test name
Test status
Simulation time 1017185048 ps
CPU time 8.09 seconds
Started May 30 02:10:04 PM PDT 24
Finished May 30 02:10:13 PM PDT 24
Peak memory 217396 kb
Host smart-75f99a9a-a699-408c-adba-deade924cb4b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119503986 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_priority.3
119503986
Directory /workspace/6.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_prog_failure.3500427110
Short name T170
Test name
Test status
Simulation time 1341299667 ps
CPU time 9.25 seconds
Started May 30 02:10:13 PM PDT 24
Finished May 30 02:10:23 PM PDT 24
Peak memory 218008 kb
Host smart-1d4fc984-5bbe-4fd4-b800-1eee3f57c419
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500427110 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag
_prog_failure.3500427110
Directory /workspace/6.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_regwen_during_op.3306027072
Short name T756
Test name
Test status
Simulation time 672288275 ps
CPU time 11.07 seconds
Started May 30 02:10:03 PM PDT 24
Finished May 30 02:10:15 PM PDT 24
Peak memory 217752 kb
Host smart-626072ef-e1af-4c0c-ad2d-991cd1033b5c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306027072 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_regwen_during_op.3306027072
Directory /workspace/6.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_smoke.1632435236
Short name T726
Test name
Test status
Simulation time 123138211 ps
CPU time 2.34 seconds
Started May 30 02:10:02 PM PDT 24
Finished May 30 02:10:05 PM PDT 24
Peak memory 217648 kb
Host smart-2e8a98c3-7ab1-431d-a754-1ba5ced2a38c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632435236 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_smoke.
1632435236
Directory /workspace/6.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_failure.2084419224
Short name T263
Test name
Test status
Simulation time 5705834069 ps
CPU time 43.85 seconds
Started May 30 02:10:03 PM PDT 24
Finished May 30 02:10:48 PM PDT 24
Peak memory 276624 kb
Host smart-ee9aee6c-9d53-474b-a8b7-e86b51d728ff
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084419224 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jta
g_state_failure.2084419224
Directory /workspace/6.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_post_trans.3316301269
Short name T575
Test name
Test status
Simulation time 1538058403 ps
CPU time 10.11 seconds
Started May 30 02:10:05 PM PDT 24
Finished May 30 02:10:16 PM PDT 24
Peak memory 247692 kb
Host smart-4e547731-293a-4df2-9676-1fe1cc223d73
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316301269 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_state_post_trans.3316301269
Directory /workspace/6.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_prog_failure.964145441
Short name T593
Test name
Test status
Simulation time 178136088 ps
CPU time 4.24 seconds
Started May 30 02:10:03 PM PDT 24
Finished May 30 02:10:08 PM PDT 24
Peak memory 218012 kb
Host smart-67cf6c9a-c475-4f01-98e3-8f18550f6cf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964145441 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_prog_failure.964145441
Directory /workspace/6.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_regwen_during_op.615505595
Short name T750
Test name
Test status
Simulation time 1041447817 ps
CPU time 17.9 seconds
Started May 30 02:10:13 PM PDT 24
Finished May 30 02:10:31 PM PDT 24
Peak memory 214612 kb
Host smart-d17f43a2-2e8a-42dc-859b-d31d98fbf57b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615505595 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_regwen_during_op.615505595
Directory /workspace/6.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_mubi.1451928919
Short name T649
Test name
Test status
Simulation time 538713600 ps
CPU time 23.05 seconds
Started May 30 02:10:01 PM PDT 24
Finished May 30 02:10:25 PM PDT 24
Peak memory 218984 kb
Host smart-6b5e88ea-4948-4977-9126-b60e3b251935
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451928919 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_mubi.1451928919
Directory /workspace/6.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_digest.3215418633
Short name T749
Test name
Test status
Simulation time 359627747 ps
CPU time 14.21 seconds
Started May 30 02:10:12 PM PDT 24
Finished May 30 02:10:27 PM PDT 24
Peak memory 218048 kb
Host smart-5f87d21f-c974-4c14-b7d3-a271578b0279
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215418633 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_di
gest.3215418633
Directory /workspace/6.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_mux.464221901
Short name T446
Test name
Test status
Simulation time 2562415613 ps
CPU time 11.8 seconds
Started May 30 02:10:15 PM PDT 24
Finished May 30 02:10:27 PM PDT 24
Peak memory 218072 kb
Host smart-08f652d0-3144-418b-a463-72bf155b7e12
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464221901 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_mux.464221901
Directory /workspace/6.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/6.lc_ctrl_security_escalation.1780125434
Short name T666
Test name
Test status
Simulation time 1041302468 ps
CPU time 7.64 seconds
Started May 30 02:10:02 PM PDT 24
Finished May 30 02:10:11 PM PDT 24
Peak memory 218080 kb
Host smart-0e873a2b-c500-461d-936c-375fabe861c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780125434 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_security_escalation.1780125434
Directory /workspace/6.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/6.lc_ctrl_smoke.2821404624
Short name T383
Test name
Test status
Simulation time 417852071 ps
CPU time 3.09 seconds
Started May 30 02:10:14 PM PDT 24
Finished May 30 02:10:18 PM PDT 24
Peak memory 214668 kb
Host smart-f21f1641-f1e1-434c-8a09-8537cd2d425f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821404624 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_smoke.2821404624
Directory /workspace/6.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_failure.2994407164
Short name T807
Test name
Test status
Simulation time 4515003100 ps
CPU time 30.78 seconds
Started May 30 02:10:03 PM PDT 24
Finished May 30 02:10:34 PM PDT 24
Peak memory 251076 kb
Host smart-f197cfa4-5adf-4152-974e-5528e4ecfee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994407164 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_failure.2994407164
Directory /workspace/6.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_post_trans.3685799062
Short name T395
Test name
Test status
Simulation time 77997242 ps
CPU time 7.41 seconds
Started May 30 02:10:02 PM PDT 24
Finished May 30 02:10:10 PM PDT 24
Peak memory 251032 kb
Host smart-cce9d6b8-caac-4409-a73d-d71ca4496203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685799062 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_post_trans.3685799062
Directory /workspace/6.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all.642473762
Short name T318
Test name
Test status
Simulation time 28543366279 ps
CPU time 329 seconds
Started May 30 02:10:02 PM PDT 24
Finished May 30 02:15:32 PM PDT 24
Peak memory 389232 kb
Host smart-1165f31a-a5b2-4ff3-9499-f0bc0137128d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642473762 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.lc_ctrl_stress_all.642473762
Directory /workspace/6.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.lc_ctrl_volatile_unlock_smoke.2679332979
Short name T542
Test name
Test status
Simulation time 12862953 ps
CPU time 1.09 seconds
Started May 30 02:10:03 PM PDT 24
Finished May 30 02:10:05 PM PDT 24
Peak memory 211668 kb
Host smart-3c37a217-568a-4879-9c78-5ef014d9e1e8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679332979 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ct
rl_volatile_unlock_smoke.2679332979
Directory /workspace/6.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_alert_test.2145083335
Short name T799
Test name
Test status
Simulation time 39666513 ps
CPU time 0.83 seconds
Started May 30 02:10:19 PM PDT 24
Finished May 30 02:10:21 PM PDT 24
Peak memory 209412 kb
Host smart-3af44024-6976-4aab-b7de-4a1490c2aef0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145083335 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_alert_test.2145083335
Directory /workspace/7.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.lc_ctrl_claim_transition_if.1703722201
Short name T375
Test name
Test status
Simulation time 22085769 ps
CPU time 0.93 seconds
Started May 30 02:10:21 PM PDT 24
Finished May 30 02:10:23 PM PDT 24
Peak memory 208776 kb
Host smart-1c8b752f-64aa-4254-940e-0b3c26e6aaa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1703722201 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_claim_transition_if.1703722201
Directory /workspace/7.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/7.lc_ctrl_errors.319468954
Short name T268
Test name
Test status
Simulation time 290116973 ps
CPU time 14.93 seconds
Started May 30 02:10:22 PM PDT 24
Finished May 30 02:10:38 PM PDT 24
Peak memory 217996 kb
Host smart-42da4b50-509e-4d58-881b-c8d071c66473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319468954 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_errors.319468954
Directory /workspace/7.lc_ctrl_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_access.739763243
Short name T607
Test name
Test status
Simulation time 976305213 ps
CPU time 3.33 seconds
Started May 30 02:10:18 PM PDT 24
Finished May 30 02:10:22 PM PDT 24
Peak memory 209584 kb
Host smart-2080c828-0217-4d33-b667-961a8b8ee81a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739763243 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_access.739763243
Directory /workspace/7.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_errors.1907081942
Short name T396
Test name
Test status
Simulation time 7695129017 ps
CPU time 65.71 seconds
Started May 30 02:10:20 PM PDT 24
Finished May 30 02:11:27 PM PDT 24
Peak memory 218920 kb
Host smart-b50dd443-7af7-4667-a13a-af8df55691a5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907081942 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_er
rors.1907081942
Directory /workspace/7.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_priority.1191382596
Short name T833
Test name
Test status
Simulation time 143731695 ps
CPU time 4.05 seconds
Started May 30 02:10:21 PM PDT 24
Finished May 30 02:10:27 PM PDT 24
Peak memory 217904 kb
Host smart-13e4d21e-7119-4876-88e5-bbd242d22ee4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191382596 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_priority.1
191382596
Directory /workspace/7.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_prog_failure.465455092
Short name T384
Test name
Test status
Simulation time 443026120 ps
CPU time 6.15 seconds
Started May 30 02:10:19 PM PDT 24
Finished May 30 02:10:26 PM PDT 24
Peak memory 218024 kb
Host smart-25830308-32b9-48e9-b05a-a23b5784def5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465455092 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_
prog_failure.465455092
Directory /workspace/7.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_regwen_during_op.490822689
Short name T270
Test name
Test status
Simulation time 936069505 ps
CPU time 14.2 seconds
Started May 30 02:10:17 PM PDT 24
Finished May 30 02:10:32 PM PDT 24
Peak memory 217608 kb
Host smart-f4e108fb-b7e3-46ad-840e-6ccd9504be4b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490822689 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_j
tag_regwen_during_op.490822689
Directory /workspace/7.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_smoke.4084310894
Short name T88
Test name
Test status
Simulation time 204926820 ps
CPU time 6.81 seconds
Started May 30 02:10:21 PM PDT 24
Finished May 30 02:10:29 PM PDT 24
Peak memory 217644 kb
Host smart-1efa9002-d1d8-430a-9207-2e4703f80b89
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084310894 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_smoke.
4084310894
Directory /workspace/7.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_failure.1975133670
Short name T742
Test name
Test status
Simulation time 7059341746 ps
CPU time 56.34 seconds
Started May 30 02:10:22 PM PDT 24
Finished May 30 02:11:20 PM PDT 24
Peak memory 276660 kb
Host smart-65d8664c-4942-4eaa-88f7-c9f5d9f2bdac
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975133670 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jta
g_state_failure.1975133670
Directory /workspace/7.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_post_trans.3603113490
Short name T222
Test name
Test status
Simulation time 368093110 ps
CPU time 7.77 seconds
Started May 30 02:10:20 PM PDT 24
Finished May 30 02:10:28 PM PDT 24
Peak memory 222992 kb
Host smart-153d6f19-abbf-4213-b3ba-dc1b13918d83
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603113490 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_state_post_trans.3603113490
Directory /workspace/7.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_prog_failure.2486704790
Short name T4
Test name
Test status
Simulation time 75815522 ps
CPU time 1.99 seconds
Started May 30 02:10:21 PM PDT 24
Finished May 30 02:10:25 PM PDT 24
Peak memory 218116 kb
Host smart-cf8ed407-c17f-43ef-9046-3379f8288637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486704790 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_prog_failure.2486704790
Directory /workspace/7.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_regwen_during_op.2742341114
Short name T701
Test name
Test status
Simulation time 1164591950 ps
CPU time 19.5 seconds
Started May 30 02:10:20 PM PDT 24
Finished May 30 02:10:40 PM PDT 24
Peak memory 217740 kb
Host smart-fb2cf199-0460-4e7d-9446-c1ccd2229b2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742341114 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_regwen_during_op.2742341114
Directory /workspace/7.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_mubi.3198563224
Short name T471
Test name
Test status
Simulation time 912443799 ps
CPU time 12.53 seconds
Started May 30 02:10:21 PM PDT 24
Finished May 30 02:10:35 PM PDT 24
Peak memory 226020 kb
Host smart-10645594-1c8b-45d8-a7a5-1e3d4dbeca02
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198563224 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_mubi.3198563224
Directory /workspace/7.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_digest.4126818768
Short name T846
Test name
Test status
Simulation time 225158080 ps
CPU time 10.31 seconds
Started May 30 02:10:20 PM PDT 24
Finished May 30 02:10:32 PM PDT 24
Peak memory 217928 kb
Host smart-ab22c710-5b4b-4bdd-adc4-a5d3bd2c6cc5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126818768 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_di
gest.4126818768
Directory /workspace/7.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_mux.1311585417
Short name T311
Test name
Test status
Simulation time 378436647 ps
CPU time 14.43 seconds
Started May 30 02:10:20 PM PDT 24
Finished May 30 02:10:35 PM PDT 24
Peak memory 218056 kb
Host smart-b1287c9b-e592-4957-b596-b351bf47c54b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311585417 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_mux.1
311585417
Directory /workspace/7.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/7.lc_ctrl_security_escalation.2767267501
Short name T677
Test name
Test status
Simulation time 331903087 ps
CPU time 6.44 seconds
Started May 30 02:10:22 PM PDT 24
Finished May 30 02:10:30 PM PDT 24
Peak memory 218172 kb
Host smart-00a0a8c6-5bd3-4035-99be-28d88f300c57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767267501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_security_escalation.2767267501
Directory /workspace/7.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/7.lc_ctrl_smoke.3380201835
Short name T79
Test name
Test status
Simulation time 24830737 ps
CPU time 1.18 seconds
Started May 30 02:10:21 PM PDT 24
Finished May 30 02:10:23 PM PDT 24
Peak memory 211948 kb
Host smart-198a38b4-2f0f-4b26-be6e-dfb779aec6d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380201835 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_smoke.3380201835
Directory /workspace/7.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_failure.3256445435
Short name T377
Test name
Test status
Simulation time 1063090677 ps
CPU time 28.49 seconds
Started May 30 02:10:21 PM PDT 24
Finished May 30 02:10:51 PM PDT 24
Peak memory 251004 kb
Host smart-180277dc-0ce1-4852-b227-8edffc7436a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256445435 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_failure.3256445435
Directory /workspace/7.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_post_trans.2039829356
Short name T485
Test name
Test status
Simulation time 53745610 ps
CPU time 6.32 seconds
Started May 30 02:10:21 PM PDT 24
Finished May 30 02:10:29 PM PDT 24
Peak memory 246608 kb
Host smart-2bdaf672-5e04-474e-9327-2a48e447ef37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039829356 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_post_trans.2039829356
Directory /workspace/7.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_stress_all.1726422206
Short name T660
Test name
Test status
Simulation time 5186210468 ps
CPU time 109.66 seconds
Started May 30 02:10:24 PM PDT 24
Finished May 30 02:12:15 PM PDT 24
Peak memory 267496 kb
Host smart-fb69035a-5686-4395-9bb4-898f03bbae32
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726422206 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.lc_ctrl_stress_all.1726422206
Directory /workspace/7.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.lc_ctrl_volatile_unlock_smoke.2347801241
Short name T687
Test name
Test status
Simulation time 45923257 ps
CPU time 0.92 seconds
Started May 30 02:10:21 PM PDT 24
Finished May 30 02:10:24 PM PDT 24
Peak memory 208640 kb
Host smart-af4a60fa-3895-4cb0-98d0-c97493c53d9f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347801241 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ct
rl_volatile_unlock_smoke.2347801241
Directory /workspace/7.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_alert_test.3588230697
Short name T228
Test name
Test status
Simulation time 13657680 ps
CPU time 0.89 seconds
Started May 30 02:10:21 PM PDT 24
Finished May 30 02:10:23 PM PDT 24
Peak memory 208736 kb
Host smart-7a4d7f34-683b-45e3-ae64-f8497a40f90e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588230697 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_alert_test.3588230697
Directory /workspace/8.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.lc_ctrl_claim_transition_if.3961572469
Short name T294
Test name
Test status
Simulation time 23468732 ps
CPU time 1.01 seconds
Started May 30 02:10:21 PM PDT 24
Finished May 30 02:10:24 PM PDT 24
Peak memory 208708 kb
Host smart-163883a4-e353-41be-a175-e131108be5c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961572469 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_claim_transition_if.3961572469
Directory /workspace/8.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/8.lc_ctrl_errors.2483025599
Short name T843
Test name
Test status
Simulation time 779016896 ps
CPU time 14.56 seconds
Started May 30 02:10:17 PM PDT 24
Finished May 30 02:10:33 PM PDT 24
Peak memory 217936 kb
Host smart-c4ff84f6-f183-46b3-a25d-e426e9927207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483025599 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_errors.2483025599
Directory /workspace/8.lc_ctrl_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_access.4083924337
Short name T854
Test name
Test status
Simulation time 2687798257 ps
CPU time 10.9 seconds
Started May 30 02:10:22 PM PDT 24
Finished May 30 02:10:34 PM PDT 24
Peak memory 209620 kb
Host smart-7e36733b-36ae-4d49-907a-fa4f1d8c4439
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083924337 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_access.4083924337
Directory /workspace/8.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_errors.1481893869
Short name T861
Test name
Test status
Simulation time 8522928822 ps
CPU time 32.26 seconds
Started May 30 02:10:19 PM PDT 24
Finished May 30 02:10:52 PM PDT 24
Peak memory 218992 kb
Host smart-bd855710-d96a-491b-b8c3-f2b95e1561eb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481893869 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_er
rors.1481893869
Directory /workspace/8.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_priority.2610581481
Short name T9
Test name
Test status
Simulation time 3891120824 ps
CPU time 11.94 seconds
Started May 30 02:10:20 PM PDT 24
Finished May 30 02:10:33 PM PDT 24
Peak memory 217872 kb
Host smart-c00673f4-6a0b-4cfe-95c5-a8bd497bfddf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610581481 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_priority.2
610581481
Directory /workspace/8.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_prog_failure.2451776903
Short name T743
Test name
Test status
Simulation time 1241433421 ps
CPU time 8.61 seconds
Started May 30 02:10:21 PM PDT 24
Finished May 30 02:10:31 PM PDT 24
Peak memory 217960 kb
Host smart-93cdcac0-2f9e-48ae-bfcb-2342f8014bb9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451776903 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag
_prog_failure.2451776903
Directory /workspace/8.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_regwen_during_op.2563468964
Short name T483
Test name
Test status
Simulation time 882301615 ps
CPU time 24.52 seconds
Started May 30 02:10:19 PM PDT 24
Finished May 30 02:10:45 PM PDT 24
Peak memory 217744 kb
Host smart-cb53e871-b042-41d5-b172-5bb02643d355
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563468964 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_regwen_during_op.2563468964
Directory /workspace/8.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_smoke.3513023305
Short name T507
Test name
Test status
Simulation time 1466627007 ps
CPU time 8.62 seconds
Started May 30 02:10:20 PM PDT 24
Finished May 30 02:10:29 PM PDT 24
Peak memory 217648 kb
Host smart-46906354-1316-44e7-b002-217cba974784
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513023305 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_smoke.
3513023305
Directory /workspace/8.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_failure.3496007542
Short name T338
Test name
Test status
Simulation time 24961842740 ps
CPU time 30.96 seconds
Started May 30 02:10:21 PM PDT 24
Finished May 30 02:10:54 PM PDT 24
Peak memory 276684 kb
Host smart-bffb5769-d3ac-4cca-8099-c3f19e341b9f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496007542 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jta
g_state_failure.3496007542
Directory /workspace/8.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_post_trans.1692479776
Short name T662
Test name
Test status
Simulation time 763791661 ps
CPU time 13.61 seconds
Started May 30 02:10:21 PM PDT 24
Finished May 30 02:10:36 PM PDT 24
Peak memory 250972 kb
Host smart-57991023-66c8-4eef-8f36-af3a1982b2e6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692479776 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_state_post_trans.1692479776
Directory /workspace/8.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_prog_failure.4243852076
Short name T826
Test name
Test status
Simulation time 200574685 ps
CPU time 3.73 seconds
Started May 30 02:10:17 PM PDT 24
Finished May 30 02:10:21 PM PDT 24
Peak memory 218028 kb
Host smart-825dd15d-eb78-4aa6-b0b6-1a6abe5ccf73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243852076 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_prog_failure.4243852076
Directory /workspace/8.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_regwen_during_op.292227995
Short name T45
Test name
Test status
Simulation time 364820249 ps
CPU time 20.21 seconds
Started May 30 02:10:18 PM PDT 24
Finished May 30 02:10:39 PM PDT 24
Peak memory 217740 kb
Host smart-ece21bb0-bb33-4174-85a0-c218e2fbbe1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292227995 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_regwen_during_op.292227995
Directory /workspace/8.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_mubi.4254224535
Short name T239
Test name
Test status
Simulation time 330988261 ps
CPU time 11.42 seconds
Started May 30 02:10:20 PM PDT 24
Finished May 30 02:10:32 PM PDT 24
Peak memory 226096 kb
Host smart-de93ac80-2e65-4675-80de-f7d7c981c288
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254224535 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_mubi.4254224535
Directory /workspace/8.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_digest.2387257477
Short name T184
Test name
Test status
Simulation time 420723384 ps
CPU time 16.19 seconds
Started May 30 02:10:23 PM PDT 24
Finished May 30 02:10:41 PM PDT 24
Peak memory 217996 kb
Host smart-0060c82b-0e8a-41ed-aa20-ffef8c593eeb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387257477 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_di
gest.2387257477
Directory /workspace/8.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_mux.3310364289
Short name T367
Test name
Test status
Simulation time 199650015 ps
CPU time 8.06 seconds
Started May 30 02:10:21 PM PDT 24
Finished May 30 02:10:31 PM PDT 24
Peak memory 218072 kb
Host smart-15d8ab78-de36-4d90-b478-e1531ced0921
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310364289 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_mux.3
310364289
Directory /workspace/8.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/8.lc_ctrl_security_escalation.3371891013
Short name T417
Test name
Test status
Simulation time 766466241 ps
CPU time 6.27 seconds
Started May 30 02:10:26 PM PDT 24
Finished May 30 02:10:33 PM PDT 24
Peak memory 218244 kb
Host smart-a774a824-e459-440d-9409-b2eecd9792e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3371891013 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_security_escalation.3371891013
Directory /workspace/8.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/8.lc_ctrl_smoke.479966931
Short name T533
Test name
Test status
Simulation time 192613286 ps
CPU time 4.95 seconds
Started May 30 02:10:22 PM PDT 24
Finished May 30 02:10:28 PM PDT 24
Peak memory 217860 kb
Host smart-f8ed6d13-504e-43be-9d15-c9f843adbe9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479966931 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_smoke.479966931
Directory /workspace/8.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_failure.3186133429
Short name T499
Test name
Test status
Simulation time 748108268 ps
CPU time 21.12 seconds
Started May 30 02:10:23 PM PDT 24
Finished May 30 02:10:46 PM PDT 24
Peak memory 251044 kb
Host smart-9d307fb9-424b-4477-82eb-7683d912cc8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186133429 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_failure.3186133429
Directory /workspace/8.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_post_trans.958261436
Short name T324
Test name
Test status
Simulation time 522933623 ps
CPU time 8.62 seconds
Started May 30 02:10:19 PM PDT 24
Finished May 30 02:10:28 PM PDT 24
Peak memory 251028 kb
Host smart-e1c87986-562c-4228-be2f-69f3116cc0ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958261436 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_post_trans.958261436
Directory /workspace/8.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all.2418903994
Short name T834
Test name
Test status
Simulation time 9654256106 ps
CPU time 319.18 seconds
Started May 30 02:10:21 PM PDT 24
Finished May 30 02:15:41 PM PDT 24
Peak memory 302020 kb
Host smart-25738c9d-42da-4300-a8c0-5be1295fe4b9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418903994 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.lc_ctrl_stress_all.2418903994
Directory /workspace/8.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.lc_ctrl_volatile_unlock_smoke.2118730338
Short name T300
Test name
Test status
Simulation time 30450816 ps
CPU time 0.8 seconds
Started May 30 02:10:18 PM PDT 24
Finished May 30 02:10:20 PM PDT 24
Peak memory 208412 kb
Host smart-9028fb39-c381-43c9-b2d8-23bc3a3806f5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118730338 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ct
rl_volatile_unlock_smoke.2118730338
Directory /workspace/8.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_alert_test.3904467791
Short name T183
Test name
Test status
Simulation time 18265302 ps
CPU time 1.15 seconds
Started May 30 02:10:38 PM PDT 24
Finished May 30 02:10:40 PM PDT 24
Peak memory 208728 kb
Host smart-20df3254-b933-48e5-b5eb-ea871e90da84
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904467791 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_alert_test.3904467791
Directory /workspace/9.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.lc_ctrl_claim_transition_if.2542782808
Short name T397
Test name
Test status
Simulation time 15275081 ps
CPU time 0.78 seconds
Started May 30 02:10:25 PM PDT 24
Finished May 30 02:10:27 PM PDT 24
Peak memory 208664 kb
Host smart-35a874ed-fe11-423f-8ad1-d6f3c4dc5107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542782808 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_claim_transition_if.2542782808
Directory /workspace/9.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/9.lc_ctrl_errors.2854589267
Short name T283
Test name
Test status
Simulation time 804157874 ps
CPU time 9.71 seconds
Started May 30 02:10:32 PM PDT 24
Finished May 30 02:10:42 PM PDT 24
Peak memory 218084 kb
Host smart-89e54aa3-9161-4035-a2a0-5c52747e3b34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854589267 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_errors.2854589267
Directory /workspace/9.lc_ctrl_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_access.2485495171
Short name T815
Test name
Test status
Simulation time 83625428 ps
CPU time 1.64 seconds
Started May 30 02:10:36 PM PDT 24
Finished May 30 02:10:38 PM PDT 24
Peak memory 209536 kb
Host smart-9538fe78-a313-48f7-a120-869a140a654a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485495171 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_access.2485495171
Directory /workspace/9.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_errors.4232970695
Short name T186
Test name
Test status
Simulation time 21118175133 ps
CPU time 119.57 seconds
Started May 30 02:10:25 PM PDT 24
Finished May 30 02:12:26 PM PDT 24
Peak memory 218980 kb
Host smart-ad52930e-cd0a-4e5f-8fb1-ff2252cf2c22
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232970695 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_er
rors.4232970695
Directory /workspace/9.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_priority.2977761384
Short name T240
Test name
Test status
Simulation time 332518488 ps
CPU time 5.01 seconds
Started May 30 02:10:35 PM PDT 24
Finished May 30 02:10:41 PM PDT 24
Peak memory 217868 kb
Host smart-d8504634-a833-462e-b36f-546a1197d39e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977761384 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_priority.2
977761384
Directory /workspace/9.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_prog_failure.4219452060
Short name T330
Test name
Test status
Simulation time 362702404 ps
CPU time 3.66 seconds
Started May 30 02:10:24 PM PDT 24
Finished May 30 02:10:29 PM PDT 24
Peak memory 218068 kb
Host smart-c6f77aa9-0f95-4907-ac00-96f379e3d81a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219452060 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag
_prog_failure.4219452060
Directory /workspace/9.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_regwen_during_op.2622890478
Short name T329
Test name
Test status
Simulation time 3470341722 ps
CPU time 14.63 seconds
Started May 30 02:10:26 PM PDT 24
Finished May 30 02:10:42 PM PDT 24
Peak memory 217760 kb
Host smart-3091aec6-c63a-46e0-b2d7-3b28515ea19c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622890478 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_regwen_during_op.2622890478
Directory /workspace/9.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_smoke.503657181
Short name T368
Test name
Test status
Simulation time 743090399 ps
CPU time 5.04 seconds
Started May 30 02:10:37 PM PDT 24
Finished May 30 02:10:42 PM PDT 24
Peak memory 217688 kb
Host smart-af20c44d-040e-45e6-b3b7-d083299ece1f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503657181 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_smoke.503657181
Directory /workspace/9.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_failure.727445471
Short name T654
Test name
Test status
Simulation time 1738731277 ps
CPU time 73.84 seconds
Started May 30 02:10:32 PM PDT 24
Finished May 30 02:11:47 PM PDT 24
Peak memory 267328 kb
Host smart-316c530f-4b04-4465-b343-48a955e5f7d3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727445471 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag
_state_failure.727445471
Directory /workspace/9.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_post_trans.1541505904
Short name T617
Test name
Test status
Simulation time 1816010444 ps
CPU time 9.72 seconds
Started May 30 02:10:32 PM PDT 24
Finished May 30 02:10:43 PM PDT 24
Peak memory 246484 kb
Host smart-653838af-9945-42a6-b4d4-f3617abc196e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541505904 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_state_post_trans.1541505904
Directory /workspace/9.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_prog_failure.494628675
Short name T752
Test name
Test status
Simulation time 29308924 ps
CPU time 2.13 seconds
Started May 30 02:10:24 PM PDT 24
Finished May 30 02:10:27 PM PDT 24
Peak memory 218004 kb
Host smart-9e691fd0-ce71-44c3-9420-23df66e3c889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494628675 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_prog_failure.494628675
Directory /workspace/9.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_regwen_during_op.2726771636
Short name T190
Test name
Test status
Simulation time 660224358 ps
CPU time 18.41 seconds
Started May 30 02:10:26 PM PDT 24
Finished May 30 02:10:45 PM PDT 24
Peak memory 217776 kb
Host smart-00671c51-9dc7-4e17-abef-5eb1a91ac4a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726771636 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_regwen_during_op.2726771636
Directory /workspace/9.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_mubi.2174745730
Short name T106
Test name
Test status
Simulation time 1388159923 ps
CPU time 18.83 seconds
Started May 30 02:10:24 PM PDT 24
Finished May 30 02:10:44 PM PDT 24
Peak memory 219004 kb
Host smart-9614c158-8855-43b4-8cde-5c4b27fc9171
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174745730 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_mubi.2174745730
Directory /workspace/9.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_digest.2765357571
Short name T478
Test name
Test status
Simulation time 2319410542 ps
CPU time 19 seconds
Started May 30 02:10:38 PM PDT 24
Finished May 30 02:10:58 PM PDT 24
Peak memory 218040 kb
Host smart-5130e852-a2eb-472b-a0cc-6b58c15580d1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765357571 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_di
gest.2765357571
Directory /workspace/9.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_mux.1143795980
Short name T245
Test name
Test status
Simulation time 238935302 ps
CPU time 6.98 seconds
Started May 30 02:10:34 PM PDT 24
Finished May 30 02:10:42 PM PDT 24
Peak memory 218028 kb
Host smart-ce5d639f-9407-4b89-abef-e236524f6d91
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143795980 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_mux.1
143795980
Directory /workspace/9.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/9.lc_ctrl_security_escalation.300200587
Short name T530
Test name
Test status
Simulation time 2243961434 ps
CPU time 13.21 seconds
Started May 30 02:10:35 PM PDT 24
Finished May 30 02:10:49 PM PDT 24
Peak memory 218144 kb
Host smart-f9963fef-55f2-465a-9ecb-ae88589f13c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300200587 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_security_escalation.300200587
Directory /workspace/9.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/9.lc_ctrl_smoke.2273809798
Short name T93
Test name
Test status
Simulation time 176815603 ps
CPU time 3.27 seconds
Started May 30 02:10:21 PM PDT 24
Finished May 30 02:10:26 PM PDT 24
Peak memory 222984 kb
Host smart-5547a211-c9e3-411a-9668-70d5499095dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273809798 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_smoke.2273809798
Directory /workspace/9.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_failure.3714378131
Short name T457
Test name
Test status
Simulation time 248978466 ps
CPU time 22.3 seconds
Started May 30 02:10:23 PM PDT 24
Finished May 30 02:10:47 PM PDT 24
Peak memory 251020 kb
Host smart-9ae74120-d478-43f8-a685-090f9415c010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714378131 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_failure.3714378131
Directory /workspace/9.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_post_trans.2942511054
Short name T428
Test name
Test status
Simulation time 49763970 ps
CPU time 9.57 seconds
Started May 30 02:10:24 PM PDT 24
Finished May 30 02:10:35 PM PDT 24
Peak memory 250980 kb
Host smart-5735b26e-5500-408d-a51f-897bdaf65ccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942511054 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_post_trans.2942511054
Directory /workspace/9.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_stress_all.3223104550
Short name T577
Test name
Test status
Simulation time 38636449115 ps
CPU time 165.67 seconds
Started May 30 02:10:23 PM PDT 24
Finished May 30 02:13:10 PM PDT 24
Peak memory 226200 kb
Host smart-628eb271-d2ba-45c0-a262-b189cec5cf94
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223104550 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.lc_ctrl_stress_all.3223104550
Directory /workspace/9.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.lc_ctrl_stress_all_with_rand_reset.714401156
Short name T162
Test name
Test status
Simulation time 108795065054 ps
CPU time 348.16 seconds
Started May 30 02:10:36 PM PDT 24
Finished May 30 02:16:26 PM PDT 24
Peak memory 270012 kb
Host smart-cce5bac7-a3e7-4591-be2a-d0be8e04cb3e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=714401156 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_stress_all_with_rand_reset.714401156
Directory /workspace/9.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.lc_ctrl_volatile_unlock_smoke.4026479126
Short name T53
Test name
Test status
Simulation time 20205557 ps
CPU time 0.86 seconds
Started May 30 02:10:22 PM PDT 24
Finished May 30 02:10:24 PM PDT 24
Peak memory 208520 kb
Host smart-6a2b6a8b-391d-454b-a94f-a3e95d82b813
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026479126 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ct
rl_volatile_unlock_smoke.4026479126
Directory /workspace/9.lc_ctrl_volatile_unlock_smoke/latest
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