Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

98946022

1

T1

1186

T2

1090

T3

25351

auto[1]

1300287

1

T3

11151

T11

2574

T13

198

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

98968235

1

T1

1186

T2

1090

T3

25762

auto[1]

1278074

1

T3

10740

T11

3960

T14

2970

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	6921372	1			T1	124		T2	94		T3	7645
auto[IdleSt]	21446174	1			T1	1062		T2	50		T3	6425
auto[ClkMuxSt]	33900	1			T3	75		T4	15		T5	11
auto[CntIncrSt]	33663	1			T3	74		T4	15		T5	11
auto[CntProgSt]	1571145	1			T3	140		T4	2006		T5	22
auto[TransCheckSt]	26408	1			T3	60		T4	15		T5	11
auto[TokenHashSt]	39893792	1			T3	6046		T4	160		T5	538
auto[FlashRmaSt]	27184	1			T3	57		T4	19		T5	11
auto[TokenCheck0St]	12049	1			T3	30		T4	15		T5	11
auto[TokenCheck1St]	8869	1			T3	28		T4	15		T5	11
auto[TransProgSt]	380780	1			T3	48		T4	2482		T5	22
auto[PostTransSt]	12685185	1			T2	946		T3	32		T4	706
auto[ScrapSt]	247801	1			T3	6		T4	34		T5	311
auto[EscalateSt]	6163736	1			T3	15836		T11	8306		T13	415
auto[InvalidSt]	10792507	1			T11	4973		T13	444		T14	4378

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1744	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	10792507	1			T11	4973		T13	444		T14	4378
EscalateSt	6163736	1			T3	15836		T11	8306		T13	415
ScrapSt	247801	1			T3	6		T4	34		T5	311
PostTransSt	12685185	1			T2	946		T3	32		T4	706
TransProgSt	380780	1			T3	48		T4	2482		T5	22
TokenCheck1St	8869	1			T3	28		T4	15		T5	11
TokenCheck0St	12049	1			T3	30		T4	15		T5	11
FlashRmaSt	27184	1			T3	57		T4	19		T5	11
TokenHashSt	39893792	1			T3	6046		T4	160		T5	538
TransCheckSt	26408	1			T3	60		T4	15		T5	11
CntProgSt	1571145	1			T3	140		T4	2006		T5	22
CntIncrSt	33663	1			T3	74		T4	15		T5	11
ClkMuxSt	33900	1			T3	75		T4	15		T5	11
IdleSt	21446174	1			T1	1062		T2	50		T3	6425
ResetSt	6921372	1			T1	124		T2	94		T3	7645
arcs[ResetSt=>IdleSt]	50667	1			T1	1		T2	1		T3	83
arcs[IdleSt=>ScrapSt]	281	1			T3	2		T4	1		T5	1
arcs[IdleSt=>ClkMuxSt]	33721	1			T3	75		T4	15		T5	11
arcs[ClkMuxSt=>CntIncrSt]	33663	1			T3	74		T4	15		T5	11
arcs[CntIncrSt=>PostTransSt]	1806	1			T41	13		T42	9		T20	8
arcs[CntIncrSt=>CntProgSt]	31789	1			T3	74		T4	15		T5	11
arcs[CntProgSt=>PostTransSt]	4367	1			T16	19		T41	11		T48	15
arcs[CntProgSt=>TransCheckSt]	26408	1			T3	60		T4	15		T5	11
arcs[TransCheckSt=>PostTransSt]	3499	1			T12	39		T23	50		T41	8
arcs[TransCheckSt=>TokenHashSt]	22780	1			T3	53		T4	15		T5	11
arcs[TokenHashSt=>PostTransSt]	9936	1			T12	8		T16	8		T23	4
arcs[TokenHashSt=>FlashRmaSt]	12147	1			T3	31		T4	15		T5	11
arcs[FlashRmaSt=>TokenCheck0St]	12049	1			T3	30		T4	15		T5	11
arcs[TokenCheck0St=>PostTransSt]	3159	1			T12	19		T16	10		T23	20
arcs[TokenCheck0St=>TokenCheck1St]	8869	1			T3	28		T4	15		T5	11
arcs[TokenCheck1St=>PostTransSt]	624	1			T12	12		T23	16		T48	1
arcs[TransProgSt=>PostTransSt]	7413	1			T3	17		T4	15		T5	11
arcs[IdleSt=>EscalateSt]	178	1			T3	5		T57	8		T60	5
arcs[ClkMuxSt=>EscalateSt]	58	1			T3	1		T57	1		T58	1
arcs[CntIncrSt=>EscalateSt]	68	1			T58	2		T59	2		T60	2
arcs[CntProgSt=>EscalateSt]	1014	1			T3	14		T57	7		T58	6
arcs[TransCheckSt=>EscalateSt]	129	1			T3	7		T57	8		T58	10
arcs[TokenHashSt=>EscalateSt]	697	1			T3	22		T57	12		T46	1
arcs[FlashRmaSt=>EscalateSt]	98	1			T3	1		T57	1		T58	3
arcs[TokenCheck0St=>EscalateSt]	21	1			T3	2		T59	2		T62	1
arcs[TokenCheck1St=>EscalateSt]	134	1			T3	2		T58	6		T59	1
arcs[TransProgSt=>EscalateSt]	698	1			T3	9		T57	9		T58	11
arcs[PostTransSt=>EscalateSt]	4601	1			T3	17		T16	19		T41	11
arcs[InvalidSt=>EscalateSt]	12760	1			T11	66		T13	2		T14	59

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	6921197	1			T1	124		T2	94		T3	7643
auto[0]	auto[IdleSt]	21446050	1			T1	1062		T2	50		T3	6421
auto[0]	auto[ClkMuxSt]	33862	1			T3	75		T4	15		T5	11
auto[0]	auto[CntIncrSt]	33611	1			T3	74		T4	15		T5	11
auto[0]	auto[CntProgSt]	1570458	1			T3	129		T4	2006		T5	22
auto[0]	auto[TransCheckSt]	26321	1			T3	56		T4	15		T5	11
auto[0]	auto[TokenHashSt]	39893341	1			T3	6029		T4	160		T5	538
auto[0]	auto[FlashRmaSt]	27116	1			T3	56		T4	19		T5	11
auto[0]	auto[TokenCheck0St]	12032	1			T3	28		T4	15		T5	11
auto[0]	auto[TokenCheck1St]	8775	1			T3	26		T4	15		T5	11
auto[0]	auto[TransProgSt]	380297	1			T3	41		T4	2482		T5	22
auto[0]	auto[PostTransSt]	12682874	1			T2	946		T3	23		T4	706
auto[0]	auto[ScrapSt]	247750	1			T3	4		T4	34		T5	311
auto[0]	auto[EscalateSt]	4874528	1			T3	4746		T11	5758		T13	219
auto[0]	auto[InvalidSt]	10786066	1			T11	4947		T13	442		T14	4349
auto[1]	auto[ResetSt]	175	1			T3	2		T57	5		T58	3
auto[1]	auto[IdleSt]	124	1			T3	4		T57	4		T60	4
auto[1]	auto[ClkMuxSt]	38	1			T57	1		T58	1		T62	2
auto[1]	auto[CntIncrSt]	52	1			T58	2		T59	2		T60	1
auto[1]	auto[CntProgSt]	687	1			T3	11		T57	5		T58	4
auto[1]	auto[TransCheckSt]	87	1			T3	4		T57	6		T58	7
auto[1]	auto[TokenHashSt]	451	1			T3	17		T57	9		T46	1
auto[1]	auto[FlashRmaSt]	68	1			T3	1		T59	2		T190	1
auto[1]	auto[TokenCheck0St]	17	1			T3	2		T59	1		T62	1
auto[1]	auto[TokenCheck1St]	94	1			T3	2		T58	5		T60	1
auto[1]	auto[TransProgSt]	483	1			T3	7		T57	3		T58	7
auto[1]	auto[PostTransSt]	2311	1			T3	9		T16	11		T41	6
auto[1]	auto[ScrapSt]	51	1			T3	2		T57	1		T58	1
auto[1]	auto[EscalateSt]	1289208	1			T3	11090		T11	2548		T13	196
auto[1]	auto[InvalidSt]	6441	1			T11	26		T13	2		T14	29

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	6921198	1			T1	124		T2	94		T3	7641
auto[0]	auto[IdleSt]	21446065	1			T1	1062		T2	50		T3	6422
auto[0]	auto[ClkMuxSt]	33864	1			T3	74		T4	15		T5	11
auto[0]	auto[CntIncrSt]	33615	1			T3	74		T4	15		T5	11
auto[0]	auto[CntProgSt]	1570494	1			T3	131		T4	2006		T5	22
auto[0]	auto[TransCheckSt]	26319	1			T3	55		T4	15		T5	11
auto[0]	auto[TokenHashSt]	39893332	1			T3	6031		T4	160		T5	538
auto[0]	auto[FlashRmaSt]	27118	1			T3	57		T4	19		T5	11
auto[0]	auto[TokenCheck0St]	12040	1			T3	30		T4	15		T5	11
auto[0]	auto[TokenCheck1St]	8784	1			T3	27		T4	15		T5	11
auto[0]	auto[TransProgSt]	380313	1			T3	43		T4	2482		T5	22
auto[0]	auto[PostTransSt]	12682823	1			T2	946		T3	19		T4	706
auto[0]	auto[ScrapSt]	247760	1			T3	4		T4	34		T5	311
auto[0]	auto[EscalateSt]	4896578	1			T3	5154		T11	4386		T13	415
auto[0]	auto[InvalidSt]	10786188	1			T11	4933		T13	444		T14	4348
auto[1]	auto[ResetSt]	174	1			T3	4		T57	4		T58	4
auto[1]	auto[IdleSt]	109	1			T3	3		T57	6		T60	1
auto[1]	auto[ClkMuxSt]	36	1			T3	1		T57	1		T60	1
auto[1]	auto[CntIncrSt]	48	1			T58	2		T59	1		T60	2
auto[1]	auto[CntProgSt]	651	1			T3	9		T57	4		T58	3
auto[1]	auto[TransCheckSt]	89	1			T3	5		T57	6		T58	7
auto[1]	auto[TokenHashSt]	460	1			T3	15		T57	6		T58	25
auto[1]	auto[FlashRmaSt]	66	1			T57	1		T58	3		T59	1
auto[1]	auto[TokenCheck0St]	9	1			T59	1		T62	1		T190	1
auto[1]	auto[TokenCheck1St]	85	1			T3	1		T58	4		T59	1
auto[1]	auto[TransProgSt]	467	1			T3	5		T57	6		T58	8
auto[1]	auto[PostTransSt]	2362	1			T3	13		T16	8		T41	5
auto[1]	auto[ScrapSt]	41	1			T3	2		T57	2		T59	1
auto[1]	auto[EscalateSt]	1267158	1			T3	10682		T11	3920		T14	2940
auto[1]	auto[InvalidSt]	6319	1			T11	40		T14	30		T15	4