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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.81 97.89 95.50 93.31 97.67 98.55 98.26 96.47


Total test records in report: 994
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T813 /workspace/coverage/default/19.lc_ctrl_errors.1023639257 Jun 02 01:25:27 PM PDT 24 Jun 02 01:25:40 PM PDT 24 245643063 ps
T814 /workspace/coverage/default/16.lc_ctrl_sec_token_digest.700373753 Jun 02 01:25:21 PM PDT 24 Jun 02 01:25:34 PM PDT 24 2221385269 ps
T815 /workspace/coverage/default/15.lc_ctrl_sec_token_digest.2659539458 Jun 02 01:25:12 PM PDT 24 Jun 02 01:25:32 PM PDT 24 1738341988 ps
T816 /workspace/coverage/default/1.lc_ctrl_jtag_regwen_during_op.801909985 Jun 02 01:23:55 PM PDT 24 Jun 02 01:24:27 PM PDT 24 1041256579 ps
T817 /workspace/coverage/default/6.lc_ctrl_state_failure.2836674861 Jun 02 01:24:22 PM PDT 24 Jun 02 01:24:45 PM PDT 24 479259102 ps
T818 /workspace/coverage/default/9.lc_ctrl_sec_token_mux.2586307773 Jun 02 01:24:42 PM PDT 24 Jun 02 01:24:53 PM PDT 24 1585766758 ps
T74 /workspace/coverage/default/28.lc_ctrl_alert_test.3567436407 Jun 02 01:26:04 PM PDT 24 Jun 02 01:26:06 PM PDT 24 45471236 ps
T819 /workspace/coverage/default/23.lc_ctrl_prog_failure.3088037137 Jun 02 01:25:50 PM PDT 24 Jun 02 01:25:54 PM PDT 24 73041664 ps
T820 /workspace/coverage/default/3.lc_ctrl_claim_transition_if.2813338005 Jun 02 01:23:59 PM PDT 24 Jun 02 01:24:01 PM PDT 24 49708675 ps
T87 /workspace/coverage/default/1.lc_ctrl_sec_cm.3488813140 Jun 02 01:23:54 PM PDT 24 Jun 02 01:24:18 PM PDT 24 108369170 ps
T821 /workspace/coverage/default/4.lc_ctrl_errors.3223952109 Jun 02 01:24:07 PM PDT 24 Jun 02 01:24:20 PM PDT 24 247778224 ps
T822 /workspace/coverage/default/14.lc_ctrl_sec_token_digest.1683465511 Jun 02 01:25:23 PM PDT 24 Jun 02 01:25:35 PM PDT 24 2147707647 ps
T823 /workspace/coverage/default/0.lc_ctrl_errors.4274911515 Jun 02 01:23:41 PM PDT 24 Jun 02 01:23:52 PM PDT 24 401231966 ps
T824 /workspace/coverage/default/42.lc_ctrl_sec_mubi.2835689880 Jun 02 01:26:50 PM PDT 24 Jun 02 01:27:10 PM PDT 24 1645541490 ps
T825 /workspace/coverage/default/41.lc_ctrl_jtag_access.297256419 Jun 02 01:26:41 PM PDT 24 Jun 02 01:26:46 PM PDT 24 244482663 ps
T826 /workspace/coverage/default/6.lc_ctrl_jtag_errors.4053759600 Jun 02 01:24:25 PM PDT 24 Jun 02 01:25:14 PM PDT 24 3293938340 ps
T827 /workspace/coverage/default/45.lc_ctrl_jtag_access.923357068 Jun 02 01:26:59 PM PDT 24 Jun 02 01:27:05 PM PDT 24 171569210 ps
T828 /workspace/coverage/default/7.lc_ctrl_jtag_access.4248626538 Jun 02 01:24:29 PM PDT 24 Jun 02 01:24:33 PM PDT 24 1392313319 ps
T829 /workspace/coverage/default/22.lc_ctrl_errors.4118542527 Jun 02 01:25:40 PM PDT 24 Jun 02 01:25:50 PM PDT 24 719752624 ps
T61 /workspace/coverage/default/2.lc_ctrl_sec_cm.3998265881 Jun 02 01:24:00 PM PDT 24 Jun 02 01:24:25 PM PDT 24 528689742 ps
T830 /workspace/coverage/default/30.lc_ctrl_state_failure.2207118445 Jun 02 01:26:07 PM PDT 24 Jun 02 01:26:38 PM PDT 24 305149028 ps
T831 /workspace/coverage/default/34.lc_ctrl_sec_token_digest.4166772995 Jun 02 01:26:19 PM PDT 24 Jun 02 01:26:31 PM PDT 24 1174362490 ps
T832 /workspace/coverage/default/7.lc_ctrl_claim_transition_if.1248967331 Jun 02 01:24:30 PM PDT 24 Jun 02 01:24:31 PM PDT 24 36241178 ps
T833 /workspace/coverage/default/43.lc_ctrl_volatile_unlock_smoke.1566396733 Jun 02 01:26:48 PM PDT 24 Jun 02 01:26:50 PM PDT 24 12324702 ps
T834 /workspace/coverage/default/13.lc_ctrl_prog_failure.4063209573 Jun 02 01:25:07 PM PDT 24 Jun 02 01:25:12 PM PDT 24 63138965 ps
T835 /workspace/coverage/default/2.lc_ctrl_sec_mubi.3645682279 Jun 02 01:23:53 PM PDT 24 Jun 02 01:24:04 PM PDT 24 537604388 ps
T836 /workspace/coverage/default/28.lc_ctrl_security_escalation.1248842425 Jun 02 01:26:01 PM PDT 24 Jun 02 01:26:10 PM PDT 24 183390529 ps
T837 /workspace/coverage/default/19.lc_ctrl_stress_all.1636106836 Jun 02 01:25:32 PM PDT 24 Jun 02 01:26:59 PM PDT 24 1880503550 ps
T838 /workspace/coverage/default/14.lc_ctrl_state_failure.2373838363 Jun 02 01:25:05 PM PDT 24 Jun 02 01:25:30 PM PDT 24 225986538 ps
T839 /workspace/coverage/default/4.lc_ctrl_regwen_during_op.725526565 Jun 02 01:24:07 PM PDT 24 Jun 02 01:24:26 PM PDT 24 297229413 ps
T840 /workspace/coverage/default/0.lc_ctrl_alert_test.3331868441 Jun 02 01:23:47 PM PDT 24 Jun 02 01:23:48 PM PDT 24 21210519 ps
T841 /workspace/coverage/default/10.lc_ctrl_sec_token_mux.1247965157 Jun 02 01:24:50 PM PDT 24 Jun 02 01:25:05 PM PDT 24 1658135014 ps
T103 /workspace/coverage/default/2.lc_ctrl_stress_all.2282723265 Jun 02 01:24:05 PM PDT 24 Jun 02 01:30:49 PM PDT 24 27407186190 ps
T92 /workspace/coverage/default/3.lc_ctrl_sec_cm.3949295880 Jun 02 01:24:00 PM PDT 24 Jun 02 01:24:26 PM PDT 24 113497425 ps
T842 /workspace/coverage/default/45.lc_ctrl_security_escalation.302924453 Jun 02 01:26:54 PM PDT 24 Jun 02 01:27:01 PM PDT 24 820285541 ps
T843 /workspace/coverage/default/10.lc_ctrl_jtag_prog_failure.2518542068 Jun 02 01:24:54 PM PDT 24 Jun 02 01:25:01 PM PDT 24 2448469408 ps
T844 /workspace/coverage/default/21.lc_ctrl_security_escalation.199766374 Jun 02 01:25:40 PM PDT 24 Jun 02 01:25:50 PM PDT 24 227488763 ps
T845 /workspace/coverage/default/29.lc_ctrl_sec_mubi.3843074091 Jun 02 01:26:05 PM PDT 24 Jun 02 01:26:22 PM PDT 24 487288979 ps
T846 /workspace/coverage/default/29.lc_ctrl_jtag_access.2154597708 Jun 02 01:26:05 PM PDT 24 Jun 02 01:26:11 PM PDT 24 714016777 ps
T847 /workspace/coverage/default/36.lc_ctrl_stress_all.427917424 Jun 02 01:26:26 PM PDT 24 Jun 02 01:29:01 PM PDT 24 12335732298 ps
T848 /workspace/coverage/default/7.lc_ctrl_jtag_smoke.4290824611 Jun 02 01:24:29 PM PDT 24 Jun 02 01:24:35 PM PDT 24 612968642 ps
T849 /workspace/coverage/default/26.lc_ctrl_alert_test.1924029146 Jun 02 01:25:58 PM PDT 24 Jun 02 01:25:59 PM PDT 24 21823368 ps
T850 /workspace/coverage/default/8.lc_ctrl_sec_token_mux.2534876507 Jun 02 01:24:36 PM PDT 24 Jun 02 01:24:46 PM PDT 24 409270487 ps
T851 /workspace/coverage/default/37.lc_ctrl_jtag_access.2035418053 Jun 02 01:26:34 PM PDT 24 Jun 02 01:26:43 PM PDT 24 381025448 ps
T852 /workspace/coverage/default/12.lc_ctrl_jtag_errors.939282517 Jun 02 01:25:07 PM PDT 24 Jun 02 01:25:53 PM PDT 24 6515217830 ps
T853 /workspace/coverage/default/30.lc_ctrl_smoke.2171361272 Jun 02 01:26:07 PM PDT 24 Jun 02 01:26:10 PM PDT 24 51336622 ps
T854 /workspace/coverage/default/29.lc_ctrl_sec_token_digest.2073550737 Jun 02 01:26:05 PM PDT 24 Jun 02 01:26:17 PM PDT 24 2530337819 ps
T855 /workspace/coverage/default/9.lc_ctrl_security_escalation.756031917 Jun 02 01:24:39 PM PDT 24 Jun 02 01:24:49 PM PDT 24 1525026531 ps
T856 /workspace/coverage/default/38.lc_ctrl_alert_test.2058195049 Jun 02 01:26:34 PM PDT 24 Jun 02 01:26:35 PM PDT 24 56611441 ps
T857 /workspace/coverage/default/12.lc_ctrl_smoke.1308592292 Jun 02 01:24:57 PM PDT 24 Jun 02 01:24:59 PM PDT 24 41117325 ps
T858 /workspace/coverage/default/0.lc_ctrl_jtag_priority.1712865385 Jun 02 01:23:42 PM PDT 24 Jun 02 01:23:50 PM PDT 24 537472207 ps
T104 /workspace/coverage/default/27.lc_ctrl_stress_all.1690275186 Jun 02 01:26:01 PM PDT 24 Jun 02 01:27:11 PM PDT 24 1861714086 ps
T75 /workspace/coverage/default/1.lc_ctrl_jtag_smoke.642689024 Jun 02 01:23:47 PM PDT 24 Jun 02 01:23:55 PM PDT 24 602534065 ps
T859 /workspace/coverage/default/33.lc_ctrl_sec_mubi.2648858973 Jun 02 01:26:18 PM PDT 24 Jun 02 01:26:31 PM PDT 24 353900531 ps
T860 /workspace/coverage/default/6.lc_ctrl_sec_token_digest.3899417755 Jun 02 01:24:23 PM PDT 24 Jun 02 01:24:35 PM PDT 24 2247977186 ps
T861 /workspace/coverage/default/18.lc_ctrl_jtag_smoke.895942276 Jun 02 01:25:24 PM PDT 24 Jun 02 01:25:29 PM PDT 24 594903042 ps
T862 /workspace/coverage/default/37.lc_ctrl_state_failure.2111169874 Jun 02 01:26:26 PM PDT 24 Jun 02 01:26:57 PM PDT 24 1209422119 ps
T863 /workspace/coverage/default/18.lc_ctrl_state_post_trans.1190187223 Jun 02 01:25:25 PM PDT 24 Jun 02 01:25:32 PM PDT 24 85291608 ps
T864 /workspace/coverage/default/14.lc_ctrl_stress_all.326977079 Jun 02 01:25:12 PM PDT 24 Jun 02 01:28:56 PM PDT 24 41119852320 ps
T111 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.3613037549 Jun 02 01:10:54 PM PDT 24 Jun 02 01:10:56 PM PDT 24 19433101 ps
T140 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.2791480687 Jun 02 01:10:31 PM PDT 24 Jun 02 01:10:33 PM PDT 24 77659132 ps
T114 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.2374039574 Jun 02 01:10:34 PM PDT 24 Jun 02 01:10:40 PM PDT 24 440191074 ps
T141 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.1498010452 Jun 02 01:10:04 PM PDT 24 Jun 02 01:10:06 PM PDT 24 25469708 ps
T115 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.3429589894 Jun 02 01:10:12 PM PDT 24 Jun 02 01:10:13 PM PDT 24 40192525 ps
T134 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.2690823463 Jun 02 01:10:53 PM PDT 24 Jun 02 01:10:54 PM PDT 24 78898269 ps
T112 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.3665696399 Jun 02 01:10:59 PM PDT 24 Jun 02 01:11:00 PM PDT 24 66476406 ps
T168 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.1652969528 Jun 02 01:10:08 PM PDT 24 Jun 02 01:10:10 PM PDT 24 188201919 ps
T143 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.2643893825 Jun 02 01:10:31 PM PDT 24 Jun 02 01:10:33 PM PDT 24 20758910 ps
T105 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.1368411254 Jun 02 01:10:21 PM PDT 24 Jun 02 01:10:24 PM PDT 24 54302736 ps
T138 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.859818322 Jun 02 01:10:17 PM PDT 24 Jun 02 01:10:22 PM PDT 24 1772588842 ps
T182 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.561785206 Jun 02 01:10:25 PM PDT 24 Jun 02 01:10:27 PM PDT 24 55401017 ps
T139 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.4004132592 Jun 02 01:10:19 PM PDT 24 Jun 02 01:10:22 PM PDT 24 46939657 ps
T106 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.3443329523 Jun 02 01:11:01 PM PDT 24 Jun 02 01:11:04 PM PDT 24 991151575 ps
T169 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.2743019535 Jun 02 01:10:04 PM PDT 24 Jun 02 01:10:05 PM PDT 24 30974466 ps
T170 /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.1700987526 Jun 02 01:10:06 PM PDT 24 Jun 02 01:10:07 PM PDT 24 26315788 ps
T144 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3839077488 Jun 02 01:10:13 PM PDT 24 Jun 02 01:10:16 PM PDT 24 67926744 ps
T107 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.243975400 Jun 02 01:11:07 PM PDT 24 Jun 02 01:11:12 PM PDT 24 391324752 ps
T865 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.4270003791 Jun 02 01:10:21 PM PDT 24 Jun 02 01:10:22 PM PDT 24 27551578 ps
T109 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.1480116815 Jun 02 01:10:52 PM PDT 24 Jun 02 01:10:54 PM PDT 24 22015126 ps
T866 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.2138423944 Jun 02 01:10:11 PM PDT 24 Jun 02 01:10:13 PM PDT 24 38810869 ps
T163 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.620409043 Jun 02 01:11:00 PM PDT 24 Jun 02 01:11:02 PM PDT 24 111247386 ps
T108 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.1839545903 Jun 02 01:11:02 PM PDT 24 Jun 02 01:11:04 PM PDT 24 47443064 ps
T171 /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.1842579545 Jun 02 01:11:08 PM PDT 24 Jun 02 01:11:10 PM PDT 24 21151945 ps
T867 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.2854580266 Jun 02 01:10:45 PM PDT 24 Jun 02 01:11:00 PM PDT 24 2829169960 ps
T135 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.2015926175 Jun 02 01:10:36 PM PDT 24 Jun 02 01:10:38 PM PDT 24 259046303 ps
T172 /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.672813001 Jun 02 01:11:01 PM PDT 24 Jun 02 01:11:03 PM PDT 24 19637523 ps
T127 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.1758219075 Jun 02 01:10:54 PM PDT 24 Jun 02 01:10:57 PM PDT 24 250259658 ps
T868 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.3770469331 Jun 02 01:11:06 PM PDT 24 Jun 02 01:11:07 PM PDT 24 69707832 ps
T116 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.3858322306 Jun 02 01:11:02 PM PDT 24 Jun 02 01:11:05 PM PDT 24 108501874 ps
T110 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.2379437379 Jun 02 01:10:32 PM PDT 24 Jun 02 01:10:36 PM PDT 24 514434307 ps
T869 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.3928400282 Jun 02 01:10:13 PM PDT 24 Jun 02 01:10:14 PM PDT 24 145592139 ps
T870 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.1820890864 Jun 02 01:10:27 PM PDT 24 Jun 02 01:10:28 PM PDT 24 19359926 ps
T119 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.1534558977 Jun 02 01:10:36 PM PDT 24 Jun 02 01:10:39 PM PDT 24 129874687 ps
T871 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.205041955 Jun 02 01:10:20 PM PDT 24 Jun 02 01:10:22 PM PDT 24 98599465 ps
T173 /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.2992760271 Jun 02 01:11:09 PM PDT 24 Jun 02 01:11:11 PM PDT 24 17272553 ps
T872 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.2163096075 Jun 02 01:10:17 PM PDT 24 Jun 02 01:10:18 PM PDT 24 17412951 ps
T873 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.1365816254 Jun 02 01:10:37 PM PDT 24 Jun 02 01:10:49 PM PDT 24 2303390636 ps
T874 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.1940168716 Jun 02 01:10:11 PM PDT 24 Jun 02 01:10:14 PM PDT 24 191561303 ps
T136 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.1887342527 Jun 02 01:10:12 PM PDT 24 Jun 02 01:10:14 PM PDT 24 128986558 ps
T124 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.2569672165 Jun 02 01:10:05 PM PDT 24 Jun 02 01:10:08 PM PDT 24 229799397 ps
T174 /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.2559613746 Jun 02 01:10:34 PM PDT 24 Jun 02 01:10:35 PM PDT 24 133346295 ps
T118 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.1626070158 Jun 02 01:11:00 PM PDT 24 Jun 02 01:11:02 PM PDT 24 125977235 ps
T875 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.2426060447 Jun 02 01:10:11 PM PDT 24 Jun 02 01:10:12 PM PDT 24 40596178 ps
T145 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3888501246 Jun 02 01:10:42 PM PDT 24 Jun 02 01:10:45 PM PDT 24 345693272 ps
T113 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.3278836081 Jun 02 01:11:08 PM PDT 24 Jun 02 01:11:11 PM PDT 24 73932534 ps
T129 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.3314993330 Jun 02 01:10:18 PM PDT 24 Jun 02 01:10:21 PM PDT 24 118769868 ps
T121 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.4104565957 Jun 02 01:10:10 PM PDT 24 Jun 02 01:10:12 PM PDT 24 21248658 ps
T120 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.3259179663 Jun 02 01:10:53 PM PDT 24 Jun 02 01:10:56 PM PDT 24 32789163 ps
T122 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.2114678962 Jun 02 01:10:38 PM PDT 24 Jun 02 01:10:42 PM PDT 24 211679151 ps
T175 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.3698915066 Jun 02 01:10:26 PM PDT 24 Jun 02 01:10:28 PM PDT 24 22039534 ps
T876 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.4274926234 Jun 02 01:11:06 PM PDT 24 Jun 02 01:11:11 PM PDT 24 170660084 ps
T133 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.710510990 Jun 02 01:11:07 PM PDT 24 Jun 02 01:11:11 PM PDT 24 121002987 ps
T176 /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.3205033101 Jun 02 01:10:11 PM PDT 24 Jun 02 01:10:13 PM PDT 24 59350231 ps
T877 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.2472937853 Jun 02 01:11:08 PM PDT 24 Jun 02 01:11:09 PM PDT 24 60910586 ps
T878 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.3956144713 Jun 02 01:10:25 PM PDT 24 Jun 02 01:10:26 PM PDT 24 29965365 ps
T879 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.938020893 Jun 02 01:10:38 PM PDT 24 Jun 02 01:10:58 PM PDT 24 1804903973 ps
T880 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.3227996242 Jun 02 01:10:51 PM PDT 24 Jun 02 01:10:53 PM PDT 24 13047937 ps
T881 /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.4240330410 Jun 02 01:10:19 PM PDT 24 Jun 02 01:10:21 PM PDT 24 44680447 ps
T882 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.1285400103 Jun 02 01:10:31 PM PDT 24 Jun 02 01:10:33 PM PDT 24 115845385 ps
T883 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.2562106885 Jun 02 01:10:27 PM PDT 24 Jun 02 01:10:30 PM PDT 24 30464566 ps
T884 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.2338224908 Jun 02 01:10:26 PM PDT 24 Jun 02 01:10:34 PM PDT 24 3334839795 ps
T885 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.1898162399 Jun 02 01:10:46 PM PDT 24 Jun 02 01:10:47 PM PDT 24 94100908 ps
T886 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.777442117 Jun 02 01:10:27 PM PDT 24 Jun 02 01:10:29 PM PDT 24 74578545 ps
T887 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.2233868470 Jun 02 01:10:18 PM PDT 24 Jun 02 01:10:19 PM PDT 24 36816518 ps
T888 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.113068611 Jun 02 01:10:32 PM PDT 24 Jun 02 01:10:34 PM PDT 24 158051147 ps
T889 /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.3466034965 Jun 02 01:10:59 PM PDT 24 Jun 02 01:11:02 PM PDT 24 49269260 ps
T137 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3741351061 Jun 02 01:10:27 PM PDT 24 Jun 02 01:10:30 PM PDT 24 232440556 ps
T890 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.2750233227 Jun 02 01:10:58 PM PDT 24 Jun 02 01:11:00 PM PDT 24 39076713 ps
T891 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.254472529 Jun 02 01:11:08 PM PDT 24 Jun 02 01:11:11 PM PDT 24 125856876 ps
T892 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.1045105271 Jun 02 01:10:47 PM PDT 24 Jun 02 01:10:48 PM PDT 24 66064663 ps
T893 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.2715835741 Jun 02 01:10:58 PM PDT 24 Jun 02 01:11:00 PM PDT 24 106167321 ps
T894 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.2651407267 Jun 02 01:10:46 PM PDT 24 Jun 02 01:10:47 PM PDT 24 48370801 ps
T895 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.244589023 Jun 02 01:10:20 PM PDT 24 Jun 02 01:10:22 PM PDT 24 107125609 ps
T896 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.3940677114 Jun 02 01:10:12 PM PDT 24 Jun 02 01:10:14 PM PDT 24 35209922 ps
T897 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.526377843 Jun 02 01:09:58 PM PDT 24 Jun 02 01:10:04 PM PDT 24 837230378 ps
T898 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.1858389224 Jun 02 01:10:39 PM PDT 24 Jun 02 01:10:42 PM PDT 24 48590162 ps
T899 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.1761846805 Jun 02 01:10:17 PM PDT 24 Jun 02 01:10:19 PM PDT 24 142277414 ps
T900 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.711491548 Jun 02 01:09:57 PM PDT 24 Jun 02 01:10:00 PM PDT 24 258271690 ps
T901 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.4253152576 Jun 02 01:10:24 PM PDT 24 Jun 02 01:10:26 PM PDT 24 108919228 ps
T902 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.939522257 Jun 02 01:10:11 PM PDT 24 Jun 02 01:10:13 PM PDT 24 263112206 ps
T903 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.3740578256 Jun 02 01:10:19 PM PDT 24 Jun 02 01:10:21 PM PDT 24 34718341 ps
T904 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.814732207 Jun 02 01:10:54 PM PDT 24 Jun 02 01:10:56 PM PDT 24 238374924 ps
T905 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.1709990941 Jun 02 01:10:14 PM PDT 24 Jun 02 01:10:17 PM PDT 24 393025252 ps
T906 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.1241368324 Jun 02 01:10:31 PM PDT 24 Jun 02 01:10:33 PM PDT 24 58388647 ps
T907 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.4116052952 Jun 02 01:10:36 PM PDT 24 Jun 02 01:10:38 PM PDT 24 79612179 ps
T908 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.1479520406 Jun 02 01:10:06 PM PDT 24 Jun 02 01:10:07 PM PDT 24 17395848 ps
T909 /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.3280758154 Jun 02 01:10:35 PM PDT 24 Jun 02 01:10:36 PM PDT 24 30661234 ps
T910 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3678431902 Jun 02 01:09:56 PM PDT 24 Jun 02 01:09:59 PM PDT 24 74291845 ps
T911 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.1334529654 Jun 02 01:10:59 PM PDT 24 Jun 02 01:11:00 PM PDT 24 21088989 ps
T912 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.1046241740 Jun 02 01:10:53 PM PDT 24 Jun 02 01:10:57 PM PDT 24 49039172 ps
T913 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.2587623350 Jun 02 01:10:47 PM PDT 24 Jun 02 01:10:56 PM PDT 24 352878847 ps
T914 /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.558728233 Jun 02 01:11:09 PM PDT 24 Jun 02 01:11:10 PM PDT 24 85005435 ps
T915 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.2816134782 Jun 02 01:10:50 PM PDT 24 Jun 02 01:10:56 PM PDT 24 207063266 ps
T916 /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.314341033 Jun 02 01:10:25 PM PDT 24 Jun 02 01:10:27 PM PDT 24 96007313 ps
T917 /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.353124566 Jun 02 01:10:46 PM PDT 24 Jun 02 01:10:48 PM PDT 24 23481224 ps
T918 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.893745291 Jun 02 01:10:12 PM PDT 24 Jun 02 01:10:17 PM PDT 24 101139259 ps
T128 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.2972804575 Jun 02 01:10:58 PM PDT 24 Jun 02 01:11:01 PM PDT 24 245913265 ps
T919 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.3785051252 Jun 02 01:10:20 PM PDT 24 Jun 02 01:10:21 PM PDT 24 52822298 ps
T920 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.2604742835 Jun 02 01:10:12 PM PDT 24 Jun 02 01:10:14 PM PDT 24 62376716 ps
T921 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.3754879137 Jun 02 01:10:54 PM PDT 24 Jun 02 01:10:56 PM PDT 24 211527755 ps
T922 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3110008093 Jun 02 01:10:12 PM PDT 24 Jun 02 01:10:15 PM PDT 24 152830456 ps
T923 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.3511995807 Jun 02 01:10:53 PM PDT 24 Jun 02 01:10:55 PM PDT 24 42347520 ps
T924 /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.4126366877 Jun 02 01:10:54 PM PDT 24 Jun 02 01:10:56 PM PDT 24 19872984 ps
T132 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.96892779 Jun 02 01:10:45 PM PDT 24 Jun 02 01:10:49 PM PDT 24 91200208 ps
T925 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.2715452636 Jun 02 01:11:08 PM PDT 24 Jun 02 01:11:11 PM PDT 24 24850323 ps
T926 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3169872431 Jun 02 01:10:19 PM PDT 24 Jun 02 01:10:22 PM PDT 24 616271590 ps
T927 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.759220223 Jun 02 01:10:45 PM PDT 24 Jun 02 01:10:47 PM PDT 24 97752316 ps
T928 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.265891162 Jun 02 01:10:26 PM PDT 24 Jun 02 01:10:43 PM PDT 24 699475352 ps
T929 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.1374387165 Jun 02 01:10:52 PM PDT 24 Jun 02 01:11:02 PM PDT 24 372422414 ps
T930 /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.1338937033 Jun 02 01:10:28 PM PDT 24 Jun 02 01:10:30 PM PDT 24 64163065 ps
T931 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.493709442 Jun 02 01:10:53 PM PDT 24 Jun 02 01:10:55 PM PDT 24 26353382 ps
T125 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.731994600 Jun 02 01:10:25 PM PDT 24 Jun 02 01:10:28 PM PDT 24 182691899 ps
T932 /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.461018991 Jun 02 01:10:57 PM PDT 24 Jun 02 01:10:59 PM PDT 24 31234761 ps
T933 /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.551744796 Jun 02 01:10:51 PM PDT 24 Jun 02 01:10:53 PM PDT 24 16564084 ps
T934 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.139912477 Jun 02 01:10:31 PM PDT 24 Jun 02 01:10:34 PM PDT 24 85123411 ps
T935 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.1391108764 Jun 02 01:11:07 PM PDT 24 Jun 02 01:11:09 PM PDT 24 87771853 ps
T936 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.474972446 Jun 02 01:10:31 PM PDT 24 Jun 02 01:10:32 PM PDT 24 15690669 ps
T937 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.1449308265 Jun 02 01:10:38 PM PDT 24 Jun 02 01:10:50 PM PDT 24 731559154 ps
T938 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.4242817448 Jun 02 01:10:50 PM PDT 24 Jun 02 01:11:09 PM PDT 24 1098870549 ps
T939 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.2758566824 Jun 02 01:11:00 PM PDT 24 Jun 02 01:11:04 PM PDT 24 193962983 ps
T940 /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.3751002259 Jun 02 01:10:51 PM PDT 24 Jun 02 01:10:53 PM PDT 24 46779892 ps
T941 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.2250845458 Jun 02 01:10:25 PM PDT 24 Jun 02 01:10:27 PM PDT 24 33275109 ps
T942 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.889537211 Jun 02 01:11:08 PM PDT 24 Jun 02 01:11:10 PM PDT 24 62120006 ps
T943 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.539541501 Jun 02 01:10:04 PM PDT 24 Jun 02 01:10:05 PM PDT 24 19428546 ps
T944 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.3519397794 Jun 02 01:10:47 PM PDT 24 Jun 02 01:10:50 PM PDT 24 117614893 ps
T945 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.115381627 Jun 02 01:11:08 PM PDT 24 Jun 02 01:11:11 PM PDT 24 200979766 ps
T946 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.137744257 Jun 02 01:10:46 PM PDT 24 Jun 02 01:10:50 PM PDT 24 111218861 ps
T947 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.2283563497 Jun 02 01:10:42 PM PDT 24 Jun 02 01:11:26 PM PDT 24 2069197263 ps
T948 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4221667748 Jun 02 01:10:51 PM PDT 24 Jun 02 01:10:53 PM PDT 24 49530958 ps
T164 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.3659360672 Jun 02 01:10:19 PM PDT 24 Jun 02 01:10:21 PM PDT 24 56397526 ps
T117 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.4215108641 Jun 02 01:10:13 PM PDT 24 Jun 02 01:10:16 PM PDT 24 634596750 ps
T949 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.3491850383 Jun 02 01:11:00 PM PDT 24 Jun 02 01:11:02 PM PDT 24 16614333 ps
T950 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.1908975165 Jun 02 01:10:39 PM PDT 24 Jun 02 01:10:41 PM PDT 24 99312548 ps
T951 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.2996903748 Jun 02 01:10:17 PM PDT 24 Jun 02 01:10:51 PM PDT 24 5922805708 ps
T952 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.3453582746 Jun 02 01:10:26 PM PDT 24 Jun 02 01:10:27 PM PDT 24 118792956 ps
T126 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.2350559663 Jun 02 01:10:11 PM PDT 24 Jun 02 01:10:14 PM PDT 24 256376843 ps
T953 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.101998220 Jun 02 01:10:53 PM PDT 24 Jun 02 01:10:55 PM PDT 24 22351161 ps
T954 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.1814306056 Jun 02 01:10:08 PM PDT 24 Jun 02 01:10:10 PM PDT 24 175123936 ps
T955 /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.2705002901 Jun 02 01:10:48 PM PDT 24 Jun 02 01:10:49 PM PDT 24 16131069 ps
T956 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.848134788 Jun 02 01:09:57 PM PDT 24 Jun 02 01:10:13 PM PDT 24 1646999413 ps
T123 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.528945294 Jun 02 01:10:53 PM PDT 24 Jun 02 01:10:57 PM PDT 24 923788726 ps
T957 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.3340930333 Jun 02 01:10:12 PM PDT 24 Jun 02 01:10:17 PM PDT 24 569367129 ps
T958 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.3827176562 Jun 02 01:10:44 PM PDT 24 Jun 02 01:10:46 PM PDT 24 27185914 ps
T959 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.3478720656 Jun 02 01:10:04 PM PDT 24 Jun 02 01:10:07 PM PDT 24 125796139 ps
T960 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.3312467687 Jun 02 01:10:33 PM PDT 24 Jun 02 01:10:35 PM PDT 24 280606008 ps
T130 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.2499258492 Jun 02 01:10:53 PM PDT 24 Jun 02 01:10:58 PM PDT 24 515429134 ps
T961 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.1795289927 Jun 02 01:10:38 PM PDT 24 Jun 02 01:10:40 PM PDT 24 122360454 ps
T962 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.4236360554 Jun 02 01:10:33 PM PDT 24 Jun 02 01:10:34 PM PDT 24 31050523 ps
T165 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.4008059309 Jun 02 01:10:32 PM PDT 24 Jun 02 01:10:33 PM PDT 24 38580966 ps
T963 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.3767403349 Jun 02 01:10:47 PM PDT 24 Jun 02 01:10:51 PM PDT 24 122188561 ps
T964 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.3854442583 Jun 02 01:10:26 PM PDT 24 Jun 02 01:10:29 PM PDT 24 25979281 ps
T965 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.2485428578 Jun 02 01:10:06 PM PDT 24 Jun 02 01:10:07 PM PDT 24 37404400 ps
T966 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3579355121 Jun 02 01:10:32 PM PDT 24 Jun 02 01:10:35 PM PDT 24 526575891 ps
T967 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.3679597016 Jun 02 01:10:27 PM PDT 24 Jun 02 01:10:29 PM PDT 24 65130869 ps
T968 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.621645503 Jun 02 01:10:13 PM PDT 24 Jun 02 01:10:23 PM PDT 24 1710062173 ps
T969 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.3634502536 Jun 02 01:11:00 PM PDT 24 Jun 02 01:11:03 PM PDT 24 303316852 ps
T131 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.3750699719 Jun 02 01:10:52 PM PDT 24 Jun 02 01:10:55 PM PDT 24 120617236 ps
T970 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.131319378 Jun 02 01:10:39 PM PDT 24 Jun 02 01:10:40 PM PDT 24 15449501 ps
T971 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.3048600077 Jun 02 01:10:12 PM PDT 24 Jun 02 01:10:26 PM PDT 24 1920353570 ps
T166 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.833962903 Jun 02 01:10:12 PM PDT 24 Jun 02 01:10:13 PM PDT 24 41715299 ps
T972 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.90318245 Jun 02 01:10:10 PM PDT 24 Jun 02 01:10:12 PM PDT 24 23095653 ps
T973 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.2505847758 Jun 02 01:10:54 PM PDT 24 Jun 02 01:10:56 PM PDT 24 186322863 ps
T974 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.2579128242 Jun 02 01:11:01 PM PDT 24 Jun 02 01:11:03 PM PDT 24 32511610 ps
T975 /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.977993074 Jun 02 01:11:06 PM PDT 24 Jun 02 01:11:08 PM PDT 24 95256385 ps
T976 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.1567399483 Jun 02 01:10:10 PM PDT 24 Jun 02 01:10:26 PM PDT 24 3039315428 ps
T977 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.2846015339 Jun 02 01:11:07 PM PDT 24 Jun 02 01:11:08 PM PDT 24 58962961 ps
T978 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.3871151670 Jun 02 01:10:33 PM PDT 24 Jun 02 01:10:35 PM PDT 24 98380845 ps
T979 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.1554772497 Jun 02 01:10:26 PM PDT 24 Jun 02 01:10:28 PM PDT 24 117932290 ps
T980 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.1410279566 Jun 02 01:10:33 PM PDT 24 Jun 02 01:10:46 PM PDT 24 1238548393 ps
T981 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.2274335790 Jun 02 01:10:31 PM PDT 24 Jun 02 01:10:35 PM PDT 24 100284792 ps
T167 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.1059685744 Jun 02 01:11:09 PM PDT 24 Jun 02 01:11:10 PM PDT 24 34397645 ps
T982 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.164526223 Jun 02 01:10:34 PM PDT 24 Jun 02 01:10:36 PM PDT 24 728816821 ps
T983 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.3586460480 Jun 02 01:10:59 PM PDT 24 Jun 02 01:11:04 PM PDT 24 118446678 ps
T984 /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.452265815 Jun 02 01:10:50 PM PDT 24 Jun 02 01:10:52 PM PDT 24 153035332 ps
T985 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.2650005921 Jun 02 01:11:08 PM PDT 24 Jun 02 01:11:11 PM PDT 24 658038166 ps
T986 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.562386474 Jun 02 01:10:12 PM PDT 24 Jun 02 01:10:14 PM PDT 24 159310525 ps
T987 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.4234074242 Jun 02 01:10:31 PM PDT 24 Jun 02 01:10:33 PM PDT 24 240497051 ps
T988 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.59172136 Jun 02 01:10:38 PM PDT 24 Jun 02 01:10:40 PM PDT 24 65809872 ps
T989 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.3290689521 Jun 02 01:10:59 PM PDT 24 Jun 02 01:11:00 PM PDT 24 34517888 ps
T990 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.629095764 Jun 02 01:10:18 PM PDT 24 Jun 02 01:10:19 PM PDT 24 38456015 ps
T991 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.1227276979 Jun 02 01:10:53 PM PDT 24 Jun 02 01:10:55 PM PDT 24 42969169 ps
T992 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.2189137658 Jun 02 01:10:01 PM PDT 24 Jun 02 01:10:03 PM PDT 24 304320251 ps
T993 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.3291942377 Jun 02 01:10:12 PM PDT 24 Jun 02 01:10:14 PM PDT 24 379833382 ps
T994 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2498911778 Jun 02 01:10:46 PM PDT 24 Jun 02 01:10:51 PM PDT 24 147558247 ps

Test location /workspace/coverage/default/27.lc_ctrl_security_escalation.534135101
Short name T3
Test name
Test status
Simulation time 1042928183 ps
CPU time 10.7 seconds
Started Jun 02 01:25:59 PM PDT 24
Finished Jun 02 01:26:10 PM PDT 24
Peak memory 218088 kb
Host smart-940e7bc8-395b-4c6d-8b6e-5750527f3dd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534135101 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_security_escalation.534135101
Directory /workspace/27.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all.4064613228
Short name T21
Test name
Test status
Simulation time 15146964067 ps
CPU time 254.24 seconds
Started Jun 02 01:24:41 PM PDT 24
Finished Jun 02 01:28:56 PM PDT 24
Peak memory 267420 kb
Host smart-11163467-353e-40f6-b744-3cbbedc5a685
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064613228 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.lc_ctrl_stress_all.4064613228
Directory /workspace/8.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_mubi.1732887279
Short name T16
Test name
Test status
Simulation time 502865871 ps
CPU time 10.7 seconds
Started Jun 02 01:26:55 PM PDT 24
Finished Jun 02 01:27:06 PM PDT 24
Peak memory 218956 kb
Host smart-7dfc568b-2fea-4072-ba1e-927e5ed575b6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732887279 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_mubi.1732887279
Directory /workspace/44.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/14.lc_ctrl_stress_all_with_rand_reset.1557557400
Short name T53
Test name
Test status
Simulation time 160219956456 ps
CPU time 927.87 seconds
Started Jun 02 01:25:15 PM PDT 24
Finished Jun 02 01:40:43 PM PDT 24
Peak memory 496880 kb
Host smart-4bc14234-c420-464a-9c9d-f0f22a0cf5d3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1557557400 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_stress_all_with_rand_reset.1557557400
Directory /workspace/14.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.243975400
Short name T107
Test name
Test status
Simulation time 391324752 ps
CPU time 5.09 seconds
Started Jun 02 01:11:07 PM PDT 24
Finished Jun 02 01:11:12 PM PDT 24
Peak memory 218132 kb
Host smart-5e39d0f5-e758-4a69-bfb2-8d68e4946af8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243975400 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_errors.243975400
Directory /workspace/19.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_volatile_unlock_smoke.1983561168
Short name T2
Test name
Test status
Simulation time 13007946 ps
CPU time 0.93 seconds
Started Jun 02 01:25:12 PM PDT 24
Finished Jun 02 01:25:13 PM PDT 24
Peak memory 208772 kb
Host smart-ef1b92ea-ba9a-4147-a1dc-2b34e8ed659b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983561168 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_c
trl_volatile_unlock_smoke.1983561168
Directory /workspace/15.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_mux.3667664081
Short name T12
Test name
Test status
Simulation time 428378354 ps
CPU time 15.31 seconds
Started Jun 02 01:25:26 PM PDT 24
Finished Jun 02 01:25:42 PM PDT 24
Peak memory 218076 kb
Host smart-c1187421-f91c-4506-b245-852a39aa154a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667664081 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_mux.
3667664081
Directory /workspace/18.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all_with_rand_reset.1792629791
Short name T63
Test name
Test status
Simulation time 442151919074 ps
CPU time 550.59 seconds
Started Jun 02 01:26:34 PM PDT 24
Finished Jun 02 01:35:45 PM PDT 24
Peak memory 332904 kb
Host smart-2a4568b9-ec7d-471d-a9ac-024f66fe8d55
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1792629791 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_stress_all_with_rand_reset.1792629791
Directory /workspace/39.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_cm.3998265881
Short name T61
Test name
Test status
Simulation time 528689742 ps
CPU time 24.58 seconds
Started Jun 02 01:24:00 PM PDT 24
Finished Jun 02 01:24:25 PM PDT 24
Peak memory 269008 kb
Host smart-afdd6a9d-4cf2-46b8-83c8-90c046ee2d86
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998265881 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_cm.3998265881
Directory /workspace/2.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/13.lc_ctrl_security_escalation.1706956183
Short name T58
Test name
Test status
Simulation time 277068792 ps
CPU time 11.8 seconds
Started Jun 02 01:25:10 PM PDT 24
Finished Jun 02 01:25:23 PM PDT 24
Peak memory 225628 kb
Host smart-ceab19eb-4a81-4c3b-a918-f55885a34b23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706956183 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_security_escalation.1706956183
Directory /workspace/13.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.1368411254
Short name T105
Test name
Test status
Simulation time 54302736 ps
CPU time 2.54 seconds
Started Jun 02 01:10:21 PM PDT 24
Finished Jun 02 01:10:24 PM PDT 24
Peak memory 218204 kb
Host smart-6cb82423-ff4e-49c5-bbc5-b61bc22d4180
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368411254 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_intg_
err.1368411254
Directory /workspace/3.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/42.lc_ctrl_jtag_access.3860543720
Short name T8
Test name
Test status
Simulation time 133641152 ps
CPU time 4.27 seconds
Started Jun 02 01:26:46 PM PDT 24
Finished Jun 02 01:26:51 PM PDT 24
Peak memory 216916 kb
Host smart-e9ac945a-d2ec-4ec2-ae5b-fb7b73f7e1b1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860543720 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_jtag_access.3860543720
Directory /workspace/42.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/24.lc_ctrl_alert_test.1766857114
Short name T270
Test name
Test status
Simulation time 501854951 ps
CPU time 1.67 seconds
Started Jun 02 01:25:52 PM PDT 24
Finished Jun 02 01:25:54 PM PDT 24
Peak memory 208724 kb
Host smart-4deef310-a0f4-45bc-bc4d-2bf2663e8435
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766857114 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_alert_test.1766857114
Directory /workspace/24.lc_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.2015926175
Short name T135
Test name
Test status
Simulation time 259046303 ps
CPU time 1.8 seconds
Started Jun 02 01:10:36 PM PDT 24
Finished Jun 02 01:10:38 PM PDT 24
Peak memory 209768 kb
Host smart-9186aa95-d73f-4e1e-b8b7-29d84750fa3d
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015926175 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.lc_ctrl_jtag_csr_rw.2015926175
Directory /workspace/5.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_post_trans.3920910980
Short name T13
Test name
Test status
Simulation time 444974834 ps
CPU time 4.28 seconds
Started Jun 02 01:25:00 PM PDT 24
Finished Jun 02 01:25:04 PM PDT 24
Peak memory 217988 kb
Host smart-e629f7a2-e491-4175-ba43-1a33c556fe1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920910980 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_post_trans.3920910980
Directory /workspace/12.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.3659360672
Short name T164
Test name
Test status
Simulation time 56397526 ps
CPU time 1.03 seconds
Started Jun 02 01:10:19 PM PDT 24
Finished Jun 02 01:10:21 PM PDT 24
Peak memory 209500 kb
Host smart-753f0cab-22ae-425d-9e0e-bb8a7ede2df2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659360672 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_rw.3659360672
Directory /workspace/2.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all_with_rand_reset.2788852381
Short name T56
Test name
Test status
Simulation time 59486738187 ps
CPU time 359.65 seconds
Started Jun 02 01:24:51 PM PDT 24
Finished Jun 02 01:30:51 PM PDT 24
Peak memory 447776 kb
Host smart-8ad8fe4e-fffc-4b1d-a2f2-7abf939ff07a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2788852381 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_stress_all_with_rand_reset.2788852381
Directory /workspace/10.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_mubi.3104991930
Short name T48
Test name
Test status
Simulation time 857870934 ps
CPU time 8.94 seconds
Started Jun 02 01:25:32 PM PDT 24
Finished Jun 02 01:25:42 PM PDT 24
Peak memory 218032 kb
Host smart-18096963-b4de-4977-981b-9b701f84b15c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104991930 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_mubi.3104991930
Directory /workspace/20.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.2569672165
Short name T124
Test name
Test status
Simulation time 229799397 ps
CPU time 2.9 seconds
Started Jun 02 01:10:05 PM PDT 24
Finished Jun 02 01:10:08 PM PDT 24
Peak memory 222524 kb
Host smart-2b54fa08-bb50-4ebb-aa9f-d0a9e751376e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569672165 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_intg_
err.2569672165
Directory /workspace/0.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/20.lc_ctrl_stress_all.3264146159
Short name T17
Test name
Test status
Simulation time 15573488533 ps
CPU time 94.02 seconds
Started Jun 02 01:25:35 PM PDT 24
Finished Jun 02 01:27:09 PM PDT 24
Peak memory 217812 kb
Host smart-d6d3dc8e-ac35-4501-9711-76fbe5a8ee3f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264146159 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.lc_ctrl_stress_all.3264146159
Directory /workspace/20.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all.2282723265
Short name T103
Test name
Test status
Simulation time 27407186190 ps
CPU time 404.31 seconds
Started Jun 02 01:24:05 PM PDT 24
Finished Jun 02 01:30:49 PM PDT 24
Peak memory 300164 kb
Host smart-49b39ae3-34f5-4fd6-b2d9-c0584dd602f8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282723265 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.lc_ctrl_stress_all.2282723265
Directory /workspace/2.lc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.3259179663
Short name T120
Test name
Test status
Simulation time 32789163 ps
CPU time 2.11 seconds
Started Jun 02 01:10:53 PM PDT 24
Finished Jun 02 01:10:56 PM PDT 24
Peak memory 219180 kb
Host smart-671ba8e4-1fa0-43e3-8ca7-16479d2c8525
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259179663 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_errors.3259179663
Directory /workspace/10.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.3443329523
Short name T106
Test name
Test status
Simulation time 991151575 ps
CPU time 3.13 seconds
Started Jun 02 01:11:01 PM PDT 24
Finished Jun 02 01:11:04 PM PDT 24
Peak memory 218076 kb
Host smart-95b7ba20-6a70-48c9-9659-e4f05e0395be
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443329523 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_intg
_err.3443329523
Directory /workspace/15.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.2350559663
Short name T126
Test name
Test status
Simulation time 256376843 ps
CPU time 3.43 seconds
Started Jun 02 01:10:11 PM PDT 24
Finished Jun 02 01:10:14 PM PDT 24
Peak memory 222724 kb
Host smart-8aca9e48-e19a-4559-92ce-36ea22d9ee10
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350559663 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_intg_
err.2350559663
Directory /workspace/2.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.2743019535
Short name T169
Test name
Test status
Simulation time 30974466 ps
CPU time 0.9 seconds
Started Jun 02 01:10:04 PM PDT 24
Finished Jun 02 01:10:05 PM PDT 24
Peak memory 209820 kb
Host smart-93d1868e-becb-47ba-ade9-e12259246b13
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743019535 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_rw.2743019535
Directory /workspace/0.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/default/2.lc_ctrl_claim_transition_if.966604968
Short name T1
Test name
Test status
Simulation time 11883048 ps
CPU time 0.79 seconds
Started Jun 02 01:23:55 PM PDT 24
Finished Jun 02 01:23:56 PM PDT 24
Peak memory 208520 kb
Host smart-c7036764-e2eb-425f-9264-093cc617f051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966604968 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_claim_transition_if.966604968
Directory /workspace/2.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.2114678962
Short name T122
Test name
Test status
Simulation time 211679151 ps
CPU time 3.95 seconds
Started Jun 02 01:10:38 PM PDT 24
Finished Jun 02 01:10:42 PM PDT 24
Peak memory 218400 kb
Host smart-e2556659-9b55-42d2-b0b0-534d2b6a5235
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114678962 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_intg_
err.2114678962
Directory /workspace/7.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_claim_transition_if.15730190
Short name T152
Test name
Test status
Simulation time 41918568 ps
CPU time 0.77 seconds
Started Jun 02 01:23:41 PM PDT 24
Finished Jun 02 01:23:43 PM PDT 24
Peak memory 208644 kb
Host smart-09fd0e89-6392-439b-a0c5-cc49509be345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15730190 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_claim_transition_if.15730190
Directory /workspace/0.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/14.lc_ctrl_security_escalation.1388970058
Short name T315
Test name
Test status
Simulation time 1689634913 ps
CPU time 5.23 seconds
Started Jun 02 01:25:06 PM PDT 24
Finished Jun 02 01:25:12 PM PDT 24
Peak memory 218024 kb
Host smart-74e495dc-7980-4393-9a09-05254f3bd092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388970058 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_security_escalation.1388970058
Directory /workspace/14.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/5.lc_ctrl_claim_transition_if.2974851102
Short name T186
Test name
Test status
Simulation time 16152790 ps
CPU time 0.81 seconds
Started Jun 02 01:24:14 PM PDT 24
Finished Jun 02 01:24:16 PM PDT 24
Peak memory 208732 kb
Host smart-6aaf5e07-fc11-4e13-9071-af633da5b88c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974851102 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_claim_transition_if.2974851102
Directory /workspace/5.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/6.lc_ctrl_claim_transition_if.2238529712
Short name T188
Test name
Test status
Simulation time 16401824 ps
CPU time 0.88 seconds
Started Jun 02 01:24:24 PM PDT 24
Finished Jun 02 01:24:25 PM PDT 24
Peak memory 208724 kb
Host smart-954a8313-38b6-40b8-8575-6afb21ee4df0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238529712 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_claim_transition_if.2238529712
Directory /workspace/6.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/9.lc_ctrl_claim_transition_if.1682885243
Short name T177
Test name
Test status
Simulation time 13602790 ps
CPU time 0.97 seconds
Started Jun 02 01:24:44 PM PDT 24
Finished Jun 02 01:24:45 PM PDT 24
Peak memory 208732 kb
Host smart-abc41877-9f27-4226-a5f0-23dbd24f968b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682885243 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_claim_transition_if.1682885243
Directory /workspace/9.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.4215108641
Short name T117
Test name
Test status
Simulation time 634596750 ps
CPU time 2.58 seconds
Started Jun 02 01:10:13 PM PDT 24
Finished Jun 02 01:10:16 PM PDT 24
Peak memory 218108 kb
Host smart-d5c852e3-96e3-4e12-bf80-264352981a44
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215108641 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_intg_
err.4215108641
Directory /workspace/1.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.3750699719
Short name T131
Test name
Test status
Simulation time 120617236 ps
CPU time 2.77 seconds
Started Jun 02 01:10:52 PM PDT 24
Finished Jun 02 01:10:55 PM PDT 24
Peak memory 218168 kb
Host smart-18c9c0d9-f9d6-4329-b6bd-d456feb3f42d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750699719 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_intg
_err.3750699719
Directory /workspace/11.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.1839545903
Short name T108
Test name
Test status
Simulation time 47443064 ps
CPU time 1.8 seconds
Started Jun 02 01:11:02 PM PDT 24
Finished Jun 02 01:11:04 PM PDT 24
Peak memory 222432 kb
Host smart-1631ad78-b0a2-4f47-95b7-e257908574e3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839545903 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_intg
_err.1839545903
Directory /workspace/14.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.2972804575
Short name T128
Test name
Test status
Simulation time 245913265 ps
CPU time 2.03 seconds
Started Jun 02 01:10:58 PM PDT 24
Finished Jun 02 01:11:01 PM PDT 24
Peak memory 222448 kb
Host smart-30fff555-0fcd-478b-966a-d6407ee4adba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972804575 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_intg
_err.2972804575
Directory /workspace/16.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.710510990
Short name T133
Test name
Test status
Simulation time 121002987 ps
CPU time 3.84 seconds
Started Jun 02 01:11:07 PM PDT 24
Finished Jun 02 01:11:11 PM PDT 24
Peak memory 218060 kb
Host smart-5b0a3d84-be07-4526-b578-176068dc29da
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710510990 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_intg_
err.710510990
Directory /workspace/17.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.731994600
Short name T125
Test name
Test status
Simulation time 182691899 ps
CPU time 2.41 seconds
Started Jun 02 01:10:25 PM PDT 24
Finished Jun 02 01:10:28 PM PDT 24
Peak memory 218192 kb
Host smart-c138e625-5205-4697-8950-c43abd02c2cc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731994600 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_intg_e
rr.731994600
Directory /workspace/4.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.1534558977
Short name T119
Test name
Test status
Simulation time 129874687 ps
CPU time 3.17 seconds
Started Jun 02 01:10:36 PM PDT 24
Finished Jun 02 01:10:39 PM PDT 24
Peak memory 222436 kb
Host smart-8a7b6def-b1a9-4185-888a-0fb5a67b8454
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534558977 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_intg_
err.1534558977
Directory /workspace/6.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_failure.3041242920
Short name T11
Test name
Test status
Simulation time 254256344 ps
CPU time 23.5 seconds
Started Jun 02 01:25:05 PM PDT 24
Finished Jun 02 01:25:29 PM PDT 24
Peak memory 250948 kb
Host smart-6966c193-8ce0-4f2c-b37a-da909afcda0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041242920 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_failure.3041242920
Directory /workspace/12.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_post_trans.1351608158
Short name T22
Test name
Test status
Simulation time 3503208739 ps
CPU time 16.95 seconds
Started Jun 02 01:24:54 PM PDT 24
Finished Jun 02 01:25:11 PM PDT 24
Peak memory 249444 kb
Host smart-dfdcc92f-e803-4b05-adc5-767cac49a402
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351608158 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl
_jtag_state_post_trans.1351608158
Directory /workspace/10.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all.3416436193
Short name T19
Test name
Test status
Simulation time 514845984 ps
CPU time 34.83 seconds
Started Jun 02 01:25:23 PM PDT 24
Finished Jun 02 01:25:58 PM PDT 24
Peak memory 251000 kb
Host smart-4d9867df-36f2-46b1-ba5f-816930c486d2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416436193 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.lc_ctrl_stress_all.3416436193
Directory /workspace/17.lc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.2485428578
Short name T965
Test name
Test status
Simulation time 37404400 ps
CPU time 1.38 seconds
Started Jun 02 01:10:06 PM PDT 24
Finished Jun 02 01:10:07 PM PDT 24
Peak memory 209848 kb
Host smart-8a2ed9d5-2eb4-41d2-8a1d-96708807659d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485428578 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_aliasin
g.2485428578
Directory /workspace/0.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.1652969528
Short name T168
Test name
Test status
Simulation time 188201919 ps
CPU time 1.45 seconds
Started Jun 02 01:10:08 PM PDT 24
Finished Jun 02 01:10:10 PM PDT 24
Peak memory 209796 kb
Host smart-d733589c-7a77-4a39-ade3-9b39d719bc41
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652969528 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_bit_bas
h.1652969528
Directory /workspace/0.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.1479520406
Short name T908
Test name
Test status
Simulation time 17395848 ps
CPU time 1.09 seconds
Started Jun 02 01:10:06 PM PDT 24
Finished Jun 02 01:10:07 PM PDT 24
Peak memory 210856 kb
Host smart-2209a844-e2b7-469c-b459-c2ad849ea55b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479520406 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_hw_rese
t.1479520406
Directory /workspace/0.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.1814306056
Short name T954
Test name
Test status
Simulation time 175123936 ps
CPU time 1.78 seconds
Started Jun 02 01:10:08 PM PDT 24
Finished Jun 02 01:10:10 PM PDT 24
Peak memory 220296 kb
Host smart-de0b7ce4-522e-4790-829d-e01116c23b2c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814306056 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 0.lc_ctrl_csr_mem_rw_with_rand_reset.1814306056
Directory /workspace/0.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.1498010452
Short name T141
Test name
Test status
Simulation time 25469708 ps
CPU time 1.01 seconds
Started Jun 02 01:10:04 PM PDT 24
Finished Jun 02 01:10:06 PM PDT 24
Peak memory 208964 kb
Host smart-367a0ef8-6b86-44e6-8db6-56e95beb36af
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498010452 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.lc_ctrl_jtag_alert_test.1498010452
Directory /workspace/0.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.526377843
Short name T897
Test name
Test status
Simulation time 837230378 ps
CPU time 6.15 seconds
Started Jun 02 01:09:58 PM PDT 24
Finished Jun 02 01:10:04 PM PDT 24
Peak memory 209684 kb
Host smart-47eeb8da-9da5-4075-b8ca-d282d63b5faa
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526377843 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 0.lc_ctrl_jtag_csr_aliasing.526377843
Directory /workspace/0.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.848134788
Short name T956
Test name
Test status
Simulation time 1646999413 ps
CPU time 15.19 seconds
Started Jun 02 01:09:57 PM PDT 24
Finished Jun 02 01:10:13 PM PDT 24
Peak memory 209736 kb
Host smart-73825c33-e347-4a3d-afc6-ddee028be3a3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848134788 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 0.lc_ctrl_jtag_csr_bit_bash.848134788
Directory /workspace/0.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.711491548
Short name T900
Test name
Test status
Simulation time 258271690 ps
CPU time 2.32 seconds
Started Jun 02 01:09:57 PM PDT 24
Finished Jun 02 01:10:00 PM PDT 24
Peak memory 217964 kb
Host smart-8912b707-d2ec-4507-bb59-cfbfc5ee1b56
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711491548 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 0.lc_ctrl_jtag_csr_hw_reset.711491548
Directory /workspace/0.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3678431902
Short name T910
Test name
Test status
Simulation time 74291845 ps
CPU time 1.78 seconds
Started Jun 02 01:09:56 PM PDT 24
Finished Jun 02 01:09:59 PM PDT 24
Peak memory 219740 kb
Host smart-6961bd9c-5bd6-4ba5-ab92-b6997d5bf278
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367843
1902 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3678431902
Directory /workspace/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.2189137658
Short name T992
Test name
Test status
Simulation time 304320251 ps
CPU time 1.16 seconds
Started Jun 02 01:10:01 PM PDT 24
Finished Jun 02 01:10:03 PM PDT 24
Peak memory 217176 kb
Host smart-41f28ca3-1f93-4677-ad2a-4349c4006bda
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189137658 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.lc_ctrl_jtag_csr_rw.2189137658
Directory /workspace/0.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.539541501
Short name T943
Test name
Test status
Simulation time 19428546 ps
CPU time 1.27 seconds
Started Jun 02 01:10:04 PM PDT 24
Finished Jun 02 01:10:05 PM PDT 24
Peak memory 209836 kb
Host smart-d94e5c04-f073-4139-9d62-0f290781f02a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539541501 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.lc_ctrl_jtag_same_csr_outstanding.539541501
Directory /workspace/0.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.1700987526
Short name T170
Test name
Test status
Simulation time 26315788 ps
CPU time 1.44 seconds
Started Jun 02 01:10:06 PM PDT 24
Finished Jun 02 01:10:07 PM PDT 24
Peak memory 217744 kb
Host smart-97a68354-3d45-4cc4-9bf7-e1d99e78552d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700987526 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl
_same_csr_outstanding.1700987526
Directory /workspace/0.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.3478720656
Short name T959
Test name
Test status
Simulation time 125796139 ps
CPU time 2.22 seconds
Started Jun 02 01:10:04 PM PDT 24
Finished Jun 02 01:10:07 PM PDT 24
Peak memory 218508 kb
Host smart-538bdb89-c830-4e02-922e-1c94a3bf2c50
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478720656 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_errors.3478720656
Directory /workspace/0.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.939522257
Short name T902
Test name
Test status
Simulation time 263112206 ps
CPU time 1.54 seconds
Started Jun 02 01:10:11 PM PDT 24
Finished Jun 02 01:10:13 PM PDT 24
Peak memory 209856 kb
Host smart-1de69e2d-4061-48e3-97f3-9d4e64a898cf
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939522257 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_aliasing
.939522257
Directory /workspace/1.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.2138423944
Short name T866
Test name
Test status
Simulation time 38810869 ps
CPU time 1.79 seconds
Started Jun 02 01:10:11 PM PDT 24
Finished Jun 02 01:10:13 PM PDT 24
Peak memory 209652 kb
Host smart-1566a8b7-10af-4f37-9d6c-bbdfe8566c82
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138423944 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_bit_bas
h.2138423944
Directory /workspace/1.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.3429589894
Short name T115
Test name
Test status
Simulation time 40192525 ps
CPU time 0.87 seconds
Started Jun 02 01:10:12 PM PDT 24
Finished Jun 02 01:10:13 PM PDT 24
Peak memory 210284 kb
Host smart-bf0763f1-d6b5-468b-9af2-1e36d09c01d4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429589894 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_hw_rese
t.3429589894
Directory /workspace/1.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.3940677114
Short name T896
Test name
Test status
Simulation time 35209922 ps
CPU time 1.17 seconds
Started Jun 02 01:10:12 PM PDT 24
Finished Jun 02 01:10:14 PM PDT 24
Peak memory 220012 kb
Host smart-5a55c313-b8b1-4f1d-888b-40445cd3ecf1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940677114 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 1.lc_ctrl_csr_mem_rw_with_rand_reset.3940677114
Directory /workspace/1.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.833962903
Short name T166
Test name
Test status
Simulation time 41715299 ps
CPU time 0.89 seconds
Started Jun 02 01:10:12 PM PDT 24
Finished Jun 02 01:10:13 PM PDT 24
Peak memory 209636 kb
Host smart-7efb88ea-ff4a-4bec-bc37-1229c6f1b564
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833962903 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_rw.833962903
Directory /workspace/1.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.3928400282
Short name T869
Test name
Test status
Simulation time 145592139 ps
CPU time 1.16 seconds
Started Jun 02 01:10:13 PM PDT 24
Finished Jun 02 01:10:14 PM PDT 24
Peak memory 209672 kb
Host smart-8569a58c-72e8-4dcb-abfe-fbefd18a0fe2
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928400282 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.lc_ctrl_jtag_alert_test.3928400282
Directory /workspace/1.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.1940168716
Short name T874
Test name
Test status
Simulation time 191561303 ps
CPU time 2.92 seconds
Started Jun 02 01:10:11 PM PDT 24
Finished Jun 02 01:10:14 PM PDT 24
Peak memory 217196 kb
Host smart-38d9efe6-4e8b-47de-ad29-04f6e688f81f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940168716 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_aliasing.1940168716
Directory /workspace/1.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.1567399483
Short name T976
Test name
Test status
Simulation time 3039315428 ps
CPU time 14.87 seconds
Started Jun 02 01:10:10 PM PDT 24
Finished Jun 02 01:10:26 PM PDT 24
Peak memory 217360 kb
Host smart-f1ef5721-777f-496e-9b22-74535cd13dde
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567399483 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_bit_bash.1567399483
Directory /workspace/1.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.562386474
Short name T986
Test name
Test status
Simulation time 159310525 ps
CPU time 1.73 seconds
Started Jun 02 01:10:12 PM PDT 24
Finished Jun 02 01:10:14 PM PDT 24
Peak memory 211368 kb
Host smart-c97fcc9c-8710-4b60-bf14-e06e481a3d24
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562386474 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 1.lc_ctrl_jtag_csr_hw_reset.562386474
Directory /workspace/1.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3839077488
Short name T144
Test name
Test status
Simulation time 67926744 ps
CPU time 2.59 seconds
Started Jun 02 01:10:13 PM PDT 24
Finished Jun 02 01:10:16 PM PDT 24
Peak memory 220916 kb
Host smart-b1dda784-9760-4137-b6c0-e9cc8825a037
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383907
7488 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3839077488
Directory /workspace/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.1887342527
Short name T136
Test name
Test status
Simulation time 128986558 ps
CPU time 1.49 seconds
Started Jun 02 01:10:12 PM PDT 24
Finished Jun 02 01:10:14 PM PDT 24
Peak memory 209704 kb
Host smart-f15d4b63-4654-48db-8723-0c3e9ba9705f
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887342527 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.lc_ctrl_jtag_csr_rw.1887342527
Directory /workspace/1.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.90318245
Short name T972
Test name
Test status
Simulation time 23095653 ps
CPU time 1.15 seconds
Started Jun 02 01:10:10 PM PDT 24
Finished Jun 02 01:10:12 PM PDT 24
Peak memory 209868 kb
Host smart-d7214024-416f-42bb-81f4-c91be018b9d7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90318245 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 1.lc_ctrl_jtag_same_csr_outstanding.90318245
Directory /workspace/1.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.3205033101
Short name T176
Test name
Test status
Simulation time 59350231 ps
CPU time 1.4 seconds
Started Jun 02 01:10:11 PM PDT 24
Finished Jun 02 01:10:13 PM PDT 24
Peak memory 212024 kb
Host smart-30d7b513-7d54-49a0-ae23-2bb959418273
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205033101 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl
_same_csr_outstanding.3205033101
Directory /workspace/1.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.893745291
Short name T918
Test name
Test status
Simulation time 101139259 ps
CPU time 3.81 seconds
Started Jun 02 01:10:12 PM PDT 24
Finished Jun 02 01:10:17 PM PDT 24
Peak memory 219140 kb
Host smart-be6cfb37-e293-4d01-ad08-ab91d7e42713
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893745291 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_errors.893745291
Directory /workspace/1.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.101998220
Short name T953
Test name
Test status
Simulation time 22351161 ps
CPU time 0.97 seconds
Started Jun 02 01:10:53 PM PDT 24
Finished Jun 02 01:10:55 PM PDT 24
Peak memory 209824 kb
Host smart-1bb26426-f214-4104-b2ec-986c36486e31
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101998220 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 10.lc_ctrl_csr_mem_rw_with_rand_reset.101998220
Directory /workspace/10.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.1227276979
Short name T991
Test name
Test status
Simulation time 42969169 ps
CPU time 1 seconds
Started Jun 02 01:10:53 PM PDT 24
Finished Jun 02 01:10:55 PM PDT 24
Peak memory 209888 kb
Host smart-a0928dfc-963d-4267-9088-414f8b5f3feb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227276979 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_csr_rw.1227276979
Directory /workspace/10.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.452265815
Short name T984
Test name
Test status
Simulation time 153035332 ps
CPU time 1.31 seconds
Started Jun 02 01:10:50 PM PDT 24
Finished Jun 02 01:10:52 PM PDT 24
Peak memory 209684 kb
Host smart-5c4dfc25-476e-4a34-a9ca-b4bde3eadb8b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452265815 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl
_same_csr_outstanding.452265815
Directory /workspace/10.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.1758219075
Short name T127
Test name
Test status
Simulation time 250259658 ps
CPU time 2.67 seconds
Started Jun 02 01:10:54 PM PDT 24
Finished Jun 02 01:10:57 PM PDT 24
Peak memory 218140 kb
Host smart-013755c5-d4b2-434e-8eb1-6f52375feef3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758219075 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_intg
_err.1758219075
Directory /workspace/10.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.493709442
Short name T931
Test name
Test status
Simulation time 26353382 ps
CPU time 1.25 seconds
Started Jun 02 01:10:53 PM PDT 24
Finished Jun 02 01:10:55 PM PDT 24
Peak memory 218268 kb
Host smart-edfcbf70-4bb1-4e4a-bd07-edf69a41e7d0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493709442 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 11.lc_ctrl_csr_mem_rw_with_rand_reset.493709442
Directory /workspace/11.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.3227996242
Short name T880
Test name
Test status
Simulation time 13047937 ps
CPU time 0.96 seconds
Started Jun 02 01:10:51 PM PDT 24
Finished Jun 02 01:10:53 PM PDT 24
Peak memory 209116 kb
Host smart-494a2016-2d9f-434c-acd9-4a131f08dcbb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227996242 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_csr_rw.3227996242
Directory /workspace/11.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.4126366877
Short name T924
Test name
Test status
Simulation time 19872984 ps
CPU time 1.37 seconds
Started Jun 02 01:10:54 PM PDT 24
Finished Jun 02 01:10:56 PM PDT 24
Peak memory 209900 kb
Host smart-b3ba8781-ef97-4ea7-a050-6aa2554d62cc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126366877 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctr
l_same_csr_outstanding.4126366877
Directory /workspace/11.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.814732207
Short name T904
Test name
Test status
Simulation time 238374924 ps
CPU time 1.83 seconds
Started Jun 02 01:10:54 PM PDT 24
Finished Jun 02 01:10:56 PM PDT 24
Peak memory 218124 kb
Host smart-b6423ff4-0de9-471f-be9e-7f1f32282c54
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814732207 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_errors.814732207
Directory /workspace/11.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.2750233227
Short name T890
Test name
Test status
Simulation time 39076713 ps
CPU time 1.75 seconds
Started Jun 02 01:10:58 PM PDT 24
Finished Jun 02 01:11:00 PM PDT 24
Peak memory 219888 kb
Host smart-e29c574c-d091-41b9-85f4-a7dba223e3d8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750233227 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 12.lc_ctrl_csr_mem_rw_with_rand_reset.2750233227
Directory /workspace/12.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.2690823463
Short name T134
Test name
Test status
Simulation time 78898269 ps
CPU time 0.9 seconds
Started Jun 02 01:10:53 PM PDT 24
Finished Jun 02 01:10:54 PM PDT 24
Peak memory 209356 kb
Host smart-c521c31f-74df-4cb3-90e7-170a70358cb2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690823463 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_csr_rw.2690823463
Directory /workspace/12.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.3751002259
Short name T940
Test name
Test status
Simulation time 46779892 ps
CPU time 1.38 seconds
Started Jun 02 01:10:51 PM PDT 24
Finished Jun 02 01:10:53 PM PDT 24
Peak memory 209924 kb
Host smart-90aa4888-6ce2-44c8-9ac0-ba9f73b7c3d4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751002259 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctr
l_same_csr_outstanding.3751002259
Directory /workspace/12.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.1046241740
Short name T912
Test name
Test status
Simulation time 49039172 ps
CPU time 3.16 seconds
Started Jun 02 01:10:53 PM PDT 24
Finished Jun 02 01:10:57 PM PDT 24
Peak memory 218128 kb
Host smart-0fa07a14-b42a-4160-a29e-882badd8567a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046241740 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_errors.1046241740
Directory /workspace/12.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.528945294
Short name T123
Test name
Test status
Simulation time 923788726 ps
CPU time 2.99 seconds
Started Jun 02 01:10:53 PM PDT 24
Finished Jun 02 01:10:57 PM PDT 24
Peak memory 222172 kb
Host smart-f677c162-abef-41d8-b213-c729afb61d76
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528945294 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_intg_
err.528945294
Directory /workspace/12.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.1334529654
Short name T911
Test name
Test status
Simulation time 21088989 ps
CPU time 1.3 seconds
Started Jun 02 01:10:59 PM PDT 24
Finished Jun 02 01:11:00 PM PDT 24
Peak memory 218552 kb
Host smart-c3d41952-18c7-4547-b615-c0908fada28a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334529654 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 13.lc_ctrl_csr_mem_rw_with_rand_reset.1334529654
Directory /workspace/13.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.2579128242
Short name T974
Test name
Test status
Simulation time 32511610 ps
CPU time 0.93 seconds
Started Jun 02 01:11:01 PM PDT 24
Finished Jun 02 01:11:03 PM PDT 24
Peak memory 209448 kb
Host smart-293a019e-7f7c-4949-a397-71022a02580b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579128242 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_csr_rw.2579128242
Directory /workspace/13.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.461018991
Short name T932
Test name
Test status
Simulation time 31234761 ps
CPU time 1.57 seconds
Started Jun 02 01:10:57 PM PDT 24
Finished Jun 02 01:10:59 PM PDT 24
Peak memory 209944 kb
Host smart-3135fde3-6a19-4777-ae01-782855599969
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461018991 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl
_same_csr_outstanding.461018991
Directory /workspace/13.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.3586460480
Short name T983
Test name
Test status
Simulation time 118446678 ps
CPU time 4.52 seconds
Started Jun 02 01:10:59 PM PDT 24
Finished Jun 02 01:11:04 PM PDT 24
Peak memory 218156 kb
Host smart-e2d22de1-fd53-4968-9c74-a9814b6b9464
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586460480 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_errors.3586460480
Directory /workspace/13.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.3858322306
Short name T116
Test name
Test status
Simulation time 108501874 ps
CPU time 2.55 seconds
Started Jun 02 01:11:02 PM PDT 24
Finished Jun 02 01:11:05 PM PDT 24
Peak memory 218212 kb
Host smart-66c32394-3a65-49b9-a83a-94977be6fc24
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858322306 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_intg
_err.3858322306
Directory /workspace/13.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.3491850383
Short name T949
Test name
Test status
Simulation time 16614333 ps
CPU time 1.35 seconds
Started Jun 02 01:11:00 PM PDT 24
Finished Jun 02 01:11:02 PM PDT 24
Peak memory 219796 kb
Host smart-9d995b15-ddc8-4a33-b27d-30b0c495fb5c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491850383 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 14.lc_ctrl_csr_mem_rw_with_rand_reset.3491850383
Directory /workspace/14.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.3665696399
Short name T112
Test name
Test status
Simulation time 66476406 ps
CPU time 0.88 seconds
Started Jun 02 01:10:59 PM PDT 24
Finished Jun 02 01:11:00 PM PDT 24
Peak memory 209360 kb
Host smart-45c4e068-8757-4573-bb1d-97d810bb269b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665696399 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_csr_rw.3665696399
Directory /workspace/14.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.3466034965
Short name T889
Test name
Test status
Simulation time 49269260 ps
CPU time 2.21 seconds
Started Jun 02 01:10:59 PM PDT 24
Finished Jun 02 01:11:02 PM PDT 24
Peak memory 212092 kb
Host smart-bad0e597-f77d-4a63-9f77-b80ae1d183a4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466034965 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctr
l_same_csr_outstanding.3466034965
Directory /workspace/14.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.3634502536
Short name T969
Test name
Test status
Simulation time 303316852 ps
CPU time 3.43 seconds
Started Jun 02 01:11:00 PM PDT 24
Finished Jun 02 01:11:03 PM PDT 24
Peak memory 218124 kb
Host smart-256c50ab-01be-4382-a747-1cb33d692cc9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634502536 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_errors.3634502536
Directory /workspace/14.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.2715835741
Short name T893
Test name
Test status
Simulation time 106167321 ps
CPU time 1.61 seconds
Started Jun 02 01:10:58 PM PDT 24
Finished Jun 02 01:11:00 PM PDT 24
Peak memory 223152 kb
Host smart-04686da0-ea67-42af-b4e8-efc2715e558a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715835741 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 15.lc_ctrl_csr_mem_rw_with_rand_reset.2715835741
Directory /workspace/15.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.620409043
Short name T163
Test name
Test status
Simulation time 111247386 ps
CPU time 1.07 seconds
Started Jun 02 01:11:00 PM PDT 24
Finished Jun 02 01:11:02 PM PDT 24
Peak memory 209644 kb
Host smart-3979e901-f07c-4a8c-81f3-4c6fc4552f18
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620409043 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_csr_rw.620409043
Directory /workspace/15.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.672813001
Short name T172
Test name
Test status
Simulation time 19637523 ps
CPU time 1.49 seconds
Started Jun 02 01:11:01 PM PDT 24
Finished Jun 02 01:11:03 PM PDT 24
Peak memory 218128 kb
Host smart-ca32b58f-829a-4ea8-9a77-6c5c3acc0911
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672813001 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl
_same_csr_outstanding.672813001
Directory /workspace/15.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.2758566824
Short name T939
Test name
Test status
Simulation time 193962983 ps
CPU time 3.95 seconds
Started Jun 02 01:11:00 PM PDT 24
Finished Jun 02 01:11:04 PM PDT 24
Peak memory 218076 kb
Host smart-1ac3e562-ed7b-4880-ba5a-fae7d7f2bcc9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758566824 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_errors.2758566824
Directory /workspace/15.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.2472937853
Short name T877
Test name
Test status
Simulation time 60910586 ps
CPU time 1.23 seconds
Started Jun 02 01:11:08 PM PDT 24
Finished Jun 02 01:11:09 PM PDT 24
Peak memory 218356 kb
Host smart-99cc4b73-dd3c-4b75-b2e0-b88b83a6df3b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472937853 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 16.lc_ctrl_csr_mem_rw_with_rand_reset.2472937853
Directory /workspace/16.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.3770469331
Short name T868
Test name
Test status
Simulation time 69707832 ps
CPU time 1.03 seconds
Started Jun 02 01:11:06 PM PDT 24
Finished Jun 02 01:11:07 PM PDT 24
Peak memory 209736 kb
Host smart-b0a47b43-88df-4346-b5d4-91a62435dddf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770469331 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_csr_rw.3770469331
Directory /workspace/16.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.1842579545
Short name T171
Test name
Test status
Simulation time 21151945 ps
CPU time 1.36 seconds
Started Jun 02 01:11:08 PM PDT 24
Finished Jun 02 01:11:10 PM PDT 24
Peak memory 210016 kb
Host smart-f154dd5b-d140-4bb6-93bd-6c7cd8e56c08
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842579545 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctr
l_same_csr_outstanding.1842579545
Directory /workspace/16.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.1626070158
Short name T118
Test name
Test status
Simulation time 125977235 ps
CPU time 2.02 seconds
Started Jun 02 01:11:00 PM PDT 24
Finished Jun 02 01:11:02 PM PDT 24
Peak memory 218596 kb
Host smart-136fdfc7-0342-4643-9564-a38098a1c477
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626070158 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_errors.1626070158
Directory /workspace/16.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.1391108764
Short name T935
Test name
Test status
Simulation time 87771853 ps
CPU time 1.47 seconds
Started Jun 02 01:11:07 PM PDT 24
Finished Jun 02 01:11:09 PM PDT 24
Peak memory 218156 kb
Host smart-f1f80b0f-8549-4c1d-a090-fbc430f4ceff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391108764 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 17.lc_ctrl_csr_mem_rw_with_rand_reset.1391108764
Directory /workspace/17.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.2846015339
Short name T977
Test name
Test status
Simulation time 58962961 ps
CPU time 0.93 seconds
Started Jun 02 01:11:07 PM PDT 24
Finished Jun 02 01:11:08 PM PDT 24
Peak memory 209484 kb
Host smart-f5728ce3-6ab1-4c68-8f5c-eab7d4e8a979
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846015339 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_csr_rw.2846015339
Directory /workspace/17.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.558728233
Short name T914
Test name
Test status
Simulation time 85005435 ps
CPU time 1.38 seconds
Started Jun 02 01:11:09 PM PDT 24
Finished Jun 02 01:11:10 PM PDT 24
Peak memory 209944 kb
Host smart-45652a65-5a69-4430-a09a-8e74f3408820
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558728233 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl
_same_csr_outstanding.558728233
Directory /workspace/17.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.4274926234
Short name T876
Test name
Test status
Simulation time 170660084 ps
CPU time 4.7 seconds
Started Jun 02 01:11:06 PM PDT 24
Finished Jun 02 01:11:11 PM PDT 24
Peak memory 218120 kb
Host smart-2ce1e9f1-c36b-43d3-af85-74267d4fd21a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274926234 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_errors.4274926234
Directory /workspace/17.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.2715452636
Short name T925
Test name
Test status
Simulation time 24850323 ps
CPU time 2.01 seconds
Started Jun 02 01:11:08 PM PDT 24
Finished Jun 02 01:11:11 PM PDT 24
Peak memory 218212 kb
Host smart-c8b60719-58f7-4d15-bbb7-714349f5d315
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715452636 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 18.lc_ctrl_csr_mem_rw_with_rand_reset.2715452636
Directory /workspace/18.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.889537211
Short name T942
Test name
Test status
Simulation time 62120006 ps
CPU time 0.96 seconds
Started Jun 02 01:11:08 PM PDT 24
Finished Jun 02 01:11:10 PM PDT 24
Peak memory 209124 kb
Host smart-eea52aa8-2d2e-480a-88bc-a0e74c18b512
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889537211 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_csr_rw.889537211
Directory /workspace/18.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.977993074
Short name T975
Test name
Test status
Simulation time 95256385 ps
CPU time 1.19 seconds
Started Jun 02 01:11:06 PM PDT 24
Finished Jun 02 01:11:08 PM PDT 24
Peak memory 217784 kb
Host smart-d48cd8ee-b872-4720-8869-1d010618ed10
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977993074 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl
_same_csr_outstanding.977993074
Directory /workspace/18.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.3278836081
Short name T113
Test name
Test status
Simulation time 73932534 ps
CPU time 2.5 seconds
Started Jun 02 01:11:08 PM PDT 24
Finished Jun 02 01:11:11 PM PDT 24
Peak memory 218124 kb
Host smart-e5a51b1d-32f9-4bca-9588-734437f2e6ed
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278836081 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_errors.3278836081
Directory /workspace/18.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.2650005921
Short name T985
Test name
Test status
Simulation time 658038166 ps
CPU time 2.12 seconds
Started Jun 02 01:11:08 PM PDT 24
Finished Jun 02 01:11:11 PM PDT 24
Peak memory 222244 kb
Host smart-7db43033-e337-40a9-bcc2-72f513978355
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650005921 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_intg
_err.2650005921
Directory /workspace/18.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.254472529
Short name T891
Test name
Test status
Simulation time 125856876 ps
CPU time 2.15 seconds
Started Jun 02 01:11:08 PM PDT 24
Finished Jun 02 01:11:11 PM PDT 24
Peak memory 220304 kb
Host smart-78aa7870-c4b2-4b61-a2e9-ede50a4801db
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254472529 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 19.lc_ctrl_csr_mem_rw_with_rand_reset.254472529
Directory /workspace/19.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.1059685744
Short name T167
Test name
Test status
Simulation time 34397645 ps
CPU time 0.98 seconds
Started Jun 02 01:11:09 PM PDT 24
Finished Jun 02 01:11:10 PM PDT 24
Peak memory 209792 kb
Host smart-6188b9d3-7ece-48be-847f-d8dde139d2cb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059685744 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_csr_rw.1059685744
Directory /workspace/19.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.2992760271
Short name T173
Test name
Test status
Simulation time 17272553 ps
CPU time 1.03 seconds
Started Jun 02 01:11:09 PM PDT 24
Finished Jun 02 01:11:11 PM PDT 24
Peak memory 209984 kb
Host smart-736df04a-b216-4523-a92e-1844fac45a27
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992760271 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctr
l_same_csr_outstanding.2992760271
Directory /workspace/19.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.115381627
Short name T945
Test name
Test status
Simulation time 200979766 ps
CPU time 2.49 seconds
Started Jun 02 01:11:08 PM PDT 24
Finished Jun 02 01:11:11 PM PDT 24
Peak memory 218116 kb
Host smart-4fe8efc8-f812-4c8c-af9f-181898ac4eb1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115381627 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_intg_
err.115381627
Directory /workspace/19.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.2233868470
Short name T887
Test name
Test status
Simulation time 36816518 ps
CPU time 0.98 seconds
Started Jun 02 01:10:18 PM PDT 24
Finished Jun 02 01:10:19 PM PDT 24
Peak memory 209276 kb
Host smart-06318de4-79e7-4984-bf73-e61b819ea45b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233868470 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_aliasin
g.2233868470
Directory /workspace/2.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.1761846805
Short name T899
Test name
Test status
Simulation time 142277414 ps
CPU time 1.7 seconds
Started Jun 02 01:10:17 PM PDT 24
Finished Jun 02 01:10:19 PM PDT 24
Peak memory 209416 kb
Host smart-0230bb2a-f9f0-4991-b60d-52c78c1690b6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761846805 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_bit_bas
h.1761846805
Directory /workspace/2.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.2426060447
Short name T875
Test name
Test status
Simulation time 40596178 ps
CPU time 0.91 seconds
Started Jun 02 01:10:11 PM PDT 24
Finished Jun 02 01:10:12 PM PDT 24
Peak memory 210268 kb
Host smart-7dec5cd2-cf81-42b0-a8e3-5e859fdfafe8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426060447 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_hw_rese
t.2426060447
Directory /workspace/2.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.3740578256
Short name T903
Test name
Test status
Simulation time 34718341 ps
CPU time 1.05 seconds
Started Jun 02 01:10:19 PM PDT 24
Finished Jun 02 01:10:21 PM PDT 24
Peak memory 219204 kb
Host smart-034ce4f3-f0bc-4fba-b8e8-006037d65fa2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740578256 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 2.lc_ctrl_csr_mem_rw_with_rand_reset.3740578256
Directory /workspace/2.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.1709990941
Short name T905
Test name
Test status
Simulation time 393025252 ps
CPU time 2.86 seconds
Started Jun 02 01:10:14 PM PDT 24
Finished Jun 02 01:10:17 PM PDT 24
Peak memory 208960 kb
Host smart-7f37057f-2f5c-458f-8eff-3f4fe168d73c
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709990941 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.lc_ctrl_jtag_alert_test.1709990941
Directory /workspace/2.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.621645503
Short name T968
Test name
Test status
Simulation time 1710062173 ps
CPU time 9.39 seconds
Started Jun 02 01:10:13 PM PDT 24
Finished Jun 02 01:10:23 PM PDT 24
Peak memory 209640 kb
Host smart-9a6fd5b2-d82f-424c-adc9-6629ce8bd0ff
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621645503 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 2.lc_ctrl_jtag_csr_aliasing.621645503
Directory /workspace/2.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.3048600077
Short name T971
Test name
Test status
Simulation time 1920353570 ps
CPU time 14.03 seconds
Started Jun 02 01:10:12 PM PDT 24
Finished Jun 02 01:10:26 PM PDT 24
Peak memory 209304 kb
Host smart-713c0c4d-5232-49a2-944d-cdc2d0022241
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048600077 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_bit_bash.3048600077
Directory /workspace/2.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.2604742835
Short name T920
Test name
Test status
Simulation time 62376716 ps
CPU time 1.56 seconds
Started Jun 02 01:10:12 PM PDT 24
Finished Jun 02 01:10:14 PM PDT 24
Peak memory 211200 kb
Host smart-5ed0b075-ac4d-41d5-83b0-6f84952a1869
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604742835 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_hw_reset.2604742835
Directory /workspace/2.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3110008093
Short name T922
Test name
Test status
Simulation time 152830456 ps
CPU time 1.73 seconds
Started Jun 02 01:10:12 PM PDT 24
Finished Jun 02 01:10:15 PM PDT 24
Peak memory 219168 kb
Host smart-08c605ce-0726-4526-a422-f2eb81ae3270
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311000
8093 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3110008093
Directory /workspace/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.3340930333
Short name T957
Test name
Test status
Simulation time 569367129 ps
CPU time 3.93 seconds
Started Jun 02 01:10:12 PM PDT 24
Finished Jun 02 01:10:17 PM PDT 24
Peak memory 209756 kb
Host smart-ba82dc06-a8fe-4b30-b872-ab90444ee233
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340930333 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.lc_ctrl_jtag_csr_rw.3340930333
Directory /workspace/2.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.3291942377
Short name T993
Test name
Test status
Simulation time 379833382 ps
CPU time 1.09 seconds
Started Jun 02 01:10:12 PM PDT 24
Finished Jun 02 01:10:14 PM PDT 24
Peak memory 209924 kb
Host smart-e903f514-97fe-4ca0-a59b-cbe28ee73c5a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291942377 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.lc_ctrl_jtag_same_csr_outstanding.3291942377
Directory /workspace/2.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.4240330410
Short name T881
Test name
Test status
Simulation time 44680447 ps
CPU time 1.44 seconds
Started Jun 02 01:10:19 PM PDT 24
Finished Jun 02 01:10:21 PM PDT 24
Peak memory 209940 kb
Host smart-69c67322-1306-45b8-a3d4-17eb06a9cceb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240330410 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl
_same_csr_outstanding.4240330410
Directory /workspace/2.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.4104565957
Short name T121
Test name
Test status
Simulation time 21248658 ps
CPU time 1.62 seconds
Started Jun 02 01:10:10 PM PDT 24
Finished Jun 02 01:10:12 PM PDT 24
Peak memory 218468 kb
Host smart-a24ec476-774c-4229-afc1-b8b99b1799c0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104565957 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_errors.4104565957
Directory /workspace/2.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.3679597016
Short name T967
Test name
Test status
Simulation time 65130869 ps
CPU time 1.35 seconds
Started Jun 02 01:10:27 PM PDT 24
Finished Jun 02 01:10:29 PM PDT 24
Peak memory 217556 kb
Host smart-24e19b82-5a3a-4e4a-9acc-8aad44b329a6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679597016 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_aliasin
g.3679597016
Directory /workspace/3.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.3785051252
Short name T919
Test name
Test status
Simulation time 52822298 ps
CPU time 1.43 seconds
Started Jun 02 01:10:20 PM PDT 24
Finished Jun 02 01:10:21 PM PDT 24
Peak memory 209760 kb
Host smart-15403a52-d5d8-4944-baf8-502a37776938
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785051252 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_bit_bas
h.3785051252
Directory /workspace/3.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.4270003791
Short name T865
Test name
Test status
Simulation time 27551578 ps
CPU time 0.9 seconds
Started Jun 02 01:10:21 PM PDT 24
Finished Jun 02 01:10:22 PM PDT 24
Peak memory 210216 kb
Host smart-7f3a8c72-0212-49ef-b177-36eae29f71c2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270003791 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_hw_rese
t.4270003791
Directory /workspace/3.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.3956144713
Short name T878
Test name
Test status
Simulation time 29965365 ps
CPU time 1.4 seconds
Started Jun 02 01:10:25 PM PDT 24
Finished Jun 02 01:10:26 PM PDT 24
Peak memory 218264 kb
Host smart-0470c6de-8f95-4a44-bce3-2e28717da642
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956144713 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 3.lc_ctrl_csr_mem_rw_with_rand_reset.3956144713
Directory /workspace/3.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.2163096075
Short name T872
Test name
Test status
Simulation time 17412951 ps
CPU time 0.91 seconds
Started Jun 02 01:10:17 PM PDT 24
Finished Jun 02 01:10:18 PM PDT 24
Peak memory 209848 kb
Host smart-544e512b-611f-4f86-9de1-5811af956954
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163096075 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_rw.2163096075
Directory /workspace/3.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.205041955
Short name T871
Test name
Test status
Simulation time 98599465 ps
CPU time 2.05 seconds
Started Jun 02 01:10:20 PM PDT 24
Finished Jun 02 01:10:22 PM PDT 24
Peak memory 217172 kb
Host smart-b1b61336-0276-4df2-922a-e6a9f06023ba
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205041955 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 3.lc_ctrl_jtag_alert_test.205041955
Directory /workspace/3.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.859818322
Short name T138
Test name
Test status
Simulation time 1772588842 ps
CPU time 5.49 seconds
Started Jun 02 01:10:17 PM PDT 24
Finished Jun 02 01:10:22 PM PDT 24
Peak memory 209360 kb
Host smart-04fd1ae3-d31a-4648-bf7c-d8603ba742f3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859818322 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 3.lc_ctrl_jtag_csr_aliasing.859818322
Directory /workspace/3.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.2996903748
Short name T951
Test name
Test status
Simulation time 5922805708 ps
CPU time 33.4 seconds
Started Jun 02 01:10:17 PM PDT 24
Finished Jun 02 01:10:51 PM PDT 24
Peak memory 209860 kb
Host smart-461a23ad-573f-4991-9f7c-fb4de64d4e80
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996903748 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_bit_bash.2996903748
Directory /workspace/3.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.4004132592
Short name T139
Test name
Test status
Simulation time 46939657 ps
CPU time 1.85 seconds
Started Jun 02 01:10:19 PM PDT 24
Finished Jun 02 01:10:22 PM PDT 24
Peak memory 211188 kb
Host smart-903884f1-cc40-43dd-b69d-3726bbcf0a6a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004132592 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_hw_reset.4004132592
Directory /workspace/3.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3169872431
Short name T926
Test name
Test status
Simulation time 616271590 ps
CPU time 2.46 seconds
Started Jun 02 01:10:19 PM PDT 24
Finished Jun 02 01:10:22 PM PDT 24
Peak memory 223456 kb
Host smart-48fe14a8-7271-4d1a-aaf8-6f9440080cd9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316987
2431 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3169872431
Directory /workspace/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.244589023
Short name T895
Test name
Test status
Simulation time 107125609 ps
CPU time 2.05 seconds
Started Jun 02 01:10:20 PM PDT 24
Finished Jun 02 01:10:22 PM PDT 24
Peak memory 209788 kb
Host smart-4b44175d-27bc-43fe-bc7b-9cde9ff02fa9
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244589023 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.lc_ctrl_jtag_csr_rw.244589023
Directory /workspace/3.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.629095764
Short name T990
Test name
Test status
Simulation time 38456015 ps
CPU time 1.36 seconds
Started Jun 02 01:10:18 PM PDT 24
Finished Jun 02 01:10:19 PM PDT 24
Peak memory 217868 kb
Host smart-49376ec8-d944-4721-9263-5487bccb17c3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629095764 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.lc_ctrl_jtag_same_csr_outstanding.629095764
Directory /workspace/3.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.314341033
Short name T916
Test name
Test status
Simulation time 96007313 ps
CPU time 1.01 seconds
Started Jun 02 01:10:25 PM PDT 24
Finished Jun 02 01:10:27 PM PDT 24
Peak memory 209980 kb
Host smart-70a08e53-d58a-4ec1-9920-298dfd8d3908
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314341033 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
same_csr_outstanding.314341033
Directory /workspace/3.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.3314993330
Short name T129
Test name
Test status
Simulation time 118769868 ps
CPU time 1.95 seconds
Started Jun 02 01:10:18 PM PDT 24
Finished Jun 02 01:10:21 PM PDT 24
Peak memory 218128 kb
Host smart-4f1e562e-87a4-47de-bea1-48a1dc67ac75
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314993330 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_errors.3314993330
Directory /workspace/3.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.2250845458
Short name T941
Test name
Test status
Simulation time 33275109 ps
CPU time 1.64 seconds
Started Jun 02 01:10:25 PM PDT 24
Finished Jun 02 01:10:27 PM PDT 24
Peak memory 209860 kb
Host smart-25e7ffc4-7614-405e-9450-8c0486a086cb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250845458 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_aliasin
g.2250845458
Directory /workspace/4.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.3854442583
Short name T964
Test name
Test status
Simulation time 25979281 ps
CPU time 1.88 seconds
Started Jun 02 01:10:26 PM PDT 24
Finished Jun 02 01:10:29 PM PDT 24
Peak memory 217196 kb
Host smart-f3e419c3-4cf8-46db-add3-3a89c485d0bd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854442583 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_bit_bas
h.3854442583
Directory /workspace/4.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.561785206
Short name T182
Test name
Test status
Simulation time 55401017 ps
CPU time 1.08 seconds
Started Jun 02 01:10:25 PM PDT 24
Finished Jun 02 01:10:27 PM PDT 24
Peak memory 210368 kb
Host smart-07d9a889-b148-4b13-bda6-af975e48b262
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561785206 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_hw_reset
.561785206
Directory /workspace/4.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.2562106885
Short name T883
Test name
Test status
Simulation time 30464566 ps
CPU time 1.99 seconds
Started Jun 02 01:10:27 PM PDT 24
Finished Jun 02 01:10:30 PM PDT 24
Peak memory 218196 kb
Host smart-03506dfb-c088-4d59-a366-9bb7710cefe9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562106885 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 4.lc_ctrl_csr_mem_rw_with_rand_reset.2562106885
Directory /workspace/4.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.1820890864
Short name T870
Test name
Test status
Simulation time 19359926 ps
CPU time 1.15 seconds
Started Jun 02 01:10:27 PM PDT 24
Finished Jun 02 01:10:28 PM PDT 24
Peak memory 209532 kb
Host smart-615b743e-3a1a-43af-b9fc-9c2ebc3e4259
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820890864 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_rw.1820890864
Directory /workspace/4.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.3453582746
Short name T952
Test name
Test status
Simulation time 118792956 ps
CPU time 0.96 seconds
Started Jun 02 01:10:26 PM PDT 24
Finished Jun 02 01:10:27 PM PDT 24
Peak memory 209700 kb
Host smart-ba31d45b-abe1-41bb-a87f-117ea2f6630f
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453582746 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.lc_ctrl_jtag_alert_test.3453582746
Directory /workspace/4.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.2338224908
Short name T884
Test name
Test status
Simulation time 3334839795 ps
CPU time 6.81 seconds
Started Jun 02 01:10:26 PM PDT 24
Finished Jun 02 01:10:34 PM PDT 24
Peak memory 209720 kb
Host smart-1c713493-053c-42f3-b50f-7f8d8e50336d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338224908 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_aliasing.2338224908
Directory /workspace/4.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.265891162
Short name T928
Test name
Test status
Simulation time 699475352 ps
CPU time 17.23 seconds
Started Jun 02 01:10:26 PM PDT 24
Finished Jun 02 01:10:43 PM PDT 24
Peak memory 209740 kb
Host smart-3e2be328-b65e-4279-8a66-423b52a313c2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265891162 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 4.lc_ctrl_jtag_csr_bit_bash.265891162
Directory /workspace/4.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.4253152576
Short name T901
Test name
Test status
Simulation time 108919228 ps
CPU time 1.82 seconds
Started Jun 02 01:10:24 PM PDT 24
Finished Jun 02 01:10:26 PM PDT 24
Peak memory 217996 kb
Host smart-02bf7860-48af-4add-8877-c7022cc3e843
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253152576 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_hw_reset.4253152576
Directory /workspace/4.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3741351061
Short name T137
Test name
Test status
Simulation time 232440556 ps
CPU time 2.54 seconds
Started Jun 02 01:10:27 PM PDT 24
Finished Jun 02 01:10:30 PM PDT 24
Peak memory 223032 kb
Host smart-6d9f1d9b-cb8f-469f-bcb1-74c7eddc419b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374135
1061 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3741351061
Directory /workspace/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.1554772497
Short name T979
Test name
Test status
Simulation time 117932290 ps
CPU time 1.3 seconds
Started Jun 02 01:10:26 PM PDT 24
Finished Jun 02 01:10:28 PM PDT 24
Peak memory 209760 kb
Host smart-f49cf4f7-11c7-4272-95d3-da2d7d711216
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554772497 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.lc_ctrl_jtag_csr_rw.1554772497
Directory /workspace/4.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.3698915066
Short name T175
Test name
Test status
Simulation time 22039534 ps
CPU time 1.22 seconds
Started Jun 02 01:10:26 PM PDT 24
Finished Jun 02 01:10:28 PM PDT 24
Peak memory 210028 kb
Host smart-2db0646b-d51e-485f-b5f1-4eeb6ca9bfc8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698915066 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.lc_ctrl_jtag_same_csr_outstanding.3698915066
Directory /workspace/4.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.1338937033
Short name T930
Test name
Test status
Simulation time 64163065 ps
CPU time 1.25 seconds
Started Jun 02 01:10:28 PM PDT 24
Finished Jun 02 01:10:30 PM PDT 24
Peak memory 217808 kb
Host smart-3ea5555b-4085-41b5-9d62-21756de4b65f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338937033 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl
_same_csr_outstanding.1338937033
Directory /workspace/4.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.777442117
Short name T886
Test name
Test status
Simulation time 74578545 ps
CPU time 2.26 seconds
Started Jun 02 01:10:27 PM PDT 24
Finished Jun 02 01:10:29 PM PDT 24
Peak memory 218152 kb
Host smart-b639259e-739c-4f3e-bc39-6f817a35db88
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777442117 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_errors.777442117
Directory /workspace/4.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.1285400103
Short name T882
Test name
Test status
Simulation time 115845385 ps
CPU time 1.1 seconds
Started Jun 02 01:10:31 PM PDT 24
Finished Jun 02 01:10:33 PM PDT 24
Peak memory 219260 kb
Host smart-dd242326-27d3-4ae1-8f09-9ec33af9c04e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285400103 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 5.lc_ctrl_csr_mem_rw_with_rand_reset.1285400103
Directory /workspace/5.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.4008059309
Short name T165
Test name
Test status
Simulation time 38580966 ps
CPU time 0.96 seconds
Started Jun 02 01:10:32 PM PDT 24
Finished Jun 02 01:10:33 PM PDT 24
Peak memory 209644 kb
Host smart-314b6404-86aa-4e0b-bc3c-01fcd14d6df8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008059309 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_csr_rw.4008059309
Directory /workspace/5.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.4236360554
Short name T962
Test name
Test status
Simulation time 31050523 ps
CPU time 1.04 seconds
Started Jun 02 01:10:33 PM PDT 24
Finished Jun 02 01:10:34 PM PDT 24
Peak memory 208984 kb
Host smart-3fb0bc19-cd8b-4fd2-8aaa-88f8fc6ce430
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236360554 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.lc_ctrl_jtag_alert_test.4236360554
Directory /workspace/5.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.1365816254
Short name T873
Test name
Test status
Simulation time 2303390636 ps
CPU time 12.49 seconds
Started Jun 02 01:10:37 PM PDT 24
Finished Jun 02 01:10:49 PM PDT 24
Peak memory 209604 kb
Host smart-e9d229e8-9f6f-437d-9a1a-0f65b2cd85af
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365816254 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_aliasing.1365816254
Directory /workspace/5.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.938020893
Short name T879
Test name
Test status
Simulation time 1804903973 ps
CPU time 20 seconds
Started Jun 02 01:10:38 PM PDT 24
Finished Jun 02 01:10:58 PM PDT 24
Peak memory 209768 kb
Host smart-4debd0a3-b298-48eb-8d96-a29aae542a09
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938020893 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 5.lc_ctrl_jtag_csr_bit_bash.938020893
Directory /workspace/5.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.3871151670
Short name T978
Test name
Test status
Simulation time 98380845 ps
CPU time 1.79 seconds
Started Jun 02 01:10:33 PM PDT 24
Finished Jun 02 01:10:35 PM PDT 24
Peak memory 217960 kb
Host smart-ed6e59dc-83c1-4593-8802-001c240369a6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871151670 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_hw_reset.3871151670
Directory /workspace/5.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.139912477
Short name T934
Test name
Test status
Simulation time 85123411 ps
CPU time 1.96 seconds
Started Jun 02 01:10:31 PM PDT 24
Finished Jun 02 01:10:34 PM PDT 24
Peak memory 219648 kb
Host smart-f977bf01-8d2e-4aff-a6e3-c8f682b6b7ee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139912
477 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.139912477
Directory /workspace/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.4116052952
Short name T907
Test name
Test status
Simulation time 79612179 ps
CPU time 1.37 seconds
Started Jun 02 01:10:36 PM PDT 24
Finished Jun 02 01:10:38 PM PDT 24
Peak memory 218124 kb
Host smart-f5c0af26-4398-4a79-9faa-6d01ec5699b8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116052952 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.lc_ctrl_jtag_same_csr_outstanding.4116052952
Directory /workspace/5.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.2559613746
Short name T174
Test name
Test status
Simulation time 133346295 ps
CPU time 1.36 seconds
Started Jun 02 01:10:34 PM PDT 24
Finished Jun 02 01:10:35 PM PDT 24
Peak memory 209520 kb
Host smart-3195c031-6ae6-483d-b0ab-fa247e0c87cf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559613746 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl
_same_csr_outstanding.2559613746
Directory /workspace/5.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.2379437379
Short name T110
Test name
Test status
Simulation time 514434307 ps
CPU time 3.78 seconds
Started Jun 02 01:10:32 PM PDT 24
Finished Jun 02 01:10:36 PM PDT 24
Peak memory 218128 kb
Host smart-a998ddab-4e16-4ae6-8512-86c9d945f177
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379437379 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_errors.2379437379
Directory /workspace/5.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.3312467687
Short name T960
Test name
Test status
Simulation time 280606008 ps
CPU time 2.16 seconds
Started Jun 02 01:10:33 PM PDT 24
Finished Jun 02 01:10:35 PM PDT 24
Peak memory 221936 kb
Host smart-cce96fd9-fe08-45bd-bee9-8ed734ef7ae2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312467687 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_intg_
err.3312467687
Directory /workspace/5.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.2643893825
Short name T143
Test name
Test status
Simulation time 20758910 ps
CPU time 1.08 seconds
Started Jun 02 01:10:31 PM PDT 24
Finished Jun 02 01:10:33 PM PDT 24
Peak memory 219288 kb
Host smart-8505b961-1d2e-4200-afbf-6031104f1fb4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643893825 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 6.lc_ctrl_csr_mem_rw_with_rand_reset.2643893825
Directory /workspace/6.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.474972446
Short name T936
Test name
Test status
Simulation time 15690669 ps
CPU time 1.04 seconds
Started Jun 02 01:10:31 PM PDT 24
Finished Jun 02 01:10:32 PM PDT 24
Peak memory 210096 kb
Host smart-1260d3b1-b9d2-446c-b6f8-7efcd8efbfe1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474972446 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_csr_rw.474972446
Directory /workspace/6.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.2791480687
Short name T140
Test name
Test status
Simulation time 77659132 ps
CPU time 1.07 seconds
Started Jun 02 01:10:31 PM PDT 24
Finished Jun 02 01:10:33 PM PDT 24
Peak memory 209628 kb
Host smart-1a249dd7-1b92-4541-8b85-ecb8f5173c5c
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791480687 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.lc_ctrl_jtag_alert_test.2791480687
Directory /workspace/6.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.2374039574
Short name T114
Test name
Test status
Simulation time 440191074 ps
CPU time 5.34 seconds
Started Jun 02 01:10:34 PM PDT 24
Finished Jun 02 01:10:40 PM PDT 24
Peak memory 217572 kb
Host smart-78ff34db-e523-4bc7-9790-4b9956593357
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374039574 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_aliasing.2374039574
Directory /workspace/6.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.1410279566
Short name T980
Test name
Test status
Simulation time 1238548393 ps
CPU time 12.51 seconds
Started Jun 02 01:10:33 PM PDT 24
Finished Jun 02 01:10:46 PM PDT 24
Peak memory 209440 kb
Host smart-52149c42-6eb1-41ae-a70f-8f38bd9e2cc0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410279566 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_bit_bash.1410279566
Directory /workspace/6.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.4234074242
Short name T987
Test name
Test status
Simulation time 240497051 ps
CPU time 2.14 seconds
Started Jun 02 01:10:31 PM PDT 24
Finished Jun 02 01:10:33 PM PDT 24
Peak memory 211392 kb
Host smart-f532b094-e9c4-47e2-a831-5621d348dbad
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234074242 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_hw_reset.4234074242
Directory /workspace/6.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3579355121
Short name T966
Test name
Test status
Simulation time 526575891 ps
CPU time 2.27 seconds
Started Jun 02 01:10:32 PM PDT 24
Finished Jun 02 01:10:35 PM PDT 24
Peak memory 221836 kb
Host smart-2745fdec-1043-4aef-8643-4c0d09530a2e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357935
5121 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3579355121
Directory /workspace/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.113068611
Short name T888
Test name
Test status
Simulation time 158051147 ps
CPU time 2.51 seconds
Started Jun 02 01:10:32 PM PDT 24
Finished Jun 02 01:10:34 PM PDT 24
Peak memory 209816 kb
Host smart-6d657d9a-c732-48b8-8e4f-f50a7b2add69
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113068611 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.lc_ctrl_jtag_csr_rw.113068611
Directory /workspace/6.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.1241368324
Short name T906
Test name
Test status
Simulation time 58388647 ps
CPU time 1.76 seconds
Started Jun 02 01:10:31 PM PDT 24
Finished Jun 02 01:10:33 PM PDT 24
Peak memory 209924 kb
Host smart-40576865-83b8-475f-bf06-50a587ce7dc8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241368324 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.lc_ctrl_jtag_same_csr_outstanding.1241368324
Directory /workspace/6.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.3280758154
Short name T909
Test name
Test status
Simulation time 30661234 ps
CPU time 1.17 seconds
Started Jun 02 01:10:35 PM PDT 24
Finished Jun 02 01:10:36 PM PDT 24
Peak memory 209560 kb
Host smart-1a8abe25-0547-425d-8c3b-2d294c5a2ecf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280758154 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl
_same_csr_outstanding.3280758154
Directory /workspace/6.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.2274335790
Short name T981
Test name
Test status
Simulation time 100284792 ps
CPU time 4.04 seconds
Started Jun 02 01:10:31 PM PDT 24
Finished Jun 02 01:10:35 PM PDT 24
Peak memory 218136 kb
Host smart-ff3fff02-6fde-464a-9a2a-a9a7c30c6848
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274335790 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_errors.2274335790
Directory /workspace/6.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.3827176562
Short name T958
Test name
Test status
Simulation time 27185914 ps
CPU time 1.77 seconds
Started Jun 02 01:10:44 PM PDT 24
Finished Jun 02 01:10:46 PM PDT 24
Peak memory 219604 kb
Host smart-dd8696fd-260b-4483-b388-48faac06521a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827176562 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 7.lc_ctrl_csr_mem_rw_with_rand_reset.3827176562
Directory /workspace/7.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.131319378
Short name T970
Test name
Test status
Simulation time 15449501 ps
CPU time 0.91 seconds
Started Jun 02 01:10:39 PM PDT 24
Finished Jun 02 01:10:40 PM PDT 24
Peak memory 209764 kb
Host smart-85de9011-9f39-433b-bf78-2b5d03e66323
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131319378 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_csr_rw.131319378
Directory /workspace/7.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.59172136
Short name T988
Test name
Test status
Simulation time 65809872 ps
CPU time 1.47 seconds
Started Jun 02 01:10:38 PM PDT 24
Finished Jun 02 01:10:40 PM PDT 24
Peak memory 208956 kb
Host smart-2a757ce3-56ac-47b1-900d-05954f592e59
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59172136 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_alert_test.59172136
Directory /workspace/7.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.1449308265
Short name T937
Test name
Test status
Simulation time 731559154 ps
CPU time 11.32 seconds
Started Jun 02 01:10:38 PM PDT 24
Finished Jun 02 01:10:50 PM PDT 24
Peak memory 209532 kb
Host smart-4285dfec-2c49-4669-8b74-e192cdfd5c3c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449308265 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_aliasing.1449308265
Directory /workspace/7.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.2283563497
Short name T947
Test name
Test status
Simulation time 2069197263 ps
CPU time 43.75 seconds
Started Jun 02 01:10:42 PM PDT 24
Finished Jun 02 01:11:26 PM PDT 24
Peak memory 209512 kb
Host smart-0a1b8f6f-a267-4a14-b62a-d75b918b1fe9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283563497 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_bit_bash.2283563497
Directory /workspace/7.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.1795289927
Short name T961
Test name
Test status
Simulation time 122360454 ps
CPU time 1.29 seconds
Started Jun 02 01:10:38 PM PDT 24
Finished Jun 02 01:10:40 PM PDT 24
Peak memory 217276 kb
Host smart-e352deac-d478-4613-8717-6e07b9c27bf3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795289927 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_hw_reset.1795289927
Directory /workspace/7.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3888501246
Short name T145
Test name
Test status
Simulation time 345693272 ps
CPU time 2.75 seconds
Started Jun 02 01:10:42 PM PDT 24
Finished Jun 02 01:10:45 PM PDT 24
Peak memory 218232 kb
Host smart-6b039f3b-b588-44e5-8359-542eda59c0af
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388850
1246 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3888501246
Directory /workspace/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.164526223
Short name T982
Test name
Test status
Simulation time 728816821 ps
CPU time 1.51 seconds
Started Jun 02 01:10:34 PM PDT 24
Finished Jun 02 01:10:36 PM PDT 24
Peak memory 209696 kb
Host smart-e8d91cb6-4a2d-4e44-af50-4b147f220b31
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164526223 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.lc_ctrl_jtag_csr_rw.164526223
Directory /workspace/7.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.1908975165
Short name T950
Test name
Test status
Simulation time 99312548 ps
CPU time 1.51 seconds
Started Jun 02 01:10:39 PM PDT 24
Finished Jun 02 01:10:41 PM PDT 24
Peak memory 211816 kb
Host smart-5d7463d6-96d4-4c3a-94e0-2399d16dbfa5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908975165 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.lc_ctrl_jtag_same_csr_outstanding.1908975165
Directory /workspace/7.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.2705002901
Short name T955
Test name
Test status
Simulation time 16131069 ps
CPU time 1.15 seconds
Started Jun 02 01:10:48 PM PDT 24
Finished Jun 02 01:10:49 PM PDT 24
Peak memory 209680 kb
Host smart-bacfdcbe-c68a-436e-bf4d-7eac745e3241
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705002901 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl
_same_csr_outstanding.2705002901
Directory /workspace/7.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.1858389224
Short name T898
Test name
Test status
Simulation time 48590162 ps
CPU time 1.9 seconds
Started Jun 02 01:10:39 PM PDT 24
Finished Jun 02 01:10:42 PM PDT 24
Peak memory 219208 kb
Host smart-a15c5d07-5949-4b55-ac26-a89e53942139
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858389224 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_errors.1858389224
Directory /workspace/7.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.759220223
Short name T927
Test name
Test status
Simulation time 97752316 ps
CPU time 1.87 seconds
Started Jun 02 01:10:45 PM PDT 24
Finished Jun 02 01:10:47 PM PDT 24
Peak memory 223092 kb
Host smart-176361f0-760e-41c1-83d1-1d319a9d666b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759220223 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 8.lc_ctrl_csr_mem_rw_with_rand_reset.759220223
Directory /workspace/8.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.1898162399
Short name T885
Test name
Test status
Simulation time 94100908 ps
CPU time 0.92 seconds
Started Jun 02 01:10:46 PM PDT 24
Finished Jun 02 01:10:47 PM PDT 24
Peak memory 209884 kb
Host smart-03c3e190-30d2-42f4-82b7-f1662c227da8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898162399 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_csr_rw.1898162399
Directory /workspace/8.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.1045105271
Short name T892
Test name
Test status
Simulation time 66064663 ps
CPU time 1.07 seconds
Started Jun 02 01:10:47 PM PDT 24
Finished Jun 02 01:10:48 PM PDT 24
Peak memory 209752 kb
Host smart-267ef0bf-ae85-4d32-a726-e070e6419d46
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045105271 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.lc_ctrl_jtag_alert_test.1045105271
Directory /workspace/8.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.2854580266
Short name T867
Test name
Test status
Simulation time 2829169960 ps
CPU time 13.6 seconds
Started Jun 02 01:10:45 PM PDT 24
Finished Jun 02 01:11:00 PM PDT 24
Peak memory 209724 kb
Host smart-3b74311f-444e-4096-9e8d-73c234a1397f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854580266 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_aliasing.2854580266
Directory /workspace/8.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.2587623350
Short name T913
Test name
Test status
Simulation time 352878847 ps
CPU time 9.37 seconds
Started Jun 02 01:10:47 PM PDT 24
Finished Jun 02 01:10:56 PM PDT 24
Peak memory 209496 kb
Host smart-d7412c8e-4d1e-42f9-ba03-1a7e23671246
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587623350 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_bit_bash.2587623350
Directory /workspace/8.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.3767403349
Short name T963
Test name
Test status
Simulation time 122188561 ps
CPU time 3.51 seconds
Started Jun 02 01:10:47 PM PDT 24
Finished Jun 02 01:10:51 PM PDT 24
Peak memory 211412 kb
Host smart-672da663-666d-4f46-9014-a246991629ec
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767403349 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_hw_reset.3767403349
Directory /workspace/8.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2498911778
Short name T994
Test name
Test status
Simulation time 147558247 ps
CPU time 4.5 seconds
Started Jun 02 01:10:46 PM PDT 24
Finished Jun 02 01:10:51 PM PDT 24
Peak memory 218132 kb
Host smart-cab85ad2-2346-4eaf-9639-7e288e6a272b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249891
1778 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2498911778
Directory /workspace/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.137744257
Short name T946
Test name
Test status
Simulation time 111218861 ps
CPU time 3.3 seconds
Started Jun 02 01:10:46 PM PDT 24
Finished Jun 02 01:10:50 PM PDT 24
Peak memory 209792 kb
Host smart-a04a7c06-4ba5-4be4-9eb8-53af17e6e998
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137744257 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.lc_ctrl_jtag_csr_rw.137744257
Directory /workspace/8.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.2651407267
Short name T894
Test name
Test status
Simulation time 48370801 ps
CPU time 1.01 seconds
Started Jun 02 01:10:46 PM PDT 24
Finished Jun 02 01:10:47 PM PDT 24
Peak memory 209924 kb
Host smart-db707b2d-262f-4bc7-9395-5f5c93f0a9da
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651407267 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.lc_ctrl_jtag_same_csr_outstanding.2651407267
Directory /workspace/8.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.353124566
Short name T917
Test name
Test status
Simulation time 23481224 ps
CPU time 1.5 seconds
Started Jun 02 01:10:46 PM PDT 24
Finished Jun 02 01:10:48 PM PDT 24
Peak memory 218052 kb
Host smart-0f5d5fad-d313-44eb-ba02-2649d1184ad0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353124566 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
same_csr_outstanding.353124566
Directory /workspace/8.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.3519397794
Short name T944
Test name
Test status
Simulation time 117614893 ps
CPU time 3.22 seconds
Started Jun 02 01:10:47 PM PDT 24
Finished Jun 02 01:10:50 PM PDT 24
Peak memory 218284 kb
Host smart-18dcf1ec-bc1b-4e98-8ddf-0e2e02ef1f1a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519397794 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_errors.3519397794
Directory /workspace/8.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.96892779
Short name T132
Test name
Test status
Simulation time 91200208 ps
CPU time 3.21 seconds
Started Jun 02 01:10:45 PM PDT 24
Finished Jun 02 01:10:49 PM PDT 24
Peak memory 218128 kb
Host smart-00d6708b-7fab-461e-b1f7-a986a63cbf80
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96892779 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_intg_er
r.96892779
Directory /workspace/8.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.3511995807
Short name T923
Test name
Test status
Simulation time 42347520 ps
CPU time 1.41 seconds
Started Jun 02 01:10:53 PM PDT 24
Finished Jun 02 01:10:55 PM PDT 24
Peak memory 218268 kb
Host smart-17aca2fc-bd94-4fce-a75a-0cf087a811dc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511995807 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 9.lc_ctrl_csr_mem_rw_with_rand_reset.3511995807
Directory /workspace/9.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.3290689521
Short name T989
Test name
Test status
Simulation time 34517888 ps
CPU time 0.92 seconds
Started Jun 02 01:10:59 PM PDT 24
Finished Jun 02 01:11:00 PM PDT 24
Peak memory 209796 kb
Host smart-7e987eee-1360-4c2e-9cc4-75f7ee3906b8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290689521 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_csr_rw.3290689521
Directory /workspace/9.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.2505847758
Short name T973
Test name
Test status
Simulation time 186322863 ps
CPU time 1.72 seconds
Started Jun 02 01:10:54 PM PDT 24
Finished Jun 02 01:10:56 PM PDT 24
Peak memory 208912 kb
Host smart-43c8c5eb-511c-4b15-b43c-62d0e6f0bfa4
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505847758 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.lc_ctrl_jtag_alert_test.2505847758
Directory /workspace/9.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.1374387165
Short name T929
Test name
Test status
Simulation time 372422414 ps
CPU time 8.88 seconds
Started Jun 02 01:10:52 PM PDT 24
Finished Jun 02 01:11:02 PM PDT 24
Peak memory 217136 kb
Host smart-b2635714-8f3b-4820-9967-e0e0e05906e7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374387165 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_aliasing.1374387165
Directory /workspace/9.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.4242817448
Short name T938
Test name
Test status
Simulation time 1098870549 ps
CPU time 17.56 seconds
Started Jun 02 01:10:50 PM PDT 24
Finished Jun 02 01:11:09 PM PDT 24
Peak memory 209528 kb
Host smart-83883493-bf3c-4b11-8e3f-006b6477e129
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242817448 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_bit_bash.4242817448
Directory /workspace/9.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.2816134782
Short name T915
Test name
Test status
Simulation time 207063266 ps
CPU time 5.07 seconds
Started Jun 02 01:10:50 PM PDT 24
Finished Jun 02 01:10:56 PM PDT 24
Peak memory 211416 kb
Host smart-c3f11507-bbf7-485f-9230-fd2a1fef2b0f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816134782 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_hw_reset.2816134782
Directory /workspace/9.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4221667748
Short name T948
Test name
Test status
Simulation time 49530958 ps
CPU time 1.5 seconds
Started Jun 02 01:10:51 PM PDT 24
Finished Jun 02 01:10:53 PM PDT 24
Peak memory 218260 kb
Host smart-7af9a635-17db-4580-ae17-7926cf153f83
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422166
7748 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4221667748
Directory /workspace/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.3754879137
Short name T921
Test name
Test status
Simulation time 211527755 ps
CPU time 1.38 seconds
Started Jun 02 01:10:54 PM PDT 24
Finished Jun 02 01:10:56 PM PDT 24
Peak memory 209836 kb
Host smart-1858fc33-0f5f-4972-83c6-4e5e00f815a6
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754879137 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.lc_ctrl_jtag_csr_rw.3754879137
Directory /workspace/9.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.3613037549
Short name T111
Test name
Test status
Simulation time 19433101 ps
CPU time 1.41 seconds
Started Jun 02 01:10:54 PM PDT 24
Finished Jun 02 01:10:56 PM PDT 24
Peak memory 217924 kb
Host smart-bf922d75-1de0-4532-b3e4-92f7b3ffea47
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613037549 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.lc_ctrl_jtag_same_csr_outstanding.3613037549
Directory /workspace/9.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.551744796
Short name T933
Test name
Test status
Simulation time 16564084 ps
CPU time 1.11 seconds
Started Jun 02 01:10:51 PM PDT 24
Finished Jun 02 01:10:53 PM PDT 24
Peak memory 209908 kb
Host smart-266a5fa6-0fc2-4808-9d23-7f26940e1fc3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551744796 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
same_csr_outstanding.551744796
Directory /workspace/9.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.1480116815
Short name T109
Test name
Test status
Simulation time 22015126 ps
CPU time 1.71 seconds
Started Jun 02 01:10:52 PM PDT 24
Finished Jun 02 01:10:54 PM PDT 24
Peak memory 219132 kb
Host smart-a4252a2b-6567-4fec-a5c0-d7a3a4c99bfd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480116815 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_errors.1480116815
Directory /workspace/9.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.2499258492
Short name T130
Test name
Test status
Simulation time 515429134 ps
CPU time 4.51 seconds
Started Jun 02 01:10:53 PM PDT 24
Finished Jun 02 01:10:58 PM PDT 24
Peak memory 218180 kb
Host smart-0fbad926-6c8d-424d-88c7-bde8d673633f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499258492 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_intg_
err.2499258492
Directory /workspace/9.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_alert_test.3331868441
Short name T840
Test name
Test status
Simulation time 21210519 ps
CPU time 1.02 seconds
Started Jun 02 01:23:47 PM PDT 24
Finished Jun 02 01:23:48 PM PDT 24
Peak memory 209512 kb
Host smart-c4fc5809-9e18-4c95-a5c1-b973301f5ee6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331868441 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_alert_test.3331868441
Directory /workspace/0.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.lc_ctrl_errors.4274911515
Short name T823
Test name
Test status
Simulation time 401231966 ps
CPU time 11.1 seconds
Started Jun 02 01:23:41 PM PDT 24
Finished Jun 02 01:23:52 PM PDT 24
Peak memory 217964 kb
Host smart-4e9ab704-49e1-4804-80e9-a60415051cd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274911515 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_errors.4274911515
Directory /workspace/0.lc_ctrl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_access.3101558214
Short name T327
Test name
Test status
Simulation time 1333235653 ps
CPU time 9.28 seconds
Started Jun 02 01:23:44 PM PDT 24
Finished Jun 02 01:23:53 PM PDT 24
Peak memory 209764 kb
Host smart-4778ab94-46b9-4f70-8515-3da204a62b35
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101558214 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_access.3101558214
Directory /workspace/0.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_errors.19634447
Short name T64
Test name
Test status
Simulation time 20377987402 ps
CPU time 60.59 seconds
Started Jun 02 01:23:42 PM PDT 24
Finished Jun 02 01:24:43 PM PDT 24
Peak memory 219328 kb
Host smart-fb6fdf97-910c-4978-9424-52b1b50a902e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19634447 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_l
c_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_erro
rs.19634447
Directory /workspace/0.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_priority.1712865385
Short name T858
Test name
Test status
Simulation time 537472207 ps
CPU time 7.12 seconds
Started Jun 02 01:23:42 PM PDT 24
Finished Jun 02 01:23:50 PM PDT 24
Peak memory 217812 kb
Host smart-8065d94c-8f35-4c95-93fd-ff6f7f47ef7a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712865385 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_priority.1
712865385
Directory /workspace/0.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_prog_failure.3367408817
Short name T214
Test name
Test status
Simulation time 456578592 ps
CPU time 7.45 seconds
Started Jun 02 01:23:41 PM PDT 24
Finished Jun 02 01:23:49 PM PDT 24
Peak memory 218024 kb
Host smart-43fc12e0-c812-4f7c-8c63-f74ae33f049f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367408817 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag
_prog_failure.3367408817
Directory /workspace/0.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_regwen_during_op.2773032646
Short name T529
Test name
Test status
Simulation time 912857588 ps
CPU time 14.44 seconds
Started Jun 02 01:23:43 PM PDT 24
Finished Jun 02 01:23:57 PM PDT 24
Peak memory 217664 kb
Host smart-f4da46d8-15c3-4fd4-aa8a-66fff88699aa
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773032646 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_regwen_during_op.2773032646
Directory /workspace/0.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_smoke.3235520282
Short name T308
Test name
Test status
Simulation time 428940678 ps
CPU time 2.45 seconds
Started Jun 02 01:23:41 PM PDT 24
Finished Jun 02 01:23:44 PM PDT 24
Peak memory 217664 kb
Host smart-528693a8-f65f-4717-b0eb-ab6ab72bc254
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235520282 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_smoke.
3235520282
Directory /workspace/0.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_failure.1746806618
Short name T332
Test name
Test status
Simulation time 1698813090 ps
CPU time 47.03 seconds
Started Jun 02 01:23:43 PM PDT 24
Finished Jun 02 01:24:30 PM PDT 24
Peak memory 276360 kb
Host smart-eca6d22f-91b8-4e8e-82a8-9cb1dff8000e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746806618 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jta
g_state_failure.1746806618
Directory /workspace/0.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_post_trans.500098444
Short name T157
Test name
Test status
Simulation time 487700548 ps
CPU time 6.13 seconds
Started Jun 02 01:23:41 PM PDT 24
Finished Jun 02 01:23:48 PM PDT 24
Peak memory 222924 kb
Host smart-a523472f-3c4f-4260-aadf-164d57ebbf73
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500098444 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_j
tag_state_post_trans.500098444
Directory /workspace/0.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_prog_failure.1349183156
Short name T780
Test name
Test status
Simulation time 415433992 ps
CPU time 4.66 seconds
Started Jun 02 01:23:42 PM PDT 24
Finished Jun 02 01:23:47 PM PDT 24
Peak memory 218024 kb
Host smart-d78ca741-707e-462a-a1d9-658c80b285be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349183156 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_prog_failure.1349183156
Directory /workspace/0.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_regwen_during_op.1090441619
Short name T776
Test name
Test status
Simulation time 405731485 ps
CPU time 20.67 seconds
Started Jun 02 01:23:44 PM PDT 24
Finished Jun 02 01:24:05 PM PDT 24
Peak memory 214808 kb
Host smart-5e443367-b496-495f-9d49-f93b9855c80a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090441619 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_regwen_during_op.1090441619
Directory /workspace/0.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_cm.2308649614
Short name T86
Test name
Test status
Simulation time 823637444 ps
CPU time 22.25 seconds
Started Jun 02 01:23:48 PM PDT 24
Finished Jun 02 01:24:10 PM PDT 24
Peak memory 268684 kb
Host smart-a522072e-dbff-41c1-a841-ce8d71ce3e21
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308649614 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_cm.2308649614
Directory /workspace/0.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_mubi.2922444246
Short name T209
Test name
Test status
Simulation time 282612522 ps
CPU time 14.76 seconds
Started Jun 02 01:23:41 PM PDT 24
Finished Jun 02 01:23:56 PM PDT 24
Peak memory 225764 kb
Host smart-d2b061b1-f184-45c2-8248-0a99da91c657
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922444246 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_mubi.2922444246
Directory /workspace/0.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_digest.2850471282
Short name T272
Test name
Test status
Simulation time 308071794 ps
CPU time 13.13 seconds
Started Jun 02 01:23:43 PM PDT 24
Finished Jun 02 01:23:56 PM PDT 24
Peak memory 226032 kb
Host smart-42b0e8a8-3a39-45c9-8fcf-f712ee4bc346
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850471282 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_di
gest.2850471282
Directory /workspace/0.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_mux.2404000429
Short name T707
Test name
Test status
Simulation time 1217544603 ps
CPU time 14.03 seconds
Started Jun 02 01:23:41 PM PDT 24
Finished Jun 02 01:23:56 PM PDT 24
Peak memory 218036 kb
Host smart-c2f0ba1a-2258-448f-907a-e125637c9d77
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404000429 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_mux.2
404000429
Directory /workspace/0.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/0.lc_ctrl_security_escalation.3671594508
Short name T57
Test name
Test status
Simulation time 249311990 ps
CPU time 9.62 seconds
Started Jun 02 01:23:42 PM PDT 24
Finished Jun 02 01:23:52 PM PDT 24
Peak memory 224216 kb
Host smart-dbb285f0-b42f-4bb6-8a3d-b20ce6cd4be6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671594508 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_security_escalation.3671594508
Directory /workspace/0.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/0.lc_ctrl_smoke.330683863
Short name T701
Test name
Test status
Simulation time 99189688 ps
CPU time 1.72 seconds
Started Jun 02 01:23:41 PM PDT 24
Finished Jun 02 01:23:43 PM PDT 24
Peak memory 217756 kb
Host smart-c20a0fa7-8659-4508-9919-5fbf7152b6dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330683863 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_smoke.330683863
Directory /workspace/0.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_failure.1510070688
Short name T771
Test name
Test status
Simulation time 248700029 ps
CPU time 18.26 seconds
Started Jun 02 01:23:40 PM PDT 24
Finished Jun 02 01:23:59 PM PDT 24
Peak memory 251012 kb
Host smart-6b7afe68-674b-4dff-8bc6-37388599966c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510070688 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_failure.1510070688
Directory /workspace/0.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_post_trans.4169816849
Short name T480
Test name
Test status
Simulation time 363767816 ps
CPU time 7.37 seconds
Started Jun 02 01:23:43 PM PDT 24
Finished Jun 02 01:23:51 PM PDT 24
Peak memory 251220 kb
Host smart-472698c0-cd7c-4a81-beab-a3752ba14c68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169816849 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_post_trans.4169816849
Directory /workspace/0.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all.1797579423
Short name T79
Test name
Test status
Simulation time 24808124131 ps
CPU time 74.61 seconds
Started Jun 02 01:23:47 PM PDT 24
Finished Jun 02 01:25:02 PM PDT 24
Peak memory 251040 kb
Host smart-fd494269-406d-4a2d-958e-c357bddcaa18
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797579423 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.lc_ctrl_stress_all.1797579423
Directory /workspace/0.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.lc_ctrl_volatile_unlock_smoke.4201196328
Short name T404
Test name
Test status
Simulation time 12622911 ps
CPU time 0.97 seconds
Started Jun 02 01:23:40 PM PDT 24
Finished Jun 02 01:23:41 PM PDT 24
Peak memory 211588 kb
Host smart-c20f1aed-3462-4915-a546-7be379ae426b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201196328 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ct
rl_volatile_unlock_smoke.4201196328
Directory /workspace/0.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_alert_test.4199653876
Short name T498
Test name
Test status
Simulation time 17859273 ps
CPU time 1.12 seconds
Started Jun 02 01:23:54 PM PDT 24
Finished Jun 02 01:23:56 PM PDT 24
Peak memory 209476 kb
Host smart-ca5ac8be-3d24-471f-8d0c-5e66ca5fd22d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199653876 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_alert_test.4199653876
Directory /workspace/1.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.lc_ctrl_claim_transition_if.1268066836
Short name T413
Test name
Test status
Simulation time 45102569 ps
CPU time 0.82 seconds
Started Jun 02 01:23:46 PM PDT 24
Finished Jun 02 01:23:47 PM PDT 24
Peak memory 208676 kb
Host smart-6ececea7-6c9f-4391-bf8c-f03dd368cacf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268066836 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_claim_transition_if.1268066836
Directory /workspace/1.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/1.lc_ctrl_errors.184786010
Short name T349
Test name
Test status
Simulation time 775596462 ps
CPU time 12.46 seconds
Started Jun 02 01:23:47 PM PDT 24
Finished Jun 02 01:23:59 PM PDT 24
Peak memory 217940 kb
Host smart-9c6d6e7a-04cf-425a-b07e-686ea02e85f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184786010 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_errors.184786010
Directory /workspace/1.lc_ctrl_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_access.17781829
Short name T478
Test name
Test status
Simulation time 851157305 ps
CPU time 8.15 seconds
Started Jun 02 01:23:55 PM PDT 24
Finished Jun 02 01:24:04 PM PDT 24
Peak memory 209468 kb
Host smart-041c227f-c5d0-44db-a05c-640ba01b3964
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17781829 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_access.17781829
Directory /workspace/1.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_errors.1629871326
Short name T409
Test name
Test status
Simulation time 1727921482 ps
CPU time 49.77 seconds
Started Jun 02 01:23:54 PM PDT 24
Finished Jun 02 01:24:44 PM PDT 24
Peak memory 217948 kb
Host smart-e5e1081d-82b5-44ee-bb76-9ee0156a9b95
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629871326 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_er
rors.1629871326
Directory /workspace/1.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_priority.3395190402
Short name T578
Test name
Test status
Simulation time 849608009 ps
CPU time 3.44 seconds
Started Jun 02 01:23:52 PM PDT 24
Finished Jun 02 01:23:56 PM PDT 24
Peak memory 217284 kb
Host smart-9e829b59-92ec-4a74-946a-2cd2763f2ca7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395190402 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_priority.3
395190402
Directory /workspace/1.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_prog_failure.2331700124
Short name T280
Test name
Test status
Simulation time 666570701 ps
CPU time 6.17 seconds
Started Jun 02 01:23:54 PM PDT 24
Finished Jun 02 01:24:00 PM PDT 24
Peak memory 217944 kb
Host smart-c64e26be-7422-4b32-ac45-d3e7faa2a208
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331700124 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag
_prog_failure.2331700124
Directory /workspace/1.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_regwen_during_op.801909985
Short name T816
Test name
Test status
Simulation time 1041256579 ps
CPU time 31.26 seconds
Started Jun 02 01:23:55 PM PDT 24
Finished Jun 02 01:24:27 PM PDT 24
Peak memory 217608 kb
Host smart-5e71f68a-591f-4b17-b8e7-27b47a6a5082
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801909985 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_j
tag_regwen_during_op.801909985
Directory /workspace/1.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_smoke.642689024
Short name T75
Test name
Test status
Simulation time 602534065 ps
CPU time 7.27 seconds
Started Jun 02 01:23:47 PM PDT 24
Finished Jun 02 01:23:55 PM PDT 24
Peak memory 217780 kb
Host smart-f5ac054c-6c9f-4683-a2cb-b889db30bf22
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642689024 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_smoke.642689024
Directory /workspace/1.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_failure.4067677064
Short name T6
Test name
Test status
Simulation time 1808855498 ps
CPU time 31.68 seconds
Started Jun 02 01:23:48 PM PDT 24
Finished Jun 02 01:24:20 PM PDT 24
Peak memory 251680 kb
Host smart-79107d45-2dc9-422a-87cc-90290e0148f5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067677064 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jta
g_state_failure.4067677064
Directory /workspace/1.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_post_trans.542962414
Short name T664
Test name
Test status
Simulation time 813312837 ps
CPU time 15.77 seconds
Started Jun 02 01:23:48 PM PDT 24
Finished Jun 02 01:24:04 PM PDT 24
Peak memory 246508 kb
Host smart-e9571fcb-4a0f-4454-88c6-6db2af59120d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542962414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_j
tag_state_post_trans.542962414
Directory /workspace/1.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_prog_failure.2956346059
Short name T549
Test name
Test status
Simulation time 266119159 ps
CPU time 2.23 seconds
Started Jun 02 01:23:47 PM PDT 24
Finished Jun 02 01:23:49 PM PDT 24
Peak memory 218116 kb
Host smart-b8909e4b-c8f4-47c9-85dc-917f62105b1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956346059 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_prog_failure.2956346059
Directory /workspace/1.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_regwen_during_op.149062078
Short name T717
Test name
Test status
Simulation time 3326042988 ps
CPU time 12.71 seconds
Started Jun 02 01:23:48 PM PDT 24
Finished Jun 02 01:24:01 PM PDT 24
Peak memory 217780 kb
Host smart-7a400c44-42c4-42aa-afae-217fb5f62ca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149062078 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_regwen_during_op.149062078
Directory /workspace/1.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_cm.3488813140
Short name T87
Test name
Test status
Simulation time 108369170 ps
CPU time 23.24 seconds
Started Jun 02 01:23:54 PM PDT 24
Finished Jun 02 01:24:18 PM PDT 24
Peak memory 267912 kb
Host smart-cdc44e79-ef08-497a-a403-d7b046c15f2c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488813140 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_cm.3488813140
Directory /workspace/1.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_mubi.2521343557
Short name T527
Test name
Test status
Simulation time 1657645855 ps
CPU time 14.55 seconds
Started Jun 02 01:23:54 PM PDT 24
Finished Jun 02 01:24:09 PM PDT 24
Peak memory 218968 kb
Host smart-ba87dfb4-eeb3-46d3-9beb-d06b3cb3a067
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521343557 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_mubi.2521343557
Directory /workspace/1.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_digest.1013067479
Short name T197
Test name
Test status
Simulation time 899384773 ps
CPU time 9.85 seconds
Started Jun 02 01:23:54 PM PDT 24
Finished Jun 02 01:24:04 PM PDT 24
Peak memory 226028 kb
Host smart-f7c8f484-3f59-4237-99bd-9dc6aff9f586
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013067479 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_di
gest.1013067479
Directory /workspace/1.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_mux.2723403615
Short name T703
Test name
Test status
Simulation time 394237329 ps
CPU time 9.91 seconds
Started Jun 02 01:23:54 PM PDT 24
Finished Jun 02 01:24:04 PM PDT 24
Peak memory 218028 kb
Host smart-4afc186b-e6d0-4105-9e2d-b46b71b48acc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723403615 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_mux.2
723403615
Directory /workspace/1.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/1.lc_ctrl_security_escalation.1646085769
Short name T94
Test name
Test status
Simulation time 306507829 ps
CPU time 7.42 seconds
Started Jun 02 01:23:47 PM PDT 24
Finished Jun 02 01:23:55 PM PDT 24
Peak memory 218072 kb
Host smart-9f456b1d-60b8-4d24-b6e2-cf5d34e35aff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646085769 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_security_escalation.1646085769
Directory /workspace/1.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/1.lc_ctrl_smoke.2783277700
Short name T97
Test name
Test status
Simulation time 64618042 ps
CPU time 4.34 seconds
Started Jun 02 01:23:49 PM PDT 24
Finished Jun 02 01:23:54 PM PDT 24
Peak memory 217740 kb
Host smart-8ac37356-1501-4651-86b0-1c3743b19d74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783277700 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_smoke.2783277700
Directory /workspace/1.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_failure.4081833079
Short name T522
Test name
Test status
Simulation time 319339099 ps
CPU time 22.53 seconds
Started Jun 02 01:23:48 PM PDT 24
Finished Jun 02 01:24:11 PM PDT 24
Peak memory 250812 kb
Host smart-99df8637-bd44-48a8-9c34-0671296ccd03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081833079 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_failure.4081833079
Directory /workspace/1.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_post_trans.1831807305
Short name T233
Test name
Test status
Simulation time 503911351 ps
CPU time 6.19 seconds
Started Jun 02 01:23:46 PM PDT 24
Finished Jun 02 01:23:53 PM PDT 24
Peak memory 250576 kb
Host smart-861ef2cd-8516-4ce5-8bbd-c1ced35d2293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831807305 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_post_trans.1831807305
Directory /workspace/1.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_stress_all.821060341
Short name T733
Test name
Test status
Simulation time 9585709105 ps
CPU time 188.53 seconds
Started Jun 02 01:23:54 PM PDT 24
Finished Jun 02 01:27:04 PM PDT 24
Peak memory 274540 kb
Host smart-9b1576a6-26df-4436-a945-d5aba13fbbe8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821060341 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.lc_ctrl_stress_all.821060341
Directory /workspace/1.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.lc_ctrl_stress_all_with_rand_reset.2842085884
Short name T179
Test name
Test status
Simulation time 30868064079 ps
CPU time 662.48 seconds
Started Jun 02 01:23:54 PM PDT 24
Finished Jun 02 01:34:58 PM PDT 24
Peak memory 513352 kb
Host smart-7577336c-3e8e-4a46-8d63-30cb95715418
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2842085884 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_stress_all_with_rand_reset.2842085884
Directory /workspace/1.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.lc_ctrl_volatile_unlock_smoke.2993394892
Short name T517
Test name
Test status
Simulation time 43651627 ps
CPU time 0.77 seconds
Started Jun 02 01:23:46 PM PDT 24
Finished Jun 02 01:23:47 PM PDT 24
Peak memory 208308 kb
Host smart-572f4e02-f26e-466e-9b41-4a464a8a1f68
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993394892 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ct
rl_volatile_unlock_smoke.2993394892
Directory /workspace/1.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_alert_test.2934883750
Short name T595
Test name
Test status
Simulation time 21160730 ps
CPU time 1.2 seconds
Started Jun 02 01:24:51 PM PDT 24
Finished Jun 02 01:24:52 PM PDT 24
Peak memory 208704 kb
Host smart-3c6de694-f966-4b8d-875c-5a3bbad2583f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934883750 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_alert_test.2934883750
Directory /workspace/10.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.lc_ctrl_errors.238059159
Short name T418
Test name
Test status
Simulation time 1404401520 ps
CPU time 11.6 seconds
Started Jun 02 01:24:51 PM PDT 24
Finished Jun 02 01:25:03 PM PDT 24
Peak memory 217888 kb
Host smart-57b8647f-867f-4a2b-8f5a-9408037d15a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238059159 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_errors.238059159
Directory /workspace/10.lc_ctrl_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_access.1990640714
Short name T30
Test name
Test status
Simulation time 1328820462 ps
CPU time 6.45 seconds
Started Jun 02 01:24:54 PM PDT 24
Finished Jun 02 01:25:00 PM PDT 24
Peak memory 216976 kb
Host smart-d7a5dfdd-81e5-44a3-9763-4c7774723c2b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990640714 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_access.1990640714
Directory /workspace/10.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_errors.762088920
Short name T624
Test name
Test status
Simulation time 1847978495 ps
CPU time 28.97 seconds
Started Jun 02 01:24:50 PM PDT 24
Finished Jun 02 01:25:20 PM PDT 24
Peak memory 217956 kb
Host smart-1c6a4477-3396-4bda-b163-61c55a064540
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762088920 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_er
rors.762088920
Directory /workspace/10.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_prog_failure.2518542068
Short name T843
Test name
Test status
Simulation time 2448469408 ps
CPU time 6.48 seconds
Started Jun 02 01:24:54 PM PDT 24
Finished Jun 02 01:25:01 PM PDT 24
Peak memory 218024 kb
Host smart-b2106410-87ed-47bd-ae3a-f4e0949bdc10
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518542068 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jta
g_prog_failure.2518542068
Directory /workspace/10.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_smoke.3907052876
Short name T359
Test name
Test status
Simulation time 284423259 ps
CPU time 4.63 seconds
Started Jun 02 01:24:51 PM PDT 24
Finished Jun 02 01:24:56 PM PDT 24
Peak memory 217656 kb
Host smart-6596175c-8180-4917-ae16-c0502065021f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907052876 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_smoke
.3907052876
Directory /workspace/10.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_failure.2146707424
Short name T807
Test name
Test status
Simulation time 2125468388 ps
CPU time 42.13 seconds
Started Jun 02 01:24:50 PM PDT 24
Finished Jun 02 01:25:33 PM PDT 24
Peak memory 251808 kb
Host smart-02e1184f-1370-47b2-8c2a-0ffcae60ed1c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146707424 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jt
ag_state_failure.2146707424
Directory /workspace/10.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_prog_failure.4097072733
Short name T363
Test name
Test status
Simulation time 249522576 ps
CPU time 3.26 seconds
Started Jun 02 01:24:45 PM PDT 24
Finished Jun 02 01:24:48 PM PDT 24
Peak memory 217992 kb
Host smart-3964c0f9-923a-4571-a0cb-71b5b2804cb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097072733 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_prog_failure.4097072733
Directory /workspace/10.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_mubi.3146838941
Short name T335
Test name
Test status
Simulation time 564350961 ps
CPU time 16.52 seconds
Started Jun 02 01:24:53 PM PDT 24
Finished Jun 02 01:25:10 PM PDT 24
Peak memory 226024 kb
Host smart-e496577a-4736-4706-aca8-afe9503ef4bc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146838941 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_mubi.3146838941
Directory /workspace/10.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_digest.3703038548
Short name T348
Test name
Test status
Simulation time 397879384 ps
CPU time 15.96 seconds
Started Jun 02 01:24:53 PM PDT 24
Finished Jun 02 01:25:09 PM PDT 24
Peak memory 217900 kb
Host smart-616c4710-c86d-4535-8f63-adf3a9e28b41
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703038548 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_d
igest.3703038548
Directory /workspace/10.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_mux.1247965157
Short name T841
Test name
Test status
Simulation time 1658135014 ps
CPU time 13.96 seconds
Started Jun 02 01:24:50 PM PDT 24
Finished Jun 02 01:25:05 PM PDT 24
Peak memory 218028 kb
Host smart-253fd10c-3418-4fd1-bf67-0d1dac34c752
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247965157 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_mux.
1247965157
Directory /workspace/10.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/10.lc_ctrl_security_escalation.88416467
Short name T684
Test name
Test status
Simulation time 244868802 ps
CPU time 6 seconds
Started Jun 02 01:24:52 PM PDT 24
Finished Jun 02 01:24:59 PM PDT 24
Peak memory 218084 kb
Host smart-9144baab-6294-448c-9447-b3cee0a23564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88416467 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_security_escalation.88416467
Directory /workspace/10.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/10.lc_ctrl_smoke.1283795705
Short name T597
Test name
Test status
Simulation time 92913330 ps
CPU time 3.59 seconds
Started Jun 02 01:24:43 PM PDT 24
Finished Jun 02 01:24:47 PM PDT 24
Peak memory 217672 kb
Host smart-07a104e5-dab4-46a8-9bc1-b009a9ffd82e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283795705 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_smoke.1283795705
Directory /workspace/10.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_failure.2714180180
Short name T543
Test name
Test status
Simulation time 2221865542 ps
CPU time 24.23 seconds
Started Jun 02 01:24:43 PM PDT 24
Finished Jun 02 01:25:07 PM PDT 24
Peak memory 251000 kb
Host smart-d2466429-716b-467f-aa3d-83752262380b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714180180 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_failure.2714180180
Directory /workspace/10.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_post_trans.2539705012
Short name T232
Test name
Test status
Simulation time 118699171 ps
CPU time 10.06 seconds
Started Jun 02 01:24:44 PM PDT 24
Finished Jun 02 01:24:54 PM PDT 24
Peak memory 250984 kb
Host smart-474d549d-48eb-4a37-b875-3e28b1669874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539705012 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_post_trans.2539705012
Directory /workspace/10.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_volatile_unlock_smoke.51993488
Short name T532
Test name
Test status
Simulation time 14427790 ps
CPU time 1.02 seconds
Started Jun 02 01:24:43 PM PDT 24
Finished Jun 02 01:24:44 PM PDT 24
Peak memory 208572 kb
Host smart-4d0f80bd-8d2b-4c8a-ae25-4c9e8b214314
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51993488 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vol
atile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctr
l_volatile_unlock_smoke.51993488
Directory /workspace/10.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_alert_test.4188366647
Short name T320
Test name
Test status
Simulation time 68328797 ps
CPU time 0.84 seconds
Started Jun 02 01:24:50 PM PDT 24
Finished Jun 02 01:24:51 PM PDT 24
Peak memory 209528 kb
Host smart-452c286c-1902-4bc3-94a1-78702b164867
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188366647 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_alert_test.4188366647
Directory /workspace/11.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.lc_ctrl_errors.1788580920
Short name T796
Test name
Test status
Simulation time 661249728 ps
CPU time 9.55 seconds
Started Jun 02 01:24:52 PM PDT 24
Finished Jun 02 01:25:02 PM PDT 24
Peak memory 217968 kb
Host smart-5599feb7-d648-4f81-ac0c-7f95835d714e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788580920 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_errors.1788580920
Directory /workspace/11.lc_ctrl_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_access.2326780071
Short name T727
Test name
Test status
Simulation time 140576638 ps
CPU time 4.02 seconds
Started Jun 02 01:24:52 PM PDT 24
Finished Jun 02 01:24:57 PM PDT 24
Peak memory 209480 kb
Host smart-672eac40-4e1d-4b63-988f-707dbc32d7a5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326780071 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_access.2326780071
Directory /workspace/11.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_errors.1159667663
Short name T773
Test name
Test status
Simulation time 7399946181 ps
CPU time 55.3 seconds
Started Jun 02 01:24:50 PM PDT 24
Finished Jun 02 01:25:46 PM PDT 24
Peak memory 218500 kb
Host smart-ea825e05-3eaf-4d45-b589-4a34c89fe1a5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159667663 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_e
rrors.1159667663
Directory /workspace/11.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_prog_failure.2107165879
Short name T265
Test name
Test status
Simulation time 527994937 ps
CPU time 16.18 seconds
Started Jun 02 01:24:50 PM PDT 24
Finished Jun 02 01:25:06 PM PDT 24
Peak memory 217904 kb
Host smart-a261c0bc-17a3-4810-bacf-00ab742a40bb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107165879 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jta
g_prog_failure.2107165879
Directory /workspace/11.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_smoke.2450158004
Short name T625
Test name
Test status
Simulation time 1434763268 ps
CPU time 8.95 seconds
Started Jun 02 01:24:51 PM PDT 24
Finished Jun 02 01:25:00 PM PDT 24
Peak memory 217680 kb
Host smart-c65e701b-e9a4-4ebb-af0e-88b6819284bc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450158004 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_smoke
.2450158004
Directory /workspace/11.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_failure.3586677934
Short name T768
Test name
Test status
Simulation time 1463510464 ps
CPU time 50.58 seconds
Started Jun 02 01:24:52 PM PDT 24
Finished Jun 02 01:25:43 PM PDT 24
Peak memory 267268 kb
Host smart-9578db4d-9c82-41e1-951a-e810efdf2952
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586677934 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jt
ag_state_failure.3586677934
Directory /workspace/11.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_post_trans.1559816538
Short name T570
Test name
Test status
Simulation time 2923758819 ps
CPU time 24.93 seconds
Started Jun 02 01:24:52 PM PDT 24
Finished Jun 02 01:25:17 PM PDT 24
Peak memory 250660 kb
Host smart-eaea3e56-49ed-4685-86cb-adfcb4c7c86a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559816538 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl
_jtag_state_post_trans.1559816538
Directory /workspace/11.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_prog_failure.2506907332
Short name T231
Test name
Test status
Simulation time 86828904 ps
CPU time 3.92 seconds
Started Jun 02 01:24:50 PM PDT 24
Finished Jun 02 01:24:54 PM PDT 24
Peak memory 218016 kb
Host smart-6ee34ef3-ccdd-4556-803d-113d72910fb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506907332 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_prog_failure.2506907332
Directory /workspace/11.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_mubi.1338556196
Short name T713
Test name
Test status
Simulation time 362902948 ps
CPU time 13.39 seconds
Started Jun 02 01:24:52 PM PDT 24
Finished Jun 02 01:25:06 PM PDT 24
Peak memory 226096 kb
Host smart-73cd4dbe-407f-4907-966d-d6866ad9fc75
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338556196 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_mubi.1338556196
Directory /workspace/11.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_digest.1317392874
Short name T347
Test name
Test status
Simulation time 491237650 ps
CPU time 15.07 seconds
Started Jun 02 01:24:50 PM PDT 24
Finished Jun 02 01:25:06 PM PDT 24
Peak memory 217944 kb
Host smart-746d6e8b-c136-4493-8023-5d4e7a271c6a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317392874 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_d
igest.1317392874
Directory /workspace/11.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_mux.2467273283
Short name T575
Test name
Test status
Simulation time 672464716 ps
CPU time 7.33 seconds
Started Jun 02 01:24:50 PM PDT 24
Finished Jun 02 01:24:58 PM PDT 24
Peak memory 217992 kb
Host smart-3b9355a7-80ec-4879-ab4b-3a171a8495cd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467273283 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_mux.
2467273283
Directory /workspace/11.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/11.lc_ctrl_security_escalation.3474454743
Short name T284
Test name
Test status
Simulation time 428069700 ps
CPU time 8.72 seconds
Started Jun 02 01:24:51 PM PDT 24
Finished Jun 02 01:25:00 PM PDT 24
Peak memory 218104 kb
Host smart-3f3c2f0c-24ca-4267-a71d-3a66ba171791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3474454743 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_security_escalation.3474454743
Directory /workspace/11.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/11.lc_ctrl_smoke.2679190222
Short name T647
Test name
Test status
Simulation time 69021325 ps
CPU time 1.51 seconds
Started Jun 02 01:24:52 PM PDT 24
Finished Jun 02 01:24:54 PM PDT 24
Peak memory 213460 kb
Host smart-ac501b3f-0d41-4f78-8b8c-982d86a44866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679190222 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_smoke.2679190222
Directory /workspace/11.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_failure.2482169478
Short name T749
Test name
Test status
Simulation time 1548324226 ps
CPU time 37.3 seconds
Started Jun 02 01:24:54 PM PDT 24
Finished Jun 02 01:25:31 PM PDT 24
Peak memory 250952 kb
Host smart-d29770cd-241a-48e0-b137-ea97fc542a7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482169478 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_failure.2482169478
Directory /workspace/11.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_post_trans.598122255
Short name T201
Test name
Test status
Simulation time 282989664 ps
CPU time 4.01 seconds
Started Jun 02 01:24:52 PM PDT 24
Finished Jun 02 01:24:57 PM PDT 24
Peak memory 222712 kb
Host smart-ec98f89f-02e5-411c-82ba-d5820beb2ea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598122255 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_post_trans.598122255
Directory /workspace/11.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_stress_all.26406004
Short name T571
Test name
Test status
Simulation time 94550684441 ps
CPU time 758.58 seconds
Started Jun 02 01:24:54 PM PDT 24
Finished Jun 02 01:37:33 PM PDT 24
Peak memory 316652 kb
Host smart-f957d9e7-ad24-4f84-9e5f-cfe003d2650a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26406004 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_T
EST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
1.lc_ctrl_stress_all.26406004
Directory /workspace/11.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.lc_ctrl_volatile_unlock_smoke.3189543114
Short name T431
Test name
Test status
Simulation time 13190562 ps
CPU time 0.83 seconds
Started Jun 02 01:24:52 PM PDT 24
Finished Jun 02 01:24:54 PM PDT 24
Peak memory 208492 kb
Host smart-5c625f7a-cd68-4c7d-bf48-e8171fa95fb0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189543114 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_c
trl_volatile_unlock_smoke.3189543114
Directory /workspace/11.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_alert_test.171744500
Short name T510
Test name
Test status
Simulation time 22006600 ps
CPU time 1.25 seconds
Started Jun 02 01:24:58 PM PDT 24
Finished Jun 02 01:24:59 PM PDT 24
Peak memory 209656 kb
Host smart-6cf23825-7ec4-4929-a460-4f54fc716172
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171744500 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_alert_test.171744500
Directory /workspace/12.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.lc_ctrl_errors.2834186821
Short name T587
Test name
Test status
Simulation time 226321149 ps
CPU time 11.14 seconds
Started Jun 02 01:24:58 PM PDT 24
Finished Jun 02 01:25:09 PM PDT 24
Peak memory 217992 kb
Host smart-8574f20c-3d0d-46a6-81e0-0c530161e9a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834186821 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_errors.2834186821
Directory /workspace/12.lc_ctrl_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_access.2021395816
Short name T602
Test name
Test status
Simulation time 438744208 ps
CPU time 2.23 seconds
Started Jun 02 01:24:58 PM PDT 24
Finished Jun 02 01:25:00 PM PDT 24
Peak memory 216808 kb
Host smart-f3c72c8e-e52a-4d8b-85f5-73e9143752c3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021395816 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_access.2021395816
Directory /workspace/12.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_errors.939282517
Short name T852
Test name
Test status
Simulation time 6515217830 ps
CPU time 46.56 seconds
Started Jun 02 01:25:07 PM PDT 24
Finished Jun 02 01:25:53 PM PDT 24
Peak memory 218900 kb
Host smart-e95d6f9a-e094-4c5f-8637-b668040a2f75
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939282517 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_er
rors.939282517
Directory /workspace/12.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_prog_failure.725628235
Short name T766
Test name
Test status
Simulation time 1414790917 ps
CPU time 9.29 seconds
Started Jun 02 01:24:56 PM PDT 24
Finished Jun 02 01:25:06 PM PDT 24
Peak memory 217924 kb
Host smart-b39344be-075e-4d24-9ecc-0f5f5456bb1d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725628235 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag
_prog_failure.725628235
Directory /workspace/12.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_smoke.3899024899
Short name T67
Test name
Test status
Simulation time 2926895804 ps
CPU time 18.63 seconds
Started Jun 02 01:25:04 PM PDT 24
Finished Jun 02 01:25:23 PM PDT 24
Peak memory 217692 kb
Host smart-dd6de762-4035-464f-975d-52193edcabd8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899024899 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_smoke
.3899024899
Directory /workspace/12.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_failure.1354652160
Short name T507
Test name
Test status
Simulation time 13758423576 ps
CPU time 45.9 seconds
Started Jun 02 01:25:00 PM PDT 24
Finished Jun 02 01:25:46 PM PDT 24
Peak memory 267400 kb
Host smart-c4a1858c-28d0-48ac-9a25-db6ca35a7f14
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354652160 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jt
ag_state_failure.1354652160
Directory /workspace/12.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_post_trans.1535514004
Short name T562
Test name
Test status
Simulation time 368554345 ps
CPU time 7.97 seconds
Started Jun 02 01:24:59 PM PDT 24
Finished Jun 02 01:25:07 PM PDT 24
Peak memory 221860 kb
Host smart-a1c409df-3043-4c36-a279-eb882616b845
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535514004 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl
_jtag_state_post_trans.1535514004
Directory /workspace/12.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_prog_failure.3284069108
Short name T356
Test name
Test status
Simulation time 63652244 ps
CPU time 2.96 seconds
Started Jun 02 01:25:03 PM PDT 24
Finished Jun 02 01:25:07 PM PDT 24
Peak memory 218064 kb
Host smart-77a2f54d-0c3d-468f-83bf-a195ffee483e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284069108 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_prog_failure.3284069108
Directory /workspace/12.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_mubi.2212564497
Short name T600
Test name
Test status
Simulation time 1147328156 ps
CPU time 10.18 seconds
Started Jun 02 01:25:06 PM PDT 24
Finished Jun 02 01:25:16 PM PDT 24
Peak memory 226080 kb
Host smart-0b9b1494-bc1a-4c7e-a18a-89d988726aa2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212564497 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_mubi.2212564497
Directory /workspace/12.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_digest.3029854816
Short name T414
Test name
Test status
Simulation time 2057033996 ps
CPU time 17.86 seconds
Started Jun 02 01:25:05 PM PDT 24
Finished Jun 02 01:25:24 PM PDT 24
Peak memory 217896 kb
Host smart-16cf7556-8cad-4c6e-afd5-0f5bdf7ccb03
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029854816 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_d
igest.3029854816
Directory /workspace/12.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_mux.1012998068
Short name T548
Test name
Test status
Simulation time 2753419247 ps
CPU time 17.94 seconds
Started Jun 02 01:24:57 PM PDT 24
Finished Jun 02 01:25:15 PM PDT 24
Peak memory 218080 kb
Host smart-841bdc53-5fed-4e5c-aea9-043d641a6b94
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012998068 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_mux.
1012998068
Directory /workspace/12.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/12.lc_ctrl_security_escalation.1956223046
Short name T287
Test name
Test status
Simulation time 194945236 ps
CPU time 6.96 seconds
Started Jun 02 01:24:58 PM PDT 24
Finished Jun 02 01:25:05 PM PDT 24
Peak memory 218032 kb
Host smart-481a44fd-c726-4913-8f02-ed379428652a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956223046 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_security_escalation.1956223046
Directory /workspace/12.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/12.lc_ctrl_smoke.1308592292
Short name T857
Test name
Test status
Simulation time 41117325 ps
CPU time 1.3 seconds
Started Jun 02 01:24:57 PM PDT 24
Finished Jun 02 01:24:59 PM PDT 24
Peak memory 217704 kb
Host smart-8bade9f8-18ce-44d9-8b2a-5aa4fadbf4eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308592292 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_smoke.1308592292
Directory /workspace/12.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_stress_all.1947273660
Short name T398
Test name
Test status
Simulation time 25936508199 ps
CPU time 114.05 seconds
Started Jun 02 01:25:06 PM PDT 24
Finished Jun 02 01:27:00 PM PDT 24
Peak memory 226180 kb
Host smart-51441e8b-0e50-47cf-9452-49f04987c115
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947273660 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.lc_ctrl_stress_all.1947273660
Directory /workspace/12.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.lc_ctrl_volatile_unlock_smoke.2893645219
Short name T689
Test name
Test status
Simulation time 40712310 ps
CPU time 0.82 seconds
Started Jun 02 01:25:05 PM PDT 24
Finished Jun 02 01:25:07 PM PDT 24
Peak memory 208504 kb
Host smart-6dc4214b-e0fd-49b6-81f0-cca853773618
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893645219 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_c
trl_volatile_unlock_smoke.2893645219
Directory /workspace/12.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_alert_test.4219161806
Short name T610
Test name
Test status
Simulation time 42129084 ps
CPU time 0.8 seconds
Started Jun 02 01:25:08 PM PDT 24
Finished Jun 02 01:25:09 PM PDT 24
Peak memory 209360 kb
Host smart-9c3e596b-0518-49d5-bed1-875692f483b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219161806 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_alert_test.4219161806
Directory /workspace/13.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.lc_ctrl_errors.708969987
Short name T372
Test name
Test status
Simulation time 530664656 ps
CPU time 13.46 seconds
Started Jun 02 01:25:06 PM PDT 24
Finished Jun 02 01:25:20 PM PDT 24
Peak memory 218060 kb
Host smart-68807ece-4ded-4638-92be-70c680f648a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708969987 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_errors.708969987
Directory /workspace/13.lc_ctrl_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_access.541556908
Short name T715
Test name
Test status
Simulation time 1170049240 ps
CPU time 6.83 seconds
Started Jun 02 01:25:09 PM PDT 24
Finished Jun 02 01:25:16 PM PDT 24
Peak memory 209468 kb
Host smart-ee1fbb0a-a699-4b83-a59e-bab8f45b5842
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541556908 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_access.541556908
Directory /workspace/13.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_errors.2790074678
Short name T492
Test name
Test status
Simulation time 38133379473 ps
CPU time 29.77 seconds
Started Jun 02 01:25:07 PM PDT 24
Finished Jun 02 01:25:38 PM PDT 24
Peak memory 218952 kb
Host smart-09803d21-fb5b-4f73-a3a6-d24234ef69f1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790074678 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_e
rrors.2790074678
Directory /workspace/13.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_prog_failure.1914465632
Short name T479
Test name
Test status
Simulation time 120866907 ps
CPU time 3.05 seconds
Started Jun 02 01:25:05 PM PDT 24
Finished Jun 02 01:25:09 PM PDT 24
Peak memory 217996 kb
Host smart-4181d2ce-c97a-4f73-8056-1d862b148890
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914465632 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jta
g_prog_failure.1914465632
Directory /workspace/13.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_smoke.4204243199
Short name T5
Test name
Test status
Simulation time 187029380 ps
CPU time 3.9 seconds
Started Jun 02 01:25:06 PM PDT 24
Finished Jun 02 01:25:10 PM PDT 24
Peak memory 217616 kb
Host smart-a08add3e-b12f-4f9b-8dfd-a5a9a5754bd6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204243199 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_smoke
.4204243199
Directory /workspace/13.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_failure.1630369896
Short name T241
Test name
Test status
Simulation time 4559965869 ps
CPU time 54.71 seconds
Started Jun 02 01:25:07 PM PDT 24
Finished Jun 02 01:26:02 PM PDT 24
Peak memory 283352 kb
Host smart-09e72b6c-47ab-4521-91c8-fbe3bea42435
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630369896 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jt
ag_state_failure.1630369896
Directory /workspace/13.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_post_trans.1840780103
Short name T229
Test name
Test status
Simulation time 516506172 ps
CPU time 13.3 seconds
Started Jun 02 01:25:07 PM PDT 24
Finished Jun 02 01:25:21 PM PDT 24
Peak memory 247580 kb
Host smart-7ca0ecc4-8299-42a4-ac26-a7953bb9f195
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840780103 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl
_jtag_state_post_trans.1840780103
Directory /workspace/13.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_prog_failure.4063209573
Short name T834
Test name
Test status
Simulation time 63138965 ps
CPU time 3.72 seconds
Started Jun 02 01:25:07 PM PDT 24
Finished Jun 02 01:25:12 PM PDT 24
Peak memory 218068 kb
Host smart-4c92cf1f-0254-4894-9f3e-c45c5aa8eed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063209573 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_prog_failure.4063209573
Directory /workspace/13.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_mubi.1602351170
Short name T154
Test name
Test status
Simulation time 505677028 ps
CPU time 13.24 seconds
Started Jun 02 01:25:05 PM PDT 24
Finished Jun 02 01:25:19 PM PDT 24
Peak memory 226044 kb
Host smart-49f57c66-a124-49ad-a6e8-5696baf32b45
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602351170 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_mubi.1602351170
Directory /workspace/13.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_digest.756753667
Short name T627
Test name
Test status
Simulation time 1199593829 ps
CPU time 9.27 seconds
Started Jun 02 01:25:06 PM PDT 24
Finished Jun 02 01:25:15 PM PDT 24
Peak memory 226056 kb
Host smart-5ef650ee-c644-44da-b3d9-a488562f3988
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756753667 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_di
gest.756753667
Directory /workspace/13.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_mux.3377893372
Short name T677
Test name
Test status
Simulation time 208670019 ps
CPU time 5.8 seconds
Started Jun 02 01:25:10 PM PDT 24
Finished Jun 02 01:25:17 PM PDT 24
Peak memory 217996 kb
Host smart-bc131ea2-20fa-4b23-bcb0-51ba201afa74
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377893372 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_mux.
3377893372
Directory /workspace/13.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/13.lc_ctrl_smoke.2271456837
Short name T508
Test name
Test status
Simulation time 142415042 ps
CPU time 2.99 seconds
Started Jun 02 01:25:07 PM PDT 24
Finished Jun 02 01:25:11 PM PDT 24
Peak memory 214228 kb
Host smart-3c80f3ed-4a9a-412a-ba30-976924e608a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271456837 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_smoke.2271456837
Directory /workspace/13.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_failure.3183569716
Short name T263
Test name
Test status
Simulation time 2807327789 ps
CPU time 22.28 seconds
Started Jun 02 01:25:04 PM PDT 24
Finished Jun 02 01:25:27 PM PDT 24
Peak memory 251040 kb
Host smart-81a64e8b-3b16-44d3-9349-5ddd4084e754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183569716 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_failure.3183569716
Directory /workspace/13.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_post_trans.4241447867
Short name T640
Test name
Test status
Simulation time 88906148 ps
CPU time 9.47 seconds
Started Jun 02 01:25:07 PM PDT 24
Finished Jun 02 01:25:17 PM PDT 24
Peak memory 250992 kb
Host smart-1e880ad3-a4c5-4765-a97b-a303d488d41a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241447867 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_post_trans.4241447867
Directory /workspace/13.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all.1665044552
Short name T753
Test name
Test status
Simulation time 6323501296 ps
CPU time 30.77 seconds
Started Jun 02 01:25:07 PM PDT 24
Finished Jun 02 01:25:38 PM PDT 24
Peak memory 219036 kb
Host smart-2b461db8-3b26-43c5-9e0c-2124781df065
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665044552 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.lc_ctrl_stress_all.1665044552
Directory /workspace/13.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.lc_ctrl_volatile_unlock_smoke.3084780634
Short name T722
Test name
Test status
Simulation time 16374074 ps
CPU time 1.15 seconds
Started Jun 02 01:24:58 PM PDT 24
Finished Jun 02 01:25:00 PM PDT 24
Peak memory 212672 kb
Host smart-f26a2e1a-fb78-4ead-89cc-6fc22c942789
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084780634 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_c
trl_volatile_unlock_smoke.3084780634
Directory /workspace/13.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_alert_test.2201960633
Short name T423
Test name
Test status
Simulation time 38823148 ps
CPU time 1.05 seconds
Started Jun 02 01:25:15 PM PDT 24
Finished Jun 02 01:25:16 PM PDT 24
Peak memory 209576 kb
Host smart-e40714b4-f77f-42b4-93fe-eca887f19fcd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201960633 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_alert_test.2201960633
Directory /workspace/14.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.lc_ctrl_errors.2437671199
Short name T683
Test name
Test status
Simulation time 3541113340 ps
CPU time 17.4 seconds
Started Jun 02 01:25:07 PM PDT 24
Finished Jun 02 01:25:24 PM PDT 24
Peak memory 219028 kb
Host smart-d0127e57-769d-472b-8b13-5fcfdc43c723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437671199 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_errors.2437671199
Directory /workspace/14.lc_ctrl_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_access.3917433154
Short name T774
Test name
Test status
Simulation time 3043253070 ps
CPU time 18.5 seconds
Started Jun 02 01:25:15 PM PDT 24
Finished Jun 02 01:25:34 PM PDT 24
Peak memory 217632 kb
Host smart-f7f65714-c75a-4fa5-893b-4b0edeeea2b1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917433154 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_access.3917433154
Directory /workspace/14.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_errors.3899079072
Short name T486
Test name
Test status
Simulation time 6959051273 ps
CPU time 33.17 seconds
Started Jun 02 01:25:15 PM PDT 24
Finished Jun 02 01:25:48 PM PDT 24
Peak memory 218400 kb
Host smart-1eb11d5f-c644-41c9-b2e2-e0c793e35a52
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899079072 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_e
rrors.3899079072
Directory /workspace/14.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_prog_failure.1387595549
Short name T714
Test name
Test status
Simulation time 887584622 ps
CPU time 6.74 seconds
Started Jun 02 01:25:08 PM PDT 24
Finished Jun 02 01:25:15 PM PDT 24
Peak memory 218008 kb
Host smart-9b6c2279-c684-4137-8880-910d473f6e65
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387595549 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jta
g_prog_failure.1387595549
Directory /workspace/14.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_smoke.1411836798
Short name T454
Test name
Test status
Simulation time 499659374 ps
CPU time 12.69 seconds
Started Jun 02 01:25:08 PM PDT 24
Finished Jun 02 01:25:21 PM PDT 24
Peak memory 217664 kb
Host smart-a89ec355-05b5-4b9c-9dbe-0a3be6cb051b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411836798 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_smoke
.1411836798
Directory /workspace/14.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_failure.747950090
Short name T261
Test name
Test status
Simulation time 12865902750 ps
CPU time 51.6 seconds
Started Jun 02 01:25:04 PM PDT 24
Finished Jun 02 01:25:56 PM PDT 24
Peak memory 271444 kb
Host smart-dd04bc95-edc1-4dfd-bb32-f97587c123f5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747950090 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jta
g_state_failure.747950090
Directory /workspace/14.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_post_trans.2796536446
Short name T685
Test name
Test status
Simulation time 639289798 ps
CPU time 15.24 seconds
Started Jun 02 01:25:09 PM PDT 24
Finished Jun 02 01:25:25 PM PDT 24
Peak memory 250980 kb
Host smart-3c3eb072-7379-4a01-969f-e4c8b34c4e4f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796536446 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl
_jtag_state_post_trans.2796536446
Directory /workspace/14.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_prog_failure.965085268
Short name T747
Test name
Test status
Simulation time 118765674 ps
CPU time 3.06 seconds
Started Jun 02 01:25:07 PM PDT 24
Finished Jun 02 01:25:11 PM PDT 24
Peak memory 218004 kb
Host smart-5d5a92fc-f4ad-4b74-a74c-bd8184fb9136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965085268 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_prog_failure.965085268
Directory /workspace/14.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_mubi.2561575262
Short name T760
Test name
Test status
Simulation time 1595116882 ps
CPU time 17.23 seconds
Started Jun 02 01:25:11 PM PDT 24
Finished Jun 02 01:25:28 PM PDT 24
Peak memory 226108 kb
Host smart-b0b5a255-2def-40ad-8c61-92268047dd80
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561575262 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_mubi.2561575262
Directory /workspace/14.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_digest.1683465511
Short name T822
Test name
Test status
Simulation time 2147707647 ps
CPU time 11.59 seconds
Started Jun 02 01:25:23 PM PDT 24
Finished Jun 02 01:25:35 PM PDT 24
Peak memory 226048 kb
Host smart-746d74b8-0b7c-483e-b6bb-0643e4b9c5ea
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683465511 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_d
igest.1683465511
Directory /workspace/14.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_mux.1927640043
Short name T764
Test name
Test status
Simulation time 306403850 ps
CPU time 10.95 seconds
Started Jun 02 01:25:11 PM PDT 24
Finished Jun 02 01:25:23 PM PDT 24
Peak memory 217960 kb
Host smart-243f29da-283c-4720-8fb0-14e3eff07a99
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927640043 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_mux.
1927640043
Directory /workspace/14.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/14.lc_ctrl_smoke.811858191
Short name T514
Test name
Test status
Simulation time 122997998 ps
CPU time 3.73 seconds
Started Jun 02 01:25:10 PM PDT 24
Finished Jun 02 01:25:14 PM PDT 24
Peak memory 217740 kb
Host smart-4cf03c5c-85dd-40cc-8e84-9e5322ab0f54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811858191 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_smoke.811858191
Directory /workspace/14.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_failure.2373838363
Short name T838
Test name
Test status
Simulation time 225986538 ps
CPU time 24.77 seconds
Started Jun 02 01:25:05 PM PDT 24
Finished Jun 02 01:25:30 PM PDT 24
Peak memory 251020 kb
Host smart-aff127b2-b522-42de-8041-813656bb506a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373838363 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_failure.2373838363
Directory /workspace/14.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_post_trans.1178708561
Short name T615
Test name
Test status
Simulation time 129532795 ps
CPU time 4.25 seconds
Started Jun 02 01:25:05 PM PDT 24
Finished Jun 02 01:25:10 PM PDT 24
Peak memory 223000 kb
Host smart-0f5facd9-383f-42ec-a4ab-23e3f8233b05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178708561 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_post_trans.1178708561
Directory /workspace/14.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_stress_all.326977079
Short name T864
Test name
Test status
Simulation time 41119852320 ps
CPU time 223.66 seconds
Started Jun 02 01:25:12 PM PDT 24
Finished Jun 02 01:28:56 PM PDT 24
Peak memory 251028 kb
Host smart-b2c788f9-7ea0-475f-9cb2-31d990206c05
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326977079 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.lc_ctrl_stress_all.326977079
Directory /workspace/14.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.lc_ctrl_volatile_unlock_smoke.3756588504
Short name T38
Test name
Test status
Simulation time 13770705 ps
CPU time 0.81 seconds
Started Jun 02 01:25:07 PM PDT 24
Finished Jun 02 01:25:08 PM PDT 24
Peak memory 208684 kb
Host smart-d1c493a3-02e0-4a0b-b893-872fc66a1e33
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756588504 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_c
trl_volatile_unlock_smoke.3756588504
Directory /workspace/14.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_alert_test.2279681083
Short name T495
Test name
Test status
Simulation time 19539148 ps
CPU time 0.87 seconds
Started Jun 02 01:25:23 PM PDT 24
Finished Jun 02 01:25:25 PM PDT 24
Peak memory 208644 kb
Host smart-912a625c-2fba-4da7-a891-b456c6931317
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279681083 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_alert_test.2279681083
Directory /workspace/15.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.lc_ctrl_errors.848367436
Short name T285
Test name
Test status
Simulation time 442919093 ps
CPU time 7.74 seconds
Started Jun 02 01:25:23 PM PDT 24
Finished Jun 02 01:25:32 PM PDT 24
Peak memory 217992 kb
Host smart-1c4b63ca-9a09-410d-944d-ae0a36b28090
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848367436 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_errors.848367436
Directory /workspace/15.lc_ctrl_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_access.1339077028
Short name T27
Test name
Test status
Simulation time 138486030 ps
CPU time 1.6 seconds
Started Jun 02 01:25:11 PM PDT 24
Finished Jun 02 01:25:13 PM PDT 24
Peak memory 216876 kb
Host smart-270c031f-8a23-4465-9c09-2502ba17ecb4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339077028 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_access.1339077028
Directory /workspace/15.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_errors.295695101
Short name T652
Test name
Test status
Simulation time 22607403902 ps
CPU time 75.17 seconds
Started Jun 02 01:25:14 PM PDT 24
Finished Jun 02 01:26:29 PM PDT 24
Peak memory 218932 kb
Host smart-8e26b033-a707-4e24-9e28-0812d8e8036b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295695101 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_er
rors.295695101
Directory /workspace/15.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_prog_failure.2992500969
Short name T551
Test name
Test status
Simulation time 646265642 ps
CPU time 18.82 seconds
Started Jun 02 01:25:13 PM PDT 24
Finished Jun 02 01:25:32 PM PDT 24
Peak memory 217956 kb
Host smart-82792066-52ab-4b10-a22c-8983e2ed6855
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992500969 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jta
g_prog_failure.2992500969
Directory /workspace/15.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_smoke.3838604376
Short name T557
Test name
Test status
Simulation time 2855072736 ps
CPU time 9.1 seconds
Started Jun 02 01:25:12 PM PDT 24
Finished Jun 02 01:25:21 PM PDT 24
Peak memory 217740 kb
Host smart-d54e51eb-c63d-4bb2-a100-4d54c182c404
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838604376 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_smoke
.3838604376
Directory /workspace/15.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_failure.1688993435
Short name T554
Test name
Test status
Simulation time 3516819066 ps
CPU time 52.15 seconds
Started Jun 02 01:25:11 PM PDT 24
Finished Jun 02 01:26:04 PM PDT 24
Peak memory 267900 kb
Host smart-2f813642-2c8a-4ad0-aa82-0c997d4295f7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688993435 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jt
ag_state_failure.1688993435
Directory /workspace/15.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_post_trans.1236833968
Short name T18
Test name
Test status
Simulation time 4742629519 ps
CPU time 20.79 seconds
Started Jun 02 01:25:10 PM PDT 24
Finished Jun 02 01:25:32 PM PDT 24
Peak memory 250612 kb
Host smart-045be4a2-9b77-410d-8d45-2ee36672eed1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236833968 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl
_jtag_state_post_trans.1236833968
Directory /workspace/15.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_prog_failure.1049656846
Short name T357
Test name
Test status
Simulation time 72400470 ps
CPU time 1.67 seconds
Started Jun 02 01:25:10 PM PDT 24
Finished Jun 02 01:25:12 PM PDT 24
Peak memory 218032 kb
Host smart-dc4b7062-0536-4406-ac59-36cccd5d91bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049656846 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_prog_failure.1049656846
Directory /workspace/15.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_mubi.93578303
Short name T572
Test name
Test status
Simulation time 1817623422 ps
CPU time 11.01 seconds
Started Jun 02 01:25:23 PM PDT 24
Finished Jun 02 01:25:35 PM PDT 24
Peak memory 226016 kb
Host smart-4a48e228-aae5-4d2c-aefa-93a2712ec3a7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93578303 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_mubi.93578303
Directory /workspace/15.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_digest.2659539458
Short name T815
Test name
Test status
Simulation time 1738341988 ps
CPU time 19.16 seconds
Started Jun 02 01:25:12 PM PDT 24
Finished Jun 02 01:25:32 PM PDT 24
Peak memory 217944 kb
Host smart-24407249-0f8c-4ec9-bdf5-f269da25766d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659539458 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_d
igest.2659539458
Directory /workspace/15.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_mux.1229309925
Short name T756
Test name
Test status
Simulation time 788265867 ps
CPU time 6.64 seconds
Started Jun 02 01:25:11 PM PDT 24
Finished Jun 02 01:25:18 PM PDT 24
Peak memory 218108 kb
Host smart-dfc5eae8-d382-4889-81ff-fb2a4c7ddb2b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229309925 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_mux.
1229309925
Directory /workspace/15.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/15.lc_ctrl_security_escalation.2108231910
Short name T490
Test name
Test status
Simulation time 224576199 ps
CPU time 7.48 seconds
Started Jun 02 01:25:10 PM PDT 24
Finished Jun 02 01:25:17 PM PDT 24
Peak memory 218040 kb
Host smart-9ac21a96-f09b-42e6-acc6-20c9184ed259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108231910 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_security_escalation.2108231910
Directory /workspace/15.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/15.lc_ctrl_smoke.3392431493
Short name T585
Test name
Test status
Simulation time 220705251 ps
CPU time 4.01 seconds
Started Jun 02 01:25:23 PM PDT 24
Finished Jun 02 01:25:28 PM PDT 24
Peak memory 217664 kb
Host smart-18daa6c3-71dc-40d4-8add-2c442054ab8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392431493 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_smoke.3392431493
Directory /workspace/15.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_failure.2177624308
Short name T669
Test name
Test status
Simulation time 135758724 ps
CPU time 25.44 seconds
Started Jun 02 01:25:15 PM PDT 24
Finished Jun 02 01:25:41 PM PDT 24
Peak memory 250688 kb
Host smart-a7f327dc-56f1-4e6c-9859-3705ac51626a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177624308 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_failure.2177624308
Directory /workspace/15.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_post_trans.2694322630
Short name T243
Test name
Test status
Simulation time 116115312 ps
CPU time 5.93 seconds
Started Jun 02 01:25:10 PM PDT 24
Finished Jun 02 01:25:16 PM PDT 24
Peak memory 246916 kb
Host smart-0f56f7cc-32bd-4cfd-bcdd-b5cfb45f36b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694322630 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_post_trans.2694322630
Directory /workspace/15.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all.3485120697
Short name T477
Test name
Test status
Simulation time 18878701920 ps
CPU time 85.35 seconds
Started Jun 02 01:25:11 PM PDT 24
Finished Jun 02 01:26:37 PM PDT 24
Peak memory 226124 kb
Host smart-72764dbf-6e2b-4ecb-a24d-57e2614714c0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485120697 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.lc_ctrl_stress_all.3485120697
Directory /workspace/15.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all_with_rand_reset.2923467817
Short name T146
Test name
Test status
Simulation time 178105855370 ps
CPU time 4713.67 seconds
Started Jun 02 01:25:11 PM PDT 24
Finished Jun 02 02:43:46 PM PDT 24
Peak memory 759056 kb
Host smart-74e5ceee-145f-415a-a934-b3cdc8b4cfc3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2923467817 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_stress_all_with_rand_reset.2923467817
Directory /workspace/15.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.lc_ctrl_alert_test.1712472529
Short name T362
Test name
Test status
Simulation time 53485330 ps
CPU time 0.86 seconds
Started Jun 02 01:25:19 PM PDT 24
Finished Jun 02 01:25:20 PM PDT 24
Peak memory 208488 kb
Host smart-bfb730e0-76a1-49c3-bc07-96c878962e41
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712472529 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_alert_test.1712472529
Directory /workspace/16.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.lc_ctrl_errors.1651565231
Short name T441
Test name
Test status
Simulation time 1182873423 ps
CPU time 13.88 seconds
Started Jun 02 01:25:11 PM PDT 24
Finished Jun 02 01:25:25 PM PDT 24
Peak memory 218192 kb
Host smart-ac7f44d8-daae-406b-823e-761254a94316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651565231 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_errors.1651565231
Directory /workspace/16.lc_ctrl_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_access.4020521024
Short name T449
Test name
Test status
Simulation time 1530774445 ps
CPU time 9.51 seconds
Started Jun 02 01:25:17 PM PDT 24
Finished Jun 02 01:25:27 PM PDT 24
Peak memory 209484 kb
Host smart-597ce6df-a294-4476-a641-fe633ce34b66
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020521024 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_access.4020521024
Directory /workspace/16.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_errors.3985027592
Short name T379
Test name
Test status
Simulation time 7252095388 ps
CPU time 102.35 seconds
Started Jun 02 01:25:17 PM PDT 24
Finished Jun 02 01:27:00 PM PDT 24
Peak memory 218944 kb
Host smart-8d1b0e7c-32af-46f3-a3a4-bdbe37696947
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985027592 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_e
rrors.3985027592
Directory /workspace/16.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_prog_failure.1331708860
Short name T341
Test name
Test status
Simulation time 137999723 ps
CPU time 3.09 seconds
Started Jun 02 01:25:19 PM PDT 24
Finished Jun 02 01:25:22 PM PDT 24
Peak memory 217940 kb
Host smart-8fdb91ea-83aa-4aa0-aa98-2bf93fc071d6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331708860 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jta
g_prog_failure.1331708860
Directory /workspace/16.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_smoke.3998462483
Short name T236
Test name
Test status
Simulation time 1497054049 ps
CPU time 5.72 seconds
Started Jun 02 01:25:15 PM PDT 24
Finished Jun 02 01:25:21 PM PDT 24
Peak memory 217652 kb
Host smart-801cbda8-4b45-4ddf-bbef-48d42e8a9602
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998462483 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_smoke
.3998462483
Directory /workspace/16.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_failure.3250796967
Short name T565
Test name
Test status
Simulation time 2453933563 ps
CPU time 73.84 seconds
Started Jun 02 01:25:18 PM PDT 24
Finished Jun 02 01:26:32 PM PDT 24
Peak memory 275560 kb
Host smart-a43ed9fb-9acd-4254-812d-875888a9b802
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250796967 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jt
ag_state_failure.3250796967
Directory /workspace/16.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_post_trans.3933673808
Short name T290
Test name
Test status
Simulation time 3075961225 ps
CPU time 12.93 seconds
Started Jun 02 01:25:20 PM PDT 24
Finished Jun 02 01:25:33 PM PDT 24
Peak memory 226348 kb
Host smart-7ceb9ab2-c592-4867-a402-0f125318a482
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933673808 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl
_jtag_state_post_trans.3933673808
Directory /workspace/16.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_prog_failure.2131034671
Short name T795
Test name
Test status
Simulation time 46227136 ps
CPU time 1.4 seconds
Started Jun 02 01:25:14 PM PDT 24
Finished Jun 02 01:25:15 PM PDT 24
Peak memory 218004 kb
Host smart-6353cf06-ced3-4ec9-b3fb-08ff662b2dc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131034671 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_prog_failure.2131034671
Directory /workspace/16.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_mubi.334372393
Short name T159
Test name
Test status
Simulation time 412548101 ps
CPU time 12.84 seconds
Started Jun 02 01:25:20 PM PDT 24
Finished Jun 02 01:25:33 PM PDT 24
Peak memory 218952 kb
Host smart-74c38abe-42af-4cf8-88a2-f67cfd4734bd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334372393 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_mubi.334372393
Directory /workspace/16.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_digest.700373753
Short name T814
Test name
Test status
Simulation time 2221385269 ps
CPU time 12.61 seconds
Started Jun 02 01:25:21 PM PDT 24
Finished Jun 02 01:25:34 PM PDT 24
Peak memory 218012 kb
Host smart-40d78699-8197-44eb-86b7-0b3723170d3a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700373753 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_di
gest.700373753
Directory /workspace/16.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_mux.994163246
Short name T95
Test name
Test status
Simulation time 181771252 ps
CPU time 7.81 seconds
Started Jun 02 01:25:18 PM PDT 24
Finished Jun 02 01:25:26 PM PDT 24
Peak memory 217992 kb
Host smart-f8c30dc9-e249-4c2c-bbef-e146aceb04df
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994163246 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_mux.994163246
Directory /workspace/16.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/16.lc_ctrl_security_escalation.3575507024
Short name T426
Test name
Test status
Simulation time 183783694 ps
CPU time 7.87 seconds
Started Jun 02 01:25:13 PM PDT 24
Finished Jun 02 01:25:21 PM PDT 24
Peak memory 218068 kb
Host smart-7ed1f78f-f122-4556-af55-14bcfb2666e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575507024 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_security_escalation.3575507024
Directory /workspace/16.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/16.lc_ctrl_smoke.3153676347
Short name T786
Test name
Test status
Simulation time 25108977 ps
CPU time 1.38 seconds
Started Jun 02 01:25:10 PM PDT 24
Finished Jun 02 01:25:12 PM PDT 24
Peak memory 213648 kb
Host smart-b5b58730-6abb-4457-a5a7-57fdb3416e80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153676347 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_smoke.3153676347
Directory /workspace/16.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_failure.3621693527
Short name T221
Test name
Test status
Simulation time 282287887 ps
CPU time 26.67 seconds
Started Jun 02 01:25:10 PM PDT 24
Finished Jun 02 01:25:37 PM PDT 24
Peak memory 250980 kb
Host smart-63596f8d-945c-4418-9f9d-69e9ab8e5353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621693527 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_failure.3621693527
Directory /workspace/16.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_post_trans.249175102
Short name T646
Test name
Test status
Simulation time 112656418 ps
CPU time 7.21 seconds
Started Jun 02 01:25:23 PM PDT 24
Finished Jun 02 01:25:31 PM PDT 24
Peak memory 251000 kb
Host smart-ebffa477-5936-4e82-988e-ffc83852d625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249175102 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_post_trans.249175102
Directory /workspace/16.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_stress_all.209026663
Short name T81
Test name
Test status
Simulation time 77597152863 ps
CPU time 153.13 seconds
Started Jun 02 01:25:17 PM PDT 24
Finished Jun 02 01:27:51 PM PDT 24
Peak memory 268536 kb
Host smart-41e8f3ec-5763-47a3-8775-1947ba1a9521
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209026663 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.lc_ctrl_stress_all.209026663
Directory /workspace/16.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.lc_ctrl_volatile_unlock_smoke.2972604839
Short name T803
Test name
Test status
Simulation time 17367903 ps
CPU time 1.02 seconds
Started Jun 02 01:25:23 PM PDT 24
Finished Jun 02 01:25:25 PM PDT 24
Peak memory 211636 kb
Host smart-2e88e971-9f25-4620-8cca-d76a50c2c95d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972604839 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_c
trl_volatile_unlock_smoke.2972604839
Directory /workspace/16.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_alert_test.3224716402
Short name T346
Test name
Test status
Simulation time 64206972 ps
CPU time 1.09 seconds
Started Jun 02 01:25:29 PM PDT 24
Finished Jun 02 01:25:30 PM PDT 24
Peak memory 209564 kb
Host smart-c90e173a-b128-4da1-8354-4ee93d677cb1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224716402 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_alert_test.3224716402
Directory /workspace/17.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.lc_ctrl_errors.2617332077
Short name T55
Test name
Test status
Simulation time 381781997 ps
CPU time 17 seconds
Started Jun 02 01:25:20 PM PDT 24
Finished Jun 02 01:25:37 PM PDT 24
Peak memory 218068 kb
Host smart-708cf12a-058c-480d-bad0-25064515ac15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617332077 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_errors.2617332077
Directory /workspace/17.lc_ctrl_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_access.432218712
Short name T10
Test name
Test status
Simulation time 235279318 ps
CPU time 4.3 seconds
Started Jun 02 01:25:18 PM PDT 24
Finished Jun 02 01:25:23 PM PDT 24
Peak memory 209476 kb
Host smart-bf5d61a2-e382-41d8-bfb9-6fb72517cb07
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432218712 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_access.432218712
Directory /workspace/17.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_errors.3368154697
Short name T601
Test name
Test status
Simulation time 2807942208 ps
CPU time 26.01 seconds
Started Jun 02 01:25:17 PM PDT 24
Finished Jun 02 01:25:43 PM PDT 24
Peak memory 218992 kb
Host smart-8494adae-5a49-420b-b23f-7c735e1013de
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368154697 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_e
rrors.3368154697
Directory /workspace/17.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_prog_failure.4217595123
Short name T416
Test name
Test status
Simulation time 947513119 ps
CPU time 3.7 seconds
Started Jun 02 01:25:19 PM PDT 24
Finished Jun 02 01:25:23 PM PDT 24
Peak memory 217932 kb
Host smart-14968a2f-d1ba-45ad-b41f-b0a11c582dd7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217595123 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jta
g_prog_failure.4217595123
Directory /workspace/17.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_smoke.1540388313
Short name T534
Test name
Test status
Simulation time 245724659 ps
CPU time 4.38 seconds
Started Jun 02 01:25:16 PM PDT 24
Finished Jun 02 01:25:21 PM PDT 24
Peak memory 217588 kb
Host smart-e070ea88-e376-4174-893c-0a5661db695b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540388313 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_smoke
.1540388313
Directory /workspace/17.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_failure.861878676
Short name T473
Test name
Test status
Simulation time 2169425410 ps
CPU time 81.75 seconds
Started Jun 02 01:25:19 PM PDT 24
Finished Jun 02 01:26:41 PM PDT 24
Peak memory 267356 kb
Host smart-178dd334-73b4-4a63-86a8-e7959cd03720
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861878676 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jta
g_state_failure.861878676
Directory /workspace/17.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_post_trans.3343771325
Short name T616
Test name
Test status
Simulation time 3550597906 ps
CPU time 16.29 seconds
Started Jun 02 01:25:18 PM PDT 24
Finished Jun 02 01:25:35 PM PDT 24
Peak memory 246000 kb
Host smart-e3894d4a-6dcd-4452-b365-52a0d3f155d2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343771325 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl
_jtag_state_post_trans.3343771325
Directory /workspace/17.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_prog_failure.3496151006
Short name T762
Test name
Test status
Simulation time 97186936 ps
CPU time 1.7 seconds
Started Jun 02 01:25:17 PM PDT 24
Finished Jun 02 01:25:19 PM PDT 24
Peak memory 217964 kb
Host smart-12231275-a461-4d78-9c64-92582303f018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496151006 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_prog_failure.3496151006
Directory /workspace/17.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_mubi.684978399
Short name T313
Test name
Test status
Simulation time 302600325 ps
CPU time 11.79 seconds
Started Jun 02 01:25:20 PM PDT 24
Finished Jun 02 01:25:32 PM PDT 24
Peak memory 218916 kb
Host smart-43b3f81c-f5a9-40f9-bbd5-5dd12f8f33dd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684978399 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_mubi.684978399
Directory /workspace/17.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_digest.1849541575
Short name T772
Test name
Test status
Simulation time 279522174 ps
CPU time 11.89 seconds
Started Jun 02 01:25:19 PM PDT 24
Finished Jun 02 01:25:31 PM PDT 24
Peak memory 217976 kb
Host smart-336b0752-7cb1-4c93-9b9d-bae583f56ba3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849541575 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_d
igest.1849541575
Directory /workspace/17.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_mux.1302905384
Short name T392
Test name
Test status
Simulation time 602672867 ps
CPU time 9.52 seconds
Started Jun 02 01:25:18 PM PDT 24
Finished Jun 02 01:25:28 PM PDT 24
Peak memory 218028 kb
Host smart-29a8c000-36d3-42cf-aa7a-6c5255d668be
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302905384 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_mux.
1302905384
Directory /workspace/17.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/17.lc_ctrl_security_escalation.2540865726
Short name T777
Test name
Test status
Simulation time 237469846 ps
CPU time 6.37 seconds
Started Jun 02 01:25:17 PM PDT 24
Finished Jun 02 01:25:24 PM PDT 24
Peak memory 218004 kb
Host smart-207fa37b-327d-4445-99ea-775ddb966683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540865726 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_security_escalation.2540865726
Directory /workspace/17.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/17.lc_ctrl_smoke.3273929331
Short name T705
Test name
Test status
Simulation time 41464070 ps
CPU time 2.99 seconds
Started Jun 02 01:25:18 PM PDT 24
Finished Jun 02 01:25:21 PM PDT 24
Peak memory 214592 kb
Host smart-4add9ed3-b6ee-49cc-b80c-334b9e7930b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273929331 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_smoke.3273929331
Directory /workspace/17.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_failure.894110053
Short name T437
Test name
Test status
Simulation time 580918441 ps
CPU time 36.21 seconds
Started Jun 02 01:25:19 PM PDT 24
Finished Jun 02 01:25:55 PM PDT 24
Peak memory 250728 kb
Host smart-6efda285-65c7-4569-8fae-b04863d123fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894110053 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_failure.894110053
Directory /workspace/17.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_post_trans.3585076650
Short name T208
Test name
Test status
Simulation time 83701885 ps
CPU time 7.86 seconds
Started Jun 02 01:25:21 PM PDT 24
Finished Jun 02 01:25:30 PM PDT 24
Peak memory 251004 kb
Host smart-fb3b25e5-3584-46cd-83d0-0701c73d654d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585076650 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_post_trans.3585076650
Directory /workspace/17.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_volatile_unlock_smoke.1411228307
Short name T643
Test name
Test status
Simulation time 34602772 ps
CPU time 0.88 seconds
Started Jun 02 01:25:17 PM PDT 24
Finished Jun 02 01:25:18 PM PDT 24
Peak memory 208764 kb
Host smart-afebb5e9-ce28-4159-aed3-a27eb3da91df
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411228307 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_c
trl_volatile_unlock_smoke.1411228307
Directory /workspace/17.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_alert_test.2456634572
Short name T693
Test name
Test status
Simulation time 72002858 ps
CPU time 1.01 seconds
Started Jun 02 01:25:24 PM PDT 24
Finished Jun 02 01:25:25 PM PDT 24
Peak memory 209512 kb
Host smart-658dd93c-e46a-4994-a8dc-635202619c6b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456634572 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_alert_test.2456634572
Directory /workspace/18.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.lc_ctrl_errors.478241512
Short name T380
Test name
Test status
Simulation time 3330367456 ps
CPU time 13.7 seconds
Started Jun 02 01:25:26 PM PDT 24
Finished Jun 02 01:25:40 PM PDT 24
Peak memory 219032 kb
Host smart-85c6fd78-ddf7-41dc-ae51-5633c0760d0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478241512 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_errors.478241512
Directory /workspace/18.lc_ctrl_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_access.1597578655
Short name T695
Test name
Test status
Simulation time 1527360153 ps
CPU time 5.07 seconds
Started Jun 02 01:25:24 PM PDT 24
Finished Jun 02 01:25:30 PM PDT 24
Peak memory 209524 kb
Host smart-d673f81e-e84c-4f70-ae17-ecd8247db0e1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597578655 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_access.1597578655
Directory /workspace/18.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_errors.2136334557
Short name T337
Test name
Test status
Simulation time 5474638486 ps
CPU time 21.52 seconds
Started Jun 02 01:25:29 PM PDT 24
Finished Jun 02 01:25:51 PM PDT 24
Peak memory 218496 kb
Host smart-cf0f9922-bd96-4d4e-91cb-c2b013db1c55
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136334557 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_e
rrors.2136334557
Directory /workspace/18.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_prog_failure.1796904118
Short name T342
Test name
Test status
Simulation time 1391133084 ps
CPU time 5.16 seconds
Started Jun 02 01:25:28 PM PDT 24
Finished Jun 02 01:25:33 PM PDT 24
Peak memory 217956 kb
Host smart-4ed6d725-313a-4b9b-bca7-6a6245303650
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796904118 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jta
g_prog_failure.1796904118
Directory /workspace/18.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_smoke.895942276
Short name T861
Test name
Test status
Simulation time 594903042 ps
CPU time 4.21 seconds
Started Jun 02 01:25:24 PM PDT 24
Finished Jun 02 01:25:29 PM PDT 24
Peak memory 217640 kb
Host smart-09af74b8-3ccf-456f-93c9-9ebefbd5b37f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895942276 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_smoke.
895942276
Directory /workspace/18.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_failure.3216711819
Short name T330
Test name
Test status
Simulation time 3140124468 ps
CPU time 95.08 seconds
Started Jun 02 01:25:25 PM PDT 24
Finished Jun 02 01:27:00 PM PDT 24
Peak memory 277260 kb
Host smart-61352a8e-cc76-4625-84dd-397db6975f4d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216711819 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jt
ag_state_failure.3216711819
Directory /workspace/18.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_post_trans.983327412
Short name T442
Test name
Test status
Simulation time 525744694 ps
CPU time 20.81 seconds
Started Jun 02 01:25:24 PM PDT 24
Finished Jun 02 01:25:46 PM PDT 24
Peak memory 250868 kb
Host smart-45f58ef5-4883-4925-9d9e-8aa96d82f632
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983327412 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_
jtag_state_post_trans.983327412
Directory /workspace/18.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_prog_failure.3115641359
Short name T397
Test name
Test status
Simulation time 109973466 ps
CPU time 3.1 seconds
Started Jun 02 01:25:25 PM PDT 24
Finished Jun 02 01:25:28 PM PDT 24
Peak memory 218300 kb
Host smart-f0d1aa73-3076-427f-bdeb-cf4c03ccee03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3115641359 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_prog_failure.3115641359
Directory /workspace/18.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_mubi.3714618211
Short name T659
Test name
Test status
Simulation time 673568891 ps
CPU time 13.19 seconds
Started Jun 02 01:25:26 PM PDT 24
Finished Jun 02 01:25:39 PM PDT 24
Peak memory 226088 kb
Host smart-d345b531-d318-4ccb-b622-04e870ef36ea
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714618211 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_mubi.3714618211
Directory /workspace/18.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_digest.1547526758
Short name T399
Test name
Test status
Simulation time 1713036768 ps
CPU time 19.45 seconds
Started Jun 02 01:25:26 PM PDT 24
Finished Jun 02 01:25:46 PM PDT 24
Peak memory 217944 kb
Host smart-d3923764-af39-4388-87b6-c36186c740e5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547526758 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_d
igest.1547526758
Directory /workspace/18.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/18.lc_ctrl_security_escalation.2183036241
Short name T264
Test name
Test status
Simulation time 306592686 ps
CPU time 9.93 seconds
Started Jun 02 01:25:25 PM PDT 24
Finished Jun 02 01:25:35 PM PDT 24
Peak memory 218080 kb
Host smart-678dead0-4ebf-41da-95d0-52eb261dfb55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183036241 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_security_escalation.2183036241
Directory /workspace/18.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/18.lc_ctrl_smoke.806165032
Short name T37
Test name
Test status
Simulation time 683704206 ps
CPU time 2.82 seconds
Started Jun 02 01:25:24 PM PDT 24
Finished Jun 02 01:25:27 PM PDT 24
Peak memory 214864 kb
Host smart-108d459f-2d3f-4a0b-9f78-e1e263d4eca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806165032 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_smoke.806165032
Directory /workspace/18.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_failure.3979138962
Short name T686
Test name
Test status
Simulation time 468245024 ps
CPU time 21.96 seconds
Started Jun 02 01:25:24 PM PDT 24
Finished Jun 02 01:25:46 PM PDT 24
Peak memory 250956 kb
Host smart-32863378-b01c-42a9-9902-929461756d49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979138962 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_failure.3979138962
Directory /workspace/18.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_post_trans.1190187223
Short name T863
Test name
Test status
Simulation time 85291608 ps
CPU time 6.95 seconds
Started Jun 02 01:25:25 PM PDT 24
Finished Jun 02 01:25:32 PM PDT 24
Peak memory 246692 kb
Host smart-31a0d896-f227-459d-91bd-0bc8b3d529fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190187223 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_post_trans.1190187223
Directory /workspace/18.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all.2287892888
Short name T545
Test name
Test status
Simulation time 6347277760 ps
CPU time 165.13 seconds
Started Jun 02 01:25:23 PM PDT 24
Finished Jun 02 01:28:08 PM PDT 24
Peak memory 275884 kb
Host smart-02395fb1-34c7-4df4-bcad-3af2fa77ce34
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287892888 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.lc_ctrl_stress_all.2287892888
Directory /workspace/18.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all_with_rand_reset.690019242
Short name T83
Test name
Test status
Simulation time 83712820713 ps
CPU time 8567.37 seconds
Started Jun 02 01:25:23 PM PDT 24
Finished Jun 02 03:48:12 PM PDT 24
Peak memory 644444 kb
Host smart-a66b3186-9a22-41a1-b384-bdb21bc7031d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=690019242 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_stress_all_with_rand_reset.690019242
Directory /workspace/18.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.lc_ctrl_volatile_unlock_smoke.3655466251
Short name T373
Test name
Test status
Simulation time 30226897 ps
CPU time 0.74 seconds
Started Jun 02 01:25:23 PM PDT 24
Finished Jun 02 01:25:24 PM PDT 24
Peak memory 208336 kb
Host smart-94782369-524c-49e0-b6bc-b36054885aaa
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655466251 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_c
trl_volatile_unlock_smoke.3655466251
Directory /workspace/18.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_alert_test.722590754
Short name T419
Test name
Test status
Simulation time 21778946 ps
CPU time 0.9 seconds
Started Jun 02 01:25:32 PM PDT 24
Finished Jun 02 01:25:33 PM PDT 24
Peak memory 208612 kb
Host smart-aa867449-e1c3-42f4-bc37-371027a9c3eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722590754 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_alert_test.722590754
Directory /workspace/19.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.lc_ctrl_errors.1023639257
Short name T813
Test name
Test status
Simulation time 245643063 ps
CPU time 12.5 seconds
Started Jun 02 01:25:27 PM PDT 24
Finished Jun 02 01:25:40 PM PDT 24
Peak memory 218016 kb
Host smart-b221414e-8e1d-4577-a11b-156173134744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023639257 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_errors.1023639257
Directory /workspace/19.lc_ctrl_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_access.1737020986
Short name T389
Test name
Test status
Simulation time 671481839 ps
CPU time 15.88 seconds
Started Jun 02 01:25:31 PM PDT 24
Finished Jun 02 01:25:48 PM PDT 24
Peak memory 209472 kb
Host smart-eb832f32-6736-44a7-b052-73548068cbdd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737020986 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_access.1737020986
Directory /workspace/19.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_errors.3456595713
Short name T730
Test name
Test status
Simulation time 2123155959 ps
CPU time 62.77 seconds
Started Jun 02 01:25:30 PM PDT 24
Finished Jun 02 01:26:33 PM PDT 24
Peak memory 218024 kb
Host smart-c02d8db0-227e-4f22-a216-37e1daa53b79
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456595713 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_e
rrors.3456595713
Directory /workspace/19.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_prog_failure.394646523
Short name T302
Test name
Test status
Simulation time 198842965 ps
CPU time 3.9 seconds
Started Jun 02 01:25:31 PM PDT 24
Finished Jun 02 01:25:36 PM PDT 24
Peak memory 217916 kb
Host smart-f237ac5e-20e6-4394-bb19-022196353f80
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394646523 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag
_prog_failure.394646523
Directory /workspace/19.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_smoke.297910300
Short name T712
Test name
Test status
Simulation time 193243416 ps
CPU time 2.24 seconds
Started Jun 02 01:25:31 PM PDT 24
Finished Jun 02 01:25:34 PM PDT 24
Peak memory 217664 kb
Host smart-32e10332-5cf1-4fc3-8ba3-df92cace06ea
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297910300 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_smoke.
297910300
Directory /workspace/19.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_failure.845675978
Short name T218
Test name
Test status
Simulation time 3843040985 ps
CPU time 40.4 seconds
Started Jun 02 01:25:32 PM PDT 24
Finished Jun 02 01:26:13 PM PDT 24
Peak memory 275580 kb
Host smart-cba67773-894d-4341-a629-14403d4a8770
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845675978 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jta
g_state_failure.845675978
Directory /workspace/19.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_post_trans.2828627053
Short name T798
Test name
Test status
Simulation time 749787298 ps
CPU time 12.95 seconds
Started Jun 02 01:25:32 PM PDT 24
Finished Jun 02 01:25:45 PM PDT 24
Peak memory 250936 kb
Host smart-ae126f20-da7f-46d2-a36d-99487a1c3cbc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828627053 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl
_jtag_state_post_trans.2828627053
Directory /workspace/19.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_prog_failure.3355757309
Short name T158
Test name
Test status
Simulation time 68324734 ps
CPU time 1.74 seconds
Started Jun 02 01:25:24 PM PDT 24
Finished Jun 02 01:25:26 PM PDT 24
Peak memory 218020 kb
Host smart-beb19668-bcae-4598-8258-03166217bb25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355757309 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_prog_failure.3355757309
Directory /workspace/19.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_mubi.4062231862
Short name T808
Test name
Test status
Simulation time 578218741 ps
CPU time 10.71 seconds
Started Jun 02 01:25:34 PM PDT 24
Finished Jun 02 01:25:45 PM PDT 24
Peak memory 218980 kb
Host smart-f660e299-dc1b-420c-92a6-260f7000c967
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062231862 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_mubi.4062231862
Directory /workspace/19.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_digest.3250871425
Short name T697
Test name
Test status
Simulation time 831375469 ps
CPU time 9.69 seconds
Started Jun 02 01:25:31 PM PDT 24
Finished Jun 02 01:25:42 PM PDT 24
Peak memory 226004 kb
Host smart-bde31bd9-35f3-49fa-afc1-90fa22509f9a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250871425 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_d
igest.3250871425
Directory /workspace/19.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_mux.167074107
Short name T253
Test name
Test status
Simulation time 518105923 ps
CPU time 8.89 seconds
Started Jun 02 01:25:32 PM PDT 24
Finished Jun 02 01:25:41 PM PDT 24
Peak memory 218020 kb
Host smart-d6af826b-b004-44ae-a6c5-50d534a60834
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167074107 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_mux.167074107
Directory /workspace/19.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/19.lc_ctrl_security_escalation.1516805161
Short name T223
Test name
Test status
Simulation time 1391433582 ps
CPU time 8.69 seconds
Started Jun 02 01:25:26 PM PDT 24
Finished Jun 02 01:25:35 PM PDT 24
Peak memory 218072 kb
Host smart-8973f61b-479e-469f-940b-5a54d30cfdf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516805161 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_security_escalation.1516805161
Directory /workspace/19.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/19.lc_ctrl_smoke.1959877108
Short name T612
Test name
Test status
Simulation time 61928811 ps
CPU time 1.23 seconds
Started Jun 02 01:25:28 PM PDT 24
Finished Jun 02 01:25:30 PM PDT 24
Peak memory 213420 kb
Host smart-0ed0f5c8-88ea-4f41-a429-a1b92cca5ed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959877108 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_smoke.1959877108
Directory /workspace/19.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_failure.2339559217
Short name T799
Test name
Test status
Simulation time 721568183 ps
CPU time 24.87 seconds
Started Jun 02 01:25:26 PM PDT 24
Finished Jun 02 01:25:51 PM PDT 24
Peak memory 251008 kb
Host smart-5afa5ecf-b16b-422b-805f-4f62387047b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339559217 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_failure.2339559217
Directory /workspace/19.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_post_trans.436230511
Short name T378
Test name
Test status
Simulation time 121645833 ps
CPU time 5.47 seconds
Started Jun 02 01:25:23 PM PDT 24
Finished Jun 02 01:25:29 PM PDT 24
Peak memory 222620 kb
Host smart-ac6a5494-deb6-492e-a201-66b0fb562b17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436230511 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_post_trans.436230511
Directory /workspace/19.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all.1636106836
Short name T837
Test name
Test status
Simulation time 1880503550 ps
CPU time 86.71 seconds
Started Jun 02 01:25:32 PM PDT 24
Finished Jun 02 01:26:59 PM PDT 24
Peak memory 277084 kb
Host smart-0512fea2-dbd7-4782-85af-0d9c849250e4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636106836 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.lc_ctrl_stress_all.1636106836
Directory /workspace/19.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.lc_ctrl_volatile_unlock_smoke.2020070018
Short name T242
Test name
Test status
Simulation time 15565439 ps
CPU time 1.08 seconds
Started Jun 02 01:25:27 PM PDT 24
Finished Jun 02 01:25:28 PM PDT 24
Peak memory 212784 kb
Host smart-d3869243-df86-434e-9d04-c73ebb6fd538
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020070018 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_c
trl_volatile_unlock_smoke.2020070018
Directory /workspace/19.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_alert_test.2205381583
Short name T568
Test name
Test status
Simulation time 54776813 ps
CPU time 0.92 seconds
Started Jun 02 01:24:02 PM PDT 24
Finished Jun 02 01:24:03 PM PDT 24
Peak memory 209516 kb
Host smart-5965b6d7-05f6-41f3-8522-49dd68fee794
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205381583 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_alert_test.2205381583
Directory /workspace/2.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.lc_ctrl_errors.2616511096
Short name T463
Test name
Test status
Simulation time 384904725 ps
CPU time 13.46 seconds
Started Jun 02 01:23:54 PM PDT 24
Finished Jun 02 01:24:08 PM PDT 24
Peak memory 218096 kb
Host smart-387084a4-95e8-427f-a47f-6516f52a94e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616511096 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_errors.2616511096
Directory /workspace/2.lc_ctrl_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_access.865524824
Short name T162
Test name
Test status
Simulation time 189745096 ps
CPU time 5.11 seconds
Started Jun 02 01:23:54 PM PDT 24
Finished Jun 02 01:24:00 PM PDT 24
Peak memory 209512 kb
Host smart-292e861c-bc19-4a79-9a33-e3712bec59f6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865524824 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_access.865524824
Directory /workspace/2.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_errors.181924349
Short name T433
Test name
Test status
Simulation time 1492692486 ps
CPU time 31.56 seconds
Started Jun 02 01:23:54 PM PDT 24
Finished Jun 02 01:24:26 PM PDT 24
Peak memory 218016 kb
Host smart-5431d75f-1e99-4df7-b552-40fefbd6124a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181924349 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_err
ors.181924349
Directory /workspace/2.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_priority.1751818552
Short name T429
Test name
Test status
Simulation time 433586178 ps
CPU time 1.95 seconds
Started Jun 02 01:23:53 PM PDT 24
Finished Jun 02 01:23:55 PM PDT 24
Peak memory 217748 kb
Host smart-06b15021-dd78-4717-9422-aca9c03ffb63
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751818552 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_priority.1
751818552
Directory /workspace/2.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_prog_failure.2725522241
Short name T456
Test name
Test status
Simulation time 369399613 ps
CPU time 11.34 seconds
Started Jun 02 01:23:54 PM PDT 24
Finished Jun 02 01:24:06 PM PDT 24
Peak memory 218020 kb
Host smart-a58e6bd9-ad3a-4ef7-af96-cc1c7825744d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725522241 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag
_prog_failure.2725522241
Directory /workspace/2.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_regwen_during_op.2379068011
Short name T770
Test name
Test status
Simulation time 2141495305 ps
CPU time 17.44 seconds
Started Jun 02 01:23:55 PM PDT 24
Finished Jun 02 01:24:13 PM PDT 24
Peak memory 217604 kb
Host smart-7a536835-01f2-49cf-a126-9564189c4733
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379068011 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_regwen_during_op.2379068011
Directory /workspace/2.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_smoke.2868094490
Short name T737
Test name
Test status
Simulation time 8267107964 ps
CPU time 10.93 seconds
Started Jun 02 01:23:54 PM PDT 24
Finished Jun 02 01:24:06 PM PDT 24
Peak memory 217720 kb
Host smart-7904fcf7-4eb4-4e9f-b96c-01a1431ea8f8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868094490 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_smoke.
2868094490
Directory /workspace/2.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_failure.4269569623
Short name T288
Test name
Test status
Simulation time 853862890 ps
CPU time 24.76 seconds
Started Jun 02 01:23:53 PM PDT 24
Finished Jun 02 01:24:18 PM PDT 24
Peak memory 250896 kb
Host smart-52290550-5c6e-4ac1-a62f-378e0b43e356
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269569623 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jta
g_state_failure.4269569623
Directory /workspace/2.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_post_trans.3549888937
Short name T384
Test name
Test status
Simulation time 1212544153 ps
CPU time 13.34 seconds
Started Jun 02 01:23:53 PM PDT 24
Finished Jun 02 01:24:07 PM PDT 24
Peak memory 250348 kb
Host smart-1560a53d-67ef-4a17-ad20-ff4f54cefd3a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549888937 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_state_post_trans.3549888937
Directory /workspace/2.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_prog_failure.322761423
Short name T333
Test name
Test status
Simulation time 90104259 ps
CPU time 2.42 seconds
Started Jun 02 01:23:53 PM PDT 24
Finished Jun 02 01:23:56 PM PDT 24
Peak memory 217996 kb
Host smart-4a77b92d-c6de-41af-bc9a-db81907d4d44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322761423 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_prog_failure.322761423
Directory /workspace/2.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_regwen_during_op.3818675022
Short name T511
Test name
Test status
Simulation time 519294603 ps
CPU time 22.52 seconds
Started Jun 02 01:23:53 PM PDT 24
Finished Jun 02 01:24:16 PM PDT 24
Peak memory 217684 kb
Host smart-a789ec51-2650-463f-aeb3-373a436ba6f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818675022 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_regwen_during_op.3818675022
Directory /workspace/2.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_mubi.3645682279
Short name T835
Test name
Test status
Simulation time 537604388 ps
CPU time 11.31 seconds
Started Jun 02 01:23:53 PM PDT 24
Finished Jun 02 01:24:04 PM PDT 24
Peak memory 225440 kb
Host smart-9a16dca5-aa04-472e-9887-5eea2c2c7344
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645682279 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_mubi.3645682279
Directory /workspace/2.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_digest.4291054556
Short name T258
Test name
Test status
Simulation time 5160829953 ps
CPU time 17.5 seconds
Started Jun 02 01:23:55 PM PDT 24
Finished Jun 02 01:24:13 PM PDT 24
Peak memory 218020 kb
Host smart-9dc126cd-55ad-462a-81b9-1acf0241d7ae
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291054556 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_di
gest.4291054556
Directory /workspace/2.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_mux.2505186859
Short name T293
Test name
Test status
Simulation time 394745337 ps
CPU time 8.24 seconds
Started Jun 02 01:23:54 PM PDT 24
Finished Jun 02 01:24:02 PM PDT 24
Peak memory 218044 kb
Host smart-63e9ebd6-2ca4-473c-81e6-ffd37830e136
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505186859 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_mux.2
505186859
Directory /workspace/2.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/2.lc_ctrl_security_escalation.757489893
Short name T609
Test name
Test status
Simulation time 218354370 ps
CPU time 7.4 seconds
Started Jun 02 01:23:54 PM PDT 24
Finished Jun 02 01:24:02 PM PDT 24
Peak memory 218152 kb
Host smart-82bbade6-6b05-42eb-b058-5ca5ddd33e13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757489893 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_security_escalation.757489893
Directory /workspace/2.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/2.lc_ctrl_smoke.654989894
Short name T198
Test name
Test status
Simulation time 118690926 ps
CPU time 6.24 seconds
Started Jun 02 01:23:54 PM PDT 24
Finished Jun 02 01:24:01 PM PDT 24
Peak memory 217680 kb
Host smart-0e5d2ada-2bd9-4758-87d3-39a1fa2732ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654989894 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_smoke.654989894
Directory /workspace/2.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_failure.4233453995
Short name T732
Test name
Test status
Simulation time 1508565943 ps
CPU time 37.54 seconds
Started Jun 02 01:23:56 PM PDT 24
Finished Jun 02 01:24:34 PM PDT 24
Peak memory 250936 kb
Host smart-4e0f67e9-4245-4f86-bc8f-3e3dd5921f7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233453995 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_failure.4233453995
Directory /workspace/2.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_post_trans.3399205214
Short name T604
Test name
Test status
Simulation time 331674992 ps
CPU time 8.01 seconds
Started Jun 02 01:23:54 PM PDT 24
Finished Jun 02 01:24:03 PM PDT 24
Peak memory 250936 kb
Host smart-0e5b7f7b-64dd-4b97-bf29-3b2ebf19b54c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399205214 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_post_trans.3399205214
Directory /workspace/2.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_volatile_unlock_smoke.1521687179
Short name T371
Test name
Test status
Simulation time 11977872 ps
CPU time 0.94 seconds
Started Jun 02 01:23:54 PM PDT 24
Finished Jun 02 01:23:56 PM PDT 24
Peak memory 208600 kb
Host smart-f3727d38-3d1e-475d-8999-4fa40dd319a1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521687179 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ct
rl_volatile_unlock_smoke.1521687179
Directory /workspace/2.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_alert_test.2385850149
Short name T657
Test name
Test status
Simulation time 15868260 ps
CPU time 1.05 seconds
Started Jun 02 01:25:33 PM PDT 24
Finished Jun 02 01:25:34 PM PDT 24
Peak memory 209500 kb
Host smart-28b20f56-1646-4bf1-a2ee-58fb76c0c933
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385850149 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_alert_test.2385850149
Directory /workspace/20.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.lc_ctrl_errors.1253119019
Short name T801
Test name
Test status
Simulation time 649882491 ps
CPU time 15.16 seconds
Started Jun 02 01:25:31 PM PDT 24
Finished Jun 02 01:25:46 PM PDT 24
Peak memory 218108 kb
Host smart-0c79a555-f064-431f-a665-601f31f63162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253119019 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_errors.1253119019
Directory /workspace/20.lc_ctrl_errors/latest

Test location /workspace/coverage/default/20.lc_ctrl_jtag_access.3226806114
Short name T648
Test name
Test status
Simulation time 1751933487 ps
CPU time 5.46 seconds
Started Jun 02 01:25:35 PM PDT 24
Finished Jun 02 01:25:41 PM PDT 24
Peak memory 209472 kb
Host smart-26df549f-93f4-4e99-a1e1-7256e83308a7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226806114 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_jtag_access.3226806114
Directory /workspace/20.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/20.lc_ctrl_prog_failure.2061168447
Short name T255
Test name
Test status
Simulation time 83289759 ps
CPU time 2.1 seconds
Started Jun 02 01:25:31 PM PDT 24
Finished Jun 02 01:25:34 PM PDT 24
Peak memory 217876 kb
Host smart-4fcea524-e9a6-4161-95de-82d32d0e1566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061168447 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_prog_failure.2061168447
Directory /workspace/20.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_digest.2664642289
Short name T183
Test name
Test status
Simulation time 504530684 ps
CPU time 11.42 seconds
Started Jun 02 01:25:31 PM PDT 24
Finished Jun 02 01:25:43 PM PDT 24
Peak memory 217956 kb
Host smart-ab3bb880-58af-4b59-88e3-3ec2cd7a7616
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664642289 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_d
igest.2664642289
Directory /workspace/20.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_mux.2399998411
Short name T661
Test name
Test status
Simulation time 425343200 ps
CPU time 14.33 seconds
Started Jun 02 01:25:33 PM PDT 24
Finished Jun 02 01:25:48 PM PDT 24
Peak memory 218048 kb
Host smart-2b39b4f0-b799-44e4-abac-deca1dc017a1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399998411 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_mux.
2399998411
Directory /workspace/20.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/20.lc_ctrl_security_escalation.70746854
Short name T656
Test name
Test status
Simulation time 288562492 ps
CPU time 7.77 seconds
Started Jun 02 01:25:30 PM PDT 24
Finished Jun 02 01:25:38 PM PDT 24
Peak memory 218084 kb
Host smart-f00d9f8a-231d-424a-905c-398fc7a6c8a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70746854 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_security_escalation.70746854
Directory /workspace/20.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/20.lc_ctrl_smoke.1360557092
Short name T386
Test name
Test status
Simulation time 25798848 ps
CPU time 1.16 seconds
Started Jun 02 01:25:32 PM PDT 24
Finished Jun 02 01:25:34 PM PDT 24
Peak memory 217672 kb
Host smart-5bbfbb54-0c58-4cc0-b264-7c53a7a36765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360557092 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_smoke.1360557092
Directory /workspace/20.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_failure.1364474749
Short name T338
Test name
Test status
Simulation time 2299963194 ps
CPU time 24.5 seconds
Started Jun 02 01:25:33 PM PDT 24
Finished Jun 02 01:25:58 PM PDT 24
Peak memory 251000 kb
Host smart-6e554ca5-cf8e-44b6-ad5f-a251a0ab4579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364474749 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_failure.1364474749
Directory /workspace/20.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_post_trans.3749168079
Short name T15
Test name
Test status
Simulation time 251308465 ps
CPU time 3.59 seconds
Started Jun 02 01:25:31 PM PDT 24
Finished Jun 02 01:25:35 PM PDT 24
Peak memory 222780 kb
Host smart-af62c41b-228f-47a5-95e6-1655245d63b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749168079 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_post_trans.3749168079
Directory /workspace/20.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/20.lc_ctrl_volatile_unlock_smoke.3825896703
Short name T469
Test name
Test status
Simulation time 27604490 ps
CPU time 0.99 seconds
Started Jun 02 01:25:32 PM PDT 24
Finished Jun 02 01:25:33 PM PDT 24
Peak memory 212772 kb
Host smart-95c8fec4-1eaa-4028-8732-09a4c7dd8e0f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825896703 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_c
trl_volatile_unlock_smoke.3825896703
Directory /workspace/20.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_alert_test.3442145880
Short name T420
Test name
Test status
Simulation time 47785507 ps
CPU time 0.85 seconds
Started Jun 02 01:25:38 PM PDT 24
Finished Jun 02 01:25:39 PM PDT 24
Peak memory 208444 kb
Host smart-89be02db-4603-442c-bfbe-d69610be25c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442145880 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_alert_test.3442145880
Directory /workspace/21.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.lc_ctrl_errors.1790792932
Short name T394
Test name
Test status
Simulation time 773925233 ps
CPU time 15.55 seconds
Started Jun 02 01:25:38 PM PDT 24
Finished Jun 02 01:25:54 PM PDT 24
Peak memory 218024 kb
Host smart-b1630684-cba0-4d26-9459-b4710031e362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790792932 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_errors.1790792932
Directory /workspace/21.lc_ctrl_errors/latest

Test location /workspace/coverage/default/21.lc_ctrl_jtag_access.3373905878
Short name T9
Test name
Test status
Simulation time 170862914 ps
CPU time 2.9 seconds
Started Jun 02 01:25:38 PM PDT 24
Finished Jun 02 01:25:41 PM PDT 24
Peak memory 216980 kb
Host smart-06934bd7-1b67-421d-84a8-3ae717641207
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373905878 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_jtag_access.3373905878
Directory /workspace/21.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/21.lc_ctrl_prog_failure.790639818
Short name T738
Test name
Test status
Simulation time 65722980 ps
CPU time 3.56 seconds
Started Jun 02 01:25:39 PM PDT 24
Finished Jun 02 01:25:43 PM PDT 24
Peak memory 217968 kb
Host smart-cd8cc3e1-3d30-41ab-ad66-820f48da451a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790639818 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_prog_failure.790639818
Directory /workspace/21.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_mubi.2436205853
Short name T424
Test name
Test status
Simulation time 288736943 ps
CPU time 9.51 seconds
Started Jun 02 01:25:37 PM PDT 24
Finished Jun 02 01:25:47 PM PDT 24
Peak memory 226124 kb
Host smart-5364d0b0-fcb3-4ac3-972f-02e1030303a4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436205853 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_mubi.2436205853
Directory /workspace/21.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_digest.1650282758
Short name T687
Test name
Test status
Simulation time 702127348 ps
CPU time 17.34 seconds
Started Jun 02 01:25:37 PM PDT 24
Finished Jun 02 01:25:55 PM PDT 24
Peak memory 217908 kb
Host smart-188d41c2-fd68-44d4-bd7d-3f5baefe6f06
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650282758 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_d
igest.1650282758
Directory /workspace/21.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_mux.403260207
Short name T505
Test name
Test status
Simulation time 569954479 ps
CPU time 8.29 seconds
Started Jun 02 01:25:39 PM PDT 24
Finished Jun 02 01:25:47 PM PDT 24
Peak memory 218040 kb
Host smart-f22fdb1a-8d68-4a05-a078-34e5e4d5156e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403260207 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_mux.403260207
Directory /workspace/21.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/21.lc_ctrl_security_escalation.199766374
Short name T844
Test name
Test status
Simulation time 227488763 ps
CPU time 9.62 seconds
Started Jun 02 01:25:40 PM PDT 24
Finished Jun 02 01:25:50 PM PDT 24
Peak memory 224756 kb
Host smart-db162fe4-a391-40fa-ad8f-c699389c6a16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199766374 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_security_escalation.199766374
Directory /workspace/21.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/21.lc_ctrl_smoke.1983949296
Short name T80
Test name
Test status
Simulation time 77794644 ps
CPU time 2.59 seconds
Started Jun 02 01:25:41 PM PDT 24
Finished Jun 02 01:25:44 PM PDT 24
Peak memory 214280 kb
Host smart-4da8fae9-e1a1-4817-8481-e561de81ea9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983949296 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_smoke.1983949296
Directory /workspace/21.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_failure.115192370
Short name T746
Test name
Test status
Simulation time 267796329 ps
CPU time 30.05 seconds
Started Jun 02 01:25:39 PM PDT 24
Finished Jun 02 01:26:09 PM PDT 24
Peak memory 250992 kb
Host smart-7bb34cc6-6dc9-449f-80a6-1b3ef434efb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115192370 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_failure.115192370
Directory /workspace/21.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_post_trans.366021546
Short name T633
Test name
Test status
Simulation time 435715307 ps
CPU time 8.19 seconds
Started Jun 02 01:25:38 PM PDT 24
Finished Jun 02 01:25:47 PM PDT 24
Peak memory 247072 kb
Host smart-6754c8b0-29e0-4e09-8316-1ea724c2391e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366021546 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_post_trans.366021546
Directory /workspace/21.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/21.lc_ctrl_stress_all.2609706273
Short name T654
Test name
Test status
Simulation time 7422158544 ps
CPU time 59.89 seconds
Started Jun 02 01:25:40 PM PDT 24
Finished Jun 02 01:26:40 PM PDT 24
Peak memory 246840 kb
Host smart-2d7a7b21-fab8-4caf-a23f-fa93e6369eab
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609706273 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.lc_ctrl_stress_all.2609706273
Directory /workspace/21.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.lc_ctrl_stress_all_with_rand_reset.1183093589
Short name T810
Test name
Test status
Simulation time 6549906052 ps
CPU time 155.27 seconds
Started Jun 02 01:25:39 PM PDT 24
Finished Jun 02 01:28:14 PM PDT 24
Peak memory 283912 kb
Host smart-352d3002-eba6-4f0e-a451-e03995c34388
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1183093589 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_stress_all_with_rand_reset.1183093589
Directory /workspace/21.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.lc_ctrl_volatile_unlock_smoke.2538902556
Short name T237
Test name
Test status
Simulation time 11615145 ps
CPU time 1.05 seconds
Started Jun 02 01:25:39 PM PDT 24
Finished Jun 02 01:25:40 PM PDT 24
Peak memory 211504 kb
Host smart-f2e99ad4-5775-45d3-9158-914ed133c3e7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538902556 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_c
trl_volatile_unlock_smoke.2538902556
Directory /workspace/21.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_alert_test.1243881872
Short name T366
Test name
Test status
Simulation time 49639160 ps
CPU time 0.98 seconds
Started Jun 02 01:25:44 PM PDT 24
Finished Jun 02 01:25:46 PM PDT 24
Peak memory 208692 kb
Host smart-bdc649b2-2253-4f49-a632-6b1dbec00dd9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243881872 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_alert_test.1243881872
Directory /workspace/22.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.lc_ctrl_errors.4118542527
Short name T829
Test name
Test status
Simulation time 719752624 ps
CPU time 10.06 seconds
Started Jun 02 01:25:40 PM PDT 24
Finished Jun 02 01:25:50 PM PDT 24
Peak memory 217988 kb
Host smart-b1358aa2-a7e1-4f0a-8c23-8a3f01d232c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118542527 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_errors.4118542527
Directory /workspace/22.lc_ctrl_errors/latest

Test location /workspace/coverage/default/22.lc_ctrl_jtag_access.2255478012
Short name T26
Test name
Test status
Simulation time 617243039 ps
CPU time 6.96 seconds
Started Jun 02 01:25:44 PM PDT 24
Finished Jun 02 01:25:51 PM PDT 24
Peak memory 209764 kb
Host smart-516436a5-ac65-473c-9b81-c6ee6faf26c4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255478012 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_jtag_access.2255478012
Directory /workspace/22.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/22.lc_ctrl_prog_failure.2040111360
Short name T65
Test name
Test status
Simulation time 65379094 ps
CPU time 2.07 seconds
Started Jun 02 01:25:39 PM PDT 24
Finished Jun 02 01:25:42 PM PDT 24
Peak memory 218092 kb
Host smart-32793dd2-2afe-4296-890d-b2fbaf53c239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040111360 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_prog_failure.2040111360
Directory /workspace/22.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_mubi.623184652
Short name T542
Test name
Test status
Simulation time 315500107 ps
CPU time 15.29 seconds
Started Jun 02 01:25:50 PM PDT 24
Finished Jun 02 01:26:06 PM PDT 24
Peak memory 226108 kb
Host smart-59f77bdd-1224-424e-9aa8-4fd49ab5b26e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623184652 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_mubi.623184652
Directory /workspace/22.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_digest.4240743433
Short name T761
Test name
Test status
Simulation time 1272429685 ps
CPU time 13.04 seconds
Started Jun 02 01:25:45 PM PDT 24
Finished Jun 02 01:25:59 PM PDT 24
Peak memory 226040 kb
Host smart-ae333bfd-13ba-4b35-ba5a-29684af76170
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240743433 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_d
igest.4240743433
Directory /workspace/22.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_mux.2938928242
Short name T376
Test name
Test status
Simulation time 1130908657 ps
CPU time 7.39 seconds
Started Jun 02 01:25:45 PM PDT 24
Finished Jun 02 01:25:53 PM PDT 24
Peak memory 218000 kb
Host smart-2d2dc746-ce85-4053-8a55-3f719d333bae
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938928242 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_mux.
2938928242
Directory /workspace/22.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/22.lc_ctrl_security_escalation.890172729
Short name T679
Test name
Test status
Simulation time 625608573 ps
CPU time 12.36 seconds
Started Jun 02 01:25:38 PM PDT 24
Finished Jun 02 01:25:50 PM PDT 24
Peak memory 218136 kb
Host smart-208a2c07-97bc-4bfa-9429-54d5a012d302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890172729 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_security_escalation.890172729
Directory /workspace/22.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/22.lc_ctrl_smoke.4220551087
Short name T300
Test name
Test status
Simulation time 82624333 ps
CPU time 1.51 seconds
Started Jun 02 01:25:40 PM PDT 24
Finished Jun 02 01:25:42 PM PDT 24
Peak memory 213652 kb
Host smart-8f27f1a6-a526-4565-943b-e43043733710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220551087 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_smoke.4220551087
Directory /workspace/22.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_failure.1706783327
Short name T591
Test name
Test status
Simulation time 184005459 ps
CPU time 25.13 seconds
Started Jun 02 01:25:36 PM PDT 24
Finished Jun 02 01:26:02 PM PDT 24
Peak memory 247484 kb
Host smart-a81a99c2-8402-4ebc-9be6-c975c6ebd064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706783327 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_failure.1706783327
Directory /workspace/22.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_post_trans.4117873955
Short name T501
Test name
Test status
Simulation time 107040794 ps
CPU time 6.08 seconds
Started Jun 02 01:25:40 PM PDT 24
Finished Jun 02 01:25:46 PM PDT 24
Peak memory 247340 kb
Host smart-5148b599-6de5-4a40-bc6c-6888229aca6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117873955 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_post_trans.4117873955
Directory /workspace/22.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/22.lc_ctrl_stress_all.2846323295
Short name T611
Test name
Test status
Simulation time 40961573980 ps
CPU time 618.52 seconds
Started Jun 02 01:25:44 PM PDT 24
Finished Jun 02 01:36:04 PM PDT 24
Peak memory 447560 kb
Host smart-11ad0c5b-ee40-4907-844f-e3cd6fd95155
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846323295 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.lc_ctrl_stress_all.2846323295
Directory /workspace/22.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.lc_ctrl_volatile_unlock_smoke.914081464
Short name T310
Test name
Test status
Simulation time 42199702 ps
CPU time 1.01 seconds
Started Jun 02 01:25:40 PM PDT 24
Finished Jun 02 01:25:41 PM PDT 24
Peak memory 211348 kb
Host smart-4de65072-29fc-4018-864e-4bddbb1672c7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914081464 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ct
rl_volatile_unlock_smoke.914081464
Directory /workspace/22.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_alert_test.1440201839
Short name T682
Test name
Test status
Simulation time 16965995 ps
CPU time 1.09 seconds
Started Jun 02 01:25:46 PM PDT 24
Finished Jun 02 01:25:48 PM PDT 24
Peak memory 209520 kb
Host smart-a93f4b48-0f25-4c5b-b7f1-265a29fbc022
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440201839 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_alert_test.1440201839
Directory /workspace/23.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.lc_ctrl_errors.2165000981
Short name T547
Test name
Test status
Simulation time 824003712 ps
CPU time 10.85 seconds
Started Jun 02 01:25:44 PM PDT 24
Finished Jun 02 01:25:55 PM PDT 24
Peak memory 218016 kb
Host smart-3f80aa22-242b-4ca1-9ee8-77811962d1ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165000981 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_errors.2165000981
Directory /workspace/23.lc_ctrl_errors/latest

Test location /workspace/coverage/default/23.lc_ctrl_jtag_access.4257594262
Short name T618
Test name
Test status
Simulation time 3059519806 ps
CPU time 18.54 seconds
Started Jun 02 01:25:46 PM PDT 24
Finished Jun 02 01:26:05 PM PDT 24
Peak memory 217732 kb
Host smart-47f9bbd6-938f-4107-9fcd-e12a0db33a0c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257594262 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_jtag_access.4257594262
Directory /workspace/23.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/23.lc_ctrl_prog_failure.3088037137
Short name T819
Test name
Test status
Simulation time 73041664 ps
CPU time 3.43 seconds
Started Jun 02 01:25:50 PM PDT 24
Finished Jun 02 01:25:54 PM PDT 24
Peak memory 218004 kb
Host smart-3b093472-28fd-4edd-8bf6-23efa5fe8d54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088037137 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_prog_failure.3088037137
Directory /workspace/23.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_mubi.1196850171
Short name T36
Test name
Test status
Simulation time 2307973181 ps
CPU time 15.57 seconds
Started Jun 02 01:25:51 PM PDT 24
Finished Jun 02 01:26:07 PM PDT 24
Peak memory 218076 kb
Host smart-82cc22c8-3dfe-4158-b79f-bdaa596c261d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196850171 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_mubi.1196850171
Directory /workspace/23.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_digest.3178364760
Short name T536
Test name
Test status
Simulation time 258727574 ps
CPU time 9.19 seconds
Started Jun 02 01:25:45 PM PDT 24
Finished Jun 02 01:25:54 PM PDT 24
Peak memory 217948 kb
Host smart-5a48a004-1e93-4136-8509-b3f73e076954
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178364760 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_d
igest.3178364760
Directory /workspace/23.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_mux.1351671377
Short name T400
Test name
Test status
Simulation time 1051202745 ps
CPU time 12.05 seconds
Started Jun 02 01:25:51 PM PDT 24
Finished Jun 02 01:26:03 PM PDT 24
Peak memory 218088 kb
Host smart-3b047394-b8b5-48d7-abca-f8c64cacbb0c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351671377 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_mux.
1351671377
Directory /workspace/23.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/23.lc_ctrl_security_escalation.1099790447
Short name T427
Test name
Test status
Simulation time 647455782 ps
CPU time 11.47 seconds
Started Jun 02 01:25:45 PM PDT 24
Finished Jun 02 01:25:57 PM PDT 24
Peak memory 217980 kb
Host smart-379964ad-393f-4429-8670-4980bad89563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099790447 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_security_escalation.1099790447
Directory /workspace/23.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/23.lc_ctrl_smoke.3247101982
Short name T292
Test name
Test status
Simulation time 126437165 ps
CPU time 2.31 seconds
Started Jun 02 01:25:45 PM PDT 24
Finished Jun 02 01:25:47 PM PDT 24
Peak memory 214212 kb
Host smart-65658fcd-1336-49d0-9d84-8b2b2e2167d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247101982 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_smoke.3247101982
Directory /workspace/23.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_failure.3059295290
Short name T603
Test name
Test status
Simulation time 1372035931 ps
CPU time 29.66 seconds
Started Jun 02 01:25:45 PM PDT 24
Finished Jun 02 01:26:15 PM PDT 24
Peak memory 250936 kb
Host smart-d7099833-aabf-4e2e-9e5b-ee3624c01573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059295290 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_failure.3059295290
Directory /workspace/23.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_post_trans.3143455821
Short name T496
Test name
Test status
Simulation time 96612584 ps
CPU time 7.76 seconds
Started Jun 02 01:25:44 PM PDT 24
Finished Jun 02 01:25:52 PM PDT 24
Peak memory 250984 kb
Host smart-c772d8bb-79f3-435b-aa9e-07647449e8d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143455821 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_post_trans.3143455821
Directory /workspace/23.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all.881752081
Short name T711
Test name
Test status
Simulation time 30123740822 ps
CPU time 104.72 seconds
Started Jun 02 01:25:46 PM PDT 24
Finished Jun 02 01:27:32 PM PDT 24
Peak memory 270356 kb
Host smart-dd8ddf86-ad12-467f-b783-a775acf163c5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881752081 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.lc_ctrl_stress_all.881752081
Directory /workspace/23.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.lc_ctrl_volatile_unlock_smoke.2292907864
Short name T299
Test name
Test status
Simulation time 13213926 ps
CPU time 0.95 seconds
Started Jun 02 01:25:46 PM PDT 24
Finished Jun 02 01:25:48 PM PDT 24
Peak memory 208636 kb
Host smart-31911c59-f797-4dc6-80f2-15d76aad4b2f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292907864 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_c
trl_volatile_unlock_smoke.2292907864
Directory /workspace/23.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_errors.2930047508
Short name T487
Test name
Test status
Simulation time 224790176 ps
CPU time 9.41 seconds
Started Jun 02 01:25:45 PM PDT 24
Finished Jun 02 01:25:55 PM PDT 24
Peak memory 218032 kb
Host smart-625892f9-080b-48c4-84a6-e4959c914756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930047508 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_errors.2930047508
Directory /workspace/24.lc_ctrl_errors/latest

Test location /workspace/coverage/default/24.lc_ctrl_jtag_access.974527693
Short name T325
Test name
Test status
Simulation time 614002696 ps
CPU time 4.2 seconds
Started Jun 02 01:25:53 PM PDT 24
Finished Jun 02 01:25:58 PM PDT 24
Peak memory 209476 kb
Host smart-e325a7b7-2dd5-40e1-9605-656c46b6bbeb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974527693 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_jtag_access.974527693
Directory /workspace/24.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/24.lc_ctrl_prog_failure.1520502277
Short name T297
Test name
Test status
Simulation time 167369096 ps
CPU time 2.17 seconds
Started Jun 02 01:25:46 PM PDT 24
Finished Jun 02 01:25:49 PM PDT 24
Peak memory 218004 kb
Host smart-30285750-8df1-4a69-8866-a09d341ed5e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520502277 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_prog_failure.1520502277
Directory /workspace/24.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_mubi.1269956325
Short name T340
Test name
Test status
Simulation time 581257712 ps
CPU time 8.94 seconds
Started Jun 02 01:25:52 PM PDT 24
Finished Jun 02 01:26:01 PM PDT 24
Peak memory 218152 kb
Host smart-eaa7a41b-7461-4997-9af4-6a88ce3fc1c5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269956325 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_mubi.1269956325
Directory /workspace/24.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_digest.2474083915
Short name T481
Test name
Test status
Simulation time 1219156761 ps
CPU time 17.63 seconds
Started Jun 02 01:25:52 PM PDT 24
Finished Jun 02 01:26:10 PM PDT 24
Peak memory 217944 kb
Host smart-a6564d9a-6254-465a-b1aa-07c2050712cb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474083915 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_d
igest.2474083915
Directory /workspace/24.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_mux.1025000692
Short name T200
Test name
Test status
Simulation time 940118417 ps
CPU time 7.86 seconds
Started Jun 02 01:25:53 PM PDT 24
Finished Jun 02 01:26:02 PM PDT 24
Peak memory 218088 kb
Host smart-dd1d4f33-5994-41c5-9358-fdc53b26aa54
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025000692 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_mux.
1025000692
Directory /workspace/24.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/24.lc_ctrl_security_escalation.3863472160
Short name T443
Test name
Test status
Simulation time 1083133432 ps
CPU time 7.64 seconds
Started Jun 02 01:25:46 PM PDT 24
Finished Jun 02 01:25:54 PM PDT 24
Peak memory 218068 kb
Host smart-3719bae6-3557-4d75-a13d-ae932990b825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863472160 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_security_escalation.3863472160
Directory /workspace/24.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/24.lc_ctrl_smoke.87725667
Short name T531
Test name
Test status
Simulation time 188993651 ps
CPU time 3.44 seconds
Started Jun 02 01:25:49 PM PDT 24
Finished Jun 02 01:25:52 PM PDT 24
Peak memory 217692 kb
Host smart-379d03be-0320-458d-8750-267a293f96e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87725667 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_smoke.87725667
Directory /workspace/24.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_failure.2960065039
Short name T193
Test name
Test status
Simulation time 931244119 ps
CPU time 24.68 seconds
Started Jun 02 01:25:46 PM PDT 24
Finished Jun 02 01:26:11 PM PDT 24
Peak memory 250724 kb
Host smart-aaa0593f-582b-4c33-8e79-3714514d84d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960065039 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_failure.2960065039
Directory /workspace/24.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_post_trans.1857138227
Short name T516
Test name
Test status
Simulation time 198076273 ps
CPU time 7.66 seconds
Started Jun 02 01:25:45 PM PDT 24
Finished Jun 02 01:25:53 PM PDT 24
Peak memory 250740 kb
Host smart-df30f8a2-92bf-47ae-bbd9-4fd65a054485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857138227 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_post_trans.1857138227
Directory /workspace/24.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all.4029290027
Short name T544
Test name
Test status
Simulation time 8240662400 ps
CPU time 55.79 seconds
Started Jun 02 01:25:52 PM PDT 24
Finished Jun 02 01:26:48 PM PDT 24
Peak memory 250980 kb
Host smart-71a4c03e-ffdc-469f-a78d-e5b7d2847c46
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029290027 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.lc_ctrl_stress_all.4029290027
Directory /workspace/24.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all_with_rand_reset.3841816260
Short name T181
Test name
Test status
Simulation time 47554302074 ps
CPU time 951.65 seconds
Started Jun 02 01:25:53 PM PDT 24
Finished Jun 02 01:41:45 PM PDT 24
Peak memory 513324 kb
Host smart-22871534-5095-4915-bc4a-bf18a845d32c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3841816260 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_stress_all_with_rand_reset.3841816260
Directory /workspace/24.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.lc_ctrl_volatile_unlock_smoke.3484520766
Short name T748
Test name
Test status
Simulation time 35792888 ps
CPU time 0.85 seconds
Started Jun 02 01:25:48 PM PDT 24
Finished Jun 02 01:25:50 PM PDT 24
Peak memory 208540 kb
Host smart-b978cd84-7081-45bf-bd8b-891edbb6607f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484520766 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_c
trl_volatile_unlock_smoke.3484520766
Directory /workspace/24.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_alert_test.296470383
Short name T89
Test name
Test status
Simulation time 29321086 ps
CPU time 1.33 seconds
Started Jun 02 01:25:52 PM PDT 24
Finished Jun 02 01:25:54 PM PDT 24
Peak memory 208704 kb
Host smart-75fa8c33-2908-41b4-85ce-75d59621c2ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296470383 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_alert_test.296470383
Directory /workspace/25.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.lc_ctrl_errors.3593795789
Short name T199
Test name
Test status
Simulation time 233978618 ps
CPU time 9.91 seconds
Started Jun 02 01:25:53 PM PDT 24
Finished Jun 02 01:26:03 PM PDT 24
Peak memory 218088 kb
Host smart-7998f8e2-ee7f-473c-bf36-e7e1152566fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593795789 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_errors.3593795789
Directory /workspace/25.lc_ctrl_errors/latest

Test location /workspace/coverage/default/25.lc_ctrl_jtag_access.3740802452
Short name T29
Test name
Test status
Simulation time 543218635 ps
CPU time 4.34 seconds
Started Jun 02 01:25:53 PM PDT 24
Finished Jun 02 01:25:58 PM PDT 24
Peak memory 209528 kb
Host smart-f9d85e38-88d9-4610-90ce-6fa0ddb5fdce
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740802452 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_jtag_access.3740802452
Directory /workspace/25.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/25.lc_ctrl_prog_failure.791276089
Short name T653
Test name
Test status
Simulation time 52073843 ps
CPU time 2.63 seconds
Started Jun 02 01:25:52 PM PDT 24
Finished Jun 02 01:25:56 PM PDT 24
Peak memory 218036 kb
Host smart-019e2722-1e59-4768-8754-d630f687cb22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791276089 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_prog_failure.791276089
Directory /workspace/25.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_mubi.1932141667
Short name T187
Test name
Test status
Simulation time 354651104 ps
CPU time 12.43 seconds
Started Jun 02 01:25:58 PM PDT 24
Finished Jun 02 01:26:11 PM PDT 24
Peak memory 218952 kb
Host smart-b0a80066-f336-4288-a481-d3cd216e1ace
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932141667 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_mubi.1932141667
Directory /workspace/25.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_digest.2961107199
Short name T403
Test name
Test status
Simulation time 394920735 ps
CPU time 12.51 seconds
Started Jun 02 01:25:52 PM PDT 24
Finished Jun 02 01:26:05 PM PDT 24
Peak memory 226052 kb
Host smart-6395218c-25ea-431d-923c-f06b5964ca7b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961107199 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_d
igest.2961107199
Directory /workspace/25.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_mux.1321482252
Short name T323
Test name
Test status
Simulation time 242343559 ps
CPU time 8.88 seconds
Started Jun 02 01:25:52 PM PDT 24
Finished Jun 02 01:26:02 PM PDT 24
Peak memory 217976 kb
Host smart-480ad1d2-06b7-46c0-b900-14c95ae0625e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321482252 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_mux.
1321482252
Directory /workspace/25.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/25.lc_ctrl_security_escalation.3950603698
Short name T62
Test name
Test status
Simulation time 404044660 ps
CPU time 9.53 seconds
Started Jun 02 01:25:52 PM PDT 24
Finished Jun 02 01:26:02 PM PDT 24
Peak memory 218092 kb
Host smart-90b028c4-8342-4683-96e1-0f1c3c15d134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950603698 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_security_escalation.3950603698
Directory /workspace/25.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/25.lc_ctrl_smoke.3450598445
Short name T580
Test name
Test status
Simulation time 237977440 ps
CPU time 2.81 seconds
Started Jun 02 01:25:53 PM PDT 24
Finished Jun 02 01:25:56 PM PDT 24
Peak memory 217760 kb
Host smart-68b663f7-0bc2-40f7-a78d-e7e390e976cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450598445 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_smoke.3450598445
Directory /workspace/25.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_failure.3710174072
Short name T576
Test name
Test status
Simulation time 1190501823 ps
CPU time 28.94 seconds
Started Jun 02 01:25:52 PM PDT 24
Finished Jun 02 01:26:22 PM PDT 24
Peak memory 250948 kb
Host smart-a3575cce-b1fd-4cb0-b8c2-1dde1b00a2e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710174072 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_failure.3710174072
Directory /workspace/25.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_post_trans.1844507016
Short name T710
Test name
Test status
Simulation time 689499257 ps
CPU time 6.8 seconds
Started Jun 02 01:25:50 PM PDT 24
Finished Jun 02 01:25:58 PM PDT 24
Peak memory 246188 kb
Host smart-65893afa-a78a-4008-89c9-e6cdd94c84b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844507016 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_post_trans.1844507016
Directory /workspace/25.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/25.lc_ctrl_stress_all.287785025
Short name T219
Test name
Test status
Simulation time 8696875797 ps
CPU time 132.34 seconds
Started Jun 02 01:25:51 PM PDT 24
Finished Jun 02 01:28:04 PM PDT 24
Peak memory 250760 kb
Host smart-81251d81-6957-4e8d-925c-a384bacdc878
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287785025 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.lc_ctrl_stress_all.287785025
Directory /workspace/25.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.lc_ctrl_volatile_unlock_smoke.3441482358
Short name T245
Test name
Test status
Simulation time 13828576 ps
CPU time 0.81 seconds
Started Jun 02 01:25:55 PM PDT 24
Finished Jun 02 01:25:56 PM PDT 24
Peak memory 208700 kb
Host smart-fdf054b7-437a-434e-a56f-62d1774e1b3a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441482358 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_c
trl_volatile_unlock_smoke.3441482358
Directory /workspace/25.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_alert_test.1924029146
Short name T849
Test name
Test status
Simulation time 21823368 ps
CPU time 1 seconds
Started Jun 02 01:25:58 PM PDT 24
Finished Jun 02 01:25:59 PM PDT 24
Peak memory 209508 kb
Host smart-6f318723-5b58-4413-b264-215415627e02
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924029146 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_alert_test.1924029146
Directory /workspace/26.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.lc_ctrl_errors.3002721443
Short name T41
Test name
Test status
Simulation time 1795699652 ps
CPU time 26.64 seconds
Started Jun 02 01:25:53 PM PDT 24
Finished Jun 02 01:26:20 PM PDT 24
Peak memory 217952 kb
Host smart-d83ddcc9-5385-47e3-8919-82aabc82d1a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002721443 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_errors.3002721443
Directory /workspace/26.lc_ctrl_errors/latest

Test location /workspace/coverage/default/26.lc_ctrl_jtag_access.1809845768
Short name T775
Test name
Test status
Simulation time 160111979 ps
CPU time 4.69 seconds
Started Jun 02 01:25:51 PM PDT 24
Finished Jun 02 01:25:56 PM PDT 24
Peak memory 209576 kb
Host smart-d46fc151-beab-47c2-8afe-df1b330b7d9d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809845768 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_jtag_access.1809845768
Directory /workspace/26.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/26.lc_ctrl_prog_failure.3443857193
Short name T282
Test name
Test status
Simulation time 28479064 ps
CPU time 1.78 seconds
Started Jun 02 01:25:54 PM PDT 24
Finished Jun 02 01:25:56 PM PDT 24
Peak memory 217964 kb
Host smart-535a7ee2-9cba-40d3-a267-f18e64829336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443857193 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_prog_failure.3443857193
Directory /workspace/26.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_mubi.1301403954
Short name T468
Test name
Test status
Simulation time 405497176 ps
CPU time 18.65 seconds
Started Jun 02 01:25:51 PM PDT 24
Finished Jun 02 01:26:10 PM PDT 24
Peak memory 218960 kb
Host smart-18a785d0-edd4-4d38-87e2-5776b80ec23c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301403954 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_mubi.1301403954
Directory /workspace/26.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_digest.4051720117
Short name T694
Test name
Test status
Simulation time 269579340 ps
CPU time 9.05 seconds
Started Jun 02 01:25:52 PM PDT 24
Finished Jun 02 01:26:01 PM PDT 24
Peak memory 217964 kb
Host smart-7669be66-3650-469c-948e-6e382dd10723
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051720117 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_d
igest.4051720117
Directory /workspace/26.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_mux.317989471
Short name T744
Test name
Test status
Simulation time 460613729 ps
CPU time 9.44 seconds
Started Jun 02 01:25:52 PM PDT 24
Finished Jun 02 01:26:02 PM PDT 24
Peak memory 218024 kb
Host smart-378e7a30-3b6c-4817-9f78-f49436c34d89
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317989471 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_mux.317989471
Directory /workspace/26.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/26.lc_ctrl_security_escalation.2545952354
Short name T309
Test name
Test status
Simulation time 2420584555 ps
CPU time 8.46 seconds
Started Jun 02 01:25:50 PM PDT 24
Finished Jun 02 01:25:59 PM PDT 24
Peak memory 218224 kb
Host smart-4768b782-57de-47dc-83b6-296aef61b803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545952354 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_security_escalation.2545952354
Directory /workspace/26.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/26.lc_ctrl_smoke.2899890863
Short name T71
Test name
Test status
Simulation time 38421005 ps
CPU time 2.88 seconds
Started Jun 02 01:25:53 PM PDT 24
Finished Jun 02 01:25:56 PM PDT 24
Peak memory 217672 kb
Host smart-7b1fc5a1-0a57-4684-bccc-5bf16e0b6196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899890863 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_smoke.2899890863
Directory /workspace/26.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_failure.1977447324
Short name T751
Test name
Test status
Simulation time 324633370 ps
CPU time 33.39 seconds
Started Jun 02 01:25:52 PM PDT 24
Finished Jun 02 01:26:26 PM PDT 24
Peak memory 251112 kb
Host smart-bc8b5aac-f0fe-4c2d-8bbc-f1b73f0b1aff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977447324 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_failure.1977447324
Directory /workspace/26.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_post_trans.750049799
Short name T503
Test name
Test status
Simulation time 334619416 ps
CPU time 7.01 seconds
Started Jun 02 01:25:52 PM PDT 24
Finished Jun 02 01:25:59 PM PDT 24
Peak memory 250508 kb
Host smart-de5b83a1-e30a-4cda-ac63-1cf7c5532cb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750049799 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_post_trans.750049799
Directory /workspace/26.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all.941546556
Short name T318
Test name
Test status
Simulation time 3436063990 ps
CPU time 104.53 seconds
Started Jun 02 01:25:54 PM PDT 24
Finished Jun 02 01:27:38 PM PDT 24
Peak memory 226164 kb
Host smart-5ddc9aa9-0429-4630-b820-5814e16e81f6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941546556 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.lc_ctrl_stress_all.941546556
Directory /workspace/26.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all_with_rand_reset.3023723473
Short name T142
Test name
Test status
Simulation time 44918106743 ps
CPU time 1154.62 seconds
Started Jun 02 01:25:57 PM PDT 24
Finished Jun 02 01:45:12 PM PDT 24
Peak memory 529592 kb
Host smart-45189f1d-72fe-4bab-9c22-708484411f2f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3023723473 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_stress_all_with_rand_reset.3023723473
Directory /workspace/26.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.lc_ctrl_volatile_unlock_smoke.857585133
Short name T619
Test name
Test status
Simulation time 11822735 ps
CPU time 0.93 seconds
Started Jun 02 01:25:53 PM PDT 24
Finished Jun 02 01:25:55 PM PDT 24
Peak memory 211516 kb
Host smart-0eb52745-2331-4498-a93d-2781c08c5661
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857585133 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ct
rl_volatile_unlock_smoke.857585133
Directory /workspace/26.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_alert_test.3889518434
Short name T262
Test name
Test status
Simulation time 14991224 ps
CPU time 0.89 seconds
Started Jun 02 01:26:01 PM PDT 24
Finished Jun 02 01:26:02 PM PDT 24
Peak memory 208656 kb
Host smart-975977c0-1ac6-40ea-afc4-1a05c990bbf6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889518434 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_alert_test.3889518434
Directory /workspace/27.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.lc_ctrl_errors.777333235
Short name T42
Test name
Test status
Simulation time 859326306 ps
CPU time 16.03 seconds
Started Jun 02 01:25:59 PM PDT 24
Finished Jun 02 01:26:15 PM PDT 24
Peak memory 217996 kb
Host smart-8d289557-913b-488b-926f-418ed8e11b47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777333235 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_errors.777333235
Directory /workspace/27.lc_ctrl_errors/latest

Test location /workspace/coverage/default/27.lc_ctrl_jtag_access.1057264082
Short name T779
Test name
Test status
Simulation time 443323947 ps
CPU time 5.43 seconds
Started Jun 02 01:25:59 PM PDT 24
Finished Jun 02 01:26:04 PM PDT 24
Peak memory 216964 kb
Host smart-a22fe0c2-f8b9-41b5-a02d-b4b0e45711f8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057264082 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_jtag_access.1057264082
Directory /workspace/27.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/27.lc_ctrl_prog_failure.34387302
Short name T702
Test name
Test status
Simulation time 132325462 ps
CPU time 2.44 seconds
Started Jun 02 01:26:00 PM PDT 24
Finished Jun 02 01:26:02 PM PDT 24
Peak memory 218004 kb
Host smart-7dec7bbd-9dbb-4322-b349-3abc02f1454a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34387302 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_prog_failure.34387302
Directory /workspace/27.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_mubi.3211881267
Short name T740
Test name
Test status
Simulation time 283379208 ps
CPU time 10.6 seconds
Started Jun 02 01:25:58 PM PDT 24
Finished Jun 02 01:26:09 PM PDT 24
Peak memory 226096 kb
Host smart-6599c12b-69d0-4a3a-a3f4-c04947e009ad
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211881267 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_mubi.3211881267
Directory /workspace/27.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_digest.383931954
Short name T160
Test name
Test status
Simulation time 2055475063 ps
CPU time 16.65 seconds
Started Jun 02 01:26:00 PM PDT 24
Finished Jun 02 01:26:17 PM PDT 24
Peak memory 224724 kb
Host smart-c470be13-2298-4fe0-a2f4-8372552d3ecf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383931954 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_di
gest.383931954
Directory /workspace/27.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_mux.2390231969
Short name T155
Test name
Test status
Simulation time 212863692 ps
CPU time 8.7 seconds
Started Jun 02 01:26:00 PM PDT 24
Finished Jun 02 01:26:09 PM PDT 24
Peak memory 218028 kb
Host smart-37062264-a376-4d37-a574-b15cd47d6773
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390231969 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_mux.
2390231969
Directory /workspace/27.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/27.lc_ctrl_smoke.516691354
Short name T672
Test name
Test status
Simulation time 340320790 ps
CPU time 2.1 seconds
Started Jun 02 01:25:59 PM PDT 24
Finished Jun 02 01:26:01 PM PDT 24
Peak memory 213972 kb
Host smart-053d0abd-f40a-4daa-bbe1-7dec468df5ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516691354 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_smoke.516691354
Directory /workspace/27.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_failure.1425360403
Short name T249
Test name
Test status
Simulation time 3425926936 ps
CPU time 33.3 seconds
Started Jun 02 01:25:58 PM PDT 24
Finished Jun 02 01:26:31 PM PDT 24
Peak memory 251016 kb
Host smart-2be6ed4e-c6d3-459d-846f-0db200348995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425360403 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_failure.1425360403
Directory /workspace/27.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_post_trans.2492697860
Short name T192
Test name
Test status
Simulation time 177628823 ps
CPU time 4.5 seconds
Started Jun 02 01:25:59 PM PDT 24
Finished Jun 02 01:26:04 PM PDT 24
Peak memory 226444 kb
Host smart-9cf70df0-65aa-4d56-b8bb-bfafee2b2ebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492697860 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_post_trans.2492697860
Directory /workspace/27.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all.1690275186
Short name T104
Test name
Test status
Simulation time 1861714086 ps
CPU time 69.21 seconds
Started Jun 02 01:26:01 PM PDT 24
Finished Jun 02 01:27:11 PM PDT 24
Peak memory 267380 kb
Host smart-75a36101-9f9a-4215-a731-c866f773728b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690275186 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.lc_ctrl_stress_all.1690275186
Directory /workspace/27.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.lc_ctrl_volatile_unlock_smoke.338456252
Short name T728
Test name
Test status
Simulation time 21783120 ps
CPU time 0.88 seconds
Started Jun 02 01:25:58 PM PDT 24
Finished Jun 02 01:25:59 PM PDT 24
Peak memory 208624 kb
Host smart-eefd1be1-7525-4fdf-ae85-d4e236d44a67
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338456252 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ct
rl_volatile_unlock_smoke.338456252
Directory /workspace/27.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_alert_test.3567436407
Short name T74
Test name
Test status
Simulation time 45471236 ps
CPU time 1.03 seconds
Started Jun 02 01:26:04 PM PDT 24
Finished Jun 02 01:26:06 PM PDT 24
Peak memory 209488 kb
Host smart-2f2a86f9-6171-4e7f-ae37-68d61b2bb113
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567436407 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_alert_test.3567436407
Directory /workspace/28.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.lc_ctrl_errors.692622272
Short name T215
Test name
Test status
Simulation time 3663294505 ps
CPU time 8.06 seconds
Started Jun 02 01:25:58 PM PDT 24
Finished Jun 02 01:26:07 PM PDT 24
Peak memory 218236 kb
Host smart-6d44db81-28f4-4c54-9503-435447f492f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692622272 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_errors.692622272
Directory /workspace/28.lc_ctrl_errors/latest

Test location /workspace/coverage/default/28.lc_ctrl_jtag_access.157894590
Short name T28
Test name
Test status
Simulation time 510023072 ps
CPU time 6.89 seconds
Started Jun 02 01:25:58 PM PDT 24
Finished Jun 02 01:26:05 PM PDT 24
Peak memory 217088 kb
Host smart-8ebaa414-adbf-4bcf-9ab6-f0fdbf7d576f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157894590 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_jtag_access.157894590
Directory /workspace/28.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/28.lc_ctrl_prog_failure.3360774441
Short name T336
Test name
Test status
Simulation time 98824970 ps
CPU time 4.24 seconds
Started Jun 02 01:26:00 PM PDT 24
Finished Jun 02 01:26:04 PM PDT 24
Peak memory 218088 kb
Host smart-7d805f1d-675a-4575-ae67-393cfb779f38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3360774441 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_prog_failure.3360774441
Directory /workspace/28.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_mubi.56508027
Short name T326
Test name
Test status
Simulation time 219763263 ps
CPU time 9.54 seconds
Started Jun 02 01:25:59 PM PDT 24
Finished Jun 02 01:26:09 PM PDT 24
Peak memory 226040 kb
Host smart-3cb4598f-072b-4a3b-a4da-f5e46b199905
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56508027 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_mubi.56508027
Directory /workspace/28.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_digest.1765300958
Short name T581
Test name
Test status
Simulation time 303906403 ps
CPU time 9.81 seconds
Started Jun 02 01:26:13 PM PDT 24
Finished Jun 02 01:26:23 PM PDT 24
Peak memory 225976 kb
Host smart-34dfa67d-592e-48ee-9642-f4b78f845719
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765300958 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_d
igest.1765300958
Directory /workspace/28.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_mux.3894257682
Short name T260
Test name
Test status
Simulation time 983220360 ps
CPU time 7.32 seconds
Started Jun 02 01:25:58 PM PDT 24
Finished Jun 02 01:26:06 PM PDT 24
Peak memory 218048 kb
Host smart-e1f04a9d-1d18-479b-a2c1-e79785270852
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894257682 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_mux.
3894257682
Directory /workspace/28.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/28.lc_ctrl_security_escalation.1248842425
Short name T836
Test name
Test status
Simulation time 183390529 ps
CPU time 8.28 seconds
Started Jun 02 01:26:01 PM PDT 24
Finished Jun 02 01:26:10 PM PDT 24
Peak memory 218056 kb
Host smart-5c36160a-cf14-4552-83de-4931e45e86d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248842425 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_security_escalation.1248842425
Directory /workspace/28.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/28.lc_ctrl_smoke.3353324076
Short name T76
Test name
Test status
Simulation time 56044224 ps
CPU time 2.68 seconds
Started Jun 02 01:25:58 PM PDT 24
Finished Jun 02 01:26:01 PM PDT 24
Peak memory 214336 kb
Host smart-82ab003d-a26e-4d3f-a9d9-937758897a68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353324076 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_smoke.3353324076
Directory /workspace/28.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_failure.627051157
Short name T246
Test name
Test status
Simulation time 3167458792 ps
CPU time 20.68 seconds
Started Jun 02 01:25:58 PM PDT 24
Finished Jun 02 01:26:19 PM PDT 24
Peak memory 250952 kb
Host smart-c9ea03bb-d849-40b7-968e-a812aee49d16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627051157 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_failure.627051157
Directory /workspace/28.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_post_trans.3303839199
Short name T278
Test name
Test status
Simulation time 669661508 ps
CPU time 7.57 seconds
Started Jun 02 01:25:58 PM PDT 24
Finished Jun 02 01:26:06 PM PDT 24
Peak memory 251092 kb
Host smart-56aa2331-44b6-4d5e-92b5-e596603a76ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3303839199 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_post_trans.3303839199
Directory /workspace/28.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/28.lc_ctrl_stress_all.1315836912
Short name T66
Test name
Test status
Simulation time 7306718673 ps
CPU time 262.15 seconds
Started Jun 02 01:26:05 PM PDT 24
Finished Jun 02 01:30:28 PM PDT 24
Peak memory 273368 kb
Host smart-860870ed-9d5b-4d5e-879d-bcc6ae461da8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315836912 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.lc_ctrl_stress_all.1315836912
Directory /workspace/28.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.lc_ctrl_volatile_unlock_smoke.224891904
Short name T538
Test name
Test status
Simulation time 40214669 ps
CPU time 1.57 seconds
Started Jun 02 01:25:59 PM PDT 24
Finished Jun 02 01:26:01 PM PDT 24
Peak memory 212524 kb
Host smart-8e84a8ec-e3dd-428c-aaaf-20f4fc69c8ce
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224891904 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ct
rl_volatile_unlock_smoke.224891904
Directory /workspace/28.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_alert_test.797937783
Short name T574
Test name
Test status
Simulation time 55611493 ps
CPU time 0.88 seconds
Started Jun 02 01:26:04 PM PDT 24
Finished Jun 02 01:26:05 PM PDT 24
Peak memory 209516 kb
Host smart-2fbe31ce-0139-40f7-88e0-6b4c440be407
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797937783 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_alert_test.797937783
Directory /workspace/29.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.lc_ctrl_errors.694824619
Short name T617
Test name
Test status
Simulation time 1819031309 ps
CPU time 11.35 seconds
Started Jun 02 01:26:05 PM PDT 24
Finished Jun 02 01:26:17 PM PDT 24
Peak memory 217992 kb
Host smart-21920753-9d00-47e7-92b5-19726add816e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694824619 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_errors.694824619
Directory /workspace/29.lc_ctrl_errors/latest

Test location /workspace/coverage/default/29.lc_ctrl_jtag_access.2154597708
Short name T846
Test name
Test status
Simulation time 714016777 ps
CPU time 5.22 seconds
Started Jun 02 01:26:05 PM PDT 24
Finished Jun 02 01:26:11 PM PDT 24
Peak memory 209532 kb
Host smart-8429efdf-8b98-4d3b-a681-3b9176375975
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154597708 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_jtag_access.2154597708
Directory /workspace/29.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/29.lc_ctrl_prog_failure.3595953941
Short name T525
Test name
Test status
Simulation time 55522137 ps
CPU time 3.02 seconds
Started Jun 02 01:26:08 PM PDT 24
Finished Jun 02 01:26:11 PM PDT 24
Peak memory 218084 kb
Host smart-d46740fc-af20-499c-b27e-a6b0d705c908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595953941 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_prog_failure.3595953941
Directory /workspace/29.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_mubi.3843074091
Short name T845
Test name
Test status
Simulation time 487288979 ps
CPU time 16.77 seconds
Started Jun 02 01:26:05 PM PDT 24
Finished Jun 02 01:26:22 PM PDT 24
Peak memory 226108 kb
Host smart-156ed76d-ebdb-46d4-86d6-7940c23c22b1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843074091 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_mubi.3843074091
Directory /workspace/29.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_digest.2073550737
Short name T854
Test name
Test status
Simulation time 2530337819 ps
CPU time 11.95 seconds
Started Jun 02 01:26:05 PM PDT 24
Finished Jun 02 01:26:17 PM PDT 24
Peak memory 217964 kb
Host smart-eaf09f85-f4d7-4047-941a-44913f946d20
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073550737 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_d
igest.2073550737
Directory /workspace/29.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_mux.3444275558
Short name T671
Test name
Test status
Simulation time 1593927253 ps
CPU time 9.78 seconds
Started Jun 02 01:26:04 PM PDT 24
Finished Jun 02 01:26:14 PM PDT 24
Peak memory 218064 kb
Host smart-8f6926ad-579e-4c9b-a7a6-a7a624143b21
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444275558 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_mux.
3444275558
Directory /workspace/29.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/29.lc_ctrl_security_escalation.2665824610
Short name T752
Test name
Test status
Simulation time 2721870848 ps
CPU time 10.08 seconds
Started Jun 02 01:26:07 PM PDT 24
Finished Jun 02 01:26:17 PM PDT 24
Peak memory 226152 kb
Host smart-d211c8ce-6c6f-47d2-b86f-7b0361c21d9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665824610 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_security_escalation.2665824610
Directory /workspace/29.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/29.lc_ctrl_smoke.3748682747
Short name T720
Test name
Test status
Simulation time 141439282 ps
CPU time 2.75 seconds
Started Jun 02 01:26:05 PM PDT 24
Finished Jun 02 01:26:08 PM PDT 24
Peak memory 214664 kb
Host smart-ea7c366e-fa6c-41c8-a2cb-4fff256c5d43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748682747 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_smoke.3748682747
Directory /workspace/29.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_failure.3384439220
Short name T369
Test name
Test status
Simulation time 1129739958 ps
CPU time 25.45 seconds
Started Jun 02 01:26:06 PM PDT 24
Finished Jun 02 01:26:32 PM PDT 24
Peak memory 251072 kb
Host smart-6710ee6c-e5e8-44b6-bd43-c1465d4212ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384439220 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_failure.3384439220
Directory /workspace/29.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_post_trans.3031859779
Short name T472
Test name
Test status
Simulation time 297256291 ps
CPU time 8.1 seconds
Started Jun 02 01:26:06 PM PDT 24
Finished Jun 02 01:26:14 PM PDT 24
Peak memory 247000 kb
Host smart-0944e90d-e449-4fb5-92c4-e5496fe4a322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031859779 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_post_trans.3031859779
Directory /workspace/29.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/29.lc_ctrl_stress_all.3615352123
Short name T78
Test name
Test status
Simulation time 2421861730 ps
CPU time 62.92 seconds
Started Jun 02 01:26:07 PM PDT 24
Finished Jun 02 01:27:10 PM PDT 24
Peak memory 226424 kb
Host smart-a20d2930-6885-4c5a-8e9d-8119457d92f7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615352123 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.lc_ctrl_stress_all.3615352123
Directory /workspace/29.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.lc_ctrl_stress_all_with_rand_reset.1961605662
Short name T100
Test name
Test status
Simulation time 42902537137 ps
CPU time 942.34 seconds
Started Jun 02 01:26:06 PM PDT 24
Finished Jun 02 01:41:49 PM PDT 24
Peak memory 529732 kb
Host smart-eab45e11-ffbf-4fff-a979-ac7698f00633
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1961605662 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_stress_all_with_rand_reset.1961605662
Directory /workspace/29.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.lc_ctrl_volatile_unlock_smoke.3565116274
Short name T497
Test name
Test status
Simulation time 88871690 ps
CPU time 0.8 seconds
Started Jun 02 01:26:07 PM PDT 24
Finished Jun 02 01:26:08 PM PDT 24
Peak memory 207740 kb
Host smart-6fa83bb5-a3ae-47fb-805a-d063794eaa5d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565116274 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_c
trl_volatile_unlock_smoke.3565116274
Directory /workspace/29.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_alert_test.3986046923
Short name T73
Test name
Test status
Simulation time 29725241 ps
CPU time 1.1 seconds
Started Jun 02 01:24:08 PM PDT 24
Finished Jun 02 01:24:10 PM PDT 24
Peak memory 208796 kb
Host smart-9e088f2f-5ad4-4876-bc34-ed526d912549
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986046923 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_alert_test.3986046923
Directory /workspace/3.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.lc_ctrl_claim_transition_if.2813338005
Short name T820
Test name
Test status
Simulation time 49708675 ps
CPU time 0.84 seconds
Started Jun 02 01:23:59 PM PDT 24
Finished Jun 02 01:24:01 PM PDT 24
Peak memory 208780 kb
Host smart-94b58cc4-de13-4d0d-a9a7-083ce712f5fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813338005 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_claim_transition_if.2813338005
Directory /workspace/3.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/3.lc_ctrl_errors.2700808426
Short name T406
Test name
Test status
Simulation time 1111093524 ps
CPU time 18.92 seconds
Started Jun 02 01:24:01 PM PDT 24
Finished Jun 02 01:24:21 PM PDT 24
Peak memory 218028 kb
Host smart-673d6e8d-a233-4a96-aa35-6780902158ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700808426 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_errors.2700808426
Directory /workspace/3.lc_ctrl_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_access.219545636
Short name T598
Test name
Test status
Simulation time 372013927 ps
CPU time 9.92 seconds
Started Jun 02 01:24:00 PM PDT 24
Finished Jun 02 01:24:10 PM PDT 24
Peak memory 209524 kb
Host smart-52a3d516-e4d3-4cac-a8d1-9a87a6b25f7a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219545636 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_access.219545636
Directory /workspace/3.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_errors.2828743874
Short name T390
Test name
Test status
Simulation time 10963613228 ps
CPU time 67.95 seconds
Started Jun 02 01:24:00 PM PDT 24
Finished Jun 02 01:25:09 PM PDT 24
Peak memory 218416 kb
Host smart-6655257f-dbeb-420a-94c6-bd31ccf3c57d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828743874 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_er
rors.2828743874
Directory /workspace/3.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_priority.3850021254
Short name T729
Test name
Test status
Simulation time 1166899351 ps
CPU time 3.66 seconds
Started Jun 02 01:24:00 PM PDT 24
Finished Jun 02 01:24:05 PM PDT 24
Peak memory 216980 kb
Host smart-b5fec9fa-c16c-4190-a621-1e3b0e3e5906
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850021254 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_priority.3
850021254
Directory /workspace/3.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_prog_failure.1654959782
Short name T660
Test name
Test status
Simulation time 4066284875 ps
CPU time 10.67 seconds
Started Jun 02 01:24:01 PM PDT 24
Finished Jun 02 01:24:12 PM PDT 24
Peak memory 218240 kb
Host smart-cdd0a927-0653-432c-86e6-00da4e15befb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654959782 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag
_prog_failure.1654959782
Directory /workspace/3.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_regwen_during_op.1875773707
Short name T70
Test name
Test status
Simulation time 5727863959 ps
CPU time 31.44 seconds
Started Jun 02 01:24:00 PM PDT 24
Finished Jun 02 01:24:32 PM PDT 24
Peak memory 217668 kb
Host smart-2f60ea30-af28-480f-8267-988083ec6cd2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875773707 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_regwen_during_op.1875773707
Directory /workspace/3.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_smoke.2569838791
Short name T235
Test name
Test status
Simulation time 773231342 ps
CPU time 10.64 seconds
Started Jun 02 01:24:01 PM PDT 24
Finished Jun 02 01:24:12 PM PDT 24
Peak memory 217648 kb
Host smart-8c1412c1-3440-4811-8e23-dd25fdfd95c7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569838791 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_smoke.
2569838791
Directory /workspace/3.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_failure.2259304106
Short name T806
Test name
Test status
Simulation time 5259048087 ps
CPU time 54.73 seconds
Started Jun 02 01:24:01 PM PDT 24
Finished Jun 02 01:24:56 PM PDT 24
Peak memory 252008 kb
Host smart-1edd35d9-19fc-4e92-b7cb-96f37c214d7d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259304106 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jta
g_state_failure.2259304106
Directory /workspace/3.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_post_trans.103612485
Short name T778
Test name
Test status
Simulation time 361242445 ps
CPU time 8.69 seconds
Started Jun 02 01:24:00 PM PDT 24
Finished Jun 02 01:24:09 PM PDT 24
Peak memory 223128 kb
Host smart-5b9ed3c8-1350-4e15-b6b1-1484eda8f427
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103612485 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_j
tag_state_post_trans.103612485
Directory /workspace/3.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_prog_failure.2175130853
Short name T726
Test name
Test status
Simulation time 116970421 ps
CPU time 1.72 seconds
Started Jun 02 01:24:01 PM PDT 24
Finished Jun 02 01:24:04 PM PDT 24
Peak memory 218008 kb
Host smart-e018478e-1589-4b8c-897f-96feee25dcad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175130853 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_prog_failure.2175130853
Directory /workspace/3.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_regwen_during_op.221997867
Short name T676
Test name
Test status
Simulation time 2579953900 ps
CPU time 6.92 seconds
Started Jun 02 01:23:59 PM PDT 24
Finished Jun 02 01:24:07 PM PDT 24
Peak memory 217704 kb
Host smart-91f3dbcd-8957-4dab-b012-dc60568d88c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221997867 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_regwen_during_op.221997867
Directory /workspace/3.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_cm.3949295880
Short name T92
Test name
Test status
Simulation time 113497425 ps
CPU time 25.02 seconds
Started Jun 02 01:24:00 PM PDT 24
Finished Jun 02 01:24:26 PM PDT 24
Peak memory 269476 kb
Host smart-54cb0c9e-354f-4dce-a3fa-53b916c673ff
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949295880 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_cm.3949295880
Directory /workspace/3.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_mubi.438080282
Short name T590
Test name
Test status
Simulation time 848164947 ps
CPU time 12.71 seconds
Started Jun 02 01:24:00 PM PDT 24
Finished Jun 02 01:24:14 PM PDT 24
Peak memory 218236 kb
Host smart-824ec338-1f2e-4b12-aca9-810e455eed9a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438080282 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_mubi.438080282
Directory /workspace/3.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_digest.1518084183
Short name T465
Test name
Test status
Simulation time 1223084149 ps
CPU time 12.71 seconds
Started Jun 02 01:23:58 PM PDT 24
Finished Jun 02 01:24:11 PM PDT 24
Peak memory 225988 kb
Host smart-d53fa299-a982-441a-95eb-def1ae5892dc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518084183 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_di
gest.1518084183
Directory /workspace/3.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_mux.4036160784
Short name T811
Test name
Test status
Simulation time 980364484 ps
CPU time 8.82 seconds
Started Jun 02 01:24:00 PM PDT 24
Finished Jun 02 01:24:09 PM PDT 24
Peak memory 217980 kb
Host smart-499b0ba6-481c-4199-a073-059a43736a71
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036160784 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_mux.4
036160784
Directory /workspace/3.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/3.lc_ctrl_security_escalation.3949457034
Short name T678
Test name
Test status
Simulation time 445171678 ps
CPU time 8.69 seconds
Started Jun 02 01:24:05 PM PDT 24
Finished Jun 02 01:24:14 PM PDT 24
Peak memory 218056 kb
Host smart-fa4db9d3-3941-450b-b4ff-a8a737a06820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949457034 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_security_escalation.3949457034
Directory /workspace/3.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/3.lc_ctrl_smoke.3057268669
Short name T494
Test name
Test status
Simulation time 59412571 ps
CPU time 1.27 seconds
Started Jun 02 01:23:59 PM PDT 24
Finished Jun 02 01:24:00 PM PDT 24
Peak memory 213400 kb
Host smart-29ee7963-dc95-4652-aff1-7f25909c9c10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057268669 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_smoke.3057268669
Directory /workspace/3.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_failure.1861844683
Short name T782
Test name
Test status
Simulation time 457977798 ps
CPU time 24.06 seconds
Started Jun 02 01:24:00 PM PDT 24
Finished Jun 02 01:24:25 PM PDT 24
Peak memory 251024 kb
Host smart-d29da874-746f-4a54-a563-487558522094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861844683 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_failure.1861844683
Directory /workspace/3.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_post_trans.3331725549
Short name T802
Test name
Test status
Simulation time 54426504 ps
CPU time 6.11 seconds
Started Jun 02 01:24:01 PM PDT 24
Finished Jun 02 01:24:08 PM PDT 24
Peak memory 242816 kb
Host smart-8c45a92e-77ef-49c5-87bd-842246556ca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331725549 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_post_trans.3331725549
Directory /workspace/3.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_stress_all.2559575895
Short name T512
Test name
Test status
Simulation time 842292795 ps
CPU time 38.23 seconds
Started Jun 02 01:24:05 PM PDT 24
Finished Jun 02 01:24:43 PM PDT 24
Peak memory 250948 kb
Host smart-1d9116ce-c00d-4b83-9a66-5f1672226e30
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559575895 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.lc_ctrl_stress_all.2559575895
Directory /workspace/3.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.lc_ctrl_volatile_unlock_smoke.2820738511
Short name T303
Test name
Test status
Simulation time 16328655 ps
CPU time 1.08 seconds
Started Jun 02 01:23:59 PM PDT 24
Finished Jun 02 01:24:00 PM PDT 24
Peak memory 211624 kb
Host smart-93963406-4fe5-4424-b6ee-3df7cd518d05
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820738511 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ct
rl_volatile_unlock_smoke.2820738511
Directory /workspace/3.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_alert_test.877984413
Short name T93
Test name
Test status
Simulation time 103719342 ps
CPU time 1.12 seconds
Started Jun 02 01:26:14 PM PDT 24
Finished Jun 02 01:26:16 PM PDT 24
Peak memory 208696 kb
Host smart-2d75ed84-b90e-4ca9-987c-10bd72948b6b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877984413 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_alert_test.877984413
Directory /workspace/30.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.lc_ctrl_errors.3273484921
Short name T46
Test name
Test status
Simulation time 1904065254 ps
CPU time 13.34 seconds
Started Jun 02 01:26:07 PM PDT 24
Finished Jun 02 01:26:21 PM PDT 24
Peak memory 218012 kb
Host smart-5b5ba1c6-6a23-4297-a4a2-a8e977c76d06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273484921 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_errors.3273484921
Directory /workspace/30.lc_ctrl_errors/latest

Test location /workspace/coverage/default/30.lc_ctrl_jtag_access.1524718927
Short name T539
Test name
Test status
Simulation time 2621562129 ps
CPU time 6.97 seconds
Started Jun 02 01:26:06 PM PDT 24
Finished Jun 02 01:26:13 PM PDT 24
Peak memory 217244 kb
Host smart-7450d483-323a-444b-88db-c32427cb9f80
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524718927 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_jtag_access.1524718927
Directory /workspace/30.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/30.lc_ctrl_prog_failure.2321585224
Short name T504
Test name
Test status
Simulation time 195593503 ps
CPU time 2.78 seconds
Started Jun 02 01:26:04 PM PDT 24
Finished Jun 02 01:26:07 PM PDT 24
Peak memory 218116 kb
Host smart-406667d7-bee9-4c1b-a3fe-98dd766ca7ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321585224 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_prog_failure.2321585224
Directory /workspace/30.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_mubi.3258947821
Short name T439
Test name
Test status
Simulation time 990353143 ps
CPU time 10.35 seconds
Started Jun 02 01:26:04 PM PDT 24
Finished Jun 02 01:26:15 PM PDT 24
Peak memory 218036 kb
Host smart-24f312e5-211d-429c-b57d-858218b23a92
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258947821 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_mubi.3258947821
Directory /workspace/30.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_digest.3179018606
Short name T622
Test name
Test status
Simulation time 2290504213 ps
CPU time 15.67 seconds
Started Jun 02 01:26:05 PM PDT 24
Finished Jun 02 01:26:21 PM PDT 24
Peak memory 226000 kb
Host smart-7c32dc97-80c2-4cda-9123-170400b43a87
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179018606 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_d
igest.3179018606
Directory /workspace/30.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_mux.1175299619
Short name T432
Test name
Test status
Simulation time 319950586 ps
CPU time 9.24 seconds
Started Jun 02 01:26:13 PM PDT 24
Finished Jun 02 01:26:22 PM PDT 24
Peak memory 217932 kb
Host smart-d5bcd68b-47c9-448f-9226-c76a3367c0d3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175299619 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_mux.
1175299619
Directory /workspace/30.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/30.lc_ctrl_security_escalation.3513856180
Short name T259
Test name
Test status
Simulation time 784152745 ps
CPU time 14.99 seconds
Started Jun 02 01:26:05 PM PDT 24
Finished Jun 02 01:26:20 PM PDT 24
Peak memory 218172 kb
Host smart-65d7dcea-f4e7-4a70-bf5d-fb63b2d81ddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513856180 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_security_escalation.3513856180
Directory /workspace/30.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/30.lc_ctrl_smoke.2171361272
Short name T853
Test name
Test status
Simulation time 51336622 ps
CPU time 2.8 seconds
Started Jun 02 01:26:07 PM PDT 24
Finished Jun 02 01:26:10 PM PDT 24
Peak memory 217652 kb
Host smart-f285ee58-5b2b-4ca9-b691-a444646c279d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171361272 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_smoke.2171361272
Directory /workspace/30.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_failure.2207118445
Short name T830
Test name
Test status
Simulation time 305149028 ps
CPU time 31.44 seconds
Started Jun 02 01:26:07 PM PDT 24
Finished Jun 02 01:26:38 PM PDT 24
Peak memory 250936 kb
Host smart-d666dccd-17e0-4966-abf3-e73f6dbe931d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207118445 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_failure.2207118445
Directory /workspace/30.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_post_trans.707531682
Short name T319
Test name
Test status
Simulation time 171655109 ps
CPU time 5.86 seconds
Started Jun 02 01:26:13 PM PDT 24
Finished Jun 02 01:26:19 PM PDT 24
Peak memory 218012 kb
Host smart-7e754601-a8ef-48f2-bdfc-d025491b8c8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707531682 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_post_trans.707531682
Directory /workspace/30.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all.928762344
Short name T560
Test name
Test status
Simulation time 2350308421 ps
CPU time 69.9 seconds
Started Jun 02 01:26:12 PM PDT 24
Finished Jun 02 01:27:23 PM PDT 24
Peak memory 268220 kb
Host smart-28d2ec6f-a0ee-430e-bc47-73fb906e96e7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928762344 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.lc_ctrl_stress_all.928762344
Directory /workspace/30.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.lc_ctrl_volatile_unlock_smoke.800229251
Short name T699
Test name
Test status
Simulation time 32248153 ps
CPU time 0.74 seconds
Started Jun 02 01:26:05 PM PDT 24
Finished Jun 02 01:26:07 PM PDT 24
Peak memory 208332 kb
Host smart-525e95c2-cd86-409d-bb9e-268a94f02432
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800229251 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ct
rl_volatile_unlock_smoke.800229251
Directory /workspace/30.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_alert_test.396571592
Short name T453
Test name
Test status
Simulation time 30302962 ps
CPU time 1.48 seconds
Started Jun 02 01:26:13 PM PDT 24
Finished Jun 02 01:26:15 PM PDT 24
Peak memory 209064 kb
Host smart-529c22c5-e4ae-4f97-921a-ebfc92dc6f3e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396571592 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_alert_test.396571592
Directory /workspace/31.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.lc_ctrl_errors.571594040
Short name T614
Test name
Test status
Simulation time 269543697 ps
CPU time 8.37 seconds
Started Jun 02 01:26:14 PM PDT 24
Finished Jun 02 01:26:23 PM PDT 24
Peak memory 218000 kb
Host smart-a71b0b91-c87d-490d-a344-ca628ec414f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571594040 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_errors.571594040
Directory /workspace/31.lc_ctrl_errors/latest

Test location /workspace/coverage/default/31.lc_ctrl_jtag_access.3393915263
Short name T396
Test name
Test status
Simulation time 590017562 ps
CPU time 14.88 seconds
Started Jun 02 01:26:13 PM PDT 24
Finished Jun 02 01:26:28 PM PDT 24
Peak memory 217164 kb
Host smart-b7b27091-64e5-49ce-b8bc-0346b8483aaa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393915263 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_jtag_access.3393915263
Directory /workspace/31.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/31.lc_ctrl_prog_failure.1220678463
Short name T635
Test name
Test status
Simulation time 509040566 ps
CPU time 4.76 seconds
Started Jun 02 01:26:11 PM PDT 24
Finished Jun 02 01:26:16 PM PDT 24
Peak memory 218080 kb
Host smart-b38b1a58-bed9-4231-aba0-1f0269c9b71b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220678463 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_prog_failure.1220678463
Directory /workspace/31.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_mubi.2463411203
Short name T790
Test name
Test status
Simulation time 373083493 ps
CPU time 12.48 seconds
Started Jun 02 01:26:09 PM PDT 24
Finished Jun 02 01:26:22 PM PDT 24
Peak memory 218976 kb
Host smart-1f85edab-25a1-4907-9a07-4c6c243f27da
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463411203 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_mubi.2463411203
Directory /workspace/31.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_digest.3445102246
Short name T629
Test name
Test status
Simulation time 506314149 ps
CPU time 8.05 seconds
Started Jun 02 01:26:11 PM PDT 24
Finished Jun 02 01:26:20 PM PDT 24
Peak memory 217940 kb
Host smart-13a8e542-dff5-4be0-9272-b36831fc1571
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445102246 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_d
igest.3445102246
Directory /workspace/31.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_mux.261631158
Short name T23
Test name
Test status
Simulation time 1450021408 ps
CPU time 9.34 seconds
Started Jun 02 01:26:14 PM PDT 24
Finished Jun 02 01:26:24 PM PDT 24
Peak memory 218092 kb
Host smart-0919ae45-de5e-4d2e-a825-f3c670fdf42f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261631158 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_mux.261631158
Directory /workspace/31.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/31.lc_ctrl_security_escalation.2743184333
Short name T225
Test name
Test status
Simulation time 607524427 ps
CPU time 11.82 seconds
Started Jun 02 01:26:12 PM PDT 24
Finished Jun 02 01:26:24 PM PDT 24
Peak memory 226092 kb
Host smart-956a2c2b-fea7-48bb-88b4-3a99582dbc47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743184333 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_security_escalation.2743184333
Directory /workspace/31.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/31.lc_ctrl_smoke.749166642
Short name T69
Test name
Test status
Simulation time 40117437 ps
CPU time 2.91 seconds
Started Jun 02 01:26:11 PM PDT 24
Finished Jun 02 01:26:15 PM PDT 24
Peak memory 214424 kb
Host smart-937172ab-38f0-4759-a109-77b63338baad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749166642 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_smoke.749166642
Directory /workspace/31.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_failure.906264594
Short name T724
Test name
Test status
Simulation time 288942858 ps
CPU time 20.5 seconds
Started Jun 02 01:26:14 PM PDT 24
Finished Jun 02 01:26:35 PM PDT 24
Peak memory 251056 kb
Host smart-1fdb7f9a-9b40-411c-a770-94b51c837b41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906264594 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_failure.906264594
Directory /workspace/31.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_post_trans.1038555101
Short name T34
Test name
Test status
Simulation time 63065018 ps
CPU time 7.24 seconds
Started Jun 02 01:26:16 PM PDT 24
Finished Jun 02 01:26:23 PM PDT 24
Peak memory 250956 kb
Host smart-da797b24-5a39-4ea4-a017-ff6b443555bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038555101 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_post_trans.1038555101
Directory /workspace/31.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/31.lc_ctrl_stress_all.492679276
Short name T665
Test name
Test status
Simulation time 3933051318 ps
CPU time 129.09 seconds
Started Jun 02 01:26:13 PM PDT 24
Finished Jun 02 01:28:22 PM PDT 24
Peak memory 227780 kb
Host smart-4811aa3c-7cfb-42c9-9523-f9d673d93056
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492679276 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.lc_ctrl_stress_all.492679276
Directory /workspace/31.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.lc_ctrl_stress_all_with_rand_reset.3261520052
Short name T180
Test name
Test status
Simulation time 195263534778 ps
CPU time 719.05 seconds
Started Jun 02 01:26:13 PM PDT 24
Finished Jun 02 01:38:13 PM PDT 24
Peak memory 279720 kb
Host smart-e4a0cb1d-e194-4d09-8a7b-41aa7250966f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3261520052 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_stress_all_with_rand_reset.3261520052
Directory /workspace/31.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.lc_ctrl_volatile_unlock_smoke.280363518
Short name T298
Test name
Test status
Simulation time 58226053 ps
CPU time 0.8 seconds
Started Jun 02 01:26:11 PM PDT 24
Finished Jun 02 01:26:12 PM PDT 24
Peak memory 208388 kb
Host smart-c60e42cf-6b75-477b-ae1e-bce40b68fca7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280363518 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ct
rl_volatile_unlock_smoke.280363518
Directory /workspace/31.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_alert_test.2997498739
Short name T559
Test name
Test status
Simulation time 62240798 ps
CPU time 1.11 seconds
Started Jun 02 01:26:15 PM PDT 24
Finished Jun 02 01:26:16 PM PDT 24
Peak memory 208712 kb
Host smart-03091779-a25e-4957-92af-a7f7e20f40b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997498739 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_alert_test.2997498739
Directory /workspace/32.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.lc_ctrl_errors.269313402
Short name T224
Test name
Test status
Simulation time 1765326367 ps
CPU time 18.87 seconds
Started Jun 02 01:26:10 PM PDT 24
Finished Jun 02 01:26:30 PM PDT 24
Peak memory 218004 kb
Host smart-c178a3a1-30af-483f-91bd-81062f529c19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269313402 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_errors.269313402
Directory /workspace/32.lc_ctrl_errors/latest

Test location /workspace/coverage/default/32.lc_ctrl_jtag_access.883340063
Short name T161
Test name
Test status
Simulation time 582087707 ps
CPU time 1.9 seconds
Started Jun 02 01:26:11 PM PDT 24
Finished Jun 02 01:26:13 PM PDT 24
Peak memory 209640 kb
Host smart-e9d4f78f-9035-4d0d-b32c-0fa864ae4e47
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883340063 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_jtag_access.883340063
Directory /workspace/32.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/32.lc_ctrl_prog_failure.1128243005
Short name T489
Test name
Test status
Simulation time 89671506 ps
CPU time 1.8 seconds
Started Jun 02 01:26:14 PM PDT 24
Finished Jun 02 01:26:16 PM PDT 24
Peak memory 218064 kb
Host smart-197e649d-dacb-4e82-8f30-4266b9486abf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128243005 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_prog_failure.1128243005
Directory /workspace/32.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_mubi.1623025885
Short name T558
Test name
Test status
Simulation time 3079495565 ps
CPU time 13.96 seconds
Started Jun 02 01:26:12 PM PDT 24
Finished Jun 02 01:26:26 PM PDT 24
Peak memory 219604 kb
Host smart-4a9a32ce-7356-40cd-b4d3-2b5786e7cbff
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623025885 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_mubi.1623025885
Directory /workspace/32.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_digest.623023377
Short name T553
Test name
Test status
Simulation time 394087610 ps
CPU time 14.63 seconds
Started Jun 02 01:26:13 PM PDT 24
Finished Jun 02 01:26:28 PM PDT 24
Peak memory 217972 kb
Host smart-adb166ef-79d8-4cf0-9412-9da3ac08fc5e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623023377 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_di
gest.623023377
Directory /workspace/32.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_mux.579466565
Short name T47
Test name
Test status
Simulation time 783367562 ps
CPU time 7.68 seconds
Started Jun 02 01:26:13 PM PDT 24
Finished Jun 02 01:26:21 PM PDT 24
Peak memory 217976 kb
Host smart-35d09a03-98ee-4e28-ba9b-ca2ba1b41d76
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579466565 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_mux.579466565
Directory /workspace/32.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/32.lc_ctrl_security_escalation.861446371
Short name T358
Test name
Test status
Simulation time 251467092 ps
CPU time 7.29 seconds
Started Jun 02 01:26:12 PM PDT 24
Finished Jun 02 01:26:19 PM PDT 24
Peak memory 218028 kb
Host smart-ad90ba78-11af-4af5-9cb8-d15e413f8ca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861446371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_security_escalation.861446371
Directory /workspace/32.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/32.lc_ctrl_smoke.2066184626
Short name T460
Test name
Test status
Simulation time 206015552 ps
CPU time 2.78 seconds
Started Jun 02 01:26:10 PM PDT 24
Finished Jun 02 01:26:13 PM PDT 24
Peak memory 217732 kb
Host smart-ad5e163a-9334-450c-9018-acc1a84c6aca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066184626 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_smoke.2066184626
Directory /workspace/32.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_failure.864283235
Short name T641
Test name
Test status
Simulation time 336959291 ps
CPU time 41.07 seconds
Started Jun 02 01:26:13 PM PDT 24
Finished Jun 02 01:26:54 PM PDT 24
Peak memory 250952 kb
Host smart-ab061d71-61ad-4305-b99f-40ecb73aaf31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864283235 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_failure.864283235
Directory /workspace/32.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_post_trans.74602932
Short name T328
Test name
Test status
Simulation time 59944281 ps
CPU time 6.82 seconds
Started Jun 02 01:26:15 PM PDT 24
Finished Jun 02 01:26:22 PM PDT 24
Peak memory 251004 kb
Host smart-95e20e16-ddb1-4afb-b21b-1b5b45191eda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74602932 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_post_trans.74602932
Directory /workspace/32.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all.389293029
Short name T102
Test name
Test status
Simulation time 4647153060 ps
CPU time 103.94 seconds
Started Jun 02 01:26:11 PM PDT 24
Finished Jun 02 01:27:55 PM PDT 24
Peak memory 272036 kb
Host smart-9386b7ea-24b6-4ba5-901e-ac3765f23062
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389293029 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.lc_ctrl_stress_all.389293029
Directory /workspace/32.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.lc_ctrl_volatile_unlock_smoke.3552597700
Short name T459
Test name
Test status
Simulation time 24200084 ps
CPU time 1.03 seconds
Started Jun 02 01:26:13 PM PDT 24
Finished Jun 02 01:26:15 PM PDT 24
Peak memory 211552 kb
Host smart-2cb501ae-7a25-41b1-903d-2311eb7dc6e7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552597700 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_c
trl_volatile_unlock_smoke.3552597700
Directory /workspace/32.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_alert_test.2214704232
Short name T304
Test name
Test status
Simulation time 63557392 ps
CPU time 1.08 seconds
Started Jun 02 01:26:20 PM PDT 24
Finished Jun 02 01:26:22 PM PDT 24
Peak memory 208648 kb
Host smart-e9f716ef-8b75-4dd7-b219-4746e3e050a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214704232 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_alert_test.2214704232
Directory /workspace/33.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.lc_ctrl_errors.4021734478
Short name T750
Test name
Test status
Simulation time 446642909 ps
CPU time 7.93 seconds
Started Jun 02 01:26:14 PM PDT 24
Finished Jun 02 01:26:23 PM PDT 24
Peak memory 218016 kb
Host smart-2bcb15a4-571c-4995-9cc3-4fe382365e7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021734478 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_errors.4021734478
Directory /workspace/33.lc_ctrl_errors/latest

Test location /workspace/coverage/default/33.lc_ctrl_jtag_access.690122188
Short name T387
Test name
Test status
Simulation time 34038873 ps
CPU time 1.12 seconds
Started Jun 02 01:26:19 PM PDT 24
Finished Jun 02 01:26:20 PM PDT 24
Peak memory 209524 kb
Host smart-722d987e-13d3-480a-aac7-6272279bdf3c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690122188 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_jtag_access.690122188
Directory /workspace/33.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/33.lc_ctrl_prog_failure.2940231967
Short name T708
Test name
Test status
Simulation time 1013714900 ps
CPU time 2.36 seconds
Started Jun 02 01:26:11 PM PDT 24
Finished Jun 02 01:26:14 PM PDT 24
Peak memory 218072 kb
Host smart-738d4b45-6746-4aeb-9047-844d55d897b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940231967 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_prog_failure.2940231967
Directory /workspace/33.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_mubi.2648858973
Short name T859
Test name
Test status
Simulation time 353900531 ps
CPU time 11.81 seconds
Started Jun 02 01:26:18 PM PDT 24
Finished Jun 02 01:26:31 PM PDT 24
Peak memory 226108 kb
Host smart-7a535772-7d3f-42d9-93d9-8de92b6bebd1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648858973 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_mubi.2648858973
Directory /workspace/33.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_digest.3668716157
Short name T680
Test name
Test status
Simulation time 372470628 ps
CPU time 15.02 seconds
Started Jun 02 01:26:19 PM PDT 24
Finished Jun 02 01:26:35 PM PDT 24
Peak memory 217952 kb
Host smart-ed67efb9-195f-4cc0-ad13-d1288bac1471
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668716157 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_d
igest.3668716157
Directory /workspace/33.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_mux.879236349
Short name T32
Test name
Test status
Simulation time 1219916555 ps
CPU time 7.26 seconds
Started Jun 02 01:26:18 PM PDT 24
Finished Jun 02 01:26:26 PM PDT 24
Peak memory 218052 kb
Host smart-25dbaacf-a0b0-41a9-84bd-afa468c21a4f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879236349 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_mux.879236349
Directory /workspace/33.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/33.lc_ctrl_security_escalation.2858812626
Short name T60
Test name
Test status
Simulation time 1256263427 ps
CPU time 8.43 seconds
Started Jun 02 01:26:19 PM PDT 24
Finished Jun 02 01:26:28 PM PDT 24
Peak memory 218080 kb
Host smart-f25e533e-ab12-46fc-be58-b87aff935a59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858812626 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_security_escalation.2858812626
Directory /workspace/33.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/33.lc_ctrl_smoke.3196282862
Short name T658
Test name
Test status
Simulation time 283844217 ps
CPU time 5.67 seconds
Started Jun 02 01:26:11 PM PDT 24
Finished Jun 02 01:26:17 PM PDT 24
Peak memory 217804 kb
Host smart-f020a075-75b1-4e1c-9f24-9238b045e156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196282862 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_smoke.3196282862
Directory /workspace/33.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_failure.958917518
Short name T638
Test name
Test status
Simulation time 1527524532 ps
CPU time 30.5 seconds
Started Jun 02 01:26:15 PM PDT 24
Finished Jun 02 01:26:46 PM PDT 24
Peak memory 250912 kb
Host smart-38b8a524-da78-46a3-b8a3-329bcb7b7781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958917518 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_failure.958917518
Directory /workspace/33.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_post_trans.3452473353
Short name T763
Test name
Test status
Simulation time 91407634 ps
CPU time 6.56 seconds
Started Jun 02 01:26:14 PM PDT 24
Finished Jun 02 01:26:21 PM PDT 24
Peak memory 250488 kb
Host smart-5108d3b3-a96f-4214-958c-6cba6f57d3d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452473353 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_post_trans.3452473353
Directory /workspace/33.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all.3316620453
Short name T804
Test name
Test status
Simulation time 82872116854 ps
CPU time 179.59 seconds
Started Jun 02 01:26:17 PM PDT 24
Finished Jun 02 01:29:17 PM PDT 24
Peak memory 283904 kb
Host smart-54b03c7f-67ef-49c3-a874-d48a5166d145
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316620453 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.lc_ctrl_stress_all.3316620453
Directory /workspace/33.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.lc_ctrl_volatile_unlock_smoke.40967125
Short name T360
Test name
Test status
Simulation time 48573768 ps
CPU time 0.89 seconds
Started Jun 02 01:26:12 PM PDT 24
Finished Jun 02 01:26:13 PM PDT 24
Peak memory 211460 kb
Host smart-235ccd39-7831-447a-823b-82f9dfd6c073
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40967125 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vol
atile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctr
l_volatile_unlock_smoke.40967125
Directory /workspace/33.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_alert_test.1940241530
Short name T502
Test name
Test status
Simulation time 28391710 ps
CPU time 0.95 seconds
Started Jun 02 01:26:19 PM PDT 24
Finished Jun 02 01:26:20 PM PDT 24
Peak memory 209628 kb
Host smart-0c1f5dbd-33fa-4974-a4a1-26dd326f403d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940241530 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_alert_test.1940241530
Directory /workspace/34.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.lc_ctrl_errors.1240783421
Short name T745
Test name
Test status
Simulation time 662575816 ps
CPU time 7.39 seconds
Started Jun 02 01:26:18 PM PDT 24
Finished Jun 02 01:26:26 PM PDT 24
Peak memory 218048 kb
Host smart-c1a09961-088b-4a0a-b64d-117d23523899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240783421 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_errors.1240783421
Directory /workspace/34.lc_ctrl_errors/latest

Test location /workspace/coverage/default/34.lc_ctrl_jtag_access.3884144910
Short name T698
Test name
Test status
Simulation time 929872161 ps
CPU time 8.95 seconds
Started Jun 02 01:26:19 PM PDT 24
Finished Jun 02 01:26:29 PM PDT 24
Peak memory 209512 kb
Host smart-a4025085-b21d-411a-a36a-cf95400d2f25
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884144910 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_jtag_access.3884144910
Directory /workspace/34.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/34.lc_ctrl_prog_failure.255641232
Short name T156
Test name
Test status
Simulation time 213723551 ps
CPU time 2.22 seconds
Started Jun 02 01:26:19 PM PDT 24
Finished Jun 02 01:26:21 PM PDT 24
Peak memory 218012 kb
Host smart-a53e136b-1cfd-478a-bdc1-3518358d65e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255641232 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_prog_failure.255641232
Directory /workspace/34.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_mubi.2762489151
Short name T274
Test name
Test status
Simulation time 342841185 ps
CPU time 12.68 seconds
Started Jun 02 01:26:19 PM PDT 24
Finished Jun 02 01:26:32 PM PDT 24
Peak memory 218032 kb
Host smart-794f144a-ad33-4b02-9586-edd99b2e00c2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762489151 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_mubi.2762489151
Directory /workspace/34.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_digest.4166772995
Short name T831
Test name
Test status
Simulation time 1174362490 ps
CPU time 11.94 seconds
Started Jun 02 01:26:19 PM PDT 24
Finished Jun 02 01:26:31 PM PDT 24
Peak memory 217972 kb
Host smart-d4b7c6ca-e5a3-4791-ae47-43349379bece
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166772995 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_d
igest.4166772995
Directory /workspace/34.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_mux.763602535
Short name T673
Test name
Test status
Simulation time 262291860 ps
CPU time 9.83 seconds
Started Jun 02 01:26:21 PM PDT 24
Finished Jun 02 01:26:32 PM PDT 24
Peak memory 218032 kb
Host smart-38c264fd-d6e6-470f-9774-f5894d5258ad
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763602535 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_mux.763602535
Directory /workspace/34.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/34.lc_ctrl_security_escalation.630575569
Short name T785
Test name
Test status
Simulation time 3759723608 ps
CPU time 12.69 seconds
Started Jun 02 01:26:21 PM PDT 24
Finished Jun 02 01:26:34 PM PDT 24
Peak memory 218136 kb
Host smart-258ca763-60f2-4365-9560-3b4fb5421237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630575569 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_security_escalation.630575569
Directory /workspace/34.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/34.lc_ctrl_smoke.833980351
Short name T84
Test name
Test status
Simulation time 22498617 ps
CPU time 1.46 seconds
Started Jun 02 01:26:19 PM PDT 24
Finished Jun 02 01:26:21 PM PDT 24
Peak memory 213376 kb
Host smart-ec6569a4-ca71-4b81-9600-92d908654af6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833980351 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_smoke.833980351
Directory /workspace/34.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_failure.1615033527
Short name T450
Test name
Test status
Simulation time 2094007641 ps
CPU time 16.87 seconds
Started Jun 02 01:26:18 PM PDT 24
Finished Jun 02 01:26:35 PM PDT 24
Peak memory 251028 kb
Host smart-a47db9d6-8c8a-4bdc-b0b5-e28107b974e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615033527 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_failure.1615033527
Directory /workspace/34.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_post_trans.764310940
Short name T743
Test name
Test status
Simulation time 510577686 ps
CPU time 9.72 seconds
Started Jun 02 01:26:17 PM PDT 24
Finished Jun 02 01:26:27 PM PDT 24
Peak memory 251008 kb
Host smart-f106773f-0472-44b5-8ad1-9b089e3f5ce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764310940 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_post_trans.764310940
Directory /workspace/34.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all.1732266705
Short name T734
Test name
Test status
Simulation time 8053212644 ps
CPU time 71.6 seconds
Started Jun 02 01:26:18 PM PDT 24
Finished Jun 02 01:27:31 PM PDT 24
Peak memory 251044 kb
Host smart-a3b3a7f8-7b6d-4931-a2f5-66961d58445d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732266705 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.lc_ctrl_stress_all.1732266705
Directory /workspace/34.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all_with_rand_reset.2679800927
Short name T51
Test name
Test status
Simulation time 7006822185 ps
CPU time 259.91 seconds
Started Jun 02 01:26:21 PM PDT 24
Finished Jun 02 01:30:42 PM PDT 24
Peak memory 275772 kb
Host smart-bf317f97-9d31-4570-a011-a534bc3b4777
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2679800927 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_stress_all_with_rand_reset.2679800927
Directory /workspace/34.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.lc_ctrl_volatile_unlock_smoke.2006604180
Short name T704
Test name
Test status
Simulation time 24545502 ps
CPU time 1.11 seconds
Started Jun 02 01:26:21 PM PDT 24
Finished Jun 02 01:26:23 PM PDT 24
Peak memory 211544 kb
Host smart-5c174f29-d563-41ed-b3df-157067841c9f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006604180 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_c
trl_volatile_unlock_smoke.2006604180
Directory /workspace/34.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_alert_test.3909830508
Short name T317
Test name
Test status
Simulation time 47531745 ps
CPU time 0.97 seconds
Started Jun 02 01:26:28 PM PDT 24
Finished Jun 02 01:26:29 PM PDT 24
Peak memory 209436 kb
Host smart-c855b06c-76cd-42de-89d9-e1b0a14c117e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909830508 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_alert_test.3909830508
Directory /workspace/35.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.lc_ctrl_errors.3152149557
Short name T765
Test name
Test status
Simulation time 1157161274 ps
CPU time 12.44 seconds
Started Jun 02 01:26:29 PM PDT 24
Finished Jun 02 01:26:42 PM PDT 24
Peak memory 218012 kb
Host smart-2de4e31a-4fdd-454b-b6d2-aa7f469badd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152149557 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_errors.3152149557
Directory /workspace/35.lc_ctrl_errors/latest

Test location /workspace/coverage/default/35.lc_ctrl_jtag_access.364203556
Short name T524
Test name
Test status
Simulation time 620308700 ps
CPU time 4.91 seconds
Started Jun 02 01:26:26 PM PDT 24
Finished Jun 02 01:26:32 PM PDT 24
Peak memory 209548 kb
Host smart-ec9cea38-4bb7-4e3f-b533-4f2ef87817a7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364203556 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_jtag_access.364203556
Directory /workspace/35.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/35.lc_ctrl_prog_failure.2346818029
Short name T484
Test name
Test status
Simulation time 73120178 ps
CPU time 1.69 seconds
Started Jun 02 01:26:26 PM PDT 24
Finished Jun 02 01:26:29 PM PDT 24
Peak memory 218068 kb
Host smart-93fb931a-31b5-42c6-a288-5d4fcdf7a52b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346818029 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_prog_failure.2346818029
Directory /workspace/35.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_mubi.2107535858
Short name T607
Test name
Test status
Simulation time 2483473723 ps
CPU time 14 seconds
Started Jun 02 01:26:28 PM PDT 24
Finished Jun 02 01:26:42 PM PDT 24
Peak memory 219164 kb
Host smart-dc446d14-0607-4b32-aaac-71a01fd25dc3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107535858 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_mubi.2107535858
Directory /workspace/35.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_digest.1854692276
Short name T205
Test name
Test status
Simulation time 684661430 ps
CPU time 16.19 seconds
Started Jun 02 01:26:27 PM PDT 24
Finished Jun 02 01:26:45 PM PDT 24
Peak memory 226156 kb
Host smart-db633d8d-bcb9-4953-a0fe-be1c8ccde50c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854692276 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_d
igest.1854692276
Directory /workspace/35.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_mux.2935021652
Short name T268
Test name
Test status
Simulation time 2821643097 ps
CPU time 14.18 seconds
Started Jun 02 01:26:29 PM PDT 24
Finished Jun 02 01:26:44 PM PDT 24
Peak memory 218160 kb
Host smart-0720de8b-ef7a-4e2b-b6d0-86186d3a3741
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935021652 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_mux.
2935021652
Directory /workspace/35.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/35.lc_ctrl_security_escalation.1642686601
Short name T59
Test name
Test status
Simulation time 709331759 ps
CPU time 9.74 seconds
Started Jun 02 01:26:26 PM PDT 24
Finished Jun 02 01:26:36 PM PDT 24
Peak memory 218136 kb
Host smart-cae14a4d-cdb5-4029-83b6-7348648ab520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642686601 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_security_escalation.1642686601
Directory /workspace/35.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/35.lc_ctrl_smoke.2243494467
Short name T295
Test name
Test status
Simulation time 288602192 ps
CPU time 3.13 seconds
Started Jun 02 01:26:22 PM PDT 24
Finished Jun 02 01:26:25 PM PDT 24
Peak memory 214560 kb
Host smart-dd195a8f-5c18-4184-9544-5d765c7074dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243494467 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_smoke.2243494467
Directory /workspace/35.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_failure.1165108766
Short name T692
Test name
Test status
Simulation time 908038671 ps
CPU time 19.6 seconds
Started Jun 02 01:26:20 PM PDT 24
Finished Jun 02 01:26:40 PM PDT 24
Peak memory 250944 kb
Host smart-c8916f59-2369-4afe-8f41-a1bbbaf2a6ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165108766 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_failure.1165108766
Directory /workspace/35.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_post_trans.3471410139
Short name T470
Test name
Test status
Simulation time 140102455 ps
CPU time 6.8 seconds
Started Jun 02 01:26:28 PM PDT 24
Finished Jun 02 01:26:36 PM PDT 24
Peak memory 245572 kb
Host smart-a20f7e80-9822-41bd-b5f6-1133b10d718f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471410139 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_post_trans.3471410139
Directory /workspace/35.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all.3376353461
Short name T151
Test name
Test status
Simulation time 18121438839 ps
CPU time 78.72 seconds
Started Jun 02 01:26:29 PM PDT 24
Finished Jun 02 01:27:48 PM PDT 24
Peak memory 251016 kb
Host smart-f500d765-9b1a-43bb-8041-104229135fc9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376353461 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.lc_ctrl_stress_all.3376353461
Directory /workspace/35.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.lc_ctrl_volatile_unlock_smoke.3202922583
Short name T316
Test name
Test status
Simulation time 23306951 ps
CPU time 1.38 seconds
Started Jun 02 01:26:18 PM PDT 24
Finished Jun 02 01:26:21 PM PDT 24
Peak memory 212620 kb
Host smart-08d77b3c-abc8-4427-a5b9-904bb9d751ee
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202922583 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_c
trl_volatile_unlock_smoke.3202922583
Directory /workspace/35.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_alert_test.1009691505
Short name T805
Test name
Test status
Simulation time 23589409 ps
CPU time 0.95 seconds
Started Jun 02 01:26:29 PM PDT 24
Finished Jun 02 01:26:30 PM PDT 24
Peak memory 208632 kb
Host smart-17493613-54de-4e1d-bcbe-3cafd309639a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009691505 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_alert_test.1009691505
Directory /workspace/36.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.lc_ctrl_errors.936280823
Short name T329
Test name
Test status
Simulation time 1285697887 ps
CPU time 9.36 seconds
Started Jun 02 01:26:31 PM PDT 24
Finished Jun 02 01:26:40 PM PDT 24
Peak memory 217980 kb
Host smart-c23c5fdb-5c3b-462c-a35a-3220b97aec1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936280823 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_errors.936280823
Directory /workspace/36.lc_ctrl_errors/latest

Test location /workspace/coverage/default/36.lc_ctrl_jtag_access.2732917514
Short name T663
Test name
Test status
Simulation time 803971979 ps
CPU time 19.8 seconds
Started Jun 02 01:26:26 PM PDT 24
Finished Jun 02 01:26:47 PM PDT 24
Peak memory 217272 kb
Host smart-d9a2ae9e-f52c-4a49-9ea8-3cc9abea2bac
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732917514 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_jtag_access.2732917514
Directory /workspace/36.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/36.lc_ctrl_prog_failure.1602121861
Short name T666
Test name
Test status
Simulation time 245842790 ps
CPU time 3.4 seconds
Started Jun 02 01:26:28 PM PDT 24
Finished Jun 02 01:26:32 PM PDT 24
Peak memory 218104 kb
Host smart-61dbd5ac-7201-4ea9-a381-59856501a662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602121861 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_prog_failure.1602121861
Directory /workspace/36.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_mubi.2804952008
Short name T636
Test name
Test status
Simulation time 2149387889 ps
CPU time 10.39 seconds
Started Jun 02 01:26:26 PM PDT 24
Finished Jun 02 01:26:37 PM PDT 24
Peak memory 226144 kb
Host smart-d4909b6b-1026-4cee-b5fa-8e4865da1ac1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804952008 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_mubi.2804952008
Directory /workspace/36.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_digest.897725690
Short name T252
Test name
Test status
Simulation time 197866352 ps
CPU time 8.01 seconds
Started Jun 02 01:26:28 PM PDT 24
Finished Jun 02 01:26:37 PM PDT 24
Peak memory 217900 kb
Host smart-137e112e-e33d-4f09-91ae-4e544acf68e3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897725690 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_di
gest.897725690
Directory /workspace/36.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_mux.2942074526
Short name T43
Test name
Test status
Simulation time 208180774 ps
CPU time 9.03 seconds
Started Jun 02 01:26:26 PM PDT 24
Finished Jun 02 01:26:36 PM PDT 24
Peak memory 217972 kb
Host smart-90c3a50a-82ad-4760-a48f-f56fb692e1cb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942074526 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_mux.
2942074526
Directory /workspace/36.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/36.lc_ctrl_security_escalation.666191138
Short name T474
Test name
Test status
Simulation time 998689046 ps
CPU time 9.55 seconds
Started Jun 02 01:26:28 PM PDT 24
Finished Jun 02 01:26:38 PM PDT 24
Peak memory 218100 kb
Host smart-966c1c8a-fc46-40bd-afba-7ee244de8c4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666191138 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_security_escalation.666191138
Directory /workspace/36.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/36.lc_ctrl_smoke.2179145851
Short name T31
Test name
Test status
Simulation time 329651800 ps
CPU time 2.48 seconds
Started Jun 02 01:26:29 PM PDT 24
Finished Jun 02 01:26:32 PM PDT 24
Peak memory 214316 kb
Host smart-eb7a59ac-528c-40b7-a340-e87e7733c2f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179145851 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_smoke.2179145851
Directory /workspace/36.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_failure.1236823379
Short name T14
Test name
Test status
Simulation time 1122654273 ps
CPU time 28.46 seconds
Started Jun 02 01:26:30 PM PDT 24
Finished Jun 02 01:26:58 PM PDT 24
Peak memory 251008 kb
Host smart-24b7e763-87e8-4396-8bdb-14a7db5f80cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236823379 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_failure.1236823379
Directory /workspace/36.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_post_trans.179450403
Short name T312
Test name
Test status
Simulation time 139382814 ps
CPU time 9.55 seconds
Started Jun 02 01:26:27 PM PDT 24
Finished Jun 02 01:26:38 PM PDT 24
Peak memory 250960 kb
Host smart-6f09a9e5-96a5-43db-bab6-63481ccab0fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179450403 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_post_trans.179450403
Directory /workspace/36.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all.427917424
Short name T847
Test name
Test status
Simulation time 12335732298 ps
CPU time 153.94 seconds
Started Jun 02 01:26:26 PM PDT 24
Finished Jun 02 01:29:01 PM PDT 24
Peak memory 283576 kb
Host smart-85308167-0846-4fa0-a23b-51261f0941ca
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427917424 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.lc_ctrl_stress_all.427917424
Directory /workspace/36.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.lc_ctrl_volatile_unlock_smoke.1992905467
Short name T537
Test name
Test status
Simulation time 66888931 ps
CPU time 0.78 seconds
Started Jun 02 01:26:30 PM PDT 24
Finished Jun 02 01:26:31 PM PDT 24
Peak memory 208536 kb
Host smart-4561114f-17ab-47a2-ae4c-dfd09f105b77
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992905467 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_c
trl_volatile_unlock_smoke.1992905467
Directory /workspace/36.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_alert_test.3048972780
Short name T88
Test name
Test status
Simulation time 13996660 ps
CPU time 1.01 seconds
Started Jun 02 01:26:34 PM PDT 24
Finished Jun 02 01:26:35 PM PDT 24
Peak memory 208632 kb
Host smart-476e8b10-93b2-4ffa-9534-fa1c166bd212
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048972780 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_alert_test.3048972780
Directory /workspace/37.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.lc_ctrl_errors.3108143126
Short name T250
Test name
Test status
Simulation time 1740427901 ps
CPU time 9.97 seconds
Started Jun 02 01:26:34 PM PDT 24
Finished Jun 02 01:26:44 PM PDT 24
Peak memory 217936 kb
Host smart-fe800843-1952-456c-864d-074bf0bb0eb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108143126 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_errors.3108143126
Directory /workspace/37.lc_ctrl_errors/latest

Test location /workspace/coverage/default/37.lc_ctrl_jtag_access.2035418053
Short name T851
Test name
Test status
Simulation time 381025448 ps
CPU time 8.97 seconds
Started Jun 02 01:26:34 PM PDT 24
Finished Jun 02 01:26:43 PM PDT 24
Peak memory 209484 kb
Host smart-d2148f2a-008b-402c-99e0-40fa13583ea7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035418053 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_jtag_access.2035418053
Directory /workspace/37.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/37.lc_ctrl_prog_failure.3632846791
Short name T194
Test name
Test status
Simulation time 67033044 ps
CPU time 2.51 seconds
Started Jun 02 01:26:30 PM PDT 24
Finished Jun 02 01:26:33 PM PDT 24
Peak memory 218088 kb
Host smart-642a6580-f2c5-4988-aabe-4c512715d632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632846791 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_prog_failure.3632846791
Directory /workspace/37.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_mubi.263085629
Short name T254
Test name
Test status
Simulation time 303197268 ps
CPU time 15.92 seconds
Started Jun 02 01:26:35 PM PDT 24
Finished Jun 02 01:26:51 PM PDT 24
Peak memory 218032 kb
Host smart-b1763a8c-af86-414e-b612-f4fa2810e0b3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263085629 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_mubi.263085629
Directory /workspace/37.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_digest.275089401
Short name T196
Test name
Test status
Simulation time 906913537 ps
CPU time 10.56 seconds
Started Jun 02 01:26:33 PM PDT 24
Finished Jun 02 01:26:44 PM PDT 24
Peak memory 217928 kb
Host smart-940dcbb0-338f-4a3e-b701-725a1da73a7f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275089401 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_di
gest.275089401
Directory /workspace/37.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_mux.3396852261
Short name T499
Test name
Test status
Simulation time 1019344769 ps
CPU time 7.65 seconds
Started Jun 02 01:26:36 PM PDT 24
Finished Jun 02 01:26:44 PM PDT 24
Peak memory 218016 kb
Host smart-5d8c0ee9-f110-43cb-ba11-b88cd4524484
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396852261 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_mux.
3396852261
Directory /workspace/37.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/37.lc_ctrl_security_escalation.3844300593
Short name T758
Test name
Test status
Simulation time 382245098 ps
CPU time 8.4 seconds
Started Jun 02 01:26:33 PM PDT 24
Finished Jun 02 01:26:42 PM PDT 24
Peak memory 218068 kb
Host smart-139ca1b3-c270-4ef9-892d-f4058d435931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844300593 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_security_escalation.3844300593
Directory /workspace/37.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/37.lc_ctrl_smoke.2392913903
Short name T238
Test name
Test status
Simulation time 93499804 ps
CPU time 2.81 seconds
Started Jun 02 01:26:26 PM PDT 24
Finished Jun 02 01:26:30 PM PDT 24
Peak memory 217724 kb
Host smart-b4994a25-ea40-48e0-8cf6-3541da6259e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392913903 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_smoke.2392913903
Directory /workspace/37.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_failure.2111169874
Short name T862
Test name
Test status
Simulation time 1209422119 ps
CPU time 30.4 seconds
Started Jun 02 01:26:26 PM PDT 24
Finished Jun 02 01:26:57 PM PDT 24
Peak memory 250952 kb
Host smart-8c612a22-732a-429a-87c4-f06bba30122c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111169874 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_failure.2111169874
Directory /workspace/37.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_post_trans.2057206256
Short name T579
Test name
Test status
Simulation time 45232983 ps
CPU time 3.14 seconds
Started Jun 02 01:26:29 PM PDT 24
Finished Jun 02 01:26:33 PM PDT 24
Peak memory 222684 kb
Host smart-fb83e99e-91ac-4efc-be31-0f92e28c4a07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057206256 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_post_trans.2057206256
Directory /workspace/37.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all.4085373760
Short name T72
Test name
Test status
Simulation time 78891514360 ps
CPU time 526.41 seconds
Started Jun 02 01:26:34 PM PDT 24
Finished Jun 02 01:35:21 PM PDT 24
Peak memory 290000 kb
Host smart-03edc479-2980-4135-8b95-4c6bc13afe0a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085373760 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.lc_ctrl_stress_all.4085373760
Directory /workspace/37.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.lc_ctrl_volatile_unlock_smoke.1336648198
Short name T518
Test name
Test status
Simulation time 14576803 ps
CPU time 0.8 seconds
Started Jun 02 01:26:31 PM PDT 24
Finished Jun 02 01:26:32 PM PDT 24
Peak memory 208704 kb
Host smart-da00361c-abcd-4b99-96a0-0bd599846b39
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336648198 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_c
trl_volatile_unlock_smoke.1336648198
Directory /workspace/37.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_alert_test.2058195049
Short name T856
Test name
Test status
Simulation time 56611441 ps
CPU time 0.87 seconds
Started Jun 02 01:26:34 PM PDT 24
Finished Jun 02 01:26:35 PM PDT 24
Peak memory 208688 kb
Host smart-fd74fd56-c11f-41ea-8d78-989c1dafbf09
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058195049 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_alert_test.2058195049
Directory /workspace/38.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.lc_ctrl_errors.1805363814
Short name T149
Test name
Test status
Simulation time 379822968 ps
CPU time 14.98 seconds
Started Jun 02 01:26:34 PM PDT 24
Finished Jun 02 01:26:50 PM PDT 24
Peak memory 218008 kb
Host smart-f8e2ddae-a402-4292-8313-a3c86a9389b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805363814 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_errors.1805363814
Directory /workspace/38.lc_ctrl_errors/latest

Test location /workspace/coverage/default/38.lc_ctrl_jtag_access.1228448213
Short name T564
Test name
Test status
Simulation time 438506859 ps
CPU time 5.74 seconds
Started Jun 02 01:26:33 PM PDT 24
Finished Jun 02 01:26:40 PM PDT 24
Peak memory 217368 kb
Host smart-6f5b3945-10c1-40c3-ba87-a93f6aec266e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228448213 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_jtag_access.1228448213
Directory /workspace/38.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/38.lc_ctrl_prog_failure.2769370043
Short name T294
Test name
Test status
Simulation time 58661467 ps
CPU time 1.84 seconds
Started Jun 02 01:26:36 PM PDT 24
Finished Jun 02 01:26:38 PM PDT 24
Peak memory 218068 kb
Host smart-e0d3fd3f-5216-42da-b889-6d1bcd717f92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769370043 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_prog_failure.2769370043
Directory /workspace/38.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_mubi.2383010463
Short name T314
Test name
Test status
Simulation time 380139081 ps
CPU time 13.5 seconds
Started Jun 02 01:26:38 PM PDT 24
Finished Jun 02 01:26:52 PM PDT 24
Peak memory 226100 kb
Host smart-b5ef052f-5c36-4b45-822e-a7c4aa234739
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383010463 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_mubi.2383010463
Directory /workspace/38.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_digest.3965960344
Short name T334
Test name
Test status
Simulation time 2353879313 ps
CPU time 12.75 seconds
Started Jun 02 01:26:35 PM PDT 24
Finished Jun 02 01:26:48 PM PDT 24
Peak memory 225844 kb
Host smart-ff86ea3d-e07c-4858-a1cd-86c978bdfbd6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965960344 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_d
igest.3965960344
Directory /workspace/38.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_mux.1097597581
Short name T422
Test name
Test status
Simulation time 971197365 ps
CPU time 9.83 seconds
Started Jun 02 01:26:34 PM PDT 24
Finished Jun 02 01:26:45 PM PDT 24
Peak memory 218016 kb
Host smart-12611224-c532-4fc2-9b8b-b3ca58308ae3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097597581 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_mux.
1097597581
Directory /workspace/38.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/38.lc_ctrl_security_escalation.612257225
Short name T606
Test name
Test status
Simulation time 410559858 ps
CPU time 9.61 seconds
Started Jun 02 01:26:34 PM PDT 24
Finished Jun 02 01:26:45 PM PDT 24
Peak memory 218032 kb
Host smart-4a73ead0-860b-4b12-9124-c718dc136c6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612257225 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_security_escalation.612257225
Directory /workspace/38.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/38.lc_ctrl_smoke.1657358137
Short name T731
Test name
Test status
Simulation time 878979644 ps
CPU time 12.94 seconds
Started Jun 02 01:26:33 PM PDT 24
Finished Jun 02 01:26:46 PM PDT 24
Peak memory 217676 kb
Host smart-2bc7f737-291d-4a4a-a738-97782f180393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657358137 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_smoke.1657358137
Directory /workspace/38.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_failure.3000498869
Short name T696
Test name
Test status
Simulation time 445141411 ps
CPU time 31.12 seconds
Started Jun 02 01:26:36 PM PDT 24
Finished Jun 02 01:27:07 PM PDT 24
Peak memory 251008 kb
Host smart-ea092fb1-7ade-4761-8130-b60ded1acb10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000498869 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_failure.3000498869
Directory /workspace/38.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_post_trans.447426333
Short name T530
Test name
Test status
Simulation time 400144802 ps
CPU time 6.15 seconds
Started Jun 02 01:26:35 PM PDT 24
Finished Jun 02 01:26:42 PM PDT 24
Peak memory 246612 kb
Host smart-18ae87bb-af55-4f70-a8c8-4fe9eb4e4bc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447426333 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_post_trans.447426333
Directory /workspace/38.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all.2240250078
Short name T721
Test name
Test status
Simulation time 53156340895 ps
CPU time 267.63 seconds
Started Jun 02 01:26:40 PM PDT 24
Finished Jun 02 01:31:08 PM PDT 24
Peak memory 302192 kb
Host smart-9feea72b-b75e-4185-bec9-dddbb4e8ca7d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240250078 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.lc_ctrl_stress_all.2240250078
Directory /workspace/38.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all_with_rand_reset.4207154150
Short name T44
Test name
Test status
Simulation time 23570006318 ps
CPU time 375.35 seconds
Started Jun 02 01:26:34 PM PDT 24
Finished Jun 02 01:32:49 PM PDT 24
Peak memory 283936 kb
Host smart-2cb464a5-8f44-475f-b6e5-f5eb0ac51066
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4207154150 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_stress_all_with_rand_reset.4207154150
Directory /workspace/38.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.lc_ctrl_volatile_unlock_smoke.4112863677
Short name T82
Test name
Test status
Simulation time 19789228 ps
CPU time 0.97 seconds
Started Jun 02 01:26:35 PM PDT 24
Finished Jun 02 01:26:37 PM PDT 24
Peak memory 212564 kb
Host smart-f9e2166c-9dda-425b-9d1b-ae19f67c1778
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112863677 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_c
trl_volatile_unlock_smoke.4112863677
Directory /workspace/38.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_alert_test.1421868252
Short name T674
Test name
Test status
Simulation time 23919333 ps
CPU time 1.26 seconds
Started Jun 02 01:26:32 PM PDT 24
Finished Jun 02 01:26:34 PM PDT 24
Peak memory 208768 kb
Host smart-fc49394e-1707-4930-9d79-aa27bf89f83c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421868252 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_alert_test.1421868252
Directory /workspace/39.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.lc_ctrl_errors.987406766
Short name T99
Test name
Test status
Simulation time 254577568 ps
CPU time 12.61 seconds
Started Jun 02 01:26:34 PM PDT 24
Finished Jun 02 01:26:47 PM PDT 24
Peak memory 217952 kb
Host smart-a8a28bc1-2c26-49b1-a743-02ec5d8e1d21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987406766 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_errors.987406766
Directory /workspace/39.lc_ctrl_errors/latest

Test location /workspace/coverage/default/39.lc_ctrl_jtag_access.1287634021
Short name T355
Test name
Test status
Simulation time 370729717 ps
CPU time 3.8 seconds
Started Jun 02 01:26:33 PM PDT 24
Finished Jun 02 01:26:38 PM PDT 24
Peak memory 209508 kb
Host smart-f1d26a8c-7b72-4b20-8628-22f0f9cc717f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287634021 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_jtag_access.1287634021
Directory /workspace/39.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/39.lc_ctrl_prog_failure.68369523
Short name T651
Test name
Test status
Simulation time 99654440 ps
CPU time 3.8 seconds
Started Jun 02 01:26:34 PM PDT 24
Finished Jun 02 01:26:39 PM PDT 24
Peak memory 217992 kb
Host smart-8dc2e99a-89a3-4d68-9de0-06a5a17d6e01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68369523 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_prog_failure.68369523
Directory /workspace/39.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_mubi.1879908002
Short name T54
Test name
Test status
Simulation time 2245434960 ps
CPU time 17.41 seconds
Started Jun 02 01:26:40 PM PDT 24
Finished Jun 02 01:26:58 PM PDT 24
Peak memory 219036 kb
Host smart-2a9945e8-27b8-41b0-bdcb-3210e86d631c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879908002 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_mubi.1879908002
Directory /workspace/39.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_digest.3482354425
Short name T491
Test name
Test status
Simulation time 2421329094 ps
CPU time 12.34 seconds
Started Jun 02 01:26:35 PM PDT 24
Finished Jun 02 01:26:48 PM PDT 24
Peak memory 226060 kb
Host smart-890241dc-eedf-4af9-a7dc-221453e2e03b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482354425 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_d
igest.3482354425
Directory /workspace/39.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_mux.3171178551
Short name T561
Test name
Test status
Simulation time 1223327409 ps
CPU time 7.76 seconds
Started Jun 02 01:26:35 PM PDT 24
Finished Jun 02 01:26:44 PM PDT 24
Peak memory 218016 kb
Host smart-0d23c5c8-d0ac-4880-bf04-c5c16e0abf42
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171178551 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_mux.
3171178551
Directory /workspace/39.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/39.lc_ctrl_security_escalation.4156817545
Short name T445
Test name
Test status
Simulation time 1165587009 ps
CPU time 14.14 seconds
Started Jun 02 01:26:36 PM PDT 24
Finished Jun 02 01:26:51 PM PDT 24
Peak memory 218088 kb
Host smart-4286fe43-aab9-41e8-b834-38c9bd65f73f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156817545 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_security_escalation.4156817545
Directory /workspace/39.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/39.lc_ctrl_smoke.3673262077
Short name T589
Test name
Test status
Simulation time 33226159 ps
CPU time 1.42 seconds
Started Jun 02 01:26:33 PM PDT 24
Finished Jun 02 01:26:35 PM PDT 24
Peak memory 218304 kb
Host smart-2adf4465-d63c-42c7-b94a-6955bd6c2929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673262077 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_smoke.3673262077
Directory /workspace/39.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_failure.451897811
Short name T220
Test name
Test status
Simulation time 1625033197 ps
CPU time 28.1 seconds
Started Jun 02 01:26:35 PM PDT 24
Finished Jun 02 01:27:03 PM PDT 24
Peak memory 251024 kb
Host smart-46d9cf9b-f1a2-49e1-a315-e5910ce6c0d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451897811 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_failure.451897811
Directory /workspace/39.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_post_trans.283118329
Short name T222
Test name
Test status
Simulation time 105248520 ps
CPU time 8.61 seconds
Started Jun 02 01:26:40 PM PDT 24
Finished Jun 02 01:26:49 PM PDT 24
Peak memory 250972 kb
Host smart-e777c289-3bbc-4752-a61b-61e7437198cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283118329 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_post_trans.283118329
Directory /workspace/39.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all.1775582412
Short name T550
Test name
Test status
Simulation time 3192785204 ps
CPU time 106.34 seconds
Started Jun 02 01:26:39 PM PDT 24
Finished Jun 02 01:28:26 PM PDT 24
Peak memory 226160 kb
Host smart-a315bca3-52fa-44c5-974e-045e36bd5d8d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775582412 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.lc_ctrl_stress_all.1775582412
Directory /workspace/39.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.lc_ctrl_volatile_unlock_smoke.992338082
Short name T275
Test name
Test status
Simulation time 17009714 ps
CPU time 0.79 seconds
Started Jun 02 01:26:34 PM PDT 24
Finished Jun 02 01:26:36 PM PDT 24
Peak memory 208492 kb
Host smart-81049bfc-70f3-4269-835b-1421dd6c6bc6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992338082 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ct
rl_volatile_unlock_smoke.992338082
Directory /workspace/39.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_alert_test.2678878505
Short name T306
Test name
Test status
Simulation time 265784986 ps
CPU time 0.98 seconds
Started Jun 02 01:24:10 PM PDT 24
Finished Jun 02 01:24:12 PM PDT 24
Peak memory 209472 kb
Host smart-d77c1485-54b1-498a-ab58-ec25824e4a7b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678878505 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_alert_test.2678878505
Directory /workspace/4.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.lc_ctrl_claim_transition_if.1765717392
Short name T483
Test name
Test status
Simulation time 26185523 ps
CPU time 0.96 seconds
Started Jun 02 01:24:10 PM PDT 24
Finished Jun 02 01:24:11 PM PDT 24
Peak memory 208720 kb
Host smart-aab1c7a2-7149-46f9-b245-771d234f15c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765717392 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_claim_transition_if.1765717392
Directory /workspace/4.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/4.lc_ctrl_errors.3223952109
Short name T821
Test name
Test status
Simulation time 247778224 ps
CPU time 12.37 seconds
Started Jun 02 01:24:07 PM PDT 24
Finished Jun 02 01:24:20 PM PDT 24
Peak memory 218012 kb
Host smart-2ab6237d-3fee-4095-b721-3db1af8e051a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223952109 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_errors.3223952109
Directory /workspace/4.lc_ctrl_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_access.254907243
Short name T784
Test name
Test status
Simulation time 301241175 ps
CPU time 3.04 seconds
Started Jun 02 01:24:08 PM PDT 24
Finished Jun 02 01:24:12 PM PDT 24
Peak memory 217056 kb
Host smart-89619fc2-3d92-409b-8982-2b10765a4012
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254907243 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_access.254907243
Directory /workspace/4.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_errors.2953532248
Short name T367
Test name
Test status
Simulation time 14559387037 ps
CPU time 60.31 seconds
Started Jun 02 01:24:07 PM PDT 24
Finished Jun 02 01:25:08 PM PDT 24
Peak memory 218952 kb
Host smart-cf8530f4-7bb3-442f-9c1c-476624ef151a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953532248 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_er
rors.2953532248
Directory /workspace/4.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_priority.2465403847
Short name T434
Test name
Test status
Simulation time 2963544687 ps
CPU time 30.31 seconds
Started Jun 02 01:24:09 PM PDT 24
Finished Jun 02 01:24:40 PM PDT 24
Peak memory 217396 kb
Host smart-db591501-b49d-4313-a40e-7d6ae67c29f1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465403847 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_priority.2
465403847
Directory /workspace/4.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_prog_failure.1578005863
Short name T421
Test name
Test status
Simulation time 473834012 ps
CPU time 7.37 seconds
Started Jun 02 01:24:10 PM PDT 24
Finished Jun 02 01:24:18 PM PDT 24
Peak memory 217948 kb
Host smart-971870c9-5b8f-4fff-b832-954f1a00ecda
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578005863 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag
_prog_failure.1578005863
Directory /workspace/4.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_regwen_during_op.3696908382
Short name T582
Test name
Test status
Simulation time 9073365900 ps
CPU time 23.54 seconds
Started Jun 02 01:24:11 PM PDT 24
Finished Jun 02 01:24:34 PM PDT 24
Peak memory 217664 kb
Host smart-4eef8ca8-4eb5-4cf7-88c4-75f941fb85d8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696908382 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_regwen_during_op.3696908382
Directory /workspace/4.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_smoke.597505485
Short name T395
Test name
Test status
Simulation time 188531360 ps
CPU time 6.46 seconds
Started Jun 02 01:24:07 PM PDT 24
Finished Jun 02 01:24:14 PM PDT 24
Peak memory 217764 kb
Host smart-6638622d-6f2a-4b28-8328-a5e292cdadd9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597505485 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_smoke.597505485
Directory /workspace/4.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_failure.3747858536
Short name T204
Test name
Test status
Simulation time 7033518452 ps
CPU time 46.01 seconds
Started Jun 02 01:24:07 PM PDT 24
Finished Jun 02 01:24:53 PM PDT 24
Peak memory 277588 kb
Host smart-b652d8c0-0589-449b-bb58-45cda5119213
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747858536 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jta
g_state_failure.3747858536
Directory /workspace/4.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_post_trans.2562229552
Short name T211
Test name
Test status
Simulation time 2169057554 ps
CPU time 20.92 seconds
Started Jun 02 01:24:11 PM PDT 24
Finished Jun 02 01:24:32 PM PDT 24
Peak memory 250964 kb
Host smart-4d7af829-1027-4079-9a17-a1479692fc92
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562229552 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_state_post_trans.2562229552
Directory /workspace/4.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_prog_failure.116383526
Short name T789
Test name
Test status
Simulation time 162155666 ps
CPU time 2.82 seconds
Started Jun 02 01:24:10 PM PDT 24
Finished Jun 02 01:24:13 PM PDT 24
Peak memory 218012 kb
Host smart-c5988ca5-bdb5-4b5f-a8c4-46c523fbce60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116383526 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_prog_failure.116383526
Directory /workspace/4.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_regwen_during_op.725526565
Short name T839
Test name
Test status
Simulation time 297229413 ps
CPU time 18.43 seconds
Started Jun 02 01:24:07 PM PDT 24
Finished Jun 02 01:24:26 PM PDT 24
Peak memory 214448 kb
Host smart-11d33e38-fa14-4641-8da8-afe2954694e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725526565 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_regwen_during_op.725526565
Directory /workspace/4.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_cm.3043839354
Short name T85
Test name
Test status
Simulation time 685679981 ps
CPU time 23.29 seconds
Started Jun 02 01:24:07 PM PDT 24
Finished Jun 02 01:24:31 PM PDT 24
Peak memory 269568 kb
Host smart-147a1aa7-34e7-4180-8a05-f2e025a1a900
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043839354 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_cm.3043839354
Directory /workspace/4.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_mubi.1064252527
Short name T382
Test name
Test status
Simulation time 358462890 ps
CPU time 14.75 seconds
Started Jun 02 01:24:11 PM PDT 24
Finished Jun 02 01:24:26 PM PDT 24
Peak memory 226096 kb
Host smart-64940ab8-1b5f-4c2e-8165-29027cde55f7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064252527 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_mubi.1064252527
Directory /workspace/4.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_digest.1276643548
Short name T462
Test name
Test status
Simulation time 1035860958 ps
CPU time 7.68 seconds
Started Jun 02 01:24:07 PM PDT 24
Finished Jun 02 01:24:15 PM PDT 24
Peak memory 217940 kb
Host smart-58fe4013-41fb-414c-80c6-7f1fd0c7ca81
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276643548 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_di
gest.1276643548
Directory /workspace/4.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_mux.3728499810
Short name T593
Test name
Test status
Simulation time 675318766 ps
CPU time 9.48 seconds
Started Jun 02 01:24:06 PM PDT 24
Finished Jun 02 01:24:16 PM PDT 24
Peak memory 218028 kb
Host smart-4e80c554-dc52-4ba0-a8cf-b887504bdab0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728499810 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_mux.3
728499810
Directory /workspace/4.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/4.lc_ctrl_security_escalation.3603044986
Short name T227
Test name
Test status
Simulation time 3340831947 ps
CPU time 9.22 seconds
Started Jun 02 01:24:09 PM PDT 24
Finished Jun 02 01:24:19 PM PDT 24
Peak memory 218092 kb
Host smart-2b798e69-c7a9-4644-b25c-40aec80f8bac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603044986 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_security_escalation.3603044986
Directory /workspace/4.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/4.lc_ctrl_smoke.1856224390
Short name T476
Test name
Test status
Simulation time 26351803 ps
CPU time 1.56 seconds
Started Jun 02 01:24:08 PM PDT 24
Finished Jun 02 01:24:10 PM PDT 24
Peak memory 213692 kb
Host smart-dadf8b13-f112-40f8-a28c-c8eeeba08158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856224390 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_smoke.1856224390
Directory /workspace/4.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_failure.3332946552
Short name T35
Test name
Test status
Simulation time 3057162747 ps
CPU time 33.82 seconds
Started Jun 02 01:24:07 PM PDT 24
Finished Jun 02 01:24:41 PM PDT 24
Peak memory 251068 kb
Host smart-2fd05f01-e9b4-4674-ae3f-5fba1ca9de47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332946552 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_failure.3332946552
Directory /workspace/4.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_post_trans.174905444
Short name T344
Test name
Test status
Simulation time 59705066 ps
CPU time 9.78 seconds
Started Jun 02 01:24:07 PM PDT 24
Finished Jun 02 01:24:18 PM PDT 24
Peak memory 250920 kb
Host smart-e516ca25-d9fc-40f3-b800-f9a0a5bbceef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174905444 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_post_trans.174905444
Directory /workspace/4.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_stress_all.1672011307
Short name T52
Test name
Test status
Simulation time 19320902754 ps
CPU time 81.26 seconds
Started Jun 02 01:24:07 PM PDT 24
Finished Jun 02 01:25:29 PM PDT 24
Peak memory 268756 kb
Host smart-e27729c3-0f84-4309-adbc-f15a6e043e43
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672011307 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.lc_ctrl_stress_all.1672011307
Directory /workspace/4.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.lc_ctrl_stress_all_with_rand_reset.1921205775
Short name T178
Test name
Test status
Simulation time 37909557964 ps
CPU time 302.32 seconds
Started Jun 02 01:24:07 PM PDT 24
Finished Jun 02 01:29:10 PM PDT 24
Peak memory 275948 kb
Host smart-1d8fb634-1c00-4270-8683-249dd519183d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1921205775 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_stress_all_with_rand_reset.1921205775
Directory /workspace/4.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.lc_ctrl_volatile_unlock_smoke.3717325468
Short name T573
Test name
Test status
Simulation time 16496447 ps
CPU time 0.97 seconds
Started Jun 02 01:24:07 PM PDT 24
Finished Jun 02 01:24:08 PM PDT 24
Peak memory 212512 kb
Host smart-f31d20c1-3e93-40ea-8a41-23e133f2b55a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717325468 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ct
rl_volatile_unlock_smoke.3717325468
Directory /workspace/4.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_alert_test.966173145
Short name T216
Test name
Test status
Simulation time 17712935 ps
CPU time 1.18 seconds
Started Jun 02 01:26:40 PM PDT 24
Finished Jun 02 01:26:42 PM PDT 24
Peak memory 208708 kb
Host smart-42cf0f07-3c8d-4b85-a8a8-08d3ed7f9b4c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966173145 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_alert_test.966173145
Directory /workspace/40.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.lc_ctrl_errors.1164050184
Short name T273
Test name
Test status
Simulation time 590931177 ps
CPU time 7.53 seconds
Started Jun 02 01:26:40 PM PDT 24
Finished Jun 02 01:26:48 PM PDT 24
Peak memory 217960 kb
Host smart-bfcf7688-690d-4d68-8833-e7be53021901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164050184 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_errors.1164050184
Directory /workspace/40.lc_ctrl_errors/latest

Test location /workspace/coverage/default/40.lc_ctrl_jtag_access.3912671183
Short name T800
Test name
Test status
Simulation time 7183863566 ps
CPU time 5.48 seconds
Started Jun 02 01:26:41 PM PDT 24
Finished Jun 02 01:26:47 PM PDT 24
Peak memory 209592 kb
Host smart-f26155cc-8e34-4806-827b-2826de385dc3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912671183 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_jtag_access.3912671183
Directory /workspace/40.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/40.lc_ctrl_prog_failure.1945319367
Short name T226
Test name
Test status
Simulation time 36978142 ps
CPU time 2.41 seconds
Started Jun 02 01:26:41 PM PDT 24
Finished Jun 02 01:26:43 PM PDT 24
Peak memory 217984 kb
Host smart-1357cd01-8161-471b-9795-d1c0f146e2de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945319367 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_prog_failure.1945319367
Directory /workspace/40.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_mubi.156701906
Short name T311
Test name
Test status
Simulation time 1482819553 ps
CPU time 10.62 seconds
Started Jun 02 01:26:39 PM PDT 24
Finished Jun 02 01:26:50 PM PDT 24
Peak memory 226112 kb
Host smart-2b39efd4-765d-4150-9270-90adf3220fa0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156701906 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_mubi.156701906
Directory /workspace/40.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_digest.88756447
Short name T321
Test name
Test status
Simulation time 1141515243 ps
CPU time 10.59 seconds
Started Jun 02 01:26:41 PM PDT 24
Finished Jun 02 01:26:53 PM PDT 24
Peak memory 217900 kb
Host smart-ddf0bdef-aba3-410a-b8f4-a89b28a71f79
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88756447 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_dig
est_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_dig
est.88756447
Directory /workspace/40.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_mux.1183077896
Short name T588
Test name
Test status
Simulation time 897325925 ps
CPU time 8.76 seconds
Started Jun 02 01:26:41 PM PDT 24
Finished Jun 02 01:26:50 PM PDT 24
Peak memory 218032 kb
Host smart-ec581c33-e3ad-4999-a4b3-42430a7afdf6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183077896 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_mux.
1183077896
Directory /workspace/40.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/40.lc_ctrl_security_escalation.3750371288
Short name T759
Test name
Test status
Simulation time 382006510 ps
CPU time 12.52 seconds
Started Jun 02 01:26:43 PM PDT 24
Finished Jun 02 01:26:55 PM PDT 24
Peak memory 218060 kb
Host smart-260643bd-71b6-4a5c-a998-58bd7bf71b2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750371288 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_security_escalation.3750371288
Directory /workspace/40.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/40.lc_ctrl_smoke.2209028529
Short name T402
Test name
Test status
Simulation time 30494415 ps
CPU time 1.63 seconds
Started Jun 02 01:26:45 PM PDT 24
Finished Jun 02 01:26:47 PM PDT 24
Peak memory 217712 kb
Host smart-35a538aa-64e5-431c-85a0-ee419360ded5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209028529 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_smoke.2209028529
Directory /workspace/40.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_failure.681571930
Short name T471
Test name
Test status
Simulation time 652828387 ps
CPU time 15.36 seconds
Started Jun 02 01:26:40 PM PDT 24
Finished Jun 02 01:26:55 PM PDT 24
Peak memory 250996 kb
Host smart-46b60871-b4d5-4e71-b855-e245d62156a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=681571930 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_failure.681571930
Directory /workspace/40.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_post_trans.3942696291
Short name T350
Test name
Test status
Simulation time 103576117 ps
CPU time 6.82 seconds
Started Jun 02 01:26:44 PM PDT 24
Finished Jun 02 01:26:51 PM PDT 24
Peak memory 250564 kb
Host smart-d210c5bb-c86a-4624-ba65-38012f75b9ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942696291 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_post_trans.3942696291
Directory /workspace/40.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/40.lc_ctrl_stress_all.2326517456
Short name T567
Test name
Test status
Simulation time 10139825836 ps
CPU time 84.77 seconds
Started Jun 02 01:26:44 PM PDT 24
Finished Jun 02 01:28:09 PM PDT 24
Peak memory 248536 kb
Host smart-f7e5023d-8ac0-44fe-85cc-da740eaacd42
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326517456 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.lc_ctrl_stress_all.2326517456
Directory /workspace/40.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.lc_ctrl_volatile_unlock_smoke.434751534
Short name T377
Test name
Test status
Simulation time 14469011 ps
CPU time 0.8 seconds
Started Jun 02 01:26:43 PM PDT 24
Finished Jun 02 01:26:44 PM PDT 24
Peak memory 208524 kb
Host smart-1384fa21-7376-4972-8835-1e4a1402f355
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434751534 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ct
rl_volatile_unlock_smoke.434751534
Directory /workspace/40.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_alert_test.3913278247
Short name T365
Test name
Test status
Simulation time 109906848 ps
CPU time 0.93 seconds
Started Jun 02 01:26:44 PM PDT 24
Finished Jun 02 01:26:45 PM PDT 24
Peak memory 209512 kb
Host smart-44b8b65c-c2bd-4e44-9895-2a7da234d916
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913278247 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_alert_test.3913278247
Directory /workspace/41.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.lc_ctrl_errors.110656674
Short name T482
Test name
Test status
Simulation time 1297179138 ps
CPU time 10.23 seconds
Started Jun 02 01:26:40 PM PDT 24
Finished Jun 02 01:26:51 PM PDT 24
Peak memory 218016 kb
Host smart-8aeb1a63-fd48-461e-9690-87156a1d007e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110656674 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_errors.110656674
Directory /workspace/41.lc_ctrl_errors/latest

Test location /workspace/coverage/default/41.lc_ctrl_jtag_access.297256419
Short name T825
Test name
Test status
Simulation time 244482663 ps
CPU time 4.01 seconds
Started Jun 02 01:26:41 PM PDT 24
Finished Jun 02 01:26:46 PM PDT 24
Peak memory 217120 kb
Host smart-0816eba0-501a-4c39-bd58-49aae74fcdcb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297256419 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_jtag_access.297256419
Directory /workspace/41.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/41.lc_ctrl_prog_failure.3177192501
Short name T277
Test name
Test status
Simulation time 311750839 ps
CPU time 3.96 seconds
Started Jun 02 01:26:45 PM PDT 24
Finished Jun 02 01:26:49 PM PDT 24
Peak memory 218176 kb
Host smart-51b2d6e9-391c-464e-99ea-3ab149bdd5eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177192501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_prog_failure.3177192501
Directory /workspace/41.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_mubi.310751270
Short name T719
Test name
Test status
Simulation time 1972471044 ps
CPU time 14.44 seconds
Started Jun 02 01:26:42 PM PDT 24
Finished Jun 02 01:26:57 PM PDT 24
Peak memory 218896 kb
Host smart-7ec387ac-61fc-49f4-9de1-5b73c0e69eb1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310751270 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_mubi.310751270
Directory /workspace/41.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_digest.922757245
Short name T405
Test name
Test status
Simulation time 539475770 ps
CPU time 14.49 seconds
Started Jun 02 01:26:40 PM PDT 24
Finished Jun 02 01:26:54 PM PDT 24
Peak memory 225644 kb
Host smart-d36620e9-4fbb-4e53-a699-d0ec2bb526a9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922757245 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_di
gest.922757245
Directory /workspace/41.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_mux.1334263805
Short name T185
Test name
Test status
Simulation time 3336261663 ps
CPU time 9.56 seconds
Started Jun 02 01:26:42 PM PDT 24
Finished Jun 02 01:26:52 PM PDT 24
Peak memory 218092 kb
Host smart-7e926c07-459c-4f59-82ba-fc898bc6ce56
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334263805 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_mux.
1334263805
Directory /workspace/41.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/41.lc_ctrl_security_escalation.1484200964
Short name T644
Test name
Test status
Simulation time 1616574277 ps
CPU time 7.86 seconds
Started Jun 02 01:26:45 PM PDT 24
Finished Jun 02 01:26:53 PM PDT 24
Peak memory 218000 kb
Host smart-82a3fb7b-b7ff-42c5-a5ae-3e8f6ca421ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484200964 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_security_escalation.1484200964
Directory /workspace/41.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/41.lc_ctrl_smoke.3937168122
Short name T267
Test name
Test status
Simulation time 332136738 ps
CPU time 2.82 seconds
Started Jun 02 01:26:45 PM PDT 24
Finished Jun 02 01:26:48 PM PDT 24
Peak memory 217716 kb
Host smart-2dc7f412-e26d-4600-9f8f-c0bd7ec83a5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937168122 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_smoke.3937168122
Directory /workspace/41.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_failure.798505096
Short name T628
Test name
Test status
Simulation time 250882267 ps
CPU time 35.85 seconds
Started Jun 02 01:26:45 PM PDT 24
Finished Jun 02 01:27:21 PM PDT 24
Peak memory 247408 kb
Host smart-36b3e355-5b15-44fe-98df-5d6e46fb65e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798505096 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_failure.798505096
Directory /workspace/41.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_post_trans.1022784002
Short name T583
Test name
Test status
Simulation time 53780097 ps
CPU time 6.87 seconds
Started Jun 02 01:26:44 PM PDT 24
Finished Jun 02 01:26:52 PM PDT 24
Peak memory 250996 kb
Host smart-9c496a73-341b-45c1-a7a0-d8dd3fbdf4a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1022784002 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_post_trans.1022784002
Directory /workspace/41.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all.2835557481
Short name T331
Test name
Test status
Simulation time 8541209914 ps
CPU time 154.95 seconds
Started Jun 02 01:26:45 PM PDT 24
Finished Jun 02 01:29:20 PM PDT 24
Peak memory 281492 kb
Host smart-1612893f-6e48-46e8-abc2-5acd1bf1adb3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835557481 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.lc_ctrl_stress_all.2835557481
Directory /workspace/41.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.lc_ctrl_volatile_unlock_smoke.861633019
Short name T675
Test name
Test status
Simulation time 27284964 ps
CPU time 0.76 seconds
Started Jun 02 01:26:44 PM PDT 24
Finished Jun 02 01:26:45 PM PDT 24
Peak memory 208376 kb
Host smart-793d3d29-dd5a-4457-9663-55120692cc54
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861633019 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ct
rl_volatile_unlock_smoke.861633019
Directory /workspace/41.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_alert_test.1979773374
Short name T586
Test name
Test status
Simulation time 19563677 ps
CPU time 0.94 seconds
Started Jun 02 01:26:48 PM PDT 24
Finished Jun 02 01:26:49 PM PDT 24
Peak memory 208920 kb
Host smart-3d89ff46-15aa-4f72-ac1c-f4a1f19234c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979773374 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_alert_test.1979773374
Directory /workspace/42.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.lc_ctrl_errors.989758805
Short name T343
Test name
Test status
Simulation time 477016137 ps
CPU time 12.42 seconds
Started Jun 02 01:26:41 PM PDT 24
Finished Jun 02 01:26:54 PM PDT 24
Peak memory 218020 kb
Host smart-46a83fa1-642d-4962-80fe-96f4fa287541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989758805 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_errors.989758805
Directory /workspace/42.lc_ctrl_errors/latest

Test location /workspace/coverage/default/42.lc_ctrl_prog_failure.3938579133
Short name T555
Test name
Test status
Simulation time 221782472 ps
CPU time 2.94 seconds
Started Jun 02 01:26:40 PM PDT 24
Finished Jun 02 01:26:43 PM PDT 24
Peak memory 218032 kb
Host smart-9efd4a24-fdcb-47de-a757-6778110991e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938579133 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_prog_failure.3938579133
Directory /workspace/42.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_mubi.2835689880
Short name T824
Test name
Test status
Simulation time 1645541490 ps
CPU time 18.98 seconds
Started Jun 02 01:26:50 PM PDT 24
Finished Jun 02 01:27:10 PM PDT 24
Peak memory 225872 kb
Host smart-022a89bc-1a77-4609-88a7-ef92edc0373a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835689880 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_mubi.2835689880
Directory /workspace/42.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_digest.2153996104
Short name T793
Test name
Test status
Simulation time 932610065 ps
CPU time 18.65 seconds
Started Jun 02 01:26:48 PM PDT 24
Finished Jun 02 01:27:07 PM PDT 24
Peak memory 226044 kb
Host smart-dfb19ee1-d917-48df-96f2-31df56f56117
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153996104 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_d
igest.2153996104
Directory /workspace/42.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_mux.2325067625
Short name T546
Test name
Test status
Simulation time 1056699762 ps
CPU time 10.11 seconds
Started Jun 02 01:26:49 PM PDT 24
Finished Jun 02 01:27:00 PM PDT 24
Peak memory 218092 kb
Host smart-9a72fd86-03b4-441d-b987-71dc05e696d8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325067625 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_mux.
2325067625
Directory /workspace/42.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/42.lc_ctrl_security_escalation.530979853
Short name T257
Test name
Test status
Simulation time 1325964910 ps
CPU time 9.23 seconds
Started Jun 02 01:26:51 PM PDT 24
Finished Jun 02 01:27:01 PM PDT 24
Peak memory 218140 kb
Host smart-44355421-4a46-45ba-aebd-7d90ed218623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530979853 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_security_escalation.530979853
Directory /workspace/42.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/42.lc_ctrl_smoke.381929577
Short name T269
Test name
Test status
Simulation time 391157145 ps
CPU time 4.91 seconds
Started Jun 02 01:26:41 PM PDT 24
Finished Jun 02 01:26:47 PM PDT 24
Peak memory 217712 kb
Host smart-44544683-e25b-4dff-b9a3-d0346f5f83a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381929577 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_smoke.381929577
Directory /workspace/42.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_failure.3172504781
Short name T563
Test name
Test status
Simulation time 1116183056 ps
CPU time 35.3 seconds
Started Jun 02 01:26:41 PM PDT 24
Finished Jun 02 01:27:16 PM PDT 24
Peak memory 251084 kb
Host smart-cb82519f-b701-4b22-935a-22e670277edd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172504781 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_failure.3172504781
Directory /workspace/42.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_post_trans.4161617316
Short name T266
Test name
Test status
Simulation time 353962088 ps
CPU time 10.04 seconds
Started Jun 02 01:26:38 PM PDT 24
Finished Jun 02 01:26:48 PM PDT 24
Peak memory 250912 kb
Host smart-bcd72652-2b42-4647-b4b5-1fe39c02628d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161617316 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_post_trans.4161617316
Directory /workspace/42.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/42.lc_ctrl_stress_all.3327587831
Short name T794
Test name
Test status
Simulation time 17636819739 ps
CPU time 124.28 seconds
Started Jun 02 01:26:48 PM PDT 24
Finished Jun 02 01:28:53 PM PDT 24
Peak memory 269924 kb
Host smart-4b3abd12-dda0-4224-856e-fc1f5d2b61f5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327587831 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.lc_ctrl_stress_all.3327587831
Directory /workspace/42.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.lc_ctrl_volatile_unlock_smoke.2652672817
Short name T39
Test name
Test status
Simulation time 11114206 ps
CPU time 1.04 seconds
Started Jun 02 01:26:40 PM PDT 24
Finished Jun 02 01:26:42 PM PDT 24
Peak memory 211596 kb
Host smart-8c3664f3-4f9e-4cc0-be65-8fa98fbb80ea
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652672817 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_c
trl_volatile_unlock_smoke.2652672817
Directory /workspace/42.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_alert_test.1261520082
Short name T251
Test name
Test status
Simulation time 19822028 ps
CPU time 0.92 seconds
Started Jun 02 01:26:49 PM PDT 24
Finished Jun 02 01:26:51 PM PDT 24
Peak memory 208704 kb
Host smart-cb509686-5e4b-49fd-8b03-938414368119
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261520082 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_alert_test.1261520082
Directory /workspace/43.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.lc_ctrl_errors.362297942
Short name T375
Test name
Test status
Simulation time 1267493136 ps
CPU time 16.45 seconds
Started Jun 02 01:26:49 PM PDT 24
Finished Jun 02 01:27:06 PM PDT 24
Peak memory 217924 kb
Host smart-81e7e898-0acb-4f51-9b42-3806d30faa0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=362297942 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_errors.362297942
Directory /workspace/43.lc_ctrl_errors/latest

Test location /workspace/coverage/default/43.lc_ctrl_jtag_access.4168719224
Short name T353
Test name
Test status
Simulation time 255011458 ps
CPU time 4.06 seconds
Started Jun 02 01:26:49 PM PDT 24
Finished Jun 02 01:26:54 PM PDT 24
Peak memory 209584 kb
Host smart-0dca3a8c-fb5b-473d-a381-4257b98f569b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168719224 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_jtag_access.4168719224
Directory /workspace/43.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/43.lc_ctrl_prog_failure.3688087416
Short name T754
Test name
Test status
Simulation time 98743914 ps
CPU time 4.14 seconds
Started Jun 02 01:26:47 PM PDT 24
Finished Jun 02 01:26:52 PM PDT 24
Peak memory 218116 kb
Host smart-a2a3a691-c506-4cbd-b6a0-71f24f1e67f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688087416 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_prog_failure.3688087416
Directory /workspace/43.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_mubi.46107484
Short name T690
Test name
Test status
Simulation time 422795700 ps
CPU time 14.48 seconds
Started Jun 02 01:26:49 PM PDT 24
Finished Jun 02 01:27:05 PM PDT 24
Peak memory 225412 kb
Host smart-ed459ca9-84f5-44ad-9d7d-2918a52e3a43
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46107484 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_mubi.46107484
Directory /workspace/43.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_digest.2294970555
Short name T755
Test name
Test status
Simulation time 729261303 ps
CPU time 9.96 seconds
Started Jun 02 01:26:48 PM PDT 24
Finished Jun 02 01:26:58 PM PDT 24
Peak memory 226052 kb
Host smart-d43d29d6-29b0-493c-af8a-57a95653f33e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294970555 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_d
igest.2294970555
Directory /workspace/43.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_mux.174014916
Short name T96
Test name
Test status
Simulation time 3022922104 ps
CPU time 9.8 seconds
Started Jun 02 01:26:49 PM PDT 24
Finished Jun 02 01:27:00 PM PDT 24
Peak memory 217492 kb
Host smart-29b11797-13bf-4817-af6f-1aa7297efca8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174014916 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_mux.174014916
Directory /workspace/43.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/43.lc_ctrl_security_escalation.3464929475
Short name T451
Test name
Test status
Simulation time 5284743824 ps
CPU time 11.74 seconds
Started Jun 02 01:26:51 PM PDT 24
Finished Jun 02 01:27:03 PM PDT 24
Peak memory 218132 kb
Host smart-f0affeb8-a3e0-414c-9b12-d9eb118c4b6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464929475 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_security_escalation.3464929475
Directory /workspace/43.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/43.lc_ctrl_smoke.3834180013
Short name T709
Test name
Test status
Simulation time 72465770 ps
CPU time 2.53 seconds
Started Jun 02 01:26:49 PM PDT 24
Finished Jun 02 01:26:52 PM PDT 24
Peak memory 214088 kb
Host smart-a08781cc-07e3-41fc-93b0-2cfc85009085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834180013 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_smoke.3834180013
Directory /workspace/43.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_failure.2547423937
Short name T809
Test name
Test status
Simulation time 199381758 ps
CPU time 18.07 seconds
Started Jun 02 01:26:48 PM PDT 24
Finished Jun 02 01:27:06 PM PDT 24
Peak memory 245736 kb
Host smart-4e8615e6-d56e-4948-ab1f-dbd417f91997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547423937 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_failure.2547423937
Directory /workspace/43.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_post_trans.1927676546
Short name T391
Test name
Test status
Simulation time 97156848 ps
CPU time 6.71 seconds
Started Jun 02 01:26:46 PM PDT 24
Finished Jun 02 01:26:53 PM PDT 24
Peak memory 246788 kb
Host smart-d7b2fad6-22f8-4132-86ec-c2437ce87b3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927676546 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_post_trans.1927676546
Directory /workspace/43.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all.1788652134
Short name T440
Test name
Test status
Simulation time 13498956273 ps
CPU time 114.21 seconds
Started Jun 02 01:26:48 PM PDT 24
Finished Jun 02 01:28:43 PM PDT 24
Peak memory 275996 kb
Host smart-0d695de3-88d4-48f0-9992-8fc2a0e9c773
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788652134 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.lc_ctrl_stress_all.1788652134
Directory /workspace/43.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.lc_ctrl_volatile_unlock_smoke.1566396733
Short name T833
Test name
Test status
Simulation time 12324702 ps
CPU time 1.11 seconds
Started Jun 02 01:26:48 PM PDT 24
Finished Jun 02 01:26:50 PM PDT 24
Peak memory 211576 kb
Host smart-aa9f38c7-c73b-4c4f-8446-4496ec7c1392
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566396733 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_c
trl_volatile_unlock_smoke.1566396733
Directory /workspace/43.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_alert_test.2977377682
Short name T521
Test name
Test status
Simulation time 26048386 ps
CPU time 1.13 seconds
Started Jun 02 01:26:56 PM PDT 24
Finished Jun 02 01:26:57 PM PDT 24
Peak memory 208696 kb
Host smart-bab601dd-73b4-45d0-a8cf-ad6c746548d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977377682 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_alert_test.2977377682
Directory /workspace/44.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.lc_ctrl_errors.2959747092
Short name T206
Test name
Test status
Simulation time 467928901 ps
CPU time 14.65 seconds
Started Jun 02 01:26:55 PM PDT 24
Finished Jun 02 01:27:10 PM PDT 24
Peak memory 218052 kb
Host smart-00e70518-ee7b-4820-b4e0-e02c18067245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959747092 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_errors.2959747092
Directory /workspace/44.lc_ctrl_errors/latest

Test location /workspace/coverage/default/44.lc_ctrl_jtag_access.999361888
Short name T435
Test name
Test status
Simulation time 4117276205 ps
CPU time 9.2 seconds
Started Jun 02 01:26:54 PM PDT 24
Finished Jun 02 01:27:04 PM PDT 24
Peak memory 217536 kb
Host smart-f9bcf297-e999-4421-b063-c6f4370e23a0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999361888 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_jtag_access.999361888
Directory /workspace/44.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/44.lc_ctrl_prog_failure.2052994692
Short name T207
Test name
Test status
Simulation time 102923601 ps
CPU time 3.97 seconds
Started Jun 02 01:26:59 PM PDT 24
Finished Jun 02 01:27:03 PM PDT 24
Peak memory 217992 kb
Host smart-37a36639-2adf-45e9-9d24-1848c10f1823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052994692 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_prog_failure.2052994692
Directory /workspace/44.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_digest.4097140508
Short name T352
Test name
Test status
Simulation time 359468024 ps
CPU time 15.37 seconds
Started Jun 02 01:26:56 PM PDT 24
Finished Jun 02 01:27:12 PM PDT 24
Peak memory 217952 kb
Host smart-4ed98446-4718-42fe-860d-0ebc61297ccc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097140508 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_d
igest.4097140508
Directory /workspace/44.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_mux.4028277893
Short name T681
Test name
Test status
Simulation time 355597008 ps
CPU time 6.25 seconds
Started Jun 02 01:26:55 PM PDT 24
Finished Jun 02 01:27:02 PM PDT 24
Peak memory 218028 kb
Host smart-5ff53617-3413-497c-9338-33a5338aef83
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028277893 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_mux.
4028277893
Directory /workspace/44.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/44.lc_ctrl_security_escalation.3775682252
Short name T279
Test name
Test status
Simulation time 1144943940 ps
CPU time 8.61 seconds
Started Jun 02 01:26:55 PM PDT 24
Finished Jun 02 01:27:04 PM PDT 24
Peak memory 218076 kb
Host smart-fe8d0aee-4f2a-4a3f-a392-d0164edd9022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775682252 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_security_escalation.3775682252
Directory /workspace/44.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/44.lc_ctrl_smoke.368729195
Short name T767
Test name
Test status
Simulation time 147913210 ps
CPU time 2.48 seconds
Started Jun 02 01:26:48 PM PDT 24
Finished Jun 02 01:26:51 PM PDT 24
Peak memory 217740 kb
Host smart-6e186746-36de-4b14-b47c-cc23a52198f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368729195 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_smoke.368729195
Directory /workspace/44.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_failure.2561495746
Short name T368
Test name
Test status
Simulation time 582982548 ps
CPU time 35.15 seconds
Started Jun 02 01:26:48 PM PDT 24
Finished Jun 02 01:27:24 PM PDT 24
Peak memory 250968 kb
Host smart-074bda3f-80df-46fe-872d-75164471c147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561495746 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_failure.2561495746
Directory /workspace/44.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_post_trans.2214113698
Short name T351
Test name
Test status
Simulation time 219412887 ps
CPU time 6.73 seconds
Started Jun 02 01:26:56 PM PDT 24
Finished Jun 02 01:27:03 PM PDT 24
Peak memory 247004 kb
Host smart-6ab1a2f9-3800-4b7f-9d5b-86259fabffea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214113698 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_post_trans.2214113698
Directory /workspace/44.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/44.lc_ctrl_stress_all.4076279950
Short name T723
Test name
Test status
Simulation time 25268200589 ps
CPU time 195.98 seconds
Started Jun 02 01:26:56 PM PDT 24
Finished Jun 02 01:30:13 PM PDT 24
Peak memory 275636 kb
Host smart-b288255a-49d1-43b9-8f81-37b5bef41b46
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076279950 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.lc_ctrl_stress_all.4076279950
Directory /workspace/44.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.lc_ctrl_stress_all_with_rand_reset.2442313697
Short name T381
Test name
Test status
Simulation time 21265528635 ps
CPU time 388.03 seconds
Started Jun 02 01:26:56 PM PDT 24
Finished Jun 02 01:33:25 PM PDT 24
Peak memory 273988 kb
Host smart-e8f2505d-7ec7-4113-9949-0fa093f07d39
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2442313697 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_stress_all_with_rand_reset.2442313697
Directory /workspace/44.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.lc_ctrl_volatile_unlock_smoke.3148268055
Short name T541
Test name
Test status
Simulation time 22978119 ps
CPU time 0.89 seconds
Started Jun 02 01:26:47 PM PDT 24
Finished Jun 02 01:26:48 PM PDT 24
Peak memory 211528 kb
Host smart-aaca73f0-0379-463e-ac21-ae5bc037201d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148268055 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_c
trl_volatile_unlock_smoke.3148268055
Directory /workspace/44.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_alert_test.177040565
Short name T307
Test name
Test status
Simulation time 169098568 ps
CPU time 0.96 seconds
Started Jun 02 01:26:55 PM PDT 24
Finished Jun 02 01:26:56 PM PDT 24
Peak memory 208692 kb
Host smart-48cd691e-6742-48c4-8a30-c92d7e9dd80e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177040565 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_alert_test.177040565
Directory /workspace/45.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.lc_ctrl_errors.2160672821
Short name T500
Test name
Test status
Simulation time 2596890535 ps
CPU time 22.39 seconds
Started Jun 02 01:26:56 PM PDT 24
Finished Jun 02 01:27:18 PM PDT 24
Peak memory 218012 kb
Host smart-cd60f6c7-7ae9-4eef-aa73-e2b2275046d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160672821 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_errors.2160672821
Directory /workspace/45.lc_ctrl_errors/latest

Test location /workspace/coverage/default/45.lc_ctrl_jtag_access.923357068
Short name T827
Test name
Test status
Simulation time 171569210 ps
CPU time 5.06 seconds
Started Jun 02 01:26:59 PM PDT 24
Finished Jun 02 01:27:05 PM PDT 24
Peak memory 209464 kb
Host smart-6c9aa2ba-5e31-4cbe-a9fa-c6ab67e76545
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923357068 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_jtag_access.923357068
Directory /workspace/45.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/45.lc_ctrl_prog_failure.2303495544
Short name T540
Test name
Test status
Simulation time 251280773 ps
CPU time 3.61 seconds
Started Jun 02 01:26:57 PM PDT 24
Finished Jun 02 01:27:01 PM PDT 24
Peak memory 218048 kb
Host smart-f2c518b2-4818-4bd3-8dd2-5b4c831d1e1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303495544 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_prog_failure.2303495544
Directory /workspace/45.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_mubi.1909762863
Short name T605
Test name
Test status
Simulation time 3245101390 ps
CPU time 13.9 seconds
Started Jun 02 01:26:55 PM PDT 24
Finished Jun 02 01:27:09 PM PDT 24
Peak memory 226044 kb
Host smart-1ef4d61f-6739-40aa-9789-10e65f935731
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909762863 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_mubi.1909762863
Directory /workspace/45.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_digest.1237882978
Short name T45
Test name
Test status
Simulation time 880830424 ps
CPU time 15.62 seconds
Started Jun 02 01:26:55 PM PDT 24
Finished Jun 02 01:27:11 PM PDT 24
Peak memory 218060 kb
Host smart-03555d5e-0f14-4a45-b34a-5acfcac629cf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237882978 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_d
igest.1237882978
Directory /workspace/45.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_mux.712155707
Short name T670
Test name
Test status
Simulation time 1497265795 ps
CPU time 6.53 seconds
Started Jun 02 01:26:59 PM PDT 24
Finished Jun 02 01:27:06 PM PDT 24
Peak memory 217952 kb
Host smart-4b0ecaf3-fe4d-44db-a86c-5cc723eaba27
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712155707 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_mux.712155707
Directory /workspace/45.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/45.lc_ctrl_security_escalation.302924453
Short name T842
Test name
Test status
Simulation time 820285541 ps
CPU time 6.11 seconds
Started Jun 02 01:26:54 PM PDT 24
Finished Jun 02 01:27:01 PM PDT 24
Peak memory 218128 kb
Host smart-8435de58-c870-41ac-9ddb-bbfcb8ca74ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302924453 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_security_escalation.302924453
Directory /workspace/45.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/45.lc_ctrl_smoke.3323783857
Short name T415
Test name
Test status
Simulation time 16238759 ps
CPU time 1.03 seconds
Started Jun 02 01:26:57 PM PDT 24
Finished Jun 02 01:26:58 PM PDT 24
Peak memory 211980 kb
Host smart-4d50e85a-ad6c-4c94-82b6-90ec05c6286a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323783857 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_smoke.3323783857
Directory /workspace/45.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_failure.444936007
Short name T408
Test name
Test status
Simulation time 273751886 ps
CPU time 28.82 seconds
Started Jun 02 01:26:56 PM PDT 24
Finished Jun 02 01:27:25 PM PDT 24
Peak memory 251004 kb
Host smart-213cd8be-c0d7-4fed-8b6d-7963d1ca3141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444936007 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_failure.444936007
Directory /workspace/45.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_post_trans.1559880521
Short name T584
Test name
Test status
Simulation time 133761532 ps
CPU time 9.49 seconds
Started Jun 02 01:26:55 PM PDT 24
Finished Jun 02 01:27:05 PM PDT 24
Peak memory 250916 kb
Host smart-8350b264-5d91-4962-88fd-47a066eaed2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559880521 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_post_trans.1559880521
Directory /workspace/45.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/45.lc_ctrl_stress_all.2532116533
Short name T509
Test name
Test status
Simulation time 1773860603 ps
CPU time 58.95 seconds
Started Jun 02 01:26:55 PM PDT 24
Finished Jun 02 01:27:55 PM PDT 24
Peak memory 268156 kb
Host smart-5840baa7-d272-4fda-8ca0-71432e0f5356
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532116533 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.lc_ctrl_stress_all.2532116533
Directory /workspace/45.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.lc_ctrl_volatile_unlock_smoke.1928380100
Short name T68
Test name
Test status
Simulation time 15770172 ps
CPU time 1.22 seconds
Started Jun 02 01:26:53 PM PDT 24
Finished Jun 02 01:26:54 PM PDT 24
Peak memory 212684 kb
Host smart-b1592b5c-b719-4eb6-bb0c-499a3274c6bf
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928380100 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_c
trl_volatile_unlock_smoke.1928380100
Directory /workspace/45.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_alert_test.1214676505
Short name T90
Test name
Test status
Simulation time 18909091 ps
CPU time 1.15 seconds
Started Jun 02 01:27:01 PM PDT 24
Finished Jun 02 01:27:03 PM PDT 24
Peak memory 208720 kb
Host smart-a01072ac-d4c3-4a89-a8fd-6e02a265dfaf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214676505 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_alert_test.1214676505
Directory /workspace/46.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.lc_ctrl_errors.2846510424
Short name T374
Test name
Test status
Simulation time 1375629389 ps
CPU time 11.43 seconds
Started Jun 02 01:26:56 PM PDT 24
Finished Jun 02 01:27:07 PM PDT 24
Peak memory 217968 kb
Host smart-8c942512-058f-4be9-b594-7fedd66d78ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846510424 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_errors.2846510424
Directory /workspace/46.lc_ctrl_errors/latest

Test location /workspace/coverage/default/46.lc_ctrl_jtag_access.3653328235
Short name T662
Test name
Test status
Simulation time 1005232819 ps
CPU time 6.74 seconds
Started Jun 02 01:26:59 PM PDT 24
Finished Jun 02 01:27:06 PM PDT 24
Peak memory 209552 kb
Host smart-a24762e1-e998-41e8-8e30-37442a2a5860
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653328235 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_jtag_access.3653328235
Directory /workspace/46.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/46.lc_ctrl_prog_failure.1766346501
Short name T526
Test name
Test status
Simulation time 175340691 ps
CPU time 2.62 seconds
Started Jun 02 01:26:59 PM PDT 24
Finished Jun 02 01:27:02 PM PDT 24
Peak memory 218060 kb
Host smart-86667dbc-2853-485c-a4a0-2a1f2968388b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766346501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_prog_failure.1766346501
Directory /workspace/46.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_mubi.3055165081
Short name T283
Test name
Test status
Simulation time 1747700393 ps
CPU time 12.43 seconds
Started Jun 02 01:26:54 PM PDT 24
Finished Jun 02 01:27:07 PM PDT 24
Peak memory 218884 kb
Host smart-5b295aa6-bbab-4f27-98fb-85ef2b5b7338
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055165081 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_mubi.3055165081
Directory /workspace/46.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_digest.4262871195
Short name T184
Test name
Test status
Simulation time 927147834 ps
CPU time 10.63 seconds
Started Jun 02 01:26:59 PM PDT 24
Finished Jun 02 01:27:10 PM PDT 24
Peak memory 224936 kb
Host smart-f4a2ec81-e403-46a2-8e04-ca5d0bff975e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262871195 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_d
igest.4262871195
Directory /workspace/46.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_mux.2272672054
Short name T700
Test name
Test status
Simulation time 299567193 ps
CPU time 11.34 seconds
Started Jun 02 01:26:55 PM PDT 24
Finished Jun 02 01:27:07 PM PDT 24
Peak memory 218016 kb
Host smart-2d536b88-7d53-4672-b82b-a92cc13ee3a1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272672054 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_mux.
2272672054
Directory /workspace/46.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/46.lc_ctrl_security_escalation.1193221461
Short name T401
Test name
Test status
Simulation time 711976097 ps
CPU time 12.46 seconds
Started Jun 02 01:26:56 PM PDT 24
Finished Jun 02 01:27:09 PM PDT 24
Peak memory 218148 kb
Host smart-644b6b6f-ff54-4711-943b-90d8902d856f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193221461 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_security_escalation.1193221461
Directory /workspace/46.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/46.lc_ctrl_smoke.91364214
Short name T202
Test name
Test status
Simulation time 38112768 ps
CPU time 1.11 seconds
Started Jun 02 01:26:56 PM PDT 24
Finished Jun 02 01:26:57 PM PDT 24
Peak memory 217664 kb
Host smart-ba6771d0-38d1-4048-8f79-0879e7a5b4d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91364214 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_smoke.91364214
Directory /workspace/46.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_failure.2229745195
Short name T296
Test name
Test status
Simulation time 779005033 ps
CPU time 21.74 seconds
Started Jun 02 01:26:56 PM PDT 24
Finished Jun 02 01:27:18 PM PDT 24
Peak memory 250976 kb
Host smart-f69ee421-6d40-46b9-ac29-83d520cbe058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229745195 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_failure.2229745195
Directory /workspace/46.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_post_trans.3850439920
Short name T639
Test name
Test status
Simulation time 815600629 ps
CPU time 6.77 seconds
Started Jun 02 01:26:57 PM PDT 24
Finished Jun 02 01:27:04 PM PDT 24
Peak memory 250636 kb
Host smart-b86f2bc9-ad34-470f-8d4b-4327c0a048b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850439920 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_post_trans.3850439920
Directory /workspace/46.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all.2732754481
Short name T623
Test name
Test status
Simulation time 4515019569 ps
CPU time 81.27 seconds
Started Jun 02 01:27:04 PM PDT 24
Finished Jun 02 01:28:25 PM PDT 24
Peak memory 251060 kb
Host smart-c63ea138-447f-4bee-a8ee-41d28c469cf3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732754481 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.lc_ctrl_stress_all.2732754481
Directory /workspace/46.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.lc_ctrl_volatile_unlock_smoke.3601395533
Short name T649
Test name
Test status
Simulation time 24762218 ps
CPU time 0.94 seconds
Started Jun 02 01:26:54 PM PDT 24
Finished Jun 02 01:26:56 PM PDT 24
Peak memory 211452 kb
Host smart-6bfe5768-2b85-4529-957c-b34db3a2a762
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601395533 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_c
trl_volatile_unlock_smoke.3601395533
Directory /workspace/46.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_alert_test.2251778437
Short name T428
Test name
Test status
Simulation time 84939853 ps
CPU time 1.14 seconds
Started Jun 02 01:27:03 PM PDT 24
Finished Jun 02 01:27:04 PM PDT 24
Peak memory 208648 kb
Host smart-dc622e5a-d36f-45e1-a755-aa71e0780407
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251778437 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_alert_test.2251778437
Directory /workspace/47.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.lc_ctrl_errors.26104172
Short name T271
Test name
Test status
Simulation time 556565740 ps
CPU time 14.21 seconds
Started Jun 02 01:27:00 PM PDT 24
Finished Jun 02 01:27:15 PM PDT 24
Peak memory 218068 kb
Host smart-1621488f-01a5-4a3d-9a12-a746ed762ed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26104172 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_errors.26104172
Directory /workspace/47.lc_ctrl_errors/latest

Test location /workspace/coverage/default/47.lc_ctrl_jtag_access.3699624019
Short name T425
Test name
Test status
Simulation time 177574091 ps
CPU time 3.21 seconds
Started Jun 02 01:27:04 PM PDT 24
Finished Jun 02 01:27:07 PM PDT 24
Peak memory 209628 kb
Host smart-4fe04bc9-acec-4cf9-8546-91d18e3f8873
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699624019 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_jtag_access.3699624019
Directory /workspace/47.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/47.lc_ctrl_prog_failure.3946176193
Short name T345
Test name
Test status
Simulation time 367410378 ps
CPU time 3.56 seconds
Started Jun 02 01:27:00 PM PDT 24
Finished Jun 02 01:27:04 PM PDT 24
Peak memory 218028 kb
Host smart-47e5510b-8fb1-4093-a4a4-f9c087dbfd05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946176193 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_prog_failure.3946176193
Directory /workspace/47.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_mubi.2491530905
Short name T608
Test name
Test status
Simulation time 1313608430 ps
CPU time 10.82 seconds
Started Jun 02 01:27:02 PM PDT 24
Finished Jun 02 01:27:13 PM PDT 24
Peak memory 218952 kb
Host smart-ccfcd8b3-613b-4fae-8513-af5910fa2728
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491530905 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_mubi.2491530905
Directory /workspace/47.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_digest.4050762322
Short name T488
Test name
Test status
Simulation time 3542985430 ps
CPU time 11.98 seconds
Started Jun 02 01:27:03 PM PDT 24
Finished Jun 02 01:27:15 PM PDT 24
Peak memory 218020 kb
Host smart-7c988a6c-db90-4481-ab2f-b10cd471b969
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050762322 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_d
igest.4050762322
Directory /workspace/47.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_mux.3626464539
Short name T385
Test name
Test status
Simulation time 324412774 ps
CPU time 13.26 seconds
Started Jun 02 01:27:01 PM PDT 24
Finished Jun 02 01:27:14 PM PDT 24
Peak memory 218020 kb
Host smart-aeb3fd7b-ae8a-437f-9780-040b6725f5f4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626464539 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_mux.
3626464539
Directory /workspace/47.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/47.lc_ctrl_security_escalation.3566759833
Short name T466
Test name
Test status
Simulation time 516284068 ps
CPU time 10 seconds
Started Jun 02 01:27:02 PM PDT 24
Finished Jun 02 01:27:12 PM PDT 24
Peak memory 224732 kb
Host smart-5efd3f3e-cd26-49e3-b32d-3ed0200a4176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566759833 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_security_escalation.3566759833
Directory /workspace/47.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/47.lc_ctrl_smoke.2184788949
Short name T783
Test name
Test status
Simulation time 52943789 ps
CPU time 3.64 seconds
Started Jun 02 01:27:00 PM PDT 24
Finished Jun 02 01:27:04 PM PDT 24
Peak memory 213836 kb
Host smart-b5e6d741-4603-42eb-8b1b-b91e79fa08c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184788949 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_smoke.2184788949
Directory /workspace/47.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_failure.1442115414
Short name T322
Test name
Test status
Simulation time 458735952 ps
CPU time 36.51 seconds
Started Jun 02 01:27:02 PM PDT 24
Finished Jun 02 01:27:39 PM PDT 24
Peak memory 250996 kb
Host smart-43462a77-ee0d-440f-ba47-5e8685fa9288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442115414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_failure.1442115414
Directory /workspace/47.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_post_trans.493849261
Short name T716
Test name
Test status
Simulation time 277395179 ps
CPU time 3.99 seconds
Started Jun 02 01:27:03 PM PDT 24
Finished Jun 02 01:27:07 PM PDT 24
Peak memory 222664 kb
Host smart-90e10ea0-1a03-46e2-b670-787a0f1edf1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493849261 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_post_trans.493849261
Directory /workspace/47.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/47.lc_ctrl_stress_all.2498398559
Short name T407
Test name
Test status
Simulation time 26392608417 ps
CPU time 40.87 seconds
Started Jun 02 01:27:02 PM PDT 24
Finished Jun 02 01:27:43 PM PDT 24
Peak memory 251044 kb
Host smart-18c91aae-8c19-49c3-aa33-dc30022cea0b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498398559 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.lc_ctrl_stress_all.2498398559
Directory /workspace/47.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.lc_ctrl_volatile_unlock_smoke.1098223685
Short name T637
Test name
Test status
Simulation time 16084467 ps
CPU time 1.06 seconds
Started Jun 02 01:27:03 PM PDT 24
Finished Jun 02 01:27:05 PM PDT 24
Peak memory 212816 kb
Host smart-86ad0ed4-27b3-400d-975f-47ec47ba1d6e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098223685 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_c
trl_volatile_unlock_smoke.1098223685
Directory /workspace/47.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_alert_test.1553267081
Short name T228
Test name
Test status
Simulation time 20394659 ps
CPU time 1.22 seconds
Started Jun 02 01:27:08 PM PDT 24
Finished Jun 02 01:27:09 PM PDT 24
Peak memory 209828 kb
Host smart-b8011ad6-5639-4328-bdf1-fbb156552b0b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553267081 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_alert_test.1553267081
Directory /workspace/48.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.lc_ctrl_errors.920773223
Short name T485
Test name
Test status
Simulation time 898435692 ps
CPU time 12.77 seconds
Started Jun 02 01:27:01 PM PDT 24
Finished Jun 02 01:27:14 PM PDT 24
Peak memory 217988 kb
Host smart-60dc34aa-6211-43d4-b53a-18a875295c33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920773223 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_errors.920773223
Directory /workspace/48.lc_ctrl_errors/latest

Test location /workspace/coverage/default/48.lc_ctrl_jtag_access.344463827
Short name T513
Test name
Test status
Simulation time 52618475 ps
CPU time 2.16 seconds
Started Jun 02 01:27:01 PM PDT 24
Finished Jun 02 01:27:03 PM PDT 24
Peak memory 209572 kb
Host smart-e7d03d1c-6225-4915-a13b-f685882e1a98
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344463827 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_jtag_access.344463827
Directory /workspace/48.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/48.lc_ctrl_prog_failure.2789398262
Short name T448
Test name
Test status
Simulation time 1842361941 ps
CPU time 4.49 seconds
Started Jun 02 01:27:02 PM PDT 24
Finished Jun 02 01:27:07 PM PDT 24
Peak memory 218032 kb
Host smart-3433c1b6-06a0-4089-bff0-6d978a51a232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789398262 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_prog_failure.2789398262
Directory /workspace/48.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_mubi.4132758944
Short name T528
Test name
Test status
Simulation time 1317051640 ps
CPU time 13.78 seconds
Started Jun 02 01:27:02 PM PDT 24
Finished Jun 02 01:27:16 PM PDT 24
Peak memory 225788 kb
Host smart-2fd92f47-b590-418e-898c-e899c1c652bd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132758944 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_mubi.4132758944
Directory /workspace/48.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_digest.1274186193
Short name T741
Test name
Test status
Simulation time 991126722 ps
CPU time 11.14 seconds
Started Jun 02 01:27:12 PM PDT 24
Finished Jun 02 01:27:24 PM PDT 24
Peak memory 217968 kb
Host smart-ce3c6f96-15cf-4c0a-a11e-1db9addbdacf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274186193 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_d
igest.1274186193
Directory /workspace/48.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_mux.3292443880
Short name T533
Test name
Test status
Simulation time 255115950 ps
CPU time 10.57 seconds
Started Jun 02 01:27:04 PM PDT 24
Finished Jun 02 01:27:15 PM PDT 24
Peak memory 218008 kb
Host smart-790338c3-8592-4e94-80fc-37d6dccf84d3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292443880 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_mux.
3292443880
Directory /workspace/48.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/48.lc_ctrl_security_escalation.397658080
Short name T668
Test name
Test status
Simulation time 957382921 ps
CPU time 7.97 seconds
Started Jun 02 01:27:02 PM PDT 24
Finished Jun 02 01:27:11 PM PDT 24
Peak memory 218032 kb
Host smart-c60b19ae-01a9-4503-ac49-d09205ae5c32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397658080 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_security_escalation.397658080
Directory /workspace/48.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/48.lc_ctrl_smoke.2195821206
Short name T4
Test name
Test status
Simulation time 346255137 ps
CPU time 4.22 seconds
Started Jun 02 01:27:03 PM PDT 24
Finished Jun 02 01:27:07 PM PDT 24
Peak memory 217788 kb
Host smart-f8f4b2a4-a5d6-4dff-b13a-753c71963498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195821206 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_smoke.2195821206
Directory /workspace/48.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_failure.4233955420
Short name T781
Test name
Test status
Simulation time 288327905 ps
CPU time 26.27 seconds
Started Jun 02 01:27:03 PM PDT 24
Finished Jun 02 01:27:30 PM PDT 24
Peak memory 250992 kb
Host smart-bc91c401-1028-4494-b1c6-830e5e2a8e92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233955420 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_failure.4233955420
Directory /workspace/48.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_post_trans.3393724540
Short name T33
Test name
Test status
Simulation time 846588972 ps
CPU time 8.52 seconds
Started Jun 02 01:27:02 PM PDT 24
Finished Jun 02 01:27:11 PM PDT 24
Peak memory 247352 kb
Host smart-0290042d-8c12-4f5f-b992-3804136dd335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393724540 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_post_trans.3393724540
Directory /workspace/48.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all.2042858960
Short name T101
Test name
Test status
Simulation time 37887400319 ps
CPU time 617.02 seconds
Started Jun 02 01:27:10 PM PDT 24
Finished Jun 02 01:37:27 PM PDT 24
Peak memory 277016 kb
Host smart-dff031b1-52a1-49b9-bbdb-2f058ff50ea1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042858960 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.lc_ctrl_stress_all.2042858960
Directory /workspace/48.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.lc_ctrl_volatile_unlock_smoke.3574088166
Short name T195
Test name
Test status
Simulation time 13610698 ps
CPU time 0.75 seconds
Started Jun 02 01:27:01 PM PDT 24
Finished Jun 02 01:27:02 PM PDT 24
Peak memory 207832 kb
Host smart-b73b6624-8385-45b4-83bb-b190b48d1a18
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574088166 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_c
trl_volatile_unlock_smoke.3574088166
Directory /workspace/48.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_alert_test.2139468944
Short name T631
Test name
Test status
Simulation time 35224600 ps
CPU time 0.81 seconds
Started Jun 02 01:27:08 PM PDT 24
Finished Jun 02 01:27:10 PM PDT 24
Peak memory 208524 kb
Host smart-01037925-b664-4775-b070-2ed46de88702
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139468944 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_alert_test.2139468944
Directory /workspace/49.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.lc_ctrl_errors.1985860396
Short name T50
Test name
Test status
Simulation time 282809437 ps
CPU time 9.23 seconds
Started Jun 02 01:27:13 PM PDT 24
Finished Jun 02 01:27:23 PM PDT 24
Peak memory 217992 kb
Host smart-3031872f-52d8-4235-bac1-cb78d6e3c968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985860396 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_errors.1985860396
Directory /workspace/49.lc_ctrl_errors/latest

Test location /workspace/coverage/default/49.lc_ctrl_jtag_access.215094895
Short name T24
Test name
Test status
Simulation time 2681163843 ps
CPU time 7.79 seconds
Started Jun 02 01:27:10 PM PDT 24
Finished Jun 02 01:27:18 PM PDT 24
Peak memory 209644 kb
Host smart-3fe0627f-3f63-4b52-8cd3-a149687ffde8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215094895 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_jtag_access.215094895
Directory /workspace/49.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/49.lc_ctrl_prog_failure.425444679
Short name T552
Test name
Test status
Simulation time 88913437 ps
CPU time 1.81 seconds
Started Jun 02 01:27:06 PM PDT 24
Finished Jun 02 01:27:09 PM PDT 24
Peak memory 218016 kb
Host smart-9ace221a-4846-4e59-a568-47720b590610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425444679 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_prog_failure.425444679
Directory /workspace/49.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_mubi.122633368
Short name T739
Test name
Test status
Simulation time 848352164 ps
CPU time 11.57 seconds
Started Jun 02 01:27:09 PM PDT 24
Finished Jun 02 01:27:21 PM PDT 24
Peak memory 226096 kb
Host smart-2ffb7026-e75c-4fb2-b8f2-f28dffaa4887
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122633368 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_mubi.122633368
Directory /workspace/49.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_digest.3074610488
Short name T239
Test name
Test status
Simulation time 8617847277 ps
CPU time 12.71 seconds
Started Jun 02 01:27:09 PM PDT 24
Finished Jun 02 01:27:22 PM PDT 24
Peak memory 226116 kb
Host smart-77eea474-5504-415a-9fa0-a4cdd053103b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074610488 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_d
igest.3074610488
Directory /workspace/49.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_mux.4060301023
Short name T791
Test name
Test status
Simulation time 1238104734 ps
CPU time 6.99 seconds
Started Jun 02 01:27:09 PM PDT 24
Finished Jun 02 01:27:16 PM PDT 24
Peak memory 218032 kb
Host smart-ff69ea9c-3b76-4205-98ce-ddb84ea5a3b7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060301023 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_mux.
4060301023
Directory /workspace/49.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/49.lc_ctrl_security_escalation.3209659499
Short name T506
Test name
Test status
Simulation time 691199426 ps
CPU time 10.12 seconds
Started Jun 02 01:27:09 PM PDT 24
Finished Jun 02 01:27:19 PM PDT 24
Peak memory 218100 kb
Host smart-a4f3ed4c-ff6f-4beb-b124-acfaea294d23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209659499 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_security_escalation.3209659499
Directory /workspace/49.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/49.lc_ctrl_smoke.1718524061
Short name T725
Test name
Test status
Simulation time 31816345 ps
CPU time 2.01 seconds
Started Jun 02 01:27:10 PM PDT 24
Finished Jun 02 01:27:13 PM PDT 24
Peak memory 217928 kb
Host smart-a5f87c7c-b971-4b00-a560-bb554b7079af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718524061 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_smoke.1718524061
Directory /workspace/49.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_failure.3547329111
Short name T98
Test name
Test status
Simulation time 269144725 ps
CPU time 20.92 seconds
Started Jun 02 01:27:10 PM PDT 24
Finished Jun 02 01:27:32 PM PDT 24
Peak memory 250996 kb
Host smart-4cadee17-49f5-48c4-b103-c45af23644c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547329111 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_failure.3547329111
Directory /workspace/49.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_post_trans.1365571211
Short name T213
Test name
Test status
Simulation time 78056741 ps
CPU time 3.25 seconds
Started Jun 02 01:27:10 PM PDT 24
Finished Jun 02 01:27:14 PM PDT 24
Peak memory 221836 kb
Host smart-4354f98f-2968-4bdf-80d2-6b2fc401d66e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365571211 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_post_trans.1365571211
Directory /workspace/49.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/49.lc_ctrl_stress_all.24524598
Short name T645
Test name
Test status
Simulation time 10424461375 ps
CPU time 60.16 seconds
Started Jun 02 01:27:10 PM PDT 24
Finished Jun 02 01:28:10 PM PDT 24
Peak memory 268124 kb
Host smart-51e913fc-4167-41f1-8661-f0c92a92cbbd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24524598 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_T
EST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
9.lc_ctrl_stress_all.24524598
Directory /workspace/49.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.lc_ctrl_volatile_unlock_smoke.1305831915
Short name T599
Test name
Test status
Simulation time 13397174 ps
CPU time 1.05 seconds
Started Jun 02 01:27:09 PM PDT 24
Finished Jun 02 01:27:10 PM PDT 24
Peak memory 211588 kb
Host smart-64075e74-dcae-497d-b249-cdeb9b85981f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305831915 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_c
trl_volatile_unlock_smoke.1305831915
Directory /workspace/49.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_alert_test.1567116208
Short name T281
Test name
Test status
Simulation time 32478353 ps
CPU time 0.94 seconds
Started Jun 02 01:24:26 PM PDT 24
Finished Jun 02 01:24:27 PM PDT 24
Peak memory 208616 kb
Host smart-1cfdbea1-e0ae-4f47-bf82-0e02a67cb959
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567116208 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_alert_test.1567116208
Directory /workspace/5.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.lc_ctrl_errors.78818399
Short name T688
Test name
Test status
Simulation time 1295469628 ps
CPU time 9.44 seconds
Started Jun 02 01:24:14 PM PDT 24
Finished Jun 02 01:24:24 PM PDT 24
Peak memory 217996 kb
Host smart-8cf93743-596b-43ff-a625-3669bc88d5de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78818399 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_errors.78818399
Directory /workspace/5.lc_ctrl_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_access.4113353439
Short name T650
Test name
Test status
Simulation time 846077149 ps
CPU time 19.71 seconds
Started Jun 02 01:24:14 PM PDT 24
Finished Jun 02 01:24:34 PM PDT 24
Peak memory 209536 kb
Host smart-d8983adc-56be-4c77-a935-3db6d7a3cf90
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113353439 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_access.4113353439
Directory /workspace/5.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_errors.2580256038
Short name T212
Test name
Test status
Simulation time 2916054900 ps
CPU time 25.4 seconds
Started Jun 02 01:24:15 PM PDT 24
Finished Jun 02 01:24:41 PM PDT 24
Peak memory 218108 kb
Host smart-880b8c45-ed2b-46b8-a8fe-a0f7d218c003
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580256038 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_er
rors.2580256038
Directory /workspace/5.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_priority.3947965776
Short name T444
Test name
Test status
Simulation time 2644712382 ps
CPU time 5.29 seconds
Started Jun 02 01:24:19 PM PDT 24
Finished Jun 02 01:24:24 PM PDT 24
Peak memory 217592 kb
Host smart-b640d50a-3e2a-4ca3-9206-c3e6c7b16870
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947965776 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_priority.3
947965776
Directory /workspace/5.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_prog_failure.577796425
Short name T364
Test name
Test status
Simulation time 882604190 ps
CPU time 14.95 seconds
Started Jun 02 01:24:15 PM PDT 24
Finished Jun 02 01:24:30 PM PDT 24
Peak memory 218008 kb
Host smart-3daf5cb6-8f47-46ca-a463-eaee80ebeb69
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577796425 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_
prog_failure.577796425
Directory /workspace/5.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_regwen_during_op.730458553
Short name T354
Test name
Test status
Simulation time 826760062 ps
CPU time 21.81 seconds
Started Jun 02 01:24:23 PM PDT 24
Finished Jun 02 01:24:46 PM PDT 24
Peak memory 217648 kb
Host smart-7ddfd283-eb7f-4e92-a6ad-ffaa93da8095
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730458553 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_j
tag_regwen_during_op.730458553
Directory /workspace/5.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_smoke.656344490
Short name T150
Test name
Test status
Simulation time 245608840 ps
CPU time 4.4 seconds
Started Jun 02 01:24:14 PM PDT 24
Finished Jun 02 01:24:18 PM PDT 24
Peak memory 217732 kb
Host smart-9b224978-30f4-4b8b-aa2d-756e0fe54c8f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656344490 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_smoke.656344490
Directory /workspace/5.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_failure.2998683622
Short name T594
Test name
Test status
Simulation time 1125900305 ps
CPU time 54.77 seconds
Started Jun 02 01:24:18 PM PDT 24
Finished Jun 02 01:25:14 PM PDT 24
Peak memory 275460 kb
Host smart-c494466e-f3a5-4231-bbbe-b10e8bfe1e5c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998683622 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jta
g_state_failure.2998683622
Directory /workspace/5.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_post_trans.4095026132
Short name T276
Test name
Test status
Simulation time 1639632088 ps
CPU time 16.36 seconds
Started Jun 02 01:24:18 PM PDT 24
Finished Jun 02 01:24:35 PM PDT 24
Peak memory 247704 kb
Host smart-a94a93ec-9a1a-4423-8016-2d6ebc659d47
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095026132 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_state_post_trans.4095026132
Directory /workspace/5.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_prog_failure.2457209858
Short name T147
Test name
Test status
Simulation time 807426003 ps
CPU time 3.09 seconds
Started Jun 02 01:24:18 PM PDT 24
Finished Jun 02 01:24:21 PM PDT 24
Peak memory 218032 kb
Host smart-5133d7df-9657-4fef-ad23-c8c2a68f26ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457209858 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_prog_failure.2457209858
Directory /workspace/5.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_regwen_during_op.3439664123
Short name T461
Test name
Test status
Simulation time 316975571 ps
CPU time 12.32 seconds
Started Jun 02 01:24:15 PM PDT 24
Finished Jun 02 01:24:28 PM PDT 24
Peak memory 217720 kb
Host smart-86fd2809-e2da-4a9a-81df-20d57e3fb0bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439664123 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_regwen_during_op.3439664123
Directory /workspace/5.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_mubi.3939491925
Short name T289
Test name
Test status
Simulation time 223935859 ps
CPU time 11.68 seconds
Started Jun 02 01:24:25 PM PDT 24
Finished Jun 02 01:24:37 PM PDT 24
Peak memory 226192 kb
Host smart-50ae0a63-6e46-45d1-87a3-150ab2edb17d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939491925 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_mubi.3939491925
Directory /workspace/5.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_digest.661423
Short name T452
Test name
Test status
Simulation time 1522470099 ps
CPU time 10.96 seconds
Started Jun 02 01:24:23 PM PDT 24
Finished Jun 02 01:24:35 PM PDT 24
Peak memory 218072 kb
Host smart-e9dff0f9-cfa7-4c5e-96e2-3e369c70baaa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661423 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_diges
t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_digest.661423
Directory /workspace/5.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_mux.596728074
Short name T556
Test name
Test status
Simulation time 483587083 ps
CPU time 12.26 seconds
Started Jun 02 01:24:22 PM PDT 24
Finished Jun 02 01:24:34 PM PDT 24
Peak memory 217944 kb
Host smart-3b1317a3-a71d-4351-a678-1d50e94b8ee4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596728074 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_mux.596728074
Directory /workspace/5.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/5.lc_ctrl_security_escalation.575358346
Short name T244
Test name
Test status
Simulation time 1533172938 ps
CPU time 9.51 seconds
Started Jun 02 01:24:20 PM PDT 24
Finished Jun 02 01:24:29 PM PDT 24
Peak memory 218028 kb
Host smart-da5fdfe9-643e-4af9-8ecc-06cf07c4aac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575358346 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_security_escalation.575358346
Directory /workspace/5.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/5.lc_ctrl_smoke.3061890218
Short name T569
Test name
Test status
Simulation time 323397281 ps
CPU time 5.11 seconds
Started Jun 02 01:24:11 PM PDT 24
Finished Jun 02 01:24:17 PM PDT 24
Peak memory 217716 kb
Host smart-25095e12-f133-447f-ac3b-17a4252393c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061890218 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_smoke.3061890218
Directory /workspace/5.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_failure.1688733083
Short name T464
Test name
Test status
Simulation time 325458874 ps
CPU time 34.89 seconds
Started Jun 02 01:24:07 PM PDT 24
Finished Jun 02 01:24:42 PM PDT 24
Peak memory 250968 kb
Host smart-b5e30926-f945-49ec-91d2-f218a1c12ecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688733083 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_failure.1688733083
Directory /workspace/5.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_post_trans.1183380103
Short name T620
Test name
Test status
Simulation time 313334691 ps
CPU time 7.76 seconds
Started Jun 02 01:24:07 PM PDT 24
Finished Jun 02 01:24:16 PM PDT 24
Peak memory 251008 kb
Host smart-716aacae-9695-4742-8930-3a9af89d1298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183380103 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_post_trans.1183380103
Directory /workspace/5.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_stress_all.1037285712
Short name T247
Test name
Test status
Simulation time 3154570699 ps
CPU time 26.7 seconds
Started Jun 02 01:24:24 PM PDT 24
Finished Jun 02 01:24:52 PM PDT 24
Peak memory 226164 kb
Host smart-3d9ab68f-7905-42fd-b510-535de9d7a924
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037285712 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.lc_ctrl_stress_all.1037285712
Directory /workspace/5.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.lc_ctrl_stress_all_with_rand_reset.3392375096
Short name T91
Test name
Test status
Simulation time 89737932450 ps
CPU time 696.86 seconds
Started Jun 02 01:24:23 PM PDT 24
Finished Jun 02 01:36:00 PM PDT 24
Peak memory 267072 kb
Host smart-726cde16-4c6e-49f2-b030-2a7ad0eab01a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3392375096 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_stress_all_with_rand_reset.3392375096
Directory /workspace/5.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.lc_ctrl_volatile_unlock_smoke.221645508
Short name T438
Test name
Test status
Simulation time 14017922 ps
CPU time 0.83 seconds
Started Jun 02 01:24:11 PM PDT 24
Finished Jun 02 01:24:13 PM PDT 24
Peak memory 208700 kb
Host smart-28efec98-f6d7-4084-b6cd-9eab364995cf
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221645508 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctr
l_volatile_unlock_smoke.221645508
Directory /workspace/5.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_alert_test.3368336554
Short name T515
Test name
Test status
Simulation time 14316552 ps
CPU time 0.8 seconds
Started Jun 02 01:24:26 PM PDT 24
Finished Jun 02 01:24:27 PM PDT 24
Peak memory 208500 kb
Host smart-bd1ec788-d69b-4cea-ad43-a38eb11854a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368336554 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_alert_test.3368336554
Directory /workspace/6.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.lc_ctrl_errors.2605300517
Short name T592
Test name
Test status
Simulation time 4057012872 ps
CPU time 18.45 seconds
Started Jun 02 01:24:25 PM PDT 24
Finished Jun 02 01:24:44 PM PDT 24
Peak memory 218392 kb
Host smart-457e1616-8b11-48ca-8881-4a33566957e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2605300517 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_errors.2605300517
Directory /workspace/6.lc_ctrl_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_access.3818214743
Short name T25
Test name
Test status
Simulation time 1229403222 ps
CPU time 6.16 seconds
Started Jun 02 01:24:23 PM PDT 24
Finished Jun 02 01:24:30 PM PDT 24
Peak memory 217040 kb
Host smart-532ada3e-470f-4ab3-9065-a796e4d0f2eb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818214743 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_access.3818214743
Directory /workspace/6.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_errors.4053759600
Short name T826
Test name
Test status
Simulation time 3293938340 ps
CPU time 48 seconds
Started Jun 02 01:24:25 PM PDT 24
Finished Jun 02 01:25:14 PM PDT 24
Peak memory 217684 kb
Host smart-ce370cba-c2c3-4f70-bf8c-7eacd9f0af7f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053759600 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_er
rors.4053759600
Directory /workspace/6.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_priority.4007301500
Short name T475
Test name
Test status
Simulation time 295416981 ps
CPU time 8.18 seconds
Started Jun 02 01:24:26 PM PDT 24
Finished Jun 02 01:24:34 PM PDT 24
Peak memory 217024 kb
Host smart-dfad94c1-4243-4c32-8428-6cba1b6997c6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007301500 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_priority.4
007301500
Directory /workspace/6.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_prog_failure.3584452830
Short name T535
Test name
Test status
Simulation time 387472256 ps
CPU time 6.26 seconds
Started Jun 02 01:24:24 PM PDT 24
Finished Jun 02 01:24:31 PM PDT 24
Peak memory 217920 kb
Host smart-4fe134e0-c985-48bd-b9f9-b4765a14544b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584452830 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag
_prog_failure.3584452830
Directory /workspace/6.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_regwen_during_op.551047892
Short name T718
Test name
Test status
Simulation time 1049803426 ps
CPU time 23.58 seconds
Started Jun 02 01:24:24 PM PDT 24
Finished Jun 02 01:24:48 PM PDT 24
Peak memory 217680 kb
Host smart-08b40fef-f27f-461e-9775-fc4c2f7ffd30
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551047892 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_j
tag_regwen_during_op.551047892
Directory /workspace/6.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_smoke.2594830671
Short name T797
Test name
Test status
Simulation time 253268083 ps
CPU time 2.83 seconds
Started Jun 02 01:24:24 PM PDT 24
Finished Jun 02 01:24:28 PM PDT 24
Peak memory 217632 kb
Host smart-d3ef9eb3-8a98-421f-a60e-db7e217ad6a2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594830671 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_smoke.
2594830671
Directory /workspace/6.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_failure.2110217797
Short name T458
Test name
Test status
Simulation time 2050176093 ps
CPU time 70.17 seconds
Started Jun 02 01:24:24 PM PDT 24
Finished Jun 02 01:25:35 PM PDT 24
Peak memory 275616 kb
Host smart-73d99380-1d1b-407c-b077-c849e484608f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110217797 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jta
g_state_failure.2110217797
Directory /workspace/6.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_post_trans.3247756657
Short name T596
Test name
Test status
Simulation time 2300812199 ps
CPU time 11.48 seconds
Started Jun 02 01:24:23 PM PDT 24
Finished Jun 02 01:24:34 PM PDT 24
Peak memory 223100 kb
Host smart-6c7950de-d68e-4480-8aa8-5f6ab3c8df25
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247756657 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_state_post_trans.3247756657
Directory /workspace/6.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_prog_failure.339028625
Short name T523
Test name
Test status
Simulation time 102957232 ps
CPU time 4.41 seconds
Started Jun 02 01:24:24 PM PDT 24
Finished Jun 02 01:24:28 PM PDT 24
Peak memory 218072 kb
Host smart-3d14986d-593a-4694-ba3e-477dd10f89b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339028625 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_prog_failure.339028625
Directory /workspace/6.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_regwen_during_op.2990851984
Short name T577
Test name
Test status
Simulation time 285597953 ps
CPU time 15.91 seconds
Started Jun 02 01:24:23 PM PDT 24
Finished Jun 02 01:24:40 PM PDT 24
Peak memory 214452 kb
Host smart-a991ea1a-9e57-472c-a67e-ede3806082ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990851984 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_regwen_during_op.2990851984
Directory /workspace/6.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_mubi.3799572292
Short name T191
Test name
Test status
Simulation time 379977914 ps
CPU time 10 seconds
Started Jun 02 01:24:25 PM PDT 24
Finished Jun 02 01:24:36 PM PDT 24
Peak memory 225720 kb
Host smart-63ef1154-de61-44bb-b056-1fb0d7588f3c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799572292 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_mubi.3799572292
Directory /workspace/6.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_digest.3899417755
Short name T860
Test name
Test status
Simulation time 2247977186 ps
CPU time 11.39 seconds
Started Jun 02 01:24:23 PM PDT 24
Finished Jun 02 01:24:35 PM PDT 24
Peak memory 225584 kb
Host smart-3cd3413b-11f8-42be-a419-c256411b91e5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899417755 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_di
gest.3899417755
Directory /workspace/6.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_mux.3683547897
Short name T291
Test name
Test status
Simulation time 830344952 ps
CPU time 8.25 seconds
Started Jun 02 01:24:24 PM PDT 24
Finished Jun 02 01:24:32 PM PDT 24
Peak memory 218044 kb
Host smart-8d8bafb3-4a69-49a3-8d78-f094bfb2dd37
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683547897 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_mux.3
683547897
Directory /workspace/6.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/6.lc_ctrl_security_escalation.2446071999
Short name T190
Test name
Test status
Simulation time 257176857 ps
CPU time 8.89 seconds
Started Jun 02 01:24:25 PM PDT 24
Finished Jun 02 01:24:34 PM PDT 24
Peak memory 218028 kb
Host smart-e3a7f75e-4474-456e-a8c2-36947f9904e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446071999 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_security_escalation.2446071999
Directory /workspace/6.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/6.lc_ctrl_smoke.3179428715
Short name T447
Test name
Test status
Simulation time 97307774 ps
CPU time 4.58 seconds
Started Jun 02 01:24:23 PM PDT 24
Finished Jun 02 01:24:28 PM PDT 24
Peak memory 217668 kb
Host smart-5f8736fc-bbe3-462b-875a-69b2ab297c52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179428715 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_smoke.3179428715
Directory /workspace/6.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_failure.2836674861
Short name T817
Test name
Test status
Simulation time 479259102 ps
CPU time 22.36 seconds
Started Jun 02 01:24:22 PM PDT 24
Finished Jun 02 01:24:45 PM PDT 24
Peak memory 251000 kb
Host smart-55872913-2764-4750-9428-0d29caa1c3ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836674861 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_failure.2836674861
Directory /workspace/6.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_post_trans.791737153
Short name T240
Test name
Test status
Simulation time 146774887 ps
CPU time 7.45 seconds
Started Jun 02 01:24:23 PM PDT 24
Finished Jun 02 01:24:31 PM PDT 24
Peak memory 250480 kb
Host smart-306c8f2a-d830-4321-a6d1-d5290b0ac5b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791737153 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_post_trans.791737153
Directory /workspace/6.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_volatile_unlock_smoke.2796884633
Short name T77
Test name
Test status
Simulation time 20623141 ps
CPU time 0.99 seconds
Started Jun 02 01:24:25 PM PDT 24
Finished Jun 02 01:24:26 PM PDT 24
Peak memory 212516 kb
Host smart-13a79abd-1647-4d08-abbf-3cc0fae728f8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796884633 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ct
rl_volatile_unlock_smoke.2796884633
Directory /workspace/6.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_alert_test.116272467
Short name T305
Test name
Test status
Simulation time 30990664 ps
CPU time 1.44 seconds
Started Jun 02 01:24:36 PM PDT 24
Finished Jun 02 01:24:39 PM PDT 24
Peak memory 208724 kb
Host smart-d036c757-5a15-4ca1-a10b-3cffac8dfcd3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116272467 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_alert_test.116272467
Directory /workspace/7.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.lc_ctrl_claim_transition_if.1248967331
Short name T832
Test name
Test status
Simulation time 36241178 ps
CPU time 0.77 seconds
Started Jun 02 01:24:30 PM PDT 24
Finished Jun 02 01:24:31 PM PDT 24
Peak memory 208508 kb
Host smart-ffca7e20-6a22-4a09-a76b-52131d2921ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248967331 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_claim_transition_if.1248967331
Directory /workspace/7.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/7.lc_ctrl_errors.3438716399
Short name T493
Test name
Test status
Simulation time 791668444 ps
CPU time 7.72 seconds
Started Jun 02 01:24:28 PM PDT 24
Finished Jun 02 01:24:36 PM PDT 24
Peak memory 217956 kb
Host smart-713d7112-45aa-4f5f-8218-a141a076e4b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438716399 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_errors.3438716399
Directory /workspace/7.lc_ctrl_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_access.4248626538
Short name T828
Test name
Test status
Simulation time 1392313319 ps
CPU time 4.14 seconds
Started Jun 02 01:24:29 PM PDT 24
Finished Jun 02 01:24:33 PM PDT 24
Peak memory 209764 kb
Host smart-666fea50-680d-4574-8c1f-d3f8cccea3da
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248626538 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_access.4248626538
Directory /workspace/7.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_errors.2856917581
Short name T417
Test name
Test status
Simulation time 1912373400 ps
CPU time 53.93 seconds
Started Jun 02 01:24:29 PM PDT 24
Finished Jun 02 01:25:24 PM PDT 24
Peak memory 217968 kb
Host smart-71834389-c32a-427f-8b8c-357e1f3e5881
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856917581 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_er
rors.2856917581
Directory /workspace/7.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_priority.1873996948
Short name T757
Test name
Test status
Simulation time 1562984074 ps
CPU time 17.86 seconds
Started Jun 02 01:24:29 PM PDT 24
Finished Jun 02 01:24:47 PM PDT 24
Peak memory 217764 kb
Host smart-e853af70-8d0f-45bb-96e9-b2a81de49764
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873996948 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_priority.1
873996948
Directory /workspace/7.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_prog_failure.2049254298
Short name T388
Test name
Test status
Simulation time 298809311 ps
CPU time 5.46 seconds
Started Jun 02 01:24:37 PM PDT 24
Finished Jun 02 01:24:43 PM PDT 24
Peak memory 217972 kb
Host smart-49dcd5fc-c07f-42c6-b571-981489fa25ba
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049254298 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag
_prog_failure.2049254298
Directory /workspace/7.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_regwen_during_op.65080334
Short name T634
Test name
Test status
Simulation time 4235665876 ps
CPU time 19.28 seconds
Started Jun 02 01:24:29 PM PDT 24
Finished Jun 02 01:24:49 PM PDT 24
Peak memory 217652 kb
Host smart-c99f81ac-5a69-4e1f-bafd-394a5bb812d5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65080334 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_r
egwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jt
ag_regwen_during_op.65080334
Directory /workspace/7.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_smoke.4290824611
Short name T848
Test name
Test status
Simulation time 612968642 ps
CPU time 5.12 seconds
Started Jun 02 01:24:29 PM PDT 24
Finished Jun 02 01:24:35 PM PDT 24
Peak memory 217696 kb
Host smart-3fa5f65f-fe75-49f9-99b3-339d0878c56e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290824611 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_smoke.
4290824611
Directory /workspace/7.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_failure.2843368946
Short name T339
Test name
Test status
Simulation time 12612003370 ps
CPU time 43.69 seconds
Started Jun 02 01:24:31 PM PDT 24
Finished Jun 02 01:25:15 PM PDT 24
Peak memory 275576 kb
Host smart-c8bd8d7c-b0f0-4cf5-be22-3d91b7b7d7ab
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843368946 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jta
g_state_failure.2843368946
Directory /workspace/7.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_post_trans.299983762
Short name T248
Test name
Test status
Simulation time 709021369 ps
CPU time 15.39 seconds
Started Jun 02 01:24:37 PM PDT 24
Finished Jun 02 01:24:53 PM PDT 24
Peak memory 250924 kb
Host smart-b8e81e5b-3cd0-4721-897e-f87c79cf2aff
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299983762 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_j
tag_state_post_trans.299983762
Directory /workspace/7.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_prog_failure.1966882551
Short name T383
Test name
Test status
Simulation time 84956930 ps
CPU time 1.72 seconds
Started Jun 02 01:24:25 PM PDT 24
Finished Jun 02 01:24:27 PM PDT 24
Peak memory 218016 kb
Host smart-1420b8fa-df1a-4d8b-a5b1-4e3580ef9aaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966882551 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_prog_failure.1966882551
Directory /workspace/7.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_regwen_during_op.2070064509
Short name T148
Test name
Test status
Simulation time 3090255980 ps
CPU time 5.79 seconds
Started Jun 02 01:24:27 PM PDT 24
Finished Jun 02 01:24:34 PM PDT 24
Peak memory 217812 kb
Host smart-c4c209d3-4109-4872-a84a-f691c51126a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070064509 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_regwen_during_op.2070064509
Directory /workspace/7.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_mubi.529040536
Short name T792
Test name
Test status
Simulation time 557746491 ps
CPU time 13.76 seconds
Started Jun 02 01:24:36 PM PDT 24
Finished Jun 02 01:24:50 PM PDT 24
Peak memory 226136 kb
Host smart-933ba546-0b50-49b6-a749-2d8074694c30
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529040536 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_mubi.529040536
Directory /workspace/7.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_digest.3839174242
Short name T210
Test name
Test status
Simulation time 1010521533 ps
CPU time 9.51 seconds
Started Jun 02 01:24:30 PM PDT 24
Finished Jun 02 01:24:40 PM PDT 24
Peak memory 217804 kb
Host smart-c749bc3e-f7b7-4806-8de1-0722e93a14d7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839174242 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_di
gest.3839174242
Directory /workspace/7.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_mux.2697281243
Short name T370
Test name
Test status
Simulation time 1578383520 ps
CPU time 13.26 seconds
Started Jun 02 01:24:31 PM PDT 24
Finished Jun 02 01:24:45 PM PDT 24
Peak memory 218032 kb
Host smart-278db78b-4449-4188-88f0-fb99b92c9603
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697281243 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_mux.2
697281243
Directory /workspace/7.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/7.lc_ctrl_security_escalation.2894586372
Short name T256
Test name
Test status
Simulation time 940030714 ps
CPU time 7.63 seconds
Started Jun 02 01:24:29 PM PDT 24
Finished Jun 02 01:24:37 PM PDT 24
Peak memory 218096 kb
Host smart-7cc733ac-7012-4de9-a176-ddcbce7478f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894586372 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_security_escalation.2894586372
Directory /workspace/7.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/7.lc_ctrl_smoke.1949333485
Short name T203
Test name
Test status
Simulation time 267209036 ps
CPU time 13.01 seconds
Started Jun 02 01:24:24 PM PDT 24
Finished Jun 02 01:24:38 PM PDT 24
Peak memory 214372 kb
Host smart-693691f8-4a22-4972-9758-4b0fe16eff62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949333485 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_smoke.1949333485
Directory /workspace/7.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_failure.529229165
Short name T410
Test name
Test status
Simulation time 242022130 ps
CPU time 23.07 seconds
Started Jun 02 01:24:22 PM PDT 24
Finished Jun 02 01:24:45 PM PDT 24
Peak memory 251000 kb
Host smart-515ff119-dc89-40c7-8135-a275d3761cbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=529229165 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_failure.529229165
Directory /workspace/7.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_post_trans.3907379209
Short name T812
Test name
Test status
Simulation time 96940380 ps
CPU time 7.34 seconds
Started Jun 02 01:24:24 PM PDT 24
Finished Jun 02 01:24:31 PM PDT 24
Peak memory 250532 kb
Host smart-cd6e775f-29b4-43d0-9c18-7ce8fb9b081a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907379209 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_post_trans.3907379209
Directory /workspace/7.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_stress_all.1267926647
Short name T436
Test name
Test status
Simulation time 75443422175 ps
CPU time 412.29 seconds
Started Jun 02 01:24:28 PM PDT 24
Finished Jun 02 01:31:21 PM PDT 24
Peak memory 273288 kb
Host smart-b6f51817-de7a-4f4f-96ba-f77c407d394c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267926647 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.lc_ctrl_stress_all.1267926647
Directory /workspace/7.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.lc_ctrl_volatile_unlock_smoke.1220075819
Short name T40
Test name
Test status
Simulation time 21754901 ps
CPU time 0.87 seconds
Started Jun 02 01:24:23 PM PDT 24
Finished Jun 02 01:24:24 PM PDT 24
Peak memory 208620 kb
Host smart-f5d67693-4091-4a62-931d-28631d40a543
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220075819 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ct
rl_volatile_unlock_smoke.1220075819
Directory /workspace/7.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_alert_test.1288848017
Short name T520
Test name
Test status
Simulation time 33326488 ps
CPU time 0.93 seconds
Started Jun 02 01:24:39 PM PDT 24
Finished Jun 02 01:24:41 PM PDT 24
Peak memory 208820 kb
Host smart-add836da-467f-4fe0-9e43-1944e4c63a9c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288848017 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_alert_test.1288848017
Directory /workspace/8.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.lc_ctrl_claim_transition_if.2397329048
Short name T189
Test name
Test status
Simulation time 97434947 ps
CPU time 0.83 seconds
Started Jun 02 01:24:38 PM PDT 24
Finished Jun 02 01:24:40 PM PDT 24
Peak memory 208664 kb
Host smart-f69e3abf-6d9b-4afa-a674-f96434e34cd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397329048 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_claim_transition_if.2397329048
Directory /workspace/8.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/8.lc_ctrl_errors.53296945
Short name T393
Test name
Test status
Simulation time 353876661 ps
CPU time 16.19 seconds
Started Jun 02 01:24:41 PM PDT 24
Finished Jun 02 01:24:58 PM PDT 24
Peak memory 218004 kb
Host smart-dda542f9-7b99-49a1-a8e7-08250e696384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53296945 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_errors.53296945
Directory /workspace/8.lc_ctrl_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_access.1316712745
Short name T736
Test name
Test status
Simulation time 585267076 ps
CPU time 2.32 seconds
Started Jun 02 01:24:37 PM PDT 24
Finished Jun 02 01:24:40 PM PDT 24
Peak memory 216864 kb
Host smart-0d442fe9-8a79-4a30-a336-04326726b7ed
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316712745 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_access.1316712745
Directory /workspace/8.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_errors.2362587512
Short name T412
Test name
Test status
Simulation time 9837474176 ps
CPU time 30.23 seconds
Started Jun 02 01:24:38 PM PDT 24
Finished Jun 02 01:25:09 PM PDT 24
Peak memory 218384 kb
Host smart-ec7d5f0a-6442-40ee-b888-6a5a4e02ad40
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362587512 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_er
rors.2362587512
Directory /workspace/8.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_priority.458164080
Short name T742
Test name
Test status
Simulation time 319378573 ps
CPU time 2.07 seconds
Started Jun 02 01:24:37 PM PDT 24
Finished Jun 02 01:24:40 PM PDT 24
Peak memory 217072 kb
Host smart-f511c770-d27f-4464-85b4-740ae136d709
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458164080 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_priority.458164080
Directory /workspace/8.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_prog_failure.4040496351
Short name T230
Test name
Test status
Simulation time 275053886 ps
CPU time 8.21 seconds
Started Jun 02 01:24:38 PM PDT 24
Finished Jun 02 01:24:47 PM PDT 24
Peak memory 218040 kb
Host smart-c66a6334-2f31-446d-92a6-790f4772d9c0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040496351 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag
_prog_failure.4040496351
Directory /workspace/8.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_regwen_during_op.4278548436
Short name T411
Test name
Test status
Simulation time 2707968649 ps
CPU time 16.57 seconds
Started Jun 02 01:24:39 PM PDT 24
Finished Jun 02 01:24:57 PM PDT 24
Peak memory 217724 kb
Host smart-3edf9b73-e7cc-455b-a47b-2af61e970e06
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278548436 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_regwen_during_op.4278548436
Directory /workspace/8.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_smoke.1308387235
Short name T286
Test name
Test status
Simulation time 199027022 ps
CPU time 3.6 seconds
Started Jun 02 01:24:35 PM PDT 24
Finished Jun 02 01:24:39 PM PDT 24
Peak memory 217652 kb
Host smart-ba34d63f-213d-40c1-8ad9-0e4f44ba8401
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308387235 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_smoke.
1308387235
Directory /workspace/8.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_failure.1998445742
Short name T519
Test name
Test status
Simulation time 1551893257 ps
CPU time 58.83 seconds
Started Jun 02 01:24:37 PM PDT 24
Finished Jun 02 01:25:37 PM PDT 24
Peak memory 276436 kb
Host smart-c4df72f4-3b9c-4be1-a0a0-96a483cebd8c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998445742 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jta
g_state_failure.1998445742
Directory /workspace/8.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_post_trans.3641907526
Short name T457
Test name
Test status
Simulation time 863311403 ps
CPU time 10.07 seconds
Started Jun 02 01:24:39 PM PDT 24
Finished Jun 02 01:24:49 PM PDT 24
Peak memory 221992 kb
Host smart-387bcb62-9606-4763-90e5-cd481f824691
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641907526 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_state_post_trans.3641907526
Directory /workspace/8.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_prog_failure.573799140
Short name T566
Test name
Test status
Simulation time 404075924 ps
CPU time 3.61 seconds
Started Jun 02 01:24:42 PM PDT 24
Finished Jun 02 01:24:45 PM PDT 24
Peak memory 218000 kb
Host smart-6148ed62-adac-493a-b2ba-39fe1c823056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573799140 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_prog_failure.573799140
Directory /workspace/8.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_regwen_during_op.2865318994
Short name T630
Test name
Test status
Simulation time 165907461 ps
CPU time 4.9 seconds
Started Jun 02 01:24:35 PM PDT 24
Finished Jun 02 01:24:40 PM PDT 24
Peak memory 213644 kb
Host smart-c0fe20fe-4e75-403c-bf09-6814152a7ffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865318994 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_regwen_during_op.2865318994
Directory /workspace/8.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_mubi.3214305777
Short name T706
Test name
Test status
Simulation time 2335451591 ps
CPU time 11.68 seconds
Started Jun 02 01:24:39 PM PDT 24
Finished Jun 02 01:24:52 PM PDT 24
Peak memory 226272 kb
Host smart-1d483dcc-efa7-4448-b8c2-d60b4b25229f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214305777 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_mubi.3214305777
Directory /workspace/8.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_digest.1527816452
Short name T626
Test name
Test status
Simulation time 1227797397 ps
CPU time 9.97 seconds
Started Jun 02 01:24:36 PM PDT 24
Finished Jun 02 01:24:47 PM PDT 24
Peak memory 217952 kb
Host smart-15e7cd8a-c412-418e-917c-1a1e063bde3a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527816452 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_di
gest.1527816452
Directory /workspace/8.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_mux.2534876507
Short name T850
Test name
Test status
Simulation time 409270487 ps
CPU time 8.68 seconds
Started Jun 02 01:24:36 PM PDT 24
Finished Jun 02 01:24:46 PM PDT 24
Peak memory 218016 kb
Host smart-a10c257f-f46d-4de1-9598-51b28abd56cb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534876507 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_mux.2
534876507
Directory /workspace/8.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/8.lc_ctrl_security_escalation.553833324
Short name T788
Test name
Test status
Simulation time 2548009635 ps
CPU time 11.99 seconds
Started Jun 02 01:24:36 PM PDT 24
Finished Jun 02 01:24:49 PM PDT 24
Peak memory 218172 kb
Host smart-b32fba2f-1660-4b12-8056-30588a5216bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553833324 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_security_escalation.553833324
Directory /workspace/8.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/8.lc_ctrl_smoke.2295649838
Short name T621
Test name
Test status
Simulation time 86654003 ps
CPU time 2.57 seconds
Started Jun 02 01:24:30 PM PDT 24
Finished Jun 02 01:24:33 PM PDT 24
Peak memory 217820 kb
Host smart-81ec777e-ed3d-4707-9a15-551f4b0ea6d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295649838 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_smoke.2295649838
Directory /workspace/8.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_failure.4033365234
Short name T787
Test name
Test status
Simulation time 1021415961 ps
CPU time 21.1 seconds
Started Jun 02 01:24:38 PM PDT 24
Finished Jun 02 01:25:00 PM PDT 24
Peak memory 250980 kb
Host smart-8949544f-3564-465a-9a4b-47c63f763850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033365234 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_failure.4033365234
Directory /workspace/8.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_post_trans.4227547554
Short name T446
Test name
Test status
Simulation time 210155679 ps
CPU time 5.96 seconds
Started Jun 02 01:24:39 PM PDT 24
Finished Jun 02 01:24:46 PM PDT 24
Peak memory 244448 kb
Host smart-a9125f32-405f-416d-811e-d3318a74944c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227547554 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_post_trans.4227547554
Directory /workspace/8.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_volatile_unlock_smoke.1512827199
Short name T324
Test name
Test status
Simulation time 54641179 ps
CPU time 0.94 seconds
Started Jun 02 01:24:28 PM PDT 24
Finished Jun 02 01:24:29 PM PDT 24
Peak memory 212568 kb
Host smart-0f4871f1-f291-4039-a629-504de74725e4
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512827199 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ct
rl_volatile_unlock_smoke.1512827199
Directory /workspace/8.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_alert_test.986331333
Short name T301
Test name
Test status
Simulation time 16306203 ps
CPU time 0.94 seconds
Started Jun 02 01:24:43 PM PDT 24
Finished Jun 02 01:24:45 PM PDT 24
Peak memory 208588 kb
Host smart-6a028163-ff54-4563-92ba-8ccd45d7c937
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986331333 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_alert_test.986331333
Directory /workspace/9.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.lc_ctrl_errors.1554810712
Short name T735
Test name
Test status
Simulation time 534977266 ps
CPU time 12.94 seconds
Started Jun 02 01:24:39 PM PDT 24
Finished Jun 02 01:24:53 PM PDT 24
Peak memory 218104 kb
Host smart-66e48df6-438e-4faf-b2b6-c19828c8c036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554810712 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_errors.1554810712
Directory /workspace/9.lc_ctrl_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_access.4060414576
Short name T430
Test name
Test status
Simulation time 1616627625 ps
CPU time 6.29 seconds
Started Jun 02 01:24:45 PM PDT 24
Finished Jun 02 01:24:52 PM PDT 24
Peak memory 209480 kb
Host smart-fac931ee-1f98-4481-b96d-f107d667b711
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060414576 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_access.4060414576
Directory /workspace/9.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_errors.3554281876
Short name T20
Test name
Test status
Simulation time 3253146862 ps
CPU time 29.7 seconds
Started Jun 02 01:24:44 PM PDT 24
Finished Jun 02 01:25:14 PM PDT 24
Peak memory 219156 kb
Host smart-a3741765-a51c-443d-a429-e5861d591b38
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554281876 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_er
rors.3554281876
Directory /workspace/9.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_priority.726487226
Short name T613
Test name
Test status
Simulation time 828766898 ps
CPU time 19.27 seconds
Started Jun 02 01:24:45 PM PDT 24
Finished Jun 02 01:25:05 PM PDT 24
Peak memory 217296 kb
Host smart-51088773-f43a-4a6e-88a3-b8d925cdc991
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726487226 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_priority.726487226
Directory /workspace/9.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_prog_failure.1802050446
Short name T467
Test name
Test status
Simulation time 3192157233 ps
CPU time 20.02 seconds
Started Jun 02 01:24:48 PM PDT 24
Finished Jun 02 01:25:08 PM PDT 24
Peak memory 218008 kb
Host smart-2b4f1214-b5a2-410c-8480-f67efe4c7875
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802050446 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag
_prog_failure.1802050446
Directory /workspace/9.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_regwen_during_op.4239731421
Short name T632
Test name
Test status
Simulation time 4306734203 ps
CPU time 32.32 seconds
Started Jun 02 01:24:41 PM PDT 24
Finished Jun 02 01:25:13 PM PDT 24
Peak memory 217720 kb
Host smart-32341396-4e76-4638-9746-90e2f906230f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239731421 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_regwen_during_op.4239731421
Directory /workspace/9.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_smoke.885868080
Short name T7
Test name
Test status
Simulation time 281077091 ps
CPU time 7.54 seconds
Started Jun 02 01:24:47 PM PDT 24
Finished Jun 02 01:24:55 PM PDT 24
Peak memory 217668 kb
Host smart-a1d811ef-2cd9-4e4b-84e8-250f76d404f3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885868080 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_smoke.885868080
Directory /workspace/9.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_failure.2675482521
Short name T153
Test name
Test status
Simulation time 1828889928 ps
CPU time 41.64 seconds
Started Jun 02 01:24:42 PM PDT 24
Finished Jun 02 01:25:24 PM PDT 24
Peak memory 267252 kb
Host smart-f9b211de-4816-439c-84e1-8cd9bcf4297b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675482521 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jta
g_state_failure.2675482521
Directory /workspace/9.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_post_trans.794473002
Short name T642
Test name
Test status
Simulation time 610263822 ps
CPU time 18.6 seconds
Started Jun 02 01:24:42 PM PDT 24
Finished Jun 02 01:25:01 PM PDT 24
Peak memory 223056 kb
Host smart-dd42ed4c-71a9-4609-ba85-4002aa758704
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794473002 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_j
tag_state_post_trans.794473002
Directory /workspace/9.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_prog_failure.1550257822
Short name T234
Test name
Test status
Simulation time 84851159 ps
CPU time 4.07 seconds
Started Jun 02 01:24:36 PM PDT 24
Finished Jun 02 01:24:40 PM PDT 24
Peak memory 218084 kb
Host smart-22611747-bd0c-4f81-9df6-9dbd187ee440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550257822 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_prog_failure.1550257822
Directory /workspace/9.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_regwen_during_op.80826444
Short name T691
Test name
Test status
Simulation time 1051104103 ps
CPU time 7.32 seconds
Started Jun 02 01:24:38 PM PDT 24
Finished Jun 02 01:24:45 PM PDT 24
Peak memory 213996 kb
Host smart-3317c028-2b94-4f24-b31f-b18c10c2edde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80826444 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_regwen_during_op.80826444
Directory /workspace/9.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_mubi.2568913909
Short name T655
Test name
Test status
Simulation time 606344073 ps
CPU time 12.72 seconds
Started Jun 02 01:24:47 PM PDT 24
Finished Jun 02 01:25:00 PM PDT 24
Peak memory 225664 kb
Host smart-a9387426-6f8a-4506-baa9-8c04e027c32c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568913909 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_mubi.2568913909
Directory /workspace/9.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_digest.1642816618
Short name T667
Test name
Test status
Simulation time 984903438 ps
CPU time 14.5 seconds
Started Jun 02 01:24:43 PM PDT 24
Finished Jun 02 01:24:58 PM PDT 24
Peak memory 217936 kb
Host smart-0d930f02-5446-4265-b80c-bb758c3a6225
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642816618 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_di
gest.1642816618
Directory /workspace/9.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_mux.2586307773
Short name T818
Test name
Test status
Simulation time 1585766758 ps
CPU time 10.3 seconds
Started Jun 02 01:24:42 PM PDT 24
Finished Jun 02 01:24:53 PM PDT 24
Peak memory 217992 kb
Host smart-80ec9eea-d9d2-4eb5-b456-045748e3e1e4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586307773 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_mux.2
586307773
Directory /workspace/9.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/9.lc_ctrl_security_escalation.756031917
Short name T855
Test name
Test status
Simulation time 1525026531 ps
CPU time 10.12 seconds
Started Jun 02 01:24:39 PM PDT 24
Finished Jun 02 01:24:49 PM PDT 24
Peak memory 218036 kb
Host smart-c57774e7-6484-4d6f-8dfa-a16a39b3d7ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756031917 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_security_escalation.756031917
Directory /workspace/9.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/9.lc_ctrl_smoke.2641648989
Short name T361
Test name
Test status
Simulation time 57830681 ps
CPU time 1.33 seconds
Started Jun 02 01:24:35 PM PDT 24
Finished Jun 02 01:24:37 PM PDT 24
Peak memory 217692 kb
Host smart-cdc4564f-b51d-4136-be26-bae80d80a332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641648989 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_smoke.2641648989
Directory /workspace/9.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_failure.1008697841
Short name T769
Test name
Test status
Simulation time 1499582928 ps
CPU time 24.26 seconds
Started Jun 02 01:24:39 PM PDT 24
Finished Jun 02 01:25:04 PM PDT 24
Peak memory 251016 kb
Host smart-f6477a42-f086-4330-a3b5-d8d0162f5872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008697841 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_failure.1008697841
Directory /workspace/9.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_post_trans.1011847309
Short name T217
Test name
Test status
Simulation time 192997985 ps
CPU time 7.06 seconds
Started Jun 02 01:24:42 PM PDT 24
Finished Jun 02 01:24:49 PM PDT 24
Peak memory 250996 kb
Host smart-980ef76d-24f0-4d46-aef4-a86cd39dad56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011847309 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_post_trans.1011847309
Directory /workspace/9.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_stress_all.1875654560
Short name T455
Test name
Test status
Simulation time 48269705186 ps
CPU time 139.68 seconds
Started Jun 02 01:24:46 PM PDT 24
Finished Jun 02 01:27:06 PM PDT 24
Peak memory 276580 kb
Host smart-2fe7ed7d-b7de-4abe-bef7-b9417c5d607e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875654560 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.lc_ctrl_stress_all.1875654560
Directory /workspace/9.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.lc_ctrl_volatile_unlock_smoke.2041996358
Short name T49
Test name
Test status
Simulation time 17133422 ps
CPU time 0.96 seconds
Started Jun 02 01:24:38 PM PDT 24
Finished Jun 02 01:24:40 PM PDT 24
Peak memory 211556 kb
Host smart-f1258003-e9bc-4959-8539-95f161f0ad5e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041996358 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ct
rl_volatile_unlock_smoke.2041996358
Directory /workspace/9.lc_ctrl_volatile_unlock_smoke/latest
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