Summary for Variable clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53106 |
1 |
|
|
T2 |
99 |
|
T4 |
68 |
|
T5 |
77 |
auto[1] |
1846 |
1 |
|
|
T19 |
10 |
|
T20 |
7 |
|
T21 |
30 |
Summary for Variable clk_byp_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54232 |
1 |
|
|
T2 |
99 |
|
T4 |
68 |
|
T5 |
60 |
auto[1] |
720 |
1 |
|
|
T5 |
17 |
|
T62 |
11 |
|
T63 |
14 |
Summary for Variable count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53015 |
1 |
|
|
T2 |
99 |
|
T4 |
59 |
|
T5 |
77 |
auto[1] |
1937 |
1 |
|
|
T4 |
9 |
|
T6 |
10 |
|
T16 |
7 |
Summary for Variable count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53010 |
1 |
|
|
T2 |
99 |
|
T4 |
61 |
|
T5 |
77 |
auto[1] |
1942 |
1 |
|
|
T4 |
7 |
|
T6 |
16 |
|
T16 |
9 |
Summary for Variable count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52963 |
1 |
|
|
T2 |
99 |
|
T4 |
59 |
|
T5 |
77 |
auto[1] |
1989 |
1 |
|
|
T4 |
9 |
|
T6 |
13 |
|
T16 |
9 |
Summary for Variable err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for err_inj_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
err_inj |
49962 |
1 |
|
|
T2 |
99 |
|
T4 |
68 |
|
T5 |
77 |
no_err_inj |
4990 |
1 |
|
|
T6 |
23 |
|
T17 |
6 |
|
T18 |
6 |
Summary for Variable flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52997 |
1 |
|
|
T2 |
99 |
|
T4 |
68 |
|
T5 |
77 |
auto[1] |
1955 |
1 |
|
|
T19 |
8 |
|
T20 |
5 |
|
T21 |
38 |
Summary for Variable flash_rma_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54217 |
1 |
|
|
T2 |
99 |
|
T4 |
68 |
|
T5 |
62 |
auto[1] |
735 |
1 |
|
|
T5 |
15 |
|
T62 |
11 |
|
T63 |
20 |
Summary for Variable jtag_csr_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for jtag_csr_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
38122 |
1 |
|
|
T2 |
99 |
|
T4 |
68 |
|
T5 |
77 |
auto[1] |
16830 |
1 |
|
|
T6 |
9 |
|
T8 |
14 |
|
T20 |
64 |
Summary for Variable kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for kmac_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53118 |
1 |
|
|
T2 |
99 |
|
T4 |
63 |
|
T5 |
77 |
auto[1] |
1834 |
1 |
|
|
T4 |
5 |
|
T6 |
11 |
|
T16 |
8 |
Summary for Variable lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for lc_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53053 |
1 |
|
|
T2 |
99 |
|
T4 |
58 |
|
T5 |
77 |
auto[1] |
1899 |
1 |
|
|
T4 |
10 |
|
T6 |
8 |
|
T16 |
14 |
Summary for Variable otp_lc_data_i_valid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_lc_data_i_valid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52982 |
1 |
|
|
T2 |
99 |
|
T4 |
62 |
|
T5 |
77 |
auto[1] |
1970 |
1 |
|
|
T4 |
6 |
|
T6 |
9 |
|
T16 |
13 |
Summary for Variable otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_partition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53000 |
1 |
|
|
T2 |
99 |
|
T4 |
68 |
|
T5 |
77 |
auto[1] |
1952 |
1 |
|
|
T19 |
7 |
|
T20 |
9 |
|
T21 |
32 |
Summary for Variable otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_prog_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52564 |
1 |
|
|
T2 |
99 |
|
T4 |
68 |
|
T5 |
77 |
auto[1] |
2388 |
1 |
|
|
T6 |
17 |
|
T36 |
4 |
|
T21 |
10 |
Summary for Variable otp_rma_token_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_rma_token_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54183 |
1 |
|
|
T2 |
99 |
|
T4 |
68 |
|
T5 |
58 |
auto[1] |
769 |
1 |
|
|
T5 |
19 |
|
T62 |
14 |
|
T63 |
21 |
Summary for Variable otp_secrets_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_secrets_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54192 |
1 |
|
|
T2 |
99 |
|
T4 |
68 |
|
T5 |
64 |
auto[1] |
760 |
1 |
|
|
T5 |
13 |
|
T62 |
7 |
|
T63 |
20 |
Summary for Variable otp_test_tokens_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_test_tokens_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54194 |
1 |
|
|
T2 |
99 |
|
T4 |
68 |
|
T5 |
64 |
auto[1] |
758 |
1 |
|
|
T5 |
13 |
|
T62 |
10 |
|
T63 |
13 |
Summary for Variable post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for post_trans_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52257 |
1 |
|
|
T2 |
99 |
|
T4 |
68 |
|
T5 |
77 |
auto[1] |
2695 |
1 |
|
|
T6 |
27 |
|
T17 |
15 |
|
T26 |
14 |
Summary for Variable security_escalation_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for security_escalation_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51105 |
1 |
|
|
T2 |
99 |
|
T4 |
68 |
|
T5 |
77 |
auto[1] |
3847 |
1 |
|
|
T15 |
80 |
|
T37 |
58 |
|
T55 |
76 |
Summary for Variable state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53085 |
1 |
|
|
T2 |
99 |
|
T4 |
61 |
|
T5 |
77 |
auto[1] |
1867 |
1 |
|
|
T4 |
7 |
|
T6 |
6 |
|
T16 |
9 |
Summary for Variable state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53066 |
1 |
|
|
T2 |
99 |
|
T4 |
59 |
|
T5 |
77 |
auto[1] |
1886 |
1 |
|
|
T4 |
9 |
|
T6 |
12 |
|
T16 |
9 |
Summary for Variable state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52980 |
1 |
|
|
T2 |
99 |
|
T4 |
62 |
|
T5 |
77 |
auto[1] |
1972 |
1 |
|
|
T4 |
6 |
|
T6 |
20 |
|
T16 |
4 |
Summary for Variable token_invalid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_invalid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53049 |
1 |
|
|
T2 |
99 |
|
T4 |
68 |
|
T5 |
77 |
auto[1] |
1903 |
1 |
|
|
T19 |
13 |
|
T20 |
10 |
|
T21 |
30 |
Summary for Variable token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mismatch_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49249 |
1 |
|
|
T4 |
68 |
|
T5 |
77 |
|
T6 |
145 |
auto[1] |
5703 |
1 |
|
|
T2 |
99 |
|
T19 |
10 |
|
T20 |
8 |
Summary for Variable token_mux_ctrl_redun_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mux_ctrl_redun_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51291 |
1 |
|
|
T2 |
99 |
|
T4 |
68 |
|
T5 |
77 |
auto[1] |
3661 |
1 |
|
|
T14 |
68 |
|
T27 |
70 |
|
T38 |
97 |
Summary for Variable token_mux_digest_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for token_mux_digest_err_cp
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54952 |
1 |
|
|
T2 |
99 |
|
T4 |
68 |
|
T5 |
77 |
Summary for Variable token_response_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_response_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53088 |
1 |
|
|
T2 |
99 |
|
T4 |
68 |
|
T5 |
77 |
auto[1] |
1864 |
1 |
|
|
T19 |
7 |
|
T20 |
11 |
|
T21 |
33 |
Summary for Variable transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53092 |
1 |
|
|
T2 |
99 |
|
T4 |
68 |
|
T5 |
77 |
auto[1] |
1860 |
1 |
|
|
T19 |
7 |
|
T20 |
9 |
|
T21 |
35 |
Summary for Variable transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53007 |
1 |
|
|
T2 |
99 |
|
T4 |
68 |
|
T5 |
77 |
auto[1] |
1945 |
1 |
|
|
T19 |
9 |
|
T20 |
5 |
|
T21 |
32 |
Summary for Cross post_trans_err_inj_xp
Samples crossed: post_trans_err_cp err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_err_inj_xp
Bins
post_trans_err_cp | err_inj_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
err_inj |
48591 |
1 |
|
|
T2 |
99 |
|
T4 |
68 |
|
T5 |
77 |
auto[0] |
no_err_inj |
3666 |
1 |
|
|
T6 |
11 |
|
T18 |
6 |
|
T8 |
20 |
auto[1] |
err_inj |
1371 |
1 |
|
|
T6 |
15 |
|
T17 |
9 |
|
T26 |
8 |
auto[1] |
no_err_inj |
1324 |
1 |
|
|
T6 |
12 |
|
T17 |
6 |
|
T26 |
6 |
Summary for Cross post_trans_state_err_xp
Samples crossed: post_trans_err_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_err_xp
Bins
post_trans_err_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
50526 |
1 |
|
|
T2 |
99 |
|
T4 |
59 |
|
T5 |
77 |
auto[0] |
auto[1] |
1731 |
1 |
|
|
T4 |
9 |
|
T6 |
11 |
|
T16 |
9 |
auto[1] |
auto[0] |
2540 |
1 |
|
|
T6 |
26 |
|
T17 |
14 |
|
T26 |
14 |
auto[1] |
auto[1] |
155 |
1 |
|
|
T6 |
1 |
|
T17 |
1 |
|
T43 |
4 |
Summary for Cross post_trans_lc_fsm_backdoor_err_xp
Samples crossed: post_trans_err_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_lc_fsm_backdoor_err_xp
Bins
post_trans_err_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
50504 |
1 |
|
|
T2 |
99 |
|
T4 |
58 |
|
T5 |
77 |
auto[0] |
auto[1] |
1753 |
1 |
|
|
T4 |
10 |
|
T6 |
5 |
|
T16 |
14 |
auto[1] |
auto[0] |
2549 |
1 |
|
|
T6 |
24 |
|
T17 |
14 |
|
T26 |
13 |
auto[1] |
auto[1] |
146 |
1 |
|
|
T6 |
3 |
|
T17 |
1 |
|
T26 |
1 |
Summary for Cross post_trans_state_illegal_err_xp
Samples crossed: post_trans_err_cp state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_illegal_err_xp
Bins
post_trans_err_cp | state_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
50432 |
1 |
|
|
T2 |
99 |
|
T4 |
62 |
|
T5 |
77 |
auto[0] |
auto[1] |
1825 |
1 |
|
|
T4 |
6 |
|
T6 |
16 |
|
T16 |
4 |
auto[1] |
auto[0] |
2548 |
1 |
|
|
T6 |
23 |
|
T17 |
13 |
|
T26 |
14 |
auto[1] |
auto[1] |
147 |
1 |
|
|
T6 |
4 |
|
T17 |
2 |
|
T21 |
1 |
Summary for Cross post_trans_count_err_xp
Samples crossed: post_trans_err_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_err_xp
Bins
post_trans_err_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
50466 |
1 |
|
|
T2 |
99 |
|
T4 |
61 |
|
T5 |
77 |
auto[0] |
auto[1] |
1791 |
1 |
|
|
T4 |
7 |
|
T6 |
15 |
|
T16 |
9 |
auto[1] |
auto[0] |
2544 |
1 |
|
|
T6 |
26 |
|
T17 |
14 |
|
T26 |
12 |
auto[1] |
auto[1] |
151 |
1 |
|
|
T6 |
1 |
|
T17 |
1 |
|
T26 |
2 |
Summary for Cross post_trans_count_illegal_err_xp
Samples crossed: post_trans_err_cp count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_illegal_err_xp
Bins
post_trans_err_cp | count_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
50401 |
1 |
|
|
T2 |
99 |
|
T4 |
59 |
|
T5 |
77 |
auto[0] |
auto[1] |
1856 |
1 |
|
|
T4 |
9 |
|
T6 |
12 |
|
T16 |
9 |
auto[1] |
auto[0] |
2562 |
1 |
|
|
T6 |
26 |
|
T17 |
14 |
|
T26 |
14 |
auto[1] |
auto[1] |
133 |
1 |
|
|
T6 |
1 |
|
T17 |
1 |
|
T43 |
3 |
Summary for Cross post_trans_count_backdoor_err_xp
Samples crossed: post_trans_err_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_backdoor_err_xp
Bins
post_trans_err_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
50477 |
1 |
|
|
T2 |
99 |
|
T4 |
59 |
|
T5 |
77 |
auto[0] |
auto[1] |
1780 |
1 |
|
|
T4 |
9 |
|
T6 |
10 |
|
T16 |
7 |
auto[1] |
auto[0] |
2538 |
1 |
|
|
T6 |
27 |
|
T17 |
15 |
|
T26 |
14 |
auto[1] |
auto[1] |
157 |
1 |
|
|
T43 |
4 |
|
T49 |
1 |
|
T230 |
1 |
Summary for Cross jtag_clk_byp_error_rsp_xp
Samples crossed: jtag_csr_cp clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_clk_byp_error_rsp_xp
Bins
jtag_csr_cp | clk_byp_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37015 |
1 |
|
|
T2 |
99 |
|
T4 |
68 |
|
T5 |
77 |
auto[0] |
auto[1] |
1107 |
1 |
|
|
T19 |
10 |
|
T21 |
26 |
|
T43 |
37 |
auto[1] |
auto[0] |
16091 |
1 |
|
|
T6 |
9 |
|
T8 |
14 |
|
T20 |
57 |
auto[1] |
auto[1] |
739 |
1 |
|
|
T20 |
7 |
|
T21 |
4 |
|
T22 |
9 |
Summary for Cross jtag_flash_rma_error_rsp_xp
Samples crossed: jtag_csr_cp flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_flash_rma_error_rsp_xp
Bins
jtag_csr_cp | flash_rma_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36965 |
1 |
|
|
T2 |
99 |
|
T4 |
68 |
|
T5 |
77 |
auto[0] |
auto[1] |
1157 |
1 |
|
|
T19 |
8 |
|
T21 |
29 |
|
T43 |
47 |
auto[1] |
auto[0] |
16032 |
1 |
|
|
T6 |
9 |
|
T8 |
14 |
|
T20 |
59 |
auto[1] |
auto[1] |
798 |
1 |
|
|
T20 |
5 |
|
T21 |
9 |
|
T22 |
16 |
Summary for Cross jtag_otp_prog_err_xp
Samples crossed: jtag_csr_cp otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_prog_err_xp
Bins
jtag_csr_cp | otp_prog_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36725 |
1 |
|
|
T2 |
99 |
|
T4 |
68 |
|
T5 |
77 |
auto[0] |
auto[1] |
1397 |
1 |
|
|
T6 |
17 |
|
T36 |
4 |
|
T21 |
10 |
auto[1] |
auto[0] |
15839 |
1 |
|
|
T6 |
9 |
|
T8 |
14 |
|
T20 |
64 |
auto[1] |
auto[1] |
991 |
1 |
|
|
T43 |
18 |
|
T156 |
29 |
|
T49 |
36 |
Summary for Cross jtag_otp_partition_err_xp
Samples crossed: jtag_csr_cp otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_partition_err_xp
Bins
jtag_csr_cp | otp_partition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36958 |
1 |
|
|
T2 |
99 |
|
T4 |
68 |
|
T5 |
77 |
auto[0] |
auto[1] |
1164 |
1 |
|
|
T19 |
7 |
|
T21 |
24 |
|
T43 |
42 |
auto[1] |
auto[0] |
16042 |
1 |
|
|
T6 |
9 |
|
T8 |
14 |
|
T20 |
55 |
auto[1] |
auto[1] |
788 |
1 |
|
|
T20 |
9 |
|
T21 |
8 |
|
T22 |
7 |
Summary for Cross jtag_token_mismatch_err_xp
Samples crossed: jtag_csr_cp token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_token_mismatch_err_xp
Bins
jtag_csr_cp | token_mismatch_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
33134 |
1 |
|
|
T4 |
68 |
|
T5 |
77 |
|
T6 |
136 |
auto[0] |
auto[1] |
4988 |
1 |
|
|
T2 |
99 |
|
T19 |
10 |
|
T21 |
20 |
auto[1] |
auto[0] |
16115 |
1 |
|
|
T6 |
9 |
|
T8 |
14 |
|
T20 |
56 |
auto[1] |
auto[1] |
715 |
1 |
|
|
T20 |
8 |
|
T21 |
4 |
|
T22 |
11 |
Summary for Cross jtag_state_err_xp
Samples crossed: jtag_csr_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_err_xp
Bins
jtag_csr_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37063 |
1 |
|
|
T2 |
99 |
|
T4 |
59 |
|
T5 |
77 |
auto[0] |
auto[1] |
1059 |
1 |
|
|
T4 |
9 |
|
T6 |
12 |
|
T16 |
9 |
auto[1] |
auto[0] |
16003 |
1 |
|
|
T6 |
9 |
|
T8 |
14 |
|
T20 |
64 |
auto[1] |
auto[1] |
827 |
1 |
|
|
T43 |
33 |
|
T156 |
9 |
|
T49 |
1 |
Summary for Cross jtag_state_backdoor_err_xp
Samples crossed: jtag_csr_cp state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_backdoor_err_xp
Bins
jtag_csr_cp | state_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37070 |
1 |
|
|
T2 |
99 |
|
T4 |
61 |
|
T5 |
77 |
auto[0] |
auto[1] |
1052 |
1 |
|
|
T4 |
7 |
|
T6 |
6 |
|
T16 |
9 |
auto[1] |
auto[0] |
16015 |
1 |
|
|
T6 |
9 |
|
T8 |
14 |
|
T20 |
64 |
auto[1] |
auto[1] |
815 |
1 |
|
|
T43 |
38 |
|
T156 |
4 |
|
T49 |
1 |
Summary for Cross jtag_lc_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_lc_fsm_backdoor_err_xp
Bins
jtag_csr_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37040 |
1 |
|
|
T2 |
99 |
|
T4 |
58 |
|
T5 |
77 |
auto[0] |
auto[1] |
1082 |
1 |
|
|
T4 |
10 |
|
T6 |
8 |
|
T16 |
14 |
auto[1] |
auto[0] |
16013 |
1 |
|
|
T6 |
9 |
|
T8 |
14 |
|
T20 |
64 |
auto[1] |
auto[1] |
817 |
1 |
|
|
T25 |
3 |
|
T43 |
28 |
|
T156 |
9 |
Summary for Cross jtag_kmac_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_kmac_fsm_backdoor_err_xp
Bins
jtag_csr_cp | kmac_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37089 |
1 |
|
|
T2 |
99 |
|
T4 |
63 |
|
T5 |
77 |
auto[0] |
auto[1] |
1033 |
1 |
|
|
T4 |
5 |
|
T6 |
11 |
|
T16 |
8 |
auto[1] |
auto[0] |
16029 |
1 |
|
|
T6 |
9 |
|
T8 |
14 |
|
T20 |
64 |
auto[1] |
auto[1] |
801 |
1 |
|
|
T43 |
29 |
|
T156 |
5 |
|
T49 |
1 |
Summary for Cross jtag_count_err_xp
Samples crossed: jtag_csr_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_err_xp
Bins
jtag_csr_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37027 |
1 |
|
|
T2 |
99 |
|
T4 |
61 |
|
T5 |
77 |
auto[0] |
auto[1] |
1095 |
1 |
|
|
T4 |
7 |
|
T6 |
16 |
|
T16 |
9 |
auto[1] |
auto[0] |
15983 |
1 |
|
|
T6 |
9 |
|
T8 |
14 |
|
T20 |
64 |
auto[1] |
auto[1] |
847 |
1 |
|
|
T25 |
1 |
|
T43 |
21 |
|
T156 |
8 |
Summary for Cross jtag_count_backdoor_err_xp
Samples crossed: jtag_csr_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_backdoor_err_xp
Bins
jtag_csr_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37044 |
1 |
|
|
T2 |
99 |
|
T4 |
59 |
|
T5 |
77 |
auto[0] |
auto[1] |
1078 |
1 |
|
|
T4 |
9 |
|
T6 |
10 |
|
T16 |
7 |
auto[1] |
auto[0] |
15971 |
1 |
|
|
T6 |
9 |
|
T8 |
14 |
|
T20 |
64 |
auto[1] |
auto[1] |
859 |
1 |
|
|
T43 |
33 |
|
T156 |
5 |
|
T231 |
12 |
Summary for Cross jtag_transition_err_xp
Samples crossed: jtag_csr_cp transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_err_xp
Bins
jtag_csr_cp | transition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36955 |
1 |
|
|
T2 |
99 |
|
T4 |
68 |
|
T5 |
77 |
auto[0] |
auto[1] |
1167 |
1 |
|
|
T19 |
9 |
|
T21 |
23 |
|
T43 |
52 |
auto[1] |
auto[0] |
16052 |
1 |
|
|
T6 |
9 |
|
T8 |
14 |
|
T20 |
59 |
auto[1] |
auto[1] |
778 |
1 |
|
|
T20 |
5 |
|
T21 |
9 |
|
T22 |
7 |
Summary for Cross jtag_transition_count_err_xp
Samples crossed: jtag_csr_cp transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_count_err_xp
Bins
jtag_csr_cp | transition_count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36988 |
1 |
|
|
T2 |
99 |
|
T4 |
68 |
|
T5 |
77 |
auto[0] |
auto[1] |
1134 |
1 |
|
|
T19 |
7 |
|
T21 |
24 |
|
T43 |
47 |
auto[1] |
auto[0] |
16104 |
1 |
|
|
T6 |
9 |
|
T8 |
14 |
|
T20 |
55 |
auto[1] |
auto[1] |
726 |
1 |
|
|
T20 |
9 |
|
T21 |
11 |
|
T22 |
9 |
Summary for Cross jtag_post_trans_err_xp
Samples crossed: jtag_csr_cp post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_post_trans_err_xp
Bins
jtag_csr_cp | post_trans_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36626 |
1 |
|
|
T2 |
99 |
|
T4 |
68 |
|
T5 |
77 |
auto[0] |
auto[1] |
1496 |
1 |
|
|
T6 |
27 |
|
T17 |
15 |
|
T26 |
14 |
auto[1] |
auto[0] |
15631 |
1 |
|
|
T6 |
9 |
|
T8 |
14 |
|
T20 |
64 |
auto[1] |
auto[1] |
1199 |
1 |
|
|
T25 |
10 |
|
T43 |
34 |
|
T49 |
11 |