Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

97622461

1

T1

1510

T2

56259

T3

1535

auto[1]

1400422

1

T4

2970

T5

1782

T6

3762

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

97585987

1

T1

1510

T2

56259

T3

1535

auto[1]

1436896

1

T4

2574

T5

1188

T6

5445

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	7480418	1			T1	95		T2	8993		T3	107
auto[IdleSt]	21728773	1			T1	203		T2	2785		T3	1428
auto[ClkMuxSt]	36397	1			T2	99		T5	64		T6	40
auto[CntIncrSt]	36180	1			T2	99		T5	64		T6	40
auto[CntProgSt]	1416193	1			T2	1797		T5	345		T6	80
auto[TransCheckSt]	28326	1			T2	99		T5	47		T6	23
auto[TokenHashSt]	36001851	1			T2	27366		T5	982		T6	1729
auto[FlashRmaSt]	28770	1			T5	100		T6	57		T14	52
auto[TokenCheck0St]	13160	1			T5	36		T6	23		T14	21
auto[TokenCheck1St]	9837	1			T5	23		T6	23		T14	5
auto[TransProgSt]	430334	1			T5	108		T6	46		T15	392
auto[PostTransSt]	13002664	1			T1	1212		T2	15021		T5	8200
auto[ScrapSt]	188881	1			T15	3		T21	291		T44	722
auto[EscalateSt]	6836688	1			T4	7641		T5	3751		T6	13690
auto[InvalidSt]	11782438	1			T4	7610		T5	958		T6	10851

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1973	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	11782438	1			T4	7610		T5	958		T6	10851
EscalateSt	6836688	1			T4	7641		T5	3751		T6	13690
ScrapSt	188881	1			T15	3		T21	291		T44	722
PostTransSt	13002664	1			T1	1212		T2	15021		T5	8200
TransProgSt	430334	1			T5	108		T6	46		T15	392
TokenCheck1St	9837	1			T5	23		T6	23		T14	5
TokenCheck0St	13160	1			T5	36		T6	23		T14	21
FlashRmaSt	28770	1			T5	100		T6	57		T14	52
TokenHashSt	36001851	1			T2	27366		T5	982		T6	1729
TransCheckSt	28326	1			T2	99		T5	47		T6	23
CntProgSt	1416193	1			T2	1797		T5	345		T6	80
CntIncrSt	36180	1			T2	99		T5	64		T6	40
ClkMuxSt	36397	1			T2	99		T5	64		T6	40
IdleSt	21728773	1			T1	203		T2	2785		T3	1428
ResetSt	7480418	1			T1	95		T2	8993		T3	107
arcs[ResetSt=>IdleSt]	55125	1			T1	1		T2	100		T3	1
arcs[IdleSt=>ScrapSt]	307	1			T15	1		T21	2		T44	1
arcs[IdleSt=>ClkMuxSt]	36239	1			T2	99		T5	64		T6	40
arcs[ClkMuxSt=>CntIncrSt]	36180	1			T2	99		T5	64		T6	40
arcs[CntIncrSt=>PostTransSt]	1861	1			T19	7		T20	9		T21	35
arcs[CntIncrSt=>CntProgSt]	34246	1			T2	99		T5	64		T6	40
arcs[CntProgSt=>PostTransSt]	4914	1			T5	17		T6	17		T19	10
arcs[CntProgSt=>TransCheckSt]	28326	1			T2	99		T5	47		T6	23
arcs[TransCheckSt=>PostTransSt]	3785	1			T14	40		T19	9		T27	32
arcs[TransCheckSt=>TokenHashSt]	24409	1			T2	99		T5	47		T6	23
arcs[TokenHashSt=>PostTransSt]	10390	1			T2	99		T5	11		T14	7
arcs[TokenHashSt=>FlashRmaSt]	13269	1			T5	36		T6	23		T14	21
arcs[FlashRmaSt=>TokenCheck0St]	13160	1			T5	36		T6	23		T14	21
arcs[TokenCheck0St=>PostTransSt]	3295	1			T5	13		T14	16		T19	7
arcs[TokenCheck0St=>TokenCheck1St]	9837	1			T5	23		T6	23		T14	5
arcs[TokenCheck1St=>PostTransSt]	689	1			T5	2		T14	5		T19	1
arcs[TransProgSt=>PostTransSt]	8258	1			T5	21		T6	23		T15	2
arcs[IdleSt=>EscalateSt]	208	1			T37	4		T53	6		T56	6
arcs[ClkMuxSt=>EscalateSt]	59	1			T15	2		T53	3		T54	1
arcs[CntIncrSt=>EscalateSt]	73	1			T15	3		T37	2		T55	3
arcs[CntProgSt=>EscalateSt]	1006	1			T15	30		T37	22		T55	6
arcs[TransCheckSt=>EscalateSt]	132	1			T55	6		T57	1		T53	1
arcs[TokenHashSt=>EscalateSt]	750	1			T15	7		T37	4		T21	1
arcs[FlashRmaSt=>EscalateSt]	109	1			T15	4		T37	1		T55	2
arcs[TokenCheck0St=>EscalateSt]	28	1			T15	1		T57	1		T53	2
arcs[TokenCheck1St=>EscalateSt]	159	1			T15	4		T37	2		T55	2
arcs[TransProgSt=>EscalateSt]	731	1			T15	21		T37	15		T55	11
arcs[PostTransSt=>EscalateSt]	5235	1			T5	17		T6	17		T15	2
arcs[InvalidSt=>EscalateSt]	14127	1			T4	56		T5	13		T6	76

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7480248	1			T1	95		T2	8993		T3	107
auto[0]	auto[IdleSt]	21728645	1			T1	203		T2	2785		T3	1428
auto[0]	auto[ClkMuxSt]	36358	1			T2	99		T5	64		T6	40
auto[0]	auto[CntIncrSt]	36130	1			T2	99		T5	64		T6	40
auto[0]	auto[CntProgSt]	1415531	1			T2	1797		T5	345		T6	80
auto[0]	auto[TransCheckSt]	28239	1			T2	99		T5	47		T6	23
auto[0]	auto[TokenHashSt]	36001373	1			T2	27366		T5	982		T6	1729
auto[0]	auto[FlashRmaSt]	28702	1			T5	100		T6	57		T14	52
auto[0]	auto[TokenCheck0St]	13145	1			T5	36		T6	23		T14	21
auto[0]	auto[TokenCheck1St]	9743	1			T5	23		T6	23		T14	5
auto[0]	auto[TransProgSt]	429843	1			T5	108		T6	46		T15	375
auto[0]	auto[PostTransSt]	13000085	1			T1	1212		T2	15021		T5	8191
auto[0]	auto[ScrapSt]	188836	1			T15	2		T21	291		T44	722
auto[0]	auto[EscalateSt]	5448254	1			T4	4701		T5	1987		T6	9966
auto[0]	auto[InvalidSt]	11775356	1			T4	7580		T5	949		T6	10823
auto[1]	auto[ResetSt]	170	1			T15	5		T37	5		T55	4
auto[1]	auto[IdleSt]	128	1			T37	4		T53	4		T56	5
auto[1]	auto[ClkMuxSt]	39	1			T15	1		T53	2		T54	1
auto[1]	auto[CntIncrSt]	50	1			T15	1		T37	2		T55	2
auto[1]	auto[CntProgSt]	662	1			T15	16		T37	14		T55	4
auto[1]	auto[TransCheckSt]	87	1			T55	5		T57	1		T53	1
auto[1]	auto[TokenHashSt]	478	1			T15	4		T37	4		T21	1
auto[1]	auto[FlashRmaSt]	68	1			T15	2		T55	2		T57	3
auto[1]	auto[TokenCheck0St]	15	1			T57	1		T53	1		T229	1
auto[1]	auto[TokenCheck1St]	94	1			T15	4		T37	1		T55	2
auto[1]	auto[TransProgSt]	491	1			T15	17		T37	8		T55	8
auto[1]	auto[PostTransSt]	2579	1			T5	9		T6	10		T15	1
auto[1]	auto[ScrapSt]	45	1			T15	1		T55	2		T53	2
auto[1]	auto[EscalateSt]	1388434	1			T4	2940		T5	1764		T6	3724
auto[1]	auto[InvalidSt]	7082	1			T4	30		T5	9		T6	28

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7480233	1			T1	95		T2	8993		T3	107
auto[0]	auto[IdleSt]	21728628	1			T1	203		T2	2785		T3	1428
auto[0]	auto[ClkMuxSt]	36357	1			T2	99		T5	64		T6	40
auto[0]	auto[CntIncrSt]	36130	1			T2	99		T5	64		T6	40
auto[0]	auto[CntProgSt]	1415525	1			T2	1797		T5	345		T6	80
auto[0]	auto[TransCheckSt]	28238	1			T2	99		T5	47		T6	23
auto[0]	auto[TokenHashSt]	36001335	1			T2	27366		T5	982		T6	1729
auto[0]	auto[FlashRmaSt]	28691	1			T5	100		T6	57		T14	52
auto[0]	auto[TokenCheck0St]	13138	1			T5	36		T6	23		T14	21
auto[0]	auto[TokenCheck1St]	9726	1			T5	23		T6	23		T14	5
auto[0]	auto[TransProgSt]	429852	1			T5	108		T6	46		T15	379
auto[0]	auto[PostTransSt]	12999917	1			T1	1212		T2	15021		T5	8192
auto[0]	auto[ScrapSt]	188845	1			T15	2		T21	291		T44	722
auto[0]	auto[EscalateSt]	5412006	1			T4	5093		T5	2575		T6	8300
auto[0]	auto[InvalidSt]	11775393	1			T4	7584		T5	954		T6	10803
auto[1]	auto[ResetSt]	185	1			T15	1		T37	5		T55	5
auto[1]	auto[IdleSt]	145	1			T37	3		T53	4		T56	3
auto[1]	auto[ClkMuxSt]	40	1			T15	1		T53	2		T98	2
auto[1]	auto[CntIncrSt]	50	1			T15	3		T37	2		T55	2
auto[1]	auto[CntProgSt]	668	1			T15	24		T37	13		T55	5
auto[1]	auto[TransCheckSt]	88	1			T55	5		T53	1		T56	3
auto[1]	auto[TokenHashSt]	516	1			T15	4		T37	1		T55	18
auto[1]	auto[FlashRmaSt]	79	1			T15	3		T37	1		T57	3
auto[1]	auto[TokenCheck0St]	22	1			T15	1		T53	2		T54	1
auto[1]	auto[TokenCheck1St]	111	1			T15	3		T37	2		T57	3
auto[1]	auto[TransProgSt]	482	1			T15	13		T37	10		T55	6
auto[1]	auto[PostTransSt]	2747	1			T5	8		T6	7		T15	2
auto[1]	auto[ScrapSt]	36	1			T15	1		T55	1		T57	1
auto[1]	auto[EscalateSt]	1424682	1			T4	2548		T5	1176		T6	5390
auto[1]	auto[InvalidSt]	7045	1			T4	26		T5	4		T6	48