Summary for Variable clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53830 |
1 |
|
|
T1 |
12 |
|
T3 |
78 |
|
T4 |
70 |
auto[1] |
1873 |
1 |
|
|
T6 |
64 |
|
T12 |
15 |
|
T19 |
10 |
Summary for Variable clk_byp_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54953 |
1 |
|
|
T1 |
12 |
|
T3 |
78 |
|
T4 |
70 |
auto[1] |
750 |
1 |
|
|
T38 |
15 |
|
T56 |
24 |
|
T39 |
14 |
Summary for Variable count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53601 |
1 |
|
|
T1 |
9 |
|
T3 |
78 |
|
T4 |
70 |
auto[1] |
2102 |
1 |
|
|
T1 |
3 |
|
T6 |
19 |
|
T13 |
5 |
Summary for Variable count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53665 |
1 |
|
|
T1 |
12 |
|
T3 |
78 |
|
T4 |
70 |
auto[1] |
2038 |
1 |
|
|
T6 |
15 |
|
T13 |
16 |
|
T14 |
1 |
Summary for Variable count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53624 |
1 |
|
|
T1 |
9 |
|
T3 |
78 |
|
T4 |
70 |
auto[1] |
2079 |
1 |
|
|
T1 |
3 |
|
T6 |
23 |
|
T13 |
15 |
Summary for Variable err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for err_inj_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
err_inj |
51089 |
1 |
|
|
T1 |
9 |
|
T3 |
78 |
|
T4 |
70 |
no_err_inj |
4614 |
1 |
|
|
T1 |
3 |
|
T11 |
16 |
|
T6 |
185 |
Summary for Variable flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53714 |
1 |
|
|
T1 |
12 |
|
T3 |
78 |
|
T4 |
70 |
auto[1] |
1989 |
1 |
|
|
T6 |
70 |
|
T12 |
7 |
|
T19 |
9 |
Summary for Variable flash_rma_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54969 |
1 |
|
|
T1 |
12 |
|
T3 |
78 |
|
T4 |
70 |
auto[1] |
734 |
1 |
|
|
T38 |
11 |
|
T56 |
20 |
|
T39 |
6 |
Summary for Variable jtag_csr_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for jtag_csr_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
39197 |
1 |
|
|
T3 |
78 |
|
T4 |
70 |
|
T9 |
2 |
auto[1] |
16506 |
1 |
|
|
T1 |
12 |
|
T6 |
399 |
|
T13 |
100 |
Summary for Variable kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for kmac_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53533 |
1 |
|
|
T1 |
12 |
|
T3 |
78 |
|
T4 |
70 |
auto[1] |
2170 |
1 |
|
|
T6 |
22 |
|
T13 |
9 |
|
T35 |
2 |
Summary for Variable lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for lc_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53566 |
1 |
|
|
T1 |
11 |
|
T3 |
78 |
|
T4 |
70 |
auto[1] |
2137 |
1 |
|
|
T1 |
1 |
|
T6 |
31 |
|
T13 |
10 |
Summary for Variable otp_lc_data_i_valid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_lc_data_i_valid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53564 |
1 |
|
|
T1 |
11 |
|
T3 |
78 |
|
T4 |
70 |
auto[1] |
2139 |
1 |
|
|
T1 |
1 |
|
T6 |
19 |
|
T13 |
15 |
Summary for Variable otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_partition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53867 |
1 |
|
|
T1 |
12 |
|
T3 |
78 |
|
T4 |
70 |
auto[1] |
1836 |
1 |
|
|
T6 |
57 |
|
T12 |
11 |
|
T19 |
4 |
Summary for Variable otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_prog_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53394 |
1 |
|
|
T1 |
12 |
|
T3 |
78 |
|
T4 |
70 |
auto[1] |
2309 |
1 |
|
|
T9 |
2 |
|
T6 |
62 |
|
T54 |
14 |
Summary for Variable otp_rma_token_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_rma_token_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54999 |
1 |
|
|
T1 |
12 |
|
T3 |
78 |
|
T4 |
70 |
auto[1] |
704 |
1 |
|
|
T38 |
12 |
|
T56 |
23 |
|
T39 |
14 |
Summary for Variable otp_secrets_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_secrets_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54982 |
1 |
|
|
T1 |
12 |
|
T3 |
78 |
|
T4 |
70 |
auto[1] |
721 |
1 |
|
|
T38 |
11 |
|
T56 |
19 |
|
T39 |
10 |
Summary for Variable otp_test_tokens_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_test_tokens_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54960 |
1 |
|
|
T1 |
12 |
|
T3 |
78 |
|
T4 |
70 |
auto[1] |
743 |
1 |
|
|
T38 |
12 |
|
T56 |
13 |
|
T39 |
14 |
Summary for Variable post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for post_trans_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53255 |
1 |
|
|
T3 |
78 |
|
T4 |
70 |
|
T9 |
2 |
auto[1] |
2448 |
1 |
|
|
T1 |
12 |
|
T6 |
54 |
|
T14 |
14 |
Summary for Variable security_escalation_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for security_escalation_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51812 |
1 |
|
|
T1 |
12 |
|
T9 |
2 |
|
T10 |
57 |
auto[1] |
3891 |
1 |
|
|
T3 |
78 |
|
T4 |
70 |
|
T44 |
88 |
Summary for Variable state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53680 |
1 |
|
|
T1 |
12 |
|
T3 |
78 |
|
T4 |
70 |
auto[1] |
2023 |
1 |
|
|
T6 |
13 |
|
T13 |
6 |
|
T14 |
1 |
Summary for Variable state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53655 |
1 |
|
|
T1 |
12 |
|
T3 |
78 |
|
T4 |
70 |
auto[1] |
2048 |
1 |
|
|
T6 |
13 |
|
T13 |
13 |
|
T35 |
1 |
Summary for Variable state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53680 |
1 |
|
|
T1 |
11 |
|
T3 |
78 |
|
T4 |
70 |
auto[1] |
2023 |
1 |
|
|
T1 |
1 |
|
T6 |
23 |
|
T13 |
11 |
Summary for Variable token_invalid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_invalid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53863 |
1 |
|
|
T1 |
12 |
|
T3 |
78 |
|
T4 |
70 |
auto[1] |
1840 |
1 |
|
|
T6 |
67 |
|
T12 |
18 |
|
T19 |
11 |
Summary for Variable token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mismatch_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50091 |
1 |
|
|
T1 |
12 |
|
T3 |
78 |
|
T4 |
70 |
auto[1] |
5612 |
1 |
|
|
T10 |
57 |
|
T6 |
54 |
|
T12 |
7 |
Summary for Variable token_mux_ctrl_redun_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mux_ctrl_redun_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51970 |
1 |
|
|
T1 |
12 |
|
T3 |
78 |
|
T4 |
70 |
auto[1] |
3733 |
1 |
|
|
T32 |
77 |
|
T33 |
54 |
|
T55 |
80 |
Summary for Variable token_mux_digest_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for token_mux_digest_err_cp
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
55703 |
1 |
|
|
T1 |
12 |
|
T3 |
78 |
|
T4 |
70 |
Summary for Variable token_response_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_response_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53862 |
1 |
|
|
T1 |
12 |
|
T3 |
78 |
|
T4 |
70 |
auto[1] |
1841 |
1 |
|
|
T6 |
61 |
|
T12 |
16 |
|
T19 |
2 |
Summary for Variable transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53863 |
1 |
|
|
T1 |
12 |
|
T3 |
78 |
|
T4 |
70 |
auto[1] |
1840 |
1 |
|
|
T6 |
72 |
|
T12 |
8 |
|
T19 |
7 |
Summary for Variable transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53789 |
1 |
|
|
T1 |
12 |
|
T3 |
78 |
|
T4 |
70 |
auto[1] |
1914 |
1 |
|
|
T6 |
56 |
|
T12 |
12 |
|
T19 |
4 |
Summary for Cross post_trans_err_inj_xp
Samples crossed: post_trans_err_cp err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_err_inj_xp
Bins
post_trans_err_cp | err_inj_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
err_inj |
49867 |
1 |
|
|
T3 |
78 |
|
T4 |
70 |
|
T9 |
2 |
auto[0] |
no_err_inj |
3388 |
1 |
|
|
T11 |
16 |
|
T6 |
157 |
|
T15 |
13 |
auto[1] |
err_inj |
1222 |
1 |
|
|
T1 |
9 |
|
T6 |
26 |
|
T14 |
6 |
auto[1] |
no_err_inj |
1226 |
1 |
|
|
T1 |
3 |
|
T6 |
28 |
|
T14 |
8 |
Summary for Cross post_trans_state_err_xp
Samples crossed: post_trans_err_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_err_xp
Bins
post_trans_err_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
51332 |
1 |
|
|
T3 |
78 |
|
T4 |
70 |
|
T9 |
2 |
auto[0] |
auto[1] |
1923 |
1 |
|
|
T6 |
12 |
|
T13 |
13 |
|
T80 |
10 |
auto[1] |
auto[0] |
2323 |
1 |
|
|
T1 |
12 |
|
T6 |
53 |
|
T14 |
14 |
auto[1] |
auto[1] |
125 |
1 |
|
|
T6 |
1 |
|
T35 |
1 |
|
T17 |
1 |
Summary for Cross post_trans_lc_fsm_backdoor_err_xp
Samples crossed: post_trans_err_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_lc_fsm_backdoor_err_xp
Bins
post_trans_err_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
51253 |
1 |
|
|
T3 |
78 |
|
T4 |
70 |
|
T9 |
2 |
auto[0] |
auto[1] |
2002 |
1 |
|
|
T6 |
27 |
|
T13 |
10 |
|
T80 |
5 |
auto[1] |
auto[0] |
2313 |
1 |
|
|
T1 |
11 |
|
T6 |
50 |
|
T14 |
13 |
auto[1] |
auto[1] |
135 |
1 |
|
|
T1 |
1 |
|
T6 |
4 |
|
T14 |
1 |
Summary for Cross post_trans_state_illegal_err_xp
Samples crossed: post_trans_err_cp state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_illegal_err_xp
Bins
post_trans_err_cp | state_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
51353 |
1 |
|
|
T3 |
78 |
|
T4 |
70 |
|
T9 |
2 |
auto[0] |
auto[1] |
1902 |
1 |
|
|
T6 |
20 |
|
T13 |
11 |
|
T80 |
10 |
auto[1] |
auto[0] |
2327 |
1 |
|
|
T1 |
11 |
|
T6 |
51 |
|
T14 |
14 |
auto[1] |
auto[1] |
121 |
1 |
|
|
T1 |
1 |
|
T6 |
3 |
|
T200 |
1 |
Summary for Cross post_trans_count_err_xp
Samples crossed: post_trans_err_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_err_xp
Bins
post_trans_err_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
51353 |
1 |
|
|
T3 |
78 |
|
T4 |
70 |
|
T9 |
2 |
auto[0] |
auto[1] |
1902 |
1 |
|
|
T6 |
10 |
|
T13 |
16 |
|
T80 |
7 |
auto[1] |
auto[0] |
2312 |
1 |
|
|
T1 |
12 |
|
T6 |
49 |
|
T14 |
13 |
auto[1] |
auto[1] |
136 |
1 |
|
|
T6 |
5 |
|
T14 |
1 |
|
T35 |
3 |
Summary for Cross post_trans_count_illegal_err_xp
Samples crossed: post_trans_err_cp count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_illegal_err_xp
Bins
post_trans_err_cp | count_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
51313 |
1 |
|
|
T3 |
78 |
|
T4 |
70 |
|
T9 |
2 |
auto[0] |
auto[1] |
1942 |
1 |
|
|
T6 |
21 |
|
T13 |
15 |
|
T80 |
16 |
auto[1] |
auto[0] |
2311 |
1 |
|
|
T1 |
9 |
|
T6 |
52 |
|
T14 |
12 |
auto[1] |
auto[1] |
137 |
1 |
|
|
T1 |
3 |
|
T6 |
2 |
|
T14 |
2 |
Summary for Cross post_trans_count_backdoor_err_xp
Samples crossed: post_trans_err_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_backdoor_err_xp
Bins
post_trans_err_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
51286 |
1 |
|
|
T3 |
78 |
|
T4 |
70 |
|
T9 |
2 |
auto[0] |
auto[1] |
1969 |
1 |
|
|
T6 |
18 |
|
T13 |
5 |
|
T80 |
9 |
auto[1] |
auto[0] |
2315 |
1 |
|
|
T1 |
9 |
|
T6 |
53 |
|
T14 |
14 |
auto[1] |
auto[1] |
133 |
1 |
|
|
T1 |
3 |
|
T6 |
1 |
|
T35 |
1 |
Summary for Cross jtag_clk_byp_error_rsp_xp
Samples crossed: jtag_csr_cp clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_clk_byp_error_rsp_xp
Bins
jtag_csr_cp | clk_byp_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38092 |
1 |
|
|
T3 |
78 |
|
T4 |
70 |
|
T9 |
2 |
auto[0] |
auto[1] |
1105 |
1 |
|
|
T6 |
51 |
|
T12 |
15 |
|
T34 |
18 |
auto[1] |
auto[0] |
15738 |
1 |
|
|
T1 |
12 |
|
T6 |
386 |
|
T13 |
100 |
auto[1] |
auto[1] |
768 |
1 |
|
|
T6 |
13 |
|
T19 |
10 |
|
T57 |
17 |
Summary for Cross jtag_flash_rma_error_rsp_xp
Samples crossed: jtag_csr_cp flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_flash_rma_error_rsp_xp
Bins
jtag_csr_cp | flash_rma_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38012 |
1 |
|
|
T3 |
78 |
|
T4 |
70 |
|
T9 |
2 |
auto[0] |
auto[1] |
1185 |
1 |
|
|
T6 |
40 |
|
T12 |
7 |
|
T34 |
13 |
auto[1] |
auto[0] |
15702 |
1 |
|
|
T1 |
12 |
|
T6 |
369 |
|
T13 |
100 |
auto[1] |
auto[1] |
804 |
1 |
|
|
T6 |
30 |
|
T19 |
9 |
|
T57 |
7 |
Summary for Cross jtag_otp_prog_err_xp
Samples crossed: jtag_csr_cp otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_prog_err_xp
Bins
jtag_csr_cp | otp_prog_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37854 |
1 |
|
|
T3 |
78 |
|
T4 |
70 |
|
T10 |
57 |
auto[0] |
auto[1] |
1343 |
1 |
|
|
T9 |
2 |
|
T6 |
40 |
|
T54 |
14 |
auto[1] |
auto[0] |
15540 |
1 |
|
|
T1 |
12 |
|
T6 |
377 |
|
T13 |
100 |
auto[1] |
auto[1] |
966 |
1 |
|
|
T6 |
22 |
|
T201 |
17 |
|
T202 |
17 |
Summary for Cross jtag_otp_partition_err_xp
Samples crossed: jtag_csr_cp otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_partition_err_xp
Bins
jtag_csr_cp | otp_partition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38069 |
1 |
|
|
T3 |
78 |
|
T4 |
70 |
|
T9 |
2 |
auto[0] |
auto[1] |
1128 |
1 |
|
|
T6 |
42 |
|
T12 |
11 |
|
T34 |
12 |
auto[1] |
auto[0] |
15798 |
1 |
|
|
T1 |
12 |
|
T6 |
384 |
|
T13 |
100 |
auto[1] |
auto[1] |
708 |
1 |
|
|
T6 |
15 |
|
T19 |
4 |
|
T57 |
11 |
Summary for Cross jtag_token_mismatch_err_xp
Samples crossed: jtag_csr_cp token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_token_mismatch_err_xp
Bins
jtag_csr_cp | token_mismatch_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
34335 |
1 |
|
|
T3 |
78 |
|
T4 |
70 |
|
T9 |
2 |
auto[0] |
auto[1] |
4862 |
1 |
|
|
T10 |
57 |
|
T6 |
34 |
|
T12 |
7 |
auto[1] |
auto[0] |
15756 |
1 |
|
|
T1 |
12 |
|
T6 |
379 |
|
T13 |
100 |
auto[1] |
auto[1] |
750 |
1 |
|
|
T6 |
20 |
|
T19 |
3 |
|
T57 |
6 |
Summary for Cross jtag_state_err_xp
Samples crossed: jtag_csr_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_err_xp
Bins
jtag_csr_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37949 |
1 |
|
|
T3 |
78 |
|
T4 |
70 |
|
T9 |
2 |
auto[0] |
auto[1] |
1248 |
1 |
|
|
T6 |
1 |
|
T35 |
1 |
|
T80 |
10 |
auto[1] |
auto[0] |
15706 |
1 |
|
|
T1 |
12 |
|
T6 |
387 |
|
T13 |
87 |
auto[1] |
auto[1] |
800 |
1 |
|
|
T6 |
12 |
|
T13 |
13 |
|
T17 |
1 |
Summary for Cross jtag_state_backdoor_err_xp
Samples crossed: jtag_csr_cp state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_backdoor_err_xp
Bins
jtag_csr_cp | state_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37970 |
1 |
|
|
T3 |
78 |
|
T4 |
70 |
|
T9 |
2 |
auto[0] |
auto[1] |
1227 |
1 |
|
|
T6 |
1 |
|
T14 |
1 |
|
T80 |
8 |
auto[1] |
auto[0] |
15710 |
1 |
|
|
T1 |
12 |
|
T6 |
387 |
|
T13 |
94 |
auto[1] |
auto[1] |
796 |
1 |
|
|
T6 |
12 |
|
T13 |
6 |
|
T17 |
1 |
Summary for Cross jtag_lc_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_lc_fsm_backdoor_err_xp
Bins
jtag_csr_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37893 |
1 |
|
|
T3 |
78 |
|
T4 |
70 |
|
T9 |
2 |
auto[0] |
auto[1] |
1304 |
1 |
|
|
T6 |
4 |
|
T14 |
1 |
|
T35 |
1 |
auto[1] |
auto[0] |
15673 |
1 |
|
|
T1 |
11 |
|
T6 |
372 |
|
T13 |
90 |
auto[1] |
auto[1] |
833 |
1 |
|
|
T1 |
1 |
|
T6 |
27 |
|
T13 |
10 |
Summary for Cross jtag_kmac_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_kmac_fsm_backdoor_err_xp
Bins
jtag_csr_cp | kmac_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37912 |
1 |
|
|
T3 |
78 |
|
T4 |
70 |
|
T9 |
2 |
auto[0] |
auto[1] |
1285 |
1 |
|
|
T6 |
4 |
|
T35 |
2 |
|
T80 |
4 |
auto[1] |
auto[0] |
15621 |
1 |
|
|
T1 |
12 |
|
T6 |
381 |
|
T13 |
91 |
auto[1] |
auto[1] |
885 |
1 |
|
|
T6 |
18 |
|
T13 |
9 |
|
T17 |
1 |
Summary for Cross jtag_count_err_xp
Samples crossed: jtag_csr_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_err_xp
Bins
jtag_csr_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37988 |
1 |
|
|
T3 |
78 |
|
T4 |
70 |
|
T9 |
2 |
auto[0] |
auto[1] |
1209 |
1 |
|
|
T6 |
3 |
|
T14 |
1 |
|
T35 |
3 |
auto[1] |
auto[0] |
15677 |
1 |
|
|
T1 |
12 |
|
T6 |
387 |
|
T13 |
84 |
auto[1] |
auto[1] |
829 |
1 |
|
|
T6 |
12 |
|
T13 |
16 |
|
T17 |
1 |
Summary for Cross jtag_count_backdoor_err_xp
Samples crossed: jtag_csr_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_backdoor_err_xp
Bins
jtag_csr_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37901 |
1 |
|
|
T3 |
78 |
|
T4 |
70 |
|
T9 |
2 |
auto[0] |
auto[1] |
1296 |
1 |
|
|
T6 |
1 |
|
T35 |
1 |
|
T80 |
9 |
auto[1] |
auto[0] |
15700 |
1 |
|
|
T1 |
9 |
|
T6 |
381 |
|
T13 |
95 |
auto[1] |
auto[1] |
806 |
1 |
|
|
T1 |
3 |
|
T6 |
18 |
|
T13 |
5 |
Summary for Cross jtag_transition_err_xp
Samples crossed: jtag_csr_cp transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_err_xp
Bins
jtag_csr_cp | transition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38028 |
1 |
|
|
T3 |
78 |
|
T4 |
70 |
|
T9 |
2 |
auto[0] |
auto[1] |
1169 |
1 |
|
|
T6 |
48 |
|
T12 |
12 |
|
T34 |
15 |
auto[1] |
auto[0] |
15761 |
1 |
|
|
T1 |
12 |
|
T6 |
391 |
|
T13 |
100 |
auto[1] |
auto[1] |
745 |
1 |
|
|
T6 |
8 |
|
T19 |
4 |
|
T57 |
6 |
Summary for Cross jtag_transition_count_err_xp
Samples crossed: jtag_csr_cp transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_count_err_xp
Bins
jtag_csr_cp | transition_count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38135 |
1 |
|
|
T3 |
78 |
|
T4 |
70 |
|
T9 |
2 |
auto[0] |
auto[1] |
1062 |
1 |
|
|
T6 |
52 |
|
T12 |
8 |
|
T34 |
11 |
auto[1] |
auto[0] |
15728 |
1 |
|
|
T1 |
12 |
|
T6 |
379 |
|
T13 |
100 |
auto[1] |
auto[1] |
778 |
1 |
|
|
T6 |
20 |
|
T19 |
7 |
|
T57 |
15 |
Summary for Cross jtag_post_trans_err_xp
Samples crossed: jtag_csr_cp post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_post_trans_err_xp
Bins
jtag_csr_cp | post_trans_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37836 |
1 |
|
|
T3 |
78 |
|
T4 |
70 |
|
T9 |
2 |
auto[0] |
auto[1] |
1361 |
1 |
|
|
T6 |
39 |
|
T14 |
14 |
|
T35 |
11 |
auto[1] |
auto[0] |
15419 |
1 |
|
|
T6 |
384 |
|
T13 |
100 |
|
T15 |
13 |
auto[1] |
auto[1] |
1087 |
1 |
|
|
T1 |
12 |
|
T6 |
15 |
|
T17 |
14 |