Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

103513284

1

T1

31109

T2

1115

T3

14844

auto[1]

1468652

1

T1

98

T3

8965

T4

9818

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

103504053

1

T1

30619

T2

1115

T3

14889

auto[1]

1477883

1

T1

588

T3

8920

T4

8972

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	7648620	1			T1	2551		T2	132		T3	7617
auto[IdleSt]	22209491	1			T1	5724		T2	151		T3	2173
auto[ClkMuxSt]	35902	1			T1	3		T3	72		T4	57
auto[CntIncrSt]	35610	1			T1	3		T3	70		T4	55
auto[CntProgSt]	1549637	1			T1	972		T3	289		T4	816
auto[TransCheckSt]	27534	1			T1	3		T3	43		T4	29
auto[TokenHashSt]	39770068	1			T1	219		T3	636		T4	261
auto[FlashRmaSt]	27320	1			T1	3		T3	30		T4	64
auto[TokenCheck0St]	12620	1			T1	3		T3	26		T4	20
auto[TokenCheck1St]	9216	1			T1	3		T3	25		T4	20
auto[TransProgSt]	330310	1			T1	602		T3	62		T4	89
auto[PostTransSt]	13179687	1			T1	4915		T2	832		T3	9
auto[ScrapSt]	479581	1			T3	3		T11	610		T6	2384
auto[EscalateSt]	7204057	1			T1	8615		T3	12754		T4	13681
auto[InvalidSt]	12460063	1			T1	7590		T6	249214		T13	147639

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	2220	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	12460063	1			T1	7590		T6	249214		T13	147639
EscalateSt	7204057	1			T1	8615		T3	12754		T4	13681
ScrapSt	479581	1			T3	3		T11	610		T6	2384
PostTransSt	13179687	1			T1	4915		T2	832		T3	9
TransProgSt	330310	1			T1	602		T3	62		T4	89
TokenCheck1St	9216	1			T1	3		T3	25		T4	20
TokenCheck0St	12620	1			T1	3		T3	26		T4	20
FlashRmaSt	27320	1			T1	3		T3	30		T4	64
TokenHashSt	39770068	1			T1	219		T3	636		T4	261
TransCheckSt	27534	1			T1	3		T3	43		T4	29
CntProgSt	1549637	1			T1	972		T3	289		T4	816
CntIncrSt	35610	1			T1	3		T3	70		T4	55
ClkMuxSt	35902	1			T1	3		T3	72		T4	57
IdleSt	22209491	1			T1	5724		T2	151		T3	2173
ResetSt	7648620	1			T1	2551		T2	132		T3	7617
arcs[ResetSt=>IdleSt]	55766	1			T1	12		T2	1		T3	74
arcs[IdleSt=>ScrapSt]	293	1			T3	1		T11	1		T6	7
arcs[IdleSt=>ClkMuxSt]	35670	1			T1	3		T3	72		T4	57
arcs[ClkMuxSt=>CntIncrSt]	35610	1			T1	3		T3	70		T4	55
arcs[CntIncrSt=>PostTransSt]	1842	1			T6	72		T12	8		T19	7
arcs[CntIncrSt=>CntProgSt]	33702	1			T1	3		T3	70		T4	55
arcs[CntProgSt=>PostTransSt]	4902	1			T9	2		T6	127		T12	15
arcs[CntProgSt=>TransCheckSt]	27534	1			T1	3		T3	43		T4	29
arcs[TransCheckSt=>PostTransSt]	3809	1			T6	56		T12	12		T32	38
arcs[TransCheckSt=>TokenHashSt]	23611	1			T1	3		T3	41		T4	29
arcs[TokenHashSt=>PostTransSt]	10219	1			T10	57		T6	184		T12	41
arcs[TokenHashSt=>FlashRmaSt]	12717	1			T1	3		T3	30		T4	21
arcs[FlashRmaSt=>TokenCheck0St]	12620	1			T1	3		T3	26		T4	20
arcs[TokenCheck0St=>PostTransSt]	3375	1			T6	68		T12	6		T32	19
arcs[TokenCheck0St=>TokenCheck1St]	9216	1			T1	3		T3	25		T4	20
arcs[TokenCheck1St=>PostTransSt]	667	1			T6	2		T12	1		T32	12
arcs[TransProgSt=>PostTransSt]	7628	1			T1	3		T3	5		T4	3
arcs[IdleSt=>EscalateSt]	127	1			T4	8		T45	4		T46	8
arcs[ClkMuxSt=>EscalateSt]	60	1			T3	2		T4	2		T44	1
arcs[CntIncrSt=>EscalateSt]	66	1			T44	2		T45	1		T46	1
arcs[CntProgSt=>EscalateSt]	1266	1			T3	27		T4	26		T44	37
arcs[TransCheckSt=>EscalateSt]	114	1			T3	2		T46	3		T49	2
arcs[TokenHashSt=>EscalateSt]	675	1			T3	11		T4	8		T44	10
arcs[FlashRmaSt=>EscalateSt]	97	1			T3	4		T4	1		T44	3
arcs[TokenCheck0St=>EscalateSt]	29	1			T3	1		T46	2		T49	1
arcs[TokenCheck1St=>EscalateSt]	139	1			T3	1		T4	1		T44	3
arcs[TransProgSt=>EscalateSt]	782	1			T3	19		T4	16		T44	16
arcs[PostTransSt=>EscalateSt]	5129	1			T3	5		T4	3		T9	2
arcs[InvalidSt=>EscalateSt]	15332	1			T1	7		T6	136		T13	74

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7648443	1			T1	2551		T2	132		T3	7614
auto[0]	auto[IdleSt]	22209419	1			T1	5724		T2	151		T3	2173
auto[0]	auto[ClkMuxSt]	35857	1			T1	3		T3	71		T4	55
auto[0]	auto[CntIncrSt]	35561	1			T1	3		T3	70		T4	55
auto[0]	auto[CntProgSt]	1548776	1			T1	972		T3	270		T4	798
auto[0]	auto[TransCheckSt]	27466	1			T1	3		T3	42		T4	29
auto[0]	auto[TokenHashSt]	39769614	1			T1	219		T3	628		T4	256
auto[0]	auto[FlashRmaSt]	27255	1			T1	3		T3	26		T4	64
auto[0]	auto[TokenCheck0St]	12601	1			T1	3		T3	26		T4	20
auto[0]	auto[TokenCheck1St]	9122	1			T1	3		T3	25		T4	19
auto[0]	auto[TransProgSt]	329777	1			T1	602		T3	48		T4	79
auto[0]	auto[PostTransSt]	13177093	1			T1	4915		T2	832		T3	5
auto[0]	auto[ScrapSt]	479534	1			T3	2		T11	610		T6	2384
auto[0]	auto[EscalateSt]	5748078	1			T1	8518		T3	3844		T4	3912
auto[0]	auto[InvalidSt]	12452468	1			T1	7589		T6	249151		T13	147604
auto[1]	auto[ResetSt]	177	1			T3	3		T4	5		T44	4
auto[1]	auto[IdleSt]	72	1			T4	6		T45	2		T46	5
auto[1]	auto[ClkMuxSt]	45	1			T3	1		T4	2		T44	1
auto[1]	auto[CntIncrSt]	49	1			T44	2		T46	1		T49	1
auto[1]	auto[CntProgSt]	861	1			T3	19		T4	18		T44	25
auto[1]	auto[TransCheckSt]	68	1			T3	1		T49	2		T196	1
auto[1]	auto[TokenHashSt]	454	1			T3	8		T4	5		T44	8
auto[1]	auto[FlashRmaSt]	65	1			T3	4		T44	2		T45	2
auto[1]	auto[TokenCheck0St]	19	1			T49	1		T197	1		T198	1
auto[1]	auto[TokenCheck1St]	94	1			T4	1		T44	1		T45	1
auto[1]	auto[TransProgSt]	533	1			T3	14		T4	10		T44	10
auto[1]	auto[PostTransSt]	2594	1			T3	4		T4	2		T9	2
auto[1]	auto[ScrapSt]	47	1			T3	1		T45	1		T46	1
auto[1]	auto[EscalateSt]	1455979	1			T1	97		T3	8910		T4	9769
auto[1]	auto[InvalidSt]	7595	1			T1	1		T6	63		T13	35

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7648427	1			T1	2551		T2	132		T3	7614
auto[0]	auto[IdleSt]	22209402	1			T1	5724		T2	151		T3	2173
auto[0]	auto[ClkMuxSt]	35865	1			T1	3		T3	70		T4	57
auto[0]	auto[CntIncrSt]	35566	1			T1	3		T3	70		T4	55
auto[0]	auto[CntProgSt]	1548799	1			T1	972		T3	269		T4	798
auto[0]	auto[TransCheckSt]	27456	1			T1	3		T3	42		T4	29
auto[0]	auto[TokenHashSt]	39769637	1			T1	219		T3	626		T4	257
auto[0]	auto[FlashRmaSt]	27255	1			T1	3		T3	29		T4	63
auto[0]	auto[TokenCheck0St]	12601	1			T1	3		T3	25		T4	20
auto[0]	auto[TokenCheck1St]	9134	1			T1	3		T3	24		T4	20
auto[0]	auto[TransProgSt]	329801	1			T1	602		T3	50		T4	78
auto[0]	auto[PostTransSt]	13177082	1			T1	4915		T2	832		T3	7
auto[0]	auto[ScrapSt]	479540	1			T3	2		T11	610		T6	2384
auto[0]	auto[EscalateSt]	5738942	1			T1	8033		T3	3888		T4	4755
auto[0]	auto[InvalidSt]	12452326	1			T1	7584		T6	249141		T13	147600
auto[1]	auto[ResetSt]	193	1			T3	3		T4	3		T44	13
auto[1]	auto[IdleSt]	89	1			T4	6		T45	2		T46	5
auto[1]	auto[ClkMuxSt]	37	1			T3	2		T44	1		T45	3
auto[1]	auto[CntIncrSt]	44	1			T45	1		T199	1		T49	1
auto[1]	auto[CntProgSt]	838	1			T3	20		T4	18		T44	25
auto[1]	auto[TransCheckSt]	78	1			T3	1		T46	3		T49	1
auto[1]	auto[TokenHashSt]	431	1			T3	10		T4	4		T44	6
auto[1]	auto[FlashRmaSt]	65	1			T3	1		T4	1		T44	2
auto[1]	auto[TokenCheck0St]	19	1			T3	1		T46	2		T198	1
auto[1]	auto[TokenCheck1St]	82	1			T3	1		T44	2		T45	1
auto[1]	auto[TransProgSt]	509	1			T3	12		T4	11		T44	8
auto[1]	auto[PostTransSt]	2605	1			T3	2		T4	3		T6	62
auto[1]	auto[ScrapSt]	41	1			T3	1		T45	1		T46	2
auto[1]	auto[EscalateSt]	1465115	1			T1	582		T3	8866		T4	8926
auto[1]	auto[InvalidSt]	7737	1			T1	6		T6	73		T13	39