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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.88 97.89 95.68 93.31 97.67 98.55 98.76 96.29


Total test records in report: 999
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T66 /workspace/coverage/default/0.lc_ctrl_regwen_during_op.1910436790 Jun 05 05:58:42 PM PDT 24 Jun 05 05:58:47 PM PDT 24 326088088 ps
T814 /workspace/coverage/default/13.lc_ctrl_prog_failure.1640243255 Jun 05 05:59:13 PM PDT 24 Jun 05 05:59:15 PM PDT 24 22862472 ps
T815 /workspace/coverage/default/6.lc_ctrl_claim_transition_if.3944735510 Jun 05 05:58:37 PM PDT 24 Jun 05 05:58:45 PM PDT 24 20643252 ps
T816 /workspace/coverage/default/10.lc_ctrl_alert_test.353741724 Jun 05 05:59:05 PM PDT 24 Jun 05 05:59:07 PM PDT 24 24196814 ps
T817 /workspace/coverage/default/41.lc_ctrl_jtag_access.4149968548 Jun 05 06:00:19 PM PDT 24 Jun 05 06:00:24 PM PDT 24 491210476 ps
T818 /workspace/coverage/default/13.lc_ctrl_errors.3730868206 Jun 05 05:58:59 PM PDT 24 Jun 05 05:59:17 PM PDT 24 380633237 ps
T819 /workspace/coverage/default/5.lc_ctrl_jtag_regwen_during_op.674153652 Jun 05 05:58:40 PM PDT 24 Jun 05 05:59:04 PM PDT 24 785736165 ps
T820 /workspace/coverage/default/47.lc_ctrl_stress_all.2659809250 Jun 05 06:00:22 PM PDT 24 Jun 05 06:04:13 PM PDT 24 58874758472 ps
T821 /workspace/coverage/default/2.lc_ctrl_state_failure.4078019389 Jun 05 05:58:44 PM PDT 24 Jun 05 05:59:22 PM PDT 24 1552601280 ps
T822 /workspace/coverage/default/48.lc_ctrl_errors.3101512068 Jun 05 06:00:33 PM PDT 24 Jun 05 06:00:49 PM PDT 24 1441278945 ps
T823 /workspace/coverage/default/17.lc_ctrl_sec_token_mux.3759816041 Jun 05 05:59:20 PM PDT 24 Jun 05 05:59:38 PM PDT 24 498636233 ps
T824 /workspace/coverage/default/26.lc_ctrl_jtag_access.1379291047 Jun 05 05:59:34 PM PDT 24 Jun 05 05:59:38 PM PDT 24 1885433798 ps
T825 /workspace/coverage/default/42.lc_ctrl_state_failure.1310587687 Jun 05 06:00:27 PM PDT 24 Jun 05 06:00:59 PM PDT 24 469144434 ps
T826 /workspace/coverage/default/39.lc_ctrl_sec_token_mux.295415749 Jun 05 05:59:54 PM PDT 24 Jun 05 06:00:05 PM PDT 24 8374337154 ps
T827 /workspace/coverage/default/2.lc_ctrl_sec_token_mux.635932355 Jun 05 05:58:38 PM PDT 24 Jun 05 05:58:49 PM PDT 24 411133602 ps
T828 /workspace/coverage/default/32.lc_ctrl_stress_all.1197213274 Jun 05 05:59:43 PM PDT 24 Jun 05 06:00:14 PM PDT 24 6833908901 ps
T48 /workspace/coverage/default/1.lc_ctrl_sec_cm.303107186 Jun 05 05:58:31 PM PDT 24 Jun 05 05:59:09 PM PDT 24 205295898 ps
T829 /workspace/coverage/default/3.lc_ctrl_errors.937280786 Jun 05 05:58:36 PM PDT 24 Jun 05 05:58:50 PM PDT 24 1055761431 ps
T830 /workspace/coverage/default/36.lc_ctrl_prog_failure.4019733166 Jun 05 06:00:05 PM PDT 24 Jun 05 06:00:08 PM PDT 24 73937325 ps
T831 /workspace/coverage/default/44.lc_ctrl_errors.1208266241 Jun 05 06:00:18 PM PDT 24 Jun 05 06:00:30 PM PDT 24 2275544153 ps
T832 /workspace/coverage/default/28.lc_ctrl_security_escalation.3602586375 Jun 05 05:59:35 PM PDT 24 Jun 05 05:59:42 PM PDT 24 1180071159 ps
T833 /workspace/coverage/default/17.lc_ctrl_errors.3206367241 Jun 05 05:59:24 PM PDT 24 Jun 05 05:59:39 PM PDT 24 1361886750 ps
T834 /workspace/coverage/default/17.lc_ctrl_jtag_smoke.704162777 Jun 05 05:59:15 PM PDT 24 Jun 05 05:59:20 PM PDT 24 1277957041 ps
T835 /workspace/coverage/default/32.lc_ctrl_smoke.379214060 Jun 05 05:59:51 PM PDT 24 Jun 05 05:59:52 PM PDT 24 15622691 ps
T836 /workspace/coverage/default/42.lc_ctrl_volatile_unlock_smoke.3885398481 Jun 05 06:00:13 PM PDT 24 Jun 05 06:00:14 PM PDT 24 54363646 ps
T837 /workspace/coverage/default/7.lc_ctrl_sec_mubi.660962710 Jun 05 05:58:39 PM PDT 24 Jun 05 05:58:49 PM PDT 24 865529231 ps
T838 /workspace/coverage/default/12.lc_ctrl_alert_test.1675078483 Jun 05 05:58:59 PM PDT 24 Jun 05 05:59:01 PM PDT 24 19218472 ps
T839 /workspace/coverage/default/0.lc_ctrl_sec_mubi.3460704513 Jun 05 05:58:42 PM PDT 24 Jun 05 05:58:55 PM PDT 24 291268382 ps
T840 /workspace/coverage/default/29.lc_ctrl_sec_token_mux.2101574090 Jun 05 05:59:39 PM PDT 24 Jun 05 05:59:50 PM PDT 24 268201029 ps
T841 /workspace/coverage/default/2.lc_ctrl_jtag_state_post_trans.3246280657 Jun 05 05:58:40 PM PDT 24 Jun 05 05:58:58 PM PDT 24 3118770332 ps
T842 /workspace/coverage/default/22.lc_ctrl_sec_mubi.1539324673 Jun 05 05:59:26 PM PDT 24 Jun 05 05:59:40 PM PDT 24 288117250 ps
T843 /workspace/coverage/default/46.lc_ctrl_sec_mubi.3182243246 Jun 05 06:00:14 PM PDT 24 Jun 05 06:00:25 PM PDT 24 420463182 ps
T844 /workspace/coverage/default/6.lc_ctrl_stress_all.3933844140 Jun 05 05:58:46 PM PDT 24 Jun 05 05:59:49 PM PDT 24 11892697218 ps
T845 /workspace/coverage/default/29.lc_ctrl_errors.3811236803 Jun 05 05:59:40 PM PDT 24 Jun 05 05:59:51 PM PDT 24 301326469 ps
T846 /workspace/coverage/default/22.lc_ctrl_errors.2271886545 Jun 05 05:59:27 PM PDT 24 Jun 05 05:59:39 PM PDT 24 220650448 ps
T847 /workspace/coverage/default/27.lc_ctrl_volatile_unlock_smoke.3607637633 Jun 05 05:59:35 PM PDT 24 Jun 05 05:59:37 PM PDT 24 26813612 ps
T91 /workspace/coverage/default/0.lc_ctrl_stress_all_with_rand_reset.1055741599 Jun 05 05:58:35 PM PDT 24 Jun 05 06:16:11 PM PDT 24 146942949063 ps
T92 /workspace/coverage/default/30.lc_ctrl_jtag_access.11465652 Jun 05 05:59:44 PM PDT 24 Jun 05 05:59:52 PM PDT 24 1352605897 ps
T93 /workspace/coverage/default/35.lc_ctrl_errors.3973562204 Jun 05 05:59:55 PM PDT 24 Jun 05 06:00:05 PM PDT 24 993593896 ps
T94 /workspace/coverage/default/19.lc_ctrl_state_failure.819071745 Jun 05 05:59:26 PM PDT 24 Jun 05 05:59:53 PM PDT 24 877748863 ps
T95 /workspace/coverage/default/8.lc_ctrl_jtag_state_failure.2499273459 Jun 05 05:58:46 PM PDT 24 Jun 05 05:59:25 PM PDT 24 1213300059 ps
T96 /workspace/coverage/default/9.lc_ctrl_stress_all.1515676229 Jun 05 05:58:48 PM PDT 24 Jun 05 06:00:22 PM PDT 24 9886201166 ps
T97 /workspace/coverage/default/12.lc_ctrl_jtag_access.2033957049 Jun 05 05:59:05 PM PDT 24 Jun 05 05:59:19 PM PDT 24 2415088148 ps
T98 /workspace/coverage/default/19.lc_ctrl_errors.177237142 Jun 05 05:59:30 PM PDT 24 Jun 05 05:59:47 PM PDT 24 468378960 ps
T99 /workspace/coverage/default/11.lc_ctrl_jtag_state_post_trans.2155673054 Jun 05 05:59:14 PM PDT 24 Jun 05 05:59:28 PM PDT 24 4949995061 ps
T100 /workspace/coverage/default/16.lc_ctrl_jtag_state_post_trans.2523309279 Jun 05 05:59:14 PM PDT 24 Jun 05 05:59:32 PM PDT 24 349287389 ps
T848 /workspace/coverage/default/1.lc_ctrl_jtag_access.1869338649 Jun 05 05:58:37 PM PDT 24 Jun 05 05:58:41 PM PDT 24 1034587455 ps
T849 /workspace/coverage/default/18.lc_ctrl_jtag_state_post_trans.4228053429 Jun 05 05:59:16 PM PDT 24 Jun 05 05:59:31 PM PDT 24 1640848054 ps
T850 /workspace/coverage/default/9.lc_ctrl_jtag_access.3629364983 Jun 05 05:58:47 PM PDT 24 Jun 05 05:58:53 PM PDT 24 537626766 ps
T851 /workspace/coverage/default/22.lc_ctrl_jtag_access.1030504503 Jun 05 05:59:27 PM PDT 24 Jun 05 05:59:35 PM PDT 24 473910003 ps
T852 /workspace/coverage/default/2.lc_ctrl_jtag_priority.821964200 Jun 05 05:58:37 PM PDT 24 Jun 05 05:58:42 PM PDT 24 462494207 ps
T853 /workspace/coverage/default/0.lc_ctrl_alert_test.13105290 Jun 05 05:58:31 PM PDT 24 Jun 05 05:58:32 PM PDT 24 15967249 ps
T854 /workspace/coverage/default/31.lc_ctrl_volatile_unlock_smoke.498287619 Jun 05 05:59:42 PM PDT 24 Jun 05 05:59:44 PM PDT 24 19288027 ps
T855 /workspace/coverage/default/42.lc_ctrl_alert_test.4054695805 Jun 05 06:00:11 PM PDT 24 Jun 05 06:00:13 PM PDT 24 83941558 ps
T856 /workspace/coverage/default/10.lc_ctrl_smoke.1470550367 Jun 05 05:59:02 PM PDT 24 Jun 05 05:59:04 PM PDT 24 22799206 ps
T857 /workspace/coverage/default/46.lc_ctrl_alert_test.1959083356 Jun 05 06:00:28 PM PDT 24 Jun 05 06:00:30 PM PDT 24 50212941 ps
T858 /workspace/coverage/default/41.lc_ctrl_prog_failure.624812532 Jun 05 06:00:05 PM PDT 24 Jun 05 06:00:08 PM PDT 24 83186529 ps
T859 /workspace/coverage/default/10.lc_ctrl_jtag_access.1786767632 Jun 05 05:59:11 PM PDT 24 Jun 05 05:59:21 PM PDT 24 1069985920 ps
T860 /workspace/coverage/default/15.lc_ctrl_errors.2183740116 Jun 05 05:59:14 PM PDT 24 Jun 05 05:59:22 PM PDT 24 196591799 ps
T861 /workspace/coverage/default/21.lc_ctrl_state_post_trans.2934823151 Jun 05 05:59:30 PM PDT 24 Jun 05 05:59:38 PM PDT 24 57478496 ps
T862 /workspace/coverage/default/9.lc_ctrl_jtag_state_post_trans.4205403330 Jun 05 05:58:49 PM PDT 24 Jun 05 05:59:05 PM PDT 24 439924671 ps
T863 /workspace/coverage/default/19.lc_ctrl_volatile_unlock_smoke.2605988516 Jun 05 05:59:16 PM PDT 24 Jun 05 05:59:17 PM PDT 24 22788776 ps
T864 /workspace/coverage/default/5.lc_ctrl_security_escalation.2098575484 Jun 05 05:58:34 PM PDT 24 Jun 05 05:58:45 PM PDT 24 478975564 ps
T865 /workspace/coverage/default/20.lc_ctrl_prog_failure.4235274928 Jun 05 05:59:28 PM PDT 24 Jun 05 05:59:34 PM PDT 24 2391869018 ps
T130 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.352206150 Jun 05 04:33:22 PM PDT 24 Jun 05 04:33:24 PM PDT 24 46572982 ps
T119 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.3574154837 Jun 05 04:33:23 PM PDT 24 Jun 05 04:33:25 PM PDT 24 52773375 ps
T131 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.613615410 Jun 05 04:33:29 PM PDT 24 Jun 05 04:33:31 PM PDT 24 88504100 ps
T123 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.2437746398 Jun 05 04:33:30 PM PDT 24 Jun 05 04:33:33 PM PDT 24 140635675 ps
T115 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.3158315026 Jun 05 04:33:37 PM PDT 24 Jun 05 04:33:42 PM PDT 24 78206719 ps
T116 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.3700745806 Jun 05 04:33:38 PM PDT 24 Jun 05 04:33:41 PM PDT 24 53819505 ps
T150 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.965222706 Jun 05 04:33:14 PM PDT 24 Jun 05 04:33:21 PM PDT 24 1020031815 ps
T117 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.1132816385 Jun 05 04:33:31 PM PDT 24 Jun 05 04:33:35 PM PDT 24 285208831 ps
T124 /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.2044150699 Jun 05 04:33:30 PM PDT 24 Jun 05 04:33:33 PM PDT 24 42204390 ps
T151 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.1725876080 Jun 05 04:33:26 PM PDT 24 Jun 05 04:33:29 PM PDT 24 558517946 ps
T184 /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.2801404832 Jun 05 04:33:40 PM PDT 24 Jun 05 04:33:42 PM PDT 24 18984403 ps
T120 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.2891712506 Jun 05 04:33:26 PM PDT 24 Jun 05 04:33:30 PM PDT 24 103606351 ps
T156 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.565881722 Jun 05 04:33:41 PM PDT 24 Jun 05 04:33:44 PM PDT 24 120453280 ps
T152 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.4139258137 Jun 05 04:33:37 PM PDT 24 Jun 05 04:33:39 PM PDT 24 49199740 ps
T121 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.3155780880 Jun 05 04:33:38 PM PDT 24 Jun 05 04:33:41 PM PDT 24 135180123 ps
T160 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.2475981375 Jun 05 04:33:40 PM PDT 24 Jun 05 04:33:43 PM PDT 24 20001744 ps
T157 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.2625272256 Jun 05 04:33:38 PM PDT 24 Jun 05 04:33:40 PM PDT 24 89535018 ps
T185 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.503221476 Jun 05 04:33:26 PM PDT 24 Jun 05 04:33:28 PM PDT 24 22615407 ps
T122 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.3391794149 Jun 05 04:33:45 PM PDT 24 Jun 05 04:33:50 PM PDT 24 212311617 ps
T866 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.2271835570 Jun 05 04:33:33 PM PDT 24 Jun 05 04:33:36 PM PDT 24 423416313 ps
T186 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.3803210255 Jun 05 04:33:43 PM PDT 24 Jun 05 04:33:46 PM PDT 24 69702160 ps
T127 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.802603088 Jun 05 04:33:31 PM PDT 24 Jun 05 04:33:35 PM PDT 24 214893266 ps
T187 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.4044842934 Jun 05 04:33:13 PM PDT 24 Jun 05 04:33:15 PM PDT 24 44712217 ps
T867 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.2204846896 Jun 05 04:33:24 PM PDT 24 Jun 05 04:33:38 PM PDT 24 2043484413 ps
T128 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.3251974306 Jun 05 04:33:31 PM PDT 24 Jun 05 04:33:35 PM PDT 24 117205310 ps
T868 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.2711631779 Jun 05 04:33:32 PM PDT 24 Jun 05 04:33:34 PM PDT 24 34609580 ps
T178 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.2142474 Jun 05 04:33:34 PM PDT 24 Jun 05 04:33:35 PM PDT 24 52260128 ps
T869 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.2572195878 Jun 05 04:33:26 PM PDT 24 Jun 05 04:33:29 PM PDT 24 147745603 ps
T870 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.1464710852 Jun 05 04:33:24 PM PDT 24 Jun 05 04:33:27 PM PDT 24 126023630 ps
T188 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.3717432996 Jun 05 04:33:48 PM PDT 24 Jun 05 04:33:51 PM PDT 24 20075104 ps
T158 /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.2155417872 Jun 05 04:33:34 PM PDT 24 Jun 05 04:33:37 PM PDT 24 179557802 ps
T871 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.3794354086 Jun 05 04:33:29 PM PDT 24 Jun 05 04:33:31 PM PDT 24 57949588 ps
T147 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.3554779750 Jun 05 04:33:24 PM PDT 24 Jun 05 04:33:33 PM PDT 24 1454589049 ps
T872 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.3597604657 Jun 05 04:33:27 PM PDT 24 Jun 05 04:33:31 PM PDT 24 136279590 ps
T189 /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.2089819114 Jun 05 04:33:44 PM PDT 24 Jun 05 04:33:48 PM PDT 24 21796101 ps
T129 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2378509801 Jun 05 04:33:17 PM PDT 24 Jun 05 04:33:20 PM PDT 24 145005810 ps
T148 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.784756657 Jun 05 04:33:37 PM PDT 24 Jun 05 04:33:40 PM PDT 24 439089065 ps
T873 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.3863269057 Jun 05 04:33:13 PM PDT 24 Jun 05 04:33:17 PM PDT 24 105510177 ps
T874 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.1045922195 Jun 05 04:33:25 PM PDT 24 Jun 05 04:33:31 PM PDT 24 983393873 ps
T875 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.882680716 Jun 05 04:33:40 PM PDT 24 Jun 05 04:33:43 PM PDT 24 48006649 ps
T149 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1153804270 Jun 05 04:33:51 PM PDT 24 Jun 05 04:33:54 PM PDT 24 1865097510 ps
T876 /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.3149491899 Jun 05 04:33:41 PM PDT 24 Jun 05 04:33:43 PM PDT 24 40168965 ps
T877 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.1209981305 Jun 05 04:33:42 PM PDT 24 Jun 05 04:33:45 PM PDT 24 27120469 ps
T878 /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.3860932054 Jun 05 04:33:26 PM PDT 24 Jun 05 04:33:28 PM PDT 24 160957401 ps
T879 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.375217839 Jun 05 04:33:24 PM PDT 24 Jun 05 04:33:27 PM PDT 24 57531401 ps
T880 /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.959798649 Jun 05 04:33:39 PM PDT 24 Jun 05 04:33:41 PM PDT 24 81526784 ps
T881 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.2589271598 Jun 05 04:33:25 PM PDT 24 Jun 05 04:33:27 PM PDT 24 517764737 ps
T882 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.3722967683 Jun 05 04:33:56 PM PDT 24 Jun 05 04:33:57 PM PDT 24 17534308 ps
T138 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.3625749915 Jun 05 04:33:27 PM PDT 24 Jun 05 04:33:32 PM PDT 24 145946661 ps
T883 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.3811268252 Jun 05 04:33:14 PM PDT 24 Jun 05 04:33:17 PM PDT 24 25655457 ps
T884 /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.3539638664 Jun 05 04:33:47 PM PDT 24 Jun 05 04:33:50 PM PDT 24 140143303 ps
T885 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.2105882514 Jun 05 04:33:34 PM PDT 24 Jun 05 04:33:37 PM PDT 24 105020226 ps
T886 /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.2531400181 Jun 05 04:34:10 PM PDT 24 Jun 05 04:34:12 PM PDT 24 54403767 ps
T887 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.3478431775 Jun 05 04:33:26 PM PDT 24 Jun 05 04:33:28 PM PDT 24 35680093 ps
T179 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.314431225 Jun 05 04:33:25 PM PDT 24 Jun 05 04:33:28 PM PDT 24 19400445 ps
T888 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.981262353 Jun 05 04:33:12 PM PDT 24 Jun 05 04:33:16 PM PDT 24 164785630 ps
T889 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.94547718 Jun 05 04:33:34 PM PDT 24 Jun 05 04:33:40 PM PDT 24 2054533827 ps
T890 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.2323285182 Jun 05 04:33:38 PM PDT 24 Jun 05 04:33:39 PM PDT 24 52612677 ps
T891 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.1657981243 Jun 05 04:33:27 PM PDT 24 Jun 05 04:33:28 PM PDT 24 26194524 ps
T892 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.1989226790 Jun 05 04:33:41 PM PDT 24 Jun 05 04:33:46 PM PDT 24 508400797 ps
T893 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.3589148530 Jun 05 04:33:31 PM PDT 24 Jun 05 04:33:35 PM PDT 24 86527025 ps
T894 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.814367065 Jun 05 04:33:39 PM PDT 24 Jun 05 04:33:42 PM PDT 24 92979102 ps
T143 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.1390304985 Jun 05 04:33:41 PM PDT 24 Jun 05 04:33:44 PM PDT 24 70325898 ps
T895 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.4151124594 Jun 05 04:33:35 PM PDT 24 Jun 05 04:33:38 PM PDT 24 57181074 ps
T896 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.2149014717 Jun 05 04:33:32 PM PDT 24 Jun 05 04:33:42 PM PDT 24 8187889665 ps
T897 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.2096869495 Jun 05 04:33:30 PM PDT 24 Jun 05 04:33:32 PM PDT 24 310320560 ps
T898 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.1853646974 Jun 05 04:33:11 PM PDT 24 Jun 05 04:33:23 PM PDT 24 1831500168 ps
T142 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.2001852748 Jun 05 04:33:47 PM PDT 24 Jun 05 04:33:52 PM PDT 24 103855546 ps
T899 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.1978053352 Jun 05 04:33:41 PM PDT 24 Jun 05 04:33:45 PM PDT 24 149527955 ps
T900 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.1517837317 Jun 05 04:33:26 PM PDT 24 Jun 05 04:33:29 PM PDT 24 18353883 ps
T901 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.4050036279 Jun 05 04:33:28 PM PDT 24 Jun 05 04:33:30 PM PDT 24 23225609 ps
T902 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.1827707766 Jun 05 04:33:43 PM PDT 24 Jun 05 04:33:46 PM PDT 24 38277756 ps
T903 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.641912060 Jun 05 04:33:39 PM PDT 24 Jun 05 04:33:40 PM PDT 24 17007268 ps
T904 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.1022682520 Jun 05 04:33:31 PM PDT 24 Jun 05 04:33:44 PM PDT 24 2388742051 ps
T905 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2389560463 Jun 05 04:33:30 PM PDT 24 Jun 05 04:33:35 PM PDT 24 1583074053 ps
T906 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.2663408807 Jun 05 04:33:31 PM PDT 24 Jun 05 04:33:38 PM PDT 24 1007420769 ps
T907 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.885508389 Jun 05 04:33:48 PM PDT 24 Jun 05 04:33:51 PM PDT 24 38254055 ps
T908 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.2742660358 Jun 05 04:33:14 PM PDT 24 Jun 05 04:33:17 PM PDT 24 94825126 ps
T909 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.3784147587 Jun 05 04:34:03 PM PDT 24 Jun 05 04:34:08 PM PDT 24 301942696 ps
T134 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.42755817 Jun 05 04:33:40 PM PDT 24 Jun 05 04:33:45 PM PDT 24 232858872 ps
T910 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.3610737936 Jun 05 04:33:30 PM PDT 24 Jun 05 04:33:50 PM PDT 24 2477818377 ps
T139 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.809607419 Jun 05 04:33:47 PM PDT 24 Jun 05 04:33:56 PM PDT 24 281997745 ps
T180 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.2672123933 Jun 05 04:33:27 PM PDT 24 Jun 05 04:33:30 PM PDT 24 29402752 ps
T911 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.1779147706 Jun 05 04:33:52 PM PDT 24 Jun 05 04:33:55 PM PDT 24 231763498 ps
T912 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.3320768182 Jun 05 04:33:37 PM PDT 24 Jun 05 04:33:39 PM PDT 24 18150063 ps
T913 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.1729503596 Jun 05 04:33:42 PM PDT 24 Jun 05 04:33:47 PM PDT 24 200291283 ps
T914 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.1163099318 Jun 05 04:33:44 PM PDT 24 Jun 05 04:33:47 PM PDT 24 17972313 ps
T915 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.4173761904 Jun 05 04:33:43 PM PDT 24 Jun 05 04:33:48 PM PDT 24 107623076 ps
T916 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.2642415997 Jun 05 04:33:30 PM PDT 24 Jun 05 04:33:33 PM PDT 24 102450397 ps
T917 /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.1327018203 Jun 05 04:33:43 PM PDT 24 Jun 05 04:33:47 PM PDT 24 16838923 ps
T918 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.767400305 Jun 05 04:33:10 PM PDT 24 Jun 05 04:33:13 PM PDT 24 29525423 ps
T919 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.2189019985 Jun 05 04:33:46 PM PDT 24 Jun 05 04:33:49 PM PDT 24 130464423 ps
T920 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.1223072979 Jun 05 04:33:30 PM PDT 24 Jun 05 04:33:32 PM PDT 24 29797586 ps
T145 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.4284343904 Jun 05 04:33:53 PM PDT 24 Jun 05 04:33:57 PM PDT 24 385834961 ps
T921 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.2062358480 Jun 05 04:33:36 PM PDT 24 Jun 05 04:33:38 PM PDT 24 34995285 ps
T922 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.999921037 Jun 05 04:33:41 PM PDT 24 Jun 05 04:33:44 PM PDT 24 110439504 ps
T923 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.3428409179 Jun 05 04:33:22 PM PDT 24 Jun 05 04:33:26 PM PDT 24 364610887 ps
T924 /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.2458373054 Jun 05 04:33:50 PM PDT 24 Jun 05 04:33:52 PM PDT 24 23320165 ps
T925 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.3589547428 Jun 05 04:33:36 PM PDT 24 Jun 05 04:33:40 PM PDT 24 81404403 ps
T926 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.24231319 Jun 05 04:33:27 PM PDT 24 Jun 05 04:33:29 PM PDT 24 16490064 ps
T927 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.763870000 Jun 05 04:33:37 PM PDT 24 Jun 05 04:33:38 PM PDT 24 26334293 ps
T928 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.2598554630 Jun 05 04:33:51 PM PDT 24 Jun 05 04:34:01 PM PDT 24 1083802720 ps
T929 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.2330033126 Jun 05 04:33:39 PM PDT 24 Jun 05 04:33:41 PM PDT 24 17714702 ps
T930 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.1070552017 Jun 05 04:33:28 PM PDT 24 Jun 05 04:33:31 PM PDT 24 617236602 ps
T931 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.4002426804 Jun 05 04:33:44 PM PDT 24 Jun 05 04:33:49 PM PDT 24 431251022 ps
T932 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.2554217367 Jun 05 04:33:33 PM PDT 24 Jun 05 04:33:35 PM PDT 24 13235193 ps
T136 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.1790182507 Jun 05 04:33:31 PM PDT 24 Jun 05 04:33:37 PM PDT 24 172203555 ps
T933 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.2478420087 Jun 05 04:33:27 PM PDT 24 Jun 05 04:33:30 PM PDT 24 121000144 ps
T934 /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.555008144 Jun 05 04:33:14 PM PDT 24 Jun 05 04:33:16 PM PDT 24 16329508 ps
T935 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.2269897805 Jun 05 04:33:33 PM PDT 24 Jun 05 04:33:36 PM PDT 24 182374373 ps
T936 /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.3252122986 Jun 05 04:33:31 PM PDT 24 Jun 05 04:33:33 PM PDT 24 32121309 ps
T937 /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.3720302379 Jun 05 04:33:35 PM PDT 24 Jun 05 04:33:37 PM PDT 24 70314915 ps
T938 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.2714267611 Jun 05 04:33:31 PM PDT 24 Jun 05 04:33:33 PM PDT 24 135449141 ps
T939 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.2453813835 Jun 05 04:33:39 PM PDT 24 Jun 05 04:33:40 PM PDT 24 101657714 ps
T940 /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.3159161806 Jun 05 04:33:20 PM PDT 24 Jun 05 04:33:23 PM PDT 24 511691546 ps
T140 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.1085434290 Jun 05 04:33:14 PM PDT 24 Jun 05 04:33:17 PM PDT 24 807071087 ps
T941 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.2042128547 Jun 05 04:33:40 PM PDT 24 Jun 05 04:33:44 PM PDT 24 143264092 ps
T942 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.2108776509 Jun 05 04:33:33 PM PDT 24 Jun 05 04:33:35 PM PDT 24 38347545 ps
T943 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.2674806475 Jun 05 04:33:45 PM PDT 24 Jun 05 04:33:48 PM PDT 24 60489665 ps
T944 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.2137744162 Jun 05 04:33:15 PM PDT 24 Jun 05 04:33:17 PM PDT 24 124195833 ps
T945 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.308102684 Jun 05 04:33:30 PM PDT 24 Jun 05 04:33:41 PM PDT 24 3738740963 ps
T141 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.1284163374 Jun 05 04:33:27 PM PDT 24 Jun 05 04:33:31 PM PDT 24 231301300 ps
T946 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.439779030 Jun 05 04:33:26 PM PDT 24 Jun 05 04:33:28 PM PDT 24 45763901 ps
T947 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.2473987506 Jun 05 04:33:25 PM PDT 24 Jun 05 04:33:28 PM PDT 24 161924544 ps
T948 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.2186627072 Jun 05 04:33:59 PM PDT 24 Jun 05 04:34:01 PM PDT 24 40556243 ps
T949 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3575090897 Jun 05 04:33:30 PM PDT 24 Jun 05 04:33:35 PM PDT 24 136986016 ps
T950 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.50309821 Jun 05 04:33:25 PM PDT 24 Jun 05 04:33:27 PM PDT 24 21501336 ps
T951 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2303164155 Jun 05 04:33:33 PM PDT 24 Jun 05 04:33:37 PM PDT 24 231227535 ps
T952 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.1852321954 Jun 05 04:33:45 PM PDT 24 Jun 05 04:33:52 PM PDT 24 169765488 ps
T953 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.1641105510 Jun 05 04:33:35 PM PDT 24 Jun 05 04:33:38 PM PDT 24 80673019 ps
T954 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2485247609 Jun 05 04:33:30 PM PDT 24 Jun 05 04:33:34 PM PDT 24 155233963 ps
T955 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.4195032384 Jun 05 04:33:30 PM PDT 24 Jun 05 04:33:33 PM PDT 24 64759775 ps
T956 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.261887216 Jun 05 04:33:44 PM PDT 24 Jun 05 04:33:47 PM PDT 24 12597715 ps
T957 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.3100860725 Jun 05 04:33:34 PM PDT 24 Jun 05 04:33:36 PM PDT 24 244317899 ps
T958 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.3944256464 Jun 05 04:33:29 PM PDT 24 Jun 05 04:33:33 PM PDT 24 1071146609 ps
T959 /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.1201790246 Jun 05 04:33:32 PM PDT 24 Jun 05 04:33:34 PM PDT 24 26374343 ps
T960 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.3265920040 Jun 05 04:33:41 PM PDT 24 Jun 05 04:33:45 PM PDT 24 38432927 ps
T961 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.1533259520 Jun 05 04:33:36 PM PDT 24 Jun 05 04:33:38 PM PDT 24 26763923 ps
T962 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.2690101477 Jun 05 04:33:37 PM PDT 24 Jun 05 04:33:39 PM PDT 24 382132791 ps
T963 /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.1029557157 Jun 05 04:33:28 PM PDT 24 Jun 05 04:33:31 PM PDT 24 182602827 ps
T964 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.2658380112 Jun 05 04:33:36 PM PDT 24 Jun 05 04:33:39 PM PDT 24 142935140 ps
T965 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.2304476536 Jun 05 04:33:45 PM PDT 24 Jun 05 04:33:48 PM PDT 24 17753512 ps
T966 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.110822879 Jun 05 04:33:33 PM PDT 24 Jun 05 04:33:35 PM PDT 24 36119749 ps
T967 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.236039999 Jun 05 04:33:34 PM PDT 24 Jun 05 04:33:36 PM PDT 24 33925284 ps
T968 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.2845982088 Jun 05 04:33:27 PM PDT 24 Jun 05 04:33:28 PM PDT 24 116320395 ps
T969 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.3637995536 Jun 05 04:33:22 PM PDT 24 Jun 05 04:33:24 PM PDT 24 154145691 ps
T970 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.2664081647 Jun 05 04:33:35 PM PDT 24 Jun 05 04:33:37 PM PDT 24 355928303 ps
T971 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.746160231 Jun 05 04:33:41 PM PDT 24 Jun 05 04:33:51 PM PDT 24 1453021716 ps
T972 /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.798681059 Jun 05 04:33:39 PM PDT 24 Jun 05 04:33:41 PM PDT 24 82471022 ps
T973 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.4138442637 Jun 05 04:33:32 PM PDT 24 Jun 05 04:33:35 PM PDT 24 33607674 ps
T181 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.3649220607 Jun 05 04:33:13 PM PDT 24 Jun 05 04:33:15 PM PDT 24 12745486 ps
T974 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.4246307108 Jun 05 04:33:29 PM PDT 24 Jun 05 04:33:32 PM PDT 24 175742666 ps
T975 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.3042200247 Jun 05 04:33:22 PM PDT 24 Jun 05 04:34:12 PM PDT 24 4016350460 ps
T976 /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.1788152590 Jun 05 04:33:36 PM PDT 24 Jun 05 04:33:38 PM PDT 24 24918356 ps
T977 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.231296719 Jun 05 04:33:14 PM PDT 24 Jun 05 04:33:18 PM PDT 24 190835410 ps
T978 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.4194434130 Jun 05 04:33:15 PM PDT 24 Jun 05 04:33:17 PM PDT 24 193653987 ps
T979 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.1956691589 Jun 05 04:33:35 PM PDT 24 Jun 05 04:33:40 PM PDT 24 419716030 ps
T182 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.2896876838 Jun 05 04:33:22 PM PDT 24 Jun 05 04:33:23 PM PDT 24 16109980 ps
T980 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.2517927278 Jun 05 04:33:42 PM PDT 24 Jun 05 04:33:46 PM PDT 24 28704015 ps
T981 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.3287384249 Jun 05 04:33:50 PM PDT 24 Jun 05 04:33:54 PM PDT 24 82806008 ps
T982 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.396451975 Jun 05 04:33:21 PM PDT 24 Jun 05 04:33:24 PM PDT 24 440626166 ps
T983 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.1135298003 Jun 05 04:33:18 PM PDT 24 Jun 05 04:33:20 PM PDT 24 43336442 ps
T984 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.938761978 Jun 05 04:33:22 PM PDT 24 Jun 05 04:33:27 PM PDT 24 139334970 ps
T985 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.2768287719 Jun 05 04:33:27 PM PDT 24 Jun 05 04:33:40 PM PDT 24 519612257 ps
T986 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.3479029739 Jun 05 04:33:49 PM PDT 24 Jun 05 04:34:04 PM PDT 24 2956944095 ps
T137 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.1499171744 Jun 05 04:33:21 PM PDT 24 Jun 05 04:33:24 PM PDT 24 209042527 ps
T987 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.2855766042 Jun 05 04:33:38 PM PDT 24 Jun 05 04:33:41 PM PDT 24 200359515 ps
T988 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.766279684 Jun 05 04:33:42 PM PDT 24 Jun 05 04:33:46 PM PDT 24 151380964 ps
T989 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.4083873676 Jun 05 04:33:38 PM PDT 24 Jun 05 04:33:42 PM PDT 24 302818878 ps
T990 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.3162737781 Jun 05 04:33:55 PM PDT 24 Jun 05 04:33:57 PM PDT 24 24287948 ps
T991 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.3648222715 Jun 05 04:33:25 PM PDT 24 Jun 05 04:33:33 PM PDT 24 626944106 ps
T146 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.2724245989 Jun 05 04:33:33 PM PDT 24 Jun 05 04:33:36 PM PDT 24 186017320 ps
T183 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.2050332926 Jun 05 04:33:13 PM PDT 24 Jun 05 04:33:15 PM PDT 24 18295013 ps
T992 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.225265332 Jun 05 04:33:13 PM PDT 24 Jun 05 04:33:16 PM PDT 24 144391504 ps
T993 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.2283846824 Jun 05 04:33:21 PM PDT 24 Jun 05 04:33:23 PM PDT 24 34350704 ps
T133 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.1810083503 Jun 05 04:33:28 PM PDT 24 Jun 05 04:33:31 PM PDT 24 63899998 ps
T994 /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.368343237 Jun 05 04:33:29 PM PDT 24 Jun 05 04:33:31 PM PDT 24 140398563 ps
T995 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.2847381448 Jun 05 04:33:50 PM PDT 24 Jun 05 04:33:55 PM PDT 24 459359110 ps
T996 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.2298877175 Jun 05 04:33:17 PM PDT 24 Jun 05 04:33:40 PM PDT 24 3571122827 ps
T997 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.1085254937 Jun 05 04:33:39 PM PDT 24 Jun 05 04:33:41 PM PDT 24 66377251 ps
T144 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.1498326114 Jun 05 04:33:32 PM PDT 24 Jun 05 04:33:37 PM PDT 24 1116983317 ps
T132 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.1702240017 Jun 05 04:33:41 PM PDT 24 Jun 05 04:33:45 PM PDT 24 282438756 ps
T998 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.3771634766 Jun 05 04:33:29 PM PDT 24 Jun 05 04:33:51 PM PDT 24 972795187 ps
T999 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.1123944252 Jun 05 04:33:31 PM PDT 24 Jun 05 04:33:34 PM PDT 24 216239971 ps
T135 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.3603437944 Jun 05 04:33:40 PM PDT 24 Jun 05 04:33:44 PM PDT 24 289913243 ps

Test location /workspace/coverage/default/30.lc_ctrl_stress_all_with_rand_reset.2875682715
Short name T6
Test name
Test status
Simulation time 240289945061 ps
CPU time 1056.51 seconds
Started Jun 05 05:59:40 PM PDT 24
Finished Jun 05 06:17:18 PM PDT 24
Peak memory 296652 kb
Host smart-3ec624ff-e3d3-4f6c-96d4-b6c91cba0d9c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2875682715 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_stress_all_with_rand_reset.2875682715
Directory /workspace/30.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.lc_ctrl_security_escalation.3393115681
Short name T3
Test name
Test status
Simulation time 1190525624 ps
CPU time 10.02 seconds
Started Jun 05 05:59:34 PM PDT 24
Finished Jun 05 05:59:44 PM PDT 24
Peak memory 218156 kb
Host smart-a9579511-2cdf-4edd-9916-972667f629ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393115681 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_security_escalation.3393115681
Directory /workspace/21.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_mubi.745922916
Short name T56
Test name
Test status
Simulation time 607821124 ps
CPU time 19.6 seconds
Started Jun 05 05:59:28 PM PDT 24
Finished Jun 05 05:59:48 PM PDT 24
Peak memory 219064 kb
Host smart-10289223-e31f-4735-9551-6000bc4c9c35
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745922916 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_mubi.745922916
Directory /workspace/19.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all_with_rand_reset.3381700778
Short name T37
Test name
Test status
Simulation time 42312524732 ps
CPU time 962.66 seconds
Started Jun 05 05:59:17 PM PDT 24
Finished Jun 05 06:15:21 PM PDT 24
Peak memory 513416 kb
Host smart-2913ed4f-15a0-413b-9ac4-6c7a8d8f5225
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3381700778 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_stress_all_with_rand_reset.3381700778
Directory /workspace/15.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.lc_ctrl_volatile_unlock_smoke.2653052231
Short name T2
Test name
Test status
Simulation time 23255299 ps
CPU time 0.91 seconds
Started Jun 05 05:59:52 PM PDT 24
Finished Jun 05 05:59:53 PM PDT 24
Peak memory 208612 kb
Host smart-0003bf32-4e74-4076-9ec9-4f4a9a0b202e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653052231 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_c
trl_volatile_unlock_smoke.2653052231
Directory /workspace/37.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.3158315026
Short name T115
Test name
Test status
Simulation time 78206719 ps
CPU time 3.53 seconds
Started Jun 05 04:33:37 PM PDT 24
Finished Jun 05 04:33:42 PM PDT 24
Peak memory 218132 kb
Host smart-820012ea-8500-48ee-8ce2-86ed6862dc90
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158315026 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_errors.3158315026
Directory /workspace/14.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_security_escalation.1325148018
Short name T198
Test name
Test status
Simulation time 1088606085 ps
CPU time 9.82 seconds
Started Jun 05 05:59:18 PM PDT 24
Finished Jun 05 05:59:28 PM PDT 24
Peak memory 218164 kb
Host smart-daa03c13-4a62-401c-a638-251610ec47e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325148018 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_security_escalation.1325148018
Directory /workspace/14.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_cm.303107186
Short name T48
Test name
Test status
Simulation time 205295898 ps
CPU time 37.62 seconds
Started Jun 05 05:58:31 PM PDT 24
Finished Jun 05 05:59:09 PM PDT 24
Peak memory 269232 kb
Host smart-9c0f6258-1d20-462f-9005-ba789fcb4001
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303107186 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_cm.303107186
Directory /workspace/1.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/20.lc_ctrl_jtag_access.3119866025
Short name T5
Test name
Test status
Simulation time 345659627 ps
CPU time 3.65 seconds
Started Jun 05 05:59:26 PM PDT 24
Finished Jun 05 05:59:31 PM PDT 24
Peak memory 216936 kb
Host smart-d91fe79b-34af-4be7-a108-f1e2b264b4ea
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119866025 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_jtag_access.3119866025
Directory /workspace/20.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.1132816385
Short name T117
Test name
Test status
Simulation time 285208831 ps
CPU time 3.52 seconds
Started Jun 05 04:33:31 PM PDT 24
Finished Jun 05 04:33:35 PM PDT 24
Peak memory 222960 kb
Host smart-91441c6c-0a60-4f43-b696-56c6fe81d5ac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132816385 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_intg_
err.1132816385
Directory /workspace/8.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_mux.1725204947
Short name T33
Test name
Test status
Simulation time 314264497 ps
CPU time 11.08 seconds
Started Jun 05 06:00:26 PM PDT 24
Finished Jun 05 06:00:38 PM PDT 24
Peak memory 218028 kb
Host smart-469599bf-e355-42c7-b4e2-cf3ebdfd1d17
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725204947 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_mux.
1725204947
Directory /workspace/44.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.784756657
Short name T148
Test name
Test status
Simulation time 439089065 ps
CPU time 2.37 seconds
Started Jun 05 04:33:37 PM PDT 24
Finished Jun 05 04:33:40 PM PDT 24
Peak memory 223332 kb
Host smart-de3a4f09-92a6-437a-8326-2acf3efca90c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784756
657 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.784756657
Directory /workspace/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/19.lc_ctrl_alert_test.2690696742
Short name T259
Test name
Test status
Simulation time 21720345 ps
CPU time 1.22 seconds
Started Jun 05 05:59:19 PM PDT 24
Finished Jun 05 05:59:21 PM PDT 24
Peak memory 208728 kb
Host smart-361c09ed-30c2-4ed5-a627-d93f4a3476c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690696742 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_alert_test.2690696742
Directory /workspace/19.lc_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.2142474
Short name T178
Test name
Test status
Simulation time 52260128 ps
CPU time 1.03 seconds
Started Jun 05 04:33:34 PM PDT 24
Finished Jun 05 04:33:35 PM PDT 24
Peak memory 209896 kb
Host smart-1e0d64e4-7489-4f2a-a6f3-37f97623195a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142474 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_aliasing.2142474
Directory /workspace/0.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/default/25.lc_ctrl_errors.1568071171
Short name T12
Test name
Test status
Simulation time 878576821 ps
CPU time 17.69 seconds
Started Jun 05 05:59:27 PM PDT 24
Finished Jun 05 05:59:45 PM PDT 24
Peak memory 218072 kb
Host smart-cc3ae749-7758-43e1-98b7-2eb68ba1457b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568071171 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_errors.1568071171
Directory /workspace/25.lc_ctrl_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_stress_all.972952208
Short name T172
Test name
Test status
Simulation time 7765081515 ps
CPU time 294.25 seconds
Started Jun 05 05:58:32 PM PDT 24
Finished Jun 05 06:03:27 PM PDT 24
Peak memory 274376 kb
Host smart-d289598a-c6ed-48c4-90c3-818443ecd652
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972952208 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.lc_ctrl_stress_all.972952208
Directory /workspace/4.lc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.1790182507
Short name T136
Test name
Test status
Simulation time 172203555 ps
CPU time 4.9 seconds
Started Jun 05 04:33:31 PM PDT 24
Finished Jun 05 04:33:37 PM PDT 24
Peak memory 218200 kb
Host smart-1119931e-e248-426c-8225-eac8cf969f98
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790182507 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_intg
_err.1790182507
Directory /workspace/10.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all_with_rand_reset.3703446032
Short name T40
Test name
Test status
Simulation time 20001967576 ps
CPU time 527.73 seconds
Started Jun 05 06:00:14 PM PDT 24
Finished Jun 05 06:09:02 PM PDT 24
Peak memory 496408 kb
Host smart-567e124b-864c-4ae9-b19f-c6ad901400c2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3703446032 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_stress_all_with_rand_reset.3703446032
Directory /workspace/46.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_failure.3398955556
Short name T113
Test name
Test status
Simulation time 1365947433 ps
CPU time 55.09 seconds
Started Jun 05 05:59:16 PM PDT 24
Finished Jun 05 06:00:11 PM PDT 24
Peak memory 269028 kb
Host smart-4549c0d2-8350-40a7-886b-b5317c631b65
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398955556 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jt
ag_state_failure.3398955556
Directory /workspace/11.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_mubi.1352353157
Short name T39
Test name
Test status
Simulation time 497146841 ps
CPU time 11.22 seconds
Started Jun 05 05:59:54 PM PDT 24
Finished Jun 05 06:00:06 PM PDT 24
Peak memory 218116 kb
Host smart-2072b4ea-d111-460b-be5a-250b775ca99c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352353157 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_mubi.1352353157
Directory /workspace/38.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.3603437944
Short name T135
Test name
Test status
Simulation time 289913243 ps
CPU time 2.53 seconds
Started Jun 05 04:33:40 PM PDT 24
Finished Jun 05 04:33:44 PM PDT 24
Peak memory 222828 kb
Host smart-0d9817af-7c56-4f9c-8df9-3f5aa0330a9c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603437944 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_intg
_err.3603437944
Directory /workspace/13.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.1284163374
Short name T141
Test name
Test status
Simulation time 231301300 ps
CPU time 2.99 seconds
Started Jun 05 04:33:27 PM PDT 24
Finished Jun 05 04:33:31 PM PDT 24
Peak memory 223004 kb
Host smart-889fd00c-9e50-49b5-919c-ae8b65ae7fcd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284163374 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_intg_
err.1284163374
Directory /workspace/4.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.4044842934
Short name T187
Test name
Test status
Simulation time 44712217 ps
CPU time 1.04 seconds
Started Jun 05 04:33:13 PM PDT 24
Finished Jun 05 04:33:15 PM PDT 24
Peak memory 209932 kb
Host smart-a09c03fe-cee1-4d12-aae3-cd0ac446dfff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044842934 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.lc_ctrl_jtag_same_csr_outstanding.4044842934
Directory /workspace/1.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all_with_rand_reset.1055741599
Short name T91
Test name
Test status
Simulation time 146942949063 ps
CPU time 1054.55 seconds
Started Jun 05 05:58:35 PM PDT 24
Finished Jun 05 06:16:11 PM PDT 24
Peak memory 422208 kb
Host smart-113b79fc-7001-4ebc-a442-1a7bd0eab04d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1055741599 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_stress_all_with_rand_reset.1055741599
Directory /workspace/0.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.lc_ctrl_claim_transition_if.335075089
Short name T27
Test name
Test status
Simulation time 13618198 ps
CPU time 0.91 seconds
Started Jun 05 05:58:33 PM PDT 24
Finished Jun 05 05:58:35 PM PDT 24
Peak memory 208596 kb
Host smart-88420457-0980-4500-bce8-9dc854de5c90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335075089 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_claim_transition_if.335075089
Directory /workspace/1.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_mux.1513442116
Short name T32
Test name
Test status
Simulation time 2992829425 ps
CPU time 9.8 seconds
Started Jun 05 05:59:59 PM PDT 24
Finished Jun 05 06:00:09 PM PDT 24
Peak memory 218108 kb
Host smart-31342fba-2597-4539-9677-cf1e0031b34a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513442116 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_mux.
1513442116
Directory /workspace/37.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.3589148530
Short name T893
Test name
Test status
Simulation time 86527025 ps
CPU time 2.96 seconds
Started Jun 05 04:33:31 PM PDT 24
Finished Jun 05 04:33:35 PM PDT 24
Peak memory 218120 kb
Host smart-662d93f2-e97a-45bd-bff9-50109f40e96a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589148530 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_errors.3589148530
Directory /workspace/11.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.1498326114
Short name T144
Test name
Test status
Simulation time 1116983317 ps
CPU time 3.49 seconds
Started Jun 05 04:33:32 PM PDT 24
Finished Jun 05 04:33:37 PM PDT 24
Peak memory 218432 kb
Host smart-a10854ea-8a1d-4423-8c3b-196e67daab5b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498326114 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_intg_
err.1498326114
Directory /workspace/3.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_claim_transition_if.1432156082
Short name T192
Test name
Test status
Simulation time 44040684 ps
CPU time 0.8 seconds
Started Jun 05 05:58:39 PM PDT 24
Finished Jun 05 05:58:41 PM PDT 24
Peak memory 208696 kb
Host smart-32d04f0e-e1c4-4abf-8dea-28e0e08ef34e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432156082 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_claim_transition_if.1432156082
Directory /workspace/0.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/3.lc_ctrl_claim_transition_if.19455442
Short name T193
Test name
Test status
Simulation time 33273127 ps
CPU time 0.8 seconds
Started Jun 05 05:58:44 PM PDT 24
Finished Jun 05 05:58:47 PM PDT 24
Peak memory 208708 kb
Host smart-103d0a72-42dc-42d5-a730-a16fb156b86c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19455442 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_claim_transition_if.19455442
Directory /workspace/3.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/7.lc_ctrl_claim_transition_if.2805489043
Short name T164
Test name
Test status
Simulation time 157466858 ps
CPU time 0.78 seconds
Started Jun 05 05:58:42 PM PDT 24
Finished Jun 05 05:58:44 PM PDT 24
Peak memory 208764 kb
Host smart-e997644c-b4ca-4e34-b3d1-ee3974d56b22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805489043 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_claim_transition_if.2805489043
Directory /workspace/7.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.2724245989
Short name T146
Test name
Test status
Simulation time 186017320 ps
CPU time 1.83 seconds
Started Jun 05 04:33:33 PM PDT 24
Finished Jun 05 04:33:36 PM PDT 24
Peak memory 222652 kb
Host smart-40e99dd6-5518-47c6-8a8a-9bce4c08c28e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724245989 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_intg
_err.2724245989
Directory /workspace/12.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.1390304985
Short name T143
Test name
Test status
Simulation time 70325898 ps
CPU time 1.92 seconds
Started Jun 05 04:33:41 PM PDT 24
Finished Jun 05 04:33:44 PM PDT 24
Peak memory 218132 kb
Host smart-28387bc6-2d32-4017-a488-d6525f492dfc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390304985 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_intg
_err.1390304985
Directory /workspace/16.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.1702240017
Short name T132
Test name
Test status
Simulation time 282438756 ps
CPU time 2.83 seconds
Started Jun 05 04:33:41 PM PDT 24
Finished Jun 05 04:33:45 PM PDT 24
Peak memory 222780 kb
Host smart-f0fa7965-9644-4fc0-a0a4-1e543cd89086
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702240017 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_intg
_err.1702240017
Directory /workspace/17.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.4284343904
Short name T145
Test name
Test status
Simulation time 385834961 ps
CPU time 3.06 seconds
Started Jun 05 04:33:53 PM PDT 24
Finished Jun 05 04:33:57 PM PDT 24
Peak memory 218148 kb
Host smart-7204d4cd-cf5a-4ed9-95c7-a4cb8d433c29
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284343904 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_intg
_err.4284343904
Directory /workspace/19.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.1499171744
Short name T137
Test name
Test status
Simulation time 209042527 ps
CPU time 2.76 seconds
Started Jun 05 04:33:21 PM PDT 24
Finished Jun 05 04:33:24 PM PDT 24
Peak memory 222772 kb
Host smart-3aedc902-f03b-43a5-8905-6b019e0310ef
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499171744 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_intg_
err.1499171744
Directory /workspace/2.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.2001852748
Short name T142
Test name
Test status
Simulation time 103855546 ps
CPU time 2.92 seconds
Started Jun 05 04:33:47 PM PDT 24
Finished Jun 05 04:33:52 PM PDT 24
Peak memory 222788 kb
Host smart-65ffb9af-e797-4bb0-b9b0-8fa46c5768bd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001852748 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_intg_
err.2001852748
Directory /workspace/7.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all_with_rand_reset.4157977746
Short name T43
Test name
Test status
Simulation time 29950865182 ps
CPU time 303.16 seconds
Started Jun 05 05:59:42 PM PDT 24
Finished Jun 05 06:04:46 PM PDT 24
Peak memory 356684 kb
Host smart-3956cadb-4d6f-4410-b2fa-c06ab356eca7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4157977746 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_stress_all_with_rand_reset.4157977746
Directory /workspace/32.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_smoke.851365336
Short name T15
Test name
Test status
Simulation time 1202561762 ps
CPU time 4.88 seconds
Started Jun 05 05:59:01 PM PDT 24
Finished Jun 05 05:59:06 PM PDT 24
Peak memory 217764 kb
Host smart-5329da70-4ba2-4505-9fae-41fd7d5eff6a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851365336 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_smoke.
851365336
Directory /workspace/11.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_post_trans.3493676327
Short name T67
Test name
Test status
Simulation time 146560282 ps
CPU time 6.35 seconds
Started Jun 05 05:58:36 PM PDT 24
Finished Jun 05 05:58:44 PM PDT 24
Peak memory 250416 kb
Host smart-89215ee5-739e-402c-909d-dd0b824651ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493676327 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_post_trans.3493676327
Directory /workspace/0.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.1464710852
Short name T870
Test name
Test status
Simulation time 126023630 ps
CPU time 2.62 seconds
Started Jun 05 04:33:24 PM PDT 24
Finished Jun 05 04:33:27 PM PDT 24
Peak memory 209164 kb
Host smart-b029bcb8-be53-478e-baad-aac954a5c46b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464710852 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_bit_bas
h.1464710852
Directory /workspace/0.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.3320768182
Short name T912
Test name
Test status
Simulation time 18150063 ps
CPU time 1.06 seconds
Started Jun 05 04:33:37 PM PDT 24
Finished Jun 05 04:33:39 PM PDT 24
Peak memory 210232 kb
Host smart-f655566f-5fca-4ffe-999e-363507729ed6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320768182 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_hw_rese
t.3320768182
Directory /workspace/0.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.767400305
Short name T918
Test name
Test status
Simulation time 29525423 ps
CPU time 1.7 seconds
Started Jun 05 04:33:10 PM PDT 24
Finished Jun 05 04:33:13 PM PDT 24
Peak memory 218156 kb
Host smart-4e174537-6df9-4eb1-97b0-c7955f91d469
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767400305 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 0.lc_ctrl_csr_mem_rw_with_rand_reset.767400305
Directory /workspace/0.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.3649220607
Short name T181
Test name
Test status
Simulation time 12745486 ps
CPU time 0.95 seconds
Started Jun 05 04:33:13 PM PDT 24
Finished Jun 05 04:33:15 PM PDT 24
Peak memory 209908 kb
Host smart-b5436eb0-a704-4a72-8714-70f36cc00867
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649220607 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_rw.3649220607
Directory /workspace/0.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.2742660358
Short name T908
Test name
Test status
Simulation time 94825126 ps
CPU time 1.84 seconds
Started Jun 05 04:33:14 PM PDT 24
Finished Jun 05 04:33:17 PM PDT 24
Peak memory 209624 kb
Host smart-62e8766d-b680-4bde-a648-ac300d776e55
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742660358 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.lc_ctrl_jtag_alert_test.2742660358
Directory /workspace/0.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.231296719
Short name T977
Test name
Test status
Simulation time 190835410 ps
CPU time 2.7 seconds
Started Jun 05 04:33:14 PM PDT 24
Finished Jun 05 04:33:18 PM PDT 24
Peak memory 209412 kb
Host smart-fb01d483-d12b-4d73-9abb-a2e6cf50b187
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231296719 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 0.lc_ctrl_jtag_csr_aliasing.231296719
Directory /workspace/0.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.3771634766
Short name T998
Test name
Test status
Simulation time 972795187 ps
CPU time 21.42 seconds
Started Jun 05 04:33:29 PM PDT 24
Finished Jun 05 04:33:51 PM PDT 24
Peak memory 209564 kb
Host smart-d8a4172e-8047-4e4c-91e9-bee5f27b4408
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771634766 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_bit_bash.3771634766
Directory /workspace/0.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.1725876080
Short name T151
Test name
Test status
Simulation time 558517946 ps
CPU time 2.06 seconds
Started Jun 05 04:33:26 PM PDT 24
Finished Jun 05 04:33:29 PM PDT 24
Peak memory 217960 kb
Host smart-8a462c3c-4416-45ed-8df1-ebefc2f14ede
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725876080 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_hw_reset.1725876080
Directory /workspace/0.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.2096869495
Short name T897
Test name
Test status
Simulation time 310320560 ps
CPU time 1.51 seconds
Started Jun 05 04:33:30 PM PDT 24
Finished Jun 05 04:33:32 PM PDT 24
Peak memory 209812 kb
Host smart-9842cd17-30a4-475a-a3ff-c9485b34767f
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096869495 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.lc_ctrl_jtag_csr_rw.2096869495
Directory /workspace/0.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.641912060
Short name T903
Test name
Test status
Simulation time 17007268 ps
CPU time 1 seconds
Started Jun 05 04:33:39 PM PDT 24
Finished Jun 05 04:33:40 PM PDT 24
Peak memory 210108 kb
Host smart-288957be-404f-45e7-a884-3b05c9b2fb1f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641912060 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.lc_ctrl_jtag_same_csr_outstanding.641912060
Directory /workspace/0.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.3720302379
Short name T937
Test name
Test status
Simulation time 70314915 ps
CPU time 0.99 seconds
Started Jun 05 04:33:35 PM PDT 24
Finished Jun 05 04:33:37 PM PDT 24
Peak memory 209952 kb
Host smart-69421857-59de-48d9-a314-42da0c5038cc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720302379 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl
_same_csr_outstanding.3720302379
Directory /workspace/0.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.2473987506
Short name T947
Test name
Test status
Simulation time 161924544 ps
CPU time 2.15 seconds
Started Jun 05 04:33:25 PM PDT 24
Finished Jun 05 04:33:28 PM PDT 24
Peak memory 218152 kb
Host smart-eb44fb13-684d-41ee-8645-aa7c1e79147d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473987506 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_errors.2473987506
Directory /workspace/0.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.1085434290
Short name T140
Test name
Test status
Simulation time 807071087 ps
CPU time 2.09 seconds
Started Jun 05 04:33:14 PM PDT 24
Finished Jun 05 04:33:17 PM PDT 24
Peak memory 222472 kb
Host smart-181e2e5a-3c00-4e39-838e-3e73f077465a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085434290 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_intg_
err.1085434290
Directory /workspace/0.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.613615410
Short name T131
Test name
Test status
Simulation time 88504100 ps
CPU time 1.1 seconds
Started Jun 05 04:33:29 PM PDT 24
Finished Jun 05 04:33:31 PM PDT 24
Peak memory 209900 kb
Host smart-941d12e5-abf0-4e7d-ae92-c2825d4d76dd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613615410 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_aliasing
.613615410
Directory /workspace/1.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.225265332
Short name T992
Test name
Test status
Simulation time 144391504 ps
CPU time 1.83 seconds
Started Jun 05 04:33:13 PM PDT 24
Finished Jun 05 04:33:16 PM PDT 24
Peak memory 209844 kb
Host smart-0cb137ec-c1ee-4aad-a0a3-6151d1aa7a36
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225265332 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_bit_bash
.225265332
Directory /workspace/1.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.2050332926
Short name T183
Test name
Test status
Simulation time 18295013 ps
CPU time 1.01 seconds
Started Jun 05 04:33:13 PM PDT 24
Finished Jun 05 04:33:15 PM PDT 24
Peak memory 210244 kb
Host smart-1fdda8f8-d7f8-46b9-ba21-d487684c713e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050332926 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_hw_rese
t.2050332926
Directory /workspace/1.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.3811268252
Short name T883
Test name
Test status
Simulation time 25655457 ps
CPU time 1.51 seconds
Started Jun 05 04:33:14 PM PDT 24
Finished Jun 05 04:33:17 PM PDT 24
Peak memory 218276 kb
Host smart-fd69b8f9-7c46-4587-a02e-44b4678ac5c7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811268252 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 1.lc_ctrl_csr_mem_rw_with_rand_reset.3811268252
Directory /workspace/1.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.2896876838
Short name T182
Test name
Test status
Simulation time 16109980 ps
CPU time 0.92 seconds
Started Jun 05 04:33:22 PM PDT 24
Finished Jun 05 04:33:23 PM PDT 24
Peak memory 209876 kb
Host smart-7c95c955-8191-4a3f-88ed-82838006bcb6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896876838 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_rw.2896876838
Directory /workspace/1.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.2845982088
Short name T968
Test name
Test status
Simulation time 116320395 ps
CPU time 0.97 seconds
Started Jun 05 04:33:27 PM PDT 24
Finished Jun 05 04:33:28 PM PDT 24
Peak memory 208996 kb
Host smart-6d85e46a-39f6-48fd-8438-c9d36bf14463
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845982088 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.lc_ctrl_jtag_alert_test.2845982088
Directory /workspace/1.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.965222706
Short name T150
Test name
Test status
Simulation time 1020031815 ps
CPU time 5.95 seconds
Started Jun 05 04:33:14 PM PDT 24
Finished Jun 05 04:33:21 PM PDT 24
Peak memory 216960 kb
Host smart-e048a874-23cf-40b2-870e-4fa20611f171
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965222706 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 1.lc_ctrl_jtag_csr_aliasing.965222706
Directory /workspace/1.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.1853646974
Short name T898
Test name
Test status
Simulation time 1831500168 ps
CPU time 11.37 seconds
Started Jun 05 04:33:11 PM PDT 24
Finished Jun 05 04:33:23 PM PDT 24
Peak memory 217072 kb
Host smart-ae963986-db68-400e-a03b-3b7b94dcd796
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853646974 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_bit_bash.1853646974
Directory /workspace/1.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.4246307108
Short name T974
Test name
Test status
Simulation time 175742666 ps
CPU time 1.99 seconds
Started Jun 05 04:33:29 PM PDT 24
Finished Jun 05 04:33:32 PM PDT 24
Peak memory 211192 kb
Host smart-539b3054-b243-4a38-b2a9-08614b087d13
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246307108 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_hw_reset.4246307108
Directory /workspace/1.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.981262353
Short name T888
Test name
Test status
Simulation time 164785630 ps
CPU time 3.12 seconds
Started Jun 05 04:33:12 PM PDT 24
Finished Jun 05 04:33:16 PM PDT 24
Peak memory 225024 kb
Host smart-9a19e69b-fd63-42dc-bda3-d1e2097431e1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981262
353 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.981262353
Directory /workspace/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.2137744162
Short name T944
Test name
Test status
Simulation time 124195833 ps
CPU time 1.28 seconds
Started Jun 05 04:33:15 PM PDT 24
Finished Jun 05 04:33:17 PM PDT 24
Peak memory 209788 kb
Host smart-9d7ebd3e-5fe0-4dfb-995e-187216ec7c82
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137744162 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.lc_ctrl_jtag_csr_rw.2137744162
Directory /workspace/1.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.555008144
Short name T934
Test name
Test status
Simulation time 16329508 ps
CPU time 1.22 seconds
Started Jun 05 04:33:14 PM PDT 24
Finished Jun 05 04:33:16 PM PDT 24
Peak memory 209964 kb
Host smart-a63e7952-e7c9-4bb6-9ffb-3805073ec5f7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555008144 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
same_csr_outstanding.555008144
Directory /workspace/1.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.2642415997
Short name T916
Test name
Test status
Simulation time 102450397 ps
CPU time 3.06 seconds
Started Jun 05 04:33:30 PM PDT 24
Finished Jun 05 04:33:33 PM PDT 24
Peak memory 218140 kb
Host smart-1da50aaa-f3b2-4c43-ade6-2757deafd4f1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642415997 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_errors.2642415997
Directory /workspace/1.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.3155780880
Short name T121
Test name
Test status
Simulation time 135180123 ps
CPU time 1.98 seconds
Started Jun 05 04:33:38 PM PDT 24
Finished Jun 05 04:33:41 PM PDT 24
Peak memory 221972 kb
Host smart-e7dab811-29db-4851-a22b-18ac02798841
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155780880 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_intg_
err.3155780880
Directory /workspace/1.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.2517927278
Short name T980
Test name
Test status
Simulation time 28704015 ps
CPU time 1.18 seconds
Started Jun 05 04:33:42 PM PDT 24
Finished Jun 05 04:33:46 PM PDT 24
Peak memory 218520 kb
Host smart-91e1076e-6189-4db1-8a33-3a3a2d9ae5a8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517927278 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 10.lc_ctrl_csr_mem_rw_with_rand_reset.2517927278
Directory /workspace/10.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.882680716
Short name T875
Test name
Test status
Simulation time 48006649 ps
CPU time 0.97 seconds
Started Jun 05 04:33:40 PM PDT 24
Finished Jun 05 04:33:43 PM PDT 24
Peak memory 209892 kb
Host smart-e90e0118-bfd1-4c2a-9689-31d0ba843239
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882680716 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_csr_rw.882680716
Directory /workspace/10.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.2801404832
Short name T184
Test name
Test status
Simulation time 18984403 ps
CPU time 1.19 seconds
Started Jun 05 04:33:40 PM PDT 24
Finished Jun 05 04:33:42 PM PDT 24
Peak memory 210056 kb
Host smart-6bf75ee6-7252-48d4-a5c3-e4dd13a142ea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801404832 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctr
l_same_csr_outstanding.2801404832
Directory /workspace/10.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.4173761904
Short name T915
Test name
Test status
Simulation time 107623076 ps
CPU time 2.86 seconds
Started Jun 05 04:33:43 PM PDT 24
Finished Jun 05 04:33:48 PM PDT 24
Peak memory 218152 kb
Host smart-b3a8ca72-f01e-451e-aee0-9cccee6ceff6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173761904 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_errors.4173761904
Directory /workspace/10.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.4195032384
Short name T955
Test name
Test status
Simulation time 64759775 ps
CPU time 1.49 seconds
Started Jun 05 04:33:30 PM PDT 24
Finished Jun 05 04:33:33 PM PDT 24
Peak memory 220460 kb
Host smart-74dcb732-c392-4c20-bf72-9c83a18b41bb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195032384 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 11.lc_ctrl_csr_mem_rw_with_rand_reset.4195032384
Directory /workspace/11.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.2304476536
Short name T965
Test name
Test status
Simulation time 17753512 ps
CPU time 0.82 seconds
Started Jun 05 04:33:45 PM PDT 24
Finished Jun 05 04:33:48 PM PDT 24
Peak memory 208924 kb
Host smart-9abf8600-73cc-4e82-8860-3ffc5a923d90
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304476536 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_csr_rw.2304476536
Directory /workspace/11.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.1201790246
Short name T959
Test name
Test status
Simulation time 26374343 ps
CPU time 1.02 seconds
Started Jun 05 04:33:32 PM PDT 24
Finished Jun 05 04:33:34 PM PDT 24
Peak memory 209960 kb
Host smart-f7336a8f-4265-4b9b-8e86-66c37b52a17c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201790246 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctr
l_same_csr_outstanding.1201790246
Directory /workspace/11.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.809607419
Short name T139
Test name
Test status
Simulation time 281997745 ps
CPU time 2.44 seconds
Started Jun 05 04:33:47 PM PDT 24
Finished Jun 05 04:33:56 PM PDT 24
Peak memory 218308 kb
Host smart-c347ac04-b96c-4096-848e-1384a605176c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809607419 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_intg_
err.809607419
Directory /workspace/11.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.3162737781
Short name T990
Test name
Test status
Simulation time 24287948 ps
CPU time 1.67 seconds
Started Jun 05 04:33:55 PM PDT 24
Finished Jun 05 04:33:57 PM PDT 24
Peak memory 220224 kb
Host smart-21436d3d-d746-41d2-9fd1-8bf0f9a9ac71
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162737781 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 12.lc_ctrl_csr_mem_rw_with_rand_reset.3162737781
Directory /workspace/12.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.1533259520
Short name T961
Test name
Test status
Simulation time 26763923 ps
CPU time 1.2 seconds
Started Jun 05 04:33:36 PM PDT 24
Finished Jun 05 04:33:38 PM PDT 24
Peak memory 209908 kb
Host smart-8b2cb8c0-cb46-4b69-82b6-b6a0102235fa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533259520 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_csr_rw.1533259520
Directory /workspace/12.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.3149491899
Short name T876
Test name
Test status
Simulation time 40168965 ps
CPU time 1.01 seconds
Started Jun 05 04:33:41 PM PDT 24
Finished Jun 05 04:33:43 PM PDT 24
Peak memory 210068 kb
Host smart-8296c910-7bd4-41c1-aeb8-8bffc2e2b30d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149491899 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctr
l_same_csr_outstanding.3149491899
Directory /workspace/12.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.2847381448
Short name T995
Test name
Test status
Simulation time 459359110 ps
CPU time 3.15 seconds
Started Jun 05 04:33:50 PM PDT 24
Finished Jun 05 04:33:55 PM PDT 24
Peak memory 218168 kb
Host smart-63252997-c24b-4333-b32f-0e0ef57f93de
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847381448 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_errors.2847381448
Directory /workspace/12.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.2674806475
Short name T943
Test name
Test status
Simulation time 60489665 ps
CPU time 1 seconds
Started Jun 05 04:33:45 PM PDT 24
Finished Jun 05 04:33:48 PM PDT 24
Peak memory 219344 kb
Host smart-ef07e367-5299-49ee-99f9-e56ff7072489
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674806475 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 13.lc_ctrl_csr_mem_rw_with_rand_reset.2674806475
Directory /workspace/13.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.3717432996
Short name T188
Test name
Test status
Simulation time 20075104 ps
CPU time 0.96 seconds
Started Jun 05 04:33:48 PM PDT 24
Finished Jun 05 04:33:51 PM PDT 24
Peak memory 209452 kb
Host smart-d86c3754-d83c-4828-ba86-67797726b080
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717432996 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_csr_rw.3717432996
Directory /workspace/13.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.2089819114
Short name T189
Test name
Test status
Simulation time 21796101 ps
CPU time 1.52 seconds
Started Jun 05 04:33:44 PM PDT 24
Finished Jun 05 04:33:48 PM PDT 24
Peak memory 218172 kb
Host smart-ffa65f62-19c9-4a84-8a70-e6df080e2818
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089819114 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctr
l_same_csr_outstanding.2089819114
Directory /workspace/13.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.94547718
Short name T889
Test name
Test status
Simulation time 2054533827 ps
CPU time 5.07 seconds
Started Jun 05 04:33:34 PM PDT 24
Finished Jun 05 04:33:40 PM PDT 24
Peak memory 218044 kb
Host smart-8ece6872-5d8f-4c0c-8600-63a9b3531989
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94547718 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_errors.94547718
Directory /workspace/13.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.1209981305
Short name T877
Test name
Test status
Simulation time 27120469 ps
CPU time 1.13 seconds
Started Jun 05 04:33:42 PM PDT 24
Finished Jun 05 04:33:45 PM PDT 24
Peak memory 218172 kb
Host smart-620a4600-5c87-40f4-b90a-c6818d84cd37
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209981305 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 14.lc_ctrl_csr_mem_rw_with_rand_reset.1209981305
Directory /workspace/14.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.2711631779
Short name T868
Test name
Test status
Simulation time 34609580 ps
CPU time 1 seconds
Started Jun 05 04:33:32 PM PDT 24
Finished Jun 05 04:33:34 PM PDT 24
Peak memory 209888 kb
Host smart-7f538aca-70e1-4f4c-9ce6-aaccc7700d7a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711631779 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_csr_rw.2711631779
Directory /workspace/14.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.2458373054
Short name T924
Test name
Test status
Simulation time 23320165 ps
CPU time 1.15 seconds
Started Jun 05 04:33:50 PM PDT 24
Finished Jun 05 04:33:52 PM PDT 24
Peak memory 217764 kb
Host smart-f7475706-a18b-49b3-b052-0b5ec4fcb173
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458373054 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctr
l_same_csr_outstanding.2458373054
Directory /workspace/14.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.2269897805
Short name T935
Test name
Test status
Simulation time 182374373 ps
CPU time 2.4 seconds
Started Jun 05 04:33:33 PM PDT 24
Finished Jun 05 04:33:36 PM PDT 24
Peak memory 217496 kb
Host smart-15fad5c5-b73c-486c-b471-9459c654c11a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269897805 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_intg
_err.2269897805
Directory /workspace/14.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.3287384249
Short name T981
Test name
Test status
Simulation time 82806008 ps
CPU time 1.61 seconds
Started Jun 05 04:33:50 PM PDT 24
Finished Jun 05 04:33:54 PM PDT 24
Peak memory 219912 kb
Host smart-617c77fc-df8f-4f97-b28e-358ec28bb1f8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287384249 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 15.lc_ctrl_csr_mem_rw_with_rand_reset.3287384249
Directory /workspace/15.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.3722967683
Short name T882
Test name
Test status
Simulation time 17534308 ps
CPU time 1.09 seconds
Started Jun 05 04:33:56 PM PDT 24
Finished Jun 05 04:33:57 PM PDT 24
Peak memory 209400 kb
Host smart-49f7b02d-dddf-448d-b3cf-368f150d4c60
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722967683 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_csr_rw.3722967683
Directory /workspace/15.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.2155417872
Short name T158
Test name
Test status
Simulation time 179557802 ps
CPU time 1.94 seconds
Started Jun 05 04:33:34 PM PDT 24
Finished Jun 05 04:33:37 PM PDT 24
Peak memory 212044 kb
Host smart-2b8c2684-2038-4c34-aafc-4bfb041e6e43
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155417872 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctr
l_same_csr_outstanding.2155417872
Directory /workspace/15.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.4151124594
Short name T895
Test name
Test status
Simulation time 57181074 ps
CPU time 1.92 seconds
Started Jun 05 04:33:35 PM PDT 24
Finished Jun 05 04:33:38 PM PDT 24
Peak memory 218464 kb
Host smart-76326b58-60f1-4bd3-b264-49372e915bd8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151124594 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_errors.4151124594
Directory /workspace/15.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.4002426804
Short name T931
Test name
Test status
Simulation time 431251022 ps
CPU time 2.53 seconds
Started Jun 05 04:33:44 PM PDT 24
Finished Jun 05 04:33:49 PM PDT 24
Peak memory 222880 kb
Host smart-4d91d6a9-e401-498a-8c75-20f9c39eeae7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002426804 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_intg
_err.4002426804
Directory /workspace/15.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.236039999
Short name T967
Test name
Test status
Simulation time 33925284 ps
CPU time 1.31 seconds
Started Jun 05 04:33:34 PM PDT 24
Finished Jun 05 04:33:36 PM PDT 24
Peak memory 223048 kb
Host smart-9abb836b-65fe-45a2-ad9d-3eb18df8d3d2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236039999 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 16.lc_ctrl_csr_mem_rw_with_rand_reset.236039999
Directory /workspace/16.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.1163099318
Short name T914
Test name
Test status
Simulation time 17972313 ps
CPU time 0.94 seconds
Started Jun 05 04:33:44 PM PDT 24
Finished Jun 05 04:33:47 PM PDT 24
Peak memory 209888 kb
Host smart-b3321391-2491-4999-a8a7-c9dbe293fcbc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163099318 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_csr_rw.1163099318
Directory /workspace/16.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.3539638664
Short name T884
Test name
Test status
Simulation time 140143303 ps
CPU time 1.38 seconds
Started Jun 05 04:33:47 PM PDT 24
Finished Jun 05 04:33:50 PM PDT 24
Peak memory 211888 kb
Host smart-e1533dde-a31b-483d-b0bc-e91c7a0a98a2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539638664 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctr
l_same_csr_outstanding.3539638664
Directory /workspace/16.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.3251974306
Short name T128
Test name
Test status
Simulation time 117205310 ps
CPU time 2.43 seconds
Started Jun 05 04:33:31 PM PDT 24
Finished Jun 05 04:33:35 PM PDT 24
Peak memory 219436 kb
Host smart-afa30bcd-9daa-4881-99a6-665a4dd58d6e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251974306 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_errors.3251974306
Directory /workspace/16.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.2475981375
Short name T160
Test name
Test status
Simulation time 20001744 ps
CPU time 1.38 seconds
Started Jun 05 04:33:40 PM PDT 24
Finished Jun 05 04:33:43 PM PDT 24
Peak memory 221648 kb
Host smart-0987e1e4-6650-4305-92f3-b341343f35a3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475981375 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 17.lc_ctrl_csr_mem_rw_with_rand_reset.2475981375
Directory /workspace/17.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.2062358480
Short name T921
Test name
Test status
Simulation time 34995285 ps
CPU time 1.1 seconds
Started Jun 05 04:33:36 PM PDT 24
Finished Jun 05 04:33:38 PM PDT 24
Peak memory 210056 kb
Host smart-15677175-b062-4145-aba0-85286cb11777
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062358480 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_csr_rw.2062358480
Directory /workspace/17.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.1788152590
Short name T976
Test name
Test status
Simulation time 24918356 ps
CPU time 1.42 seconds
Started Jun 05 04:33:36 PM PDT 24
Finished Jun 05 04:33:38 PM PDT 24
Peak memory 209960 kb
Host smart-d5d52a84-0581-46cd-a8fc-f490c85aa0c8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788152590 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctr
l_same_csr_outstanding.1788152590
Directory /workspace/17.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.1779147706
Short name T911
Test name
Test status
Simulation time 231763498 ps
CPU time 2.72 seconds
Started Jun 05 04:33:52 PM PDT 24
Finished Jun 05 04:33:55 PM PDT 24
Peak memory 218148 kb
Host smart-a8f5baab-c116-4f82-b4ff-194dcfe143c2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779147706 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_errors.1779147706
Directory /workspace/17.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.3265920040
Short name T960
Test name
Test status
Simulation time 38432927 ps
CPU time 1.35 seconds
Started Jun 05 04:33:41 PM PDT 24
Finished Jun 05 04:33:45 PM PDT 24
Peak memory 219432 kb
Host smart-912ea2f5-1544-4be0-b8fe-10aefe507a38
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265920040 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 18.lc_ctrl_csr_mem_rw_with_rand_reset.3265920040
Directory /workspace/18.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.261887216
Short name T956
Test name
Test status
Simulation time 12597715 ps
CPU time 0.84 seconds
Started Jun 05 04:33:44 PM PDT 24
Finished Jun 05 04:33:47 PM PDT 24
Peak memory 209660 kb
Host smart-7169869d-b99c-4484-904d-1ff691c9a7d8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261887216 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_csr_rw.261887216
Directory /workspace/18.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.1327018203
Short name T917
Test name
Test status
Simulation time 16838923 ps
CPU time 1.25 seconds
Started Jun 05 04:33:43 PM PDT 24
Finished Jun 05 04:33:47 PM PDT 24
Peak memory 210056 kb
Host smart-a606a982-8e94-4f3c-803f-b081e219d5f9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327018203 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctr
l_same_csr_outstanding.1327018203
Directory /workspace/18.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.1852321954
Short name T952
Test name
Test status
Simulation time 169765488 ps
CPU time 4.75 seconds
Started Jun 05 04:33:45 PM PDT 24
Finished Jun 05 04:33:52 PM PDT 24
Peak memory 218424 kb
Host smart-84df6473-97b5-49a4-9689-81641836d506
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852321954 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_errors.1852321954
Directory /workspace/18.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.42755817
Short name T134
Test name
Test status
Simulation time 232858872 ps
CPU time 3.43 seconds
Started Jun 05 04:33:40 PM PDT 24
Finished Jun 05 04:33:45 PM PDT 24
Peak memory 222404 kb
Host smart-9d5a44f7-6be8-49b7-8502-a3368ca69914
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42755817 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_intg_e
rr.42755817
Directory /workspace/18.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.766279684
Short name T988
Test name
Test status
Simulation time 151380964 ps
CPU time 1.69 seconds
Started Jun 05 04:33:42 PM PDT 24
Finished Jun 05 04:33:46 PM PDT 24
Peak memory 218908 kb
Host smart-8fd04242-5875-43a3-95da-e1424648ed73
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766279684 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 19.lc_ctrl_csr_mem_rw_with_rand_reset.766279684
Directory /workspace/19.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.2186627072
Short name T948
Test name
Test status
Simulation time 40556243 ps
CPU time 0.86 seconds
Started Jun 05 04:33:59 PM PDT 24
Finished Jun 05 04:34:01 PM PDT 24
Peak memory 209912 kb
Host smart-29fa9dd8-eb5f-4208-ab6b-e93f0794126d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186627072 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_csr_rw.2186627072
Directory /workspace/19.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.798681059
Short name T972
Test name
Test status
Simulation time 82471022 ps
CPU time 1.16 seconds
Started Jun 05 04:33:39 PM PDT 24
Finished Jun 05 04:33:41 PM PDT 24
Peak memory 209960 kb
Host smart-f62ad471-c719-4494-8dbf-1dbbbf15ecd1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798681059 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl
_same_csr_outstanding.798681059
Directory /workspace/19.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.3784147587
Short name T909
Test name
Test status
Simulation time 301942696 ps
CPU time 3.03 seconds
Started Jun 05 04:34:03 PM PDT 24
Finished Jun 05 04:34:08 PM PDT 24
Peak memory 218160 kb
Host smart-332e875b-0b15-4d2e-a102-d4d89b304f3e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784147587 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_errors.3784147587
Directory /workspace/19.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.1223072979
Short name T920
Test name
Test status
Simulation time 29797586 ps
CPU time 1.17 seconds
Started Jun 05 04:33:30 PM PDT 24
Finished Jun 05 04:33:32 PM PDT 24
Peak memory 209984 kb
Host smart-ca2c339c-448a-4062-8598-83ec02b9ce57
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223072979 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_aliasin
g.1223072979
Directory /workspace/2.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.3428409179
Short name T923
Test name
Test status
Simulation time 364610887 ps
CPU time 3.31 seconds
Started Jun 05 04:33:22 PM PDT 24
Finished Jun 05 04:33:26 PM PDT 24
Peak memory 209860 kb
Host smart-ff352d57-db1f-477f-a9c8-0f1c1accbb15
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428409179 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_bit_bas
h.3428409179
Directory /workspace/2.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.1135298003
Short name T983
Test name
Test status
Simulation time 43336442 ps
CPU time 1.02 seconds
Started Jun 05 04:33:18 PM PDT 24
Finished Jun 05 04:33:20 PM PDT 24
Peak memory 210312 kb
Host smart-5acaf30c-8a8f-465e-87d6-070c4c39faf6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135298003 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_hw_rese
t.1135298003
Directory /workspace/2.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.2664081647
Short name T970
Test name
Test status
Simulation time 355928303 ps
CPU time 1.18 seconds
Started Jun 05 04:33:35 PM PDT 24
Finished Jun 05 04:33:37 PM PDT 24
Peak memory 218296 kb
Host smart-e9fccd78-c172-4422-99a4-5d4f774c0b89
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664081647 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 2.lc_ctrl_csr_mem_rw_with_rand_reset.2664081647
Directory /workspace/2.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.2330033126
Short name T929
Test name
Test status
Simulation time 17714702 ps
CPU time 0.99 seconds
Started Jun 05 04:33:39 PM PDT 24
Finished Jun 05 04:33:41 PM PDT 24
Peak memory 209888 kb
Host smart-8efeebdc-1543-4788-8864-ac94774ec514
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330033126 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_rw.2330033126
Directory /workspace/2.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.396451975
Short name T982
Test name
Test status
Simulation time 440626166 ps
CPU time 2.61 seconds
Started Jun 05 04:33:21 PM PDT 24
Finished Jun 05 04:33:24 PM PDT 24
Peak memory 209084 kb
Host smart-fb7b8ffb-003d-43b8-81ee-76f3d21cce12
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396451975 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 2.lc_ctrl_jtag_alert_test.396451975
Directory /workspace/2.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.3554779750
Short name T147
Test name
Test status
Simulation time 1454589049 ps
CPU time 7.67 seconds
Started Jun 05 04:33:24 PM PDT 24
Finished Jun 05 04:33:33 PM PDT 24
Peak memory 209492 kb
Host smart-7474cae0-bb3b-4da4-bcdf-4dd8ca5fe45a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554779750 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_aliasing.3554779750
Directory /workspace/2.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.2298877175
Short name T996
Test name
Test status
Simulation time 3571122827 ps
CPU time 22.14 seconds
Started Jun 05 04:33:17 PM PDT 24
Finished Jun 05 04:33:40 PM PDT 24
Peak memory 209924 kb
Host smart-372e62bd-6723-483c-85c4-d8f10b0581a0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298877175 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_bit_bash.2298877175
Directory /workspace/2.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.2478420087
Short name T933
Test name
Test status
Simulation time 121000144 ps
CPU time 1.38 seconds
Started Jun 05 04:33:27 PM PDT 24
Finished Jun 05 04:33:30 PM PDT 24
Peak memory 211152 kb
Host smart-b46d6d77-db20-4100-9a62-eb3f942b8b3a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478420087 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_hw_reset.2478420087
Directory /workspace/2.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2378509801
Short name T129
Test name
Test status
Simulation time 145005810 ps
CPU time 2.27 seconds
Started Jun 05 04:33:17 PM PDT 24
Finished Jun 05 04:33:20 PM PDT 24
Peak memory 218224 kb
Host smart-c4976bf2-8563-4755-bd32-71b29a6d398f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237850
9801 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2378509801
Directory /workspace/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.2105882514
Short name T885
Test name
Test status
Simulation time 105020226 ps
CPU time 1.79 seconds
Started Jun 05 04:33:34 PM PDT 24
Finished Jun 05 04:33:37 PM PDT 24
Peak memory 209788 kb
Host smart-bad66ecc-59a1-4423-946e-f6f6b5379e09
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105882514 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.lc_ctrl_jtag_csr_rw.2105882514
Directory /workspace/2.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.4194434130
Short name T978
Test name
Test status
Simulation time 193653987 ps
CPU time 1.17 seconds
Started Jun 05 04:33:15 PM PDT 24
Finished Jun 05 04:33:17 PM PDT 24
Peak memory 209952 kb
Host smart-7c119924-d8e7-47ba-aee2-bb10a88d6ad0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194434130 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.lc_ctrl_jtag_same_csr_outstanding.4194434130
Directory /workspace/2.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.1029557157
Short name T963
Test name
Test status
Simulation time 182602827 ps
CPU time 1.85 seconds
Started Jun 05 04:33:28 PM PDT 24
Finished Jun 05 04:33:31 PM PDT 24
Peak memory 218176 kb
Host smart-f2d36000-7dff-4469-b1bf-0deac99da5e8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029557157 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl
_same_csr_outstanding.1029557157
Directory /workspace/2.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.3863269057
Short name T873
Test name
Test status
Simulation time 105510177 ps
CPU time 2.8 seconds
Started Jun 05 04:33:13 PM PDT 24
Finished Jun 05 04:33:17 PM PDT 24
Peak memory 218316 kb
Host smart-9defb619-9ce8-46dd-a8fa-b8c33b9d6cb0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863269057 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_errors.3863269057
Directory /workspace/2.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.3478431775
Short name T887
Test name
Test status
Simulation time 35680093 ps
CPU time 1.77 seconds
Started Jun 05 04:33:26 PM PDT 24
Finished Jun 05 04:33:28 PM PDT 24
Peak memory 217632 kb
Host smart-d0ea3231-7950-47ca-ad40-27456016ebab
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478431775 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_aliasin
g.3478431775
Directory /workspace/3.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.885508389
Short name T907
Test name
Test status
Simulation time 38254055 ps
CPU time 1.41 seconds
Started Jun 05 04:33:48 PM PDT 24
Finished Jun 05 04:33:51 PM PDT 24
Peak memory 217420 kb
Host smart-b07ada90-2634-4426-9367-844311dd7cf9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885508389 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_bit_bash
.885508389
Directory /workspace/3.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.3794354086
Short name T871
Test name
Test status
Simulation time 57949588 ps
CPU time 0.98 seconds
Started Jun 05 04:33:29 PM PDT 24
Finished Jun 05 04:33:31 PM PDT 24
Peak memory 210976 kb
Host smart-375bd694-5541-4122-8594-60cbefeb4f63
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794354086 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_hw_rese
t.3794354086
Directory /workspace/3.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.1517837317
Short name T900
Test name
Test status
Simulation time 18353883 ps
CPU time 1.49 seconds
Started Jun 05 04:33:26 PM PDT 24
Finished Jun 05 04:33:29 PM PDT 24
Peak memory 220916 kb
Host smart-909fdd99-630f-49f4-b372-6927b8fb6eee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517837317 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 3.lc_ctrl_csr_mem_rw_with_rand_reset.1517837317
Directory /workspace/3.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.4050036279
Short name T901
Test name
Test status
Simulation time 23225609 ps
CPU time 0.92 seconds
Started Jun 05 04:33:28 PM PDT 24
Finished Jun 05 04:33:30 PM PDT 24
Peak memory 209924 kb
Host smart-28eac061-ae38-404c-bac7-32b3fa200dbf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050036279 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_rw.4050036279
Directory /workspace/3.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.1657981243
Short name T891
Test name
Test status
Simulation time 26194524 ps
CPU time 0.92 seconds
Started Jun 05 04:33:27 PM PDT 24
Finished Jun 05 04:33:28 PM PDT 24
Peak memory 208960 kb
Host smart-87c08edf-e646-4105-bad0-1eae2382070e
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657981243 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.lc_ctrl_jtag_alert_test.1657981243
Directory /workspace/3.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.3648222715
Short name T991
Test name
Test status
Simulation time 626944106 ps
CPU time 7.89 seconds
Started Jun 05 04:33:25 PM PDT 24
Finished Jun 05 04:33:33 PM PDT 24
Peak memory 209696 kb
Host smart-e384b56f-e887-49b4-90b2-3525028e6a77
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648222715 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_aliasing.3648222715
Directory /workspace/3.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.3042200247
Short name T975
Test name
Test status
Simulation time 4016350460 ps
CPU time 49.66 seconds
Started Jun 05 04:33:22 PM PDT 24
Finished Jun 05 04:34:12 PM PDT 24
Peak memory 217400 kb
Host smart-531b0d0e-f704-4387-95f7-4d8e7beff67f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042200247 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_bit_bash.3042200247
Directory /workspace/3.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.4139258137
Short name T152
Test name
Test status
Simulation time 49199740 ps
CPU time 1.17 seconds
Started Jun 05 04:33:37 PM PDT 24
Finished Jun 05 04:33:39 PM PDT 24
Peak memory 211176 kb
Host smart-a511a7cc-9ff7-45e9-a6fa-ab64bf7ecccd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139258137 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_hw_reset.4139258137
Directory /workspace/3.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.938761978
Short name T984
Test name
Test status
Simulation time 139334970 ps
CPU time 3.88 seconds
Started Jun 05 04:33:22 PM PDT 24
Finished Jun 05 04:33:27 PM PDT 24
Peak memory 219220 kb
Host smart-0fac1d93-47f7-46a4-8cfe-e8d8fcef800b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938761
978 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.938761978
Directory /workspace/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.2855766042
Short name T987
Test name
Test status
Simulation time 200359515 ps
CPU time 2.46 seconds
Started Jun 05 04:33:38 PM PDT 24
Finished Jun 05 04:33:41 PM PDT 24
Peak memory 209804 kb
Host smart-2c1c54b5-2091-4fe1-b99d-b94d5925d1ae
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855766042 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.lc_ctrl_jtag_csr_rw.2855766042
Directory /workspace/3.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.2283846824
Short name T993
Test name
Test status
Simulation time 34350704 ps
CPU time 1.74 seconds
Started Jun 05 04:33:21 PM PDT 24
Finished Jun 05 04:33:23 PM PDT 24
Peak memory 209952 kb
Host smart-105d015b-991e-4bd3-8d1e-0005237d5b7b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283846824 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.lc_ctrl_jtag_same_csr_outstanding.2283846824
Directory /workspace/3.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.3159161806
Short name T940
Test name
Test status
Simulation time 511691546 ps
CPU time 2.03 seconds
Started Jun 05 04:33:20 PM PDT 24
Finished Jun 05 04:33:23 PM PDT 24
Peak memory 209956 kb
Host smart-ef992d87-3318-427f-9b16-5808ec50e7cb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159161806 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl
_same_csr_outstanding.3159161806
Directory /workspace/3.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.2891712506
Short name T120
Test name
Test status
Simulation time 103606351 ps
CPU time 3.07 seconds
Started Jun 05 04:33:26 PM PDT 24
Finished Jun 05 04:33:30 PM PDT 24
Peak memory 218112 kb
Host smart-a23ef031-83cb-4e60-a539-166c021ddf37
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891712506 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_errors.2891712506
Directory /workspace/3.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.314431225
Short name T179
Test name
Test status
Simulation time 19400445 ps
CPU time 1.56 seconds
Started Jun 05 04:33:25 PM PDT 24
Finished Jun 05 04:33:28 PM PDT 24
Peak memory 217572 kb
Host smart-af107c21-dd96-47c3-8307-b13a980cf529
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314431225 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_aliasing
.314431225
Directory /workspace/4.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.4138442637
Short name T973
Test name
Test status
Simulation time 33607674 ps
CPU time 1.2 seconds
Started Jun 05 04:33:32 PM PDT 24
Finished Jun 05 04:33:35 PM PDT 24
Peak memory 209132 kb
Host smart-be71e43f-e566-4277-8d40-d4f0bd09a293
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138442637 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_bit_bas
h.4138442637
Directory /workspace/4.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.352206150
Short name T130
Test name
Test status
Simulation time 46572982 ps
CPU time 0.97 seconds
Started Jun 05 04:33:22 PM PDT 24
Finished Jun 05 04:33:24 PM PDT 24
Peak memory 211024 kb
Host smart-5084677a-1486-4421-89e8-803a97e94c7b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352206150 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_hw_reset
.352206150
Directory /workspace/4.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.3574154837
Short name T119
Test name
Test status
Simulation time 52773375 ps
CPU time 1.72 seconds
Started Jun 05 04:33:23 PM PDT 24
Finished Jun 05 04:33:25 PM PDT 24
Peak memory 219440 kb
Host smart-24064ed7-d829-493b-9bf5-ef83ec9cfc72
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574154837 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 4.lc_ctrl_csr_mem_rw_with_rand_reset.3574154837
Directory /workspace/4.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.24231319
Short name T926
Test name
Test status
Simulation time 16490064 ps
CPU time 0.89 seconds
Started Jun 05 04:33:27 PM PDT 24
Finished Jun 05 04:33:29 PM PDT 24
Peak memory 209828 kb
Host smart-65d48a52-419b-45d6-b032-1cb8834bc352
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24231319 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_rw.24231319
Directory /workspace/4.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.50309821
Short name T950
Test name
Test status
Simulation time 21501336 ps
CPU time 0.99 seconds
Started Jun 05 04:33:25 PM PDT 24
Finished Jun 05 04:33:27 PM PDT 24
Peak memory 209776 kb
Host smart-196d34de-6943-4d9f-a400-2083e14a206a
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50309821 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_alert_test.50309821
Directory /workspace/4.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.2204846896
Short name T867
Test name
Test status
Simulation time 2043484413 ps
CPU time 13.02 seconds
Started Jun 05 04:33:24 PM PDT 24
Finished Jun 05 04:33:38 PM PDT 24
Peak memory 217640 kb
Host smart-4eae5150-7d98-4e82-bd74-f040f5cfa50d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204846896 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_aliasing.2204846896
Directory /workspace/4.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.1045922195
Short name T874
Test name
Test status
Simulation time 983393873 ps
CPU time 5.52 seconds
Started Jun 05 04:33:25 PM PDT 24
Finished Jun 05 04:33:31 PM PDT 24
Peak memory 209752 kb
Host smart-6c114549-4b4b-4a20-8ab1-664e92c70484
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045922195 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_bit_bash.1045922195
Directory /workspace/4.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.2589271598
Short name T881
Test name
Test status
Simulation time 517764737 ps
CPU time 1.89 seconds
Started Jun 05 04:33:25 PM PDT 24
Finished Jun 05 04:33:27 PM PDT 24
Peak memory 218016 kb
Host smart-c6b5f5b4-bd42-480b-b9b8-40bfabfd8306
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589271598 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_hw_reset.2589271598
Directory /workspace/4.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2485247609
Short name T954
Test name
Test status
Simulation time 155233963 ps
CPU time 3.29 seconds
Started Jun 05 04:33:30 PM PDT 24
Finished Jun 05 04:33:34 PM PDT 24
Peak memory 222912 kb
Host smart-cad8dffd-081f-447d-80ee-51f4fe668d6a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248524
7609 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2485247609
Directory /workspace/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.375217839
Short name T879
Test name
Test status
Simulation time 57531401 ps
CPU time 2.08 seconds
Started Jun 05 04:33:24 PM PDT 24
Finished Jun 05 04:33:27 PM PDT 24
Peak memory 209824 kb
Host smart-ead4126c-e902-4a81-bb1b-c20fc42ae7f9
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375217839 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.lc_ctrl_jtag_csr_rw.375217839
Directory /workspace/4.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.2323285182
Short name T890
Test name
Test status
Simulation time 52612677 ps
CPU time 0.97 seconds
Started Jun 05 04:33:38 PM PDT 24
Finished Jun 05 04:33:39 PM PDT 24
Peak memory 209948 kb
Host smart-3dc9a6ad-8099-41ab-ae50-f421cd6f2b8f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323285182 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.lc_ctrl_jtag_same_csr_outstanding.2323285182
Directory /workspace/4.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.959798649
Short name T880
Test name
Test status
Simulation time 81526784 ps
CPU time 1.07 seconds
Started Jun 05 04:33:39 PM PDT 24
Finished Jun 05 04:33:41 PM PDT 24
Peak memory 209984 kb
Host smart-47668272-cc87-4fd7-9f50-81965eaac6f6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959798649 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
same_csr_outstanding.959798649
Directory /workspace/4.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.3589547428
Short name T925
Test name
Test status
Simulation time 81404403 ps
CPU time 3.13 seconds
Started Jun 05 04:33:36 PM PDT 24
Finished Jun 05 04:33:40 PM PDT 24
Peak memory 218168 kb
Host smart-aba38a2f-955e-41c6-8f2b-6a8d1b14d4c8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589547428 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_errors.3589547428
Directory /workspace/4.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.439779030
Short name T946
Test name
Test status
Simulation time 45763901 ps
CPU time 1.51 seconds
Started Jun 05 04:33:26 PM PDT 24
Finished Jun 05 04:33:28 PM PDT 24
Peak memory 218412 kb
Host smart-37c7b7ed-4c03-4777-9cc3-f6b92c0a954e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439779030 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 5.lc_ctrl_csr_mem_rw_with_rand_reset.439779030
Directory /workspace/5.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.2672123933
Short name T180
Test name
Test status
Simulation time 29402752 ps
CPU time 1.13 seconds
Started Jun 05 04:33:27 PM PDT 24
Finished Jun 05 04:33:30 PM PDT 24
Peak memory 210108 kb
Host smart-4909ccf4-5d81-4527-9a61-f5faea347a22
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672123933 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_csr_rw.2672123933
Directory /workspace/5.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.1070552017
Short name T930
Test name
Test status
Simulation time 617236602 ps
CPU time 1.29 seconds
Started Jun 05 04:33:28 PM PDT 24
Finished Jun 05 04:33:31 PM PDT 24
Peak memory 209784 kb
Host smart-731085e0-bc7c-447f-9fb5-0cd5456639cb
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070552017 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.lc_ctrl_jtag_alert_test.1070552017
Directory /workspace/5.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.4083873676
Short name T989
Test name
Test status
Simulation time 302818878 ps
CPU time 3.3 seconds
Started Jun 05 04:33:38 PM PDT 24
Finished Jun 05 04:33:42 PM PDT 24
Peak memory 209480 kb
Host smart-693855a9-ac57-4ad1-b983-c8db3e5fee12
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083873676 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_aliasing.4083873676
Directory /workspace/5.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.746160231
Short name T971
Test name
Test status
Simulation time 1453021716 ps
CPU time 9.13 seconds
Started Jun 05 04:33:41 PM PDT 24
Finished Jun 05 04:33:51 PM PDT 24
Peak memory 209788 kb
Host smart-9df545dd-9b5f-4031-8896-7ce3ce2d1ad3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746160231 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 5.lc_ctrl_jtag_csr_bit_bash.746160231
Directory /workspace/5.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.3637995536
Short name T969
Test name
Test status
Simulation time 154145691 ps
CPU time 1.59 seconds
Started Jun 05 04:33:22 PM PDT 24
Finished Jun 05 04:33:24 PM PDT 24
Peak memory 211400 kb
Host smart-05589e05-945b-46dc-a894-2981954004d0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637995536 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_hw_reset.3637995536
Directory /workspace/5.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2389560463
Short name T905
Test name
Test status
Simulation time 1583074053 ps
CPU time 3.87 seconds
Started Jun 05 04:33:30 PM PDT 24
Finished Jun 05 04:33:35 PM PDT 24
Peak memory 218232 kb
Host smart-7d83b4dd-83a9-418d-be47-420a692eefdf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238956
0463 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2389560463
Directory /workspace/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.1641105510
Short name T953
Test name
Test status
Simulation time 80673019 ps
CPU time 1.58 seconds
Started Jun 05 04:33:35 PM PDT 24
Finished Jun 05 04:33:38 PM PDT 24
Peak memory 209760 kb
Host smart-46409fab-339d-4b6f-a0f2-9cefd2dfa045
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641105510 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.lc_ctrl_jtag_csr_rw.1641105510
Directory /workspace/5.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.503221476
Short name T185
Test name
Test status
Simulation time 22615407 ps
CPU time 1.07 seconds
Started Jun 05 04:33:26 PM PDT 24
Finished Jun 05 04:33:28 PM PDT 24
Peak memory 210208 kb
Host smart-45d5c45a-49e5-42bc-9552-d1f8423dc021
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503221476 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.lc_ctrl_jtag_same_csr_outstanding.503221476
Directory /workspace/5.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.3860932054
Short name T878
Test name
Test status
Simulation time 160957401 ps
CPU time 1.89 seconds
Started Jun 05 04:33:26 PM PDT 24
Finished Jun 05 04:33:28 PM PDT 24
Peak memory 212048 kb
Host smart-c430af09-aa39-4535-9446-15dd7d2b8d06
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860932054 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl
_same_csr_outstanding.3860932054
Directory /workspace/5.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.3700745806
Short name T116
Test name
Test status
Simulation time 53819505 ps
CPU time 2.14 seconds
Started Jun 05 04:33:38 PM PDT 24
Finished Jun 05 04:33:41 PM PDT 24
Peak memory 218580 kb
Host smart-253cd2d9-28b4-4154-a263-287146f536f3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700745806 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_errors.3700745806
Directory /workspace/5.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.3625749915
Short name T138
Test name
Test status
Simulation time 145946661 ps
CPU time 3.31 seconds
Started Jun 05 04:33:27 PM PDT 24
Finished Jun 05 04:33:32 PM PDT 24
Peak memory 218160 kb
Host smart-45b436a0-a560-4e93-abf7-b757726e8838
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625749915 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_intg_
err.3625749915
Directory /workspace/5.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.763870000
Short name T927
Test name
Test status
Simulation time 26334293 ps
CPU time 1.21 seconds
Started Jun 05 04:33:37 PM PDT 24
Finished Jun 05 04:33:38 PM PDT 24
Peak memory 218384 kb
Host smart-71f1db46-5b38-471a-b5f0-b81a2ba3d6c0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763870000 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 6.lc_ctrl_csr_mem_rw_with_rand_reset.763870000
Directory /workspace/6.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.2714267611
Short name T938
Test name
Test status
Simulation time 135449141 ps
CPU time 1.07 seconds
Started Jun 05 04:33:31 PM PDT 24
Finished Jun 05 04:33:33 PM PDT 24
Peak memory 209720 kb
Host smart-5c92bec9-198b-46a7-834f-f555701cf7d3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714267611 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_csr_rw.2714267611
Directory /workspace/6.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.2572195878
Short name T869
Test name
Test status
Simulation time 147745603 ps
CPU time 1.42 seconds
Started Jun 05 04:33:26 PM PDT 24
Finished Jun 05 04:33:29 PM PDT 24
Peak memory 209000 kb
Host smart-e4234a5b-0696-4adc-91dd-9849149804d3
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572195878 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.lc_ctrl_jtag_alert_test.2572195878
Directory /workspace/6.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.2768287719
Short name T985
Test name
Test status
Simulation time 519612257 ps
CPU time 11.5 seconds
Started Jun 05 04:33:27 PM PDT 24
Finished Jun 05 04:33:40 PM PDT 24
Peak memory 209588 kb
Host smart-3bf79a96-0efa-40eb-ad9e-33ad9e65638f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768287719 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_aliasing.2768287719
Directory /workspace/6.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.1956691589
Short name T979
Test name
Test status
Simulation time 419716030 ps
CPU time 4.68 seconds
Started Jun 05 04:33:35 PM PDT 24
Finished Jun 05 04:33:40 PM PDT 24
Peak memory 209744 kb
Host smart-3468df1c-21da-4084-b5bb-a06d992a4e5d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956691589 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_bit_bash.1956691589
Directory /workspace/6.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.3597604657
Short name T872
Test name
Test status
Simulation time 136279590 ps
CPU time 3.61 seconds
Started Jun 05 04:33:27 PM PDT 24
Finished Jun 05 04:33:31 PM PDT 24
Peak memory 211444 kb
Host smart-22969925-bfc6-40ab-978d-2169e648757a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597604657 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_hw_reset.3597604657
Directory /workspace/6.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2303164155
Short name T951
Test name
Test status
Simulation time 231227535 ps
CPU time 3.9 seconds
Started Jun 05 04:33:33 PM PDT 24
Finished Jun 05 04:33:37 PM PDT 24
Peak memory 219244 kb
Host smart-da349a70-be14-437e-bc02-15698bcb28b9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230316
4155 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2303164155
Directory /workspace/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.999921037
Short name T922
Test name
Test status
Simulation time 110439504 ps
CPU time 1.43 seconds
Started Jun 05 04:33:41 PM PDT 24
Finished Jun 05 04:33:44 PM PDT 24
Peak memory 209776 kb
Host smart-1f26bae9-4674-404f-9c7a-28710bd125d5
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999921037 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.lc_ctrl_jtag_csr_rw.999921037
Directory /workspace/6.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.3803210255
Short name T186
Test name
Test status
Simulation time 69702160 ps
CPU time 1.17 seconds
Started Jun 05 04:33:43 PM PDT 24
Finished Jun 05 04:33:46 PM PDT 24
Peak memory 209932 kb
Host smart-3dc38dae-cbfc-47bc-a06b-193f4ac17f3b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803210255 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.lc_ctrl_jtag_same_csr_outstanding.3803210255
Directory /workspace/6.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.2531400181
Short name T886
Test name
Test status
Simulation time 54403767 ps
CPU time 0.91 seconds
Started Jun 05 04:34:10 PM PDT 24
Finished Jun 05 04:34:12 PM PDT 24
Peak memory 209572 kb
Host smart-4b1afe7e-8f09-4527-a1ad-0f520fdd85f0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531400181 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl
_same_csr_outstanding.2531400181
Directory /workspace/6.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.2042128547
Short name T941
Test name
Test status
Simulation time 143264092 ps
CPU time 3.08 seconds
Started Jun 05 04:33:40 PM PDT 24
Finished Jun 05 04:33:44 PM PDT 24
Peak memory 218152 kb
Host smart-9862a21a-6acb-494a-a72f-df889df13658
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042128547 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_errors.2042128547
Directory /workspace/6.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.1810083503
Short name T133
Test name
Test status
Simulation time 63899998 ps
CPU time 2.14 seconds
Started Jun 05 04:33:28 PM PDT 24
Finished Jun 05 04:33:31 PM PDT 24
Peak memory 222396 kb
Host smart-3551ec62-6eaa-450a-ac40-ccb5cf3f11ff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810083503 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_intg_
err.1810083503
Directory /workspace/6.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.1123944252
Short name T999
Test name
Test status
Simulation time 216239971 ps
CPU time 1.67 seconds
Started Jun 05 04:33:31 PM PDT 24
Finished Jun 05 04:33:34 PM PDT 24
Peak memory 219972 kb
Host smart-d43118b1-96fb-4548-8f0f-a07f5dba8625
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123944252 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 7.lc_ctrl_csr_mem_rw_with_rand_reset.1123944252
Directory /workspace/7.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.2108776509
Short name T942
Test name
Test status
Simulation time 38347545 ps
CPU time 0.9 seconds
Started Jun 05 04:33:33 PM PDT 24
Finished Jun 05 04:33:35 PM PDT 24
Peak memory 209888 kb
Host smart-84392e19-0f65-459e-8211-5e19edaf2941
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108776509 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_csr_rw.2108776509
Directory /workspace/7.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.2453813835
Short name T939
Test name
Test status
Simulation time 101657714 ps
CPU time 0.97 seconds
Started Jun 05 04:33:39 PM PDT 24
Finished Jun 05 04:33:40 PM PDT 24
Peak memory 209980 kb
Host smart-ad5edfb4-891e-40e1-a5f8-96d8e8edfd12
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453813835 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.lc_ctrl_jtag_alert_test.2453813835
Directory /workspace/7.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.1022682520
Short name T904
Test name
Test status
Simulation time 2388742051 ps
CPU time 11.11 seconds
Started Jun 05 04:33:31 PM PDT 24
Finished Jun 05 04:33:44 PM PDT 24
Peak memory 209716 kb
Host smart-eb81ff86-2824-4b98-8b40-f56920945950
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022682520 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_aliasing.1022682520
Directory /workspace/7.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.308102684
Short name T945
Test name
Test status
Simulation time 3738740963 ps
CPU time 10.58 seconds
Started Jun 05 04:33:30 PM PDT 24
Finished Jun 05 04:33:41 PM PDT 24
Peak memory 209888 kb
Host smart-6ed7342d-f93e-4ef6-819e-29fa4c0c9099
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308102684 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 7.lc_ctrl_jtag_csr_bit_bash.308102684
Directory /workspace/7.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.2663408807
Short name T906
Test name
Test status
Simulation time 1007420769 ps
CPU time 6.05 seconds
Started Jun 05 04:33:31 PM PDT 24
Finished Jun 05 04:33:38 PM PDT 24
Peak memory 211468 kb
Host smart-a70fbd04-ea02-44a4-a187-9d29ce2a728d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663408807 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_hw_reset.2663408807
Directory /workspace/7.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3575090897
Short name T949
Test name
Test status
Simulation time 136986016 ps
CPU time 4.28 seconds
Started Jun 05 04:33:30 PM PDT 24
Finished Jun 05 04:33:35 PM PDT 24
Peak memory 223752 kb
Host smart-683bf8af-065f-47f6-a1b4-d35dff2bef91
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357509
0897 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3575090897
Directory /workspace/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.3100860725
Short name T957
Test name
Test status
Simulation time 244317899 ps
CPU time 1.21 seconds
Started Jun 05 04:33:34 PM PDT 24
Finished Jun 05 04:33:36 PM PDT 24
Peak memory 209788 kb
Host smart-cdd2be5e-5960-45f5-81e2-468562d24ed4
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100860725 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.lc_ctrl_jtag_csr_rw.3100860725
Directory /workspace/7.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.1729503596
Short name T913
Test name
Test status
Simulation time 200291283 ps
CPU time 2.09 seconds
Started Jun 05 04:33:42 PM PDT 24
Finished Jun 05 04:33:47 PM PDT 24
Peak memory 209952 kb
Host smart-0eee6239-16bb-4aa8-a419-c0de00e96287
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729503596 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.lc_ctrl_jtag_same_csr_outstanding.1729503596
Directory /workspace/7.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.368343237
Short name T994
Test name
Test status
Simulation time 140398563 ps
CPU time 1.4 seconds
Started Jun 05 04:33:29 PM PDT 24
Finished Jun 05 04:33:31 PM PDT 24
Peak memory 218132 kb
Host smart-ba571fef-6ebe-4a05-8194-9ac89a1e84cb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368343237 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
same_csr_outstanding.368343237
Directory /workspace/7.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.1989226790
Short name T892
Test name
Test status
Simulation time 508400797 ps
CPU time 3.61 seconds
Started Jun 05 04:33:41 PM PDT 24
Finished Jun 05 04:33:46 PM PDT 24
Peak memory 218028 kb
Host smart-bfb2973c-fc7a-4219-bbca-03b2af413d75
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989226790 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_errors.1989226790
Directory /workspace/7.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.2625272256
Short name T157
Test name
Test status
Simulation time 89535018 ps
CPU time 1.15 seconds
Started Jun 05 04:33:38 PM PDT 24
Finished Jun 05 04:33:40 PM PDT 24
Peak memory 218212 kb
Host smart-f34c8d52-e59a-4880-92c2-a7916d6cf2b9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625272256 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 8.lc_ctrl_csr_mem_rw_with_rand_reset.2625272256
Directory /workspace/8.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.1827707766
Short name T902
Test name
Test status
Simulation time 38277756 ps
CPU time 0.96 seconds
Started Jun 05 04:33:43 PM PDT 24
Finished Jun 05 04:33:46 PM PDT 24
Peak memory 209644 kb
Host smart-f6213c72-04b8-40ba-a1d0-dece1e858ce2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827707766 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_csr_rw.1827707766
Directory /workspace/8.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.2189019985
Short name T919
Test name
Test status
Simulation time 130464423 ps
CPU time 1.43 seconds
Started Jun 05 04:33:46 PM PDT 24
Finished Jun 05 04:33:49 PM PDT 24
Peak memory 208996 kb
Host smart-ff469e56-da02-4efe-a9b8-6f37569a0b4b
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189019985 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.lc_ctrl_jtag_alert_test.2189019985
Directory /workspace/8.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.2598554630
Short name T928
Test name
Test status
Simulation time 1083802720 ps
CPU time 8.68 seconds
Started Jun 05 04:33:51 PM PDT 24
Finished Jun 05 04:34:01 PM PDT 24
Peak memory 209412 kb
Host smart-5b8bc9c3-d17e-46c3-b62a-56e1ba2b481c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598554630 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_aliasing.2598554630
Directory /workspace/8.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.3610737936
Short name T910
Test name
Test status
Simulation time 2477818377 ps
CPU time 18.61 seconds
Started Jun 05 04:33:30 PM PDT 24
Finished Jun 05 04:33:50 PM PDT 24
Peak memory 209748 kb
Host smart-b118601a-8961-461c-873a-a29761027e77
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610737936 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_bit_bash.3610737936
Directory /workspace/8.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.2271835570
Short name T866
Test name
Test status
Simulation time 423416313 ps
CPU time 1.83 seconds
Started Jun 05 04:33:33 PM PDT 24
Finished Jun 05 04:33:36 PM PDT 24
Peak memory 210644 kb
Host smart-b79b7e94-e3bb-45af-889c-a9f3c91c2a41
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271835570 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_hw_reset.2271835570
Directory /workspace/8.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.814367065
Short name T894
Test name
Test status
Simulation time 92979102 ps
CPU time 2.04 seconds
Started Jun 05 04:33:39 PM PDT 24
Finished Jun 05 04:33:42 PM PDT 24
Peak memory 223336 kb
Host smart-5afc2387-1cba-4171-9f5c-c33458795636
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814367
065 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.814367065
Directory /workspace/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.2690101477
Short name T962
Test name
Test status
Simulation time 382132791 ps
CPU time 1.8 seconds
Started Jun 05 04:33:37 PM PDT 24
Finished Jun 05 04:33:39 PM PDT 24
Peak memory 209836 kb
Host smart-10c4e811-16b8-4fdf-9289-8600834a5fc8
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690101477 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.lc_ctrl_jtag_csr_rw.2690101477
Directory /workspace/8.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.565881722
Short name T156
Test name
Test status
Simulation time 120453280 ps
CPU time 1.21 seconds
Started Jun 05 04:33:41 PM PDT 24
Finished Jun 05 04:33:44 PM PDT 24
Peak memory 209960 kb
Host smart-a0519bea-65bd-4743-9f9e-5ea2aba0dc11
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565881722 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.lc_ctrl_jtag_same_csr_outstanding.565881722
Directory /workspace/8.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.3252122986
Short name T936
Test name
Test status
Simulation time 32121309 ps
CPU time 1.23 seconds
Started Jun 05 04:33:31 PM PDT 24
Finished Jun 05 04:33:33 PM PDT 24
Peak memory 210048 kb
Host smart-1d70acc7-18bf-4576-89c7-c74f0543adbb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252122986 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl
_same_csr_outstanding.3252122986
Directory /workspace/8.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.1978053352
Short name T899
Test name
Test status
Simulation time 149527955 ps
CPU time 2.29 seconds
Started Jun 05 04:33:41 PM PDT 24
Finished Jun 05 04:33:45 PM PDT 24
Peak memory 218236 kb
Host smart-0e077fd6-7fa4-4bf4-a69b-d1f4730c1248
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978053352 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_errors.1978053352
Directory /workspace/8.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.1085254937
Short name T997
Test name
Test status
Simulation time 66377251 ps
CPU time 1.71 seconds
Started Jun 05 04:33:39 PM PDT 24
Finished Jun 05 04:33:41 PM PDT 24
Peak memory 219440 kb
Host smart-20e0a270-b4bf-44b7-a476-daa5797ee0f7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085254937 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 9.lc_ctrl_csr_mem_rw_with_rand_reset.1085254937
Directory /workspace/9.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.2554217367
Short name T932
Test name
Test status
Simulation time 13235193 ps
CPU time 1.04 seconds
Started Jun 05 04:33:33 PM PDT 24
Finished Jun 05 04:33:35 PM PDT 24
Peak memory 209600 kb
Host smart-a93fb34a-7dc0-4bfb-b291-57e2d7bc8d25
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554217367 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_csr_rw.2554217367
Directory /workspace/9.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.2658380112
Short name T964
Test name
Test status
Simulation time 142935140 ps
CPU time 2.34 seconds
Started Jun 05 04:33:36 PM PDT 24
Finished Jun 05 04:33:39 PM PDT 24
Peak memory 209796 kb
Host smart-da39aec3-e1bd-47cf-a03d-23e7484bb8da
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658380112 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.lc_ctrl_jtag_alert_test.2658380112
Directory /workspace/9.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.2149014717
Short name T896
Test name
Test status
Simulation time 8187889665 ps
CPU time 9.12 seconds
Started Jun 05 04:33:32 PM PDT 24
Finished Jun 05 04:33:42 PM PDT 24
Peak memory 209912 kb
Host smart-be006615-ae3a-476c-9a09-30d74941a3bd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149014717 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_aliasing.2149014717
Directory /workspace/9.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.3479029739
Short name T986
Test name
Test status
Simulation time 2956944095 ps
CPU time 14.11 seconds
Started Jun 05 04:33:49 PM PDT 24
Finished Jun 05 04:34:04 PM PDT 24
Peak memory 209824 kb
Host smart-2ea6ff47-5546-4aa3-bda8-4a76c6315f99
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479029739 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_bit_bash.3479029739
Directory /workspace/9.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.3944256464
Short name T958
Test name
Test status
Simulation time 1071146609 ps
CPU time 3.15 seconds
Started Jun 05 04:33:29 PM PDT 24
Finished Jun 05 04:33:33 PM PDT 24
Peak memory 211392 kb
Host smart-25cea3f2-0841-4d07-9ef8-1a0269d5052c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944256464 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_hw_reset.3944256464
Directory /workspace/9.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1153804270
Short name T149
Test name
Test status
Simulation time 1865097510 ps
CPU time 2.11 seconds
Started Jun 05 04:33:51 PM PDT 24
Finished Jun 05 04:33:54 PM PDT 24
Peak memory 218304 kb
Host smart-356a206e-d0e2-417d-8370-7d0fac7ab470
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115380
4270 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1153804270
Directory /workspace/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.110822879
Short name T966
Test name
Test status
Simulation time 36119749 ps
CPU time 1.54 seconds
Started Jun 05 04:33:33 PM PDT 24
Finished Jun 05 04:33:35 PM PDT 24
Peak memory 217284 kb
Host smart-c159afac-931a-4cc0-9938-e430791911c6
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110822879 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.lc_ctrl_jtag_csr_rw.110822879
Directory /workspace/9.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.2437746398
Short name T123
Test name
Test status
Simulation time 140635675 ps
CPU time 1.77 seconds
Started Jun 05 04:33:30 PM PDT 24
Finished Jun 05 04:33:33 PM PDT 24
Peak memory 209828 kb
Host smart-d9fab647-7e79-470d-b892-772733c0c9d1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437746398 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.lc_ctrl_jtag_same_csr_outstanding.2437746398
Directory /workspace/9.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.2044150699
Short name T124
Test name
Test status
Simulation time 42204390 ps
CPU time 2 seconds
Started Jun 05 04:33:30 PM PDT 24
Finished Jun 05 04:33:33 PM PDT 24
Peak memory 209948 kb
Host smart-8e5cc098-4d5b-43bc-8f76-1e0fabba7dec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044150699 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl
_same_csr_outstanding.2044150699
Directory /workspace/9.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.802603088
Short name T127
Test name
Test status
Simulation time 214893266 ps
CPU time 3.15 seconds
Started Jun 05 04:33:31 PM PDT 24
Finished Jun 05 04:33:35 PM PDT 24
Peak memory 218156 kb
Host smart-65e229b0-d59b-412d-b57a-af06c18f01d2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802603088 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_errors.802603088
Directory /workspace/9.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.3391794149
Short name T122
Test name
Test status
Simulation time 212311617 ps
CPU time 2.53 seconds
Started Jun 05 04:33:45 PM PDT 24
Finished Jun 05 04:33:50 PM PDT 24
Peak memory 218348 kb
Host smart-7cba3166-6ad8-4632-933d-29ba6c58035e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391794149 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_intg_
err.3391794149
Directory /workspace/9.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_alert_test.13105290
Short name T853
Test name
Test status
Simulation time 15967249 ps
CPU time 0.9 seconds
Started Jun 05 05:58:31 PM PDT 24
Finished Jun 05 05:58:32 PM PDT 24
Peak memory 209536 kb
Host smart-0bdd1fc4-42ac-4841-921d-431a3bb55794
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13105290 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_alert_test.13105290
Directory /workspace/0.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.lc_ctrl_errors.2781808613
Short name T625
Test name
Test status
Simulation time 2786638419 ps
CPU time 9.34 seconds
Started Jun 05 05:58:33 PM PDT 24
Finished Jun 05 05:58:43 PM PDT 24
Peak memory 217692 kb
Host smart-85b129fd-4f32-4a2f-8ac2-5d89d7b78956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781808613 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_errors.2781808613
Directory /workspace/0.lc_ctrl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_access.3945427489
Short name T21
Test name
Test status
Simulation time 945896810 ps
CPU time 2.36 seconds
Started Jun 05 05:58:45 PM PDT 24
Finished Jun 05 05:58:49 PM PDT 24
Peak memory 216884 kb
Host smart-1fd0577a-e3b0-4bfe-86a3-de239e6ae28a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945427489 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_access.3945427489
Directory /workspace/0.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_errors.3413868614
Short name T437
Test name
Test status
Simulation time 12529290079 ps
CPU time 33.24 seconds
Started Jun 05 05:58:33 PM PDT 24
Finished Jun 05 05:59:07 PM PDT 24
Peak memory 218728 kb
Host smart-685b501e-8cd2-49be-b183-65acf5e5acc3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413868614 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_er
rors.3413868614
Directory /workspace/0.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_priority.1436809705
Short name T786
Test name
Test status
Simulation time 157306085 ps
CPU time 4.28 seconds
Started Jun 05 05:58:38 PM PDT 24
Finished Jun 05 05:58:44 PM PDT 24
Peak memory 217108 kb
Host smart-74e15304-7fb6-4707-b6ad-a2493e046598
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436809705 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_priority.1
436809705
Directory /workspace/0.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_prog_failure.3338656239
Short name T265
Test name
Test status
Simulation time 412855342 ps
CPU time 5.7 seconds
Started Jun 05 05:58:33 PM PDT 24
Finished Jun 05 05:58:40 PM PDT 24
Peak memory 217960 kb
Host smart-3a5f2857-052d-4f94-b79e-9e058a806697
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338656239 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag
_prog_failure.3338656239
Directory /workspace/0.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_regwen_during_op.2669749603
Short name T320
Test name
Test status
Simulation time 1891598405 ps
CPU time 14 seconds
Started Jun 05 05:58:36 PM PDT 24
Finished Jun 05 05:58:51 PM PDT 24
Peak memory 217760 kb
Host smart-172a4704-07bc-4c1f-8f40-9f80ede034ac
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669749603 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_regwen_during_op.2669749603
Directory /workspace/0.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_smoke.1390361036
Short name T428
Test name
Test status
Simulation time 5331250221 ps
CPU time 5.42 seconds
Started Jun 05 05:58:31 PM PDT 24
Finished Jun 05 05:58:37 PM PDT 24
Peak memory 217784 kb
Host smart-6ff5d1e2-5fe3-4488-b82d-6c4f2ba94984
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390361036 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_smoke.
1390361036
Directory /workspace/0.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_failure.3435828668
Short name T88
Test name
Test status
Simulation time 1596311682 ps
CPU time 37.41 seconds
Started Jun 05 05:58:32 PM PDT 24
Finished Jun 05 05:59:11 PM PDT 24
Peak memory 267332 kb
Host smart-d1d33d7d-5272-4601-a082-1011079b1dfe
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435828668 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jta
g_state_failure.3435828668
Directory /workspace/0.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_post_trans.1095376972
Short name T535
Test name
Test status
Simulation time 1033204821 ps
CPU time 13.88 seconds
Started Jun 05 05:58:36 PM PDT 24
Finished Jun 05 05:58:51 PM PDT 24
Peak memory 250944 kb
Host smart-2555cbc9-0fb0-4f1b-9eff-a0a259df7f9e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095376972 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_state_post_trans.1095376972
Directory /workspace/0.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_prog_failure.1939527849
Short name T636
Test name
Test status
Simulation time 47749471 ps
CPU time 2.83 seconds
Started Jun 05 05:58:36 PM PDT 24
Finished Jun 05 05:58:40 PM PDT 24
Peak memory 218060 kb
Host smart-b20316b0-3145-4fa9-8144-e7804a5fe8ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939527849 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_prog_failure.1939527849
Directory /workspace/0.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_regwen_during_op.1910436790
Short name T66
Test name
Test status
Simulation time 326088088 ps
CPU time 3.97 seconds
Started Jun 05 05:58:42 PM PDT 24
Finished Jun 05 05:58:47 PM PDT 24
Peak memory 217744 kb
Host smart-cffac42d-a4dc-4f3a-a618-cd50c71af259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910436790 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_regwen_during_op.1910436790
Directory /workspace/0.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_cm.14219449
Short name T61
Test name
Test status
Simulation time 741602556 ps
CPU time 26.26 seconds
Started Jun 05 05:58:32 PM PDT 24
Finished Jun 05 05:58:59 PM PDT 24
Peak memory 281784 kb
Host smart-64ac2903-ad78-40a8-b846-e9b2748b20c9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14219449 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_cm.14219449
Directory /workspace/0.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_mubi.3460704513
Short name T839
Test name
Test status
Simulation time 291268382 ps
CPU time 11.7 seconds
Started Jun 05 05:58:42 PM PDT 24
Finished Jun 05 05:58:55 PM PDT 24
Peak memory 218960 kb
Host smart-805adb3e-136e-463b-81b8-6f74da047c43
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460704513 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_mubi.3460704513
Directory /workspace/0.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_digest.827740778
Short name T811
Test name
Test status
Simulation time 235007275 ps
CPU time 9.81 seconds
Started Jun 05 05:58:36 PM PDT 24
Finished Jun 05 05:58:47 PM PDT 24
Peak memory 226220 kb
Host smart-2f65ef7c-f9f4-4c50-899e-78d100f0fabb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827740778 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_dig
est.827740778
Directory /workspace/0.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_mux.3317777554
Short name T644
Test name
Test status
Simulation time 2022819543 ps
CPU time 8.5 seconds
Started Jun 05 05:58:35 PM PDT 24
Finished Jun 05 05:58:44 PM PDT 24
Peak memory 218120 kb
Host smart-9eb84675-00df-487e-b545-c7cc8b2d65f4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317777554 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_mux.3
317777554
Directory /workspace/0.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/0.lc_ctrl_security_escalation.2701606200
Short name T78
Test name
Test status
Simulation time 1784667220 ps
CPU time 8.1 seconds
Started Jun 05 05:58:34 PM PDT 24
Finished Jun 05 05:58:43 PM PDT 24
Peak memory 218092 kb
Host smart-91f2e806-1646-41da-8f68-c95def506bd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701606200 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_security_escalation.2701606200
Directory /workspace/0.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/0.lc_ctrl_smoke.2532910926
Short name T809
Test name
Test status
Simulation time 220919899 ps
CPU time 2.49 seconds
Started Jun 05 05:58:33 PM PDT 24
Finished Jun 05 05:58:36 PM PDT 24
Peak memory 213992 kb
Host smart-c8292cc5-3ac7-413d-a142-5f554077296e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532910926 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_smoke.2532910926
Directory /workspace/0.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_failure.2324527766
Short name T312
Test name
Test status
Simulation time 1254751014 ps
CPU time 25.76 seconds
Started Jun 05 05:58:36 PM PDT 24
Finished Jun 05 05:59:03 PM PDT 24
Peak memory 251000 kb
Host smart-194e8884-0138-4d24-bfea-16dcd24b2ba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324527766 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_failure.2324527766
Directory /workspace/0.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all.4164461
Short name T435
Test name
Test status
Simulation time 41778178122 ps
CPU time 83.74 seconds
Started Jun 05 05:58:27 PM PDT 24
Finished Jun 05 05:59:51 PM PDT 24
Peak memory 276056 kb
Host smart-8ac9a509-7bb6-42c5-b60a-be7e64f62ff6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164461 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TE
ST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.
lc_ctrl_stress_all.4164461
Directory /workspace/0.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.lc_ctrl_volatile_unlock_smoke.3460800231
Short name T483
Test name
Test status
Simulation time 16560929 ps
CPU time 0.96 seconds
Started Jun 05 05:58:36 PM PDT 24
Finished Jun 05 05:58:38 PM PDT 24
Peak memory 211524 kb
Host smart-1bbb89dc-924e-408e-8d94-65f9680475a9
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460800231 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ct
rl_volatile_unlock_smoke.3460800231
Directory /workspace/0.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_alert_test.2625556225
Short name T599
Test name
Test status
Simulation time 154820071 ps
CPU time 0.88 seconds
Started Jun 05 05:58:43 PM PDT 24
Finished Jun 05 05:58:47 PM PDT 24
Peak memory 208692 kb
Host smart-a053e6f9-3a1a-4b23-9d1b-0fa47a0c8c76
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625556225 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_alert_test.2625556225
Directory /workspace/1.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.lc_ctrl_errors.1122348739
Short name T373
Test name
Test status
Simulation time 511159021 ps
CPU time 10.64 seconds
Started Jun 05 05:58:36 PM PDT 24
Finished Jun 05 05:58:48 PM PDT 24
Peak memory 218144 kb
Host smart-48e7722e-aac4-480a-bf61-e99b06be1ee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122348739 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_errors.1122348739
Directory /workspace/1.lc_ctrl_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_access.1869338649
Short name T848
Test name
Test status
Simulation time 1034587455 ps
CPU time 3.37 seconds
Started Jun 05 05:58:37 PM PDT 24
Finished Jun 05 05:58:41 PM PDT 24
Peak memory 209524 kb
Host smart-0f59d163-7354-42d7-9f82-68b8201fda2a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869338649 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_access.1869338649
Directory /workspace/1.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_errors.425109944
Short name T540
Test name
Test status
Simulation time 6216217098 ps
CPU time 25.56 seconds
Started Jun 05 05:58:32 PM PDT 24
Finished Jun 05 05:58:58 PM PDT 24
Peak memory 219000 kb
Host smart-d4ac77ba-d58e-4ac1-abc1-e40f8caa7aad
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425109944 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_err
ors.425109944
Directory /workspace/1.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_priority.234613343
Short name T519
Test name
Test status
Simulation time 120067333 ps
CPU time 2.14 seconds
Started Jun 05 05:58:33 PM PDT 24
Finished Jun 05 05:58:36 PM PDT 24
Peak memory 217400 kb
Host smart-69e8070e-6190-461f-9984-778ec3cc0fa2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234613343 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_priority.234613343
Directory /workspace/1.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_prog_failure.3244714114
Short name T680
Test name
Test status
Simulation time 1572222908 ps
CPU time 6.15 seconds
Started Jun 05 05:58:35 PM PDT 24
Finished Jun 05 05:58:42 PM PDT 24
Peak memory 217872 kb
Host smart-a7dfbf0f-790a-40aa-8048-023076977e7e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244714114 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag
_prog_failure.3244714114
Directory /workspace/1.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_regwen_during_op.3670022726
Short name T163
Test name
Test status
Simulation time 2720256286 ps
CPU time 23.76 seconds
Started Jun 05 05:58:35 PM PDT 24
Finished Jun 05 05:59:00 PM PDT 24
Peak memory 217732 kb
Host smart-278095b9-99a0-451a-87b5-c746f17c0aa0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670022726 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_regwen_during_op.3670022726
Directory /workspace/1.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_smoke.1134598029
Short name T106
Test name
Test status
Simulation time 902307413 ps
CPU time 4.18 seconds
Started Jun 05 05:58:37 PM PDT 24
Finished Jun 05 05:58:42 PM PDT 24
Peak memory 217672 kb
Host smart-ef7fbe01-02e4-4511-8351-b5495c196af8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134598029 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_smoke.
1134598029
Directory /workspace/1.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_failure.2854248965
Short name T89
Test name
Test status
Simulation time 10536792728 ps
CPU time 50.93 seconds
Started Jun 05 05:58:39 PM PDT 24
Finished Jun 05 05:59:31 PM PDT 24
Peak memory 267404 kb
Host smart-cfe81e55-be67-4cf3-a692-a06d9f87da2a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854248965 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jta
g_state_failure.2854248965
Directory /workspace/1.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_post_trans.1086860527
Short name T239
Test name
Test status
Simulation time 1082594607 ps
CPU time 20.27 seconds
Started Jun 05 05:58:44 PM PDT 24
Finished Jun 05 05:59:06 PM PDT 24
Peak memory 250904 kb
Host smart-5667c34a-1e77-4447-ab38-af58cd9071ab
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086860527 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_state_post_trans.1086860527
Directory /workspace/1.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_prog_failure.2807009614
Short name T398
Test name
Test status
Simulation time 25229665 ps
CPU time 2.14 seconds
Started Jun 05 05:58:35 PM PDT 24
Finished Jun 05 05:58:38 PM PDT 24
Peak memory 218048 kb
Host smart-c9da2c16-66f0-45ce-80c0-c590c5520d6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807009614 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_prog_failure.2807009614
Directory /workspace/1.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_regwen_during_op.3627774902
Short name T68
Test name
Test status
Simulation time 372769025 ps
CPU time 12.46 seconds
Started Jun 05 05:58:34 PM PDT 24
Finished Jun 05 05:58:47 PM PDT 24
Peak memory 217776 kb
Host smart-745e4ce7-003f-4bc0-a68f-e0eadc440284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627774902 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_regwen_during_op.3627774902
Directory /workspace/1.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_mubi.1353610832
Short name T389
Test name
Test status
Simulation time 363215449 ps
CPU time 16.14 seconds
Started Jun 05 05:58:42 PM PDT 24
Finished Jun 05 05:58:59 PM PDT 24
Peak memory 226148 kb
Host smart-497da358-d5bb-48d5-8fe6-7d2e2d1f6e3f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353610832 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_mubi.1353610832
Directory /workspace/1.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_digest.284232129
Short name T284
Test name
Test status
Simulation time 843677389 ps
CPU time 9.19 seconds
Started Jun 05 05:58:38 PM PDT 24
Finished Jun 05 05:58:54 PM PDT 24
Peak memory 217896 kb
Host smart-b770aea9-110a-4263-aa2a-6ac34de54017
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284232129 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_dig
est.284232129
Directory /workspace/1.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_mux.1134906491
Short name T375
Test name
Test status
Simulation time 767545869 ps
CPU time 6.93 seconds
Started Jun 05 05:58:36 PM PDT 24
Finished Jun 05 05:58:44 PM PDT 24
Peak memory 218116 kb
Host smart-d26e4845-8207-4fcc-a61c-526af96c83fa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134906491 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_mux.1
134906491
Directory /workspace/1.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/1.lc_ctrl_security_escalation.173527102
Short name T588
Test name
Test status
Simulation time 552503540 ps
CPU time 6.74 seconds
Started Jun 05 05:58:33 PM PDT 24
Finished Jun 05 05:58:41 PM PDT 24
Peak memory 217724 kb
Host smart-5c545153-e12e-4453-8ad8-ae6c2ae1dfd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173527102 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_security_escalation.173527102
Directory /workspace/1.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/1.lc_ctrl_smoke.109964371
Short name T278
Test name
Test status
Simulation time 862453253 ps
CPU time 2 seconds
Started Jun 05 05:58:24 PM PDT 24
Finished Jun 05 05:58:27 PM PDT 24
Peak memory 213952 kb
Host smart-2d081f86-14e6-4eb7-9a6f-fab166994cd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109964371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_smoke.109964371
Directory /workspace/1.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_failure.3415947744
Short name T390
Test name
Test status
Simulation time 459863002 ps
CPU time 26.94 seconds
Started Jun 05 05:58:34 PM PDT 24
Finished Jun 05 05:59:01 PM PDT 24
Peak memory 251024 kb
Host smart-9863cca8-c739-4ea4-be00-1fbbc3c40c96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415947744 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_failure.3415947744
Directory /workspace/1.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_post_trans.2854792429
Short name T475
Test name
Test status
Simulation time 51549196 ps
CPU time 2.89 seconds
Started Jun 05 05:58:41 PM PDT 24
Finished Jun 05 05:58:45 PM PDT 24
Peak memory 221152 kb
Host smart-0ebf4bb3-37d1-44a4-876e-c509b6b2aa17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854792429 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_post_trans.2854792429
Directory /workspace/1.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_stress_all.2498186641
Short name T704
Test name
Test status
Simulation time 13639098066 ps
CPU time 266.92 seconds
Started Jun 05 05:58:39 PM PDT 24
Finished Jun 05 06:03:07 PM PDT 24
Peak memory 251068 kb
Host smart-41674d6c-e0f8-4012-a69f-0f6b7d4862c6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498186641 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.lc_ctrl_stress_all.2498186641
Directory /workspace/1.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.lc_ctrl_volatile_unlock_smoke.3119567023
Short name T747
Test name
Test status
Simulation time 72614520 ps
CPU time 1.01 seconds
Started Jun 05 05:58:31 PM PDT 24
Finished Jun 05 05:58:33 PM PDT 24
Peak memory 211588 kb
Host smart-353768d2-d969-48bc-813a-85514109ffdb
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119567023 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ct
rl_volatile_unlock_smoke.3119567023
Directory /workspace/1.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_alert_test.353741724
Short name T816
Test name
Test status
Simulation time 24196814 ps
CPU time 0.96 seconds
Started Jun 05 05:59:05 PM PDT 24
Finished Jun 05 05:59:07 PM PDT 24
Peak memory 208700 kb
Host smart-9905d947-cda6-4973-9124-97594fcf76af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353741724 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_alert_test.353741724
Directory /workspace/10.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.lc_ctrl_errors.3087508996
Short name T396
Test name
Test status
Simulation time 1614275716 ps
CPU time 18.23 seconds
Started Jun 05 05:59:08 PM PDT 24
Finished Jun 05 05:59:27 PM PDT 24
Peak memory 218036 kb
Host smart-a5acfb9f-bac3-4f8a-b5b4-4c29c6cc3b54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087508996 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_errors.3087508996
Directory /workspace/10.lc_ctrl_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_access.1786767632
Short name T859
Test name
Test status
Simulation time 1069985920 ps
CPU time 10.2 seconds
Started Jun 05 05:59:11 PM PDT 24
Finished Jun 05 05:59:21 PM PDT 24
Peak memory 209508 kb
Host smart-fb1b68b6-92c9-4e2e-8993-097737378de9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786767632 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_access.1786767632
Directory /workspace/10.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_errors.4206204681
Short name T763
Test name
Test status
Simulation time 5042106531 ps
CPU time 22.28 seconds
Started Jun 05 05:59:22 PM PDT 24
Finished Jun 05 05:59:44 PM PDT 24
Peak memory 218092 kb
Host smart-7f64703f-012b-43a9-829d-df605f80c6cd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206204681 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_e
rrors.4206204681
Directory /workspace/10.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_prog_failure.385144038
Short name T408
Test name
Test status
Simulation time 1142531226 ps
CPU time 13.5 seconds
Started Jun 05 05:59:06 PM PDT 24
Finished Jun 05 05:59:21 PM PDT 24
Peak memory 217968 kb
Host smart-6553de0e-df22-4430-aad3-ba362a431daa
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385144038 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag
_prog_failure.385144038
Directory /workspace/10.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_smoke.2116502574
Short name T216
Test name
Test status
Simulation time 1178913203 ps
CPU time 16.12 seconds
Started Jun 05 05:58:52 PM PDT 24
Finished Jun 05 05:59:10 PM PDT 24
Peak memory 217680 kb
Host smart-fc19fa74-76ba-4a43-8500-be171d00cf96
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116502574 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_smoke
.2116502574
Directory /workspace/10.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_failure.2530028244
Short name T298
Test name
Test status
Simulation time 1187714839 ps
CPU time 50.8 seconds
Started Jun 05 05:59:13 PM PDT 24
Finished Jun 05 06:00:04 PM PDT 24
Peak memory 251712 kb
Host smart-0b36149d-647f-41c5-a236-b83b90713505
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530028244 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jt
ag_state_failure.2530028244
Directory /workspace/10.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_post_trans.2234926303
Short name T416
Test name
Test status
Simulation time 1499039965 ps
CPU time 25.6 seconds
Started Jun 05 05:59:04 PM PDT 24
Finished Jun 05 05:59:31 PM PDT 24
Peak memory 247392 kb
Host smart-352754dd-841f-4b1a-93f1-3810b4b62a01
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234926303 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl
_jtag_state_post_trans.2234926303
Directory /workspace/10.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_prog_failure.3488581546
Short name T504
Test name
Test status
Simulation time 23093425 ps
CPU time 1.74 seconds
Started Jun 05 05:59:11 PM PDT 24
Finished Jun 05 05:59:13 PM PDT 24
Peak memory 218116 kb
Host smart-a17588a0-b671-4177-a7af-89b1a320d583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488581546 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_prog_failure.3488581546
Directory /workspace/10.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_mubi.705569750
Short name T262
Test name
Test status
Simulation time 3020695120 ps
CPU time 15.57 seconds
Started Jun 05 05:59:06 PM PDT 24
Finished Jun 05 05:59:23 PM PDT 24
Peak memory 226224 kb
Host smart-54ee8ccf-77c3-4de2-8fce-804ebb90995b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705569750 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_mubi.705569750
Directory /workspace/10.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_digest.3307761331
Short name T666
Test name
Test status
Simulation time 4805191209 ps
CPU time 21.9 seconds
Started Jun 05 05:59:00 PM PDT 24
Finished Jun 05 05:59:23 PM PDT 24
Peak memory 226060 kb
Host smart-6de22ece-8ef6-42bd-aa3c-74021283365f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307761331 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_d
igest.3307761331
Directory /workspace/10.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_mux.3666560328
Short name T450
Test name
Test status
Simulation time 1555185234 ps
CPU time 15.14 seconds
Started Jun 05 05:58:59 PM PDT 24
Finished Jun 05 05:59:15 PM PDT 24
Peak memory 218044 kb
Host smart-554de406-9482-4a0e-a97c-e60b6aac7f7b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666560328 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_mux.
3666560328
Directory /workspace/10.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/10.lc_ctrl_security_escalation.4063849295
Short name T397
Test name
Test status
Simulation time 2911140701 ps
CPU time 14.31 seconds
Started Jun 05 05:58:49 PM PDT 24
Finished Jun 05 05:59:10 PM PDT 24
Peak memory 218128 kb
Host smart-ea2839b3-c551-49c1-a7bb-0cc5b2b4d533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063849295 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_security_escalation.4063849295
Directory /workspace/10.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/10.lc_ctrl_smoke.1470550367
Short name T856
Test name
Test status
Simulation time 22799206 ps
CPU time 1.15 seconds
Started Jun 05 05:59:02 PM PDT 24
Finished Jun 05 05:59:04 PM PDT 24
Peak memory 212056 kb
Host smart-9aae7601-2226-47ad-ac1d-8aba9209087e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470550367 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_smoke.1470550367
Directory /workspace/10.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_failure.1287996301
Short name T668
Test name
Test status
Simulation time 243225000 ps
CPU time 21.29 seconds
Started Jun 05 05:58:51 PM PDT 24
Finished Jun 05 05:59:14 PM PDT 24
Peak memory 251140 kb
Host smart-e704c0da-6200-4175-8dc5-3fbb1b6cc598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287996301 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_failure.1287996301
Directory /workspace/10.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_post_trans.264649091
Short name T526
Test name
Test status
Simulation time 340969791 ps
CPU time 6.58 seconds
Started Jun 05 05:58:50 PM PDT 24
Finished Jun 05 05:58:59 PM PDT 24
Peak memory 250608 kb
Host smart-a51ca591-7b2f-4c66-b509-1781954153a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264649091 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_post_trans.264649091
Directory /workspace/10.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all.811413013
Short name T745
Test name
Test status
Simulation time 16498081545 ps
CPU time 109.12 seconds
Started Jun 05 05:59:24 PM PDT 24
Finished Jun 05 06:01:13 PM PDT 24
Peak memory 272420 kb
Host smart-1d99e46a-0d4d-4f96-892c-91aefef9ab22
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811413013 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.lc_ctrl_stress_all.811413013
Directory /workspace/10.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all_with_rand_reset.3355946294
Short name T153
Test name
Test status
Simulation time 6442190032 ps
CPU time 217.6 seconds
Started Jun 05 05:59:13 PM PDT 24
Finished Jun 05 06:02:51 PM PDT 24
Peak memory 272240 kb
Host smart-822a5d2b-76ad-4fca-b8ee-28887be89de4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3355946294 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_stress_all_with_rand_reset.3355946294
Directory /workspace/10.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.lc_ctrl_volatile_unlock_smoke.1829734511
Short name T688
Test name
Test status
Simulation time 13207583 ps
CPU time 0.94 seconds
Started Jun 05 05:58:46 PM PDT 24
Finished Jun 05 05:58:49 PM PDT 24
Peak memory 208616 kb
Host smart-861127dc-d5ad-4478-ae02-697832001115
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829734511 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_c
trl_volatile_unlock_smoke.1829734511
Directory /workspace/10.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_alert_test.3533117269
Short name T168
Test name
Test status
Simulation time 130486182 ps
CPU time 0.92 seconds
Started Jun 05 05:59:04 PM PDT 24
Finished Jun 05 05:59:06 PM PDT 24
Peak memory 208708 kb
Host smart-fd592b03-c066-467b-a02b-8f35c66ff43a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533117269 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_alert_test.3533117269
Directory /workspace/11.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.lc_ctrl_errors.292471155
Short name T34
Test name
Test status
Simulation time 1668726211 ps
CPU time 17.08 seconds
Started Jun 05 05:59:04 PM PDT 24
Finished Jun 05 05:59:22 PM PDT 24
Peak memory 218040 kb
Host smart-19e04294-1898-4a16-940b-a0d4e0fecb8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292471155 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_errors.292471155
Directory /workspace/11.lc_ctrl_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_access.1680039612
Short name T655
Test name
Test status
Simulation time 344921024 ps
CPU time 1.74 seconds
Started Jun 05 05:59:22 PM PDT 24
Finished Jun 05 05:59:24 PM PDT 24
Peak memory 216864 kb
Host smart-10dce951-532d-4bc3-a9da-888a0673b084
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680039612 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_access.1680039612
Directory /workspace/11.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_errors.1368120680
Short name T365
Test name
Test status
Simulation time 2115949470 ps
CPU time 33.57 seconds
Started Jun 05 05:59:13 PM PDT 24
Finished Jun 05 05:59:47 PM PDT 24
Peak memory 217900 kb
Host smart-f0c409f9-1459-4f9f-840f-982a4446c76c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368120680 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_e
rrors.1368120680
Directory /workspace/11.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_prog_failure.3785394812
Short name T479
Test name
Test status
Simulation time 12373362684 ps
CPU time 16.58 seconds
Started Jun 05 05:59:12 PM PDT 24
Finished Jun 05 05:59:29 PM PDT 24
Peak memory 218960 kb
Host smart-360e5228-da76-4c16-af0c-e6133b8d5f18
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785394812 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jta
g_prog_failure.3785394812
Directory /workspace/11.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_post_trans.2155673054
Short name T99
Test name
Test status
Simulation time 4949995061 ps
CPU time 13.08 seconds
Started Jun 05 05:59:14 PM PDT 24
Finished Jun 05 05:59:28 PM PDT 24
Peak memory 249304 kb
Host smart-043deca5-2892-40af-a44c-5c186b0e18d6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155673054 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl
_jtag_state_post_trans.2155673054
Directory /workspace/11.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_prog_failure.1438109178
Short name T497
Test name
Test status
Simulation time 106628374 ps
CPU time 2.95 seconds
Started Jun 05 05:58:53 PM PDT 24
Finished Jun 05 05:58:56 PM PDT 24
Peak memory 218144 kb
Host smart-5279481f-5a0e-4602-9d19-1b1a2d4b12cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438109178 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_prog_failure.1438109178
Directory /workspace/11.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_mubi.868527060
Short name T650
Test name
Test status
Simulation time 412084986 ps
CPU time 13.33 seconds
Started Jun 05 05:59:07 PM PDT 24
Finished Jun 05 05:59:21 PM PDT 24
Peak memory 218988 kb
Host smart-ae1f42b0-c321-4fe9-93d5-feac6e5f1c6e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868527060 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_mubi.868527060
Directory /workspace/11.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_digest.3548958751
Short name T457
Test name
Test status
Simulation time 252804721 ps
CPU time 8.42 seconds
Started Jun 05 05:59:11 PM PDT 24
Finished Jun 05 05:59:20 PM PDT 24
Peak memory 217904 kb
Host smart-0f9b2c00-3826-4413-88c2-bf60f1be89f7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548958751 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_d
igest.3548958751
Directory /workspace/11.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_mux.3186975224
Short name T274
Test name
Test status
Simulation time 2108040642 ps
CPU time 8.63 seconds
Started Jun 05 05:59:04 PM PDT 24
Finished Jun 05 05:59:14 PM PDT 24
Peak memory 218028 kb
Host smart-e7966d67-1df0-40ff-8afb-8e3e827bd2ce
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186975224 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_mux.
3186975224
Directory /workspace/11.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/11.lc_ctrl_security_escalation.2332503081
Short name T371
Test name
Test status
Simulation time 999736741 ps
CPU time 10.23 seconds
Started Jun 05 05:58:58 PM PDT 24
Finished Jun 05 05:59:08 PM PDT 24
Peak memory 218100 kb
Host smart-4d350405-e54b-4b22-92cd-e4fcf5f573d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332503081 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_security_escalation.2332503081
Directory /workspace/11.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/11.lc_ctrl_smoke.225067111
Short name T319
Test name
Test status
Simulation time 306397491 ps
CPU time 2.78 seconds
Started Jun 05 05:59:10 PM PDT 24
Finished Jun 05 05:59:14 PM PDT 24
Peak memory 214348 kb
Host smart-9bf056c3-efa1-44ad-83a7-b1b1db3996e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225067111 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_smoke.225067111
Directory /workspace/11.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_failure.3752697466
Short name T791
Test name
Test status
Simulation time 651353502 ps
CPU time 18.73 seconds
Started Jun 05 05:59:10 PM PDT 24
Finished Jun 05 05:59:29 PM PDT 24
Peak memory 251116 kb
Host smart-014abf6a-c28c-4c5d-9af7-ea905180c25d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752697466 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_failure.3752697466
Directory /workspace/11.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_post_trans.3209549629
Short name T546
Test name
Test status
Simulation time 72729459 ps
CPU time 3.02 seconds
Started Jun 05 05:59:06 PM PDT 24
Finished Jun 05 05:59:10 PM PDT 24
Peak memory 218032 kb
Host smart-deb8f27b-b63e-4ff2-a0e7-b86684bf6c8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209549629 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_post_trans.3209549629
Directory /workspace/11.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_stress_all.1412875566
Short name T173
Test name
Test status
Simulation time 6694826828 ps
CPU time 279.49 seconds
Started Jun 05 05:58:46 PM PDT 24
Finished Jun 05 06:03:27 PM PDT 24
Peak memory 250680 kb
Host smart-a417668b-c9ea-4386-b8b6-dde1eda93528
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412875566 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.lc_ctrl_stress_all.1412875566
Directory /workspace/11.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.lc_ctrl_volatile_unlock_smoke.2670891211
Short name T59
Test name
Test status
Simulation time 194236469 ps
CPU time 0.92 seconds
Started Jun 05 05:59:03 PM PDT 24
Finished Jun 05 05:59:04 PM PDT 24
Peak memory 212600 kb
Host smart-3cc01666-1f11-4a59-b678-627f5b9d16ba
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670891211 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_c
trl_volatile_unlock_smoke.2670891211
Directory /workspace/11.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_alert_test.1675078483
Short name T838
Test name
Test status
Simulation time 19218472 ps
CPU time 1.12 seconds
Started Jun 05 05:58:59 PM PDT 24
Finished Jun 05 05:59:01 PM PDT 24
Peak memory 209556 kb
Host smart-1d35a02c-af65-47f2-9631-6b7a279e8c02
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675078483 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_alert_test.1675078483
Directory /workspace/12.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.lc_ctrl_errors.3776140139
Short name T279
Test name
Test status
Simulation time 358679975 ps
CPU time 11.76 seconds
Started Jun 05 05:58:45 PM PDT 24
Finished Jun 05 05:58:59 PM PDT 24
Peak memory 218076 kb
Host smart-88ce4859-5036-4228-87bc-29698e1871c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776140139 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_errors.3776140139
Directory /workspace/12.lc_ctrl_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_access.2033957049
Short name T97
Test name
Test status
Simulation time 2415088148 ps
CPU time 13.54 seconds
Started Jun 05 05:59:05 PM PDT 24
Finished Jun 05 05:59:19 PM PDT 24
Peak memory 209616 kb
Host smart-cbd3c2f5-150f-4c0c-a622-998767a62a37
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033957049 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_access.2033957049
Directory /workspace/12.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_errors.3964284915
Short name T244
Test name
Test status
Simulation time 5341281094 ps
CPU time 39.48 seconds
Started Jun 05 05:59:12 PM PDT 24
Finished Jun 05 05:59:52 PM PDT 24
Peak memory 218512 kb
Host smart-b68d87c1-c73e-4fb9-8f28-0a8bcbd714d9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964284915 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_e
rrors.3964284915
Directory /workspace/12.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_prog_failure.574706860
Short name T632
Test name
Test status
Simulation time 147906992 ps
CPU time 2.96 seconds
Started Jun 05 05:59:07 PM PDT 24
Finished Jun 05 05:59:11 PM PDT 24
Peak memory 218040 kb
Host smart-d314d886-39f7-4e74-a294-50b3ff9a6cf7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574706860 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag
_prog_failure.574706860
Directory /workspace/12.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_smoke.2531090098
Short name T72
Test name
Test status
Simulation time 382890683 ps
CPU time 6.07 seconds
Started Jun 05 05:58:59 PM PDT 24
Finished Jun 05 05:59:06 PM PDT 24
Peak memory 217708 kb
Host smart-2a641794-969b-42c8-89a2-09fd2535f6b8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531090098 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_smoke
.2531090098
Directory /workspace/12.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_failure.2559827994
Short name T327
Test name
Test status
Simulation time 1556825499 ps
CPU time 43.48 seconds
Started Jun 05 05:58:47 PM PDT 24
Finished Jun 05 05:59:32 PM PDT 24
Peak memory 275572 kb
Host smart-d3229ea9-d7a4-4357-9129-a801616c69a9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559827994 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jt
ag_state_failure.2559827994
Directory /workspace/12.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_post_trans.2242373123
Short name T17
Test name
Test status
Simulation time 830843181 ps
CPU time 11.42 seconds
Started Jun 05 05:59:10 PM PDT 24
Finished Jun 05 05:59:22 PM PDT 24
Peak memory 247908 kb
Host smart-5599157b-0651-44dc-b871-4b5b96a1cdcf
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242373123 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl
_jtag_state_post_trans.2242373123
Directory /workspace/12.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_prog_failure.349730496
Short name T404
Test name
Test status
Simulation time 46616027 ps
CPU time 2.23 seconds
Started Jun 05 05:58:48 PM PDT 24
Finished Jun 05 05:58:52 PM PDT 24
Peak memory 218048 kb
Host smart-b83802b9-824f-4aa1-b619-34d6bf16078e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349730496 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_prog_failure.349730496
Directory /workspace/12.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_mubi.199179844
Short name T245
Test name
Test status
Simulation time 1028617993 ps
CPU time 19.83 seconds
Started Jun 05 05:58:47 PM PDT 24
Finished Jun 05 05:59:08 PM PDT 24
Peak memory 226108 kb
Host smart-42d3c15d-db76-47b0-a975-6d077f8b98be
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199179844 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_mubi.199179844
Directory /workspace/12.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_digest.3384076403
Short name T798
Test name
Test status
Simulation time 1287551059 ps
CPU time 7.73 seconds
Started Jun 05 05:59:10 PM PDT 24
Finished Jun 05 05:59:19 PM PDT 24
Peak memory 217972 kb
Host smart-9ed93819-7d90-477e-8110-953813a67c0c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384076403 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_d
igest.3384076403
Directory /workspace/12.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_mux.3897115493
Short name T318
Test name
Test status
Simulation time 822308256 ps
CPU time 12.59 seconds
Started Jun 05 05:58:58 PM PDT 24
Finished Jun 05 05:59:11 PM PDT 24
Peak memory 218036 kb
Host smart-1cb89381-2272-41e4-ab4b-af0e757609f6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897115493 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_mux.
3897115493
Directory /workspace/12.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/12.lc_ctrl_security_escalation.48871680
Short name T545
Test name
Test status
Simulation time 325323484 ps
CPU time 9.32 seconds
Started Jun 05 05:58:46 PM PDT 24
Finished Jun 05 05:59:02 PM PDT 24
Peak memory 218116 kb
Host smart-4af1afc0-4924-46da-bda0-5ea6e1ac134b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48871680 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_security_escalation.48871680
Directory /workspace/12.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/12.lc_ctrl_smoke.4009079661
Short name T564
Test name
Test status
Simulation time 83297283 ps
CPU time 1.88 seconds
Started Jun 05 05:58:49 PM PDT 24
Finished Jun 05 05:58:53 PM PDT 24
Peak memory 213748 kb
Host smart-e495c475-f402-4cbd-b00c-09919fe36d19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009079661 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_smoke.4009079661
Directory /workspace/12.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_failure.3321476546
Short name T499
Test name
Test status
Simulation time 665191426 ps
CPU time 35.13 seconds
Started Jun 05 05:58:57 PM PDT 24
Finished Jun 05 05:59:33 PM PDT 24
Peak memory 250992 kb
Host smart-04ee3a37-66af-42bd-b8e7-9c0d1b6324e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321476546 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_failure.3321476546
Directory /workspace/12.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_post_trans.2429646419
Short name T783
Test name
Test status
Simulation time 91318314 ps
CPU time 9.51 seconds
Started Jun 05 05:58:57 PM PDT 24
Finished Jun 05 05:59:07 PM PDT 24
Peak memory 251064 kb
Host smart-251875aa-9a2c-46db-86c8-da08c1072ecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429646419 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_post_trans.2429646419
Directory /workspace/12.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_stress_all.1612304625
Short name T488
Test name
Test status
Simulation time 41006118768 ps
CPU time 80.16 seconds
Started Jun 05 05:59:08 PM PDT 24
Finished Jun 05 06:00:28 PM PDT 24
Peak memory 277624 kb
Host smart-341f0d54-1f77-424e-aac3-586b5cd81fbc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612304625 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.lc_ctrl_stress_all.1612304625
Directory /workspace/12.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.lc_ctrl_volatile_unlock_smoke.2453714812
Short name T505
Test name
Test status
Simulation time 24219872 ps
CPU time 1.04 seconds
Started Jun 05 05:58:50 PM PDT 24
Finished Jun 05 05:58:53 PM PDT 24
Peak memory 211592 kb
Host smart-df2a07c4-ce85-49a7-9dc1-32575446c194
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453714812 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_c
trl_volatile_unlock_smoke.2453714812
Directory /workspace/12.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_alert_test.3502616228
Short name T774
Test name
Test status
Simulation time 15451225 ps
CPU time 1.09 seconds
Started Jun 05 05:59:11 PM PDT 24
Finished Jun 05 05:59:13 PM PDT 24
Peak memory 209536 kb
Host smart-becc0e59-c077-4a10-a01e-d4447285e065
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502616228 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_alert_test.3502616228
Directory /workspace/13.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.lc_ctrl_errors.3730868206
Short name T818
Test name
Test status
Simulation time 380633237 ps
CPU time 16.33 seconds
Started Jun 05 05:58:59 PM PDT 24
Finished Jun 05 05:59:17 PM PDT 24
Peak memory 217956 kb
Host smart-075315cc-9c61-4023-b145-a763d640caa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730868206 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_errors.3730868206
Directory /workspace/13.lc_ctrl_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_access.1638400540
Short name T288
Test name
Test status
Simulation time 1669198446 ps
CPU time 19.51 seconds
Started Jun 05 05:59:00 PM PDT 24
Finished Jun 05 05:59:20 PM PDT 24
Peak memory 209540 kb
Host smart-989c02fd-6a82-4ec1-9203-8d89b47a1bb6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638400540 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_access.1638400540
Directory /workspace/13.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_errors.1739726349
Short name T539
Test name
Test status
Simulation time 1651853459 ps
CPU time 48.88 seconds
Started Jun 05 05:58:54 PM PDT 24
Finished Jun 05 05:59:43 PM PDT 24
Peak memory 218048 kb
Host smart-33e53c6d-fd5b-40e1-910b-1c6eaace7c2c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739726349 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_e
rrors.1739726349
Directory /workspace/13.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_prog_failure.1615553181
Short name T105
Test name
Test status
Simulation time 204479865 ps
CPU time 7.04 seconds
Started Jun 05 05:59:07 PM PDT 24
Finished Jun 05 05:59:15 PM PDT 24
Peak memory 217968 kb
Host smart-e57196ea-4f3e-4a4d-b1de-676ede4a528e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615553181 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jta
g_prog_failure.1615553181
Directory /workspace/13.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_smoke.3885288969
Short name T785
Test name
Test status
Simulation time 1136135493 ps
CPU time 5.17 seconds
Started Jun 05 05:59:09 PM PDT 24
Finished Jun 05 05:59:15 PM PDT 24
Peak memory 217716 kb
Host smart-4662f936-3178-4178-88ef-e3a6b10cc06a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885288969 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_smoke
.3885288969
Directory /workspace/13.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_failure.2903890936
Short name T697
Test name
Test status
Simulation time 15759145930 ps
CPU time 58.27 seconds
Started Jun 05 05:59:13 PM PDT 24
Finished Jun 05 06:00:12 PM PDT 24
Peak memory 274824 kb
Host smart-3b95d0e7-9348-48e1-9e66-81cc615ae8a5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903890936 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jt
ag_state_failure.2903890936
Directory /workspace/13.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_post_trans.425349854
Short name T1
Test name
Test status
Simulation time 1486102895 ps
CPU time 11.05 seconds
Started Jun 05 05:59:08 PM PDT 24
Finished Jun 05 05:59:20 PM PDT 24
Peak memory 250948 kb
Host smart-745318c6-2fdc-4632-ba6e-cde57781368c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425349854 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_
jtag_state_post_trans.425349854
Directory /workspace/13.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_prog_failure.1640243255
Short name T814
Test name
Test status
Simulation time 22862472 ps
CPU time 1.37 seconds
Started Jun 05 05:59:13 PM PDT 24
Finished Jun 05 05:59:15 PM PDT 24
Peak memory 218060 kb
Host smart-b546669e-cea5-40be-b6d8-4074aebc9459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640243255 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_prog_failure.1640243255
Directory /workspace/13.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_mubi.3910895872
Short name T336
Test name
Test status
Simulation time 845267748 ps
CPU time 17.05 seconds
Started Jun 05 05:58:52 PM PDT 24
Finished Jun 05 05:59:10 PM PDT 24
Peak memory 219028 kb
Host smart-49ff5e7c-169c-4e65-8686-7cbe21d9f74a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910895872 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_mubi.3910895872
Directory /workspace/13.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_digest.3372818849
Short name T523
Test name
Test status
Simulation time 289850859 ps
CPU time 14.36 seconds
Started Jun 05 05:59:12 PM PDT 24
Finished Jun 05 05:59:26 PM PDT 24
Peak memory 217908 kb
Host smart-2ab89304-b954-4ebd-b485-9a8e6a03c0c0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372818849 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_d
igest.3372818849
Directory /workspace/13.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_mux.194408382
Short name T466
Test name
Test status
Simulation time 283898230 ps
CPU time 9.95 seconds
Started Jun 05 05:59:15 PM PDT 24
Finished Jun 05 05:59:26 PM PDT 24
Peak memory 218048 kb
Host smart-c5fba6a7-404b-4815-8ecf-de51fc7168a1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194408382 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_mux.194408382
Directory /workspace/13.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/13.lc_ctrl_security_escalation.2959243935
Short name T753
Test name
Test status
Simulation time 500836233 ps
CPU time 7.96 seconds
Started Jun 05 05:59:08 PM PDT 24
Finished Jun 05 05:59:17 PM PDT 24
Peak memory 218100 kb
Host smart-b962335c-9792-4dce-b781-998e7ee488fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959243935 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_security_escalation.2959243935
Directory /workspace/13.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/13.lc_ctrl_smoke.125720352
Short name T805
Test name
Test status
Simulation time 369434593 ps
CPU time 10.45 seconds
Started Jun 05 05:58:58 PM PDT 24
Finished Jun 05 05:59:09 PM PDT 24
Peak memory 217728 kb
Host smart-69a0f626-d44c-4831-9fa8-1aba2ba0e5e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125720352 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_smoke.125720352
Directory /workspace/13.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_failure.2802187513
Short name T742
Test name
Test status
Simulation time 247005710 ps
CPU time 31.59 seconds
Started Jun 05 05:59:09 PM PDT 24
Finished Jun 05 05:59:42 PM PDT 24
Peak memory 251104 kb
Host smart-7fc88559-ba49-4087-8fcd-d908a124e777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802187513 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_failure.2802187513
Directory /workspace/13.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_post_trans.3284134228
Short name T289
Test name
Test status
Simulation time 360230887 ps
CPU time 7.04 seconds
Started Jun 05 05:59:09 PM PDT 24
Finished Jun 05 05:59:16 PM PDT 24
Peak memory 247068 kb
Host smart-365d67d8-466a-4a03-9474-4dbed2d7eafc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284134228 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_post_trans.3284134228
Directory /workspace/13.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all.1863912500
Short name T462
Test name
Test status
Simulation time 63936946383 ps
CPU time 276.22 seconds
Started Jun 05 05:58:50 PM PDT 24
Finished Jun 05 06:03:28 PM PDT 24
Peak memory 253920 kb
Host smart-e94d68b0-6885-417c-a1ba-d0d4fa750d14
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863912500 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.lc_ctrl_stress_all.1863912500
Directory /workspace/13.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.lc_ctrl_volatile_unlock_smoke.335427841
Short name T29
Test name
Test status
Simulation time 16389858 ps
CPU time 0.83 seconds
Started Jun 05 05:59:05 PM PDT 24
Finished Jun 05 05:59:07 PM PDT 24
Peak memory 208756 kb
Host smart-ce8736a5-c3f1-4c31-bdb8-a79486f07e77
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335427841 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ct
rl_volatile_unlock_smoke.335427841
Directory /workspace/13.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_alert_test.3514053716
Short name T332
Test name
Test status
Simulation time 344097104 ps
CPU time 1.25 seconds
Started Jun 05 05:59:07 PM PDT 24
Finished Jun 05 05:59:09 PM PDT 24
Peak memory 208812 kb
Host smart-c42890d5-dcb3-45ea-a833-560230e61d77
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514053716 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_alert_test.3514053716
Directory /workspace/14.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.lc_ctrl_errors.222389430
Short name T536
Test name
Test status
Simulation time 3831593756 ps
CPU time 12.35 seconds
Started Jun 05 05:59:11 PM PDT 24
Finished Jun 05 05:59:24 PM PDT 24
Peak memory 218072 kb
Host smart-d547f9fa-4930-49cf-8f8d-e5f9a10e0dad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222389430 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_errors.222389430
Directory /workspace/14.lc_ctrl_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_access.4282381264
Short name T627
Test name
Test status
Simulation time 782930098 ps
CPU time 9.94 seconds
Started Jun 05 05:59:07 PM PDT 24
Finished Jun 05 05:59:17 PM PDT 24
Peak memory 217172 kb
Host smart-5f82c68f-5f72-417c-8028-e7dc934d9c78
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282381264 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_access.4282381264
Directory /workspace/14.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_errors.3700456709
Short name T447
Test name
Test status
Simulation time 32076458597 ps
CPU time 45.91 seconds
Started Jun 05 05:59:10 PM PDT 24
Finished Jun 05 05:59:56 PM PDT 24
Peak memory 218032 kb
Host smart-c130c13c-b934-434a-8512-1188271397d8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700456709 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_e
rrors.3700456709
Directory /workspace/14.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_prog_failure.1012654001
Short name T202
Test name
Test status
Simulation time 1742393057 ps
CPU time 7.34 seconds
Started Jun 05 05:59:13 PM PDT 24
Finished Jun 05 05:59:21 PM PDT 24
Peak memory 217964 kb
Host smart-4de90b6d-9993-4bf0-89a7-d18d8ccd8bbb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012654001 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jta
g_prog_failure.1012654001
Directory /workspace/14.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_smoke.1668132391
Short name T607
Test name
Test status
Simulation time 357318319 ps
CPU time 3.2 seconds
Started Jun 05 05:59:06 PM PDT 24
Finished Jun 05 05:59:10 PM PDT 24
Peak memory 217676 kb
Host smart-5d5b82f5-f663-49bc-ba57-c0a4ca03729a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668132391 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_smoke
.1668132391
Directory /workspace/14.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_failure.2527180078
Short name T716
Test name
Test status
Simulation time 4476552899 ps
CPU time 44.67 seconds
Started Jun 05 05:59:01 PM PDT 24
Finished Jun 05 05:59:46 PM PDT 24
Peak memory 252456 kb
Host smart-c0b91554-9b3d-4dbf-bf40-20966ea095ae
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527180078 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jt
ag_state_failure.2527180078
Directory /workspace/14.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_post_trans.857473054
Short name T755
Test name
Test status
Simulation time 4350253567 ps
CPU time 18.14 seconds
Started Jun 05 05:59:04 PM PDT 24
Finished Jun 05 05:59:22 PM PDT 24
Peak memory 223748 kb
Host smart-78b728ff-0bc1-465a-8b71-42af91500533
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857473054 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_
jtag_state_post_trans.857473054
Directory /workspace/14.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_prog_failure.932736994
Short name T277
Test name
Test status
Simulation time 28601249 ps
CPU time 1.82 seconds
Started Jun 05 05:59:09 PM PDT 24
Finished Jun 05 05:59:12 PM PDT 24
Peak memory 218032 kb
Host smart-fab3d0b6-d32e-4ea0-9f88-cf39d4348563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932736994 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_prog_failure.932736994
Directory /workspace/14.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_mubi.1467377896
Short name T242
Test name
Test status
Simulation time 226881400 ps
CPU time 11.25 seconds
Started Jun 05 05:59:11 PM PDT 24
Finished Jun 05 05:59:23 PM PDT 24
Peak memory 226128 kb
Host smart-0d339a40-4914-42bc-9cb6-c9dea0c2440a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467377896 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_mubi.1467377896
Directory /workspace/14.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_digest.830543803
Short name T667
Test name
Test status
Simulation time 1451234303 ps
CPU time 10.97 seconds
Started Jun 05 05:59:15 PM PDT 24
Finished Jun 05 05:59:27 PM PDT 24
Peak memory 226112 kb
Host smart-5591e271-e6b3-4cd3-961d-5020ac0a100c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830543803 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_di
gest.830543803
Directory /workspace/14.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_mux.3973725570
Short name T385
Test name
Test status
Simulation time 2245004138 ps
CPU time 11.71 seconds
Started Jun 05 05:58:56 PM PDT 24
Finished Jun 05 05:59:08 PM PDT 24
Peak memory 218204 kb
Host smart-c2392a64-5d1f-4337-862b-86c44c58febb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973725570 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_mux.
3973725570
Directory /workspace/14.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/14.lc_ctrl_smoke.3122970099
Short name T591
Test name
Test status
Simulation time 280178864 ps
CPU time 3.47 seconds
Started Jun 05 05:59:10 PM PDT 24
Finished Jun 05 05:59:14 PM PDT 24
Peak memory 217740 kb
Host smart-8a90a7ed-eb64-41ba-a99f-f1867f698a14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122970099 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_smoke.3122970099
Directory /workspace/14.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_failure.2406727099
Short name T524
Test name
Test status
Simulation time 486258735 ps
CPU time 20.93 seconds
Started Jun 05 05:59:06 PM PDT 24
Finished Jun 05 05:59:28 PM PDT 24
Peak memory 251008 kb
Host smart-93d1b3a1-b2b7-432c-8198-9cfa5dae0d1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406727099 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_failure.2406727099
Directory /workspace/14.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_post_trans.2583325794
Short name T300
Test name
Test status
Simulation time 87124185 ps
CPU time 8.77 seconds
Started Jun 05 05:59:04 PM PDT 24
Finished Jun 05 05:59:18 PM PDT 24
Peak memory 247508 kb
Host smart-7c68ff79-6cc8-457a-b0df-a1d7978ecf51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583325794 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_post_trans.2583325794
Directory /workspace/14.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_stress_all.4129222968
Short name T248
Test name
Test status
Simulation time 7182900528 ps
CPU time 109.51 seconds
Started Jun 05 05:59:12 PM PDT 24
Finished Jun 05 06:01:02 PM PDT 24
Peak memory 273112 kb
Host smart-dfba38ec-38b2-4599-b6ab-eb9e4924456e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129222968 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.lc_ctrl_stress_all.4129222968
Directory /workspace/14.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.lc_ctrl_volatile_unlock_smoke.3311989361
Short name T386
Test name
Test status
Simulation time 40109304 ps
CPU time 0.88 seconds
Started Jun 05 05:59:12 PM PDT 24
Finished Jun 05 05:59:14 PM PDT 24
Peak memory 208604 kb
Host smart-a2585bef-2b8b-406b-9614-28d5bcba44d3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311989361 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_c
trl_volatile_unlock_smoke.3311989361
Directory /workspace/14.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_alert_test.3252695785
Short name T618
Test name
Test status
Simulation time 42976385 ps
CPU time 1 seconds
Started Jun 05 05:59:05 PM PDT 24
Finished Jun 05 05:59:07 PM PDT 24
Peak memory 208672 kb
Host smart-7d68c868-9f04-422b-a1fa-420d5aab5390
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252695785 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_alert_test.3252695785
Directory /workspace/15.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.lc_ctrl_errors.2183740116
Short name T860
Test name
Test status
Simulation time 196591799 ps
CPU time 8.01 seconds
Started Jun 05 05:59:14 PM PDT 24
Finished Jun 05 05:59:22 PM PDT 24
Peak memory 218096 kb
Host smart-694360f6-b104-4625-8f72-b9acdeed78d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183740116 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_errors.2183740116
Directory /workspace/15.lc_ctrl_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_access.2949973391
Short name T174
Test name
Test status
Simulation time 728503435 ps
CPU time 9.5 seconds
Started Jun 05 05:59:15 PM PDT 24
Finished Jun 05 05:59:25 PM PDT 24
Peak memory 217236 kb
Host smart-cf37b85f-5f83-45e1-b629-af9086be2fb1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949973391 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_access.2949973391
Directory /workspace/15.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_errors.2454733652
Short name T444
Test name
Test status
Simulation time 3208509712 ps
CPU time 39.87 seconds
Started Jun 05 05:59:05 PM PDT 24
Finished Jun 05 05:59:46 PM PDT 24
Peak memory 219120 kb
Host smart-7175247d-e76f-4557-b064-082fa728f6e0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454733652 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_e
rrors.2454733652
Directory /workspace/15.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_prog_failure.2614887536
Short name T761
Test name
Test status
Simulation time 989397456 ps
CPU time 9.29 seconds
Started Jun 05 05:59:12 PM PDT 24
Finished Jun 05 05:59:22 PM PDT 24
Peak memory 217968 kb
Host smart-8df2f98b-649d-4a66-86c2-c580d3130f6c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614887536 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jta
g_prog_failure.2614887536
Directory /workspace/15.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_smoke.1418279222
Short name T349
Test name
Test status
Simulation time 3608480249 ps
CPU time 9.2 seconds
Started Jun 05 05:59:11 PM PDT 24
Finished Jun 05 05:59:20 PM PDT 24
Peak memory 217736 kb
Host smart-97d7a829-c95b-4ea2-a72c-9dcef69b5dd0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418279222 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_smoke
.1418279222
Directory /workspace/15.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_failure.2845290772
Short name T432
Test name
Test status
Simulation time 3791125725 ps
CPU time 68.83 seconds
Started Jun 05 05:59:04 PM PDT 24
Finished Jun 05 06:00:14 PM PDT 24
Peak memory 275632 kb
Host smart-c17b45a6-9d7e-45d6-a781-18e63711b625
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845290772 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jt
ag_state_failure.2845290772
Directory /workspace/15.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_post_trans.4039448982
Short name T797
Test name
Test status
Simulation time 921220277 ps
CPU time 12.3 seconds
Started Jun 05 05:59:12 PM PDT 24
Finished Jun 05 05:59:25 PM PDT 24
Peak memory 246824 kb
Host smart-367cf3c4-abdb-497e-8a66-4e45003bad03
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039448982 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl
_jtag_state_post_trans.4039448982
Directory /workspace/15.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_prog_failure.676799373
Short name T611
Test name
Test status
Simulation time 58525860 ps
CPU time 2.55 seconds
Started Jun 05 05:59:14 PM PDT 24
Finished Jun 05 05:59:17 PM PDT 24
Peak memory 218064 kb
Host smart-6491bb5b-747d-4178-8baa-4823fa784ce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676799373 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_prog_failure.676799373
Directory /workspace/15.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_mubi.253292683
Short name T226
Test name
Test status
Simulation time 1492800464 ps
CPU time 16.16 seconds
Started Jun 05 05:59:13 PM PDT 24
Finished Jun 05 05:59:30 PM PDT 24
Peak memory 218064 kb
Host smart-6e2cb76e-23dc-4da1-9f69-ac2bcb577d37
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253292683 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_mubi.253292683
Directory /workspace/15.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_digest.166403236
Short name T782
Test name
Test status
Simulation time 422735666 ps
CPU time 15.26 seconds
Started Jun 05 05:59:22 PM PDT 24
Finished Jun 05 05:59:38 PM PDT 24
Peak memory 226072 kb
Host smart-37a6effa-cd7e-40f4-b02f-0db843561220
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166403236 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_di
gest.166403236
Directory /workspace/15.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_mux.1933620283
Short name T807
Test name
Test status
Simulation time 658022135 ps
CPU time 9.39 seconds
Started Jun 05 05:59:10 PM PDT 24
Finished Jun 05 05:59:20 PM PDT 24
Peak memory 217992 kb
Host smart-d767b422-fbb4-4a87-be82-fb6ad88c9609
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933620283 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_mux.
1933620283
Directory /workspace/15.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/15.lc_ctrl_security_escalation.2907863355
Short name T324
Test name
Test status
Simulation time 413831725 ps
CPU time 11.08 seconds
Started Jun 05 05:59:16 PM PDT 24
Finished Jun 05 05:59:28 PM PDT 24
Peak memory 218268 kb
Host smart-c556984a-b007-4b79-9888-5a78f9958132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907863355 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_security_escalation.2907863355
Directory /workspace/15.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/15.lc_ctrl_smoke.1236022247
Short name T581
Test name
Test status
Simulation time 33161860 ps
CPU time 1 seconds
Started Jun 05 05:59:11 PM PDT 24
Finished Jun 05 05:59:13 PM PDT 24
Peak memory 217672 kb
Host smart-82b0e7d6-20c0-42d9-9030-b3f69b608b6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236022247 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_smoke.1236022247
Directory /workspace/15.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_failure.388739278
Short name T296
Test name
Test status
Simulation time 1352744205 ps
CPU time 27.94 seconds
Started Jun 05 05:59:04 PM PDT 24
Finished Jun 05 05:59:33 PM PDT 24
Peak memory 251036 kb
Host smart-3a54fe77-4f20-468a-a1aa-28a3bb1026dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388739278 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_failure.388739278
Directory /workspace/15.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_post_trans.228468603
Short name T14
Test name
Test status
Simulation time 177900736 ps
CPU time 6.59 seconds
Started Jun 05 05:59:05 PM PDT 24
Finished Jun 05 05:59:12 PM PDT 24
Peak memory 247184 kb
Host smart-c6f4bcc9-3b7c-4ec2-aad9-ddd3c58cba47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228468603 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_post_trans.228468603
Directory /workspace/15.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all.115016680
Short name T267
Test name
Test status
Simulation time 23557694750 ps
CPU time 105.79 seconds
Started Jun 05 05:59:29 PM PDT 24
Finished Jun 05 06:01:16 PM PDT 24
Peak memory 226188 kb
Host smart-7e83d7a3-e68e-47ed-a511-cff68c367888
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115016680 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.lc_ctrl_stress_all.115016680
Directory /workspace/15.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.lc_ctrl_volatile_unlock_smoke.1204526866
Short name T592
Test name
Test status
Simulation time 14545636 ps
CPU time 1.02 seconds
Started Jun 05 05:59:12 PM PDT 24
Finished Jun 05 05:59:13 PM PDT 24
Peak memory 208592 kb
Host smart-8aec9013-d882-4bd0-8e3f-ce360d008ab4
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204526866 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_c
trl_volatile_unlock_smoke.1204526866
Directory /workspace/15.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_alert_test.3943453926
Short name T421
Test name
Test status
Simulation time 15842704 ps
CPU time 0.91 seconds
Started Jun 05 05:59:20 PM PDT 24
Finished Jun 05 05:59:22 PM PDT 24
Peak memory 208712 kb
Host smart-77dfef3e-4391-4618-ba4a-eb916af3574a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943453926 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_alert_test.3943453926
Directory /workspace/16.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.lc_ctrl_errors.990374867
Short name T679
Test name
Test status
Simulation time 1175752633 ps
CPU time 12.16 seconds
Started Jun 05 05:59:10 PM PDT 24
Finished Jun 05 05:59:23 PM PDT 24
Peak memory 218084 kb
Host smart-b9369a95-1f88-4e1d-8dd3-831af238b790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990374867 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_errors.990374867
Directory /workspace/16.lc_ctrl_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_access.1993479246
Short name T387
Test name
Test status
Simulation time 5585435134 ps
CPU time 3.73 seconds
Started Jun 05 05:59:21 PM PDT 24
Finished Jun 05 05:59:25 PM PDT 24
Peak memory 217576 kb
Host smart-cb1da2be-ab97-4a43-b77c-a9a051f2f4dd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993479246 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_access.1993479246
Directory /workspace/16.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_errors.1042371129
Short name T315
Test name
Test status
Simulation time 1864876607 ps
CPU time 55.58 seconds
Started Jun 05 05:59:17 PM PDT 24
Finished Jun 05 06:00:13 PM PDT 24
Peak memory 217960 kb
Host smart-6c959b04-393d-4b56-81c8-b314205e2acd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042371129 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_e
rrors.1042371129
Directory /workspace/16.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_prog_failure.3721917921
Short name T440
Test name
Test status
Simulation time 136432021 ps
CPU time 2.61 seconds
Started Jun 05 05:59:16 PM PDT 24
Finished Jun 05 05:59:19 PM PDT 24
Peak memory 217968 kb
Host smart-7a8022af-8376-44f2-8810-4fd68726e10b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721917921 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jta
g_prog_failure.3721917921
Directory /workspace/16.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_smoke.1611359707
Short name T162
Test name
Test status
Simulation time 331475160 ps
CPU time 9.63 seconds
Started Jun 05 05:59:16 PM PDT 24
Finished Jun 05 05:59:26 PM PDT 24
Peak memory 217660 kb
Host smart-0d15258b-b5d7-4b1c-8419-d21781da187b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611359707 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_smoke
.1611359707
Directory /workspace/16.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_failure.844641800
Short name T270
Test name
Test status
Simulation time 3733721130 ps
CPU time 89.67 seconds
Started Jun 05 05:59:11 PM PDT 24
Finished Jun 05 06:00:41 PM PDT 24
Peak memory 283816 kb
Host smart-93196d33-c43e-46c3-8e3f-f272dbc093a9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844641800 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jta
g_state_failure.844641800
Directory /workspace/16.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_post_trans.2523309279
Short name T100
Test name
Test status
Simulation time 349287389 ps
CPU time 17.25 seconds
Started Jun 05 05:59:14 PM PDT 24
Finished Jun 05 05:59:32 PM PDT 24
Peak memory 250956 kb
Host smart-527e69e2-8240-4e75-aac5-6cfec439cbbc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523309279 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl
_jtag_state_post_trans.2523309279
Directory /workspace/16.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_prog_failure.293157950
Short name T283
Test name
Test status
Simulation time 85082877 ps
CPU time 2.15 seconds
Started Jun 05 05:59:14 PM PDT 24
Finished Jun 05 05:59:17 PM PDT 24
Peak memory 218068 kb
Host smart-75db94ba-c7f4-4ad7-a841-c39d226026af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293157950 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_prog_failure.293157950
Directory /workspace/16.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_mubi.1329928949
Short name T161
Test name
Test status
Simulation time 808012709 ps
CPU time 11.37 seconds
Started Jun 05 05:59:14 PM PDT 24
Finished Jun 05 05:59:26 PM PDT 24
Peak memory 218032 kb
Host smart-b902a99a-3f98-4860-895d-032bf2b17b0d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329928949 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_mubi.1329928949
Directory /workspace/16.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_digest.2673389988
Short name T400
Test name
Test status
Simulation time 1089044038 ps
CPU time 7.85 seconds
Started Jun 05 05:59:04 PM PDT 24
Finished Jun 05 05:59:13 PM PDT 24
Peak memory 217972 kb
Host smart-3ba25ba4-0de1-47d2-842b-9b188b816c03
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673389988 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_d
igest.2673389988
Directory /workspace/16.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_mux.4153982338
Short name T664
Test name
Test status
Simulation time 612397273 ps
CPU time 11.63 seconds
Started Jun 05 05:59:20 PM PDT 24
Finished Jun 05 05:59:32 PM PDT 24
Peak memory 218044 kb
Host smart-f697faf9-e98a-4793-b6e2-1d1fd6d5abc8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153982338 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_mux.
4153982338
Directory /workspace/16.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/16.lc_ctrl_security_escalation.189376302
Short name T429
Test name
Test status
Simulation time 450643768 ps
CPU time 9.53 seconds
Started Jun 05 05:59:11 PM PDT 24
Finished Jun 05 05:59:21 PM PDT 24
Peak memory 218184 kb
Host smart-c6925590-903c-4374-9822-8aba562ee178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189376302 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_security_escalation.189376302
Directory /workspace/16.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/16.lc_ctrl_smoke.1965194967
Short name T366
Test name
Test status
Simulation time 25658930 ps
CPU time 2.09 seconds
Started Jun 05 05:59:11 PM PDT 24
Finished Jun 05 05:59:14 PM PDT 24
Peak memory 213868 kb
Host smart-856c5fb6-2d4a-43c0-b901-60fe42155f75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965194967 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_smoke.1965194967
Directory /workspace/16.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_failure.201347796
Short name T551
Test name
Test status
Simulation time 1514779107 ps
CPU time 33.51 seconds
Started Jun 05 05:59:15 PM PDT 24
Finished Jun 05 05:59:49 PM PDT 24
Peak memory 251024 kb
Host smart-ff1089d6-8ec4-4345-bd9d-b08f1b368082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201347796 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_failure.201347796
Directory /workspace/16.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_post_trans.2692313670
Short name T302
Test name
Test status
Simulation time 218599506 ps
CPU time 7.63 seconds
Started Jun 05 05:59:18 PM PDT 24
Finished Jun 05 05:59:26 PM PDT 24
Peak memory 251024 kb
Host smart-d1cc505b-14e4-4708-9789-282c6b22b808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692313670 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_post_trans.2692313670
Directory /workspace/16.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_stress_all.275692337
Short name T788
Test name
Test status
Simulation time 6647193385 ps
CPU time 225.42 seconds
Started Jun 05 05:59:25 PM PDT 24
Finished Jun 05 06:03:10 PM PDT 24
Peak memory 259268 kb
Host smart-087da01a-0754-4bb4-8079-0dcddd809d7f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275692337 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.lc_ctrl_stress_all.275692337
Directory /workspace/16.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.lc_ctrl_volatile_unlock_smoke.3315596033
Short name T304
Test name
Test status
Simulation time 267167337 ps
CPU time 1.21 seconds
Started Jun 05 05:59:20 PM PDT 24
Finished Jun 05 05:59:22 PM PDT 24
Peak memory 212768 kb
Host smart-d96d5e30-5934-4f4e-a8a2-b88de853e21b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315596033 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_c
trl_volatile_unlock_smoke.3315596033
Directory /workspace/16.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_alert_test.1661148397
Short name T333
Test name
Test status
Simulation time 79676021 ps
CPU time 0.95 seconds
Started Jun 05 05:59:22 PM PDT 24
Finished Jun 05 05:59:23 PM PDT 24
Peak memory 208704 kb
Host smart-0124a285-7cba-4cec-a867-4babc9a02f82
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661148397 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_alert_test.1661148397
Directory /workspace/17.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.lc_ctrl_errors.3206367241
Short name T833
Test name
Test status
Simulation time 1361886750 ps
CPU time 15.31 seconds
Started Jun 05 05:59:24 PM PDT 24
Finished Jun 05 05:59:39 PM PDT 24
Peak memory 217948 kb
Host smart-f34764c8-4d3f-467c-93c8-506ae9513567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206367241 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_errors.3206367241
Directory /workspace/17.lc_ctrl_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_access.1027483209
Short name T8
Test name
Test status
Simulation time 1295042042 ps
CPU time 10.36 seconds
Started Jun 05 05:59:20 PM PDT 24
Finished Jun 05 05:59:31 PM PDT 24
Peak memory 217104 kb
Host smart-a44a51de-728c-4ebb-8e1b-c6cd82b57bd0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027483209 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_access.1027483209
Directory /workspace/17.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_errors.2053499503
Short name T582
Test name
Test status
Simulation time 9822705409 ps
CPU time 79.16 seconds
Started Jun 05 05:59:23 PM PDT 24
Finished Jun 05 06:00:43 PM PDT 24
Peak memory 218544 kb
Host smart-d2ce903a-231f-47f7-8ee5-537ae5dbec81
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053499503 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_e
rrors.2053499503
Directory /workspace/17.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_prog_failure.637024377
Short name T291
Test name
Test status
Simulation time 1298944525 ps
CPU time 3.48 seconds
Started Jun 05 05:59:16 PM PDT 24
Finished Jun 05 05:59:21 PM PDT 24
Peak memory 217988 kb
Host smart-d42afa5b-dbbf-48e6-8c95-8bdd426bdd51
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637024377 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag
_prog_failure.637024377
Directory /workspace/17.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_smoke.704162777
Short name T834
Test name
Test status
Simulation time 1277957041 ps
CPU time 5.13 seconds
Started Jun 05 05:59:15 PM PDT 24
Finished Jun 05 05:59:20 PM PDT 24
Peak memory 217696 kb
Host smart-5e433f19-c367-4e00-bef6-9b4494e16aee
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704162777 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_smoke.
704162777
Directory /workspace/17.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_failure.2361214113
Short name T470
Test name
Test status
Simulation time 1183328820 ps
CPU time 37.02 seconds
Started Jun 05 05:59:23 PM PDT 24
Finished Jun 05 06:00:01 PM PDT 24
Peak memory 267332 kb
Host smart-eb2bbd66-979a-416c-83af-a75413f95e1e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361214113 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jt
ag_state_failure.2361214113
Directory /workspace/17.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_post_trans.442931916
Short name T527
Test name
Test status
Simulation time 6196473474 ps
CPU time 15.81 seconds
Started Jun 05 05:59:26 PM PDT 24
Finished Jun 05 05:59:42 PM PDT 24
Peak memory 247056 kb
Host smart-785cc5eb-1d67-4059-beb6-3d7be02e1231
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442931916 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_
jtag_state_post_trans.442931916
Directory /workspace/17.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_prog_failure.2870539047
Short name T204
Test name
Test status
Simulation time 32832401 ps
CPU time 1.84 seconds
Started Jun 05 05:59:15 PM PDT 24
Finished Jun 05 05:59:18 PM PDT 24
Peak memory 218028 kb
Host smart-b55afdcb-cc46-4572-b83e-083d84666d90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870539047 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_prog_failure.2870539047
Directory /workspace/17.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_mubi.3761490358
Short name T403
Test name
Test status
Simulation time 324635026 ps
CPU time 12.89 seconds
Started Jun 05 05:59:19 PM PDT 24
Finished Jun 05 05:59:33 PM PDT 24
Peak memory 219012 kb
Host smart-d86ce2fd-7699-4330-aadf-a346a35ea41d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761490358 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_mubi.3761490358
Directory /workspace/17.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_digest.1763268802
Short name T208
Test name
Test status
Simulation time 1759378052 ps
CPU time 31.86 seconds
Started Jun 05 05:59:28 PM PDT 24
Finished Jun 05 06:00:00 PM PDT 24
Peak memory 217936 kb
Host smart-55d325d4-ff9d-4a8a-a119-78d276d840e2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763268802 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_d
igest.1763268802
Directory /workspace/17.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_mux.3759816041
Short name T823
Test name
Test status
Simulation time 498636233 ps
CPU time 17.08 seconds
Started Jun 05 05:59:20 PM PDT 24
Finished Jun 05 05:59:38 PM PDT 24
Peak memory 218116 kb
Host smart-8478d167-fa4b-44bc-a4d9-e429da3d5d46
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759816041 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_mux.
3759816041
Directory /workspace/17.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/17.lc_ctrl_security_escalation.356559301
Short name T196
Test name
Test status
Simulation time 756403474 ps
CPU time 5.42 seconds
Started Jun 05 05:59:17 PM PDT 24
Finished Jun 05 05:59:23 PM PDT 24
Peak memory 218100 kb
Host smart-cfa228dc-5d53-4046-a993-ab9e4bc0b2da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356559301 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_security_escalation.356559301
Directory /workspace/17.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/17.lc_ctrl_smoke.3753423916
Short name T743
Test name
Test status
Simulation time 106593867 ps
CPU time 4.99 seconds
Started Jun 05 05:59:04 PM PDT 24
Finished Jun 05 05:59:10 PM PDT 24
Peak memory 217740 kb
Host smart-8738b6be-637d-47b4-ba42-1920103e58d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753423916 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_smoke.3753423916
Directory /workspace/17.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_failure.1935871865
Short name T295
Test name
Test status
Simulation time 280874423 ps
CPU time 27.42 seconds
Started Jun 05 05:59:18 PM PDT 24
Finished Jun 05 05:59:46 PM PDT 24
Peak memory 251032 kb
Host smart-0f1bfe1c-7414-4eab-94ef-f7c79af6cd7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935871865 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_failure.1935871865
Directory /workspace/17.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_post_trans.3778658489
Short name T609
Test name
Test status
Simulation time 345704844 ps
CPU time 6.26 seconds
Started Jun 05 05:59:27 PM PDT 24
Finished Jun 05 05:59:34 PM PDT 24
Peak memory 250532 kb
Host smart-70b9badb-7a58-49d7-a7c7-d880df792121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778658489 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_post_trans.3778658489
Directory /workspace/17.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all.1726394543
Short name T516
Test name
Test status
Simulation time 7322965799 ps
CPU time 47.7 seconds
Started Jun 05 05:59:27 PM PDT 24
Finished Jun 05 06:00:16 PM PDT 24
Peak memory 269868 kb
Host smart-9f75a194-89ab-4c87-a6f2-ee1b1e61c88e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726394543 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.lc_ctrl_stress_all.1726394543
Directory /workspace/17.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.lc_ctrl_volatile_unlock_smoke.2901087117
Short name T510
Test name
Test status
Simulation time 13485669 ps
CPU time 1.06 seconds
Started Jun 05 05:59:07 PM PDT 24
Finished Jun 05 05:59:09 PM PDT 24
Peak memory 211572 kb
Host smart-5740ab13-ebc6-4b31-a4d5-9ca8683bb195
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901087117 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_c
trl_volatile_unlock_smoke.2901087117
Directory /workspace/17.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_alert_test.3558281976
Short name T705
Test name
Test status
Simulation time 67917165 ps
CPU time 0.92 seconds
Started Jun 05 05:59:28 PM PDT 24
Finished Jun 05 05:59:30 PM PDT 24
Peak memory 209536 kb
Host smart-0c2a4e41-bd74-4001-9256-508420ae43f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558281976 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_alert_test.3558281976
Directory /workspace/18.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.lc_ctrl_errors.2189411690
Short name T272
Test name
Test status
Simulation time 1199223366 ps
CPU time 12.42 seconds
Started Jun 05 05:59:16 PM PDT 24
Finished Jun 05 05:59:29 PM PDT 24
Peak memory 218128 kb
Host smart-fb00f7a9-efdb-4b82-b0db-181ad36d0307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189411690 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_errors.2189411690
Directory /workspace/18.lc_ctrl_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_access.2730493718
Short name T517
Test name
Test status
Simulation time 1398030825 ps
CPU time 5.16 seconds
Started Jun 05 05:59:26 PM PDT 24
Finished Jun 05 05:59:32 PM PDT 24
Peak memory 217028 kb
Host smart-0bee8922-0683-4393-b253-c1f07ed33b52
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730493718 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_access.2730493718
Directory /workspace/18.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_errors.490458215
Short name T808
Test name
Test status
Simulation time 9114120367 ps
CPU time 35.76 seconds
Started Jun 05 05:59:36 PM PDT 24
Finished Jun 05 06:00:12 PM PDT 24
Peak memory 218444 kb
Host smart-cd1c26df-8d05-44a4-8a09-957a40d86207
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490458215 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_er
rors.490458215
Directory /workspace/18.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_prog_failure.636541929
Short name T469
Test name
Test status
Simulation time 2007570919 ps
CPU time 7.82 seconds
Started Jun 05 05:59:30 PM PDT 24
Finished Jun 05 05:59:38 PM PDT 24
Peak memory 217968 kb
Host smart-0ccdbbeb-e9e3-43ce-b5a0-4258c21b0822
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636541929 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag
_prog_failure.636541929
Directory /workspace/18.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_smoke.3087544877
Short name T775
Test name
Test status
Simulation time 1165761360 ps
CPU time 6.54 seconds
Started Jun 05 05:59:20 PM PDT 24
Finished Jun 05 05:59:27 PM PDT 24
Peak memory 217708 kb
Host smart-5346e3c3-d80b-4efd-bf93-83b58787f7c9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087544877 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_smoke
.3087544877
Directory /workspace/18.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_failure.2604936028
Short name T673
Test name
Test status
Simulation time 8806027732 ps
CPU time 99.79 seconds
Started Jun 05 05:59:26 PM PDT 24
Finished Jun 05 06:01:06 PM PDT 24
Peak memory 283716 kb
Host smart-c289d2a2-acd1-4382-9fdb-11a84f1a7bb5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604936028 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jt
ag_state_failure.2604936028
Directory /workspace/18.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_post_trans.4228053429
Short name T849
Test name
Test status
Simulation time 1640848054 ps
CPU time 13.85 seconds
Started Jun 05 05:59:16 PM PDT 24
Finished Jun 05 05:59:31 PM PDT 24
Peak memory 223220 kb
Host smart-786c8285-7adc-485b-8d06-5a9ed00a11f5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228053429 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl
_jtag_state_post_trans.4228053429
Directory /workspace/18.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_prog_failure.2420784640
Short name T501
Test name
Test status
Simulation time 209704853 ps
CPU time 3.33 seconds
Started Jun 05 05:59:31 PM PDT 24
Finished Jun 05 05:59:35 PM PDT 24
Peak memory 218204 kb
Host smart-60ce5bdb-c23a-4d99-ba8a-299a37e06a7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420784640 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_prog_failure.2420784640
Directory /workspace/18.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_mubi.2871215601
Short name T553
Test name
Test status
Simulation time 634514087 ps
CPU time 14.19 seconds
Started Jun 05 05:59:23 PM PDT 24
Finished Jun 05 05:59:37 PM PDT 24
Peak memory 218996 kb
Host smart-1c4623ff-c1ed-4bdb-b11b-a934ba77a8ec
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871215601 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_mubi.2871215601
Directory /workspace/18.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_digest.3360354283
Short name T205
Test name
Test status
Simulation time 644063827 ps
CPU time 14.2 seconds
Started Jun 05 05:59:29 PM PDT 24
Finished Jun 05 05:59:44 PM PDT 24
Peak memory 217964 kb
Host smart-b9193be4-2794-4fe6-8beb-45102acd0074
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360354283 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_d
igest.3360354283
Directory /workspace/18.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_mux.691806641
Short name T169
Test name
Test status
Simulation time 210374199 ps
CPU time 6.74 seconds
Started Jun 05 05:59:16 PM PDT 24
Finished Jun 05 05:59:23 PM PDT 24
Peak memory 218112 kb
Host smart-7353279d-2872-4672-a7f1-c90ca06c964e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691806641 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_mux.691806641
Directory /workspace/18.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/18.lc_ctrl_security_escalation.2076274119
Short name T579
Test name
Test status
Simulation time 394835300 ps
CPU time 14.28 seconds
Started Jun 05 05:59:17 PM PDT 24
Finished Jun 05 05:59:32 PM PDT 24
Peak memory 218092 kb
Host smart-8ebd78c6-a693-4c09-8202-c515a0114593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076274119 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_security_escalation.2076274119
Directory /workspace/18.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/18.lc_ctrl_smoke.4174237619
Short name T812
Test name
Test status
Simulation time 101380784 ps
CPU time 1.7 seconds
Started Jun 05 05:59:27 PM PDT 24
Finished Jun 05 05:59:29 PM PDT 24
Peak memory 217744 kb
Host smart-a21da9a5-f096-4a36-9b46-a0816073a45b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174237619 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_smoke.4174237619
Directory /workspace/18.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_failure.332327472
Short name T395
Test name
Test status
Simulation time 640885921 ps
CPU time 26.34 seconds
Started Jun 05 05:59:17 PM PDT 24
Finished Jun 05 05:59:44 PM PDT 24
Peak memory 251040 kb
Host smart-db7f43c6-3731-477a-a9fe-80b9483864a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332327472 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_failure.332327472
Directory /workspace/18.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_post_trans.1038690895
Short name T221
Test name
Test status
Simulation time 57670096 ps
CPU time 7.03 seconds
Started Jun 05 05:59:30 PM PDT 24
Finished Jun 05 05:59:38 PM PDT 24
Peak memory 250584 kb
Host smart-9319cbb7-568f-46d0-993b-6cef590e688d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038690895 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_post_trans.1038690895
Directory /workspace/18.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all.2422085395
Short name T675
Test name
Test status
Simulation time 10290315290 ps
CPU time 100.13 seconds
Started Jun 05 05:59:25 PM PDT 24
Finished Jun 05 06:01:06 PM PDT 24
Peak memory 270680 kb
Host smart-45870182-77a7-43a3-ae10-97dbbe6e4f1d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422085395 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.lc_ctrl_stress_all.2422085395
Directory /workspace/18.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all_with_rand_reset.282970561
Short name T154
Test name
Test status
Simulation time 16991129860 ps
CPU time 364.12 seconds
Started Jun 05 05:59:15 PM PDT 24
Finished Jun 05 06:05:19 PM PDT 24
Peak memory 283948 kb
Host smart-bee1b8de-7ae7-41a9-adc7-208a6c2b30ef
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=282970561 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_stress_all_with_rand_reset.282970561
Directory /workspace/18.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.lc_ctrl_volatile_unlock_smoke.1824701691
Short name T419
Test name
Test status
Simulation time 11632165 ps
CPU time 0.89 seconds
Started Jun 05 05:59:19 PM PDT 24
Finished Jun 05 05:59:20 PM PDT 24
Peak memory 208320 kb
Host smart-68b83a52-834c-48ec-80a3-ef13da44e861
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824701691 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_c
trl_volatile_unlock_smoke.1824701691
Directory /workspace/18.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_errors.177237142
Short name T98
Test name
Test status
Simulation time 468378960 ps
CPU time 15.44 seconds
Started Jun 05 05:59:30 PM PDT 24
Finished Jun 05 05:59:47 PM PDT 24
Peak memory 218020 kb
Host smart-6aa5c0f0-7b02-4b22-863d-21d8922b8eec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177237142 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_errors.177237142
Directory /workspace/19.lc_ctrl_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_access.1676724568
Short name T407
Test name
Test status
Simulation time 688753167 ps
CPU time 4.33 seconds
Started Jun 05 05:59:13 PM PDT 24
Finished Jun 05 05:59:18 PM PDT 24
Peak memory 209632 kb
Host smart-911e8b1f-55d4-4ab5-a74f-a1e34ad8439b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676724568 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_access.1676724568
Directory /workspace/19.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_errors.1637255985
Short name T628
Test name
Test status
Simulation time 8758357971 ps
CPU time 58.48 seconds
Started Jun 05 05:59:26 PM PDT 24
Finished Jun 05 06:00:25 PM PDT 24
Peak memory 218600 kb
Host smart-e6f5b145-852e-4c50-8830-25177ada2b9e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637255985 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_e
rrors.1637255985
Directory /workspace/19.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_prog_failure.2455347244
Short name T294
Test name
Test status
Simulation time 2875785015 ps
CPU time 11.36 seconds
Started Jun 05 05:59:33 PM PDT 24
Finished Jun 05 05:59:45 PM PDT 24
Peak memory 218012 kb
Host smart-e5192d3d-6bfa-4e8d-a5eb-6e5a4b666141
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455347244 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jta
g_prog_failure.2455347244
Directory /workspace/19.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_smoke.748015244
Short name T433
Test name
Test status
Simulation time 383806680 ps
CPU time 10.48 seconds
Started Jun 05 05:59:28 PM PDT 24
Finished Jun 05 05:59:39 PM PDT 24
Peak memory 217676 kb
Host smart-e3aa32e1-9cac-4849-a994-e5c865b6f4f1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748015244 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_smoke.
748015244
Directory /workspace/19.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_failure.2315872095
Short name T367
Test name
Test status
Simulation time 1647374641 ps
CPU time 37.87 seconds
Started Jun 05 05:59:29 PM PDT 24
Finished Jun 05 06:00:08 PM PDT 24
Peak memory 272100 kb
Host smart-24acfd4e-13d7-48f2-8273-e5136903bf38
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315872095 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jt
ag_state_failure.2315872095
Directory /workspace/19.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_post_trans.2975960308
Short name T776
Test name
Test status
Simulation time 1431683189 ps
CPU time 12.36 seconds
Started Jun 05 05:59:29 PM PDT 24
Finished Jun 05 05:59:42 PM PDT 24
Peak memory 222996 kb
Host smart-c2e6a5b4-182f-4717-aa4f-ace0ea7edd4f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975960308 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl
_jtag_state_post_trans.2975960308
Directory /workspace/19.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_prog_failure.313234841
Short name T9
Test name
Test status
Simulation time 65689855 ps
CPU time 1.78 seconds
Started Jun 05 05:59:20 PM PDT 24
Finished Jun 05 05:59:23 PM PDT 24
Peak memory 218048 kb
Host smart-1c65a1a1-98ee-47a7-93ad-4cc50c2a5d57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=313234841 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_prog_failure.313234841
Directory /workspace/19.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_digest.1542981820
Short name T381
Test name
Test status
Simulation time 1043380854 ps
CPU time 16.99 seconds
Started Jun 05 05:59:30 PM PDT 24
Finished Jun 05 05:59:48 PM PDT 24
Peak memory 225876 kb
Host smart-a873cb90-b5ce-4d52-a441-e552c95b6b86
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542981820 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_d
igest.1542981820
Directory /workspace/19.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_mux.2595140212
Short name T311
Test name
Test status
Simulation time 1603773060 ps
CPU time 6.13 seconds
Started Jun 05 05:59:22 PM PDT 24
Finished Jun 05 05:59:28 PM PDT 24
Peak memory 218144 kb
Host smart-67dd65af-b6e6-4bd0-879e-8b8ab88746a6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595140212 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_mux.
2595140212
Directory /workspace/19.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/19.lc_ctrl_security_escalation.218661104
Short name T356
Test name
Test status
Simulation time 535490343 ps
CPU time 8.59 seconds
Started Jun 05 05:59:27 PM PDT 24
Finished Jun 05 05:59:36 PM PDT 24
Peak memory 218200 kb
Host smart-3a802300-e1ed-4e6e-aa6a-23749eec506b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218661104 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_security_escalation.218661104
Directory /workspace/19.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/19.lc_ctrl_smoke.2584175709
Short name T550
Test name
Test status
Simulation time 189468662 ps
CPU time 3.13 seconds
Started Jun 05 05:59:26 PM PDT 24
Finished Jun 05 05:59:30 PM PDT 24
Peak memory 218288 kb
Host smart-3c0b7250-0ec5-41f7-b654-e6d23bfa55e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584175709 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_smoke.2584175709
Directory /workspace/19.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_failure.819071745
Short name T94
Test name
Test status
Simulation time 877748863 ps
CPU time 26.25 seconds
Started Jun 05 05:59:26 PM PDT 24
Finished Jun 05 05:59:53 PM PDT 24
Peak memory 251056 kb
Host smart-3b103711-c427-4879-8050-8b3bba8c790b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819071745 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_failure.819071745
Directory /workspace/19.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_post_trans.2361605731
Short name T455
Test name
Test status
Simulation time 48925049 ps
CPU time 7.44 seconds
Started Jun 05 05:59:30 PM PDT 24
Finished Jun 05 05:59:38 PM PDT 24
Peak memory 251020 kb
Host smart-d839d816-c249-479b-be50-5b606aee41a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361605731 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_post_trans.2361605731
Directory /workspace/19.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all.4229711480
Short name T299
Test name
Test status
Simulation time 2700486556 ps
CPU time 38.28 seconds
Started Jun 05 05:59:28 PM PDT 24
Finished Jun 05 06:00:07 PM PDT 24
Peak memory 251060 kb
Host smart-a0ed1b12-c970-478e-a084-770c1d2edeb6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229711480 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.lc_ctrl_stress_all.4229711480
Directory /workspace/19.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.lc_ctrl_volatile_unlock_smoke.2605988516
Short name T863
Test name
Test status
Simulation time 22788776 ps
CPU time 1.03 seconds
Started Jun 05 05:59:16 PM PDT 24
Finished Jun 05 05:59:17 PM PDT 24
Peak memory 211640 kb
Host smart-ea097faf-c6b2-406e-b0ed-c0678bb49bf2
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605988516 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_c
trl_volatile_unlock_smoke.2605988516
Directory /workspace/19.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_alert_test.2577248792
Short name T459
Test name
Test status
Simulation time 26392993 ps
CPU time 1.26 seconds
Started Jun 05 05:58:45 PM PDT 24
Finished Jun 05 05:58:48 PM PDT 24
Peak memory 208628 kb
Host smart-5ff370aa-3cad-4bb6-9d7b-3d5321de812c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577248792 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_alert_test.2577248792
Directory /workspace/2.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.lc_ctrl_claim_transition_if.3984204988
Short name T717
Test name
Test status
Simulation time 47012712 ps
CPU time 0.78 seconds
Started Jun 05 05:58:40 PM PDT 24
Finished Jun 05 05:58:42 PM PDT 24
Peak memory 208684 kb
Host smart-ff2e614f-464c-46a5-88ba-0a2dd197467e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984204988 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_claim_transition_if.3984204988
Directory /workspace/2.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/2.lc_ctrl_errors.2832312420
Short name T423
Test name
Test status
Simulation time 4056399981 ps
CPU time 19.79 seconds
Started Jun 05 05:58:44 PM PDT 24
Finished Jun 05 05:59:06 PM PDT 24
Peak memory 219164 kb
Host smart-8d6d2cf5-1976-4118-b473-ca6737a26fc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832312420 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_errors.2832312420
Directory /workspace/2.lc_ctrl_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_access.2927353880
Short name T23
Test name
Test status
Simulation time 502453148 ps
CPU time 6.58 seconds
Started Jun 05 05:58:39 PM PDT 24
Finished Jun 05 05:58:47 PM PDT 24
Peak memory 209576 kb
Host smart-a10953cb-1337-41a8-a399-7c506440a6c9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927353880 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_access.2927353880
Directory /workspace/2.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_errors.1774021532
Short name T19
Test name
Test status
Simulation time 3516363925 ps
CPU time 30.22 seconds
Started Jun 05 05:58:39 PM PDT 24
Finished Jun 05 05:59:10 PM PDT 24
Peak memory 218368 kb
Host smart-087062ba-2512-466a-b8e1-6f46c2a0c250
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774021532 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_er
rors.1774021532
Directory /workspace/2.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_priority.821964200
Short name T852
Test name
Test status
Simulation time 462494207 ps
CPU time 3.34 seconds
Started Jun 05 05:58:37 PM PDT 24
Finished Jun 05 05:58:42 PM PDT 24
Peak memory 217076 kb
Host smart-53398641-2c4f-4c73-881b-e87d92ccdbd4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821964200 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_priority.821964200
Directory /workspace/2.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_prog_failure.2417992044
Short name T201
Test name
Test status
Simulation time 952924419 ps
CPU time 12.01 seconds
Started Jun 05 05:58:34 PM PDT 24
Finished Jun 05 05:58:47 PM PDT 24
Peak memory 218124 kb
Host smart-2a65dbe6-e1ac-4d21-a475-4569538a21e9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417992044 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag
_prog_failure.2417992044
Directory /workspace/2.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_regwen_during_op.4253610731
Short name T410
Test name
Test status
Simulation time 1070946904 ps
CPU time 15.41 seconds
Started Jun 05 05:58:39 PM PDT 24
Finished Jun 05 05:58:55 PM PDT 24
Peak memory 217700 kb
Host smart-0a25ff75-00df-43d8-a633-d38f66166c58
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253610731 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_regwen_during_op.4253610731
Directory /workspace/2.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_smoke.2949516564
Short name T322
Test name
Test status
Simulation time 144496629 ps
CPU time 2.8 seconds
Started Jun 05 05:58:40 PM PDT 24
Finished Jun 05 05:58:44 PM PDT 24
Peak memory 217736 kb
Host smart-3749462f-830e-46c9-a676-e60f8224379f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949516564 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_smoke.
2949516564
Directory /workspace/2.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_failure.3993219435
Short name T382
Test name
Test status
Simulation time 1206300347 ps
CPU time 54.43 seconds
Started Jun 05 05:58:40 PM PDT 24
Finished Jun 05 05:59:35 PM PDT 24
Peak memory 267364 kb
Host smart-bf6f6a75-6d2e-4fcf-8bdd-7f7d7b0b2eb9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993219435 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jta
g_state_failure.3993219435
Directory /workspace/2.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_post_trans.3246280657
Short name T841
Test name
Test status
Simulation time 3118770332 ps
CPU time 16.44 seconds
Started Jun 05 05:58:40 PM PDT 24
Finished Jun 05 05:58:58 PM PDT 24
Peak memory 250620 kb
Host smart-1a3ce34a-8f09-4685-885e-6b48768937be
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246280657 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_state_post_trans.3246280657
Directory /workspace/2.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_prog_failure.2805001970
Short name T235
Test name
Test status
Simulation time 117445204 ps
CPU time 5.03 seconds
Started Jun 05 05:58:38 PM PDT 24
Finished Jun 05 05:58:44 PM PDT 24
Peak memory 217764 kb
Host smart-b05400d9-85da-4d2d-9276-211a80a4911c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805001970 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_prog_failure.2805001970
Directory /workspace/2.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_regwen_during_op.3813494681
Short name T104
Test name
Test status
Simulation time 505423293 ps
CPU time 6.14 seconds
Started Jun 05 05:58:34 PM PDT 24
Finished Jun 05 05:58:42 PM PDT 24
Peak memory 217760 kb
Host smart-74c90e13-528d-4488-bf7a-3137b12d23c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813494681 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_regwen_during_op.3813494681
Directory /workspace/2.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_cm.2978847297
Short name T47
Test name
Test status
Simulation time 470812963 ps
CPU time 43.51 seconds
Started Jun 05 05:58:48 PM PDT 24
Finished Jun 05 05:59:34 PM PDT 24
Peak memory 392216 kb
Host smart-682d46ab-a5d9-4249-9af8-987ee40fda47
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978847297 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_cm.2978847297
Directory /workspace/2.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_mubi.793244320
Short name T512
Test name
Test status
Simulation time 307085580 ps
CPU time 14.14 seconds
Started Jun 05 05:58:40 PM PDT 24
Finished Jun 05 05:58:56 PM PDT 24
Peak memory 219012 kb
Host smart-770985ab-bb65-4c59-8a3f-591035114e3b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793244320 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_mubi.793244320
Directory /workspace/2.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_digest.639142353
Short name T500
Test name
Test status
Simulation time 1175220273 ps
CPU time 13.63 seconds
Started Jun 05 05:58:45 PM PDT 24
Finished Jun 05 05:59:01 PM PDT 24
Peak memory 225820 kb
Host smart-127436e3-b987-43c1-a31d-2836b59031f7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639142353 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_dig
est.639142353
Directory /workspace/2.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_mux.635932355
Short name T827
Test name
Test status
Simulation time 411133602 ps
CPU time 9.72 seconds
Started Jun 05 05:58:38 PM PDT 24
Finished Jun 05 05:58:49 PM PDT 24
Peak memory 217804 kb
Host smart-42169364-d84c-43d1-a0f9-1635fad58abe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635932355 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_mux.635932355
Directory /workspace/2.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/2.lc_ctrl_security_escalation.3769455344
Short name T346
Test name
Test status
Simulation time 778128609 ps
CPU time 8.17 seconds
Started Jun 05 05:58:35 PM PDT 24
Finished Jun 05 05:58:45 PM PDT 24
Peak memory 218168 kb
Host smart-f45be9bf-652f-4716-aca4-d097174b5517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769455344 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_security_escalation.3769455344
Directory /workspace/2.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/2.lc_ctrl_smoke.2213244742
Short name T646
Test name
Test status
Simulation time 63272933 ps
CPU time 2.91 seconds
Started Jun 05 05:58:46 PM PDT 24
Finished Jun 05 05:58:51 PM PDT 24
Peak memory 217764 kb
Host smart-b8cf236a-c174-4baa-9a79-b258e63d8b85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213244742 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_smoke.2213244742
Directory /workspace/2.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_failure.4078019389
Short name T821
Test name
Test status
Simulation time 1552601280 ps
CPU time 35.39 seconds
Started Jun 05 05:58:44 PM PDT 24
Finished Jun 05 05:59:22 PM PDT 24
Peak memory 251020 kb
Host smart-41539e2d-c100-45ed-afe1-3eb58ac20300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078019389 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_failure.4078019389
Directory /workspace/2.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_post_trans.3572789627
Short name T465
Test name
Test status
Simulation time 108570120 ps
CPU time 8.12 seconds
Started Jun 05 05:58:35 PM PDT 24
Finished Jun 05 05:58:44 PM PDT 24
Peak memory 250936 kb
Host smart-c944906f-9032-4755-a687-db4a7e4ca4ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572789627 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_post_trans.3572789627
Directory /workspace/2.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all.1793327952
Short name T393
Test name
Test status
Simulation time 17354519925 ps
CPU time 214.2 seconds
Started Jun 05 05:58:44 PM PDT 24
Finished Jun 05 06:02:21 PM PDT 24
Peak memory 278960 kb
Host smart-8bdffe93-0acd-4ef1-a6b6-9bc3f776540e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793327952 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.lc_ctrl_stress_all.1793327952
Directory /workspace/2.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all_with_rand_reset.720343608
Short name T534
Test name
Test status
Simulation time 31093908678 ps
CPU time 1039.53 seconds
Started Jun 05 05:58:34 PM PDT 24
Finished Jun 05 06:15:54 PM PDT 24
Peak memory 523608 kb
Host smart-f8bbdabd-90ce-45b1-9b18-6649b9e5fa28
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=720343608 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_stress_all_with_rand_reset.720343608
Directory /workspace/2.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.lc_ctrl_volatile_unlock_smoke.776900778
Short name T74
Test name
Test status
Simulation time 28331282 ps
CPU time 1.71 seconds
Started Jun 05 05:58:41 PM PDT 24
Finished Jun 05 05:58:44 PM PDT 24
Peak memory 217696 kb
Host smart-4bab21fc-fede-4f6e-a482-08e8a589f24b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776900778 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctr
l_volatile_unlock_smoke.776900778
Directory /workspace/2.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_alert_test.2430747136
Short name T364
Test name
Test status
Simulation time 70537647 ps
CPU time 1.05 seconds
Started Jun 05 05:59:30 PM PDT 24
Finished Jun 05 05:59:32 PM PDT 24
Peak memory 208704 kb
Host smart-98d2f8a1-f06f-4eb3-8be7-66428a669b2d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430747136 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_alert_test.2430747136
Directory /workspace/20.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.lc_ctrl_errors.2027954202
Short name T728
Test name
Test status
Simulation time 343725628 ps
CPU time 13.92 seconds
Started Jun 05 05:59:31 PM PDT 24
Finished Jun 05 05:59:46 PM PDT 24
Peak memory 218052 kb
Host smart-e79ed1be-1009-41f9-9439-d35b95524f0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027954202 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_errors.2027954202
Directory /workspace/20.lc_ctrl_errors/latest

Test location /workspace/coverage/default/20.lc_ctrl_prog_failure.4235274928
Short name T865
Test name
Test status
Simulation time 2391869018 ps
CPU time 5.07 seconds
Started Jun 05 05:59:28 PM PDT 24
Finished Jun 05 05:59:34 PM PDT 24
Peak memory 218128 kb
Host smart-996b5f1f-5c8e-4af6-a122-36dc2a4aac4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235274928 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_prog_failure.4235274928
Directory /workspace/20.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_mubi.3892942720
Short name T511
Test name
Test status
Simulation time 337411602 ps
CPU time 16.66 seconds
Started Jun 05 05:59:34 PM PDT 24
Finished Jun 05 05:59:51 PM PDT 24
Peak memory 226132 kb
Host smart-55e21917-c805-4955-8612-2a182166cb95
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892942720 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_mubi.3892942720
Directory /workspace/20.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_digest.969171523
Short name T751
Test name
Test status
Simulation time 730559803 ps
CPU time 17.83 seconds
Started Jun 05 05:59:19 PM PDT 24
Finished Jun 05 05:59:37 PM PDT 24
Peak memory 217976 kb
Host smart-3d0ff8ed-6852-4203-abb5-bbcf706cc9ae
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969171523 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_di
gest.969171523
Directory /workspace/20.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_mux.4294887414
Short name T638
Test name
Test status
Simulation time 1114330120 ps
CPU time 11.16 seconds
Started Jun 05 05:59:27 PM PDT 24
Finished Jun 05 05:59:39 PM PDT 24
Peak memory 218116 kb
Host smart-0298b557-6f7f-4a03-8099-e8e463b8b7ef
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294887414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_mux.
4294887414
Directory /workspace/20.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/20.lc_ctrl_security_escalation.2352565267
Short name T337
Test name
Test status
Simulation time 448222389 ps
CPU time 14.88 seconds
Started Jun 05 05:59:33 PM PDT 24
Finished Jun 05 05:59:48 PM PDT 24
Peak memory 226112 kb
Host smart-4d34deed-47f8-4ab1-9b82-11a5682c0455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352565267 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_security_escalation.2352565267
Directory /workspace/20.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/20.lc_ctrl_smoke.478664490
Short name T647
Test name
Test status
Simulation time 84734527 ps
CPU time 3.28 seconds
Started Jun 05 05:59:24 PM PDT 24
Finished Jun 05 05:59:28 PM PDT 24
Peak memory 217788 kb
Host smart-09d1197c-2013-49db-a555-c77581764d94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478664490 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_smoke.478664490
Directory /workspace/20.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_failure.2429301404
Short name T779
Test name
Test status
Simulation time 792553664 ps
CPU time 20.61 seconds
Started Jun 05 05:59:35 PM PDT 24
Finished Jun 05 05:59:57 PM PDT 24
Peak memory 251124 kb
Host smart-e15aa80d-a917-4fea-b206-6094dc3b0f29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429301404 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_failure.2429301404
Directory /workspace/20.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_post_trans.2690741868
Short name T561
Test name
Test status
Simulation time 154943795 ps
CPU time 6.45 seconds
Started Jun 05 05:59:18 PM PDT 24
Finished Jun 05 05:59:25 PM PDT 24
Peak memory 247316 kb
Host smart-1c99913a-1cc1-4299-b90c-4f39647e3ed7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690741868 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_post_trans.2690741868
Directory /workspace/20.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/20.lc_ctrl_stress_all.4117303006
Short name T79
Test name
Test status
Simulation time 7846120298 ps
CPU time 35.48 seconds
Started Jun 05 05:59:29 PM PDT 24
Finished Jun 05 06:00:05 PM PDT 24
Peak memory 218316 kb
Host smart-09eedf94-de75-4ece-bade-04c819f0ed2c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117303006 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.lc_ctrl_stress_all.4117303006
Directory /workspace/20.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.lc_ctrl_volatile_unlock_smoke.3165601280
Short name T69
Test name
Test status
Simulation time 13475398 ps
CPU time 1.14 seconds
Started Jun 05 05:59:16 PM PDT 24
Finished Jun 05 05:59:18 PM PDT 24
Peak memory 211644 kb
Host smart-6b1d5c48-cd19-4ff7-b408-8748c144a308
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165601280 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_c
trl_volatile_unlock_smoke.3165601280
Directory /workspace/20.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_alert_test.3731329619
Short name T456
Test name
Test status
Simulation time 18175629 ps
CPU time 1.12 seconds
Started Jun 05 05:59:35 PM PDT 24
Finished Jun 05 05:59:37 PM PDT 24
Peak memory 209568 kb
Host smart-a12ef120-1ec4-4dde-b8ef-57daf662c7f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731329619 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_alert_test.3731329619
Directory /workspace/21.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.lc_ctrl_errors.2743727311
Short name T707
Test name
Test status
Simulation time 448563988 ps
CPU time 9.58 seconds
Started Jun 05 05:59:24 PM PDT 24
Finished Jun 05 05:59:34 PM PDT 24
Peak memory 218044 kb
Host smart-7a017cfe-5992-4dc6-ad8f-34ba7d4f3eb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743727311 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_errors.2743727311
Directory /workspace/21.lc_ctrl_errors/latest

Test location /workspace/coverage/default/21.lc_ctrl_jtag_access.4277199923
Short name T362
Test name
Test status
Simulation time 885698592 ps
CPU time 2.91 seconds
Started Jun 05 05:59:29 PM PDT 24
Finished Jun 05 05:59:32 PM PDT 24
Peak memory 209556 kb
Host smart-98cf57aa-3ece-4131-a6fc-edbaba327f66
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277199923 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_jtag_access.4277199923
Directory /workspace/21.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/21.lc_ctrl_prog_failure.450647191
Short name T801
Test name
Test status
Simulation time 170866316 ps
CPU time 2.26 seconds
Started Jun 05 05:59:34 PM PDT 24
Finished Jun 05 05:59:36 PM PDT 24
Peak memory 218044 kb
Host smart-b40cb8c9-bfbc-4c7a-bb93-6be823484b36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450647191 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_prog_failure.450647191
Directory /workspace/21.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_mubi.95516353
Short name T313
Test name
Test status
Simulation time 603397319 ps
CPU time 11.28 seconds
Started Jun 05 05:59:29 PM PDT 24
Finished Jun 05 05:59:41 PM PDT 24
Peak memory 226132 kb
Host smart-9bc167b6-fe69-4b9b-9f9c-e6e7abd14a8b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95516353 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_mubi.95516353
Directory /workspace/21.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_digest.892514908
Short name T301
Test name
Test status
Simulation time 1175311464 ps
CPU time 28.46 seconds
Started Jun 05 05:59:23 PM PDT 24
Finished Jun 05 05:59:52 PM PDT 24
Peak memory 226064 kb
Host smart-85087139-6334-4753-a091-c47eaf6e319d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892514908 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_di
gest.892514908
Directory /workspace/21.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_mux.726528659
Short name T493
Test name
Test status
Simulation time 812890243 ps
CPU time 16.25 seconds
Started Jun 05 05:59:21 PM PDT 24
Finished Jun 05 05:59:38 PM PDT 24
Peak memory 218204 kb
Host smart-4e75bb91-5c36-4ff8-bd17-3f26c462a584
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726528659 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_mux.726528659
Directory /workspace/21.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/21.lc_ctrl_smoke.1573616800
Short name T738
Test name
Test status
Simulation time 186189327 ps
CPU time 3.41 seconds
Started Jun 05 05:59:25 PM PDT 24
Finished Jun 05 05:59:29 PM PDT 24
Peak memory 214324 kb
Host smart-59f42d04-a784-4927-8606-24f65a9b3b8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573616800 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_smoke.1573616800
Directory /workspace/21.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_failure.1517765390
Short name T702
Test name
Test status
Simulation time 2228527620 ps
CPU time 23.21 seconds
Started Jun 05 05:59:29 PM PDT 24
Finished Jun 05 05:59:53 PM PDT 24
Peak memory 251092 kb
Host smart-e679c6b0-e149-4889-9198-1f03b3cef16e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517765390 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_failure.1517765390
Directory /workspace/21.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_post_trans.2934823151
Short name T861
Test name
Test status
Simulation time 57478496 ps
CPU time 6.95 seconds
Started Jun 05 05:59:30 PM PDT 24
Finished Jun 05 05:59:38 PM PDT 24
Peak memory 251028 kb
Host smart-62a4665c-fc39-4f3e-a191-4aab6608ca5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934823151 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_post_trans.2934823151
Directory /workspace/21.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/21.lc_ctrl_stress_all.2746800053
Short name T624
Test name
Test status
Simulation time 9445883809 ps
CPU time 322.37 seconds
Started Jun 05 05:59:26 PM PDT 24
Finished Jun 05 06:04:49 PM PDT 24
Peak memory 280856 kb
Host smart-7c9df10c-3e54-45b1-845d-72b652741827
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746800053 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.lc_ctrl_stress_all.2746800053
Directory /workspace/21.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.lc_ctrl_stress_all_with_rand_reset.1800389688
Short name T538
Test name
Test status
Simulation time 82908507287 ps
CPU time 619.58 seconds
Started Jun 05 05:59:27 PM PDT 24
Finished Jun 05 06:09:48 PM PDT 24
Peak memory 443784 kb
Host smart-5826e25e-b148-491e-b7eb-a2ad94547939
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1800389688 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_stress_all_with_rand_reset.1800389688
Directory /workspace/21.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.lc_ctrl_volatile_unlock_smoke.1439913349
Short name T513
Test name
Test status
Simulation time 10810826 ps
CPU time 1.07 seconds
Started Jun 05 05:59:30 PM PDT 24
Finished Jun 05 05:59:32 PM PDT 24
Peak memory 211612 kb
Host smart-97059b44-b8b3-4553-a601-bd110abf1eff
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439913349 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_c
trl_volatile_unlock_smoke.1439913349
Directory /workspace/21.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_alert_test.2413585498
Short name T355
Test name
Test status
Simulation time 30771275 ps
CPU time 1.07 seconds
Started Jun 05 05:59:41 PM PDT 24
Finished Jun 05 05:59:43 PM PDT 24
Peak memory 208732 kb
Host smart-4c30c3a6-f40f-48cd-a5a5-4ae7e795e7a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413585498 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_alert_test.2413585498
Directory /workspace/22.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.lc_ctrl_errors.2271886545
Short name T846
Test name
Test status
Simulation time 220650448 ps
CPU time 11.11 seconds
Started Jun 05 05:59:27 PM PDT 24
Finished Jun 05 05:59:39 PM PDT 24
Peak memory 217960 kb
Host smart-9d5a3fbe-48e7-4f88-b85b-5735335b1ab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271886545 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_errors.2271886545
Directory /workspace/22.lc_ctrl_errors/latest

Test location /workspace/coverage/default/22.lc_ctrl_jtag_access.1030504503
Short name T851
Test name
Test status
Simulation time 473910003 ps
CPU time 6.92 seconds
Started Jun 05 05:59:27 PM PDT 24
Finished Jun 05 05:59:35 PM PDT 24
Peak memory 217064 kb
Host smart-6e25ff7d-c8a4-40d6-a5b2-cdab1b69b7f8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030504503 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_jtag_access.1030504503
Directory /workspace/22.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/22.lc_ctrl_prog_failure.4235089228
Short name T261
Test name
Test status
Simulation time 106432780 ps
CPU time 2.62 seconds
Started Jun 05 05:59:29 PM PDT 24
Finished Jun 05 05:59:32 PM PDT 24
Peak memory 218112 kb
Host smart-f06b5124-edd5-4730-94af-0322a2e3d347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235089228 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_prog_failure.4235089228
Directory /workspace/22.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_mubi.1539324673
Short name T842
Test name
Test status
Simulation time 288117250 ps
CPU time 13.2 seconds
Started Jun 05 05:59:26 PM PDT 24
Finished Jun 05 05:59:40 PM PDT 24
Peak memory 226120 kb
Host smart-8add5dee-4cf9-4756-8f87-23d9dcbf5866
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539324673 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_mubi.1539324673
Directory /workspace/22.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_digest.101771724
Short name T126
Test name
Test status
Simulation time 383617650 ps
CPU time 15.6 seconds
Started Jun 05 05:59:26 PM PDT 24
Finished Jun 05 05:59:42 PM PDT 24
Peak memory 226108 kb
Host smart-cce6bb5d-46f4-4d4c-9242-c7b0713e34ec
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101771724 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_di
gest.101771724
Directory /workspace/22.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_mux.2793547526
Short name T273
Test name
Test status
Simulation time 614351547 ps
CPU time 11.39 seconds
Started Jun 05 05:59:19 PM PDT 24
Finished Jun 05 05:59:31 PM PDT 24
Peak memory 218148 kb
Host smart-27b97608-e4f4-4c0a-8688-3286c73695dd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793547526 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_mux.
2793547526
Directory /workspace/22.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/22.lc_ctrl_security_escalation.80958242
Short name T589
Test name
Test status
Simulation time 422401810 ps
CPU time 9.95 seconds
Started Jun 05 05:59:30 PM PDT 24
Finished Jun 05 05:59:41 PM PDT 24
Peak memory 218160 kb
Host smart-0c0f4297-28da-4800-b22b-4bd9e0a00ae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80958242 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_security_escalation.80958242
Directory /workspace/22.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/22.lc_ctrl_smoke.3331396721
Short name T726
Test name
Test status
Simulation time 60260419 ps
CPU time 1.19 seconds
Started Jun 05 05:59:28 PM PDT 24
Finished Jun 05 05:59:30 PM PDT 24
Peak memory 213452 kb
Host smart-0e354375-5386-4000-8148-b29159ece75e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331396721 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_smoke.3331396721
Directory /workspace/22.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_failure.375921510
Short name T90
Test name
Test status
Simulation time 181009242 ps
CPU time 20.69 seconds
Started Jun 05 05:59:35 PM PDT 24
Finished Jun 05 05:59:56 PM PDT 24
Peak memory 251000 kb
Host smart-1de5d07b-984d-4953-90d7-ec41536f4d64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375921510 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_failure.375921510
Directory /workspace/22.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_post_trans.2019313667
Short name T422
Test name
Test status
Simulation time 1291543820 ps
CPU time 6.81 seconds
Started Jun 05 05:59:36 PM PDT 24
Finished Jun 05 05:59:44 PM PDT 24
Peak memory 250392 kb
Host smart-3c82d77f-5e3c-44b1-b2b1-888b9e39bd36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019313667 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_post_trans.2019313667
Directory /workspace/22.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/22.lc_ctrl_stress_all.675124859
Short name T290
Test name
Test status
Simulation time 21359726208 ps
CPU time 194.02 seconds
Started Jun 05 05:59:34 PM PDT 24
Finished Jun 05 06:02:49 PM PDT 24
Peak memory 275656 kb
Host smart-c4be7ca7-3370-401e-9370-b7fa1211130b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675124859 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.lc_ctrl_stress_all.675124859
Directory /workspace/22.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.lc_ctrl_stress_all_with_rand_reset.1550530925
Short name T63
Test name
Test status
Simulation time 149470047876 ps
CPU time 685.06 seconds
Started Jun 05 05:59:29 PM PDT 24
Finished Jun 05 06:10:55 PM PDT 24
Peak memory 438576 kb
Host smart-9f31357c-9c61-4a0a-8072-8d7dd4ed313b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1550530925 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_stress_all_with_rand_reset.1550530925
Directory /workspace/22.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.lc_ctrl_volatile_unlock_smoke.2234012600
Short name T254
Test name
Test status
Simulation time 29306951 ps
CPU time 0.8 seconds
Started Jun 05 05:59:20 PM PDT 24
Finished Jun 05 05:59:21 PM PDT 24
Peak memory 208496 kb
Host smart-47eed768-527e-439d-831a-f4698719717b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234012600 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_c
trl_volatile_unlock_smoke.2234012600
Directory /workspace/22.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_alert_test.577160147
Short name T85
Test name
Test status
Simulation time 19585605 ps
CPU time 0.9 seconds
Started Jun 05 05:59:31 PM PDT 24
Finished Jun 05 05:59:32 PM PDT 24
Peak memory 209576 kb
Host smart-0b8501bc-fe27-417b-ae96-b8deceb8138e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577160147 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_alert_test.577160147
Directory /workspace/23.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.lc_ctrl_errors.2341804968
Short name T487
Test name
Test status
Simulation time 1252517644 ps
CPU time 19.32 seconds
Started Jun 05 05:59:36 PM PDT 24
Finished Jun 05 05:59:57 PM PDT 24
Peak memory 218104 kb
Host smart-c12bbc29-6cb8-434a-8c23-94ad5b8b31e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341804968 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_errors.2341804968
Directory /workspace/23.lc_ctrl_errors/latest

Test location /workspace/coverage/default/23.lc_ctrl_jtag_access.1765163798
Short name T568
Test name
Test status
Simulation time 1233386375 ps
CPU time 11.82 seconds
Started Jun 05 05:59:39 PM PDT 24
Finished Jun 05 05:59:52 PM PDT 24
Peak memory 209588 kb
Host smart-96bf2172-f4b1-49e9-816a-27c39cc70f6e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765163798 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_jtag_access.1765163798
Directory /workspace/23.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/23.lc_ctrl_prog_failure.4281131424
Short name T409
Test name
Test status
Simulation time 95388018 ps
CPU time 4.09 seconds
Started Jun 05 05:59:35 PM PDT 24
Finished Jun 05 05:59:40 PM PDT 24
Peak memory 218012 kb
Host smart-779ff4fb-733d-49d7-87bd-c7e55af5562b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281131424 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_prog_failure.4281131424
Directory /workspace/23.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_mubi.2432796951
Short name T417
Test name
Test status
Simulation time 1969027665 ps
CPU time 12.86 seconds
Started Jun 05 05:59:35 PM PDT 24
Finished Jun 05 05:59:48 PM PDT 24
Peak memory 218264 kb
Host smart-9da6ba6d-9278-4d88-80e3-5f03e759e473
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432796951 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_mubi.2432796951
Directory /workspace/23.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_digest.3840935187
Short name T405
Test name
Test status
Simulation time 414707460 ps
CPU time 12.54 seconds
Started Jun 05 05:59:34 PM PDT 24
Finished Jun 05 05:59:47 PM PDT 24
Peak memory 217980 kb
Host smart-cd684df8-7e46-4ae3-881d-87dad80d910e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840935187 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_d
igest.3840935187
Directory /workspace/23.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_mux.42958923
Short name T575
Test name
Test status
Simulation time 796051907 ps
CPU time 10.04 seconds
Started Jun 05 05:59:36 PM PDT 24
Finished Jun 05 05:59:47 PM PDT 24
Peak memory 218124 kb
Host smart-4baa28bf-ad10-4511-b7d2-1619954ecdb6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42958923 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_mux.42958923
Directory /workspace/23.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/23.lc_ctrl_security_escalation.710471100
Short name T388
Test name
Test status
Simulation time 341155567 ps
CPU time 12.44 seconds
Started Jun 05 05:59:29 PM PDT 24
Finished Jun 05 05:59:42 PM PDT 24
Peak memory 218168 kb
Host smart-6d513023-68ef-4662-9541-5b10dae0550a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710471100 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_security_escalation.710471100
Directory /workspace/23.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/23.lc_ctrl_smoke.4106834042
Short name T494
Test name
Test status
Simulation time 213479241 ps
CPU time 2.32 seconds
Started Jun 05 05:59:37 PM PDT 24
Finished Jun 05 05:59:40 PM PDT 24
Peak memory 214384 kb
Host smart-66ea7403-ab49-4bb7-a04b-b26b57dad76b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106834042 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_smoke.4106834042
Directory /workspace/23.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_failure.3124570687
Short name T496
Test name
Test status
Simulation time 2059761437 ps
CPU time 23.76 seconds
Started Jun 05 05:59:30 PM PDT 24
Finished Jun 05 05:59:55 PM PDT 24
Peak memory 246376 kb
Host smart-728a2c8b-d0de-4ff8-abe0-3ae93de0fb01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124570687 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_failure.3124570687
Directory /workspace/23.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_post_trans.3354019821
Short name T626
Test name
Test status
Simulation time 188601032 ps
CPU time 8.18 seconds
Started Jun 05 05:59:27 PM PDT 24
Finished Jun 05 05:59:36 PM PDT 24
Peak memory 250588 kb
Host smart-8d0776ee-6c9a-43cd-9e50-31a81e14718d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354019821 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_post_trans.3354019821
Directory /workspace/23.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all.1590624010
Short name T111
Test name
Test status
Simulation time 3006865057 ps
CPU time 95.91 seconds
Started Jun 05 05:59:35 PM PDT 24
Finished Jun 05 06:01:11 PM PDT 24
Peak memory 283836 kb
Host smart-c9b02f15-1bc9-4455-8582-b88c589d8b4d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590624010 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.lc_ctrl_stress_all.1590624010
Directory /workspace/23.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.lc_ctrl_volatile_unlock_smoke.3868439660
Short name T557
Test name
Test status
Simulation time 15794154 ps
CPU time 0.8 seconds
Started Jun 05 05:59:28 PM PDT 24
Finished Jun 05 05:59:29 PM PDT 24
Peak memory 208760 kb
Host smart-41309ae1-8f6d-423a-a825-1295d16a1bd5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868439660 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_c
trl_volatile_unlock_smoke.3868439660
Directory /workspace/23.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_alert_test.4093526840
Short name T554
Test name
Test status
Simulation time 94639601 ps
CPU time 0.99 seconds
Started Jun 05 05:59:35 PM PDT 24
Finished Jun 05 05:59:37 PM PDT 24
Peak memory 208704 kb
Host smart-cbbfe943-f7a6-4604-b357-19f5a6b63fe1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093526840 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_alert_test.4093526840
Directory /workspace/24.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.lc_ctrl_errors.2625753909
Short name T377
Test name
Test status
Simulation time 1616940000 ps
CPU time 18.42 seconds
Started Jun 05 05:59:38 PM PDT 24
Finished Jun 05 05:59:57 PM PDT 24
Peak memory 218168 kb
Host smart-bc5d9013-5e6c-40d0-ab84-02ea20e18677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625753909 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_errors.2625753909
Directory /workspace/24.lc_ctrl_errors/latest

Test location /workspace/coverage/default/24.lc_ctrl_jtag_access.1511838430
Short name T316
Test name
Test status
Simulation time 244159975 ps
CPU time 1.28 seconds
Started Jun 05 05:59:33 PM PDT 24
Finished Jun 05 05:59:35 PM PDT 24
Peak memory 216868 kb
Host smart-05c6cb03-825b-45a3-bc8b-903b9eea3fa4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511838430 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_jtag_access.1511838430
Directory /workspace/24.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/24.lc_ctrl_prog_failure.495712887
Short name T656
Test name
Test status
Simulation time 42821358 ps
CPU time 2.25 seconds
Started Jun 05 05:59:38 PM PDT 24
Finished Jun 05 05:59:41 PM PDT 24
Peak memory 218032 kb
Host smart-81fcc889-1eab-4f95-a326-08321603b79f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495712887 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_prog_failure.495712887
Directory /workspace/24.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_mubi.2177501114
Short name T374
Test name
Test status
Simulation time 1049229996 ps
CPU time 10.64 seconds
Started Jun 05 05:59:30 PM PDT 24
Finished Jun 05 05:59:41 PM PDT 24
Peak memory 218832 kb
Host smart-05275bad-c654-4693-ab78-1fe6cbaaa318
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177501114 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_mubi.2177501114
Directory /workspace/24.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_digest.1036969943
Short name T438
Test name
Test status
Simulation time 350929197 ps
CPU time 7.48 seconds
Started Jun 05 05:59:32 PM PDT 24
Finished Jun 05 05:59:40 PM PDT 24
Peak memory 218056 kb
Host smart-a97079ea-4f33-435e-88ee-d1e05f6d42d5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036969943 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_d
igest.1036969943
Directory /workspace/24.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_mux.3033015671
Short name T326
Test name
Test status
Simulation time 400000221 ps
CPU time 7.47 seconds
Started Jun 05 05:59:39 PM PDT 24
Finished Jun 05 05:59:48 PM PDT 24
Peak memory 217980 kb
Host smart-7de0a05a-5c45-460a-aaba-86d3ad2f0020
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033015671 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_mux.
3033015671
Directory /workspace/24.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/24.lc_ctrl_security_escalation.1506935472
Short name T619
Test name
Test status
Simulation time 1572638310 ps
CPU time 13.06 seconds
Started Jun 05 05:59:35 PM PDT 24
Finished Jun 05 05:59:49 PM PDT 24
Peak memory 224908 kb
Host smart-c8b0de1b-233f-451e-948b-c4935311d567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506935472 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_security_escalation.1506935472
Directory /workspace/24.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/24.lc_ctrl_smoke.3133141667
Short name T215
Test name
Test status
Simulation time 33118608 ps
CPU time 2.09 seconds
Started Jun 05 05:59:33 PM PDT 24
Finished Jun 05 05:59:36 PM PDT 24
Peak memory 217748 kb
Host smart-954c775b-d136-4fee-8a2a-1bdf0386475a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133141667 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_smoke.3133141667
Directory /workspace/24.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_failure.1338086545
Short name T359
Test name
Test status
Simulation time 250671823 ps
CPU time 35.35 seconds
Started Jun 05 05:59:37 PM PDT 24
Finished Jun 05 06:00:13 PM PDT 24
Peak memory 251020 kb
Host smart-800b6b57-b2fe-46ac-aedc-68e91b4df793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338086545 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_failure.1338086545
Directory /workspace/24.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_post_trans.247163961
Short name T555
Test name
Test status
Simulation time 502647107 ps
CPU time 7.1 seconds
Started Jun 05 05:59:37 PM PDT 24
Finished Jun 05 05:59:45 PM PDT 24
Peak memory 251028 kb
Host smart-6086f065-50aa-4546-85a0-9db948a87ae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247163961 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_post_trans.247163961
Directory /workspace/24.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all.2486226574
Short name T764
Test name
Test status
Simulation time 2119368638 ps
CPU time 28.38 seconds
Started Jun 05 05:59:27 PM PDT 24
Finished Jun 05 05:59:56 PM PDT 24
Peak memory 226116 kb
Host smart-5320ed0e-6bb8-4b76-b2f7-4a803e0253c5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486226574 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.lc_ctrl_stress_all.2486226574
Directory /workspace/24.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.lc_ctrl_volatile_unlock_smoke.2597552125
Short name T701
Test name
Test status
Simulation time 40751440 ps
CPU time 0.99 seconds
Started Jun 05 05:59:41 PM PDT 24
Finished Jun 05 05:59:43 PM PDT 24
Peak memory 211656 kb
Host smart-fef6c155-aa69-4a5a-8243-1ba4785f916a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597552125 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_c
trl_volatile_unlock_smoke.2597552125
Directory /workspace/24.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_alert_test.908558509
Short name T605
Test name
Test status
Simulation time 37102432 ps
CPU time 0.93 seconds
Started Jun 05 05:59:37 PM PDT 24
Finished Jun 05 05:59:39 PM PDT 24
Peak memory 209536 kb
Host smart-726dd5dd-54d3-454e-80d0-15fc0941f2ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908558509 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_alert_test.908558509
Directory /workspace/25.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.lc_ctrl_jtag_access.3200982227
Short name T541
Test name
Test status
Simulation time 564288185 ps
CPU time 6.27 seconds
Started Jun 05 05:59:39 PM PDT 24
Finished Jun 05 05:59:46 PM PDT 24
Peak memory 209600 kb
Host smart-35c80764-05ae-4c8c-b0b2-1a9b91639159
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200982227 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_jtag_access.3200982227
Directory /workspace/25.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/25.lc_ctrl_prog_failure.827978991
Short name T266
Test name
Test status
Simulation time 92774312 ps
CPU time 1.85 seconds
Started Jun 05 05:59:28 PM PDT 24
Finished Jun 05 05:59:31 PM PDT 24
Peak memory 218212 kb
Host smart-5be87a37-f9c3-48ef-b0d7-71dd010c9f27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827978991 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_prog_failure.827978991
Directory /workspace/25.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_mubi.1601911840
Short name T38
Test name
Test status
Simulation time 486841850 ps
CPU time 8.81 seconds
Started Jun 05 05:59:29 PM PDT 24
Finished Jun 05 05:59:39 PM PDT 24
Peak memory 219000 kb
Host smart-3385a3ae-f50f-4f31-aa49-4f9826741f43
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601911840 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_mubi.1601911840
Directory /workspace/25.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_digest.1235522392
Short name T354
Test name
Test status
Simulation time 696120312 ps
CPU time 15.19 seconds
Started Jun 05 05:59:29 PM PDT 24
Finished Jun 05 05:59:45 PM PDT 24
Peak memory 226004 kb
Host smart-72178dd3-f064-4045-920e-3480a0a19f27
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235522392 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_d
igest.1235522392
Directory /workspace/25.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_mux.672562146
Short name T800
Test name
Test status
Simulation time 318789527 ps
CPU time 8.6 seconds
Started Jun 05 05:59:35 PM PDT 24
Finished Jun 05 05:59:44 PM PDT 24
Peak memory 218184 kb
Host smart-7677622f-a8c7-4d2f-921c-e41cbbb553fc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672562146 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_mux.672562146
Directory /workspace/25.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/25.lc_ctrl_security_escalation.2424735636
Short name T765
Test name
Test status
Simulation time 355094194 ps
CPU time 13.88 seconds
Started Jun 05 05:59:32 PM PDT 24
Finished Jun 05 05:59:47 PM PDT 24
Peak memory 218116 kb
Host smart-c7a55fdd-9db0-4827-bce5-c46ca6a61fdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424735636 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_security_escalation.2424735636
Directory /workspace/25.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/25.lc_ctrl_smoke.2170758803
Short name T247
Test name
Test status
Simulation time 151984319 ps
CPU time 2.92 seconds
Started Jun 05 05:59:36 PM PDT 24
Finished Jun 05 05:59:40 PM PDT 24
Peak memory 214928 kb
Host smart-ef36320e-7ee7-42be-a28d-da55b748b007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2170758803 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_smoke.2170758803
Directory /workspace/25.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_failure.3260816270
Short name T793
Test name
Test status
Simulation time 352640122 ps
CPU time 31.88 seconds
Started Jun 05 05:59:30 PM PDT 24
Finished Jun 05 06:00:03 PM PDT 24
Peak memory 250992 kb
Host smart-87bc6bbe-4ce3-4873-a7af-89cbfcd32a0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260816270 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_failure.3260816270
Directory /workspace/25.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_post_trans.155365032
Short name T699
Test name
Test status
Simulation time 93470344 ps
CPU time 6.61 seconds
Started Jun 05 05:59:41 PM PDT 24
Finished Jun 05 05:59:48 PM PDT 24
Peak memory 251032 kb
Host smart-ac2d38d8-27b4-48e1-8ed3-893a94c99b91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=155365032 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_post_trans.155365032
Directory /workspace/25.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/25.lc_ctrl_stress_all.3288805582
Short name T587
Test name
Test status
Simulation time 8427159012 ps
CPU time 74.63 seconds
Started Jun 05 05:59:34 PM PDT 24
Finished Jun 05 06:00:50 PM PDT 24
Peak memory 251192 kb
Host smart-549ac1fb-115f-4225-9191-c8682b1031a8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288805582 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.lc_ctrl_stress_all.3288805582
Directory /workspace/25.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.lc_ctrl_volatile_unlock_smoke.267730222
Short name T503
Test name
Test status
Simulation time 49245262 ps
CPU time 0.94 seconds
Started Jun 05 05:59:31 PM PDT 24
Finished Jun 05 05:59:33 PM PDT 24
Peak memory 211588 kb
Host smart-c1a82c42-802c-46ba-85e1-2d0c22744769
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267730222 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ct
rl_volatile_unlock_smoke.267730222
Directory /workspace/25.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_alert_test.25439108
Short name T87
Test name
Test status
Simulation time 14121885 ps
CPU time 0.82 seconds
Started Jun 05 05:59:32 PM PDT 24
Finished Jun 05 05:59:34 PM PDT 24
Peak memory 209416 kb
Host smart-9ed2849d-0f33-4687-9536-e4f600b34db7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25439108 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_alert_test.25439108
Directory /workspace/26.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.lc_ctrl_errors.674516763
Short name T411
Test name
Test status
Simulation time 728812590 ps
CPU time 11.1 seconds
Started Jun 05 05:59:32 PM PDT 24
Finished Jun 05 05:59:44 PM PDT 24
Peak memory 218012 kb
Host smart-75a0c7b8-f2dd-4452-b424-fd028a177033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674516763 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_errors.674516763
Directory /workspace/26.lc_ctrl_errors/latest

Test location /workspace/coverage/default/26.lc_ctrl_jtag_access.1379291047
Short name T824
Test name
Test status
Simulation time 1885433798 ps
CPU time 4.24 seconds
Started Jun 05 05:59:34 PM PDT 24
Finished Jun 05 05:59:38 PM PDT 24
Peak memory 209564 kb
Host smart-fbcdf931-54b1-40e5-bef0-fafcee7cf909
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379291047 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_jtag_access.1379291047
Directory /workspace/26.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/26.lc_ctrl_prog_failure.3085841890
Short name T399
Test name
Test status
Simulation time 201165878 ps
CPU time 3.21 seconds
Started Jun 05 05:59:41 PM PDT 24
Finished Jun 05 05:59:46 PM PDT 24
Peak memory 218192 kb
Host smart-5c495a4f-21a8-45d0-a3ca-f9714babe05c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085841890 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_prog_failure.3085841890
Directory /workspace/26.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_mubi.861909217
Short name T439
Test name
Test status
Simulation time 1856394330 ps
CPU time 13.75 seconds
Started Jun 05 05:59:36 PM PDT 24
Finished Jun 05 05:59:51 PM PDT 24
Peak memory 226136 kb
Host smart-98c498fe-433e-4410-937c-b44bbf578a49
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861909217 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_mubi.861909217
Directory /workspace/26.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_digest.1776750929
Short name T651
Test name
Test status
Simulation time 4748325043 ps
CPU time 10.09 seconds
Started Jun 05 05:59:36 PM PDT 24
Finished Jun 05 05:59:47 PM PDT 24
Peak memory 226124 kb
Host smart-1af405cc-d0a5-4ff6-9e03-989d803d45c8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776750929 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_d
igest.1776750929
Directory /workspace/26.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_mux.1255436178
Short name T777
Test name
Test status
Simulation time 265378889 ps
CPU time 8.54 seconds
Started Jun 05 05:59:42 PM PDT 24
Finished Jun 05 05:59:51 PM PDT 24
Peak memory 218012 kb
Host smart-09b6334c-23f7-44d9-831c-2c7f36fc7d7e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255436178 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_mux.
1255436178
Directory /workspace/26.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/26.lc_ctrl_security_escalation.4270166874
Short name T719
Test name
Test status
Simulation time 581974074 ps
CPU time 8.2 seconds
Started Jun 05 05:59:27 PM PDT 24
Finished Jun 05 05:59:36 PM PDT 24
Peak memory 218120 kb
Host smart-11667447-3367-41da-8d4f-10fbbc97b9ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270166874 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_security_escalation.4270166874
Directory /workspace/26.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/26.lc_ctrl_smoke.3136065977
Short name T70
Test name
Test status
Simulation time 84873332 ps
CPU time 1.46 seconds
Started Jun 05 05:59:29 PM PDT 24
Finished Jun 05 05:59:31 PM PDT 24
Peak memory 217740 kb
Host smart-9f44b9ba-2708-4f66-ab59-0e956c487a3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136065977 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_smoke.3136065977
Directory /workspace/26.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_failure.2056290578
Short name T490
Test name
Test status
Simulation time 1229272931 ps
CPU time 32.32 seconds
Started Jun 05 05:59:35 PM PDT 24
Finished Jun 05 06:00:08 PM PDT 24
Peak memory 251044 kb
Host smart-1d4d3ba0-834c-4846-b035-df67ca4883ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056290578 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_failure.2056290578
Directory /workspace/26.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_post_trans.4098672764
Short name T253
Test name
Test status
Simulation time 382312248 ps
CPU time 6.53 seconds
Started Jun 05 05:59:31 PM PDT 24
Finished Jun 05 05:59:38 PM PDT 24
Peak memory 242824 kb
Host smart-a8c63f23-09a7-4362-a8fb-1258574328d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098672764 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_post_trans.4098672764
Directory /workspace/26.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all.1872220761
Short name T740
Test name
Test status
Simulation time 9175468448 ps
CPU time 332.81 seconds
Started Jun 05 05:59:35 PM PDT 24
Finished Jun 05 06:05:09 PM PDT 24
Peak memory 275664 kb
Host smart-3d7dc16d-1178-49f4-94d9-cf88c75076b6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872220761 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.lc_ctrl_stress_all.1872220761
Directory /workspace/26.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.lc_ctrl_volatile_unlock_smoke.1301386855
Short name T549
Test name
Test status
Simulation time 80519480 ps
CPU time 0.88 seconds
Started Jun 05 05:59:33 PM PDT 24
Finished Jun 05 05:59:34 PM PDT 24
Peak memory 208500 kb
Host smart-776584e0-6ca7-4abd-ab86-0beb14cf4cfd
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301386855 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_c
trl_volatile_unlock_smoke.1301386855
Directory /workspace/26.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_alert_test.432986036
Short name T314
Test name
Test status
Simulation time 92568627 ps
CPU time 0.85 seconds
Started Jun 05 05:59:44 PM PDT 24
Finished Jun 05 05:59:46 PM PDT 24
Peak memory 208620 kb
Host smart-8f8c256d-1fd4-424c-a310-6dd30bde4513
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432986036 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_alert_test.432986036
Directory /workspace/27.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.lc_ctrl_errors.3195732015
Short name T502
Test name
Test status
Simulation time 612975750 ps
CPU time 11.39 seconds
Started Jun 05 05:59:35 PM PDT 24
Finished Jun 05 05:59:47 PM PDT 24
Peak memory 218200 kb
Host smart-3fc1c78c-11fe-448a-9252-fcd12ac9b151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195732015 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_errors.3195732015
Directory /workspace/27.lc_ctrl_errors/latest

Test location /workspace/coverage/default/27.lc_ctrl_jtag_access.2262382220
Short name T24
Test name
Test status
Simulation time 942955740 ps
CPU time 9.35 seconds
Started Jun 05 05:59:36 PM PDT 24
Finished Jun 05 05:59:46 PM PDT 24
Peak memory 209556 kb
Host smart-74ca5496-a55e-45a1-a7c1-24609c5f2a9d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262382220 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_jtag_access.2262382220
Directory /workspace/27.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/27.lc_ctrl_prog_failure.3457015332
Short name T54
Test name
Test status
Simulation time 286893401 ps
CPU time 3.56 seconds
Started Jun 05 05:59:39 PM PDT 24
Finished Jun 05 05:59:44 PM PDT 24
Peak memory 218176 kb
Host smart-a5e675e1-c65a-47fd-b6e3-761746231fa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457015332 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_prog_failure.3457015332
Directory /workspace/27.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_mubi.2094595279
Short name T531
Test name
Test status
Simulation time 243230655 ps
CPU time 10.36 seconds
Started Jun 05 05:59:37 PM PDT 24
Finished Jun 05 05:59:48 PM PDT 24
Peak memory 218044 kb
Host smart-58a415f8-d240-4dfb-bfb1-3312fd2e0b8e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094595279 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_mubi.2094595279
Directory /workspace/27.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_digest.172327109
Short name T677
Test name
Test status
Simulation time 287440521 ps
CPU time 13.71 seconds
Started Jun 05 05:59:33 PM PDT 24
Finished Jun 05 05:59:47 PM PDT 24
Peak memory 225988 kb
Host smart-38cc6d4f-104d-43b2-9a42-9cb787128b59
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172327109 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_di
gest.172327109
Directory /workspace/27.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_mux.3801082311
Short name T413
Test name
Test status
Simulation time 281085372 ps
CPU time 11.18 seconds
Started Jun 05 05:59:33 PM PDT 24
Finished Jun 05 05:59:44 PM PDT 24
Peak memory 218072 kb
Host smart-8daf269a-f43b-4313-b8c7-57242ceb2399
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801082311 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_mux.
3801082311
Directory /workspace/27.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/27.lc_ctrl_security_escalation.104670937
Short name T711
Test name
Test status
Simulation time 444201265 ps
CPU time 15.99 seconds
Started Jun 05 05:59:31 PM PDT 24
Finished Jun 05 05:59:48 PM PDT 24
Peak memory 218116 kb
Host smart-ce4c1f87-5a5e-4eca-9f0b-4334a0763d1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104670937 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_security_escalation.104670937
Directory /workspace/27.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/27.lc_ctrl_smoke.3845071999
Short name T473
Test name
Test status
Simulation time 70984947 ps
CPU time 1.25 seconds
Started Jun 05 05:59:39 PM PDT 24
Finished Jun 05 05:59:40 PM PDT 24
Peak memory 217724 kb
Host smart-35548d1b-e034-4551-85f6-d960cdfaa89d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845071999 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_smoke.3845071999
Directory /workspace/27.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_failure.2215484788
Short name T112
Test name
Test status
Simulation time 1108145719 ps
CPU time 29.38 seconds
Started Jun 05 05:59:38 PM PDT 24
Finished Jun 05 06:00:08 PM PDT 24
Peak memory 251028 kb
Host smart-5a46d1e4-d958-4061-b751-df38b47bf3fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215484788 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_failure.2215484788
Directory /workspace/27.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_post_trans.3245016157
Short name T234
Test name
Test status
Simulation time 76088061 ps
CPU time 6.06 seconds
Started Jun 05 05:59:38 PM PDT 24
Finished Jun 05 05:59:45 PM PDT 24
Peak memory 246816 kb
Host smart-59e3e898-c6af-426d-bfdf-7ab1ca1650f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245016157 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_post_trans.3245016157
Directory /workspace/27.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all.1883054211
Short name T687
Test name
Test status
Simulation time 9995866865 ps
CPU time 356.01 seconds
Started Jun 05 05:59:39 PM PDT 24
Finished Jun 05 06:05:35 PM PDT 24
Peak memory 251020 kb
Host smart-e1e42faf-8968-471a-bcc1-a145656c93b5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883054211 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.lc_ctrl_stress_all.1883054211
Directory /workspace/27.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.lc_ctrl_volatile_unlock_smoke.3607637633
Short name T847
Test name
Test status
Simulation time 26813612 ps
CPU time 0.94 seconds
Started Jun 05 05:59:35 PM PDT 24
Finished Jun 05 05:59:37 PM PDT 24
Peak memory 211556 kb
Host smart-769b183b-6824-455e-9a91-41932cad6416
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607637633 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_c
trl_volatile_unlock_smoke.3607637633
Directory /workspace/27.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_alert_test.2893982539
Short name T724
Test name
Test status
Simulation time 85262260 ps
CPU time 1.3 seconds
Started Jun 05 05:59:37 PM PDT 24
Finished Jun 05 05:59:39 PM PDT 24
Peak memory 208912 kb
Host smart-65a71b75-da9d-4ab0-add1-1f048e123955
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893982539 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_alert_test.2893982539
Directory /workspace/28.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.lc_ctrl_errors.4225438733
Short name T446
Test name
Test status
Simulation time 265203858 ps
CPU time 11.77 seconds
Started Jun 05 05:59:32 PM PDT 24
Finished Jun 05 05:59:45 PM PDT 24
Peak memory 218028 kb
Host smart-ce644ddf-6fa4-41a8-8ffc-ea76ca74016f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225438733 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_errors.4225438733
Directory /workspace/28.lc_ctrl_errors/latest

Test location /workspace/coverage/default/28.lc_ctrl_jtag_access.4147342014
Short name T109
Test name
Test status
Simulation time 93967269 ps
CPU time 1.61 seconds
Started Jun 05 05:59:34 PM PDT 24
Finished Jun 05 05:59:36 PM PDT 24
Peak memory 217104 kb
Host smart-947cb543-29ea-424c-85c8-2be332c9bb73
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147342014 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_jtag_access.4147342014
Directory /workspace/28.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/28.lc_ctrl_prog_failure.2363484198
Short name T357
Test name
Test status
Simulation time 71192810 ps
CPU time 3.09 seconds
Started Jun 05 05:59:41 PM PDT 24
Finished Jun 05 05:59:45 PM PDT 24
Peak memory 218028 kb
Host smart-ad1cc21b-19bc-4fa8-a4f7-9a5e6dcb5d22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2363484198 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_prog_failure.2363484198
Directory /workspace/28.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_mubi.471073798
Short name T544
Test name
Test status
Simulation time 1175025766 ps
CPU time 13.59 seconds
Started Jun 05 05:59:49 PM PDT 24
Finished Jun 05 06:00:03 PM PDT 24
Peak memory 218220 kb
Host smart-bcb9cf99-9222-4130-a8b9-8e9a2cae1b9a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471073798 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_mubi.471073798
Directory /workspace/28.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_digest.832670143
Short name T710
Test name
Test status
Simulation time 5213029713 ps
CPU time 19.07 seconds
Started Jun 05 05:59:39 PM PDT 24
Finished Jun 05 05:59:59 PM PDT 24
Peak memory 226148 kb
Host smart-01d0766b-4ee9-46ea-a167-8c33681175be
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832670143 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_di
gest.832670143
Directory /workspace/28.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_mux.2910733146
Short name T756
Test name
Test status
Simulation time 1522232841 ps
CPU time 10.15 seconds
Started Jun 05 05:59:37 PM PDT 24
Finished Jun 05 05:59:48 PM PDT 24
Peak memory 218044 kb
Host smart-36fc796b-49bf-48d8-8ac0-da69915343bb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910733146 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_mux.
2910733146
Directory /workspace/28.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/28.lc_ctrl_security_escalation.3602586375
Short name T832
Test name
Test status
Simulation time 1180071159 ps
CPU time 7.29 seconds
Started Jun 05 05:59:35 PM PDT 24
Finished Jun 05 05:59:42 PM PDT 24
Peak memory 218096 kb
Host smart-abb57009-55db-44c0-991c-cea97722f0bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602586375 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_security_escalation.3602586375
Directory /workspace/28.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/28.lc_ctrl_smoke.3321268716
Short name T224
Test name
Test status
Simulation time 532175688 ps
CPU time 1.8 seconds
Started Jun 05 05:59:38 PM PDT 24
Finished Jun 05 05:59:40 PM PDT 24
Peak memory 217740 kb
Host smart-48e56fbf-b272-4adb-bc6a-73cb59dc284b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321268716 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_smoke.3321268716
Directory /workspace/28.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_failure.2875510692
Short name T449
Test name
Test status
Simulation time 257445907 ps
CPU time 30.36 seconds
Started Jun 05 05:59:38 PM PDT 24
Finished Jun 05 06:00:09 PM PDT 24
Peak memory 251096 kb
Host smart-d4d153a9-8cd6-41f5-82ad-48d347ccd51c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875510692 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_failure.2875510692
Directory /workspace/28.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_post_trans.2385107442
Short name T310
Test name
Test status
Simulation time 82292165 ps
CPU time 9.54 seconds
Started Jun 05 05:59:38 PM PDT 24
Finished Jun 05 05:59:48 PM PDT 24
Peak memory 251024 kb
Host smart-7c6bb708-4ccf-42e6-85e4-379ae1fd8e14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385107442 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_post_trans.2385107442
Directory /workspace/28.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/28.lc_ctrl_stress_all.2815514222
Short name T379
Test name
Test status
Simulation time 8050911592 ps
CPU time 273.11 seconds
Started Jun 05 05:59:36 PM PDT 24
Finished Jun 05 06:04:10 PM PDT 24
Peak memory 251168 kb
Host smart-c0c54955-050a-4f44-93cd-fe382be38708
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815514222 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.lc_ctrl_stress_all.2815514222
Directory /workspace/28.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.lc_ctrl_volatile_unlock_smoke.2078787490
Short name T467
Test name
Test status
Simulation time 16611384 ps
CPU time 1.03 seconds
Started Jun 05 05:59:34 PM PDT 24
Finished Jun 05 05:59:36 PM PDT 24
Peak memory 208656 kb
Host smart-9d725829-3034-4821-9fab-b6c83df7154f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078787490 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_c
trl_volatile_unlock_smoke.2078787490
Directory /workspace/28.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_alert_test.1465919380
Short name T692
Test name
Test status
Simulation time 31993207 ps
CPU time 0.9 seconds
Started Jun 05 05:59:43 PM PDT 24
Finished Jun 05 05:59:45 PM PDT 24
Peak memory 208496 kb
Host smart-79211d91-c25c-44e8-b72b-2cd30e8328d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465919380 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_alert_test.1465919380
Directory /workspace/29.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.lc_ctrl_errors.3811236803
Short name T845
Test name
Test status
Simulation time 301326469 ps
CPU time 9.94 seconds
Started Jun 05 05:59:40 PM PDT 24
Finished Jun 05 05:59:51 PM PDT 24
Peak memory 218056 kb
Host smart-42375895-ace8-4343-a639-7464baac52fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811236803 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_errors.3811236803
Directory /workspace/29.lc_ctrl_errors/latest

Test location /workspace/coverage/default/29.lc_ctrl_jtag_access.982972904
Short name T280
Test name
Test status
Simulation time 73199212 ps
CPU time 2.45 seconds
Started Jun 05 05:59:34 PM PDT 24
Finished Jun 05 05:59:38 PM PDT 24
Peak memory 209560 kb
Host smart-c6b0552a-715a-4906-81f3-f61c83b62b83
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982972904 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_jtag_access.982972904
Directory /workspace/29.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/29.lc_ctrl_prog_failure.1117156146
Short name T580
Test name
Test status
Simulation time 287481120 ps
CPU time 2.95 seconds
Started Jun 05 05:59:40 PM PDT 24
Finished Jun 05 05:59:44 PM PDT 24
Peak memory 218076 kb
Host smart-175d9f7b-99da-400a-bbd8-ddf73d31d20a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117156146 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_prog_failure.1117156146
Directory /workspace/29.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_mubi.2013625742
Short name T372
Test name
Test status
Simulation time 1580305112 ps
CPU time 10.1 seconds
Started Jun 05 05:59:34 PM PDT 24
Finished Jun 05 05:59:45 PM PDT 24
Peak memory 218444 kb
Host smart-1db2cdac-d25d-459b-86fe-a1c6f4844c7d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013625742 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_mubi.2013625742
Directory /workspace/29.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_digest.848717041
Short name T441
Test name
Test status
Simulation time 256671467 ps
CPU time 10.35 seconds
Started Jun 05 05:59:35 PM PDT 24
Finished Jun 05 05:59:46 PM PDT 24
Peak memory 226068 kb
Host smart-e0f53ace-a28e-4ff6-a6c7-e0d2b80a299c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848717041 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_di
gest.848717041
Directory /workspace/29.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_mux.2101574090
Short name T840
Test name
Test status
Simulation time 268201029 ps
CPU time 9.66 seconds
Started Jun 05 05:59:39 PM PDT 24
Finished Jun 05 05:59:50 PM PDT 24
Peak memory 217968 kb
Host smart-d414959d-b57b-46a0-a3f3-846c71525907
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101574090 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_mux.
2101574090
Directory /workspace/29.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/29.lc_ctrl_security_escalation.3721398489
Short name T792
Test name
Test status
Simulation time 1938024475 ps
CPU time 10.67 seconds
Started Jun 05 05:59:37 PM PDT 24
Finished Jun 05 05:59:48 PM PDT 24
Peak memory 218216 kb
Host smart-8642f516-2b02-4c1e-af6d-671d3b7e6906
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721398489 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_security_escalation.3721398489
Directory /workspace/29.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/29.lc_ctrl_smoke.3945370654
Short name T641
Test name
Test status
Simulation time 94954598 ps
CPU time 3.13 seconds
Started Jun 05 05:59:38 PM PDT 24
Finished Jun 05 05:59:42 PM PDT 24
Peak memory 214436 kb
Host smart-4cd5bd62-8aa1-433c-8aaa-64779e6b8314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945370654 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_smoke.3945370654
Directory /workspace/29.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_failure.2365967224
Short name T80
Test name
Test status
Simulation time 1037258200 ps
CPU time 25.12 seconds
Started Jun 05 05:59:44 PM PDT 24
Finished Jun 05 06:00:10 PM PDT 24
Peak memory 250972 kb
Host smart-7e688913-2fd3-49af-b223-c1852a7ab2c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365967224 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_failure.2365967224
Directory /workspace/29.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_post_trans.1797739244
Short name T358
Test name
Test status
Simulation time 349452463 ps
CPU time 4.34 seconds
Started Jun 05 05:59:43 PM PDT 24
Finished Jun 05 05:59:49 PM PDT 24
Peak memory 222968 kb
Host smart-32d14c06-886c-4061-a26b-9dd6ca95fd09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797739244 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_post_trans.1797739244
Directory /workspace/29.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/29.lc_ctrl_stress_all.2390599134
Short name T547
Test name
Test status
Simulation time 4361474914 ps
CPU time 73.67 seconds
Started Jun 05 05:59:38 PM PDT 24
Finished Jun 05 06:00:52 PM PDT 24
Peak memory 228368 kb
Host smart-06d4127f-6c4c-401c-b27d-44f0839c51db
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390599134 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.lc_ctrl_stress_all.2390599134
Directory /workspace/29.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.lc_ctrl_volatile_unlock_smoke.166036215
Short name T165
Test name
Test status
Simulation time 43243845 ps
CPU time 0.79 seconds
Started Jun 05 05:59:40 PM PDT 24
Finished Jun 05 05:59:41 PM PDT 24
Peak memory 208700 kb
Host smart-ff1da714-49a1-464a-a9f2-e9196cad92a5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166036215 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ct
rl_volatile_unlock_smoke.166036215
Directory /workspace/29.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_alert_test.2072624163
Short name T86
Test name
Test status
Simulation time 85517738 ps
CPU time 1.28 seconds
Started Jun 05 05:59:01 PM PDT 24
Finished Jun 05 05:59:03 PM PDT 24
Peak memory 208724 kb
Host smart-9a3e5b32-94b6-4be1-a086-f853c24f842e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072624163 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_alert_test.2072624163
Directory /workspace/3.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.lc_ctrl_errors.937280786
Short name T829
Test name
Test status
Simulation time 1055761431 ps
CPU time 12.38 seconds
Started Jun 05 05:58:36 PM PDT 24
Finished Jun 05 05:58:50 PM PDT 24
Peak memory 218052 kb
Host smart-36a453ee-25ad-435a-9138-831d66309f85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937280786 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_errors.937280786
Directory /workspace/3.lc_ctrl_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_access.383560197
Short name T676
Test name
Test status
Simulation time 240231129 ps
CPU time 3.8 seconds
Started Jun 05 05:58:39 PM PDT 24
Finished Jun 05 05:58:44 PM PDT 24
Peak memory 217184 kb
Host smart-9b9cbfab-0b6a-46b3-8ee9-39391792d27b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383560197 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_access.383560197
Directory /workspace/3.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_errors.2985520289
Short name T238
Test name
Test status
Simulation time 36497224826 ps
CPU time 27.89 seconds
Started Jun 05 05:58:42 PM PDT 24
Finished Jun 05 05:59:12 PM PDT 24
Peak memory 218712 kb
Host smart-0d4cde62-5a17-4ceb-be5a-cfcf7cd3d844
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985520289 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_er
rors.2985520289
Directory /workspace/3.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_priority.3956143774
Short name T250
Test name
Test status
Simulation time 2869965988 ps
CPU time 19 seconds
Started Jun 05 05:58:47 PM PDT 24
Finished Jun 05 05:59:08 PM PDT 24
Peak memory 217748 kb
Host smart-74bbf0e4-0769-49dd-870f-0f8f8135e7d5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956143774 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_priority.3
956143774
Directory /workspace/3.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_prog_failure.1324138079
Short name T678
Test name
Test status
Simulation time 709847883 ps
CPU time 3.62 seconds
Started Jun 05 05:58:54 PM PDT 24
Finished Jun 05 05:58:59 PM PDT 24
Peak memory 218140 kb
Host smart-cf9f0f37-1ce5-41d7-91af-09cd842c44e5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324138079 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag
_prog_failure.1324138079
Directory /workspace/3.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_regwen_during_op.3579202491
Short name T292
Test name
Test status
Simulation time 701842279 ps
CPU time 10.99 seconds
Started Jun 05 05:58:39 PM PDT 24
Finished Jun 05 05:58:51 PM PDT 24
Peak memory 217704 kb
Host smart-d4659676-c6bd-4509-9bb7-4c63edbbe218
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579202491 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_regwen_during_op.3579202491
Directory /workspace/3.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_smoke.1183041118
Short name T669
Test name
Test status
Simulation time 1659270381 ps
CPU time 7.24 seconds
Started Jun 05 05:58:44 PM PDT 24
Finished Jun 05 05:58:53 PM PDT 24
Peak memory 217652 kb
Host smart-fec1d674-cd75-4ba4-af00-844b8786532b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183041118 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_smoke.
1183041118
Directory /workspace/3.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_failure.2265993648
Short name T601
Test name
Test status
Simulation time 4761260963 ps
CPU time 53.66 seconds
Started Jun 05 05:58:33 PM PDT 24
Finished Jun 05 05:59:27 PM PDT 24
Peak memory 279504 kb
Host smart-f9c08c28-1e0e-4118-9ef4-3cca8900bda2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265993648 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jta
g_state_failure.2265993648
Directory /workspace/3.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_post_trans.1111381250
Short name T334
Test name
Test status
Simulation time 400931699 ps
CPU time 7.08 seconds
Started Jun 05 05:58:47 PM PDT 24
Finished Jun 05 05:58:57 PM PDT 24
Peak memory 222952 kb
Host smart-d626b72d-a7e8-49ec-a691-b9df6e30f5b8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111381250 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_state_post_trans.1111381250
Directory /workspace/3.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_prog_failure.2940605940
Short name T640
Test name
Test status
Simulation time 1518848462 ps
CPU time 4.25 seconds
Started Jun 05 05:58:34 PM PDT 24
Finished Jun 05 05:58:39 PM PDT 24
Peak memory 218048 kb
Host smart-8ce8b405-75e4-461c-9f9e-1d6a34fb9190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940605940 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_prog_failure.2940605940
Directory /workspace/3.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_regwen_during_op.3131630027
Short name T739
Test name
Test status
Simulation time 343859201 ps
CPU time 13.15 seconds
Started Jun 05 05:58:47 PM PDT 24
Finished Jun 05 05:59:02 PM PDT 24
Peak memory 214008 kb
Host smart-fa54caa2-03d7-489d-b0be-d737e98893e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131630027 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_regwen_during_op.3131630027
Directory /workspace/3.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_cm.526340880
Short name T101
Test name
Test status
Simulation time 4362115310 ps
CPU time 40.91 seconds
Started Jun 05 05:58:42 PM PDT 24
Finished Jun 05 05:59:25 PM PDT 24
Peak memory 284544 kb
Host smart-15c250db-d052-401a-b60e-09851bb567c6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526340880 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_cm.526340880
Directory /workspace/3.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_mubi.2971115998
Short name T515
Test name
Test status
Simulation time 11865951193 ps
CPU time 14.74 seconds
Started Jun 05 05:58:36 PM PDT 24
Finished Jun 05 05:58:52 PM PDT 24
Peak memory 218920 kb
Host smart-66c028b5-fa99-4e3b-b5c4-f4a9fd9e492f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971115998 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_mubi.2971115998
Directory /workspace/3.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_digest.420584973
Short name T251
Test name
Test status
Simulation time 1460935316 ps
CPU time 15.88 seconds
Started Jun 05 05:58:35 PM PDT 24
Finished Jun 05 05:58:52 PM PDT 24
Peak memory 218008 kb
Host smart-3d360d75-7a80-4196-bae3-b68b16f18108
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420584973 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_dig
est.420584973
Directory /workspace/3.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_mux.2071496486
Short name T759
Test name
Test status
Simulation time 415740492 ps
CPU time 8.85 seconds
Started Jun 05 05:58:40 PM PDT 24
Finished Jun 05 05:58:50 PM PDT 24
Peak memory 218044 kb
Host smart-0f4774c5-da97-432f-80b9-b5334d9b3ea1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071496486 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_mux.2
071496486
Directory /workspace/3.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/3.lc_ctrl_security_escalation.3422295771
Short name T518
Test name
Test status
Simulation time 220757164 ps
CPU time 9.46 seconds
Started Jun 05 05:58:34 PM PDT 24
Finished Jun 05 05:58:44 PM PDT 24
Peak memory 218080 kb
Host smart-6935d316-2644-4d84-a0b3-13ef379b2c3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422295771 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_security_escalation.3422295771
Directory /workspace/3.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/3.lc_ctrl_smoke.2870733849
Short name T684
Test name
Test status
Simulation time 26435564 ps
CPU time 1.37 seconds
Started Jun 05 05:58:43 PM PDT 24
Finished Jun 05 05:58:47 PM PDT 24
Peak memory 213500 kb
Host smart-17850091-b3f6-414e-85ff-56358dc29093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870733849 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_smoke.2870733849
Directory /workspace/3.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_failure.2943111894
Short name T577
Test name
Test status
Simulation time 362014444 ps
CPU time 27.6 seconds
Started Jun 05 05:58:37 PM PDT 24
Finished Jun 05 05:59:06 PM PDT 24
Peak memory 251040 kb
Host smart-3f95feee-a160-4b73-90c1-ac7e5b0a7692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943111894 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_failure.2943111894
Directory /workspace/3.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_post_trans.2699792844
Short name T222
Test name
Test status
Simulation time 161922323 ps
CPU time 8.29 seconds
Started Jun 05 05:58:40 PM PDT 24
Finished Jun 05 05:58:50 PM PDT 24
Peak memory 251020 kb
Host smart-74e2f2eb-59cc-45ef-bafa-f7e94cb40cb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699792844 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_post_trans.2699792844
Directory /workspace/3.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_stress_all.61057558
Short name T425
Test name
Test status
Simulation time 3533163794 ps
CPU time 58.4 seconds
Started Jun 05 05:58:41 PM PDT 24
Finished Jun 05 05:59:41 PM PDT 24
Peak memory 251056 kb
Host smart-2d471e42-2871-403b-a0b9-b9bb60b931ed
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61057558 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_T
EST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
.lc_ctrl_stress_all.61057558
Directory /workspace/3.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.lc_ctrl_stress_all_with_rand_reset.4198059093
Short name T114
Test name
Test status
Simulation time 54767512820 ps
CPU time 431.72 seconds
Started Jun 05 05:58:38 PM PDT 24
Finished Jun 05 06:05:51 PM PDT 24
Peak memory 308552 kb
Host smart-4cad8eff-81a7-4d8c-bcc6-4899a5e8aec2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4198059093 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_stress_all_with_rand_reset.4198059093
Directory /workspace/3.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.lc_ctrl_volatile_unlock_smoke.1615049009
Short name T28
Test name
Test status
Simulation time 168500410 ps
CPU time 0.87 seconds
Started Jun 05 05:58:42 PM PDT 24
Finished Jun 05 05:58:44 PM PDT 24
Peak memory 211540 kb
Host smart-a0a59664-8c0f-4903-bed8-cbca337c6ab5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615049009 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ct
rl_volatile_unlock_smoke.1615049009
Directory /workspace/3.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_alert_test.3875317726
Short name T495
Test name
Test status
Simulation time 28899043 ps
CPU time 1.41 seconds
Started Jun 05 05:59:39 PM PDT 24
Finished Jun 05 05:59:41 PM PDT 24
Peak memory 208788 kb
Host smart-69eb6c73-b63d-4e9d-87bc-a70d413b2ad8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875317726 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_alert_test.3875317726
Directory /workspace/30.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.lc_ctrl_errors.1774328974
Short name T621
Test name
Test status
Simulation time 1547440693 ps
CPU time 12.44 seconds
Started Jun 05 05:59:42 PM PDT 24
Finished Jun 05 05:59:55 PM PDT 24
Peak memory 217984 kb
Host smart-4058078a-aca7-4741-8afd-97d2618434f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774328974 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_errors.1774328974
Directory /workspace/30.lc_ctrl_errors/latest

Test location /workspace/coverage/default/30.lc_ctrl_jtag_access.11465652
Short name T92
Test name
Test status
Simulation time 1352605897 ps
CPU time 7.03 seconds
Started Jun 05 05:59:44 PM PDT 24
Finished Jun 05 05:59:52 PM PDT 24
Peak memory 209516 kb
Host smart-ffd5feb0-9d40-4e84-bbbf-0a32947ef75e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11465652 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_jtag_access.11465652
Directory /workspace/30.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/30.lc_ctrl_prog_failure.328488762
Short name T671
Test name
Test status
Simulation time 149140797 ps
CPU time 2.34 seconds
Started Jun 05 05:59:41 PM PDT 24
Finished Jun 05 05:59:45 PM PDT 24
Peak memory 218016 kb
Host smart-9d97ec11-eea9-4b91-bb03-01ec335927ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=328488762 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_prog_failure.328488762
Directory /workspace/30.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_mubi.4214633985
Short name T662
Test name
Test status
Simulation time 755721933 ps
CPU time 16.67 seconds
Started Jun 05 05:59:43 PM PDT 24
Finished Jun 05 06:00:01 PM PDT 24
Peak memory 225708 kb
Host smart-a1be6124-7a1e-47d3-9c76-d578a80b17ba
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214633985 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_mubi.4214633985
Directory /workspace/30.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_digest.4200085684
Short name T384
Test name
Test status
Simulation time 668549517 ps
CPU time 13.16 seconds
Started Jun 05 05:59:43 PM PDT 24
Finished Jun 05 05:59:58 PM PDT 24
Peak memory 217624 kb
Host smart-c0c8d455-4426-40d5-831d-b54c17494ac1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200085684 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_d
igest.4200085684
Directory /workspace/30.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_mux.3161783931
Short name T594
Test name
Test status
Simulation time 419016531 ps
CPU time 6.54 seconds
Started Jun 05 05:59:39 PM PDT 24
Finished Jun 05 05:59:46 PM PDT 24
Peak memory 218036 kb
Host smart-619b63cf-9892-4322-9b6e-bafe98012679
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161783931 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_mux.
3161783931
Directory /workspace/30.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/30.lc_ctrl_security_escalation.3888588268
Short name T49
Test name
Test status
Simulation time 269500422 ps
CPU time 7.25 seconds
Started Jun 05 05:59:39 PM PDT 24
Finished Jun 05 05:59:48 PM PDT 24
Peak memory 218132 kb
Host smart-7762763f-3fbd-4cc7-832b-9a8f165a8287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888588268 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_security_escalation.3888588268
Directory /workspace/30.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/30.lc_ctrl_smoke.3938095653
Short name T578
Test name
Test status
Simulation time 83347480 ps
CPU time 5.27 seconds
Started Jun 05 05:59:39 PM PDT 24
Finished Jun 05 05:59:45 PM PDT 24
Peak memory 217684 kb
Host smart-06d41441-e913-4212-bb0c-88f6cccd25c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938095653 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_smoke.3938095653
Directory /workspace/30.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_failure.718909454
Short name T341
Test name
Test status
Simulation time 915336699 ps
CPU time 25.06 seconds
Started Jun 05 05:59:35 PM PDT 24
Finished Jun 05 06:00:01 PM PDT 24
Peak memory 250848 kb
Host smart-5aa16795-6c7e-401a-98b3-239dca85c09d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718909454 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_failure.718909454
Directory /workspace/30.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_post_trans.2460515849
Short name T210
Test name
Test status
Simulation time 129650188 ps
CPU time 2.86 seconds
Started Jun 05 05:59:45 PM PDT 24
Finished Jun 05 05:59:48 PM PDT 24
Peak memory 222172 kb
Host smart-4f7038cd-bf8c-4be0-80c4-d60dff54a87e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460515849 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_post_trans.2460515849
Directory /workspace/30.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all.796096952
Short name T482
Test name
Test status
Simulation time 12393611730 ps
CPU time 192.73 seconds
Started Jun 05 05:59:38 PM PDT 24
Finished Jun 05 06:02:52 PM PDT 24
Peak memory 496756 kb
Host smart-2d59f22b-4615-4e97-ac3b-63809028b8fe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796096952 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.lc_ctrl_stress_all.796096952
Directory /workspace/30.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.lc_ctrl_volatile_unlock_smoke.948225045
Short name T528
Test name
Test status
Simulation time 19632566 ps
CPU time 0.73 seconds
Started Jun 05 05:59:38 PM PDT 24
Finished Jun 05 05:59:40 PM PDT 24
Peak memory 208324 kb
Host smart-5bc44a81-3562-4641-8270-a8006a92703e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948225045 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ct
rl_volatile_unlock_smoke.948225045
Directory /workspace/30.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_alert_test.1844464593
Short name T415
Test name
Test status
Simulation time 46107355 ps
CPU time 1 seconds
Started Jun 05 05:59:42 PM PDT 24
Finished Jun 05 05:59:43 PM PDT 24
Peak memory 208700 kb
Host smart-f1530b16-6170-42ba-b42e-faf445573c60
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844464593 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_alert_test.1844464593
Directory /workspace/31.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.lc_ctrl_errors.3869432415
Short name T657
Test name
Test status
Simulation time 198058483 ps
CPU time 10.37 seconds
Started Jun 05 05:59:37 PM PDT 24
Finished Jun 05 05:59:48 PM PDT 24
Peak memory 218120 kb
Host smart-23fa98e5-a4ae-4980-bcdb-2decde1e8532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869432415 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_errors.3869432415
Directory /workspace/31.lc_ctrl_errors/latest

Test location /workspace/coverage/default/31.lc_ctrl_jtag_access.2500368820
Short name T648
Test name
Test status
Simulation time 3487222474 ps
CPU time 6.43 seconds
Started Jun 05 05:59:38 PM PDT 24
Finished Jun 05 05:59:45 PM PDT 24
Peak memory 209724 kb
Host smart-18d9fb3a-e9df-4309-bb84-eb37be7201e2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500368820 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_jtag_access.2500368820
Directory /workspace/31.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/31.lc_ctrl_prog_failure.3850284956
Short name T562
Test name
Test status
Simulation time 61088008 ps
CPU time 1.98 seconds
Started Jun 05 05:59:39 PM PDT 24
Finished Jun 05 05:59:42 PM PDT 24
Peak memory 218028 kb
Host smart-be64a647-9127-491c-a761-6657960c03ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850284956 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_prog_failure.3850284956
Directory /workspace/31.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_mubi.3167659968
Short name T345
Test name
Test status
Simulation time 457134944 ps
CPU time 12.12 seconds
Started Jun 05 05:59:44 PM PDT 24
Finished Jun 05 05:59:57 PM PDT 24
Peak memory 218920 kb
Host smart-577473db-8a9d-4f75-8bc7-2d21f6be434f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167659968 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_mubi.3167659968
Directory /workspace/31.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_digest.3539613213
Short name T481
Test name
Test status
Simulation time 379054326 ps
CPU time 8.17 seconds
Started Jun 05 05:59:42 PM PDT 24
Finished Jun 05 05:59:51 PM PDT 24
Peak memory 217968 kb
Host smart-86b91216-893b-4713-a460-3559ee4bd85e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539613213 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_d
igest.3539613213
Directory /workspace/31.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_mux.3263354150
Short name T236
Test name
Test status
Simulation time 339975240 ps
CPU time 7.72 seconds
Started Jun 05 05:59:43 PM PDT 24
Finished Jun 05 05:59:52 PM PDT 24
Peak memory 218052 kb
Host smart-063fe6a8-7413-4152-b996-422b8da10317
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263354150 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_mux.
3263354150
Directory /workspace/31.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/31.lc_ctrl_security_escalation.2487715270
Short name T46
Test name
Test status
Simulation time 1796017339 ps
CPU time 9.54 seconds
Started Jun 05 05:59:43 PM PDT 24
Finished Jun 05 05:59:53 PM PDT 24
Peak memory 218180 kb
Host smart-d00b6782-f7b3-4753-bb78-1ef3795d980b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487715270 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_security_escalation.2487715270
Directory /workspace/31.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/31.lc_ctrl_smoke.929619359
Short name T556
Test name
Test status
Simulation time 273495759 ps
CPU time 2.95 seconds
Started Jun 05 05:59:42 PM PDT 24
Finished Jun 05 05:59:46 PM PDT 24
Peak memory 214536 kb
Host smart-df98ac51-c7ec-4570-83de-7d9c3f671dcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929619359 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_smoke.929619359
Directory /workspace/31.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_failure.2084846284
Short name T293
Test name
Test status
Simulation time 1121889719 ps
CPU time 30.68 seconds
Started Jun 05 05:59:40 PM PDT 24
Finished Jun 05 06:00:12 PM PDT 24
Peak memory 251032 kb
Host smart-d722630b-5e78-405d-8ee9-ad49e72f6402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084846284 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_failure.2084846284
Directory /workspace/31.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_post_trans.2985341987
Short name T780
Test name
Test status
Simulation time 657400757 ps
CPU time 11.02 seconds
Started Jun 05 05:59:39 PM PDT 24
Finished Jun 05 05:59:51 PM PDT 24
Peak memory 251016 kb
Host smart-242c0fdf-2ea4-4104-a36d-acb86987e768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985341987 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_post_trans.2985341987
Directory /workspace/31.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/31.lc_ctrl_stress_all.1729690529
Short name T714
Test name
Test status
Simulation time 1226177252 ps
CPU time 52.53 seconds
Started Jun 05 05:59:52 PM PDT 24
Finished Jun 05 06:00:45 PM PDT 24
Peak memory 250852 kb
Host smart-7226d878-71e7-414e-862f-c2d5a25149bf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729690529 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.lc_ctrl_stress_all.1729690529
Directory /workspace/31.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.lc_ctrl_volatile_unlock_smoke.498287619
Short name T854
Test name
Test status
Simulation time 19288027 ps
CPU time 0.77 seconds
Started Jun 05 05:59:42 PM PDT 24
Finished Jun 05 05:59:44 PM PDT 24
Peak memory 208572 kb
Host smart-5e330200-745e-4764-9ab0-49fc2c56f294
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498287619 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ct
rl_volatile_unlock_smoke.498287619
Directory /workspace/31.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_alert_test.4278431114
Short name T491
Test name
Test status
Simulation time 22717370 ps
CPU time 1.28 seconds
Started Jun 05 05:59:41 PM PDT 24
Finished Jun 05 05:59:43 PM PDT 24
Peak memory 208796 kb
Host smart-beb98f76-fc96-4ce1-8db7-c1c3920a4f87
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278431114 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_alert_test.4278431114
Directory /workspace/32.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.lc_ctrl_errors.177038529
Short name T206
Test name
Test status
Simulation time 905922070 ps
CPU time 7.91 seconds
Started Jun 05 05:59:44 PM PDT 24
Finished Jun 05 05:59:53 PM PDT 24
Peak memory 218048 kb
Host smart-7dedc276-6de1-428f-bf64-1d8b388743e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177038529 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_errors.177038529
Directory /workspace/32.lc_ctrl_errors/latest

Test location /workspace/coverage/default/32.lc_ctrl_jtag_access.2769531070
Short name T350
Test name
Test status
Simulation time 1206312152 ps
CPU time 7.92 seconds
Started Jun 05 05:59:49 PM PDT 24
Finished Jun 05 05:59:58 PM PDT 24
Peak memory 209552 kb
Host smart-a555fa52-879a-4b84-a407-334008795be1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769531070 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_jtag_access.2769531070
Directory /workspace/32.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/32.lc_ctrl_prog_failure.1611633297
Short name T260
Test name
Test status
Simulation time 37736119 ps
CPU time 2.57 seconds
Started Jun 05 05:59:41 PM PDT 24
Finished Jun 05 05:59:44 PM PDT 24
Peak memory 218180 kb
Host smart-cadeeaed-0303-49dd-88cd-e4272f223878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611633297 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_prog_failure.1611633297
Directory /workspace/32.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_mubi.347063812
Short name T317
Test name
Test status
Simulation time 968557059 ps
CPU time 11.15 seconds
Started Jun 05 05:59:40 PM PDT 24
Finished Jun 05 05:59:52 PM PDT 24
Peak memory 218984 kb
Host smart-af3662eb-2d9f-4274-81eb-c92caf065b72
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347063812 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_mubi.347063812
Directory /workspace/32.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_digest.1700938876
Short name T681
Test name
Test status
Simulation time 2874858654 ps
CPU time 23.31 seconds
Started Jun 05 05:59:42 PM PDT 24
Finished Jun 05 06:00:06 PM PDT 24
Peak memory 226100 kb
Host smart-68e258a8-26d1-432e-84f6-ea9ed9c6c895
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700938876 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_d
igest.1700938876
Directory /workspace/32.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_mux.4293339430
Short name T233
Test name
Test status
Simulation time 593490119 ps
CPU time 8.71 seconds
Started Jun 05 05:59:40 PM PDT 24
Finished Jun 05 05:59:50 PM PDT 24
Peak memory 218044 kb
Host smart-9bbe0519-dcfd-4435-a8bc-965537285050
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293339430 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_mux.
4293339430
Directory /workspace/32.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/32.lc_ctrl_security_escalation.676368887
Short name T583
Test name
Test status
Simulation time 430311479 ps
CPU time 8.5 seconds
Started Jun 05 05:59:39 PM PDT 24
Finished Jun 05 05:59:48 PM PDT 24
Peak memory 218116 kb
Host smart-f8f9c024-8c1d-41ee-9a88-6132ec74ae0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676368887 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_security_escalation.676368887
Directory /workspace/32.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/32.lc_ctrl_smoke.379214060
Short name T835
Test name
Test status
Simulation time 15622691 ps
CPU time 1.32 seconds
Started Jun 05 05:59:51 PM PDT 24
Finished Jun 05 05:59:52 PM PDT 24
Peak memory 213292 kb
Host smart-a56fe013-5afe-4797-936b-14859496e190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379214060 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_smoke.379214060
Directory /workspace/32.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_failure.288442171
Short name T424
Test name
Test status
Simulation time 835337950 ps
CPU time 22 seconds
Started Jun 05 05:59:40 PM PDT 24
Finished Jun 05 06:00:03 PM PDT 24
Peak memory 251012 kb
Host smart-eeaba273-933e-49e1-abb1-d4f5f895ee5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288442171 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_failure.288442171
Directory /workspace/32.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_post_trans.3875813064
Short name T734
Test name
Test status
Simulation time 57909231 ps
CPU time 2.85 seconds
Started Jun 05 05:59:42 PM PDT 24
Finished Jun 05 05:59:45 PM PDT 24
Peak memory 218024 kb
Host smart-26e72834-ed12-4a51-8314-edb1c558b88d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875813064 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_post_trans.3875813064
Directory /workspace/32.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all.1197213274
Short name T828
Test name
Test status
Simulation time 6833908901 ps
CPU time 30.14 seconds
Started Jun 05 05:59:43 PM PDT 24
Finished Jun 05 06:00:14 PM PDT 24
Peak memory 216148 kb
Host smart-1a7a7044-1ef2-4b2d-8a30-c85f4c03b2a7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197213274 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.lc_ctrl_stress_all.1197213274
Directory /workspace/32.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.lc_ctrl_volatile_unlock_smoke.495415502
Short name T593
Test name
Test status
Simulation time 15840887 ps
CPU time 1.04 seconds
Started Jun 05 05:59:42 PM PDT 24
Finished Jun 05 05:59:44 PM PDT 24
Peak memory 208616 kb
Host smart-77180ba6-1c0f-4f28-90fe-936ed043a5a3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495415502 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ct
rl_volatile_unlock_smoke.495415502
Directory /workspace/32.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_alert_test.1886590388
Short name T485
Test name
Test status
Simulation time 56216385 ps
CPU time 0.86 seconds
Started Jun 05 05:59:39 PM PDT 24
Finished Jun 05 05:59:41 PM PDT 24
Peak memory 208660 kb
Host smart-444fc792-7d6f-4788-98ba-069b798c915b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886590388 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_alert_test.1886590388
Directory /workspace/33.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.lc_ctrl_errors.2377343217
Short name T36
Test name
Test status
Simulation time 1616556428 ps
CPU time 17.57 seconds
Started Jun 05 05:59:58 PM PDT 24
Finished Jun 05 06:00:16 PM PDT 24
Peak memory 218024 kb
Host smart-0e5507f6-4108-4f61-8ffd-e83be77a51c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377343217 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_errors.2377343217
Directory /workspace/33.lc_ctrl_errors/latest

Test location /workspace/coverage/default/33.lc_ctrl_jtag_access.3391933529
Short name T309
Test name
Test status
Simulation time 511366566 ps
CPU time 5.96 seconds
Started Jun 05 05:59:44 PM PDT 24
Finished Jun 05 05:59:51 PM PDT 24
Peak memory 209620 kb
Host smart-70b1f2f7-2c04-49f0-95bb-2683292dc35d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391933529 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_jtag_access.3391933529
Directory /workspace/33.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/33.lc_ctrl_prog_failure.2242810651
Short name T171
Test name
Test status
Simulation time 25202088 ps
CPU time 1.63 seconds
Started Jun 05 05:59:41 PM PDT 24
Finished Jun 05 05:59:44 PM PDT 24
Peak memory 218032 kb
Host smart-41c6963e-0aa2-4988-b55c-871b4baec057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242810651 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_prog_failure.2242810651
Directory /workspace/33.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_mubi.35374074
Short name T639
Test name
Test status
Simulation time 2417564743 ps
CPU time 15.22 seconds
Started Jun 05 05:59:43 PM PDT 24
Finished Jun 05 05:59:59 PM PDT 24
Peak memory 219048 kb
Host smart-031dd52f-dbf0-44fb-a9b8-0e5e4845b37e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35374074 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_mubi.35374074
Directory /workspace/33.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_digest.3959676831
Short name T584
Test name
Test status
Simulation time 5849469212 ps
CPU time 12.91 seconds
Started Jun 05 05:59:43 PM PDT 24
Finished Jun 05 05:59:56 PM PDT 24
Peak memory 218028 kb
Host smart-b6362b78-ac27-466b-81fa-010ddadd6385
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959676831 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_d
igest.3959676831
Directory /workspace/33.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_mux.1103278870
Short name T695
Test name
Test status
Simulation time 1385127661 ps
CPU time 11.75 seconds
Started Jun 05 05:59:44 PM PDT 24
Finished Jun 05 05:59:57 PM PDT 24
Peak memory 217968 kb
Host smart-26948de2-f773-4332-a00b-94e5a53d18d1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103278870 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_mux.
1103278870
Directory /workspace/33.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/33.lc_ctrl_security_escalation.3496867107
Short name T45
Test name
Test status
Simulation time 211697462 ps
CPU time 8.22 seconds
Started Jun 05 05:59:55 PM PDT 24
Finished Jun 05 06:00:04 PM PDT 24
Peak memory 218164 kb
Host smart-dd5c46bd-f01b-47fc-94ed-b144787203e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496867107 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_security_escalation.3496867107
Directory /workspace/33.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/33.lc_ctrl_smoke.874843133
Short name T108
Test name
Test status
Simulation time 15756571 ps
CPU time 1.02 seconds
Started Jun 05 05:59:40 PM PDT 24
Finished Jun 05 05:59:42 PM PDT 24
Peak memory 217752 kb
Host smart-285564dd-3cb7-4300-84b9-cd842d766d95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874843133 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_smoke.874843133
Directory /workspace/33.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_failure.3904816172
Short name T453
Test name
Test status
Simulation time 594019487 ps
CPU time 18.23 seconds
Started Jun 05 05:59:42 PM PDT 24
Finished Jun 05 06:00:01 PM PDT 24
Peak memory 251028 kb
Host smart-aefbba82-aff0-4b33-a15c-0964c8a27d7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904816172 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_failure.3904816172
Directory /workspace/33.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_post_trans.1111566749
Short name T569
Test name
Test status
Simulation time 83707252 ps
CPU time 7.8 seconds
Started Jun 05 05:59:41 PM PDT 24
Finished Jun 05 05:59:50 PM PDT 24
Peak memory 250588 kb
Host smart-3f39c0cb-2650-4638-aaac-ab5b6a23add8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111566749 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_post_trans.1111566749
Directory /workspace/33.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all.3465154318
Short name T733
Test name
Test status
Simulation time 5825117857 ps
CPU time 195.84 seconds
Started Jun 05 05:59:38 PM PDT 24
Finished Jun 05 06:02:55 PM PDT 24
Peak memory 283760 kb
Host smart-2ba7febd-9e41-492d-b1d0-db5d8e59df69
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465154318 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.lc_ctrl_stress_all.3465154318
Directory /workspace/33.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.lc_ctrl_volatile_unlock_smoke.3198646356
Short name T243
Test name
Test status
Simulation time 70503375 ps
CPU time 1.05 seconds
Started Jun 05 05:59:44 PM PDT 24
Finished Jun 05 05:59:46 PM PDT 24
Peak memory 211560 kb
Host smart-f6023152-529e-4046-91df-97d5f882f319
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198646356 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_c
trl_volatile_unlock_smoke.3198646356
Directory /workspace/33.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_alert_test.1521762482
Short name T803
Test name
Test status
Simulation time 20204756 ps
CPU time 0.94 seconds
Started Jun 05 05:59:50 PM PDT 24
Finished Jun 05 05:59:51 PM PDT 24
Peak memory 208744 kb
Host smart-ae6004b9-84fe-4318-bf1f-a3f584e73c9f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521762482 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_alert_test.1521762482
Directory /workspace/34.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.lc_ctrl_errors.2260035470
Short name T477
Test name
Test status
Simulation time 2747771083 ps
CPU time 17.89 seconds
Started Jun 05 05:59:54 PM PDT 24
Finished Jun 05 06:00:13 PM PDT 24
Peak memory 218044 kb
Host smart-c35ef42e-dcc2-4c34-ba82-c0ec9afc7f09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260035470 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_errors.2260035470
Directory /workspace/34.lc_ctrl_errors/latest

Test location /workspace/coverage/default/34.lc_ctrl_jtag_access.293556662
Short name T665
Test name
Test status
Simulation time 566174350 ps
CPU time 2.26 seconds
Started Jun 05 05:59:54 PM PDT 24
Finished Jun 05 05:59:57 PM PDT 24
Peak memory 209540 kb
Host smart-d0c2396f-57d8-4e8f-b870-82079cbd4241
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293556662 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_jtag_access.293556662
Directory /workspace/34.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/34.lc_ctrl_prog_failure.770542556
Short name T552
Test name
Test status
Simulation time 26541278 ps
CPU time 1.82 seconds
Started Jun 05 05:59:43 PM PDT 24
Finished Jun 05 05:59:46 PM PDT 24
Peak memory 218032 kb
Host smart-0549e623-1739-49b7-b968-8637ffdb0650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770542556 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_prog_failure.770542556
Directory /workspace/34.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_mubi.4218258665
Short name T672
Test name
Test status
Simulation time 809610244 ps
CPU time 13.14 seconds
Started Jun 05 05:59:55 PM PDT 24
Finished Jun 05 06:00:09 PM PDT 24
Peak memory 218044 kb
Host smart-7ff029df-8c00-4384-92ff-4f0c6a8bda89
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218258665 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_mubi.4218258665
Directory /workspace/34.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_digest.1495096198
Short name T794
Test name
Test status
Simulation time 4191154408 ps
CPU time 12.31 seconds
Started Jun 05 05:59:47 PM PDT 24
Finished Jun 05 06:00:00 PM PDT 24
Peak memory 218036 kb
Host smart-c23ced3c-c5ea-4433-920b-128ec6b7caff
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495096198 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_d
igest.1495096198
Directory /workspace/34.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_mux.1674782307
Short name T430
Test name
Test status
Simulation time 754524388 ps
CPU time 13.76 seconds
Started Jun 05 06:00:09 PM PDT 24
Finished Jun 05 06:00:23 PM PDT 24
Peak memory 218036 kb
Host smart-356d1884-0283-4917-9e07-92b21685eeae
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674782307 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_mux.
1674782307
Directory /workspace/34.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/34.lc_ctrl_security_escalation.2578557782
Short name T197
Test name
Test status
Simulation time 525898523 ps
CPU time 10.15 seconds
Started Jun 05 06:00:05 PM PDT 24
Finished Jun 05 06:00:16 PM PDT 24
Peak memory 218212 kb
Host smart-6419dc7e-7643-4f79-93e1-c0359b08676c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578557782 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_security_escalation.2578557782
Directory /workspace/34.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/34.lc_ctrl_smoke.2256860830
Short name T418
Test name
Test status
Simulation time 48496358 ps
CPU time 2.14 seconds
Started Jun 05 05:59:44 PM PDT 24
Finished Jun 05 05:59:48 PM PDT 24
Peak memory 217736 kb
Host smart-a5739a53-1b32-41e9-bae2-4d4b561686b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256860830 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_smoke.2256860830
Directory /workspace/34.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_failure.1154450287
Short name T606
Test name
Test status
Simulation time 631599743 ps
CPU time 26.22 seconds
Started Jun 05 05:59:55 PM PDT 24
Finished Jun 05 06:00:22 PM PDT 24
Peak memory 250956 kb
Host smart-4aa8e08b-8094-4be7-bf66-167f7bde483b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154450287 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_failure.1154450287
Directory /workspace/34.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_post_trans.2975850726
Short name T363
Test name
Test status
Simulation time 71381323 ps
CPU time 7.97 seconds
Started Jun 05 05:59:40 PM PDT 24
Finished Jun 05 05:59:49 PM PDT 24
Peak memory 251084 kb
Host smart-ac65a230-7e99-4636-b332-3b77df40ef07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975850726 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_post_trans.2975850726
Directory /workspace/34.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all.1176547302
Short name T402
Test name
Test status
Simulation time 9820148416 ps
CPU time 201.49 seconds
Started Jun 05 05:59:52 PM PDT 24
Finished Jun 05 06:03:14 PM PDT 24
Peak memory 281428 kb
Host smart-d7cb37bf-16f6-4627-bf22-7dddffbec479
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176547302 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.lc_ctrl_stress_all.1176547302
Directory /workspace/34.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all_with_rand_reset.106032192
Short name T50
Test name
Test status
Simulation time 39147044318 ps
CPU time 966.52 seconds
Started Jun 05 05:59:52 PM PDT 24
Finished Jun 05 06:15:59 PM PDT 24
Peak memory 458272 kb
Host smart-49c5a5c1-aff0-4387-9583-aa2500f42295
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=106032192 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_stress_all_with_rand_reset.106032192
Directory /workspace/34.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.lc_ctrl_volatile_unlock_smoke.1298756935
Short name T335
Test name
Test status
Simulation time 25105885 ps
CPU time 1.05 seconds
Started Jun 05 05:59:44 PM PDT 24
Finished Jun 05 05:59:46 PM PDT 24
Peak memory 211584 kb
Host smart-178dde74-4789-4938-9e59-e0064834ef4e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298756935 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_c
trl_volatile_unlock_smoke.1298756935
Directory /workspace/34.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_alert_test.2322568848
Short name T383
Test name
Test status
Simulation time 14787484 ps
CPU time 0.83 seconds
Started Jun 05 05:59:49 PM PDT 24
Finished Jun 05 05:59:50 PM PDT 24
Peak memory 209544 kb
Host smart-17aef98c-60d6-4408-aea8-73c86ecfb398
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322568848 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_alert_test.2322568848
Directory /workspace/35.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.lc_ctrl_errors.3973562204
Short name T93
Test name
Test status
Simulation time 993593896 ps
CPU time 9.5 seconds
Started Jun 05 05:59:55 PM PDT 24
Finished Jun 05 06:00:05 PM PDT 24
Peak memory 218084 kb
Host smart-b4e9e81c-d147-4eef-8368-1716f32abb4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973562204 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_errors.3973562204
Directory /workspace/35.lc_ctrl_errors/latest

Test location /workspace/coverage/default/35.lc_ctrl_jtag_access.707854887
Short name T321
Test name
Test status
Simulation time 4800992921 ps
CPU time 10.28 seconds
Started Jun 05 05:59:49 PM PDT 24
Finished Jun 05 06:00:00 PM PDT 24
Peak memory 217540 kb
Host smart-139d0b68-479e-4cca-ba5d-ff8ff20cef10
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707854887 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_jtag_access.707854887
Directory /workspace/35.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/35.lc_ctrl_prog_failure.2441098712
Short name T303
Test name
Test status
Simulation time 91185656 ps
CPU time 1.92 seconds
Started Jun 05 05:59:57 PM PDT 24
Finished Jun 05 05:59:59 PM PDT 24
Peak memory 218032 kb
Host smart-069ad064-3e36-4785-ac27-40dd3ce318d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441098712 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_prog_failure.2441098712
Directory /workspace/35.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_mubi.1657531974
Short name T723
Test name
Test status
Simulation time 1013297295 ps
CPU time 12.81 seconds
Started Jun 05 05:59:53 PM PDT 24
Finished Jun 05 06:00:07 PM PDT 24
Peak memory 218984 kb
Host smart-4d60812f-88df-4606-aa5b-947af1e9529d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657531974 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_mubi.1657531974
Directory /workspace/35.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_digest.1243246563
Short name T351
Test name
Test status
Simulation time 721491211 ps
CPU time 11.39 seconds
Started Jun 05 05:59:50 PM PDT 24
Finished Jun 05 06:00:02 PM PDT 24
Peak memory 217992 kb
Host smart-5491758b-4eb0-4e91-8d94-6f656e712d7d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243246563 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_d
igest.1243246563
Directory /workspace/35.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_mux.1469403959
Short name T103
Test name
Test status
Simulation time 285996036 ps
CPU time 8.59 seconds
Started Jun 05 05:59:58 PM PDT 24
Finished Jun 05 06:00:07 PM PDT 24
Peak memory 218096 kb
Host smart-650b4579-f0a9-4f7a-8489-7e648efc31b9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469403959 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_mux.
1469403959
Directory /workspace/35.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/35.lc_ctrl_security_escalation.608255937
Short name T199
Test name
Test status
Simulation time 1879606895 ps
CPU time 17.56 seconds
Started Jun 05 06:00:02 PM PDT 24
Finished Jun 05 06:00:20 PM PDT 24
Peak memory 218104 kb
Host smart-0db10b08-62bf-4d38-b3e2-7675513ea6b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608255937 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_security_escalation.608255937
Directory /workspace/35.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/35.lc_ctrl_smoke.72478392
Short name T718
Test name
Test status
Simulation time 284906467 ps
CPU time 4.36 seconds
Started Jun 05 05:59:47 PM PDT 24
Finished Jun 05 05:59:51 PM PDT 24
Peak memory 217784 kb
Host smart-4b2c73a3-1105-4a5e-aa51-5985d593b717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72478392 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_smoke.72478392
Directory /workspace/35.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_failure.3039531207
Short name T703
Test name
Test status
Simulation time 508983109 ps
CPU time 27.36 seconds
Started Jun 05 05:59:50 PM PDT 24
Finished Jun 05 06:00:18 PM PDT 24
Peak memory 251176 kb
Host smart-1c56f795-93db-4e52-8c49-074888a47f31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039531207 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_failure.3039531207
Directory /workspace/35.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_post_trans.1997926968
Short name T474
Test name
Test status
Simulation time 203392299 ps
CPU time 6.43 seconds
Started Jun 05 05:59:46 PM PDT 24
Finished Jun 05 05:59:53 PM PDT 24
Peak memory 248564 kb
Host smart-2f24137e-4f5b-452c-8126-276e49d5fd12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997926968 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_post_trans.1997926968
Directory /workspace/35.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all.4255674952
Short name T576
Test name
Test status
Simulation time 46943547876 ps
CPU time 206.16 seconds
Started Jun 05 05:59:52 PM PDT 24
Finished Jun 05 06:03:19 PM PDT 24
Peak memory 291016 kb
Host smart-9ce4b596-bbb6-4d9a-bdde-26125ca0ffba
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255674952 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.lc_ctrl_stress_all.4255674952
Directory /workspace/35.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.lc_ctrl_volatile_unlock_smoke.2289585689
Short name T558
Test name
Test status
Simulation time 28021900 ps
CPU time 1.09 seconds
Started Jun 05 05:59:58 PM PDT 24
Finished Jun 05 06:00:00 PM PDT 24
Peak memory 211680 kb
Host smart-6676f197-c31f-44fc-84c6-6ffb5768059c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289585689 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_c
trl_volatile_unlock_smoke.2289585689
Directory /workspace/35.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_alert_test.2830451667
Short name T268
Test name
Test status
Simulation time 55229777 ps
CPU time 1.04 seconds
Started Jun 05 05:59:48 PM PDT 24
Finished Jun 05 05:59:50 PM PDT 24
Peak memory 208748 kb
Host smart-8afd74cd-6f26-491d-8ebb-dce2faf7b0cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830451667 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_alert_test.2830451667
Directory /workspace/36.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.lc_ctrl_errors.2876565805
Short name T658
Test name
Test status
Simulation time 278365772 ps
CPU time 14.31 seconds
Started Jun 05 05:59:55 PM PDT 24
Finished Jun 05 06:00:10 PM PDT 24
Peak memory 218020 kb
Host smart-e87adc01-c7dc-48de-951f-290e3fb5c8ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876565805 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_errors.2876565805
Directory /workspace/36.lc_ctrl_errors/latest

Test location /workspace/coverage/default/36.lc_ctrl_jtag_access.2047022753
Short name T347
Test name
Test status
Simulation time 682156047 ps
CPU time 4.14 seconds
Started Jun 05 05:59:52 PM PDT 24
Finished Jun 05 05:59:57 PM PDT 24
Peak memory 209600 kb
Host smart-a047fe3a-a119-4d6c-bdf0-a0a7d6cbbeca
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047022753 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_jtag_access.2047022753
Directory /workspace/36.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/36.lc_ctrl_prog_failure.4019733166
Short name T830
Test name
Test status
Simulation time 73937325 ps
CPU time 2.69 seconds
Started Jun 05 06:00:05 PM PDT 24
Finished Jun 05 06:00:08 PM PDT 24
Peak memory 218032 kb
Host smart-52ab7ec6-48e0-4801-81f5-0b523d9e55f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019733166 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_prog_failure.4019733166
Directory /workspace/36.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_mubi.815606881
Short name T693
Test name
Test status
Simulation time 640738257 ps
CPU time 13.93 seconds
Started Jun 05 05:59:46 PM PDT 24
Finished Jun 05 06:00:00 PM PDT 24
Peak memory 218024 kb
Host smart-9a7c5eb0-94a1-40f7-a7d5-09f8b20bfa52
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815606881 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_mubi.815606881
Directory /workspace/36.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_digest.2947582494
Short name T595
Test name
Test status
Simulation time 551932546 ps
CPU time 14.08 seconds
Started Jun 05 05:59:49 PM PDT 24
Finished Jun 05 06:00:03 PM PDT 24
Peak memory 217972 kb
Host smart-ae2011f5-f0fa-46b1-97f7-f7c53410ca6d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947582494 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_d
igest.2947582494
Directory /workspace/36.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_mux.3376844472
Short name T394
Test name
Test status
Simulation time 2111162663 ps
CPU time 7.34 seconds
Started Jun 05 05:59:52 PM PDT 24
Finished Jun 05 06:00:00 PM PDT 24
Peak memory 218112 kb
Host smart-a4298069-1252-41ff-8476-8a84d5f80429
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376844472 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_mux.
3376844472
Directory /workspace/36.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/36.lc_ctrl_security_escalation.1728687587
Short name T787
Test name
Test status
Simulation time 906432037 ps
CPU time 7.11 seconds
Started Jun 05 05:59:49 PM PDT 24
Finished Jun 05 05:59:56 PM PDT 24
Peak memory 218092 kb
Host smart-0fbe3900-ce1e-4213-bb08-a2bde926bdc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728687587 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_security_escalation.1728687587
Directory /workspace/36.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/36.lc_ctrl_smoke.1482070732
Short name T71
Test name
Test status
Simulation time 393452211 ps
CPU time 1.19 seconds
Started Jun 05 05:59:47 PM PDT 24
Finished Jun 05 05:59:48 PM PDT 24
Peak memory 217756 kb
Host smart-ebb25317-d70b-4e28-b1a6-09c74f7d019c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482070732 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_smoke.1482070732
Directory /workspace/36.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_failure.1873690144
Short name T752
Test name
Test status
Simulation time 405850185 ps
CPU time 31.7 seconds
Started Jun 05 05:59:53 PM PDT 24
Finished Jun 05 06:00:25 PM PDT 24
Peak memory 250848 kb
Host smart-8d605cd1-53ed-4a2d-bfd6-d0f9a651f166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873690144 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_failure.1873690144
Directory /workspace/36.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_post_trans.4201054095
Short name T330
Test name
Test status
Simulation time 290016881 ps
CPU time 7.36 seconds
Started Jun 05 05:59:52 PM PDT 24
Finished Jun 05 06:00:00 PM PDT 24
Peak memory 251084 kb
Host smart-85d186ac-f6c0-42a7-833f-3cca28ca4dfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201054095 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_post_trans.4201054095
Directory /workspace/36.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all.2917457738
Short name T426
Test name
Test status
Simulation time 67906835145 ps
CPU time 518.7 seconds
Started Jun 05 05:59:53 PM PDT 24
Finished Jun 05 06:08:32 PM PDT 24
Peak memory 332988 kb
Host smart-60785734-41ed-45f1-8245-267948e88cf3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917457738 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.lc_ctrl_stress_all.2917457738
Directory /workspace/36.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.lc_ctrl_volatile_unlock_smoke.1961178645
Short name T492
Test name
Test status
Simulation time 40056576 ps
CPU time 0.79 seconds
Started Jun 05 05:59:57 PM PDT 24
Finished Jun 05 05:59:58 PM PDT 24
Peak memory 208720 kb
Host smart-ed539487-dda0-415b-898f-27ccd6e981c2
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961178645 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_c
trl_volatile_unlock_smoke.1961178645
Directory /workspace/36.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_alert_test.406343308
Short name T771
Test name
Test status
Simulation time 122460248 ps
CPU time 0.88 seconds
Started Jun 05 05:59:53 PM PDT 24
Finished Jun 05 05:59:55 PM PDT 24
Peak memory 208656 kb
Host smart-3155a3c6-bb7e-4094-90bf-f5745e324516
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406343308 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_alert_test.406343308
Directory /workspace/37.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.lc_ctrl_errors.3988883092
Short name T630
Test name
Test status
Simulation time 2527287277 ps
CPU time 16.27 seconds
Started Jun 05 05:59:48 PM PDT 24
Finished Jun 05 06:00:10 PM PDT 24
Peak memory 218108 kb
Host smart-9354e5d4-4530-4d3a-9809-20cc8b6b6e25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988883092 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_errors.3988883092
Directory /workspace/37.lc_ctrl_errors/latest

Test location /workspace/coverage/default/37.lc_ctrl_jtag_access.228699147
Short name T476
Test name
Test status
Simulation time 1290857687 ps
CPU time 12.46 seconds
Started Jun 05 05:59:52 PM PDT 24
Finished Jun 05 06:00:06 PM PDT 24
Peak memory 209528 kb
Host smart-900426db-65db-42f6-a72e-d7beb3844e99
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228699147 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_jtag_access.228699147
Directory /workspace/37.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/37.lc_ctrl_prog_failure.2799236206
Short name T778
Test name
Test status
Simulation time 281671644 ps
CPU time 3.88 seconds
Started Jun 05 05:59:57 PM PDT 24
Finished Jun 05 06:00:01 PM PDT 24
Peak memory 218100 kb
Host smart-eb15d684-148d-472d-a6ba-d06ed580deb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799236206 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_prog_failure.2799236206
Directory /workspace/37.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_mubi.3093849252
Short name T203
Test name
Test status
Simulation time 474208288 ps
CPU time 21.05 seconds
Started Jun 05 05:59:58 PM PDT 24
Finished Jun 05 06:00:20 PM PDT 24
Peak memory 218348 kb
Host smart-5e9e7fd4-89cf-43b4-924b-20084a7e2896
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093849252 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_mubi.3093849252
Directory /workspace/37.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_digest.1187022295
Short name T654
Test name
Test status
Simulation time 1052233066 ps
CPU time 9.37 seconds
Started Jun 05 05:59:54 PM PDT 24
Finished Jun 05 06:00:04 PM PDT 24
Peak memory 217952 kb
Host smart-65d2eaee-bde8-4b55-9fca-1e1d9b5cb7dd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187022295 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_d
igest.1187022295
Directory /workspace/37.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/37.lc_ctrl_security_escalation.4194182525
Short name T731
Test name
Test status
Simulation time 1064924241 ps
CPU time 8.62 seconds
Started Jun 05 05:59:55 PM PDT 24
Finished Jun 05 06:00:04 PM PDT 24
Peak memory 218072 kb
Host smart-cff22a47-8256-4a92-bcb3-84092e9f6d2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194182525 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_security_escalation.4194182525
Directory /workspace/37.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/37.lc_ctrl_smoke.1818625693
Short name T64
Test name
Test status
Simulation time 59101055 ps
CPU time 1.86 seconds
Started Jun 05 05:59:48 PM PDT 24
Finished Jun 05 05:59:51 PM PDT 24
Peak memory 217772 kb
Host smart-9c3a04c1-f1b1-4d76-a647-799aef21f67f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818625693 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_smoke.1818625693
Directory /workspace/37.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_failure.3777241693
Short name T225
Test name
Test status
Simulation time 6215201895 ps
CPU time 29.37 seconds
Started Jun 05 06:00:03 PM PDT 24
Finished Jun 05 06:00:32 PM PDT 24
Peak memory 251028 kb
Host smart-9b5a2c0f-325f-4fbd-9a69-9f8a2c5bbc9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777241693 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_failure.3777241693
Directory /workspace/37.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_post_trans.3256471443
Short name T207
Test name
Test status
Simulation time 77590288 ps
CPU time 6.25 seconds
Started Jun 05 06:00:01 PM PDT 24
Finished Jun 05 06:00:08 PM PDT 24
Peak memory 250516 kb
Host smart-50c50aff-ac00-46e7-80cd-7971cde135a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256471443 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_post_trans.3256471443
Directory /workspace/37.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all.845548264
Short name T757
Test name
Test status
Simulation time 23379064858 ps
CPU time 218.44 seconds
Started Jun 05 05:59:51 PM PDT 24
Finished Jun 05 06:03:30 PM PDT 24
Peak memory 251040 kb
Host smart-9433273a-2aa8-4409-b599-59e43b99c982
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845548264 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.lc_ctrl_stress_all.845548264
Directory /workspace/37.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all_with_rand_reset.3050261596
Short name T118
Test name
Test status
Simulation time 93171571054 ps
CPU time 575.28 seconds
Started Jun 05 05:59:59 PM PDT 24
Finished Jun 05 06:09:35 PM PDT 24
Peak memory 349508 kb
Host smart-0a697ff4-2e0b-4b50-a53b-318456b35e32
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3050261596 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_stress_all_with_rand_reset.3050261596
Directory /workspace/37.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.lc_ctrl_alert_test.3402422581
Short name T567
Test name
Test status
Simulation time 20617476 ps
CPU time 1.16 seconds
Started Jun 05 05:59:54 PM PDT 24
Finished Jun 05 05:59:56 PM PDT 24
Peak memory 209716 kb
Host smart-0a67178c-9100-41c2-b2ec-bc74848b692e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402422581 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_alert_test.3402422581
Directory /workspace/38.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.lc_ctrl_errors.4074109341
Short name T451
Test name
Test status
Simulation time 314134721 ps
CPU time 13.67 seconds
Started Jun 05 06:00:04 PM PDT 24
Finished Jun 05 06:00:19 PM PDT 24
Peak memory 218056 kb
Host smart-6aa9d2f6-ca4a-4f18-a73b-1e805f9a025d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074109341 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_errors.4074109341
Directory /workspace/38.lc_ctrl_errors/latest

Test location /workspace/coverage/default/38.lc_ctrl_jtag_access.394001658
Short name T7
Test name
Test status
Simulation time 446943449 ps
CPU time 3.34 seconds
Started Jun 05 05:59:53 PM PDT 24
Finished Jun 05 05:59:57 PM PDT 24
Peak memory 209540 kb
Host smart-ca4d5c85-fa55-4ac9-8dcd-758f13185495
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394001658 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_jtag_access.394001658
Directory /workspace/38.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/38.lc_ctrl_prog_failure.341241941
Short name T217
Test name
Test status
Simulation time 58681603 ps
CPU time 2.8 seconds
Started Jun 05 05:59:59 PM PDT 24
Finished Jun 05 06:00:02 PM PDT 24
Peak memory 218068 kb
Host smart-40651f85-4c16-4ce7-8327-d609062787f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341241941 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_prog_failure.341241941
Directory /workspace/38.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_digest.2068243914
Short name T720
Test name
Test status
Simulation time 1736332311 ps
CPU time 13.23 seconds
Started Jun 05 05:59:52 PM PDT 24
Finished Jun 05 06:00:06 PM PDT 24
Peak memory 217968 kb
Host smart-c5575eb6-13c8-4616-ab3b-9661ce9646f8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068243914 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_d
igest.2068243914
Directory /workspace/38.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_mux.3850036017
Short name T741
Test name
Test status
Simulation time 408281537 ps
CPU time 14.26 seconds
Started Jun 05 05:59:54 PM PDT 24
Finished Jun 05 06:00:08 PM PDT 24
Peak memory 218052 kb
Host smart-1f3b9a72-8849-4999-ac27-b85e8b6ca605
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850036017 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_mux.
3850036017
Directory /workspace/38.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/38.lc_ctrl_security_escalation.3369872330
Short name T754
Test name
Test status
Simulation time 4194432765 ps
CPU time 12.02 seconds
Started Jun 05 05:59:52 PM PDT 24
Finished Jun 05 06:00:04 PM PDT 24
Peak memory 218156 kb
Host smart-7bd3ad78-5ce6-4437-8240-98691d2080b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369872330 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_security_escalation.3369872330
Directory /workspace/38.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/38.lc_ctrl_smoke.3011278908
Short name T11
Test name
Test status
Simulation time 233868429 ps
CPU time 3.25 seconds
Started Jun 05 06:00:04 PM PDT 24
Finished Jun 05 06:00:08 PM PDT 24
Peak memory 217744 kb
Host smart-6eb746ca-c19a-48e2-94b9-ca60c2122555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011278908 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_smoke.3011278908
Directory /workspace/38.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_failure.3123339028
Short name T471
Test name
Test status
Simulation time 373667687 ps
CPU time 21.11 seconds
Started Jun 05 05:59:54 PM PDT 24
Finished Jun 05 06:00:16 PM PDT 24
Peak memory 250960 kb
Host smart-0ec23558-0bc1-4198-95c5-ec9239aa75db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123339028 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_failure.3123339028
Directory /workspace/38.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_post_trans.771891125
Short name T246
Test name
Test status
Simulation time 92723134 ps
CPU time 8.1 seconds
Started Jun 05 06:00:00 PM PDT 24
Finished Jun 05 06:00:09 PM PDT 24
Peak memory 251104 kb
Host smart-231ea9d5-5827-4e66-8741-cfc8299d7d07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771891125 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_post_trans.771891125
Directory /workspace/38.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all.941177853
Short name T52
Test name
Test status
Simulation time 3933561851 ps
CPU time 68.46 seconds
Started Jun 05 05:59:59 PM PDT 24
Finished Jun 05 06:01:08 PM PDT 24
Peak memory 251072 kb
Host smart-ba1a97e5-692c-4e98-89c5-63785852202b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941177853 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.lc_ctrl_stress_all.941177853
Directory /workspace/38.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all_with_rand_reset.3175237529
Short name T110
Test name
Test status
Simulation time 21754284714 ps
CPU time 1926.2 seconds
Started Jun 05 05:59:59 PM PDT 24
Finished Jun 05 06:32:06 PM PDT 24
Peak memory 917276 kb
Host smart-34cbdfaf-64dd-4c35-9ed9-36451721ee21
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3175237529 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_stress_all_with_rand_reset.3175237529
Directory /workspace/38.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.lc_ctrl_volatile_unlock_smoke.2359360813
Short name T463
Test name
Test status
Simulation time 79043974 ps
CPU time 1.05 seconds
Started Jun 05 06:00:03 PM PDT 24
Finished Jun 05 06:00:05 PM PDT 24
Peak memory 211304 kb
Host smart-e5bfc01a-1fe3-45ab-960f-76570d7b8c75
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359360813 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_c
trl_volatile_unlock_smoke.2359360813
Directory /workspace/38.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_alert_test.205381398
Short name T276
Test name
Test status
Simulation time 34886475 ps
CPU time 0.96 seconds
Started Jun 05 06:00:03 PM PDT 24
Finished Jun 05 06:00:05 PM PDT 24
Peak memory 208364 kb
Host smart-2872f324-01b1-4889-bef4-4f98cac3f7db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205381398 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_alert_test.205381398
Directory /workspace/39.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.lc_ctrl_errors.1534175915
Short name T543
Test name
Test status
Simulation time 269237917 ps
CPU time 9.6 seconds
Started Jun 05 05:59:54 PM PDT 24
Finished Jun 05 06:00:04 PM PDT 24
Peak memory 218060 kb
Host smart-c2ecfb34-78ea-4095-8798-2010609a62b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534175915 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_errors.1534175915
Directory /workspace/39.lc_ctrl_errors/latest

Test location /workspace/coverage/default/39.lc_ctrl_jtag_access.3999487123
Short name T342
Test name
Test status
Simulation time 107543724 ps
CPU time 1.43 seconds
Started Jun 05 05:59:56 PM PDT 24
Finished Jun 05 05:59:58 PM PDT 24
Peak memory 216924 kb
Host smart-57a8031c-05d9-459c-b4f8-70e253573818
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999487123 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_jtag_access.3999487123
Directory /workspace/39.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/39.lc_ctrl_prog_failure.977916252
Short name T211
Test name
Test status
Simulation time 66987054 ps
CPU time 3.41 seconds
Started Jun 05 05:59:57 PM PDT 24
Finished Jun 05 06:00:00 PM PDT 24
Peak memory 217964 kb
Host smart-bf262a86-4e63-4f0e-ac03-f6592df7bf13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977916252 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_prog_failure.977916252
Directory /workspace/39.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_mubi.3545878730
Short name T308
Test name
Test status
Simulation time 965681489 ps
CPU time 9.01 seconds
Started Jun 05 06:00:05 PM PDT 24
Finished Jun 05 06:00:15 PM PDT 24
Peak memory 218980 kb
Host smart-115f3e2f-46b0-4988-aae9-a7ac0d476b1f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545878730 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_mubi.3545878730
Directory /workspace/39.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_digest.4182452368
Short name T269
Test name
Test status
Simulation time 603997191 ps
CPU time 11.03 seconds
Started Jun 05 05:59:55 PM PDT 24
Finished Jun 05 06:00:06 PM PDT 24
Peak memory 217992 kb
Host smart-f043ec17-b4c7-41e0-af2f-a7c80771e87c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182452368 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_d
igest.4182452368
Directory /workspace/39.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_mux.295415749
Short name T826
Test name
Test status
Simulation time 8374337154 ps
CPU time 9.66 seconds
Started Jun 05 05:59:54 PM PDT 24
Finished Jun 05 06:00:05 PM PDT 24
Peak memory 218216 kb
Host smart-d9899dbc-9b2c-418e-bf12-525f4286d7bc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295415749 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_mux.295415749
Directory /workspace/39.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/39.lc_ctrl_security_escalation.1370546900
Short name T448
Test name
Test status
Simulation time 260651132 ps
CPU time 8.22 seconds
Started Jun 05 06:00:01 PM PDT 24
Finished Jun 05 06:00:10 PM PDT 24
Peak memory 218096 kb
Host smart-dd95540e-7e0d-4fa5-a2f1-5f14d1a769dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370546900 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_security_escalation.1370546900
Directory /workspace/39.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/39.lc_ctrl_smoke.1163195464
Short name T353
Test name
Test status
Simulation time 47734588 ps
CPU time 1.62 seconds
Started Jun 05 06:00:04 PM PDT 24
Finished Jun 05 06:00:07 PM PDT 24
Peak memory 217732 kb
Host smart-9bca76d7-1176-42f4-8275-005ae0694432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163195464 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_smoke.1163195464
Directory /workspace/39.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_failure.517132969
Short name T414
Test name
Test status
Simulation time 870826405 ps
CPU time 28.72 seconds
Started Jun 05 05:59:54 PM PDT 24
Finished Jun 05 06:00:24 PM PDT 24
Peak memory 251020 kb
Host smart-ed603323-6576-46aa-9c8d-23c11017bf49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517132969 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_failure.517132969
Directory /workspace/39.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_post_trans.1646241291
Short name T360
Test name
Test status
Simulation time 311989123 ps
CPU time 5.99 seconds
Started Jun 05 05:59:58 PM PDT 24
Finished Jun 05 06:00:05 PM PDT 24
Peak memory 246376 kb
Host smart-66eace54-0cc6-4064-a27a-9dfc2488d208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646241291 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_post_trans.1646241291
Directory /workspace/39.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all.3030690857
Short name T391
Test name
Test status
Simulation time 36605331484 ps
CPU time 231.93 seconds
Started Jun 05 05:59:55 PM PDT 24
Finished Jun 05 06:03:47 PM PDT 24
Peak memory 250936 kb
Host smart-9e0ea0c9-18ac-4de3-be6b-c324bfabfa2b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030690857 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.lc_ctrl_stress_all.3030690857
Directory /workspace/39.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.lc_ctrl_volatile_unlock_smoke.1243640456
Short name T255
Test name
Test status
Simulation time 13021512 ps
CPU time 0.79 seconds
Started Jun 05 05:59:54 PM PDT 24
Finished Jun 05 05:59:55 PM PDT 24
Peak memory 208788 kb
Host smart-6fafb853-6da4-4e6e-815f-dabf27e3697d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243640456 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_c
trl_volatile_unlock_smoke.1243640456
Directory /workspace/39.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_alert_test.2307134764
Short name T401
Test name
Test status
Simulation time 62177354 ps
CPU time 0.85 seconds
Started Jun 05 05:58:45 PM PDT 24
Finished Jun 05 05:58:48 PM PDT 24
Peak memory 208708 kb
Host smart-92d46fe1-fbb8-40aa-91c2-c1f13dbae477
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307134764 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_alert_test.2307134764
Directory /workspace/4.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.lc_ctrl_claim_transition_if.2555013023
Short name T194
Test name
Test status
Simulation time 33597588 ps
CPU time 0.93 seconds
Started Jun 05 05:58:36 PM PDT 24
Finished Jun 05 05:58:38 PM PDT 24
Peak memory 208664 kb
Host smart-7fc55796-1897-46e5-9fd6-facf197792d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555013023 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_claim_transition_if.2555013023
Directory /workspace/4.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/4.lc_ctrl_errors.3061962285
Short name T559
Test name
Test status
Simulation time 616121643 ps
CPU time 9.69 seconds
Started Jun 05 05:58:35 PM PDT 24
Finished Jun 05 05:58:46 PM PDT 24
Peak memory 218056 kb
Host smart-baff9b6c-fcab-4bac-b004-a4e5c4068b72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061962285 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_errors.3061962285
Directory /workspace/4.lc_ctrl_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_access.3987632878
Short name T789
Test name
Test status
Simulation time 395056141 ps
CPU time 10.87 seconds
Started Jun 05 05:58:35 PM PDT 24
Finished Jun 05 05:58:46 PM PDT 24
Peak memory 217320 kb
Host smart-1f38cbac-241e-41a8-9f53-d8a3fa59dc0e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987632878 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_access.3987632878
Directory /workspace/4.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_errors.1814357749
Short name T31
Test name
Test status
Simulation time 4880660685 ps
CPU time 25.91 seconds
Started Jun 05 05:58:35 PM PDT 24
Finished Jun 05 05:59:02 PM PDT 24
Peak memory 218500 kb
Host smart-2847992e-5e20-4c03-ad4f-8da0d68da2c6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814357749 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_er
rors.1814357749
Directory /workspace/4.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_priority.213664465
Short name T634
Test name
Test status
Simulation time 712195736 ps
CPU time 8.48 seconds
Started Jun 05 05:58:41 PM PDT 24
Finished Jun 05 05:58:51 PM PDT 24
Peak memory 217424 kb
Host smart-75169b61-2a7b-4d7f-b40a-27ce33ad9a84
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213664465 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_priority.213664465
Directory /workspace/4.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_prog_failure.172910566
Short name T252
Test name
Test status
Simulation time 1449728799 ps
CPU time 6.47 seconds
Started Jun 05 05:58:45 PM PDT 24
Finished Jun 05 05:58:54 PM PDT 24
Peak memory 218040 kb
Host smart-db73ee75-b027-4364-be88-7fbc2aa486d2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172910566 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_
prog_failure.172910566
Directory /workspace/4.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_regwen_during_op.3761047135
Short name T16
Test name
Test status
Simulation time 1440507233 ps
CPU time 20.86 seconds
Started Jun 05 05:58:49 PM PDT 24
Finished Jun 05 05:59:12 PM PDT 24
Peak memory 217672 kb
Host smart-7e1d430f-707f-4edf-ae86-7f413ac73acb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761047135 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_regwen_during_op.3761047135
Directory /workspace/4.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_smoke.2214356874
Short name T62
Test name
Test status
Simulation time 461462035 ps
CPU time 7.41 seconds
Started Jun 05 05:58:48 PM PDT 24
Finished Jun 05 05:58:58 PM PDT 24
Peak memory 217848 kb
Host smart-60f8a419-d8dd-4f44-9135-a350058be4a0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214356874 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_smoke.
2214356874
Directory /workspace/4.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_failure.3161585876
Short name T682
Test name
Test status
Simulation time 2558019753 ps
CPU time 47.15 seconds
Started Jun 05 05:58:37 PM PDT 24
Finished Jun 05 05:59:30 PM PDT 24
Peak memory 267424 kb
Host smart-8e02319f-828a-4bfe-900e-e6c228e6dd57
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161585876 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jta
g_state_failure.3161585876
Directory /workspace/4.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_post_trans.3140200042
Short name T661
Test name
Test status
Simulation time 3800672394 ps
CPU time 28.98 seconds
Started Jun 05 05:58:35 PM PDT 24
Finished Jun 05 05:59:06 PM PDT 24
Peak memory 250668 kb
Host smart-c63984dc-3126-46b9-a5b2-95286ccd6a8e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140200042 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_state_post_trans.3140200042
Directory /workspace/4.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_prog_failure.1359601361
Short name T659
Test name
Test status
Simulation time 117805556 ps
CPU time 2.66 seconds
Started Jun 05 05:58:43 PM PDT 24
Finished Jun 05 05:58:47 PM PDT 24
Peak memory 218148 kb
Host smart-bcb8668a-ee46-400e-9310-bdf45b40e1c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359601361 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_prog_failure.1359601361
Directory /workspace/4.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_regwen_during_op.1209355336
Short name T175
Test name
Test status
Simulation time 459993381 ps
CPU time 9.72 seconds
Started Jun 05 05:58:33 PM PDT 24
Finished Jun 05 05:58:43 PM PDT 24
Peak memory 214548 kb
Host smart-1fd086ee-34e9-468c-b583-5c03c97ab113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209355336 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_regwen_during_op.1209355336
Directory /workspace/4.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_cm.2163448422
Short name T83
Test name
Test status
Simulation time 1231871840 ps
CPU time 22.07 seconds
Started Jun 05 05:58:44 PM PDT 24
Finished Jun 05 05:59:09 PM PDT 24
Peak memory 284568 kb
Host smart-219f337b-c9da-4692-8ad6-d1fe958be132
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163448422 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_cm.2163448422
Directory /workspace/4.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_mubi.1087768869
Short name T436
Test name
Test status
Simulation time 413505197 ps
CPU time 10.32 seconds
Started Jun 05 05:58:38 PM PDT 24
Finished Jun 05 05:58:50 PM PDT 24
Peak memory 218988 kb
Host smart-d020ca10-851b-47a3-8a29-688f87ed1b54
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087768869 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_mubi.1087768869
Directory /workspace/4.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_digest.2641331633
Short name T125
Test name
Test status
Simulation time 2275880957 ps
CPU time 14.08 seconds
Started Jun 05 05:58:48 PM PDT 24
Finished Jun 05 05:59:05 PM PDT 24
Peak memory 226128 kb
Host smart-06e3eedd-5309-4e80-a52f-bfe2b42c636b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641331633 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_di
gest.2641331633
Directory /workspace/4.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_mux.4044961400
Short name T223
Test name
Test status
Simulation time 184202128 ps
CPU time 5.97 seconds
Started Jun 05 05:58:33 PM PDT 24
Finished Jun 05 05:58:40 PM PDT 24
Peak memory 218284 kb
Host smart-de2aae03-3621-4ad6-85c4-b1fd73078362
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044961400 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_mux.4
044961400
Directory /workspace/4.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/4.lc_ctrl_security_escalation.3456123275
Short name T598
Test name
Test status
Simulation time 584867147 ps
CPU time 9.36 seconds
Started Jun 05 05:58:42 PM PDT 24
Finished Jun 05 05:58:53 PM PDT 24
Peak memory 218164 kb
Host smart-e8e081f0-89d3-4f75-95ad-04f33d3a57ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456123275 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_security_escalation.3456123275
Directory /workspace/4.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/4.lc_ctrl_smoke.1338839914
Short name T468
Test name
Test status
Simulation time 70682169 ps
CPU time 2.73 seconds
Started Jun 05 05:58:41 PM PDT 24
Finished Jun 05 05:58:44 PM PDT 24
Peak memory 217776 kb
Host smart-a917a5eb-a948-4885-87a6-cdbaed2ec070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338839914 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_smoke.1338839914
Directory /workspace/4.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_failure.1898090304
Short name T750
Test name
Test status
Simulation time 252846457 ps
CPU time 27.88 seconds
Started Jun 05 05:58:38 PM PDT 24
Finished Jun 05 05:59:07 PM PDT 24
Peak memory 251008 kb
Host smart-7fc16134-a0e8-4c80-a46b-edb7b6d724bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898090304 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_failure.1898090304
Directory /workspace/4.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_post_trans.660301031
Short name T570
Test name
Test status
Simulation time 194758386 ps
CPU time 7.16 seconds
Started Jun 05 05:58:36 PM PDT 24
Finished Jun 05 05:58:44 PM PDT 24
Peak memory 250808 kb
Host smart-194110ef-9ed4-4f9d-a43f-7ba77eb89583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660301031 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_post_trans.660301031
Directory /workspace/4.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_stress_all_with_rand_reset.3919418803
Short name T42
Test name
Test status
Simulation time 13402866440 ps
CPU time 258.53 seconds
Started Jun 05 05:59:02 PM PDT 24
Finished Jun 05 06:03:21 PM PDT 24
Peak memory 267564 kb
Host smart-4eeec58c-a9f2-4a68-9d34-6e264cb18a82
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3919418803 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_stress_all_with_rand_reset.3919418803
Directory /workspace/4.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.lc_ctrl_volatile_unlock_smoke.3071743162
Short name T452
Test name
Test status
Simulation time 25193424 ps
CPU time 0.91 seconds
Started Jun 05 05:58:36 PM PDT 24
Finished Jun 05 05:58:38 PM PDT 24
Peak memory 211616 kb
Host smart-d4a4bf68-f2fb-48de-9c59-b17ab03844ba
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071743162 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ct
rl_volatile_unlock_smoke.3071743162
Directory /workspace/4.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_alert_test.521575738
Short name T328
Test name
Test status
Simulation time 21432544 ps
CPU time 1.17 seconds
Started Jun 05 06:00:09 PM PDT 24
Finished Jun 05 06:00:11 PM PDT 24
Peak memory 209544 kb
Host smart-789ee91c-dae5-4cc3-9011-3e5d587bb5d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521575738 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_alert_test.521575738
Directory /workspace/40.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.lc_ctrl_errors.2885873678
Short name T804
Test name
Test status
Simulation time 227527928 ps
CPU time 8.24 seconds
Started Jun 05 05:59:53 PM PDT 24
Finished Jun 05 06:00:02 PM PDT 24
Peak memory 217992 kb
Host smart-c882b67c-6916-4eec-bfca-73951aa30c35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885873678 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_errors.2885873678
Directory /workspace/40.lc_ctrl_errors/latest

Test location /workspace/coverage/default/40.lc_ctrl_jtag_access.1993593195
Short name T736
Test name
Test status
Simulation time 537897733 ps
CPU time 4.06 seconds
Started Jun 05 05:59:59 PM PDT 24
Finished Jun 05 06:00:03 PM PDT 24
Peak memory 216988 kb
Host smart-961ef3fd-46a9-4a04-b248-b2797a0465b5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993593195 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_jtag_access.1993593195
Directory /workspace/40.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/40.lc_ctrl_prog_failure.3275017663
Short name T361
Test name
Test status
Simulation time 167232425 ps
CPU time 2.5 seconds
Started Jun 05 05:59:58 PM PDT 24
Finished Jun 05 06:00:01 PM PDT 24
Peak memory 218032 kb
Host smart-7cfb247b-e325-43e8-9737-8a2b0a931c5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275017663 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_prog_failure.3275017663
Directory /workspace/40.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_mubi.2583335470
Short name T392
Test name
Test status
Simulation time 1226207104 ps
CPU time 16.15 seconds
Started Jun 05 05:59:57 PM PDT 24
Finished Jun 05 06:00:14 PM PDT 24
Peak memory 218988 kb
Host smart-d58351cd-3cbc-4f60-9ace-c1d657036a9a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583335470 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_mubi.2583335470
Directory /workspace/40.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_digest.2125864453
Short name T769
Test name
Test status
Simulation time 1702173459 ps
CPU time 17.26 seconds
Started Jun 05 06:00:16 PM PDT 24
Finished Jun 05 06:00:35 PM PDT 24
Peak memory 226060 kb
Host smart-b4a147ad-a34d-4b97-ba76-fec42a0fa997
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125864453 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_d
igest.2125864453
Directory /workspace/40.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_mux.3340315796
Short name T102
Test name
Test status
Simulation time 2398150768 ps
CPU time 10.78 seconds
Started Jun 05 06:00:09 PM PDT 24
Finished Jun 05 06:00:20 PM PDT 24
Peak memory 218140 kb
Host smart-0770ba77-294b-45d8-824e-c425138bcd2d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340315796 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_mux.
3340315796
Directory /workspace/40.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/40.lc_ctrl_security_escalation.2303099891
Short name T620
Test name
Test status
Simulation time 208181431 ps
CPU time 8.72 seconds
Started Jun 05 05:59:54 PM PDT 24
Finished Jun 05 06:00:03 PM PDT 24
Peak memory 218092 kb
Host smart-a4fe59f4-9f1d-4ac1-8fa5-88ed4ed884dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303099891 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_security_escalation.2303099891
Directory /workspace/40.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/40.lc_ctrl_smoke.1516663761
Short name T604
Test name
Test status
Simulation time 51540521 ps
CPU time 1.59 seconds
Started Jun 05 06:00:05 PM PDT 24
Finished Jun 05 06:00:07 PM PDT 24
Peak memory 213628 kb
Host smart-530a8211-d088-4e98-8cca-4de22b854744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516663761 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_smoke.1516663761
Directory /workspace/40.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_failure.1231446877
Short name T81
Test name
Test status
Simulation time 375239095 ps
CPU time 21.45 seconds
Started Jun 05 05:59:53 PM PDT 24
Finished Jun 05 06:00:15 PM PDT 24
Peak memory 251048 kb
Host smart-5cf241d7-af23-4273-b8a9-470b0bc2edb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231446877 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_failure.1231446877
Directory /workspace/40.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_post_trans.2199737856
Short name T689
Test name
Test status
Simulation time 295106867 ps
CPU time 7.73 seconds
Started Jun 05 05:59:53 PM PDT 24
Finished Jun 05 06:00:01 PM PDT 24
Peak memory 251008 kb
Host smart-333e4feb-484f-4f61-82ce-6f05e2277ac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199737856 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_post_trans.2199737856
Directory /workspace/40.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/40.lc_ctrl_stress_all.1287480101
Short name T507
Test name
Test status
Simulation time 4889452779 ps
CPU time 55.31 seconds
Started Jun 05 06:00:14 PM PDT 24
Finished Jun 05 06:01:10 PM PDT 24
Peak memory 250968 kb
Host smart-fa5e324b-b97b-441c-96ac-1a142bf34eb9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287480101 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.lc_ctrl_stress_all.1287480101
Directory /workspace/40.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.lc_ctrl_volatile_unlock_smoke.3185506562
Short name T633
Test name
Test status
Simulation time 33363595 ps
CPU time 0.85 seconds
Started Jun 05 05:59:52 PM PDT 24
Finished Jun 05 05:59:54 PM PDT 24
Peak memory 208636 kb
Host smart-112506d8-f658-4f55-9580-e39fff90462a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185506562 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_c
trl_volatile_unlock_smoke.3185506562
Directory /workspace/40.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_alert_test.881361289
Short name T663
Test name
Test status
Simulation time 24621312 ps
CPU time 1.22 seconds
Started Jun 05 06:00:27 PM PDT 24
Finished Jun 05 06:00:30 PM PDT 24
Peak memory 209572 kb
Host smart-a5bd4367-abc4-4140-8221-2b97810a1334
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881361289 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_alert_test.881361289
Directory /workspace/41.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.lc_ctrl_errors.2648002435
Short name T674
Test name
Test status
Simulation time 1962848652 ps
CPU time 25.77 seconds
Started Jun 05 06:00:18 PM PDT 24
Finished Jun 05 06:00:45 PM PDT 24
Peak memory 218064 kb
Host smart-58f515ea-a476-4f7c-969b-59909cebbf46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648002435 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_errors.2648002435
Directory /workspace/41.lc_ctrl_errors/latest

Test location /workspace/coverage/default/41.lc_ctrl_jtag_access.4149968548
Short name T817
Test name
Test status
Simulation time 491210476 ps
CPU time 4.01 seconds
Started Jun 05 06:00:19 PM PDT 24
Finished Jun 05 06:00:24 PM PDT 24
Peak memory 209548 kb
Host smart-0400bc96-81b7-40a7-b919-dc6eefeafbbb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149968548 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_jtag_access.4149968548
Directory /workspace/41.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/41.lc_ctrl_prog_failure.624812532
Short name T858
Test name
Test status
Simulation time 83186529 ps
CPU time 2.56 seconds
Started Jun 05 06:00:05 PM PDT 24
Finished Jun 05 06:00:08 PM PDT 24
Peak memory 218060 kb
Host smart-0fc3b15a-97df-402c-a298-f130c32ce166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624812532 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_prog_failure.624812532
Directory /workspace/41.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_mubi.442364847
Short name T708
Test name
Test status
Simulation time 628853668 ps
CPU time 10.69 seconds
Started Jun 05 06:00:16 PM PDT 24
Finished Jun 05 06:00:28 PM PDT 24
Peak memory 218980 kb
Host smart-b76396b6-1f5b-4914-9dd6-5ddbae0a9c9b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442364847 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_mubi.442364847
Directory /workspace/41.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_digest.225933594
Short name T431
Test name
Test status
Simulation time 459745414 ps
CPU time 12.67 seconds
Started Jun 05 06:00:23 PM PDT 24
Finished Jun 05 06:00:36 PM PDT 24
Peak memory 217984 kb
Host smart-2345aff6-2418-4d1a-8a7e-7e5d3df8410a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225933594 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_di
gest.225933594
Directory /workspace/41.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_mux.3316948707
Short name T521
Test name
Test status
Simulation time 1629860947 ps
CPU time 15.37 seconds
Started Jun 05 06:00:02 PM PDT 24
Finished Jun 05 06:00:17 PM PDT 24
Peak memory 218024 kb
Host smart-8bd06830-7a8d-4273-b67c-e2dd4ab07723
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316948707 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_mux.
3316948707
Directory /workspace/41.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/41.lc_ctrl_security_escalation.298343474
Short name T486
Test name
Test status
Simulation time 541628892 ps
CPU time 12.05 seconds
Started Jun 05 06:00:06 PM PDT 24
Finished Jun 05 06:00:18 PM PDT 24
Peak memory 225004 kb
Host smart-7bf8d781-e45a-41e6-a7d5-b3802d47358c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=298343474 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_security_escalation.298343474
Directory /workspace/41.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/41.lc_ctrl_smoke.2300410871
Short name T762
Test name
Test status
Simulation time 358856794 ps
CPU time 3.2 seconds
Started Jun 05 06:00:08 PM PDT 24
Finished Jun 05 06:00:12 PM PDT 24
Peak memory 214800 kb
Host smart-2e0512c7-edc9-496d-9496-63fd8f30c1cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300410871 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_smoke.2300410871
Directory /workspace/41.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_failure.710406575
Short name T271
Test name
Test status
Simulation time 485367645 ps
CPU time 22.61 seconds
Started Jun 05 06:00:14 PM PDT 24
Finished Jun 05 06:00:37 PM PDT 24
Peak memory 251000 kb
Host smart-dcda6bfb-8a82-49b8-b10e-4c350e6e7360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710406575 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_failure.710406575
Directory /workspace/41.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_post_trans.3414485129
Short name T683
Test name
Test status
Simulation time 211683504 ps
CPU time 3.04 seconds
Started Jun 05 06:00:20 PM PDT 24
Finished Jun 05 06:00:24 PM PDT 24
Peak memory 222552 kb
Host smart-1f1be51f-0b14-4463-8496-3c60947d658c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414485129 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_post_trans.3414485129
Directory /workspace/41.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all.944179743
Short name T57
Test name
Test status
Simulation time 22755979132 ps
CPU time 321.74 seconds
Started Jun 05 06:00:09 PM PDT 24
Finished Jun 05 06:05:31 PM PDT 24
Peak memory 251888 kb
Host smart-9c6b03c0-3b48-4964-accf-92fdfed28e1e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944179743 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.lc_ctrl_stress_all.944179743
Directory /workspace/41.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.lc_ctrl_volatile_unlock_smoke.2732079669
Short name T258
Test name
Test status
Simulation time 13068633 ps
CPU time 0.75 seconds
Started Jun 05 06:00:06 PM PDT 24
Finished Jun 05 06:00:07 PM PDT 24
Peak memory 207856 kb
Host smart-204b9cff-0797-4db6-80b1-3103379298dc
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732079669 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_c
trl_volatile_unlock_smoke.2732079669
Directory /workspace/41.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_alert_test.4054695805
Short name T855
Test name
Test status
Simulation time 83941558 ps
CPU time 1.21 seconds
Started Jun 05 06:00:11 PM PDT 24
Finished Jun 05 06:00:13 PM PDT 24
Peak memory 208748 kb
Host smart-ad320090-a817-47fe-a2dd-c5880b262f55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054695805 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_alert_test.4054695805
Directory /workspace/42.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.lc_ctrl_errors.3139153832
Short name T514
Test name
Test status
Simulation time 327403206 ps
CPU time 10.46 seconds
Started Jun 05 06:00:13 PM PDT 24
Finished Jun 05 06:00:24 PM PDT 24
Peak memory 217956 kb
Host smart-c859bbf1-31e5-45b7-bcf2-0cb7ec340f6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139153832 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_errors.3139153832
Directory /workspace/42.lc_ctrl_errors/latest

Test location /workspace/coverage/default/42.lc_ctrl_jtag_access.2991295774
Short name T660
Test name
Test status
Simulation time 517753820 ps
CPU time 3.7 seconds
Started Jun 05 06:00:18 PM PDT 24
Finished Jun 05 06:00:23 PM PDT 24
Peak memory 209548 kb
Host smart-ba64d8b6-96d6-4983-baac-dbcf7a13dc0b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991295774 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_jtag_access.2991295774
Directory /workspace/42.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/42.lc_ctrl_prog_failure.2206638130
Short name T434
Test name
Test status
Simulation time 320179962 ps
CPU time 1.58 seconds
Started Jun 05 06:00:06 PM PDT 24
Finished Jun 05 06:00:08 PM PDT 24
Peak memory 218108 kb
Host smart-bdbb3b1b-a43c-4d1c-a1f6-ac369cdd2255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206638130 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_prog_failure.2206638130
Directory /workspace/42.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_mubi.3682145259
Short name T590
Test name
Test status
Simulation time 1010029790 ps
CPU time 11.61 seconds
Started Jun 05 06:00:04 PM PDT 24
Finished Jun 05 06:00:17 PM PDT 24
Peak memory 218976 kb
Host smart-fc4909af-004a-4fe3-8588-84727a451a02
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682145259 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_mubi.3682145259
Directory /workspace/42.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_digest.3487483487
Short name T352
Test name
Test status
Simulation time 421325687 ps
CPU time 11.95 seconds
Started Jun 05 06:00:13 PM PDT 24
Finished Jun 05 06:00:25 PM PDT 24
Peak memory 226044 kb
Host smart-b295db3a-8c55-4304-800a-08bdd8f076c9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487483487 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_d
igest.3487483487
Directory /workspace/42.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_mux.1084770648
Short name T686
Test name
Test status
Simulation time 1600559240 ps
CPU time 10.67 seconds
Started Jun 05 06:00:17 PM PDT 24
Finished Jun 05 06:00:28 PM PDT 24
Peak memory 218124 kb
Host smart-aae154d4-a5b5-48ab-81e5-bffb6c055067
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084770648 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_mux.
1084770648
Directory /workspace/42.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/42.lc_ctrl_security_escalation.3167207035
Short name T612
Test name
Test status
Simulation time 1217694666 ps
CPU time 11.83 seconds
Started Jun 05 06:00:12 PM PDT 24
Finished Jun 05 06:00:24 PM PDT 24
Peak memory 224676 kb
Host smart-527c40ca-e5c9-4c80-9c99-dda83cd607c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167207035 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_security_escalation.3167207035
Directory /workspace/42.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/42.lc_ctrl_smoke.1334126562
Short name T770
Test name
Test status
Simulation time 118948347 ps
CPU time 1.37 seconds
Started Jun 05 06:00:08 PM PDT 24
Finished Jun 05 06:00:10 PM PDT 24
Peak memory 217756 kb
Host smart-916d5481-3f3c-4dcc-b225-c9efac977f28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334126562 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_smoke.1334126562
Directory /workspace/42.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_failure.1310587687
Short name T825
Test name
Test status
Simulation time 469144434 ps
CPU time 31.59 seconds
Started Jun 05 06:00:27 PM PDT 24
Finished Jun 05 06:00:59 PM PDT 24
Peak memory 251024 kb
Host smart-b9c6bc22-1f7c-4da8-8c70-f4974f9ec279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310587687 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_failure.1310587687
Directory /workspace/42.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_post_trans.152262198
Short name T230
Test name
Test status
Simulation time 82659604 ps
CPU time 6.79 seconds
Started Jun 05 06:00:16 PM PDT 24
Finished Jun 05 06:00:24 PM PDT 24
Peak memory 250432 kb
Host smart-3f53712a-789b-4ee7-a434-cd02b9918989
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152262198 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_post_trans.152262198
Directory /workspace/42.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/42.lc_ctrl_stress_all.706195998
Short name T443
Test name
Test status
Simulation time 21094946333 ps
CPU time 115.26 seconds
Started Jun 05 06:00:12 PM PDT 24
Finished Jun 05 06:02:08 PM PDT 24
Peak memory 249564 kb
Host smart-9a9d821c-9056-471d-90e8-35d6dc81f98c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706195998 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.lc_ctrl_stress_all.706195998
Directory /workspace/42.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.lc_ctrl_stress_all_with_rand_reset.3924940978
Short name T155
Test name
Test status
Simulation time 115868616454 ps
CPU time 1069.05 seconds
Started Jun 05 06:00:11 PM PDT 24
Finished Jun 05 06:18:01 PM PDT 24
Peak memory 496936 kb
Host smart-d70979cc-46a2-4310-831d-08bb4f45e265
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3924940978 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_stress_all_with_rand_reset.3924940978
Directory /workspace/42.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.lc_ctrl_volatile_unlock_smoke.3885398481
Short name T836
Test name
Test status
Simulation time 54363646 ps
CPU time 0.76 seconds
Started Jun 05 06:00:13 PM PDT 24
Finished Jun 05 06:00:14 PM PDT 24
Peak memory 208400 kb
Host smart-c91bfa49-eab9-4089-9c53-dd6c9ece2578
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885398481 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_c
trl_volatile_unlock_smoke.3885398481
Directory /workspace/42.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_alert_test.2234956202
Short name T813
Test name
Test status
Simulation time 38549974 ps
CPU time 1.12 seconds
Started Jun 05 06:00:12 PM PDT 24
Finished Jun 05 06:00:14 PM PDT 24
Peak memory 208808 kb
Host smart-c8d25ca7-9bce-46c9-b918-97b0cf6d28ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234956202 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_alert_test.2234956202
Directory /workspace/43.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.lc_ctrl_errors.1454209346
Short name T329
Test name
Test status
Simulation time 1944390113 ps
CPU time 11.18 seconds
Started Jun 05 06:00:32 PM PDT 24
Finished Jun 05 06:00:44 PM PDT 24
Peak memory 218024 kb
Host smart-b348a786-a9a2-4033-9aef-9e5038dc41b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454209346 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_errors.1454209346
Directory /workspace/43.lc_ctrl_errors/latest

Test location /workspace/coverage/default/43.lc_ctrl_jtag_access.2329472466
Short name T406
Test name
Test status
Simulation time 2186813930 ps
CPU time 8.21 seconds
Started Jun 05 06:00:12 PM PDT 24
Finished Jun 05 06:00:21 PM PDT 24
Peak memory 209616 kb
Host smart-a49747f0-4f1d-4d9c-80d2-368bc2706678
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329472466 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_jtag_access.2329472466
Directory /workspace/43.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/43.lc_ctrl_prog_failure.1865622814
Short name T306
Test name
Test status
Simulation time 50364510 ps
CPU time 1.74 seconds
Started Jun 05 05:59:59 PM PDT 24
Finished Jun 05 06:00:01 PM PDT 24
Peak memory 218028 kb
Host smart-f5b8a27c-c08f-43de-9789-1890b1093e25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865622814 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_prog_failure.1865622814
Directory /workspace/43.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_mubi.381345350
Short name T727
Test name
Test status
Simulation time 834121073 ps
CPU time 13.36 seconds
Started Jun 05 06:00:12 PM PDT 24
Finished Jun 05 06:00:26 PM PDT 24
Peak memory 218920 kb
Host smart-9967f332-4b7e-4a00-8ab9-15f9801bde8e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381345350 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_mubi.381345350
Directory /workspace/43.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_digest.3092361892
Short name T560
Test name
Test status
Simulation time 247172175 ps
CPU time 7.29 seconds
Started Jun 05 06:00:17 PM PDT 24
Finished Jun 05 06:00:25 PM PDT 24
Peak memory 226084 kb
Host smart-d29bd171-d463-475f-88c9-ceaead4f0455
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092361892 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_d
igest.3092361892
Directory /workspace/43.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_mux.1804168946
Short name T282
Test name
Test status
Simulation time 415205564 ps
CPU time 10.91 seconds
Started Jun 05 06:00:15 PM PDT 24
Finished Jun 05 06:00:27 PM PDT 24
Peak memory 217976 kb
Host smart-0a656b76-bcd1-4da2-95bb-4e035af089f2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804168946 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_mux.
1804168946
Directory /workspace/43.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/43.lc_ctrl_security_escalation.313204308
Short name T44
Test name
Test status
Simulation time 1415225748 ps
CPU time 10.72 seconds
Started Jun 05 06:00:10 PM PDT 24
Finished Jun 05 06:00:22 PM PDT 24
Peak memory 218092 kb
Host smart-2a36d38d-5888-4c8b-b514-ac0e0df2fc9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=313204308 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_security_escalation.313204308
Directory /workspace/43.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/43.lc_ctrl_smoke.2871239013
Short name T325
Test name
Test status
Simulation time 23316485 ps
CPU time 0.99 seconds
Started Jun 05 06:00:15 PM PDT 24
Finished Jun 05 06:00:17 PM PDT 24
Peak memory 211968 kb
Host smart-8d2c6db4-e955-409a-a28a-9be8dcc3cbae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871239013 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_smoke.2871239013
Directory /workspace/43.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_failure.891617791
Short name T263
Test name
Test status
Simulation time 232181476 ps
CPU time 21.17 seconds
Started Jun 05 06:00:14 PM PDT 24
Finished Jun 05 06:00:36 PM PDT 24
Peak memory 246324 kb
Host smart-5a751e12-1644-4f4e-a15f-5b480cbe3f98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891617791 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_failure.891617791
Directory /workspace/43.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_post_trans.2929558426
Short name T200
Test name
Test status
Simulation time 72158399 ps
CPU time 7.51 seconds
Started Jun 05 06:00:06 PM PDT 24
Finished Jun 05 06:00:14 PM PDT 24
Peak memory 248504 kb
Host smart-6cc8af99-a844-4d90-9b40-6af2ab765292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929558426 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_post_trans.2929558426
Directory /workspace/43.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all.1112403393
Short name T454
Test name
Test status
Simulation time 6415620263 ps
CPU time 119.6 seconds
Started Jun 05 06:00:08 PM PDT 24
Finished Jun 05 06:02:08 PM PDT 24
Peak memory 268296 kb
Host smart-27ee637b-4e9b-4022-810e-ff7b3afcb569
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112403393 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.lc_ctrl_stress_all.1112403393
Directory /workspace/43.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.lc_ctrl_volatile_unlock_smoke.3652474360
Short name T378
Test name
Test status
Simulation time 14731508 ps
CPU time 0.87 seconds
Started Jun 05 06:00:06 PM PDT 24
Finished Jun 05 06:00:07 PM PDT 24
Peak memory 208736 kb
Host smart-627942e9-cfcd-491f-b1b5-7e820801d2c9
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652474360 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_c
trl_volatile_unlock_smoke.3652474360
Directory /workspace/43.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_alert_test.455432069
Short name T84
Test name
Test status
Simulation time 19937276 ps
CPU time 0.96 seconds
Started Jun 05 06:00:12 PM PDT 24
Finished Jun 05 06:00:14 PM PDT 24
Peak memory 209720 kb
Host smart-a596dba5-c5df-438e-a6dc-3c88800211b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455432069 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_alert_test.455432069
Directory /workspace/44.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.lc_ctrl_errors.1208266241
Short name T831
Test name
Test status
Simulation time 2275544153 ps
CPU time 11.21 seconds
Started Jun 05 06:00:18 PM PDT 24
Finished Jun 05 06:00:30 PM PDT 24
Peak memory 218092 kb
Host smart-2f563cd4-f481-4661-aa3c-ff1e1e297424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208266241 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_errors.1208266241
Directory /workspace/44.lc_ctrl_errors/latest

Test location /workspace/coverage/default/44.lc_ctrl_jtag_access.3675752111
Short name T22
Test name
Test status
Simulation time 131192967 ps
CPU time 2.35 seconds
Started Jun 05 06:00:18 PM PDT 24
Finished Jun 05 06:00:21 PM PDT 24
Peak memory 216920 kb
Host smart-2cb5bb64-4ae7-40c0-8645-832513ba3528
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675752111 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_jtag_access.3675752111
Directory /workspace/44.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/44.lc_ctrl_prog_failure.1069395749
Short name T498
Test name
Test status
Simulation time 94202674 ps
CPU time 3.38 seconds
Started Jun 05 06:00:10 PM PDT 24
Finished Jun 05 06:00:14 PM PDT 24
Peak memory 218096 kb
Host smart-4857db2b-dbaa-4c2b-b7c4-de0259dc36db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069395749 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_prog_failure.1069395749
Directory /workspace/44.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_mubi.2619747622
Short name T670
Test name
Test status
Simulation time 1360221951 ps
CPU time 11.19 seconds
Started Jun 05 06:00:19 PM PDT 24
Finished Jun 05 06:00:31 PM PDT 24
Peak memory 219012 kb
Host smart-4398fa79-a03d-481c-b267-90211dc4a4b7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619747622 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_mubi.2619747622
Directory /workspace/44.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_digest.934806823
Short name T715
Test name
Test status
Simulation time 306111972 ps
CPU time 8.5 seconds
Started Jun 05 06:00:29 PM PDT 24
Finished Jun 05 06:00:39 PM PDT 24
Peak memory 217968 kb
Host smart-8c4e31ec-910e-49e8-96b4-cab9ecf42f29
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934806823 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_di
gest.934806823
Directory /workspace/44.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/44.lc_ctrl_security_escalation.3982529449
Short name T631
Test name
Test status
Simulation time 758320776 ps
CPU time 9.29 seconds
Started Jun 05 06:00:13 PM PDT 24
Finished Jun 05 06:00:23 PM PDT 24
Peak memory 218096 kb
Host smart-682ce750-5d8c-480b-bf6a-803d2232c8e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982529449 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_security_escalation.3982529449
Directory /workspace/44.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/44.lc_ctrl_smoke.165997536
Short name T484
Test name
Test status
Simulation time 85681963 ps
CPU time 1.52 seconds
Started Jun 05 06:00:17 PM PDT 24
Finished Jun 05 06:00:19 PM PDT 24
Peak memory 213520 kb
Host smart-8abd8ab8-2157-4d67-93e7-d8c3e18cc65a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165997536 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_smoke.165997536
Directory /workspace/44.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_failure.4262214309
Short name T489
Test name
Test status
Simulation time 322717554 ps
CPU time 28.42 seconds
Started Jun 05 06:00:16 PM PDT 24
Finished Jun 05 06:00:46 PM PDT 24
Peak memory 251024 kb
Host smart-7a705787-e374-4b5b-812f-b2f2a4ffe2a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262214309 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_failure.4262214309
Directory /workspace/44.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_post_trans.377838789
Short name T214
Test name
Test status
Simulation time 84032899 ps
CPU time 7.29 seconds
Started Jun 05 06:00:23 PM PDT 24
Finished Jun 05 06:00:31 PM PDT 24
Peak memory 251024 kb
Host smart-e2e8ba28-95d3-49f0-a378-4231c95eaedd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377838789 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_post_trans.377838789
Directory /workspace/44.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/44.lc_ctrl_stress_all.4188737710
Short name T176
Test name
Test status
Simulation time 16284394415 ps
CPU time 254.84 seconds
Started Jun 05 06:00:28 PM PDT 24
Finished Jun 05 06:04:44 PM PDT 24
Peak memory 283184 kb
Host smart-ae41dd08-0a8a-48c4-b5d9-32fa7cd41f1f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188737710 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.lc_ctrl_stress_all.4188737710
Directory /workspace/44.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.lc_ctrl_stress_all_with_rand_reset.1432789615
Short name T795
Test name
Test status
Simulation time 49175689642 ps
CPU time 442.77 seconds
Started Jun 05 06:00:11 PM PDT 24
Finished Jun 05 06:07:34 PM PDT 24
Peak memory 371836 kb
Host smart-96b6ed09-7580-47cc-aaa8-ac1a2e6a39bd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1432789615 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_stress_all_with_rand_reset.1432789615
Directory /workspace/44.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.lc_ctrl_volatile_unlock_smoke.1121747626
Short name T653
Test name
Test status
Simulation time 37451037 ps
CPU time 0.78 seconds
Started Jun 05 06:00:14 PM PDT 24
Finished Jun 05 06:00:16 PM PDT 24
Peak memory 208388 kb
Host smart-380f59b8-d985-4bea-be91-9793bd3f01e1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121747626 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_c
trl_volatile_unlock_smoke.1121747626
Directory /workspace/44.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_alert_test.1511166189
Short name T712
Test name
Test status
Simulation time 48067774 ps
CPU time 0.91 seconds
Started Jun 05 06:00:22 PM PDT 24
Finished Jun 05 06:00:29 PM PDT 24
Peak memory 208544 kb
Host smart-d5588d86-d416-4b34-bc07-a3842716d5ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511166189 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_alert_test.1511166189
Directory /workspace/45.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.lc_ctrl_errors.1380841409
Short name T286
Test name
Test status
Simulation time 427979200 ps
CPU time 9.24 seconds
Started Jun 05 06:00:20 PM PDT 24
Finished Jun 05 06:00:30 PM PDT 24
Peak memory 217888 kb
Host smart-caee0b21-feb6-4e40-969b-9814d525fcc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380841409 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_errors.1380841409
Directory /workspace/45.lc_ctrl_errors/latest

Test location /workspace/coverage/default/45.lc_ctrl_jtag_access.3793357943
Short name T20
Test name
Test status
Simulation time 568632347 ps
CPU time 5.94 seconds
Started Jun 05 06:00:19 PM PDT 24
Finished Jun 05 06:00:25 PM PDT 24
Peak memory 209552 kb
Host smart-a96599c1-057e-4cb1-b4c8-82db6511f230
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793357943 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_jtag_access.3793357943
Directory /workspace/45.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/45.lc_ctrl_prog_failure.24905257
Short name T713
Test name
Test status
Simulation time 59861762 ps
CPU time 2.09 seconds
Started Jun 05 06:00:23 PM PDT 24
Finished Jun 05 06:00:26 PM PDT 24
Peak memory 217956 kb
Host smart-7b67cc64-613a-42a1-9635-77dc42ee3a81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24905257 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_prog_failure.24905257
Directory /workspace/45.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_mubi.712256426
Short name T520
Test name
Test status
Simulation time 1863388680 ps
CPU time 10.02 seconds
Started Jun 05 06:00:16 PM PDT 24
Finished Jun 05 06:00:27 PM PDT 24
Peak memory 225936 kb
Host smart-809ae9d1-ceca-4294-b7b9-68789ee479a3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712256426 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_mubi.712256426
Directory /workspace/45.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_digest.1121715518
Short name T256
Test name
Test status
Simulation time 264865714 ps
CPU time 8.97 seconds
Started Jun 05 06:00:19 PM PDT 24
Finished Jun 05 06:00:28 PM PDT 24
Peak memory 217992 kb
Host smart-dd23f7cb-6863-4241-b712-d651f5e63550
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121715518 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_d
igest.1121715518
Directory /workspace/45.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_mux.4128634993
Short name T729
Test name
Test status
Simulation time 1252895258 ps
CPU time 10.52 seconds
Started Jun 05 06:00:18 PM PDT 24
Finished Jun 05 06:00:29 PM PDT 24
Peak memory 218100 kb
Host smart-e5fc18ca-97ba-410c-9324-94473977e79e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128634993 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_mux.
4128634993
Directory /workspace/45.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/45.lc_ctrl_security_escalation.2577726339
Short name T799
Test name
Test status
Simulation time 1175086247 ps
CPU time 11.7 seconds
Started Jun 05 06:00:14 PM PDT 24
Finished Jun 05 06:00:27 PM PDT 24
Peak memory 218124 kb
Host smart-1bc5914b-7281-4ccc-af91-a5d258e05470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577726339 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_security_escalation.2577726339
Directory /workspace/45.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/45.lc_ctrl_smoke.1300176704
Short name T297
Test name
Test status
Simulation time 181114464 ps
CPU time 3.4 seconds
Started Jun 05 06:00:14 PM PDT 24
Finished Jun 05 06:00:18 PM PDT 24
Peak memory 214564 kb
Host smart-2645af30-da3f-42ae-a975-a1cd3ca2e130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1300176704 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_smoke.1300176704
Directory /workspace/45.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_failure.1504609749
Short name T240
Test name
Test status
Simulation time 1249349052 ps
CPU time 29.54 seconds
Started Jun 05 06:00:17 PM PDT 24
Finished Jun 05 06:00:48 PM PDT 24
Peak memory 251104 kb
Host smart-a5ce2fa4-1c17-49d6-b743-cfefeac1339b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504609749 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_failure.1504609749
Directory /workspace/45.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_post_trans.2519784083
Short name T458
Test name
Test status
Simulation time 274242425 ps
CPU time 8.49 seconds
Started Jun 05 06:00:17 PM PDT 24
Finished Jun 05 06:00:26 PM PDT 24
Peak memory 251032 kb
Host smart-ed17bf7f-ed14-486c-adb5-c4182df7aa4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519784083 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_post_trans.2519784083
Directory /workspace/45.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/45.lc_ctrl_stress_all.3266216762
Short name T53
Test name
Test status
Simulation time 35467220298 ps
CPU time 283.94 seconds
Started Jun 05 06:00:13 PM PDT 24
Finished Jun 05 06:04:57 PM PDT 24
Peak memory 372948 kb
Host smart-95318425-02d8-42eb-9640-f594b8a919f8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266216762 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.lc_ctrl_stress_all.3266216762
Directory /workspace/45.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.lc_ctrl_volatile_unlock_smoke.2516107423
Short name T700
Test name
Test status
Simulation time 151375429 ps
CPU time 0.83 seconds
Started Jun 05 06:00:22 PM PDT 24
Finished Jun 05 06:00:23 PM PDT 24
Peak memory 208324 kb
Host smart-f523da6d-4dab-4f3c-af16-e8561159a6d5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516107423 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_c
trl_volatile_unlock_smoke.2516107423
Directory /workspace/45.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_alert_test.1959083356
Short name T857
Test name
Test status
Simulation time 50212941 ps
CPU time 0.87 seconds
Started Jun 05 06:00:28 PM PDT 24
Finished Jun 05 06:00:30 PM PDT 24
Peak memory 209388 kb
Host smart-2c889407-2adb-426f-b61e-77cbf8349337
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959083356 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_alert_test.1959083356
Directory /workspace/46.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.lc_ctrl_errors.750118074
Short name T571
Test name
Test status
Simulation time 590860991 ps
CPU time 14.61 seconds
Started Jun 05 06:00:19 PM PDT 24
Finished Jun 05 06:00:35 PM PDT 24
Peak memory 218088 kb
Host smart-55adb21b-a532-488e-93a8-474b5c3a2013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750118074 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_errors.750118074
Directory /workspace/46.lc_ctrl_errors/latest

Test location /workspace/coverage/default/46.lc_ctrl_jtag_access.3516206115
Short name T758
Test name
Test status
Simulation time 31488192 ps
CPU time 1.57 seconds
Started Jun 05 06:00:25 PM PDT 24
Finished Jun 05 06:00:27 PM PDT 24
Peak memory 216984 kb
Host smart-d8b4c2bd-d9cd-467d-b727-63e811a36306
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516206115 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_jtag_access.3516206115
Directory /workspace/46.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/46.lc_ctrl_prog_failure.101224346
Short name T748
Test name
Test status
Simulation time 386805319 ps
CPU time 2.62 seconds
Started Jun 05 06:00:13 PM PDT 24
Finished Jun 05 06:00:16 PM PDT 24
Peak memory 218100 kb
Host smart-93d48907-0ff0-4586-b975-1ad021056515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101224346 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_prog_failure.101224346
Directory /workspace/46.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_mubi.3182243246
Short name T843
Test name
Test status
Simulation time 420463182 ps
CPU time 10.7 seconds
Started Jun 05 06:00:14 PM PDT 24
Finished Jun 05 06:00:25 PM PDT 24
Peak memory 218148 kb
Host smart-5d91cdba-d411-4409-afef-4c890e3d5a9b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182243246 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_mubi.3182243246
Directory /workspace/46.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_digest.80702816
Short name T649
Test name
Test status
Simulation time 531457586 ps
CPU time 12.43 seconds
Started Jun 05 06:00:15 PM PDT 24
Finished Jun 05 06:00:29 PM PDT 24
Peak memory 217908 kb
Host smart-03d6a700-b615-4877-987a-c4c5fa39f376
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80702816 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_dig
est_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_dig
est.80702816
Directory /workspace/46.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_mux.1401365955
Short name T442
Test name
Test status
Simulation time 388360079 ps
CPU time 12.65 seconds
Started Jun 05 06:00:27 PM PDT 24
Finished Jun 05 06:00:40 PM PDT 24
Peak memory 218112 kb
Host smart-3e8c306e-cf17-4321-95b7-704638eb18af
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401365955 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_mux.
1401365955
Directory /workspace/46.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/46.lc_ctrl_security_escalation.617357380
Short name T709
Test name
Test status
Simulation time 305251400 ps
CPU time 10.7 seconds
Started Jun 05 06:00:10 PM PDT 24
Finished Jun 05 06:00:22 PM PDT 24
Peak memory 218044 kb
Host smart-f6ccfb0c-1a53-41c4-bc83-a193cc9903b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617357380 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_security_escalation.617357380
Directory /workspace/46.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/46.lc_ctrl_smoke.1111438396
Short name T694
Test name
Test status
Simulation time 230404937 ps
CPU time 2.81 seconds
Started Jun 05 06:00:15 PM PDT 24
Finished Jun 05 06:00:18 PM PDT 24
Peak memory 217788 kb
Host smart-296e4230-5382-4109-b91e-9e2c9a58bffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111438396 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_smoke.1111438396
Directory /workspace/46.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_failure.4117645017
Short name T566
Test name
Test status
Simulation time 1026324825 ps
CPU time 30.44 seconds
Started Jun 05 06:00:14 PM PDT 24
Finished Jun 05 06:00:45 PM PDT 24
Peak memory 251020 kb
Host smart-f6c4ff98-ac93-4854-bcc3-3f765e01d862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117645017 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_failure.4117645017
Directory /workspace/46.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_post_trans.730464090
Short name T232
Test name
Test status
Simulation time 55278365 ps
CPU time 9.35 seconds
Started Jun 05 06:00:16 PM PDT 24
Finished Jun 05 06:00:27 PM PDT 24
Peak memory 250948 kb
Host smart-f1be647c-da63-45d8-b3f5-17f9b22d17bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730464090 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_post_trans.730464090
Directory /workspace/46.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all.1886328226
Short name T41
Test name
Test status
Simulation time 4674989086 ps
CPU time 120.31 seconds
Started Jun 05 06:00:13 PM PDT 24
Finished Jun 05 06:02:14 PM PDT 24
Peak memory 226180 kb
Host smart-45e7f188-8086-447f-b87a-0c372f1dd712
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886328226 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.lc_ctrl_stress_all.1886328226
Directory /workspace/46.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.lc_ctrl_volatile_unlock_smoke.402525762
Short name T231
Test name
Test status
Simulation time 36007366 ps
CPU time 0.86 seconds
Started Jun 05 06:00:24 PM PDT 24
Finished Jun 05 06:00:26 PM PDT 24
Peak memory 208624 kb
Host smart-de44be14-87fa-4661-8696-a0b3c3508435
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402525762 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ct
rl_volatile_unlock_smoke.402525762
Directory /workspace/46.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_alert_test.2540427327
Short name T285
Test name
Test status
Simulation time 21656406 ps
CPU time 0.84 seconds
Started Jun 05 06:00:36 PM PDT 24
Finished Jun 05 06:00:38 PM PDT 24
Peak memory 208496 kb
Host smart-7c50ab0a-848a-4f98-abd1-e4931924abe6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540427327 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_alert_test.2540427327
Directory /workspace/47.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.lc_ctrl_errors.3829712010
Short name T766
Test name
Test status
Simulation time 350317823 ps
CPU time 11.3 seconds
Started Jun 05 06:00:31 PM PDT 24
Finished Jun 05 06:00:43 PM PDT 24
Peak memory 218024 kb
Host smart-7d2a1cf9-b39a-444d-876b-71167c29d3b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829712010 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_errors.3829712010
Directory /workspace/47.lc_ctrl_errors/latest

Test location /workspace/coverage/default/47.lc_ctrl_jtag_access.1123016216
Short name T331
Test name
Test status
Simulation time 624497245 ps
CPU time 8.73 seconds
Started Jun 05 06:00:20 PM PDT 24
Finished Jun 05 06:00:29 PM PDT 24
Peak memory 209552 kb
Host smart-d192bf81-934e-469c-8ed8-31f04a7f9f0b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123016216 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_jtag_access.1123016216
Directory /workspace/47.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/47.lc_ctrl_prog_failure.401463281
Short name T107
Test name
Test status
Simulation time 23129856 ps
CPU time 1.92 seconds
Started Jun 05 06:00:12 PM PDT 24
Finished Jun 05 06:00:14 PM PDT 24
Peak memory 217984 kb
Host smart-005a5381-2c6f-41b0-909e-ef945690e1d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401463281 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_prog_failure.401463281
Directory /workspace/47.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_mubi.2049521418
Short name T380
Test name
Test status
Simulation time 420546451 ps
CPU time 12.51 seconds
Started Jun 05 06:00:26 PM PDT 24
Finished Jun 05 06:00:39 PM PDT 24
Peak memory 226132 kb
Host smart-e330eb71-7af0-4afa-9e18-b90655723cd8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049521418 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_mubi.2049521418
Directory /workspace/47.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_digest.2457501922
Short name T608
Test name
Test status
Simulation time 1246558799 ps
CPU time 13.1 seconds
Started Jun 05 06:00:36 PM PDT 24
Finished Jun 05 06:00:49 PM PDT 24
Peak memory 217980 kb
Host smart-187a1413-4bc6-40e9-8644-c1cf1418293a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457501922 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_d
igest.2457501922
Directory /workspace/47.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_mux.3626256566
Short name T725
Test name
Test status
Simulation time 254805099 ps
CPU time 7.27 seconds
Started Jun 05 06:00:22 PM PDT 24
Finished Jun 05 06:00:30 PM PDT 24
Peak memory 218044 kb
Host smart-74fdc3eb-8ad4-4f1d-911e-dc6b56146ba2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626256566 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_mux.
3626256566
Directory /workspace/47.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/47.lc_ctrl_security_escalation.1463293883
Short name T4
Test name
Test status
Simulation time 1221903537 ps
CPU time 10.86 seconds
Started Jun 05 06:00:23 PM PDT 24
Finished Jun 05 06:00:34 PM PDT 24
Peak memory 218088 kb
Host smart-95c2a38b-9152-405d-871d-ec8e9d5abc98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463293883 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_security_escalation.1463293883
Directory /workspace/47.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/47.lc_ctrl_smoke.2828336735
Short name T537
Test name
Test status
Simulation time 59787840 ps
CPU time 1.16 seconds
Started Jun 05 06:00:15 PM PDT 24
Finished Jun 05 06:00:17 PM PDT 24
Peak memory 217636 kb
Host smart-5b7cd351-eacd-496b-820f-1239fbc0bbbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828336735 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_smoke.2828336735
Directory /workspace/47.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_failure.1482055552
Short name T218
Test name
Test status
Simulation time 398120116 ps
CPU time 23.23 seconds
Started Jun 05 06:00:17 PM PDT 24
Finished Jun 05 06:00:41 PM PDT 24
Peak memory 251020 kb
Host smart-05696e46-546d-4c67-ae46-3ed67665c5c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482055552 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_failure.1482055552
Directory /workspace/47.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_post_trans.1330884939
Short name T652
Test name
Test status
Simulation time 67420432 ps
CPU time 8.45 seconds
Started Jun 05 06:00:29 PM PDT 24
Finished Jun 05 06:00:38 PM PDT 24
Peak memory 251036 kb
Host smart-6eb1c3bf-0fb7-4042-baf5-abcd8d58811e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330884939 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_post_trans.1330884939
Directory /workspace/47.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/47.lc_ctrl_stress_all.2659809250
Short name T820
Test name
Test status
Simulation time 58874758472 ps
CPU time 229.76 seconds
Started Jun 05 06:00:22 PM PDT 24
Finished Jun 05 06:04:13 PM PDT 24
Peak memory 281424 kb
Host smart-b9a29221-ea23-4b6c-ac85-def41c5a63e6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659809250 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.lc_ctrl_stress_all.2659809250
Directory /workspace/47.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.lc_ctrl_volatile_unlock_smoke.4180186566
Short name T744
Test name
Test status
Simulation time 53846222 ps
CPU time 1.08 seconds
Started Jun 05 06:00:18 PM PDT 24
Finished Jun 05 06:00:20 PM PDT 24
Peak memory 212612 kb
Host smart-a0fbb5aa-d95c-4c58-a696-01cbef90975f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180186566 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_c
trl_volatile_unlock_smoke.4180186566
Directory /workspace/47.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_alert_test.2222294353
Short name T525
Test name
Test status
Simulation time 346556234 ps
CPU time 1.01 seconds
Started Jun 05 06:00:21 PM PDT 24
Finished Jun 05 06:00:23 PM PDT 24
Peak memory 209532 kb
Host smart-46628d75-57d8-45b6-b8c1-34daf59d89c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222294353 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_alert_test.2222294353
Directory /workspace/48.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.lc_ctrl_errors.3101512068
Short name T822
Test name
Test status
Simulation time 1441278945 ps
CPU time 14.81 seconds
Started Jun 05 06:00:33 PM PDT 24
Finished Jun 05 06:00:49 PM PDT 24
Peak memory 218052 kb
Host smart-3bb13877-c841-4d94-baa8-1160dd5fae7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101512068 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_errors.3101512068
Directory /workspace/48.lc_ctrl_errors/latest

Test location /workspace/coverage/default/48.lc_ctrl_jtag_access.845205827
Short name T412
Test name
Test status
Simulation time 781003890 ps
CPU time 16.19 seconds
Started Jun 05 06:00:20 PM PDT 24
Finished Jun 05 06:00:37 PM PDT 24
Peak memory 209592 kb
Host smart-73fae173-3cd2-400f-a01a-8ba0c830cb6e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845205827 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_jtag_access.845205827
Directory /workspace/48.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/48.lc_ctrl_prog_failure.1894894399
Short name T461
Test name
Test status
Simulation time 63337354 ps
CPU time 3.13 seconds
Started Jun 05 06:00:30 PM PDT 24
Finished Jun 05 06:00:34 PM PDT 24
Peak memory 218032 kb
Host smart-3424b4b0-d39f-474a-9eea-b72fc985dbbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894894399 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_prog_failure.1894894399
Directory /workspace/48.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_mubi.3337574114
Short name T586
Test name
Test status
Simulation time 843323381 ps
CPU time 13.14 seconds
Started Jun 05 06:00:25 PM PDT 24
Finished Jun 05 06:00:38 PM PDT 24
Peak memory 219000 kb
Host smart-13141ed1-5066-4034-b613-1d56a1fcd288
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337574114 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_mubi.3337574114
Directory /workspace/48.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_digest.2661223930
Short name T10
Test name
Test status
Simulation time 741328786 ps
CPU time 7.77 seconds
Started Jun 05 06:00:30 PM PDT 24
Finished Jun 05 06:00:39 PM PDT 24
Peak memory 226064 kb
Host smart-b7fed6ce-398b-4157-bf56-fd7c89d7246d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661223930 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_d
igest.2661223930
Directory /workspace/48.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_mux.835397654
Short name T772
Test name
Test status
Simulation time 1148545490 ps
CPU time 9.88 seconds
Started Jun 05 06:00:43 PM PDT 24
Finished Jun 05 06:00:54 PM PDT 24
Peak memory 218072 kb
Host smart-eceb81a3-f45a-466e-bb0c-6596085430f2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835397654 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_mux.835397654
Directory /workspace/48.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/48.lc_ctrl_security_escalation.3993259863
Short name T573
Test name
Test status
Simulation time 4862362848 ps
CPU time 14.59 seconds
Started Jun 05 06:00:22 PM PDT 24
Finished Jun 05 06:00:37 PM PDT 24
Peak memory 225784 kb
Host smart-1fbf0970-0c56-4301-8e0d-117f151e7961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993259863 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_security_escalation.3993259863
Directory /workspace/48.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/48.lc_ctrl_smoke.3183349164
Short name T522
Test name
Test status
Simulation time 179285447 ps
CPU time 2.97 seconds
Started Jun 05 06:00:25 PM PDT 24
Finished Jun 05 06:00:29 PM PDT 24
Peak memory 217768 kb
Host smart-ac921ca3-ad6f-4dee-8fc4-5b1270eeb678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183349164 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_smoke.3183349164
Directory /workspace/48.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_failure.2186372054
Short name T616
Test name
Test status
Simulation time 1399757095 ps
CPU time 24.11 seconds
Started Jun 05 06:00:22 PM PDT 24
Finished Jun 05 06:00:46 PM PDT 24
Peak memory 251068 kb
Host smart-7a16d1cf-bde1-440e-a0e4-c3c3617c697a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186372054 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_failure.2186372054
Directory /workspace/48.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_post_trans.4170647078
Short name T264
Test name
Test status
Simulation time 212992580 ps
CPU time 6.82 seconds
Started Jun 05 06:00:32 PM PDT 24
Finished Jun 05 06:00:40 PM PDT 24
Peak memory 247628 kb
Host smart-f61775b6-1b9b-4456-b7bd-79bab3152dca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170647078 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_post_trans.4170647078
Directory /workspace/48.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all.3408043844
Short name T73
Test name
Test status
Simulation time 30290816973 ps
CPU time 206.84 seconds
Started Jun 05 06:00:26 PM PDT 24
Finished Jun 05 06:03:54 PM PDT 24
Peak memory 296280 kb
Host smart-68f0af92-0816-47c3-828b-fbb6849d8b03
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408043844 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.lc_ctrl_stress_all.3408043844
Directory /workspace/48.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all_with_rand_reset.2708807660
Short name T170
Test name
Test status
Simulation time 14666121866 ps
CPU time 620.46 seconds
Started Jun 05 06:00:21 PM PDT 24
Finished Jun 05 06:10:42 PM PDT 24
Peak memory 422052 kb
Host smart-decd2ee7-658c-4f84-be82-660472eebd12
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2708807660 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_stress_all_with_rand_reset.2708807660
Directory /workspace/48.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.lc_ctrl_volatile_unlock_smoke.120741436
Short name T227
Test name
Test status
Simulation time 18979832 ps
CPU time 1.49 seconds
Started Jun 05 06:00:25 PM PDT 24
Finished Jun 05 06:00:27 PM PDT 24
Peak memory 212768 kb
Host smart-873aa9bd-5681-41ad-a3d4-93ab1c38c2a1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120741436 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ct
rl_volatile_unlock_smoke.120741436
Directory /workspace/48.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_alert_test.1387993116
Short name T65
Test name
Test status
Simulation time 51248015 ps
CPU time 1.08 seconds
Started Jun 05 06:00:23 PM PDT 24
Finished Jun 05 06:00:25 PM PDT 24
Peak memory 208740 kb
Host smart-bf7e1e34-ac22-4ece-bef4-d12bbb8c0b4e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387993116 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_alert_test.1387993116
Directory /workspace/49.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.lc_ctrl_errors.2304363053
Short name T369
Test name
Test status
Simulation time 388201367 ps
CPU time 12.91 seconds
Started Jun 05 06:00:22 PM PDT 24
Finished Jun 05 06:00:35 PM PDT 24
Peak memory 218028 kb
Host smart-3050311e-43cf-4525-9f5a-069c31d8792c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304363053 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_errors.2304363053
Directory /workspace/49.lc_ctrl_errors/latest

Test location /workspace/coverage/default/49.lc_ctrl_jtag_access.884783235
Short name T177
Test name
Test status
Simulation time 4334427681 ps
CPU time 10.75 seconds
Started Jun 05 06:00:28 PM PDT 24
Finished Jun 05 06:00:40 PM PDT 24
Peak memory 217792 kb
Host smart-94051be3-d068-4f3d-848e-3e9625e559a2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884783235 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_jtag_access.884783235
Directory /workspace/49.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/49.lc_ctrl_prog_failure.796802624
Short name T698
Test name
Test status
Simulation time 23753582 ps
CPU time 1.62 seconds
Started Jun 05 06:00:30 PM PDT 24
Finished Jun 05 06:00:33 PM PDT 24
Peak memory 218108 kb
Host smart-5b9a99a6-43d0-40bd-b04c-30b3ff0dff18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796802624 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_prog_failure.796802624
Directory /workspace/49.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_mubi.2635214106
Short name T344
Test name
Test status
Simulation time 524993070 ps
CPU time 13.53 seconds
Started Jun 05 06:00:28 PM PDT 24
Finished Jun 05 06:00:43 PM PDT 24
Peak memory 218124 kb
Host smart-fc7d6540-f564-4678-a9b9-db5037f8746a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635214106 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_mubi.2635214106
Directory /workspace/49.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_digest.486726445
Short name T464
Test name
Test status
Simulation time 369893757 ps
CPU time 11.23 seconds
Started Jun 05 06:00:26 PM PDT 24
Finished Jun 05 06:00:38 PM PDT 24
Peak memory 226072 kb
Host smart-a13e2572-5668-4622-a649-dce5e8a375ad
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486726445 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_di
gest.486726445
Directory /workspace/49.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_mux.3003282505
Short name T338
Test name
Test status
Simulation time 218308567 ps
CPU time 8.73 seconds
Started Jun 05 06:00:28 PM PDT 24
Finished Jun 05 06:00:38 PM PDT 24
Peak memory 218044 kb
Host smart-8b01523a-bb92-4faa-b935-5ab351c88716
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003282505 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_mux.
3003282505
Directory /workspace/49.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/49.lc_ctrl_security_escalation.3295114805
Short name T622
Test name
Test status
Simulation time 1046623332 ps
CPU time 6.66 seconds
Started Jun 05 06:00:26 PM PDT 24
Finished Jun 05 06:00:34 PM PDT 24
Peak memory 218140 kb
Host smart-b5b0c831-561c-4667-9564-48b323655627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295114805 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_security_escalation.3295114805
Directory /workspace/49.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/49.lc_ctrl_smoke.4213591369
Short name T623
Test name
Test status
Simulation time 460359894 ps
CPU time 3.31 seconds
Started Jun 05 06:00:32 PM PDT 24
Finished Jun 05 06:00:37 PM PDT 24
Peak memory 217732 kb
Host smart-48476d54-04b3-403e-a184-19d697426402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213591369 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_smoke.4213591369
Directory /workspace/49.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_failure.4085816100
Short name T722
Test name
Test status
Simulation time 521724954 ps
CPU time 26.07 seconds
Started Jun 05 06:00:22 PM PDT 24
Finished Jun 05 06:00:49 PM PDT 24
Peak memory 251096 kb
Host smart-ca4de6f6-fe1a-44c7-ba31-2e57d893cdde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085816100 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_failure.4085816100
Directory /workspace/49.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_post_trans.42779373
Short name T508
Test name
Test status
Simulation time 147487376 ps
CPU time 9.47 seconds
Started Jun 05 06:00:32 PM PDT 24
Finished Jun 05 06:00:42 PM PDT 24
Peak memory 251092 kb
Host smart-4fc45f51-35bf-4aa4-b6c6-83c49454dc95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42779373 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_post_trans.42779373
Directory /workspace/49.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/49.lc_ctrl_stress_all.1350005484
Short name T60
Test name
Test status
Simulation time 971981363 ps
CPU time 20.57 seconds
Started Jun 05 06:00:26 PM PDT 24
Finished Jun 05 06:00:47 PM PDT 24
Peak memory 226116 kb
Host smart-0111a181-b185-4a70-b766-5eacdf38d1b0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350005484 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.lc_ctrl_stress_all.1350005484
Directory /workspace/49.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.lc_ctrl_volatile_unlock_smoke.2870449533
Short name T643
Test name
Test status
Simulation time 19267014 ps
CPU time 0.94 seconds
Started Jun 05 06:00:20 PM PDT 24
Finished Jun 05 06:00:21 PM PDT 24
Peak memory 211588 kb
Host smart-5ea6f49a-c194-428e-b059-5f22db2bd830
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870449533 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_c
trl_volatile_unlock_smoke.2870449533
Directory /workspace/49.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_alert_test.485469971
Short name T721
Test name
Test status
Simulation time 51934187 ps
CPU time 1 seconds
Started Jun 05 05:58:52 PM PDT 24
Finished Jun 05 05:58:54 PM PDT 24
Peak memory 209540 kb
Host smart-f4f66783-b713-41f9-82d4-6fe7cc6f321a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485469971 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_alert_test.485469971
Directory /workspace/5.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.lc_ctrl_claim_transition_if.1793141017
Short name T195
Test name
Test status
Simulation time 10560252 ps
CPU time 0.81 seconds
Started Jun 05 05:58:52 PM PDT 24
Finished Jun 05 05:58:54 PM PDT 24
Peak memory 208784 kb
Host smart-7dba02cf-a658-4d93-b4d1-9a102e732995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793141017 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_claim_transition_if.1793141017
Directory /workspace/5.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/5.lc_ctrl_errors.3783601893
Short name T737
Test name
Test status
Simulation time 379340604 ps
CPU time 12.6 seconds
Started Jun 05 05:58:39 PM PDT 24
Finished Jun 05 05:58:53 PM PDT 24
Peak memory 217992 kb
Host smart-7a3d934f-1152-4609-aeae-0807d3724618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783601893 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_errors.3783601893
Directory /workspace/5.lc_ctrl_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_access.2105178711
Short name T25
Test name
Test status
Simulation time 2783845867 ps
CPU time 7.29 seconds
Started Jun 05 05:58:40 PM PDT 24
Finished Jun 05 05:58:48 PM PDT 24
Peak memory 209692 kb
Host smart-66e4e846-896f-490b-94fa-0574f0c9ed2b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105178711 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_access.2105178711
Directory /workspace/5.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_errors.615059841
Short name T305
Test name
Test status
Simulation time 7539422555 ps
CPU time 50.64 seconds
Started Jun 05 05:58:49 PM PDT 24
Finished Jun 05 05:59:42 PM PDT 24
Peak memory 218032 kb
Host smart-d8e3246d-f4e1-48b0-8a22-50ee2a47c2b5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615059841 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_err
ors.615059841
Directory /workspace/5.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_priority.2108056268
Short name T784
Test name
Test status
Simulation time 639279260 ps
CPU time 2.46 seconds
Started Jun 05 05:58:48 PM PDT 24
Finished Jun 05 05:58:53 PM PDT 24
Peak memory 217108 kb
Host smart-d6a98a34-4423-43cc-9c0f-c5475725859c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108056268 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_priority.2
108056268
Directory /workspace/5.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_prog_failure.25822475
Short name T760
Test name
Test status
Simulation time 1756943014 ps
CPU time 12.49 seconds
Started Jun 05 05:58:45 PM PDT 24
Finished Jun 05 05:59:00 PM PDT 24
Peak memory 218000 kb
Host smart-e29a4839-ed3e-4f35-866f-0d86aed65f66
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25822475 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_p
rog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_p
rog_failure.25822475
Directory /workspace/5.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_regwen_during_op.674153652
Short name T819
Test name
Test status
Simulation time 785736165 ps
CPU time 23.24 seconds
Started Jun 05 05:58:40 PM PDT 24
Finished Jun 05 05:59:04 PM PDT 24
Peak memory 217720 kb
Host smart-eadffac7-f2e6-495c-9457-da2649174d68
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674153652 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_j
tag_regwen_during_op.674153652
Directory /workspace/5.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_smoke.13159135
Short name T18
Test name
Test status
Simulation time 56446992 ps
CPU time 2.22 seconds
Started Jun 05 05:58:40 PM PDT 24
Finished Jun 05 05:58:44 PM PDT 24
Peak memory 217724 kb
Host smart-bff7d124-035e-42fe-8df9-df3e8853185f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13159135 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_smoke.13159135
Directory /workspace/5.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_failure.3296246970
Short name T600
Test name
Test status
Simulation time 11383449892 ps
CPU time 82.13 seconds
Started Jun 05 05:58:47 PM PDT 24
Finished Jun 05 06:00:12 PM PDT 24
Peak memory 277324 kb
Host smart-5fe2d195-ef24-4486-bd9a-37c325108753
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296246970 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jta
g_state_failure.3296246970
Directory /workspace/5.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_post_trans.1411819113
Short name T746
Test name
Test status
Simulation time 395913352 ps
CPU time 16.24 seconds
Started Jun 05 05:58:35 PM PDT 24
Finished Jun 05 05:58:52 PM PDT 24
Peak memory 245768 kb
Host smart-fef93669-2d6f-41dd-be13-cbf823106f1e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411819113 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_state_post_trans.1411819113
Directory /workspace/5.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_prog_failure.1129014163
Short name T339
Test name
Test status
Simulation time 40195223 ps
CPU time 2.49 seconds
Started Jun 05 05:58:40 PM PDT 24
Finished Jun 05 05:58:44 PM PDT 24
Peak memory 218076 kb
Host smart-0f3b8f27-cba6-4361-8fc1-0c5c05107420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129014163 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_prog_failure.1129014163
Directory /workspace/5.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_regwen_during_op.3570096146
Short name T191
Test name
Test status
Simulation time 309322286 ps
CPU time 11.17 seconds
Started Jun 05 05:58:47 PM PDT 24
Finished Jun 05 05:59:01 PM PDT 24
Peak memory 217748 kb
Host smart-53c699de-92c6-4eb8-a632-9f70722ba1f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570096146 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_regwen_during_op.3570096146
Directory /workspace/5.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_mubi.1998721512
Short name T597
Test name
Test status
Simulation time 283969076 ps
CPU time 10.31 seconds
Started Jun 05 05:58:42 PM PDT 24
Finished Jun 05 05:58:53 PM PDT 24
Peak memory 225476 kb
Host smart-f13b4bf0-112d-4605-8331-7d3793e02f4d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998721512 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_mubi.1998721512
Directory /workspace/5.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_digest.2573155724
Short name T213
Test name
Test status
Simulation time 460096966 ps
CPU time 8.42 seconds
Started Jun 05 05:58:46 PM PDT 24
Finished Jun 05 05:58:56 PM PDT 24
Peak memory 217964 kb
Host smart-d39fe630-f69a-4771-9e85-2646bdfa0d26
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573155724 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_di
gest.2573155724
Directory /workspace/5.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_mux.1120269954
Short name T51
Test name
Test status
Simulation time 307459644 ps
CPU time 7.96 seconds
Started Jun 05 05:59:00 PM PDT 24
Finished Jun 05 05:59:08 PM PDT 24
Peak memory 218052 kb
Host smart-691ecb29-1840-4e0b-a9c1-3be8dcaa2aae
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120269954 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_mux.1
120269954
Directory /workspace/5.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/5.lc_ctrl_security_escalation.2098575484
Short name T864
Test name
Test status
Simulation time 478975564 ps
CPU time 10.29 seconds
Started Jun 05 05:58:34 PM PDT 24
Finished Jun 05 05:58:45 PM PDT 24
Peak memory 218196 kb
Host smart-3c7f1a7c-d677-4cce-aa23-5f8db2bcc83a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098575484 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_security_escalation.2098575484
Directory /workspace/5.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/5.lc_ctrl_smoke.3090695882
Short name T603
Test name
Test status
Simulation time 705152576 ps
CPU time 11.42 seconds
Started Jun 05 05:58:45 PM PDT 24
Finished Jun 05 05:58:59 PM PDT 24
Peak memory 217856 kb
Host smart-0fc27c9d-da02-421b-ba59-319b990be372
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090695882 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_smoke.3090695882
Directory /workspace/5.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_failure.3301596293
Short name T480
Test name
Test status
Simulation time 1647095398 ps
CPU time 30.45 seconds
Started Jun 05 05:58:44 PM PDT 24
Finished Jun 05 05:59:17 PM PDT 24
Peak memory 251048 kb
Host smart-08fc7559-88f8-4fa0-8485-8a30bb2699a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301596293 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_failure.3301596293
Directory /workspace/5.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_post_trans.2493314252
Short name T806
Test name
Test status
Simulation time 117595851 ps
CPU time 3.22 seconds
Started Jun 05 05:58:44 PM PDT 24
Finished Jun 05 05:58:50 PM PDT 24
Peak memory 218100 kb
Host smart-40b2d7f7-a022-45b8-8180-36d0a3403c76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493314252 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_post_trans.2493314252
Directory /workspace/5.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_stress_all.436098940
Short name T509
Test name
Test status
Simulation time 8234636806 ps
CPU time 318.47 seconds
Started Jun 05 05:59:15 PM PDT 24
Finished Jun 05 06:04:34 PM PDT 24
Peak memory 268884 kb
Host smart-7d69b8bd-945e-4bed-bf96-e3fd52b5dd55
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436098940 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.lc_ctrl_stress_all.436098940
Directory /workspace/5.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.lc_ctrl_volatile_unlock_smoke.3412866075
Short name T30
Test name
Test status
Simulation time 11728681 ps
CPU time 0.92 seconds
Started Jun 05 05:58:41 PM PDT 24
Finished Jun 05 05:58:43 PM PDT 24
Peak memory 208828 kb
Host smart-94bb6cd6-ce01-47c7-ae62-6da62956640b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412866075 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ct
rl_volatile_unlock_smoke.3412866075
Directory /workspace/5.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_alert_test.2254953627
Short name T565
Test name
Test status
Simulation time 24001659 ps
CPU time 1.22 seconds
Started Jun 05 05:58:39 PM PDT 24
Finished Jun 05 05:58:42 PM PDT 24
Peak memory 208764 kb
Host smart-4fd05c07-249d-4c7b-baa2-0361cb878913
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254953627 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_alert_test.2254953627
Directory /workspace/6.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.lc_ctrl_claim_transition_if.3944735510
Short name T815
Test name
Test status
Simulation time 20643252 ps
CPU time 0.91 seconds
Started Jun 05 05:58:37 PM PDT 24
Finished Jun 05 05:58:45 PM PDT 24
Peak memory 208696 kb
Host smart-e2c5fcab-d7c4-4576-9a44-5fa1590e940c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944735510 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_claim_transition_if.3944735510
Directory /workspace/6.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/6.lc_ctrl_errors.500004213
Short name T613
Test name
Test status
Simulation time 670785625 ps
CPU time 19.71 seconds
Started Jun 05 05:58:54 PM PDT 24
Finished Jun 05 05:59:15 PM PDT 24
Peak memory 218016 kb
Host smart-63782be8-c40a-4f80-999f-b958f25c10cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500004213 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_errors.500004213
Directory /workspace/6.lc_ctrl_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_access.2759868914
Short name T768
Test name
Test status
Simulation time 481905718 ps
CPU time 12.96 seconds
Started Jun 05 05:58:45 PM PDT 24
Finished Jun 05 05:59:01 PM PDT 24
Peak memory 209584 kb
Host smart-56eea548-f25c-4c9a-bb60-9375355a06c0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759868914 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_access.2759868914
Directory /workspace/6.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_errors.1365448448
Short name T343
Test name
Test status
Simulation time 2893632192 ps
CPU time 42.3 seconds
Started Jun 05 05:58:48 PM PDT 24
Finished Jun 05 05:59:32 PM PDT 24
Peak memory 218140 kb
Host smart-d09e2fd9-6e4d-4b16-b84e-b8d20411f7dc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365448448 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_er
rors.1365448448
Directory /workspace/6.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_priority.1742885048
Short name T614
Test name
Test status
Simulation time 5944859246 ps
CPU time 11.32 seconds
Started Jun 05 05:58:46 PM PDT 24
Finished Jun 05 05:59:00 PM PDT 24
Peak memory 217868 kb
Host smart-b1ef0010-cba1-4ede-aab8-5c127c9fd81f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742885048 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_priority.1
742885048
Directory /workspace/6.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_prog_failure.1713620067
Short name T617
Test name
Test status
Simulation time 2359405020 ps
CPU time 7.33 seconds
Started Jun 05 05:58:49 PM PDT 24
Finished Jun 05 05:58:59 PM PDT 24
Peak memory 218052 kb
Host smart-1103ec44-d59b-404a-a3ae-5f14ba2b4237
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713620067 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag
_prog_failure.1713620067
Directory /workspace/6.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_regwen_during_op.1146783847
Short name T166
Test name
Test status
Simulation time 3663824070 ps
CPU time 23.86 seconds
Started Jun 05 05:58:43 PM PDT 24
Finished Jun 05 05:59:10 PM PDT 24
Peak memory 217736 kb
Host smart-028ea40f-aa90-4994-93f0-a4e7ffcbfa77
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146783847 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_regwen_during_op.1146783847
Directory /workspace/6.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_smoke.869972331
Short name T530
Test name
Test status
Simulation time 2143697792 ps
CPU time 6.74 seconds
Started Jun 05 05:58:41 PM PDT 24
Finished Jun 05 05:58:49 PM PDT 24
Peak memory 217660 kb
Host smart-985c942c-0a50-4157-9fa6-750a12cc7b53
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869972331 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_smoke.869972331
Directory /workspace/6.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_failure.1823025011
Short name T281
Test name
Test status
Simulation time 2414866303 ps
CPU time 85.56 seconds
Started Jun 05 05:59:01 PM PDT 24
Finished Jun 05 06:00:27 PM PDT 24
Peak memory 276488 kb
Host smart-20c11b85-a9a0-4a7f-ab06-e6ddfaad6d85
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823025011 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jta
g_state_failure.1823025011
Directory /workspace/6.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_post_trans.2135717841
Short name T445
Test name
Test status
Simulation time 1494903914 ps
CPU time 16.88 seconds
Started Jun 05 05:58:41 PM PDT 24
Finished Jun 05 05:59:00 PM PDT 24
Peak memory 250924 kb
Host smart-5a6871e6-1808-4dcb-8605-5988b515d9d7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135717841 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_state_post_trans.2135717841
Directory /workspace/6.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_prog_failure.319352963
Short name T229
Test name
Test status
Simulation time 49290476 ps
CPU time 2.86 seconds
Started Jun 05 05:58:36 PM PDT 24
Finished Jun 05 05:58:40 PM PDT 24
Peak memory 218040 kb
Host smart-ccbe3cc2-3540-4b05-a115-1aa0eb953b0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319352963 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_prog_failure.319352963
Directory /workspace/6.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_regwen_during_op.2831689591
Short name T635
Test name
Test status
Simulation time 1717446815 ps
CPU time 12.26 seconds
Started Jun 05 05:58:36 PM PDT 24
Finished Jun 05 05:58:49 PM PDT 24
Peak memory 217748 kb
Host smart-5fec729e-8205-470f-a7d6-37a78eeac60d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831689591 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_regwen_during_op.2831689591
Directory /workspace/6.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_mubi.1277983823
Short name T275
Test name
Test status
Simulation time 276902847 ps
CPU time 11.61 seconds
Started Jun 05 05:58:45 PM PDT 24
Finished Jun 05 05:58:59 PM PDT 24
Peak memory 226160 kb
Host smart-0706cc83-8b7a-4cbd-943e-fd4b0b63b828
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277983823 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_mubi.1277983823
Directory /workspace/6.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_digest.3500531088
Short name T249
Test name
Test status
Simulation time 513546339 ps
CPU time 17.38 seconds
Started Jun 05 05:58:40 PM PDT 24
Finished Jun 05 05:58:59 PM PDT 24
Peak memory 226052 kb
Host smart-9540c4d8-6640-4604-a0ff-c2cd8866d826
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500531088 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_di
gest.3500531088
Directory /workspace/6.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_mux.2383871155
Short name T629
Test name
Test status
Simulation time 1035657403 ps
CPU time 10.85 seconds
Started Jun 05 05:58:34 PM PDT 24
Finished Jun 05 05:58:45 PM PDT 24
Peak memory 218204 kb
Host smart-c9588d70-e9d1-4a7f-bf94-c45d3ddde11f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383871155 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_mux.2
383871155
Directory /workspace/6.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/6.lc_ctrl_security_escalation.2249282672
Short name T802
Test name
Test status
Simulation time 1364817835 ps
CPU time 8.4 seconds
Started Jun 05 05:58:45 PM PDT 24
Finished Jun 05 05:58:56 PM PDT 24
Peak memory 218132 kb
Host smart-9fecc83c-fa42-4693-ac03-976c982c9d40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249282672 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_security_escalation.2249282672
Directory /workspace/6.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/6.lc_ctrl_smoke.4194377128
Short name T732
Test name
Test status
Simulation time 33996847 ps
CPU time 1.39 seconds
Started Jun 05 05:59:02 PM PDT 24
Finished Jun 05 05:59:04 PM PDT 24
Peak memory 217744 kb
Host smart-aec1bbc0-8eb7-43f4-82a9-613298ed7272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194377128 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_smoke.4194377128
Directory /workspace/6.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_failure.2965732564
Short name T241
Test name
Test status
Simulation time 1090302368 ps
CPU time 32.31 seconds
Started Jun 05 05:58:49 PM PDT 24
Finished Jun 05 05:59:24 PM PDT 24
Peak memory 250996 kb
Host smart-d1bb5e72-6651-4bfc-bcb9-b0cd237b93d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965732564 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_failure.2965732564
Directory /workspace/6.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_post_trans.2276442107
Short name T460
Test name
Test status
Simulation time 57353950 ps
CPU time 9.91 seconds
Started Jun 05 05:58:45 PM PDT 24
Finished Jun 05 05:58:57 PM PDT 24
Peak memory 251056 kb
Host smart-8a2f2e21-37e1-4563-94da-049c335f80b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276442107 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_post_trans.2276442107
Directory /workspace/6.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all.3933844140
Short name T844
Test name
Test status
Simulation time 11892697218 ps
CPU time 60.88 seconds
Started Jun 05 05:58:46 PM PDT 24
Finished Jun 05 05:59:49 PM PDT 24
Peak memory 250856 kb
Host smart-b54f6db4-2337-45dd-8229-d3d37f56c7ef
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933844140 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.lc_ctrl_stress_all.3933844140
Directory /workspace/6.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all_with_rand_reset.3181854052
Short name T596
Test name
Test status
Simulation time 8474601586 ps
CPU time 216.21 seconds
Started Jun 05 05:58:44 PM PDT 24
Finished Jun 05 06:02:23 PM PDT 24
Peak memory 333428 kb
Host smart-89182e1e-04fa-4541-924f-2c3b686391ba
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3181854052 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_stress_all_with_rand_reset.3181854052
Directory /workspace/6.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.lc_ctrl_volatile_unlock_smoke.1364781930
Short name T58
Test name
Test status
Simulation time 34333259 ps
CPU time 1.02 seconds
Started Jun 05 05:58:46 PM PDT 24
Finished Jun 05 05:58:49 PM PDT 24
Peak memory 211644 kb
Host smart-7a7a577d-bcf9-476c-ba14-5c24ae330b1a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364781930 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ct
rl_volatile_unlock_smoke.1364781930
Directory /workspace/6.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_alert_test.4880590
Short name T307
Test name
Test status
Simulation time 37402205 ps
CPU time 1.13 seconds
Started Jun 05 05:58:42 PM PDT 24
Finished Jun 05 05:58:45 PM PDT 24
Peak memory 208684 kb
Host smart-74984382-b477-40fd-9840-5dd48679c30f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4880590 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_alert_test.4880590
Directory /workspace/7.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.lc_ctrl_errors.2687362024
Short name T167
Test name
Test status
Simulation time 411334996 ps
CPU time 10.07 seconds
Started Jun 05 05:58:37 PM PDT 24
Finished Jun 05 05:58:49 PM PDT 24
Peak memory 218024 kb
Host smart-9ad01941-bced-4275-9e6e-c7872faefcd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687362024 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_errors.2687362024
Directory /workspace/7.lc_ctrl_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_access.3341367658
Short name T26
Test name
Test status
Simulation time 1648412964 ps
CPU time 5.94 seconds
Started Jun 05 05:58:41 PM PDT 24
Finished Jun 05 05:58:48 PM PDT 24
Peak memory 209580 kb
Host smart-f30628e0-2a15-40cf-8d05-32a858a42a03
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341367658 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_access.3341367658
Directory /workspace/7.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_errors.3767486351
Short name T237
Test name
Test status
Simulation time 2612122286 ps
CPU time 72.56 seconds
Started Jun 05 05:59:00 PM PDT 24
Finished Jun 05 06:00:13 PM PDT 24
Peak memory 218988 kb
Host smart-12c528ef-34e4-4469-9fd1-7ac4ed4dcb9a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767486351 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_er
rors.3767486351
Directory /workspace/7.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_priority.3008873951
Short name T190
Test name
Test status
Simulation time 2016990333 ps
CPU time 17.13 seconds
Started Jun 05 05:58:56 PM PDT 24
Finished Jun 05 05:59:14 PM PDT 24
Peak memory 217180 kb
Host smart-8cc70cc6-c775-4cf6-a694-73424f49fe45
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008873951 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_priority.3
008873951
Directory /workspace/7.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_prog_failure.1207315589
Short name T287
Test name
Test status
Simulation time 1612315714 ps
CPU time 4.88 seconds
Started Jun 05 05:58:44 PM PDT 24
Finished Jun 05 05:58:52 PM PDT 24
Peak memory 218024 kb
Host smart-0a93407a-577b-4bd0-bd5d-8dc999537d14
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207315589 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag
_prog_failure.1207315589
Directory /workspace/7.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_regwen_during_op.360099326
Short name T427
Test name
Test status
Simulation time 1690750916 ps
CPU time 20.78 seconds
Started Jun 05 05:58:42 PM PDT 24
Finished Jun 05 05:59:05 PM PDT 24
Peak memory 217676 kb
Host smart-c18d7a1f-c514-410e-8dcf-345f5c87bf1e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360099326 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_j
tag_regwen_during_op.360099326
Directory /workspace/7.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_smoke.632875770
Short name T257
Test name
Test status
Simulation time 5415283544 ps
CPU time 5.16 seconds
Started Jun 05 05:58:43 PM PDT 24
Finished Jun 05 05:58:51 PM PDT 24
Peak memory 217764 kb
Host smart-5f319a10-dfb0-48bb-9112-c9d257587ce1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632875770 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_smoke.632875770
Directory /workspace/7.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_failure.1741167301
Short name T13
Test name
Test status
Simulation time 2425130063 ps
CPU time 82.02 seconds
Started Jun 05 05:58:41 PM PDT 24
Finished Jun 05 06:00:05 PM PDT 24
Peak memory 280184 kb
Host smart-07403f28-d999-46d1-9560-9e5b0ff048bf
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741167301 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jta
g_state_failure.1741167301
Directory /workspace/7.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_post_trans.3383987089
Short name T212
Test name
Test status
Simulation time 1924405858 ps
CPU time 13.47 seconds
Started Jun 05 05:58:57 PM PDT 24
Finished Jun 05 05:59:11 PM PDT 24
Peak memory 250952 kb
Host smart-8532c425-6e01-4f12-ad2d-61062a041e25
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383987089 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_state_post_trans.3383987089
Directory /workspace/7.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_prog_failure.2245527672
Short name T690
Test name
Test status
Simulation time 270559145 ps
CPU time 2.74 seconds
Started Jun 05 05:58:40 PM PDT 24
Finished Jun 05 05:58:44 PM PDT 24
Peak memory 218028 kb
Host smart-00c59ef2-0c68-429c-a510-4aa9ce0a1acb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2245527672 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_prog_failure.2245527672
Directory /workspace/7.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_regwen_during_op.3626691202
Short name T790
Test name
Test status
Simulation time 282907951 ps
CPU time 18.77 seconds
Started Jun 05 05:58:38 PM PDT 24
Finished Jun 05 05:58:58 PM PDT 24
Peak memory 217784 kb
Host smart-944a3721-9e2d-49e5-b418-d9d85c332b05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626691202 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_regwen_during_op.3626691202
Directory /workspace/7.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_mubi.660962710
Short name T837
Test name
Test status
Simulation time 865529231 ps
CPU time 8.85 seconds
Started Jun 05 05:58:39 PM PDT 24
Finished Jun 05 05:58:49 PM PDT 24
Peak memory 226144 kb
Host smart-06679329-3532-40bb-ab1d-87c4225c8132
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660962710 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_mubi.660962710
Directory /workspace/7.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_digest.2415088770
Short name T533
Test name
Test status
Simulation time 1083420742 ps
CPU time 20.87 seconds
Started Jun 05 05:58:53 PM PDT 24
Finished Jun 05 05:59:15 PM PDT 24
Peak memory 224968 kb
Host smart-9d143466-8c1f-4ed1-93dd-f26c619f6482
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415088770 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_di
gest.2415088770
Directory /workspace/7.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_mux.3785000717
Short name T696
Test name
Test status
Simulation time 408480610 ps
CPU time 8.38 seconds
Started Jun 05 05:58:44 PM PDT 24
Finished Jun 05 05:58:55 PM PDT 24
Peak memory 218112 kb
Host smart-944bf674-68b2-4a60-92a1-807179dcc254
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785000717 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_mux.3
785000717
Directory /workspace/7.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/7.lc_ctrl_security_escalation.1457937750
Short name T615
Test name
Test status
Simulation time 303107887 ps
CPU time 6.91 seconds
Started Jun 05 05:58:35 PM PDT 24
Finished Jun 05 05:58:43 PM PDT 24
Peak memory 218092 kb
Host smart-071f600e-3d1f-4ded-b784-1c01e369eb2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457937750 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_security_escalation.1457937750
Directory /workspace/7.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/7.lc_ctrl_smoke.1490399555
Short name T76
Test name
Test status
Simulation time 106292454 ps
CPU time 2.1 seconds
Started Jun 05 05:58:50 PM PDT 24
Finished Jun 05 05:58:54 PM PDT 24
Peak memory 217764 kb
Host smart-ed04ba4a-c1df-430a-a07c-3f62a5c19b4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490399555 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_smoke.1490399555
Directory /workspace/7.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_failure.3083023135
Short name T781
Test name
Test status
Simulation time 1190957759 ps
CPU time 29.46 seconds
Started Jun 05 05:59:06 PM PDT 24
Finished Jun 05 05:59:36 PM PDT 24
Peak memory 251052 kb
Host smart-27906bbb-5e35-4de3-8b38-299004907328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083023135 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_failure.3083023135
Directory /workspace/7.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_post_trans.2306905636
Short name T532
Test name
Test status
Simulation time 134238777 ps
CPU time 6.47 seconds
Started Jun 05 05:58:34 PM PDT 24
Finished Jun 05 05:58:41 PM PDT 24
Peak memory 246796 kb
Host smart-a76c713f-0167-4c04-98c4-90c631de472d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306905636 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_post_trans.2306905636
Directory /workspace/7.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_stress_all.2541116998
Short name T472
Test name
Test status
Simulation time 7474964434 ps
CPU time 144.87 seconds
Started Jun 05 05:58:50 PM PDT 24
Finished Jun 05 06:01:17 PM PDT 24
Peak memory 288164 kb
Host smart-270a2256-f3bd-4063-afc5-03f5636bd800
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541116998 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.lc_ctrl_stress_all.2541116998
Directory /workspace/7.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.lc_ctrl_volatile_unlock_smoke.464379543
Short name T735
Test name
Test status
Simulation time 28117868 ps
CPU time 1 seconds
Started Jun 05 05:58:49 PM PDT 24
Finished Jun 05 05:58:52 PM PDT 24
Peak memory 211612 kb
Host smart-91f6643e-068d-48d9-b881-8da921a65a9c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464379543 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctr
l_volatile_unlock_smoke.464379543
Directory /workspace/7.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_alert_test.1524504800
Short name T767
Test name
Test status
Simulation time 15927083 ps
CPU time 1.03 seconds
Started Jun 05 05:58:44 PM PDT 24
Finished Jun 05 05:58:48 PM PDT 24
Peak memory 208732 kb
Host smart-59525d0e-6d91-4de4-9f59-eb097cd0ce38
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524504800 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_alert_test.1524504800
Directory /workspace/8.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.lc_ctrl_claim_transition_if.1952461124
Short name T585
Test name
Test status
Simulation time 46937951 ps
CPU time 0.79 seconds
Started Jun 05 05:58:51 PM PDT 24
Finished Jun 05 05:58:54 PM PDT 24
Peak memory 208728 kb
Host smart-dc34b7b1-51c0-4024-9cf3-c4a05c6a551a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952461124 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_claim_transition_if.1952461124
Directory /workspace/8.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/8.lc_ctrl_errors.2896302596
Short name T220
Test name
Test status
Simulation time 255785881 ps
CPU time 9.26 seconds
Started Jun 05 05:59:08 PM PDT 24
Finished Jun 05 05:59:18 PM PDT 24
Peak memory 218096 kb
Host smart-acc6408c-98ad-4fef-ac15-2ac3cfb200eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896302596 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_errors.2896302596
Directory /workspace/8.lc_ctrl_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_access.2760155155
Short name T685
Test name
Test status
Simulation time 4098848003 ps
CPU time 23.6 seconds
Started Jun 05 05:58:39 PM PDT 24
Finished Jun 05 05:59:04 PM PDT 24
Peak memory 209612 kb
Host smart-1b425996-d2ad-4666-901a-9c8123b5782b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760155155 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_access.2760155155
Directory /workspace/8.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_errors.788902815
Short name T376
Test name
Test status
Simulation time 13511428135 ps
CPU time 88.58 seconds
Started Jun 05 05:58:46 PM PDT 24
Finished Jun 05 06:00:17 PM PDT 24
Peak memory 218984 kb
Host smart-ecd0b29e-1246-416f-9b89-fb5f1fcfd5da
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788902815 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_err
ors.788902815
Directory /workspace/8.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_priority.1421174563
Short name T348
Test name
Test status
Simulation time 1021742386 ps
CPU time 6.97 seconds
Started Jun 05 05:58:44 PM PDT 24
Finished Jun 05 05:58:53 PM PDT 24
Peak memory 217768 kb
Host smart-d623dbaf-7395-4f81-b4b3-cecd67351ee6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421174563 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_priority.1
421174563
Directory /workspace/8.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_prog_failure.2126417142
Short name T706
Test name
Test status
Simulation time 200127296 ps
CPU time 4.23 seconds
Started Jun 05 05:59:05 PM PDT 24
Finished Jun 05 05:59:10 PM PDT 24
Peak memory 217964 kb
Host smart-f41810c6-f5b7-474d-8641-a21ec8539873
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126417142 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag
_prog_failure.2126417142
Directory /workspace/8.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_regwen_during_op.2817220797
Short name T645
Test name
Test status
Simulation time 1259184886 ps
CPU time 31.64 seconds
Started Jun 05 05:59:00 PM PDT 24
Finished Jun 05 05:59:32 PM PDT 24
Peak memory 217672 kb
Host smart-5baa146f-ad54-45f9-a7ec-85abc54b08de
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817220797 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_regwen_during_op.2817220797
Directory /workspace/8.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_smoke.82610801
Short name T749
Test name
Test status
Simulation time 66809425 ps
CPU time 2.41 seconds
Started Jun 05 05:58:42 PM PDT 24
Finished Jun 05 05:58:46 PM PDT 24
Peak memory 217708 kb
Host smart-316ec7f7-6966-42a9-ae2f-b30111b3a975
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82610801 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_smoke.82610801
Directory /workspace/8.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_failure.2499273459
Short name T95
Test name
Test status
Simulation time 1213300059 ps
CPU time 37.08 seconds
Started Jun 05 05:58:46 PM PDT 24
Finished Jun 05 05:59:25 PM PDT 24
Peak memory 253896 kb
Host smart-c86903a9-bd45-4f16-abfd-7051ef6fc45a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499273459 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jta
g_state_failure.2499273459
Directory /workspace/8.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_post_trans.2287210708
Short name T219
Test name
Test status
Simulation time 3884153152 ps
CPU time 16.11 seconds
Started Jun 05 05:58:46 PM PDT 24
Finished Jun 05 05:59:04 PM PDT 24
Peak memory 217960 kb
Host smart-66955f7d-b5d1-4625-b9aa-2a48c40c35a6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287210708 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_state_post_trans.2287210708
Directory /workspace/8.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_prog_failure.1201736032
Short name T773
Test name
Test status
Simulation time 89917256 ps
CPU time 2.97 seconds
Started Jun 05 05:58:44 PM PDT 24
Finished Jun 05 05:58:49 PM PDT 24
Peak memory 218016 kb
Host smart-0f1a31a3-0ba8-4c1d-941d-85a6ad655417
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201736032 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_prog_failure.1201736032
Directory /workspace/8.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_regwen_during_op.1778561154
Short name T75
Test name
Test status
Simulation time 193081830 ps
CPU time 12.51 seconds
Started Jun 05 05:58:36 PM PDT 24
Finished Jun 05 05:58:50 PM PDT 24
Peak memory 214508 kb
Host smart-2e1ee96f-3c32-4742-8d4a-c4d91d621d8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778561154 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_regwen_during_op.1778561154
Directory /workspace/8.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_mubi.3171066187
Short name T506
Test name
Test status
Simulation time 2227194127 ps
CPU time 10.33 seconds
Started Jun 05 05:59:03 PM PDT 24
Finished Jun 05 05:59:14 PM PDT 24
Peak memory 218264 kb
Host smart-6e580adf-fff2-4af1-b17c-d508d7d30f74
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171066187 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_mubi.3171066187
Directory /workspace/8.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_digest.3988272477
Short name T563
Test name
Test status
Simulation time 483858931 ps
CPU time 11.59 seconds
Started Jun 05 05:58:50 PM PDT 24
Finished Jun 05 05:59:03 PM PDT 24
Peak memory 226068 kb
Host smart-45799734-fc93-466e-8642-39bf55c4476c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988272477 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_di
gest.3988272477
Directory /workspace/8.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_mux.2864120896
Short name T228
Test name
Test status
Simulation time 497091133 ps
CPU time 6.39 seconds
Started Jun 05 05:58:49 PM PDT 24
Finished Jun 05 05:58:57 PM PDT 24
Peak memory 218052 kb
Host smart-d0ea9892-204a-4101-89ad-1649d049df03
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864120896 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_mux.2
864120896
Directory /workspace/8.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/8.lc_ctrl_security_escalation.503806759
Short name T810
Test name
Test status
Simulation time 355479383 ps
CPU time 9.97 seconds
Started Jun 05 05:58:43 PM PDT 24
Finished Jun 05 05:58:56 PM PDT 24
Peak memory 218196 kb
Host smart-435b9df4-395c-492f-b9b0-05be88625374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503806759 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_security_escalation.503806759
Directory /workspace/8.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/8.lc_ctrl_smoke.2574612396
Short name T548
Test name
Test status
Simulation time 69096119 ps
CPU time 1.33 seconds
Started Jun 05 05:58:47 PM PDT 24
Finished Jun 05 05:58:50 PM PDT 24
Peak memory 217764 kb
Host smart-eb49bed8-2e48-48f8-8596-8a13bf46fce1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574612396 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_smoke.2574612396
Directory /workspace/8.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_failure.4231183958
Short name T340
Test name
Test status
Simulation time 320577482 ps
CPU time 29.41 seconds
Started Jun 05 05:58:50 PM PDT 24
Finished Jun 05 05:59:22 PM PDT 24
Peak memory 251056 kb
Host smart-fbcb8b49-bb4c-48a1-9352-4fd48ffa06a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231183958 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_failure.4231183958
Directory /workspace/8.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_post_trans.4200189575
Short name T82
Test name
Test status
Simulation time 399024356 ps
CPU time 3.31 seconds
Started Jun 05 05:58:44 PM PDT 24
Finished Jun 05 05:58:50 PM PDT 24
Peak memory 218080 kb
Host smart-bdf28864-0807-4d41-acfa-fde74aeade97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200189575 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_post_trans.4200189575
Directory /workspace/8.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all.2482807155
Short name T370
Test name
Test status
Simulation time 6174968081 ps
CPU time 110.38 seconds
Started Jun 05 05:58:48 PM PDT 24
Finished Jun 05 06:00:41 PM PDT 24
Peak memory 283864 kb
Host smart-f5d59ca9-9fda-4c6b-808d-5b8fd6a0a761
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482807155 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.lc_ctrl_stress_all.2482807155
Directory /workspace/8.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all_with_rand_reset.3123091965
Short name T159
Test name
Test status
Simulation time 21553386673 ps
CPU time 522.47 seconds
Started Jun 05 05:58:46 PM PDT 24
Finished Jun 05 06:07:31 PM PDT 24
Peak memory 333636 kb
Host smart-606b35da-f718-452a-a1cb-8d765dae5d92
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3123091965 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_stress_all_with_rand_reset.3123091965
Directory /workspace/8.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.lc_ctrl_volatile_unlock_smoke.4022797277
Short name T529
Test name
Test status
Simulation time 14629836 ps
CPU time 0.98 seconds
Started Jun 05 05:58:56 PM PDT 24
Finished Jun 05 05:58:58 PM PDT 24
Peak memory 211532 kb
Host smart-77d0cb4c-d18b-4aec-95ad-b353e45445d8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022797277 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ct
rl_volatile_unlock_smoke.4022797277
Directory /workspace/8.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_alert_test.3896981858
Short name T574
Test name
Test status
Simulation time 48189537 ps
CPU time 0.83 seconds
Started Jun 05 05:58:49 PM PDT 24
Finished Jun 05 05:58:52 PM PDT 24
Peak memory 209356 kb
Host smart-50baa4b3-9830-44ab-9afa-d0dca19cb8ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896981858 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_alert_test.3896981858
Directory /workspace/9.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.lc_ctrl_claim_transition_if.3670498781
Short name T209
Test name
Test status
Simulation time 21121972 ps
CPU time 0.84 seconds
Started Jun 05 05:58:54 PM PDT 24
Finished Jun 05 05:58:56 PM PDT 24
Peak memory 208540 kb
Host smart-fe121ebb-9a5e-47f0-aba6-6ea9eddca4a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670498781 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_claim_transition_if.3670498781
Directory /workspace/9.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/9.lc_ctrl_errors.3421089806
Short name T730
Test name
Test status
Simulation time 1509930356 ps
CPU time 11.18 seconds
Started Jun 05 05:58:50 PM PDT 24
Finished Jun 05 05:59:03 PM PDT 24
Peak memory 217948 kb
Host smart-03461012-24cc-4c93-8ab9-623eb397b67c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421089806 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_errors.3421089806
Directory /workspace/9.lc_ctrl_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_access.3629364983
Short name T850
Test name
Test status
Simulation time 537626766 ps
CPU time 4.03 seconds
Started Jun 05 05:58:47 PM PDT 24
Finished Jun 05 05:58:53 PM PDT 24
Peak memory 209664 kb
Host smart-df855a0e-0b1d-4d5a-8d14-8d9894a56ba0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629364983 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_access.3629364983
Directory /workspace/9.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_priority.2650712954
Short name T368
Test name
Test status
Simulation time 1142782774 ps
CPU time 4.32 seconds
Started Jun 05 05:58:48 PM PDT 24
Finished Jun 05 05:58:54 PM PDT 24
Peak memory 217052 kb
Host smart-00acc9c8-1e90-48a9-a0bb-7a76fd18fe2f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650712954 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_priority.2
650712954
Directory /workspace/9.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_prog_failure.1183646499
Short name T420
Test name
Test status
Simulation time 112074942 ps
CPU time 2.56 seconds
Started Jun 05 05:58:48 PM PDT 24
Finished Jun 05 05:58:53 PM PDT 24
Peak memory 218056 kb
Host smart-a28fccf9-4fc2-40e9-bad4-8f64f91bc429
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183646499 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag
_prog_failure.1183646499
Directory /workspace/9.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_regwen_during_op.2440639648
Short name T77
Test name
Test status
Simulation time 1207793337 ps
CPU time 36.51 seconds
Started Jun 05 05:59:09 PM PDT 24
Finished Jun 05 05:59:46 PM PDT 24
Peak memory 217700 kb
Host smart-55a3495d-e272-41f1-b11a-643b9321e668
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440639648 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_regwen_during_op.2440639648
Directory /workspace/9.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_smoke.4206166865
Short name T323
Test name
Test status
Simulation time 1554707601 ps
CPU time 10.33 seconds
Started Jun 05 05:58:51 PM PDT 24
Finished Jun 05 05:59:03 PM PDT 24
Peak memory 217632 kb
Host smart-81956c4d-0ce7-4e25-9cb8-56872f51f607
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206166865 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_smoke.
4206166865
Directory /workspace/9.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_failure.2395613392
Short name T478
Test name
Test status
Simulation time 2542366944 ps
CPU time 57.74 seconds
Started Jun 05 05:58:49 PM PDT 24
Finished Jun 05 05:59:49 PM PDT 24
Peak memory 275808 kb
Host smart-088aba60-0a92-403f-8066-26b781730fc0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395613392 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jta
g_state_failure.2395613392
Directory /workspace/9.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_post_trans.4205403330
Short name T862
Test name
Test status
Simulation time 439924671 ps
CPU time 13.62 seconds
Started Jun 05 05:58:49 PM PDT 24
Finished Jun 05 05:59:05 PM PDT 24
Peak memory 250772 kb
Host smart-11a4fb44-6161-427b-83ed-16500fbde0fc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205403330 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_state_post_trans.4205403330
Directory /workspace/9.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_prog_failure.1708767188
Short name T796
Test name
Test status
Simulation time 134642162 ps
CPU time 3.56 seconds
Started Jun 05 05:58:42 PM PDT 24
Finished Jun 05 05:58:46 PM PDT 24
Peak memory 218028 kb
Host smart-fd0aeebb-8b7d-4297-8141-3ac7d42bdd93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708767188 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_prog_failure.1708767188
Directory /workspace/9.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_regwen_during_op.1178234706
Short name T602
Test name
Test status
Simulation time 759224152 ps
CPU time 11.47 seconds
Started Jun 05 05:58:46 PM PDT 24
Finished Jun 05 05:59:04 PM PDT 24
Peak memory 217852 kb
Host smart-24bdefa3-16fc-4316-a877-aab9c03a41b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178234706 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_regwen_during_op.1178234706
Directory /workspace/9.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_mubi.2449886449
Short name T610
Test name
Test status
Simulation time 759432167 ps
CPU time 7.97 seconds
Started Jun 05 05:58:54 PM PDT 24
Finished Jun 05 05:59:03 PM PDT 24
Peak memory 225592 kb
Host smart-d1a1a4b8-3eeb-44d9-9933-274f0bd85acd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449886449 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_mubi.2449886449
Directory /workspace/9.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_digest.2526480708
Short name T572
Test name
Test status
Simulation time 1328756992 ps
CPU time 8.78 seconds
Started Jun 05 05:59:14 PM PDT 24
Finished Jun 05 05:59:23 PM PDT 24
Peak memory 217988 kb
Host smart-f05ac59e-2eb8-488b-8b92-f8d5d3da4331
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526480708 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_di
gest.2526480708
Directory /workspace/9.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_mux.3853248886
Short name T55
Test name
Test status
Simulation time 1893097697 ps
CPU time 11.85 seconds
Started Jun 05 05:59:08 PM PDT 24
Finished Jun 05 05:59:21 PM PDT 24
Peak memory 218116 kb
Host smart-bc37ce7d-d5d7-4d19-a209-f2ce36b427f0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853248886 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_mux.3
853248886
Directory /workspace/9.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/9.lc_ctrl_security_escalation.3206646897
Short name T542
Test name
Test status
Simulation time 1422522478 ps
CPU time 11.04 seconds
Started Jun 05 05:58:40 PM PDT 24
Finished Jun 05 05:58:53 PM PDT 24
Peak memory 218120 kb
Host smart-7f6ce784-0515-4832-b185-2ec172ff4281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206646897 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_security_escalation.3206646897
Directory /workspace/9.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/9.lc_ctrl_smoke.1887268791
Short name T642
Test name
Test status
Simulation time 111847194 ps
CPU time 2.76 seconds
Started Jun 05 05:58:59 PM PDT 24
Finished Jun 05 05:59:08 PM PDT 24
Peak memory 214648 kb
Host smart-91dbaafd-88c8-4f2a-821c-1060bbb2329c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887268791 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_smoke.1887268791
Directory /workspace/9.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_failure.4271435533
Short name T691
Test name
Test status
Simulation time 775075404 ps
CPU time 20.28 seconds
Started Jun 05 05:58:44 PM PDT 24
Finished Jun 05 05:59:07 PM PDT 24
Peak memory 250720 kb
Host smart-acbb2575-92e5-4265-b81d-989108763d38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271435533 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_failure.4271435533
Directory /workspace/9.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_post_trans.476376602
Short name T35
Test name
Test status
Simulation time 316723983 ps
CPU time 6.06 seconds
Started Jun 05 05:58:42 PM PDT 24
Finished Jun 05 05:58:50 PM PDT 24
Peak memory 250512 kb
Host smart-41bcee54-80e3-4f26-8686-5c706edfe7d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476376602 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_post_trans.476376602
Directory /workspace/9.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_stress_all.1515676229
Short name T96
Test name
Test status
Simulation time 9886201166 ps
CPU time 91.88 seconds
Started Jun 05 05:58:48 PM PDT 24
Finished Jun 05 06:00:22 PM PDT 24
Peak memory 270076 kb
Host smart-86415ab8-6c7f-4d89-b971-1db5bb587dfb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515676229 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.lc_ctrl_stress_all.1515676229
Directory /workspace/9.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.lc_ctrl_volatile_unlock_smoke.3682114117
Short name T637
Test name
Test status
Simulation time 14806480 ps
CPU time 1.12 seconds
Started Jun 05 05:58:46 PM PDT 24
Finished Jun 05 05:58:49 PM PDT 24
Peak memory 211556 kb
Host smart-b95adb3f-8f17-42a7-a986-9b3bea8e6b41
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682114117 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ct
rl_volatile_unlock_smoke.3682114117
Directory /workspace/9.lc_ctrl_volatile_unlock_smoke/latest
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