Summary for Variable clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52286 |
1 |
|
|
T1 |
119 |
|
T2 |
89 |
|
T3 |
10 |
auto[1] |
1921 |
1 |
|
|
T1 |
11 |
|
T2 |
11 |
|
T20 |
30 |
Summary for Variable clk_byp_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53404 |
1 |
|
|
T1 |
130 |
|
T2 |
100 |
|
T3 |
10 |
auto[1] |
803 |
1 |
|
|
T67 |
13 |
|
T52 |
20 |
|
T68 |
20 |
Summary for Variable count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52358 |
1 |
|
|
T1 |
128 |
|
T2 |
100 |
|
T3 |
9 |
auto[1] |
1849 |
1 |
|
|
T1 |
2 |
|
T3 |
1 |
|
T12 |
1 |
Summary for Variable count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52418 |
1 |
|
|
T1 |
129 |
|
T2 |
100 |
|
T3 |
10 |
auto[1] |
1789 |
1 |
|
|
T1 |
1 |
|
T16 |
6 |
|
T18 |
7 |
Summary for Variable count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52328 |
1 |
|
|
T1 |
130 |
|
T2 |
100 |
|
T3 |
9 |
auto[1] |
1879 |
1 |
|
|
T3 |
1 |
|
T12 |
2 |
|
T16 |
5 |
Summary for Variable err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for err_inj_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
err_inj |
49388 |
1 |
|
|
T1 |
110 |
|
T2 |
100 |
|
T3 |
5 |
no_err_inj |
4819 |
1 |
|
|
T1 |
20 |
|
T3 |
5 |
|
T4 |
10 |
Summary for Variable flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52302 |
1 |
|
|
T1 |
116 |
|
T2 |
93 |
|
T3 |
10 |
auto[1] |
1905 |
1 |
|
|
T1 |
14 |
|
T2 |
7 |
|
T20 |
36 |
Summary for Variable flash_rma_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53461 |
1 |
|
|
T1 |
130 |
|
T2 |
100 |
|
T3 |
10 |
auto[1] |
746 |
1 |
|
|
T67 |
16 |
|
T52 |
16 |
|
T68 |
7 |
Summary for Variable jtag_csr_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for jtag_csr_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
38006 |
1 |
|
|
T1 |
13 |
|
T2 |
100 |
|
T3 |
10 |
auto[1] |
16201 |
1 |
|
|
T1 |
117 |
|
T4 |
14 |
|
T5 |
5 |
Summary for Variable kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for kmac_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52293 |
1 |
|
|
T1 |
127 |
|
T2 |
100 |
|
T3 |
10 |
auto[1] |
1914 |
1 |
|
|
T1 |
3 |
|
T16 |
13 |
|
T18 |
10 |
Summary for Variable lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for lc_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52306 |
1 |
|
|
T1 |
129 |
|
T2 |
100 |
|
T3 |
9 |
auto[1] |
1901 |
1 |
|
|
T1 |
1 |
|
T3 |
1 |
|
T16 |
12 |
Summary for Variable otp_lc_data_i_valid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_lc_data_i_valid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52322 |
1 |
|
|
T1 |
129 |
|
T2 |
100 |
|
T3 |
9 |
auto[1] |
1885 |
1 |
|
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_partition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52307 |
1 |
|
|
T1 |
119 |
|
T2 |
89 |
|
T3 |
10 |
auto[1] |
1900 |
1 |
|
|
T1 |
11 |
|
T2 |
11 |
|
T20 |
40 |
Summary for Variable otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_prog_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51932 |
1 |
|
|
T1 |
125 |
|
T2 |
100 |
|
T3 |
10 |
auto[1] |
2275 |
1 |
|
|
T1 |
5 |
|
T13 |
10 |
|
T14 |
7 |
Summary for Variable otp_rma_token_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_rma_token_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53394 |
1 |
|
|
T1 |
130 |
|
T2 |
100 |
|
T3 |
10 |
auto[1] |
813 |
1 |
|
|
T67 |
13 |
|
T52 |
22 |
|
T68 |
14 |
Summary for Variable otp_secrets_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_secrets_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53419 |
1 |
|
|
T1 |
130 |
|
T2 |
100 |
|
T3 |
10 |
auto[1] |
788 |
1 |
|
|
T67 |
8 |
|
T52 |
20 |
|
T68 |
16 |
Summary for Variable otp_test_tokens_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_test_tokens_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53420 |
1 |
|
|
T1 |
130 |
|
T2 |
100 |
|
T3 |
10 |
auto[1] |
787 |
1 |
|
|
T67 |
10 |
|
T52 |
16 |
|
T68 |
21 |
Summary for Variable post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for post_trans_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51552 |
1 |
|
|
T1 |
106 |
|
T2 |
100 |
|
T11 |
81 |
auto[1] |
2655 |
1 |
|
|
T1 |
24 |
|
T3 |
10 |
|
T4 |
14 |
Summary for Variable security_escalation_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for security_escalation_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50455 |
1 |
|
|
T1 |
130 |
|
T2 |
100 |
|
T3 |
10 |
auto[1] |
3752 |
1 |
|
|
T11 |
81 |
|
T46 |
82 |
|
T44 |
88 |
Summary for Variable state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52317 |
1 |
|
|
T1 |
130 |
|
T2 |
100 |
|
T3 |
9 |
auto[1] |
1890 |
1 |
|
|
T3 |
1 |
|
T4 |
2 |
|
T16 |
7 |
Summary for Variable state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52375 |
1 |
|
|
T1 |
128 |
|
T2 |
100 |
|
T3 |
10 |
auto[1] |
1832 |
1 |
|
|
T1 |
2 |
|
T4 |
1 |
|
T16 |
10 |
Summary for Variable state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52357 |
1 |
|
|
T1 |
129 |
|
T2 |
100 |
|
T3 |
10 |
auto[1] |
1850 |
1 |
|
|
T1 |
1 |
|
T12 |
1 |
|
T16 |
9 |
Summary for Variable token_invalid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_invalid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52291 |
1 |
|
|
T1 |
125 |
|
T2 |
91 |
|
T3 |
10 |
auto[1] |
1916 |
1 |
|
|
T1 |
5 |
|
T2 |
9 |
|
T20 |
30 |
Summary for Variable token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mismatch_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
48572 |
1 |
|
|
T1 |
116 |
|
T2 |
79 |
|
T3 |
10 |
auto[1] |
5635 |
1 |
|
|
T1 |
14 |
|
T2 |
21 |
|
T15 |
87 |
Summary for Variable token_mux_ctrl_redun_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mux_ctrl_redun_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50494 |
1 |
|
|
T1 |
130 |
|
T2 |
100 |
|
T3 |
10 |
auto[1] |
3713 |
1 |
|
|
T57 |
61 |
|
T65 |
85 |
|
T66 |
55 |
Summary for Variable token_mux_digest_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for token_mux_digest_err_cp
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54207 |
1 |
|
|
T1 |
130 |
|
T2 |
100 |
|
T3 |
10 |
Summary for Variable token_response_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_response_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52352 |
1 |
|
|
T1 |
120 |
|
T2 |
83 |
|
T3 |
10 |
auto[1] |
1855 |
1 |
|
|
T1 |
10 |
|
T2 |
17 |
|
T20 |
44 |
Summary for Variable transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52330 |
1 |
|
|
T1 |
120 |
|
T2 |
91 |
|
T3 |
10 |
auto[1] |
1877 |
1 |
|
|
T1 |
10 |
|
T2 |
9 |
|
T20 |
50 |
Summary for Variable transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52294 |
1 |
|
|
T1 |
111 |
|
T2 |
85 |
|
T3 |
10 |
auto[1] |
1913 |
1 |
|
|
T1 |
19 |
|
T2 |
15 |
|
T20 |
44 |
Summary for Cross post_trans_err_inj_xp
Samples crossed: post_trans_err_cp err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_err_inj_xp
Bins
post_trans_err_cp | err_inj_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
err_inj |
48084 |
1 |
|
|
T1 |
99 |
|
T2 |
100 |
|
T11 |
81 |
auto[0] |
no_err_inj |
3468 |
1 |
|
|
T1 |
7 |
|
T5 |
5 |
|
T17 |
10 |
auto[1] |
err_inj |
1304 |
1 |
|
|
T1 |
11 |
|
T3 |
5 |
|
T4 |
4 |
auto[1] |
no_err_inj |
1351 |
1 |
|
|
T1 |
13 |
|
T3 |
5 |
|
T4 |
10 |
Summary for Cross post_trans_state_err_xp
Samples crossed: post_trans_err_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_err_xp
Bins
post_trans_err_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
49872 |
1 |
|
|
T1 |
106 |
|
T2 |
100 |
|
T11 |
81 |
auto[0] |
auto[1] |
1680 |
1 |
|
|
T16 |
10 |
|
T18 |
6 |
|
T94 |
7 |
auto[1] |
auto[0] |
2503 |
1 |
|
|
T1 |
22 |
|
T3 |
10 |
|
T4 |
13 |
auto[1] |
auto[1] |
152 |
1 |
|
|
T1 |
2 |
|
T4 |
1 |
|
T20 |
1 |
Summary for Cross post_trans_lc_fsm_backdoor_err_xp
Samples crossed: post_trans_err_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_lc_fsm_backdoor_err_xp
Bins
post_trans_err_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
49797 |
1 |
|
|
T1 |
106 |
|
T2 |
100 |
|
T11 |
81 |
auto[0] |
auto[1] |
1755 |
1 |
|
|
T16 |
12 |
|
T18 |
5 |
|
T94 |
12 |
auto[1] |
auto[0] |
2509 |
1 |
|
|
T1 |
23 |
|
T3 |
9 |
|
T4 |
14 |
auto[1] |
auto[1] |
146 |
1 |
|
|
T1 |
1 |
|
T3 |
1 |
|
T20 |
1 |
Summary for Cross post_trans_state_illegal_err_xp
Samples crossed: post_trans_err_cp state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_illegal_err_xp
Bins
post_trans_err_cp | state_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
49846 |
1 |
|
|
T1 |
106 |
|
T2 |
100 |
|
T11 |
81 |
auto[0] |
auto[1] |
1706 |
1 |
|
|
T16 |
9 |
|
T18 |
6 |
|
T94 |
6 |
auto[1] |
auto[0] |
2511 |
1 |
|
|
T1 |
23 |
|
T3 |
10 |
|
T4 |
14 |
auto[1] |
auto[1] |
144 |
1 |
|
|
T1 |
1 |
|
T12 |
1 |
|
T19 |
2 |
Summary for Cross post_trans_count_err_xp
Samples crossed: post_trans_err_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_err_xp
Bins
post_trans_err_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
49883 |
1 |
|
|
T1 |
106 |
|
T2 |
100 |
|
T11 |
81 |
auto[0] |
auto[1] |
1669 |
1 |
|
|
T16 |
6 |
|
T18 |
7 |
|
T94 |
5 |
auto[1] |
auto[0] |
2535 |
1 |
|
|
T1 |
23 |
|
T3 |
10 |
|
T4 |
14 |
auto[1] |
auto[1] |
120 |
1 |
|
|
T1 |
1 |
|
T20 |
1 |
|
T35 |
3 |
Summary for Cross post_trans_count_illegal_err_xp
Samples crossed: post_trans_err_cp count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_illegal_err_xp
Bins
post_trans_err_cp | count_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
49832 |
1 |
|
|
T1 |
106 |
|
T2 |
100 |
|
T11 |
81 |
auto[0] |
auto[1] |
1720 |
1 |
|
|
T16 |
5 |
|
T18 |
7 |
|
T94 |
9 |
auto[1] |
auto[0] |
2496 |
1 |
|
|
T1 |
24 |
|
T3 |
9 |
|
T4 |
14 |
auto[1] |
auto[1] |
159 |
1 |
|
|
T3 |
1 |
|
T12 |
2 |
|
T20 |
2 |
Summary for Cross post_trans_count_backdoor_err_xp
Samples crossed: post_trans_err_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_backdoor_err_xp
Bins
post_trans_err_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
49853 |
1 |
|
|
T1 |
106 |
|
T2 |
100 |
|
T11 |
81 |
auto[0] |
auto[1] |
1699 |
1 |
|
|
T16 |
7 |
|
T18 |
4 |
|
T94 |
3 |
auto[1] |
auto[0] |
2505 |
1 |
|
|
T1 |
22 |
|
T3 |
9 |
|
T4 |
14 |
auto[1] |
auto[1] |
150 |
1 |
|
|
T1 |
2 |
|
T3 |
1 |
|
T12 |
1 |
Summary for Cross jtag_clk_byp_error_rsp_xp
Samples crossed: jtag_csr_cp clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_clk_byp_error_rsp_xp
Bins
jtag_csr_cp | clk_byp_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36917 |
1 |
|
|
T1 |
13 |
|
T2 |
89 |
|
T3 |
10 |
auto[0] |
auto[1] |
1089 |
1 |
|
|
T2 |
11 |
|
T20 |
25 |
|
T165 |
10 |
auto[1] |
auto[0] |
15369 |
1 |
|
|
T1 |
106 |
|
T4 |
14 |
|
T5 |
5 |
auto[1] |
auto[1] |
832 |
1 |
|
|
T1 |
11 |
|
T20 |
5 |
|
T21 |
14 |
Summary for Cross jtag_flash_rma_error_rsp_xp
Samples crossed: jtag_csr_cp flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_flash_rma_error_rsp_xp
Bins
jtag_csr_cp | flash_rma_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36936 |
1 |
|
|
T1 |
13 |
|
T2 |
93 |
|
T3 |
10 |
auto[0] |
auto[1] |
1070 |
1 |
|
|
T2 |
7 |
|
T20 |
27 |
|
T165 |
9 |
auto[1] |
auto[0] |
15366 |
1 |
|
|
T1 |
103 |
|
T4 |
14 |
|
T5 |
5 |
auto[1] |
auto[1] |
835 |
1 |
|
|
T1 |
14 |
|
T20 |
9 |
|
T21 |
9 |
Summary for Cross jtag_otp_prog_err_xp
Samples crossed: jtag_csr_cp otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_prog_err_xp
Bins
jtag_csr_cp | otp_prog_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36681 |
1 |
|
|
T1 |
13 |
|
T2 |
100 |
|
T3 |
10 |
auto[0] |
auto[1] |
1325 |
1 |
|
|
T13 |
10 |
|
T14 |
7 |
|
T236 |
16 |
auto[1] |
auto[0] |
15251 |
1 |
|
|
T1 |
112 |
|
T4 |
14 |
|
T5 |
5 |
auto[1] |
auto[1] |
950 |
1 |
|
|
T1 |
5 |
|
T22 |
10 |
|
T35 |
18 |
Summary for Cross jtag_otp_partition_err_xp
Samples crossed: jtag_csr_cp otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_partition_err_xp
Bins
jtag_csr_cp | otp_partition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36931 |
1 |
|
|
T1 |
13 |
|
T2 |
89 |
|
T3 |
10 |
auto[0] |
auto[1] |
1075 |
1 |
|
|
T2 |
11 |
|
T20 |
26 |
|
T165 |
15 |
auto[1] |
auto[0] |
15376 |
1 |
|
|
T1 |
106 |
|
T4 |
14 |
|
T5 |
5 |
auto[1] |
auto[1] |
825 |
1 |
|
|
T1 |
11 |
|
T20 |
14 |
|
T21 |
11 |
Summary for Cross jtag_token_mismatch_err_xp
Samples crossed: jtag_csr_cp token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_token_mismatch_err_xp
Bins
jtag_csr_cp | token_mismatch_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
33190 |
1 |
|
|
T1 |
13 |
|
T2 |
79 |
|
T3 |
10 |
auto[0] |
auto[1] |
4816 |
1 |
|
|
T2 |
21 |
|
T15 |
87 |
|
T93 |
54 |
auto[1] |
auto[0] |
15382 |
1 |
|
|
T1 |
103 |
|
T4 |
14 |
|
T5 |
5 |
auto[1] |
auto[1] |
819 |
1 |
|
|
T1 |
14 |
|
T20 |
3 |
|
T21 |
10 |
Summary for Cross jtag_state_err_xp
Samples crossed: jtag_csr_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_err_xp
Bins
jtag_csr_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36881 |
1 |
|
|
T1 |
11 |
|
T2 |
100 |
|
T3 |
10 |
auto[0] |
auto[1] |
1125 |
1 |
|
|
T1 |
2 |
|
T16 |
10 |
|
T94 |
7 |
auto[1] |
auto[0] |
15494 |
1 |
|
|
T1 |
117 |
|
T4 |
13 |
|
T5 |
5 |
auto[1] |
auto[1] |
707 |
1 |
|
|
T4 |
1 |
|
T18 |
6 |
|
T20 |
6 |
Summary for Cross jtag_state_backdoor_err_xp
Samples crossed: jtag_csr_cp state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_backdoor_err_xp
Bins
jtag_csr_cp | state_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36888 |
1 |
|
|
T1 |
13 |
|
T2 |
100 |
|
T3 |
9 |
auto[0] |
auto[1] |
1118 |
1 |
|
|
T3 |
1 |
|
T16 |
7 |
|
T94 |
6 |
auto[1] |
auto[0] |
15429 |
1 |
|
|
T1 |
117 |
|
T4 |
12 |
|
T5 |
5 |
auto[1] |
auto[1] |
772 |
1 |
|
|
T4 |
2 |
|
T18 |
5 |
|
T19 |
1 |
Summary for Cross jtag_lc_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_lc_fsm_backdoor_err_xp
Bins
jtag_csr_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36849 |
1 |
|
|
T1 |
13 |
|
T2 |
100 |
|
T3 |
9 |
auto[0] |
auto[1] |
1157 |
1 |
|
|
T3 |
1 |
|
T16 |
12 |
|
T94 |
12 |
auto[1] |
auto[0] |
15457 |
1 |
|
|
T1 |
116 |
|
T4 |
14 |
|
T5 |
5 |
auto[1] |
auto[1] |
744 |
1 |
|
|
T1 |
1 |
|
T18 |
5 |
|
T20 |
9 |
Summary for Cross jtag_kmac_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_kmac_fsm_backdoor_err_xp
Bins
jtag_csr_cp | kmac_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36807 |
1 |
|
|
T1 |
11 |
|
T2 |
100 |
|
T3 |
10 |
auto[0] |
auto[1] |
1199 |
1 |
|
|
T1 |
2 |
|
T16 |
13 |
|
T94 |
5 |
auto[1] |
auto[0] |
15486 |
1 |
|
|
T1 |
116 |
|
T4 |
14 |
|
T5 |
5 |
auto[1] |
auto[1] |
715 |
1 |
|
|
T1 |
1 |
|
T18 |
10 |
|
T19 |
1 |
Summary for Cross jtag_count_err_xp
Samples crossed: jtag_csr_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_err_xp
Bins
jtag_csr_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36918 |
1 |
|
|
T1 |
12 |
|
T2 |
100 |
|
T3 |
10 |
auto[0] |
auto[1] |
1088 |
1 |
|
|
T1 |
1 |
|
T16 |
6 |
|
T94 |
5 |
auto[1] |
auto[0] |
15500 |
1 |
|
|
T1 |
117 |
|
T4 |
14 |
|
T5 |
5 |
auto[1] |
auto[1] |
701 |
1 |
|
|
T18 |
7 |
|
T20 |
5 |
|
T31 |
6 |
Summary for Cross jtag_count_backdoor_err_xp
Samples crossed: jtag_csr_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_backdoor_err_xp
Bins
jtag_csr_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36867 |
1 |
|
|
T1 |
13 |
|
T2 |
100 |
|
T3 |
9 |
auto[0] |
auto[1] |
1139 |
1 |
|
|
T3 |
1 |
|
T12 |
1 |
|
T16 |
7 |
auto[1] |
auto[0] |
15491 |
1 |
|
|
T1 |
115 |
|
T4 |
14 |
|
T5 |
5 |
auto[1] |
auto[1] |
710 |
1 |
|
|
T1 |
2 |
|
T18 |
4 |
|
T19 |
2 |
Summary for Cross jtag_transition_err_xp
Samples crossed: jtag_csr_cp transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_err_xp
Bins
jtag_csr_cp | transition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36909 |
1 |
|
|
T1 |
13 |
|
T2 |
85 |
|
T3 |
10 |
auto[0] |
auto[1] |
1097 |
1 |
|
|
T2 |
15 |
|
T20 |
34 |
|
T165 |
8 |
auto[1] |
auto[0] |
15385 |
1 |
|
|
T1 |
98 |
|
T4 |
14 |
|
T5 |
5 |
auto[1] |
auto[1] |
816 |
1 |
|
|
T1 |
19 |
|
T20 |
10 |
|
T21 |
8 |
Summary for Cross jtag_transition_count_err_xp
Samples crossed: jtag_csr_cp transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_count_err_xp
Bins
jtag_csr_cp | transition_count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36930 |
1 |
|
|
T1 |
13 |
|
T2 |
91 |
|
T3 |
10 |
auto[0] |
auto[1] |
1076 |
1 |
|
|
T2 |
9 |
|
T20 |
40 |
|
T165 |
6 |
auto[1] |
auto[0] |
15400 |
1 |
|
|
T1 |
107 |
|
T4 |
14 |
|
T5 |
5 |
auto[1] |
auto[1] |
801 |
1 |
|
|
T1 |
10 |
|
T20 |
10 |
|
T21 |
8 |
Summary for Cross jtag_post_trans_err_xp
Samples crossed: jtag_csr_cp post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_post_trans_err_xp
Bins
jtag_csr_cp | post_trans_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36430 |
1 |
|
|
T2 |
100 |
|
T11 |
81 |
|
T13 |
10 |
auto[0] |
auto[1] |
1576 |
1 |
|
|
T1 |
13 |
|
T3 |
10 |
|
T12 |
13 |
auto[1] |
auto[0] |
15122 |
1 |
|
|
T1 |
106 |
|
T5 |
5 |
|
T17 |
10 |
auto[1] |
auto[1] |
1079 |
1 |
|
|
T1 |
11 |
|
T4 |
14 |
|
T19 |
12 |