Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

104943346

1

T1

253177

T2

41481

T3

6859

auto[1]

1419887

1

T1

790

T2

693

T3

396

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

104985894

1

T1

252291

T2

41778

T3

7255

auto[1]

1377339

1

T1

1676

T2

396

T4

196

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	7198898	1			T1	12519		T2	9593		T3	1676
auto[IdleSt]	22030370	1			T1	120776		T2	11632		T3	1258
auto[ClkMuxSt]	36204	1			T1	119		T2	100		T3	5
auto[CntIncrSt]	35920	1			T1	119		T2	100		T3	5
auto[CntProgSt]	1445944	1			T1	1615		T2	172		T3	486
auto[TransCheckSt]	28040	1			T1	93		T2	81		T3	5
auto[TokenHashSt]	45502915	1			T1	2695		T2	732		T3	536
auto[FlashRmaSt]	29023	1			T1	76		T2	19		T3	5
auto[TokenCheck0St]	12866	1			T1	45		T2	19		T3	5
auto[TokenCheck1St]	9565	1			T1	32		T2	14		T3	5
auto[TransProgSt]	361343	1			T1	536		T2	23		T3	488
auto[PostTransSt]	12979927	1			T1	95954		T2	18108		T3	1233
auto[ScrapSt]	267930	1			T11	6		T46	6		T5	830
auto[EscalateSt]	6300616	1			T1	13753		T2	1581		T3	994
auto[InvalidSt]	10121681	1			T1	5634		T3	553		T4	4490

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1991	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	10121681	1			T1	5634		T3	553		T4	4490
EscalateSt	6300616	1			T1	13753		T2	1581		T3	994
ScrapSt	267930	1			T11	6		T46	6		T5	830
PostTransSt	12979927	1			T1	95954		T2	18108		T3	1233
TransProgSt	361343	1			T1	536		T2	23		T3	488
TokenCheck1St	9565	1			T1	32		T2	14		T3	5
TokenCheck0St	12866	1			T1	45		T2	19		T3	5
FlashRmaSt	29023	1			T1	76		T2	19		T3	5
TokenHashSt	45502915	1			T1	2695		T2	732		T3	536
TransCheckSt	28040	1			T1	93		T2	81		T3	5
CntProgSt	1445944	1			T1	1615		T2	172		T3	486
CntIncrSt	35920	1			T1	119		T2	100		T3	5
ClkMuxSt	36204	1			T1	119		T2	100		T3	5
IdleSt	22030370	1			T1	120776		T2	11632		T3	1258
ResetSt	7198898	1			T1	12519		T2	9593		T3	1676
arcs[ResetSt=>IdleSt]	54566	1			T1	134		T2	101		T3	10
arcs[IdleSt=>ScrapSt]	300	1			T11	2		T46	2		T5	1
arcs[IdleSt=>ClkMuxSt]	35988	1			T1	119		T2	100		T3	5
arcs[ClkMuxSt=>CntIncrSt]	35920	1			T1	119		T2	100		T3	5
arcs[CntIncrSt=>PostTransSt]	1881	1			T1	10		T2	9		T20	50
arcs[CntIncrSt=>CntProgSt]	33965	1			T1	109		T2	91		T3	5
arcs[CntProgSt=>PostTransSt]	4973	1			T1	16		T2	10		T13	10
arcs[CntProgSt=>TransCheckSt]	28040	1			T1	93		T2	81		T3	5
arcs[TransCheckSt=>PostTransSt]	3773	1			T1	19		T2	15		T20	44
arcs[TransCheckSt=>TokenHashSt]	24122	1			T1	74		T2	66		T3	5
arcs[TokenHashSt=>PostTransSt]	10407	1			T1	29		T2	47		T15	87
arcs[TokenHashSt=>FlashRmaSt]	12966	1			T1	45		T2	19		T3	5
arcs[FlashRmaSt=>TokenCheck0St]	12866	1			T1	45		T2	19		T3	5
arcs[TokenCheck0St=>PostTransSt]	3273	1			T1	13		T2	5		T20	33
arcs[TokenCheck0St=>TokenCheck1St]	9565	1			T1	32		T2	14		T3	5
arcs[TokenCheck1St=>PostTransSt]	695	1			T1	1		T2	2		T20	4
arcs[TransProgSt=>PostTransSt]	8031	1			T1	31		T2	12		T3	5
arcs[IdleSt=>EscalateSt]	222	1			T11	12		T44	6		T58	7
arcs[ClkMuxSt=>EscalateSt]	68	1			T44	4		T58	2		T59	2
arcs[CntIncrSt=>EscalateSt]	74	1			T11	3		T46	1		T58	2
arcs[CntProgSt=>EscalateSt]	952	1			T11	18		T46	11		T44	14
arcs[TransCheckSt=>EscalateSt]	145	1			T11	3		T46	6		T44	7
arcs[TokenHashSt=>EscalateSt]	749	1			T11	9		T46	23		T44	24
arcs[FlashRmaSt=>EscalateSt]	100	1			T11	2		T46	2		T44	4
arcs[TokenCheck0St=>EscalateSt]	28	1			T58	2		T37	1		T61	3
arcs[TokenCheck1St=>EscalateSt]	141	1			T11	4		T46	4		T44	5
arcs[TransProgSt=>EscalateSt]	698	1			T11	21		T46	12		T44	8
arcs[PostTransSt=>EscalateSt]	5266	1			T1	16		T2	11		T11	3
arcs[InvalidSt=>EscalateSt]	13855	1			T1	9		T3	4		T4	3

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7198734	1			T1	12519		T2	9593		T3	1676
auto[0]	auto[IdleSt]	22030213	1			T1	120776		T2	11632		T3	1258
auto[0]	auto[ClkMuxSt]	36161	1			T1	119		T2	100		T3	5
auto[0]	auto[CntIncrSt]	35869	1			T1	119		T2	100		T3	5
auto[0]	auto[CntProgSt]	1445293	1			T1	1615		T2	172		T3	486
auto[0]	auto[TransCheckSt]	27947	1			T1	93		T2	81		T3	5
auto[0]	auto[TokenHashSt]	45502402	1			T1	2695		T2	732		T3	536
auto[0]	auto[FlashRmaSt]	28955	1			T1	76		T2	19		T3	5
auto[0]	auto[TokenCheck0St]	12847	1			T1	45		T2	19		T3	5
auto[0]	auto[TokenCheck1St]	9469	1			T1	32		T2	14		T3	5
auto[0]	auto[TransProgSt]	360880	1			T1	536		T2	23		T3	488
auto[0]	auto[PostTransSt]	12977127	1			T1	95951		T2	18101		T3	1233
auto[0]	auto[ScrapSt]	267880	1			T11	4		T46	4		T5	830
auto[0]	auto[EscalateSt]	4892846	1			T1	12971		T2	895		T3	602
auto[0]	auto[InvalidSt]	10114732	1			T1	5629		T3	549		T4	4489
auto[1]	auto[ResetSt]	164	1			T11	2		T46	3		T44	2
auto[1]	auto[IdleSt]	157	1			T11	7		T44	3		T58	5
auto[1]	auto[ClkMuxSt]	43	1			T44	3		T58	1		T59	1
auto[1]	auto[CntIncrSt]	51	1			T11	3		T46	1		T58	1
auto[1]	auto[CntProgSt]	651	1			T11	14		T46	7		T44	9
auto[1]	auto[TransCheckSt]	93	1			T11	2		T46	3		T44	2
auto[1]	auto[TokenHashSt]	513	1			T11	7		T46	14		T44	18
auto[1]	auto[FlashRmaSt]	68	1			T11	2		T46	1		T44	3
auto[1]	auto[TokenCheck0St]	19	1			T58	2		T61	1		T235	1
auto[1]	auto[TokenCheck1St]	96	1			T11	4		T46	2		T44	3
auto[1]	auto[TransProgSt]	463	1			T11	14		T46	6		T44	3
auto[1]	auto[PostTransSt]	2800	1			T1	3		T2	7		T11	2
auto[1]	auto[ScrapSt]	50	1			T11	2		T46	2		T44	1
auto[1]	auto[EscalateSt]	1407770	1			T1	782		T2	686		T3	392
auto[1]	auto[InvalidSt]	6949	1			T1	5		T3	4		T4	1

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7198734	1			T1	12519		T2	9593		T3	1676
auto[0]	auto[IdleSt]	22030221	1			T1	120776		T2	11632		T3	1258
auto[0]	auto[ClkMuxSt]	36156	1			T1	119		T2	100		T3	5
auto[0]	auto[CntIncrSt]	35871	1			T1	119		T2	100		T3	5
auto[0]	auto[CntProgSt]	1445323	1			T1	1615		T2	172		T3	486
auto[0]	auto[TransCheckSt]	27944	1			T1	93		T2	81		T3	5
auto[0]	auto[TokenHashSt]	45502436	1			T1	2695		T2	732		T3	536
auto[0]	auto[FlashRmaSt]	28962	1			T1	76		T2	19		T3	5
auto[0]	auto[TokenCheck0St]	12850	1			T1	45		T2	19		T3	5
auto[0]	auto[TokenCheck1St]	9478	1			T1	32		T2	14		T3	5
auto[0]	auto[TransProgSt]	360872	1			T1	536		T2	23		T3	488
auto[0]	auto[PostTransSt]	12977368	1			T1	95941		T2	18104		T3	1233
auto[0]	auto[ScrapSt]	267877	1			T11	5		T46	4		T5	830
auto[0]	auto[EscalateSt]	4935036	1			T1	12094		T2	1189		T3	994
auto[0]	auto[InvalidSt]	10114775	1			T1	5630		T3	553		T4	4488
auto[1]	auto[ResetSt]	164	1			T11	3		T46	5		T44	3
auto[1]	auto[IdleSt]	149	1			T11	10		T44	5		T58	5
auto[1]	auto[ClkMuxSt]	48	1			T44	4		T58	2		T59	1
auto[1]	auto[CntIncrSt]	49	1			T11	2		T58	2		T36	1
auto[1]	auto[CntProgSt]	621	1			T11	12		T46	4		T44	10
auto[1]	auto[TransCheckSt]	96	1			T11	2		T46	4		T44	6
auto[1]	auto[TokenHashSt]	479	1			T11	6		T46	15		T44	16
auto[1]	auto[FlashRmaSt]	61	1			T46	2		T44	1		T58	3
auto[1]	auto[TokenCheck0St]	16	1			T37	1		T61	2		T235	1
auto[1]	auto[TokenCheck1St]	87	1			T11	2		T46	2		T44	4
auto[1]	auto[TransProgSt]	471	1			T11	12		T46	8		T44	8
auto[1]	auto[PostTransSt]	2559	1			T1	13		T2	4		T11	2
auto[1]	auto[ScrapSt]	53	1			T11	1		T46	2		T44	1
auto[1]	auto[EscalateSt]	1365580	1			T1	1659		T2	392		T4	194
auto[1]	auto[InvalidSt]	6906	1			T1	4		T4	2		T16	31