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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.20 97.89 95.59 93.31 100.00 98.55 98.76 96.29


Total test records in report: 999
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T815 /workspace/coverage/default/15.lc_ctrl_stress_all_with_rand_reset.1600921884 Jun 06 01:11:38 PM PDT 24 Jun 06 01:17:27 PM PDT 24 137116899464 ps
T816 /workspace/coverage/default/5.lc_ctrl_jtag_priority.3709265182 Jun 06 01:10:11 PM PDT 24 Jun 06 01:10:14 PM PDT 24 452070358 ps
T817 /workspace/coverage/default/14.lc_ctrl_prog_failure.697238857 Jun 06 01:11:27 PM PDT 24 Jun 06 01:11:30 PM PDT 24 177048312 ps
T818 /workspace/coverage/default/25.lc_ctrl_jtag_access.1365942338 Jun 06 01:12:20 PM PDT 24 Jun 06 01:12:24 PM PDT 24 475879460 ps
T819 /workspace/coverage/default/18.lc_ctrl_errors.1062977724 Jun 06 01:11:50 PM PDT 24 Jun 06 01:12:02 PM PDT 24 1457755555 ps
T820 /workspace/coverage/default/17.lc_ctrl_jtag_access.245474550 Jun 06 01:11:49 PM PDT 24 Jun 06 01:11:55 PM PDT 24 211771635 ps
T821 /workspace/coverage/default/9.lc_ctrl_state_failure.1693702996 Jun 06 01:10:49 PM PDT 24 Jun 06 01:11:23 PM PDT 24 1710134043 ps
T822 /workspace/coverage/default/41.lc_ctrl_sec_mubi.914215363 Jun 06 01:13:30 PM PDT 24 Jun 06 01:13:47 PM PDT 24 6679950062 ps
T823 /workspace/coverage/default/8.lc_ctrl_jtag_errors.1706270240 Jun 06 01:10:41 PM PDT 24 Jun 06 01:11:14 PM PDT 24 25360339817 ps
T824 /workspace/coverage/default/48.lc_ctrl_sec_token_mux.1007981778 Jun 06 01:13:54 PM PDT 24 Jun 06 01:14:03 PM PDT 24 311118625 ps
T56 /workspace/coverage/default/10.lc_ctrl_jtag_errors.1589013918 Jun 06 01:10:59 PM PDT 24 Jun 06 01:12:52 PM PDT 24 4127315251 ps
T825 /workspace/coverage/default/33.lc_ctrl_sec_token_mux.2240576904 Jun 06 01:12:54 PM PDT 24 Jun 06 01:13:01 PM PDT 24 809320384 ps
T826 /workspace/coverage/default/16.lc_ctrl_jtag_smoke.479212145 Jun 06 01:11:48 PM PDT 24 Jun 06 01:11:57 PM PDT 24 363630187 ps
T827 /workspace/coverage/default/32.lc_ctrl_sec_token_digest.165659364 Jun 06 01:12:56 PM PDT 24 Jun 06 01:13:09 PM PDT 24 516455023 ps
T828 /workspace/coverage/default/29.lc_ctrl_prog_failure.1534864196 Jun 06 01:12:36 PM PDT 24 Jun 06 01:12:40 PM PDT 24 1142023992 ps
T829 /workspace/coverage/default/8.lc_ctrl_jtag_priority.3759883076 Jun 06 01:10:41 PM PDT 24 Jun 06 01:10:50 PM PDT 24 327345241 ps
T830 /workspace/coverage/default/8.lc_ctrl_jtag_state_failure.292449798 Jun 06 01:10:40 PM PDT 24 Jun 06 01:11:52 PM PDT 24 1566842789 ps
T831 /workspace/coverage/default/23.lc_ctrl_stress_all.2996213299 Jun 06 01:12:17 PM PDT 24 Jun 06 01:14:05 PM PDT 24 24843072950 ps
T832 /workspace/coverage/default/9.lc_ctrl_state_post_trans.721576653 Jun 06 01:10:50 PM PDT 24 Jun 06 01:10:55 PM PDT 24 259154958 ps
T833 /workspace/coverage/default/18.lc_ctrl_sec_token_mux.1971974322 Jun 06 01:11:52 PM PDT 24 Jun 06 01:12:06 PM PDT 24 1544183116 ps
T834 /workspace/coverage/default/37.lc_ctrl_sec_token_mux.4176527058 Jun 06 01:13:14 PM PDT 24 Jun 06 01:13:22 PM PDT 24 317190179 ps
T835 /workspace/coverage/default/33.lc_ctrl_stress_all.456243290 Jun 06 01:12:53 PM PDT 24 Jun 06 01:14:42 PM PDT 24 14487064292 ps
T836 /workspace/coverage/default/43.lc_ctrl_smoke.3583763657 Jun 06 01:13:37 PM PDT 24 Jun 06 01:13:40 PM PDT 24 58755072 ps
T837 /workspace/coverage/default/15.lc_ctrl_sec_token_mux.1159221654 Jun 06 01:11:37 PM PDT 24 Jun 06 01:11:50 PM PDT 24 1340593482 ps
T838 /workspace/coverage/default/6.lc_ctrl_sec_token_mux.2841376427 Jun 06 01:10:33 PM PDT 24 Jun 06 01:10:40 PM PDT 24 908298133 ps
T839 /workspace/coverage/default/40.lc_ctrl_smoke.3591665882 Jun 06 01:13:22 PM PDT 24 Jun 06 01:13:25 PM PDT 24 62848509 ps
T840 /workspace/coverage/default/33.lc_ctrl_jtag_access.35827575 Jun 06 01:12:55 PM PDT 24 Jun 06 01:12:59 PM PDT 24 150791042 ps
T841 /workspace/coverage/default/30.lc_ctrl_alert_test.207355773 Jun 06 01:12:49 PM PDT 24 Jun 06 01:12:51 PM PDT 24 19557238 ps
T842 /workspace/coverage/default/11.lc_ctrl_errors.1028639752 Jun 06 01:11:09 PM PDT 24 Jun 06 01:11:20 PM PDT 24 2028447560 ps
T843 /workspace/coverage/default/10.lc_ctrl_sec_token_digest.3097872731 Jun 06 01:11:01 PM PDT 24 Jun 06 01:11:10 PM PDT 24 1229159353 ps
T844 /workspace/coverage/default/30.lc_ctrl_sec_mubi.204642768 Jun 06 01:12:43 PM PDT 24 Jun 06 01:13:01 PM PDT 24 1524003414 ps
T845 /workspace/coverage/default/0.lc_ctrl_alert_test.2043793846 Jun 06 01:09:21 PM PDT 24 Jun 06 01:09:24 PM PDT 24 17081192 ps
T846 /workspace/coverage/default/14.lc_ctrl_volatile_unlock_smoke.421583834 Jun 06 01:11:27 PM PDT 24 Jun 06 01:11:29 PM PDT 24 15614767 ps
T847 /workspace/coverage/default/21.lc_ctrl_alert_test.989595738 Jun 06 01:12:12 PM PDT 24 Jun 06 01:12:15 PM PDT 24 20244622 ps
T848 /workspace/coverage/default/42.lc_ctrl_state_failure.2151635658 Jun 06 01:13:36 PM PDT 24 Jun 06 01:14:09 PM PDT 24 689754551 ps
T849 /workspace/coverage/default/46.lc_ctrl_prog_failure.1371754000 Jun 06 01:13:52 PM PDT 24 Jun 06 01:13:56 PM PDT 24 88716539 ps
T111 /workspace/coverage/default/1.lc_ctrl_sec_cm.3426458710 Jun 06 01:09:31 PM PDT 24 Jun 06 01:10:11 PM PDT 24 652400129 ps
T850 /workspace/coverage/default/16.lc_ctrl_security_escalation.3770955779 Jun 06 01:11:41 PM PDT 24 Jun 06 01:11:50 PM PDT 24 479690761 ps
T851 /workspace/coverage/default/17.lc_ctrl_state_post_trans.1270034159 Jun 06 01:11:36 PM PDT 24 Jun 06 01:11:45 PM PDT 24 77839466 ps
T852 /workspace/coverage/default/40.lc_ctrl_sec_token_digest.2435529772 Jun 06 01:13:23 PM PDT 24 Jun 06 01:13:34 PM PDT 24 642356884 ps
T853 /workspace/coverage/default/10.lc_ctrl_state_post_trans.4241490687 Jun 06 01:11:01 PM PDT 24 Jun 06 01:11:10 PM PDT 24 303265107 ps
T854 /workspace/coverage/default/38.lc_ctrl_smoke.216686920 Jun 06 01:13:14 PM PDT 24 Jun 06 01:13:18 PM PDT 24 41268489 ps
T855 /workspace/coverage/default/47.lc_ctrl_sec_mubi.2570700615 Jun 06 01:13:56 PM PDT 24 Jun 06 01:14:11 PM PDT 24 389945667 ps
T856 /workspace/coverage/default/10.lc_ctrl_errors.112847371 Jun 06 01:11:00 PM PDT 24 Jun 06 01:11:13 PM PDT 24 1609002822 ps
T857 /workspace/coverage/default/23.lc_ctrl_state_post_trans.2989267951 Jun 06 01:12:09 PM PDT 24 Jun 06 01:12:20 PM PDT 24 1007202020 ps
T858 /workspace/coverage/default/47.lc_ctrl_jtag_access.627741241 Jun 06 01:13:55 PM PDT 24 Jun 06 01:14:03 PM PDT 24 1058074581 ps
T859 /workspace/coverage/default/37.lc_ctrl_sec_mubi.1783415879 Jun 06 01:13:13 PM PDT 24 Jun 06 01:13:29 PM PDT 24 915835088 ps
T860 /workspace/coverage/default/21.lc_ctrl_errors.3611429270 Jun 06 01:12:10 PM PDT 24 Jun 06 01:12:24 PM PDT 24 1483225504 ps
T861 /workspace/coverage/default/44.lc_ctrl_volatile_unlock_smoke.324149469 Jun 06 01:13:43 PM PDT 24 Jun 06 01:13:46 PM PDT 24 37452781 ps
T862 /workspace/coverage/default/4.lc_ctrl_jtag_access.2338191140 Jun 06 01:10:11 PM PDT 24 Jun 06 01:10:18 PM PDT 24 452883559 ps
T863 /workspace/coverage/default/4.lc_ctrl_jtag_state_failure.1224313031 Jun 06 01:10:04 PM PDT 24 Jun 06 01:10:43 PM PDT 24 858807135 ps
T864 /workspace/coverage/default/42.lc_ctrl_sec_token_mux.1830862588 Jun 06 01:13:30 PM PDT 24 Jun 06 01:13:39 PM PDT 24 706584375 ps
T865 /workspace/coverage/default/37.lc_ctrl_state_post_trans.4107293432 Jun 06 01:13:13 PM PDT 24 Jun 06 01:13:22 PM PDT 24 102248905 ps
T866 /workspace/coverage/default/12.lc_ctrl_jtag_state_post_trans.2138757663 Jun 06 01:11:11 PM PDT 24 Jun 06 01:11:33 PM PDT 24 545787226 ps
T867 /workspace/coverage/default/29.lc_ctrl_security_escalation.2679145624 Jun 06 01:12:44 PM PDT 24 Jun 06 01:12:54 PM PDT 24 2584821858 ps
T868 /workspace/coverage/default/3.lc_ctrl_jtag_access.532555765 Jun 06 01:09:54 PM PDT 24 Jun 06 01:10:02 PM PDT 24 2528987431 ps
T869 /workspace/coverage/default/39.lc_ctrl_sec_token_digest.4132298729 Jun 06 01:13:23 PM PDT 24 Jun 06 01:13:39 PM PDT 24 2657377673 ps
T870 /workspace/coverage/default/23.lc_ctrl_sec_token_digest.3816507025 Jun 06 01:12:16 PM PDT 24 Jun 06 01:12:31 PM PDT 24 1596730707 ps
T871 /workspace/coverage/default/37.lc_ctrl_smoke.2883867358 Jun 06 01:13:14 PM PDT 24 Jun 06 01:13:17 PM PDT 24 132498485 ps
T872 /workspace/coverage/default/41.lc_ctrl_state_failure.1328011865 Jun 06 01:13:27 PM PDT 24 Jun 06 01:13:48 PM PDT 24 667072679 ps
T873 /workspace/coverage/default/7.lc_ctrl_sec_token_mux.473193820 Jun 06 01:10:42 PM PDT 24 Jun 06 01:10:53 PM PDT 24 1586751702 ps
T874 /workspace/coverage/default/14.lc_ctrl_stress_all.597089052 Jun 06 01:11:28 PM PDT 24 Jun 06 01:11:43 PM PDT 24 1304642155 ps
T875 /workspace/coverage/default/37.lc_ctrl_jtag_access.3435970302 Jun 06 01:13:14 PM PDT 24 Jun 06 01:13:21 PM PDT 24 1753880918 ps
T876 /workspace/coverage/default/12.lc_ctrl_volatile_unlock_smoke.2308237935 Jun 06 01:11:10 PM PDT 24 Jun 06 01:11:12 PM PDT 24 19994632 ps
T124 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.856109270 Jun 06 02:31:25 PM PDT 24 Jun 06 02:31:34 PM PDT 24 128573688 ps
T125 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.3578040640 Jun 06 02:31:33 PM PDT 24 Jun 06 02:31:40 PM PDT 24 66329423 ps
T137 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.276025595 Jun 06 02:31:25 PM PDT 24 Jun 06 02:31:31 PM PDT 24 48139275 ps
T132 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.373063331 Jun 06 02:31:09 PM PDT 24 Jun 06 02:31:15 PM PDT 24 38175032 ps
T133 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.744109312 Jun 06 02:30:55 PM PDT 24 Jun 06 02:30:57 PM PDT 24 15089102 ps
T134 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.1324777620 Jun 06 02:31:08 PM PDT 24 Jun 06 02:31:16 PM PDT 24 373037513 ps
T225 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.3997603096 Jun 06 02:31:12 PM PDT 24 Jun 06 02:31:20 PM PDT 24 45979776 ps
T127 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.3740870084 Jun 06 02:31:33 PM PDT 24 Jun 06 02:31:39 PM PDT 24 19869462 ps
T169 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.2008176702 Jun 06 02:31:15 PM PDT 24 Jun 06 02:31:25 PM PDT 24 574518543 ps
T161 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3294440086 Jun 06 02:31:12 PM PDT 24 Jun 06 02:31:21 PM PDT 24 136423444 ps
T162 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.697244801 Jun 06 02:31:10 PM PDT 24 Jun 06 02:31:16 PM PDT 24 59167208 ps
T877 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.3413307627 Jun 06 02:31:09 PM PDT 24 Jun 06 02:31:16 PM PDT 24 120717802 ps
T212 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.1959523642 Jun 06 02:31:14 PM PDT 24 Jun 06 02:31:22 PM PDT 24 20441254 ps
T159 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.3727077110 Jun 06 02:31:07 PM PDT 24 Jun 06 02:31:13 PM PDT 24 113007847 ps
T226 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.1368491396 Jun 06 02:31:13 PM PDT 24 Jun 06 02:31:26 PM PDT 24 7817830057 ps
T126 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.607918447 Jun 06 02:31:42 PM PDT 24 Jun 06 02:31:48 PM PDT 24 26539412 ps
T128 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.1383377578 Jun 06 02:31:32 PM PDT 24 Jun 06 02:31:39 PM PDT 24 150645332 ps
T878 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.411783704 Jun 06 02:31:25 PM PDT 24 Jun 06 02:31:32 PM PDT 24 39136303 ps
T170 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.834061217 Jun 06 02:31:08 PM PDT 24 Jun 06 02:31:13 PM PDT 24 161437892 ps
T213 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.1753197423 Jun 06 02:31:09 PM PDT 24 Jun 06 02:31:14 PM PDT 24 76625813 ps
T160 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.944061561 Jun 06 02:31:38 PM PDT 24 Jun 06 02:31:48 PM PDT 24 924026394 ps
T171 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.1398910109 Jun 06 02:31:31 PM PDT 24 Jun 06 02:31:37 PM PDT 24 69418111 ps
T203 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.3221903004 Jun 06 02:31:14 PM PDT 24 Jun 06 02:31:22 PM PDT 24 16680174 ps
T129 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.2903251495 Jun 06 02:31:09 PM PDT 24 Jun 06 02:31:16 PM PDT 24 291597325 ps
T204 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.2324757052 Jun 06 02:31:16 PM PDT 24 Jun 06 02:31:25 PM PDT 24 13903936 ps
T879 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.1348869355 Jun 06 02:31:15 PM PDT 24 Jun 06 02:31:24 PM PDT 24 274256123 ps
T130 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.1822032421 Jun 06 02:31:17 PM PDT 24 Jun 06 02:31:27 PM PDT 24 349108730 ps
T880 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.807898825 Jun 06 02:31:13 PM PDT 24 Jun 06 02:31:21 PM PDT 24 296173588 ps
T151 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.2889821600 Jun 06 02:31:16 PM PDT 24 Jun 06 02:31:26 PM PDT 24 119107540 ps
T146 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.3807311269 Jun 06 02:31:12 PM PDT 24 Jun 06 02:31:21 PM PDT 24 54244604 ps
T881 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.189129127 Jun 06 02:31:10 PM PDT 24 Jun 06 02:31:16 PM PDT 24 198966879 ps
T882 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.967380600 Jun 06 02:31:08 PM PDT 24 Jun 06 02:31:13 PM PDT 24 127616841 ps
T883 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.2731872940 Jun 06 02:31:15 PM PDT 24 Jun 06 02:31:25 PM PDT 24 87007479 ps
T884 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.2770932624 Jun 06 02:31:10 PM PDT 24 Jun 06 02:31:21 PM PDT 24 2437633360 ps
T885 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.3374107881 Jun 06 02:31:04 PM PDT 24 Jun 06 02:31:15 PM PDT 24 10762554488 ps
T886 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.173524694 Jun 06 02:31:09 PM PDT 24 Jun 06 02:31:16 PM PDT 24 136178634 ps
T887 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.1094272254 Jun 06 02:31:16 PM PDT 24 Jun 06 02:31:25 PM PDT 24 53936262 ps
T888 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.2222953725 Jun 06 02:31:11 PM PDT 24 Jun 06 02:31:17 PM PDT 24 173151455 ps
T131 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.3934927036 Jun 06 02:31:17 PM PDT 24 Jun 06 02:31:27 PM PDT 24 58821093 ps
T214 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.2982299870 Jun 06 02:31:06 PM PDT 24 Jun 06 02:31:10 PM PDT 24 71428839 ps
T205 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.1513405924 Jun 06 02:31:14 PM PDT 24 Jun 06 02:31:23 PM PDT 24 20620348 ps
T889 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.410236954 Jun 06 02:31:15 PM PDT 24 Jun 06 02:31:37 PM PDT 24 1247738611 ps
T890 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.3740703661 Jun 06 02:31:13 PM PDT 24 Jun 06 02:31:22 PM PDT 24 180379830 ps
T215 /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.430337238 Jun 06 02:31:33 PM PDT 24 Jun 06 02:31:39 PM PDT 24 56258224 ps
T141 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.939955750 Jun 06 02:31:31 PM PDT 24 Jun 06 02:31:37 PM PDT 24 338559019 ps
T891 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.3915747646 Jun 06 02:31:10 PM PDT 24 Jun 06 02:31:17 PM PDT 24 291962555 ps
T892 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.1094540168 Jun 06 02:31:07 PM PDT 24 Jun 06 02:31:13 PM PDT 24 219092760 ps
T136 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.2093296049 Jun 06 02:31:25 PM PDT 24 Jun 06 02:31:33 PM PDT 24 24424067 ps
T893 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2193066891 Jun 06 02:31:21 PM PDT 24 Jun 06 02:31:30 PM PDT 24 67191881 ps
T894 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.1042256092 Jun 06 02:31:10 PM PDT 24 Jun 06 02:31:17 PM PDT 24 197278067 ps
T895 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.3585590066 Jun 06 02:31:03 PM PDT 24 Jun 06 02:31:07 PM PDT 24 176407193 ps
T896 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.3289196003 Jun 06 02:31:04 PM PDT 24 Jun 06 02:31:08 PM PDT 24 15787065 ps
T897 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3839944727 Jun 06 02:31:12 PM PDT 24 Jun 06 02:31:24 PM PDT 24 116986798 ps
T898 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.1502231394 Jun 06 02:31:14 PM PDT 24 Jun 06 02:31:23 PM PDT 24 48992756 ps
T899 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.3388943869 Jun 06 02:31:05 PM PDT 24 Jun 06 02:31:08 PM PDT 24 60126330 ps
T900 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.1765033027 Jun 06 02:31:11 PM PDT 24 Jun 06 02:31:20 PM PDT 24 127375875 ps
T901 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.1465152223 Jun 06 02:31:24 PM PDT 24 Jun 06 02:31:32 PM PDT 24 41032826 ps
T902 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.360356542 Jun 06 02:31:12 PM PDT 24 Jun 06 02:31:23 PM PDT 24 186313389 ps
T216 /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.2942100963 Jun 06 02:31:25 PM PDT 24 Jun 06 02:31:33 PM PDT 24 22542111 ps
T147 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.2994259917 Jun 06 02:31:38 PM PDT 24 Jun 06 02:31:44 PM PDT 24 101008694 ps
T217 /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.1216083852 Jun 06 02:31:29 PM PDT 24 Jun 06 02:31:36 PM PDT 24 42802827 ps
T903 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.968413690 Jun 06 02:31:36 PM PDT 24 Jun 06 02:31:42 PM PDT 24 69613550 ps
T158 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.2951616514 Jun 06 02:31:04 PM PDT 24 Jun 06 02:31:09 PM PDT 24 85955764 ps
T144 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.3165809346 Jun 06 02:31:09 PM PDT 24 Jun 06 02:31:16 PM PDT 24 42318237 ps
T904 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.3194548841 Jun 06 02:31:03 PM PDT 24 Jun 06 02:31:06 PM PDT 24 235906500 ps
T905 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.1959470561 Jun 06 02:31:15 PM PDT 24 Jun 06 02:31:46 PM PDT 24 2326352652 ps
T218 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.3288102199 Jun 06 02:31:23 PM PDT 24 Jun 06 02:31:31 PM PDT 24 29573663 ps
T219 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.4096103379 Jun 06 02:31:27 PM PDT 24 Jun 06 02:31:34 PM PDT 24 14012038 ps
T906 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.1340871404 Jun 06 02:31:18 PM PDT 24 Jun 06 02:31:26 PM PDT 24 12226672 ps
T220 /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.547843611 Jun 06 02:31:32 PM PDT 24 Jun 06 02:31:38 PM PDT 24 73996948 ps
T907 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.3445594401 Jun 06 02:31:15 PM PDT 24 Jun 06 02:31:29 PM PDT 24 624950048 ps
T908 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.3422712728 Jun 06 02:31:29 PM PDT 24 Jun 06 02:31:35 PM PDT 24 22646135 ps
T148 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.2060321453 Jun 06 02:31:07 PM PDT 24 Jun 06 02:31:13 PM PDT 24 110580097 ps
T909 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.3309052474 Jun 06 02:31:09 PM PDT 24 Jun 06 02:31:26 PM PDT 24 525814197 ps
T221 /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.1730531756 Jun 06 02:31:12 PM PDT 24 Jun 06 02:31:20 PM PDT 24 141261237 ps
T142 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.2311360152 Jun 06 02:31:13 PM PDT 24 Jun 06 02:31:22 PM PDT 24 59430486 ps
T910 /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.380932096 Jun 06 02:31:28 PM PDT 24 Jun 06 02:31:35 PM PDT 24 154084600 ps
T911 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.1175094979 Jun 06 02:31:06 PM PDT 24 Jun 06 02:31:10 PM PDT 24 68550985 ps
T912 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.3187515969 Jun 06 02:31:29 PM PDT 24 Jun 06 02:31:35 PM PDT 24 21834211 ps
T913 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.3473057766 Jun 06 02:31:15 PM PDT 24 Jun 06 02:31:25 PM PDT 24 23326890 ps
T914 /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.3403776425 Jun 06 02:31:32 PM PDT 24 Jun 06 02:31:38 PM PDT 24 159802627 ps
T915 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.1933677811 Jun 06 02:31:14 PM PDT 24 Jun 06 02:31:23 PM PDT 24 35237896 ps
T916 /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.3862012043 Jun 06 02:30:55 PM PDT 24 Jun 06 02:30:58 PM PDT 24 26308914 ps
T917 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.3379344871 Jun 06 02:31:13 PM PDT 24 Jun 06 02:31:22 PM PDT 24 123774024 ps
T918 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.2761078664 Jun 06 02:30:59 PM PDT 24 Jun 06 02:31:04 PM PDT 24 79094623 ps
T140 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.317646792 Jun 06 02:31:14 PM PDT 24 Jun 06 02:31:25 PM PDT 24 122318215 ps
T919 /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.1792912681 Jun 06 02:31:20 PM PDT 24 Jun 06 02:31:28 PM PDT 24 78634119 ps
T920 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.16608883 Jun 06 02:30:57 PM PDT 24 Jun 06 02:31:03 PM PDT 24 378364407 ps
T921 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.2841315411 Jun 06 02:31:21 PM PDT 24 Jun 06 02:31:30 PM PDT 24 151208400 ps
T155 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.2006010707 Jun 06 02:31:24 PM PDT 24 Jun 06 02:31:33 PM PDT 24 59553610 ps
T922 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.2446166702 Jun 06 02:31:33 PM PDT 24 Jun 06 02:31:40 PM PDT 24 40954234 ps
T923 /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.229246873 Jun 06 02:30:55 PM PDT 24 Jun 06 02:30:58 PM PDT 24 45092413 ps
T924 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.3520575217 Jun 06 02:31:07 PM PDT 24 Jun 06 02:31:13 PM PDT 24 37216827 ps
T925 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.1659114117 Jun 06 02:31:12 PM PDT 24 Jun 06 02:31:21 PM PDT 24 99768526 ps
T926 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.2127883986 Jun 06 02:31:14 PM PDT 24 Jun 06 02:31:23 PM PDT 24 28461384 ps
T927 /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.3642453006 Jun 06 02:31:27 PM PDT 24 Jun 06 02:31:34 PM PDT 24 246362046 ps
T154 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.62250060 Jun 06 02:31:07 PM PDT 24 Jun 06 02:31:14 PM PDT 24 210073790 ps
T928 /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.2163009060 Jun 06 02:31:32 PM PDT 24 Jun 06 02:31:38 PM PDT 24 91476529 ps
T929 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.199294790 Jun 06 02:31:33 PM PDT 24 Jun 06 02:31:41 PM PDT 24 126720188 ps
T156 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.232269139 Jun 06 02:31:14 PM PDT 24 Jun 06 02:31:24 PM PDT 24 164397901 ps
T930 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.1305112141 Jun 06 02:31:06 PM PDT 24 Jun 06 02:31:09 PM PDT 24 24486103 ps
T931 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.2231222900 Jun 06 02:31:17 PM PDT 24 Jun 06 02:31:26 PM PDT 24 171694570 ps
T206 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.2787685135 Jun 06 02:31:07 PM PDT 24 Jun 06 02:31:11 PM PDT 24 14266695 ps
T207 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.2039972708 Jun 06 02:31:21 PM PDT 24 Jun 06 02:31:29 PM PDT 24 63105621 ps
T932 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.2233997202 Jun 06 02:31:11 PM PDT 24 Jun 06 02:31:19 PM PDT 24 867934018 ps
T933 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.1846096761 Jun 06 02:31:46 PM PDT 24 Jun 06 02:31:52 PM PDT 24 27023947 ps
T934 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2380884144 Jun 06 02:31:08 PM PDT 24 Jun 06 02:31:14 PM PDT 24 313011093 ps
T935 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.3662574392 Jun 06 02:31:14 PM PDT 24 Jun 06 02:31:24 PM PDT 24 272470932 ps
T936 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.1232468808 Jun 06 02:31:07 PM PDT 24 Jun 06 02:31:12 PM PDT 24 190637427 ps
T937 /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.2984452241 Jun 06 02:31:14 PM PDT 24 Jun 06 02:31:23 PM PDT 24 138765857 ps
T938 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.1913124392 Jun 06 02:31:15 PM PDT 24 Jun 06 02:31:24 PM PDT 24 391374883 ps
T939 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.1704341024 Jun 06 02:31:08 PM PDT 24 Jun 06 02:31:13 PM PDT 24 37170359 ps
T940 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1815792943 Jun 06 02:31:07 PM PDT 24 Jun 06 02:31:13 PM PDT 24 253186514 ps
T941 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.495693179 Jun 06 02:30:58 PM PDT 24 Jun 06 02:31:03 PM PDT 24 104090860 ps
T942 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.2595747535 Jun 06 02:31:17 PM PDT 24 Jun 06 02:31:28 PM PDT 24 48361018 ps
T943 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.975907873 Jun 06 02:31:13 PM PDT 24 Jun 06 02:31:22 PM PDT 24 198700446 ps
T944 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.2159661002 Jun 06 02:31:16 PM PDT 24 Jun 06 02:31:27 PM PDT 24 52996220 ps
T945 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.1976681739 Jun 06 02:31:14 PM PDT 24 Jun 06 02:31:22 PM PDT 24 18338267 ps
T946 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.3040295879 Jun 06 02:31:06 PM PDT 24 Jun 06 02:31:09 PM PDT 24 74850642 ps
T947 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.622405317 Jun 06 02:31:12 PM PDT 24 Jun 06 02:31:19 PM PDT 24 118073939 ps
T948 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.2145380419 Jun 06 02:31:08 PM PDT 24 Jun 06 02:31:13 PM PDT 24 20924327 ps
T949 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.4170382744 Jun 06 02:31:07 PM PDT 24 Jun 06 02:31:12 PM PDT 24 160735766 ps
T950 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.4142909143 Jun 06 02:31:01 PM PDT 24 Jun 06 02:31:06 PM PDT 24 85186990 ps
T951 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.1969564707 Jun 06 02:31:13 PM PDT 24 Jun 06 02:31:29 PM PDT 24 1775976680 ps
T952 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.1741278876 Jun 06 02:31:08 PM PDT 24 Jun 06 02:31:33 PM PDT 24 3730392835 ps
T953 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.3807572310 Jun 06 02:31:13 PM PDT 24 Jun 06 02:32:06 PM PDT 24 2196884515 ps
T145 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.2929849081 Jun 06 02:31:17 PM PDT 24 Jun 06 02:31:27 PM PDT 24 139433431 ps
T954 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.287418321 Jun 06 02:31:11 PM PDT 24 Jun 06 02:31:19 PM PDT 24 47204567 ps
T152 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.3308007506 Jun 06 02:31:23 PM PDT 24 Jun 06 02:31:32 PM PDT 24 251426109 ps
T955 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.2606050689 Jun 06 02:31:09 PM PDT 24 Jun 06 02:31:16 PM PDT 24 47016345 ps
T208 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.540784917 Jun 06 02:30:55 PM PDT 24 Jun 06 02:30:57 PM PDT 24 38079470 ps
T956 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.4242292413 Jun 06 02:31:15 PM PDT 24 Jun 06 02:31:23 PM PDT 24 93718024 ps
T957 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.152880329 Jun 06 02:30:54 PM PDT 24 Jun 06 02:31:08 PM PDT 24 2759323534 ps
T958 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.1817250467 Jun 06 02:31:43 PM PDT 24 Jun 06 02:31:50 PM PDT 24 32938571 ps
T959 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.1746230491 Jun 06 02:31:05 PM PDT 24 Jun 06 02:31:39 PM PDT 24 4705518023 ps
T960 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.1687490710 Jun 06 02:31:05 PM PDT 24 Jun 06 02:31:11 PM PDT 24 621727856 ps
T961 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.36144587 Jun 06 02:30:58 PM PDT 24 Jun 06 02:31:02 PM PDT 24 12037856 ps
T962 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.2318390664 Jun 06 02:31:05 PM PDT 24 Jun 06 02:31:10 PM PDT 24 513309313 ps
T143 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.1840234494 Jun 06 02:31:14 PM PDT 24 Jun 06 02:31:25 PM PDT 24 101229838 ps
T963 /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.1993915775 Jun 06 02:31:14 PM PDT 24 Jun 06 02:31:22 PM PDT 24 84550680 ps
T964 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.3548714837 Jun 06 02:30:58 PM PDT 24 Jun 06 02:31:03 PM PDT 24 120550814 ps
T965 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.225534151 Jun 06 02:31:42 PM PDT 24 Jun 06 02:31:48 PM PDT 24 75965765 ps
T966 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.2127210634 Jun 06 02:31:11 PM PDT 24 Jun 06 02:31:19 PM PDT 24 442067971 ps
T967 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.1243409340 Jun 06 02:31:09 PM PDT 24 Jun 06 02:31:15 PM PDT 24 103685440 ps
T968 /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.2738421629 Jun 06 02:31:29 PM PDT 24 Jun 06 02:31:36 PM PDT 24 43963436 ps
T969 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.3383917703 Jun 06 02:31:16 PM PDT 24 Jun 06 02:31:28 PM PDT 24 624338566 ps
T970 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.4156005187 Jun 06 02:31:13 PM PDT 24 Jun 06 02:31:54 PM PDT 24 9061011758 ps
T971 /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.1893063061 Jun 06 02:31:11 PM PDT 24 Jun 06 02:31:17 PM PDT 24 65622787 ps
T972 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.766932802 Jun 06 02:31:10 PM PDT 24 Jun 06 02:31:16 PM PDT 24 15301398 ps
T973 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.1075242573 Jun 06 02:30:55 PM PDT 24 Jun 06 02:30:57 PM PDT 24 248960763 ps
T153 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.1692201995 Jun 06 02:31:32 PM PDT 24 Jun 06 02:31:40 PM PDT 24 98204518 ps
T974 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.516710430 Jun 06 02:31:36 PM PDT 24 Jun 06 02:31:45 PM PDT 24 206861807 ps
T975 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.244174778 Jun 06 02:31:07 PM PDT 24 Jun 06 02:31:11 PM PDT 24 30032917 ps
T976 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.1105432070 Jun 06 02:31:10 PM PDT 24 Jun 06 02:31:23 PM PDT 24 1458914626 ps
T149 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.4022448218 Jun 06 02:31:20 PM PDT 24 Jun 06 02:31:30 PM PDT 24 90821591 ps
T977 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.1229771279 Jun 06 02:31:08 PM PDT 24 Jun 06 02:31:20 PM PDT 24 365501208 ps
T978 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.2020849519 Jun 06 02:31:15 PM PDT 24 Jun 06 02:31:26 PM PDT 24 118348144 ps
T979 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.3303288868 Jun 06 02:31:35 PM PDT 24 Jun 06 02:31:44 PM PDT 24 112756491 ps
T980 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.1560346219 Jun 06 02:31:15 PM PDT 24 Jun 06 02:31:34 PM PDT 24 1451804719 ps
T981 /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.4147940088 Jun 06 02:31:18 PM PDT 24 Jun 06 02:31:27 PM PDT 24 26307060 ps
T982 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3561539654 Jun 06 02:31:09 PM PDT 24 Jun 06 02:31:16 PM PDT 24 301138634 ps
T150 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.141109802 Jun 06 02:31:44 PM PDT 24 Jun 06 02:31:52 PM PDT 24 146155591 ps
T983 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.1122553834 Jun 06 02:31:06 PM PDT 24 Jun 06 02:31:09 PM PDT 24 23883518 ps
T984 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.958818113 Jun 06 02:31:00 PM PDT 24 Jun 06 02:31:05 PM PDT 24 74099933 ps
T985 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2119196089 Jun 06 02:31:05 PM PDT 24 Jun 06 02:31:10 PM PDT 24 505701081 ps
T986 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.2177842004 Jun 06 02:30:55 PM PDT 24 Jun 06 02:30:58 PM PDT 24 14791419 ps
T987 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.1808765057 Jun 06 02:31:14 PM PDT 24 Jun 06 02:31:49 PM PDT 24 16869973887 ps
T988 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.1024230278 Jun 06 02:31:11 PM PDT 24 Jun 06 02:31:20 PM PDT 24 112349347 ps
T989 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.475199665 Jun 06 02:31:14 PM PDT 24 Jun 06 02:31:24 PM PDT 24 87560484 ps
T990 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.3480698256 Jun 06 02:31:09 PM PDT 24 Jun 06 02:31:15 PM PDT 24 44833277 ps
T138 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.3334261193 Jun 06 02:30:59 PM PDT 24 Jun 06 02:31:05 PM PDT 24 448461662 ps
T209 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.4057719728 Jun 06 02:31:29 PM PDT 24 Jun 06 02:31:35 PM PDT 24 17200262 ps
T991 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.2138726431 Jun 06 02:31:13 PM PDT 24 Jun 06 02:31:23 PM PDT 24 53004747 ps
T139 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.2241582452 Jun 06 02:31:29 PM PDT 24 Jun 06 02:31:36 PM PDT 24 268610023 ps
T210 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.1544991417 Jun 06 02:31:06 PM PDT 24 Jun 06 02:31:10 PM PDT 24 65373412 ps
T157 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.3639080559 Jun 06 02:31:11 PM PDT 24 Jun 06 02:31:18 PM PDT 24 67353129 ps
T992 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.389452889 Jun 06 02:31:15 PM PDT 24 Jun 06 02:31:26 PM PDT 24 86617582 ps
T993 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.1936325202 Jun 06 02:31:13 PM PDT 24 Jun 06 02:31:24 PM PDT 24 481710915 ps
T994 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.3297118837 Jun 06 02:31:14 PM PDT 24 Jun 06 02:31:34 PM PDT 24 806120070 ps
T211 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.1968490223 Jun 06 02:31:21 PM PDT 24 Jun 06 02:31:29 PM PDT 24 51589768 ps
T995 /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.127334493 Jun 06 02:31:12 PM PDT 24 Jun 06 02:31:20 PM PDT 24 302884653 ps
T996 /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.1652076214 Jun 06 02:31:08 PM PDT 24 Jun 06 02:31:13 PM PDT 24 94780213 ps
T997 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.2973751874 Jun 06 02:31:13 PM PDT 24 Jun 06 02:31:22 PM PDT 24 28996883 ps
T998 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.3841596080 Jun 06 02:31:15 PM PDT 24 Jun 06 02:31:25 PM PDT 24 28935919 ps
T999 /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.1425841471 Jun 06 02:31:07 PM PDT 24 Jun 06 02:31:12 PM PDT 24 390629245 ps

Test location /workspace/coverage/default/8.lc_ctrl_stress_all.1475478398
Short name T1
Test name
Test status
Simulation time 5079369215 ps
CPU time 55.84 seconds
Started Jun 06 01:10:47 PM PDT 24
Finished Jun 06 01:11:44 PM PDT 24
Peak memory 259212 kb
Host smart-e92088df-2b69-41c7-ba1c-374958694be2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475478398 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.lc_ctrl_stress_all.1475478398
Directory /workspace/8.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.lc_ctrl_security_escalation.3650863678
Short name T44
Test name
Test status
Simulation time 4941429844 ps
CPU time 13 seconds
Started Jun 06 01:13:20 PM PDT 24
Finished Jun 06 01:13:34 PM PDT 24
Peak memory 226144 kb
Host smart-1c3cfb94-6429-46d0-b86e-a2823657b310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650863678 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_security_escalation.3650863678
Directory /workspace/38.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all_with_rand_reset.1783921638
Short name T62
Test name
Test status
Simulation time 43529530764 ps
CPU time 521.33 seconds
Started Jun 06 01:11:52 PM PDT 24
Finished Jun 06 01:20:36 PM PDT 24
Peak memory 497208 kb
Host smart-47d5b375-be70-41b4-8e05-4a1ad2f5d6bb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1783921638 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_stress_all_with_rand_reset.1783921638
Directory /workspace/17.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_mubi.1640152796
Short name T342
Test name
Test status
Simulation time 1368438918 ps
CPU time 12.2 seconds
Started Jun 06 01:11:50 PM PDT 24
Finished Jun 06 01:12:05 PM PDT 24
Peak memory 225524 kb
Host smart-c7ab37f1-a319-4448-b828-cf55e12e26ea
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640152796 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_mubi.1640152796
Directory /workspace/17.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.944061561
Short name T160
Test name
Test status
Simulation time 924026394 ps
CPU time 6 seconds
Started Jun 06 02:31:38 PM PDT 24
Finished Jun 06 02:31:48 PM PDT 24
Peak memory 219648 kb
Host smart-f50ab369-7046-408e-9bed-e0a94ef73038
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944061
561 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.944061561
Directory /workspace/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all_with_rand_reset.3632423954
Short name T20
Test name
Test status
Simulation time 49544666543 ps
CPU time 409.39 seconds
Started Jun 06 01:13:54 PM PDT 24
Finished Jun 06 01:20:45 PM PDT 24
Peak memory 282276 kb
Host smart-cb12f43b-ef1e-4e44-a384-8266f8b9d665
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3632423954 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_stress_all_with_rand_reset.3632423954
Directory /workspace/46.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.lc_ctrl_volatile_unlock_smoke.172080343
Short name T38
Test name
Test status
Simulation time 14600627 ps
CPU time 1.02 seconds
Started Jun 06 01:13:33 PM PDT 24
Finished Jun 06 01:13:35 PM PDT 24
Peak memory 208660 kb
Host smart-44bea943-bc26-4207-a49d-2c250d5a935a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172080343 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ct
rl_volatile_unlock_smoke.172080343
Directory /workspace/40.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_security_escalation.3475398740
Short name T61
Test name
Test status
Simulation time 899206364 ps
CPU time 8.75 seconds
Started Jun 06 01:12:46 PM PDT 24
Finished Jun 06 01:12:55 PM PDT 24
Peak memory 218008 kb
Host smart-7c5440b5-8ae2-41bf-a9cc-5864399e3302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475398740 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_security_escalation.3475398740
Directory /workspace/30.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_cm.558782039
Short name T60
Test name
Test status
Simulation time 202067682 ps
CPU time 38.32 seconds
Started Jun 06 01:09:55 PM PDT 24
Finished Jun 06 01:10:35 PM PDT 24
Peak memory 268376 kb
Host smart-c785ef64-e90c-4486-936d-7cb7b1ed3150
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558782039 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_cm.558782039
Directory /workspace/3.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_access.3749031819
Short name T26
Test name
Test status
Simulation time 4411410396 ps
CPU time 8.51 seconds
Started Jun 06 01:10:10 PM PDT 24
Finished Jun 06 01:10:20 PM PDT 24
Peak memory 209604 kb
Host smart-32fb0d8e-b5b4-4fbe-8993-7063415d52b9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749031819 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_access.3749031819
Directory /workspace/5.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/17.lc_ctrl_errors.1529860267
Short name T2
Test name
Test status
Simulation time 1757364666 ps
CPU time 19.34 seconds
Started Jun 06 01:11:38 PM PDT 24
Finished Jun 06 01:11:59 PM PDT 24
Peak memory 217972 kb
Host smart-6260cb26-ed25-4b10-80fd-4df1d8cb76d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529860267 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_errors.1529860267
Directory /workspace/17.lc_ctrl_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_security_escalation.115287658
Short name T181
Test name
Test status
Simulation time 1035216725 ps
CPU time 12.44 seconds
Started Jun 06 01:10:46 PM PDT 24
Finished Jun 06 01:10:59 PM PDT 24
Peak memory 217944 kb
Host smart-61fd8fbe-7507-4d0f-989e-f1692b676e9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115287658 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_security_escalation.115287658
Directory /workspace/8.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.2903251495
Short name T129
Test name
Test status
Simulation time 291597325 ps
CPU time 3.3 seconds
Started Jun 06 02:31:09 PM PDT 24
Finished Jun 06 02:31:16 PM PDT 24
Peak memory 222664 kb
Host smart-32ff8284-ca3c-4025-839f-5c0b3e179316
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903251495 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_intg
_err.2903251495
Directory /workspace/10.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/38.lc_ctrl_alert_test.2359221505
Short name T98
Test name
Test status
Simulation time 15822044 ps
CPU time 0.9 seconds
Started Jun 06 01:13:26 PM PDT 24
Finished Jun 06 01:13:28 PM PDT 24
Peak memory 208384 kb
Host smart-dab84298-c377-4248-8f99-ac47a666ae71
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359221505 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_alert_test.2359221505
Directory /workspace/38.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_mux.2545987501
Short name T285
Test name
Test status
Simulation time 576053520 ps
CPU time 7.75 seconds
Started Jun 06 01:11:28 PM PDT 24
Finished Jun 06 01:11:37 PM PDT 24
Peak memory 218012 kb
Host smart-a636f548-f344-49c6-a855-5f3362818d19
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545987501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_mux.
2545987501
Directory /workspace/14.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.607918447
Short name T126
Test name
Test status
Simulation time 26539412 ps
CPU time 2 seconds
Started Jun 06 02:31:42 PM PDT 24
Finished Jun 06 02:31:48 PM PDT 24
Peak memory 220160 kb
Host smart-91af654c-808f-4cad-931a-4a3fb0506440
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607918447 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 19.lc_ctrl_csr_mem_rw_with_rand_reset.607918447
Directory /workspace/19.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.4057719728
Short name T209
Test name
Test status
Simulation time 17200262 ps
CPU time 0.94 seconds
Started Jun 06 02:31:29 PM PDT 24
Finished Jun 06 02:31:35 PM PDT 24
Peak memory 209836 kb
Host smart-27bcd17d-5a55-4b93-9bca-229d69d7fe18
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057719728 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_csr_rw.4057719728
Directory /workspace/18.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_post_trans.578574123
Short name T3
Test name
Test status
Simulation time 315444741 ps
CPU time 7.28 seconds
Started Jun 06 01:13:43 PM PDT 24
Finished Jun 06 01:13:51 PM PDT 24
Peak memory 250896 kb
Host smart-754aab0c-e595-4f77-94a7-8379771d59fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578574123 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_post_trans.578574123
Directory /workspace/44.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.3334261193
Short name T138
Test name
Test status
Simulation time 448461662 ps
CPU time 4 seconds
Started Jun 06 02:30:59 PM PDT 24
Finished Jun 06 02:31:05 PM PDT 24
Peak memory 218284 kb
Host smart-210a8b6a-4414-44f1-a365-e31295ff5b95
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334261193 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_intg_
err.3334261193
Directory /workspace/0.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.2595747535
Short name T942
Test name
Test status
Simulation time 48361018 ps
CPU time 3.49 seconds
Started Jun 06 02:31:17 PM PDT 24
Finished Jun 06 02:31:28 PM PDT 24
Peak memory 219156 kb
Host smart-19311635-fbd0-4da0-bbb7-04dbdcbb5be3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595747535 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_errors.2595747535
Directory /workspace/11.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_failure.2396584627
Short name T18
Test name
Test status
Simulation time 2476413976 ps
CPU time 29.25 seconds
Started Jun 06 01:10:11 PM PDT 24
Finished Jun 06 01:10:42 PM PDT 24
Peak memory 251616 kb
Host smart-473da201-65ae-46f8-b101-985045e137d7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396584627 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jta
g_state_failure.2396584627
Directory /workspace/5.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.1822032421
Short name T130
Test name
Test status
Simulation time 349108730 ps
CPU time 2.55 seconds
Started Jun 06 02:31:17 PM PDT 24
Finished Jun 06 02:31:27 PM PDT 24
Peak memory 222580 kb
Host smart-4f6d7685-6a33-4f7e-a5b9-c11b0ef3b644
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822032421 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_intg
_err.1822032421
Directory /workspace/14.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.141109802
Short name T150
Test name
Test status
Simulation time 146155591 ps
CPU time 3.1 seconds
Started Jun 06 02:31:44 PM PDT 24
Finished Jun 06 02:31:52 PM PDT 24
Peak memory 218136 kb
Host smart-082f3ca4-bc0c-4951-9dd0-89a36a043135
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141109802 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_intg_
err.141109802
Directory /workspace/16.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.1692201995
Short name T153
Test name
Test status
Simulation time 98204518 ps
CPU time 2.76 seconds
Started Jun 06 02:31:32 PM PDT 24
Finished Jun 06 02:31:40 PM PDT 24
Peak memory 218132 kb
Host smart-e33f2083-517f-415b-aea3-6a7c9535705d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692201995 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_intg
_err.1692201995
Directory /workspace/15.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all_with_rand_reset.1102611269
Short name T55
Test name
Test status
Simulation time 29692630533 ps
CPU time 430.26 seconds
Started Jun 06 01:10:32 PM PDT 24
Finished Jun 06 01:17:43 PM PDT 24
Peak memory 294012 kb
Host smart-41b1ec59-fe8f-4cae-a4b2-ea6c76429e2c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1102611269 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_stress_all_with_rand_reset.1102611269
Directory /workspace/6.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.lc_ctrl_stress_all.2771998488
Short name T121
Test name
Test status
Simulation time 12353762820 ps
CPU time 223.61 seconds
Started Jun 06 01:13:52 PM PDT 24
Finished Jun 06 01:17:36 PM PDT 24
Peak memory 281776 kb
Host smart-c2552ba1-e230-4c03-92ff-7ec3a9bb1fa6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771998488 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.lc_ctrl_stress_all.2771998488
Directory /workspace/47.lc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.2982299870
Short name T214
Test name
Test status
Simulation time 71428839 ps
CPU time 1.42 seconds
Started Jun 06 02:31:06 PM PDT 24
Finished Jun 06 02:31:10 PM PDT 24
Peak memory 217920 kb
Host smart-bc4a67bf-5875-4a0f-8e3c-80ee3f6827cc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982299870 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.lc_ctrl_jtag_same_csr_outstanding.2982299870
Directory /workspace/0.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/default/0.lc_ctrl_claim_transition_if.3651172242
Short name T233
Test name
Test status
Simulation time 10435198 ps
CPU time 0.73 seconds
Started Jun 06 01:09:13 PM PDT 24
Finished Jun 06 01:09:15 PM PDT 24
Peak memory 208552 kb
Host smart-acb12393-5fce-46b8-8277-f8234ed2698f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651172242 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_claim_transition_if.3651172242
Directory /workspace/0.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/2.lc_ctrl_claim_transition_if.4101949059
Short name T229
Test name
Test status
Simulation time 11396863 ps
CPU time 0.78 seconds
Started Jun 06 01:09:46 PM PDT 24
Finished Jun 06 01:09:47 PM PDT 24
Peak memory 208500 kb
Host smart-d4a1af49-d37b-445a-94ce-e0522115e141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101949059 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_claim_transition_if.4101949059
Directory /workspace/2.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/4.lc_ctrl_claim_transition_if.3360953586
Short name T230
Test name
Test status
Simulation time 12821399 ps
CPU time 0.92 seconds
Started Jun 06 01:10:01 PM PDT 24
Finished Jun 06 01:10:04 PM PDT 24
Peak memory 208632 kb
Host smart-1b1496cc-cd17-4c0a-9c33-9d18599c97e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3360953586 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_claim_transition_if.3360953586
Directory /workspace/4.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/7.lc_ctrl_claim_transition_if.1787421208
Short name T234
Test name
Test status
Simulation time 10876990 ps
CPU time 0.78 seconds
Started Jun 06 01:10:31 PM PDT 24
Finished Jun 06 01:10:33 PM PDT 24
Peak memory 208524 kb
Host smart-049710f2-206e-4990-bd40-9d183e03b49b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787421208 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_claim_transition_if.1787421208
Directory /workspace/7.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/31.lc_ctrl_prog_failure.156810397
Short name T14
Test name
Test status
Simulation time 529179203 ps
CPU time 2.09 seconds
Started Jun 06 01:12:49 PM PDT 24
Finished Jun 06 01:12:53 PM PDT 24
Peak memory 217924 kb
Host smart-a6d2bb2d-b3a3-4449-83f1-9cfa8f74edf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156810397 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_prog_failure.156810397
Directory /workspace/31.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.232269139
Short name T156
Test name
Test status
Simulation time 164397901 ps
CPU time 2.18 seconds
Started Jun 06 02:31:14 PM PDT 24
Finished Jun 06 02:31:24 PM PDT 24
Peak memory 222680 kb
Host smart-b8a4c4b2-344d-41f2-9188-b1d407c05ba7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232269139 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_intg_e
rr.232269139
Directory /workspace/1.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.3934927036
Short name T131
Test name
Test status
Simulation time 58821093 ps
CPU time 2.11 seconds
Started Jun 06 02:31:17 PM PDT 24
Finished Jun 06 02:31:27 PM PDT 24
Peak memory 222512 kb
Host smart-ff19e0a3-3a15-4c7f-8e13-80e438cf4854
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934927036 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_intg
_err.3934927036
Directory /workspace/11.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.939955750
Short name T141
Test name
Test status
Simulation time 338559019 ps
CPU time 1.86 seconds
Started Jun 06 02:31:31 PM PDT 24
Finished Jun 06 02:31:37 PM PDT 24
Peak memory 222380 kb
Host smart-e278b1a7-59ee-416c-bef9-e341266d534e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939955750 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_intg_
err.939955750
Directory /workspace/12.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.2929849081
Short name T145
Test name
Test status
Simulation time 139433431 ps
CPU time 2.58 seconds
Started Jun 06 02:31:17 PM PDT 24
Finished Jun 06 02:31:27 PM PDT 24
Peak memory 222844 kb
Host smart-2505e43a-274d-48a3-9ef2-6c71668a89be
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929849081 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_intg
_err.2929849081
Directory /workspace/13.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.2006010707
Short name T155
Test name
Test status
Simulation time 59553610 ps
CPU time 2.61 seconds
Started Jun 06 02:31:24 PM PDT 24
Finished Jun 06 02:31:33 PM PDT 24
Peak memory 218132 kb
Host smart-4e714840-abec-42ef-8892-73c5b658ce52
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006010707 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_intg
_err.2006010707
Directory /workspace/19.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.62250060
Short name T154
Test name
Test status
Simulation time 210073790 ps
CPU time 3.22 seconds
Started Jun 06 02:31:07 PM PDT 24
Finished Jun 06 02:31:14 PM PDT 24
Peak memory 222844 kb
Host smart-cc7138d1-b681-45dd-aabd-d76feaffeb1f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62250060 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_intg_er
r.62250060
Directory /workspace/6.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_errors.1589013918
Short name T56
Test name
Test status
Simulation time 4127315251 ps
CPU time 111.52 seconds
Started Jun 06 01:10:59 PM PDT 24
Finished Jun 06 01:12:52 PM PDT 24
Peak memory 218916 kb
Host smart-7d72ec2f-c3e3-469b-8223-0e43fe0d0061
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589013918 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_e
rrors.1589013918
Directory /workspace/10.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_digest.117572976
Short name T93
Test name
Test status
Simulation time 293855043 ps
CPU time 8.16 seconds
Started Jun 06 01:12:46 PM PDT 24
Finished Jun 06 01:12:55 PM PDT 24
Peak memory 217964 kb
Host smart-0e4e779e-acec-4018-9fed-c6d019031d7b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117572976 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_di
gest.117572976
Directory /workspace/29.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/13.lc_ctrl_prog_failure.560210022
Short name T236
Test name
Test status
Simulation time 251720468 ps
CPU time 2.73 seconds
Started Jun 06 01:11:18 PM PDT 24
Finished Jun 06 01:11:22 PM PDT 24
Peak memory 218012 kb
Host smart-9f94bd18-7e24-41ca-aad7-c7b0796dc246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560210022 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_prog_failure.560210022
Directory /workspace/13.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.1544991417
Short name T210
Test name
Test status
Simulation time 65373412 ps
CPU time 1.73 seconds
Started Jun 06 02:31:06 PM PDT 24
Finished Jun 06 02:31:10 PM PDT 24
Peak memory 217488 kb
Host smart-942d49a0-9b61-4354-aaa3-3dd7fc6ee1db
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544991417 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_aliasin
g.1544991417
Directory /workspace/0.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.3585590066
Short name T895
Test name
Test status
Simulation time 176407193 ps
CPU time 2.02 seconds
Started Jun 06 02:31:03 PM PDT 24
Finished Jun 06 02:31:07 PM PDT 24
Peak memory 209728 kb
Host smart-d1834e0d-07cf-4802-a169-b67ec31b8efa
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585590066 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_bit_bas
h.3585590066
Directory /workspace/0.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.744109312
Short name T133
Test name
Test status
Simulation time 15089102 ps
CPU time 1.07 seconds
Started Jun 06 02:30:55 PM PDT 24
Finished Jun 06 02:30:57 PM PDT 24
Peak memory 210528 kb
Host smart-8bf89596-f354-4f9a-a837-af6e1e9d2c32
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744109312 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_hw_reset
.744109312
Directory /workspace/0.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.3289196003
Short name T896
Test name
Test status
Simulation time 15787065 ps
CPU time 1.35 seconds
Started Jun 06 02:31:04 PM PDT 24
Finished Jun 06 02:31:08 PM PDT 24
Peak memory 219700 kb
Host smart-6fa0d850-bd6c-4638-acd2-94c96d88bc0a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289196003 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 0.lc_ctrl_csr_mem_rw_with_rand_reset.3289196003
Directory /workspace/0.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.2177842004
Short name T986
Test name
Test status
Simulation time 14791419 ps
CPU time 0.88 seconds
Started Jun 06 02:30:55 PM PDT 24
Finished Jun 06 02:30:58 PM PDT 24
Peak memory 209888 kb
Host smart-734dfd19-bc15-4842-98e0-b442fa661446
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177842004 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_rw.2177842004
Directory /workspace/0.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.4142909143
Short name T950
Test name
Test status
Simulation time 85186990 ps
CPU time 2.72 seconds
Started Jun 06 02:31:01 PM PDT 24
Finished Jun 06 02:31:06 PM PDT 24
Peak memory 209736 kb
Host smart-6e52cd9b-75a0-4d1c-a6de-905c7e9bad67
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142909143 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.lc_ctrl_jtag_alert_test.4142909143
Directory /workspace/0.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.410236954
Short name T889
Test name
Test status
Simulation time 1247738611 ps
CPU time 14.31 seconds
Started Jun 06 02:31:15 PM PDT 24
Finished Jun 06 02:31:37 PM PDT 24
Peak memory 209768 kb
Host smart-e8833017-4cb9-4a56-8d5a-5f2e529bb85d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410236954 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 0.lc_ctrl_jtag_csr_aliasing.410236954
Directory /workspace/0.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.152880329
Short name T957
Test name
Test status
Simulation time 2759323534 ps
CPU time 13.51 seconds
Started Jun 06 02:30:54 PM PDT 24
Finished Jun 06 02:31:08 PM PDT 24
Peak memory 209820 kb
Host smart-1c089c97-5ad1-403e-a083-1e312fbce2db
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152880329 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 0.lc_ctrl_jtag_csr_bit_bash.152880329
Directory /workspace/0.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.3194548841
Short name T904
Test name
Test status
Simulation time 235906500 ps
CPU time 1.37 seconds
Started Jun 06 02:31:03 PM PDT 24
Finished Jun 06 02:31:06 PM PDT 24
Peak memory 211180 kb
Host smart-fa212af9-9463-454f-958a-590d2eee23a7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194548841 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_hw_reset.3194548841
Directory /workspace/0.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.495693179
Short name T941
Test name
Test status
Simulation time 104090860 ps
CPU time 2.17 seconds
Started Jun 06 02:30:58 PM PDT 24
Finished Jun 06 02:31:03 PM PDT 24
Peak memory 218584 kb
Host smart-6bc306e4-fb13-4156-a15d-23a23452d25d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495693
179 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.495693179
Directory /workspace/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.1075242573
Short name T973
Test name
Test status
Simulation time 248960763 ps
CPU time 1.02 seconds
Started Jun 06 02:30:55 PM PDT 24
Finished Jun 06 02:30:57 PM PDT 24
Peak memory 209800 kb
Host smart-0512d292-72dd-4db8-b457-b516ae85930f
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075242573 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.lc_ctrl_jtag_csr_rw.1075242573
Directory /workspace/0.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.229246873
Short name T923
Test name
Test status
Simulation time 45092413 ps
CPU time 0.95 seconds
Started Jun 06 02:30:55 PM PDT 24
Finished Jun 06 02:30:58 PM PDT 24
Peak memory 217784 kb
Host smart-56a0a2bd-b571-4dd4-b1c1-39b1a5cbfd4d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229246873 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
same_csr_outstanding.229246873
Directory /workspace/0.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.3548714837
Short name T964
Test name
Test status
Simulation time 120550814 ps
CPU time 2.14 seconds
Started Jun 06 02:30:58 PM PDT 24
Finished Jun 06 02:31:03 PM PDT 24
Peak memory 218248 kb
Host smart-0220a550-4bd8-44d0-83be-daadc7846d1f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548714837 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_errors.3548714837
Directory /workspace/0.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.373063331
Short name T132
Test name
Test status
Simulation time 38175032 ps
CPU time 1.21 seconds
Started Jun 06 02:31:09 PM PDT 24
Finished Jun 06 02:31:15 PM PDT 24
Peak memory 209884 kb
Host smart-93d45cfb-b906-490a-ae92-60b8ea7ee636
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373063331 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_aliasing
.373063331
Directory /workspace/1.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.3915747646
Short name T891
Test name
Test status
Simulation time 291962555 ps
CPU time 1.32 seconds
Started Jun 06 02:31:10 PM PDT 24
Finished Jun 06 02:31:17 PM PDT 24
Peak memory 209828 kb
Host smart-1f28ce81-b830-4de3-9d60-d71cf830d98c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915747646 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_bit_bas
h.3915747646
Directory /workspace/1.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.540784917
Short name T208
Test name
Test status
Simulation time 38079470 ps
CPU time 0.97 seconds
Started Jun 06 02:30:55 PM PDT 24
Finished Jun 06 02:30:57 PM PDT 24
Peak memory 210396 kb
Host smart-a2424331-a7e0-4e73-8185-61ddfbbe0145
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540784917 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_hw_reset
.540784917
Directory /workspace/1.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.1765033027
Short name T900
Test name
Test status
Simulation time 127375875 ps
CPU time 1.77 seconds
Started Jun 06 02:31:11 PM PDT 24
Finished Jun 06 02:31:20 PM PDT 24
Peak memory 218848 kb
Host smart-f6a4ca37-4348-4655-acb6-32aee2d2dc15
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765033027 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 1.lc_ctrl_csr_mem_rw_with_rand_reset.1765033027
Directory /workspace/1.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.36144587
Short name T961
Test name
Test status
Simulation time 12037856 ps
CPU time 0.99 seconds
Started Jun 06 02:30:58 PM PDT 24
Finished Jun 06 02:31:02 PM PDT 24
Peak memory 209864 kb
Host smart-466affe4-945f-4b30-8db9-a0894d8546b7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36144587 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_rw.36144587
Directory /workspace/1.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.2761078664
Short name T918
Test name
Test status
Simulation time 79094623 ps
CPU time 2.71 seconds
Started Jun 06 02:30:59 PM PDT 24
Finished Jun 06 02:31:04 PM PDT 24
Peak memory 209724 kb
Host smart-a5741bb6-d579-44fe-bdb5-230ab03d8a49
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761078664 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.lc_ctrl_jtag_alert_test.2761078664
Directory /workspace/1.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.1324777620
Short name T134
Test name
Test status
Simulation time 373037513 ps
CPU time 4.55 seconds
Started Jun 06 02:31:08 PM PDT 24
Finished Jun 06 02:31:16 PM PDT 24
Peak memory 209516 kb
Host smart-a13772d1-eb8a-4fac-81e6-15933d2f625b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324777620 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_aliasing.1324777620
Directory /workspace/1.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.1746230491
Short name T959
Test name
Test status
Simulation time 4705518023 ps
CPU time 31.62 seconds
Started Jun 06 02:31:05 PM PDT 24
Finished Jun 06 02:31:39 PM PDT 24
Peak memory 209844 kb
Host smart-7b380bea-f7ea-468f-b8c2-ce9c6dfbaf14
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746230491 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_bit_bash.1746230491
Directory /workspace/1.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.3727077110
Short name T159
Test name
Test status
Simulation time 113007847 ps
CPU time 2.16 seconds
Started Jun 06 02:31:07 PM PDT 24
Finished Jun 06 02:31:13 PM PDT 24
Peak memory 211244 kb
Host smart-2d398637-ff28-4c2f-98fa-69b58adfab84
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727077110 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_hw_reset.3727077110
Directory /workspace/1.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.16608883
Short name T920
Test name
Test status
Simulation time 378364407 ps
CPU time 2.68 seconds
Started Jun 06 02:30:57 PM PDT 24
Finished Jun 06 02:31:03 PM PDT 24
Peak memory 218320 kb
Host smart-df4e4b52-c774-4be9-b7bc-a18e0b1b2941
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166088
83 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.16608883
Directory /workspace/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.2318390664
Short name T962
Test name
Test status
Simulation time 513309313 ps
CPU time 3 seconds
Started Jun 06 02:31:05 PM PDT 24
Finished Jun 06 02:31:10 PM PDT 24
Peak memory 209832 kb
Host smart-788ec3b0-b671-4ab6-91ce-60a430508c2f
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318390664 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.lc_ctrl_jtag_csr_rw.2318390664
Directory /workspace/1.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.622405317
Short name T947
Test name
Test status
Simulation time 118073939 ps
CPU time 1.31 seconds
Started Jun 06 02:31:12 PM PDT 24
Finished Jun 06 02:31:19 PM PDT 24
Peak memory 209900 kb
Host smart-04928f24-b99f-49f7-9873-da2c720a05da
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622405317 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.lc_ctrl_jtag_same_csr_outstanding.622405317
Directory /workspace/1.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.3862012043
Short name T916
Test name
Test status
Simulation time 26308914 ps
CPU time 1.42 seconds
Started Jun 06 02:30:55 PM PDT 24
Finished Jun 06 02:30:58 PM PDT 24
Peak memory 217832 kb
Host smart-fa4e1882-f4db-4329-9d14-111e5999a6a9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862012043 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl
_same_csr_outstanding.3862012043
Directory /workspace/1.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.2233997202
Short name T932
Test name
Test status
Simulation time 867934018 ps
CPU time 2 seconds
Started Jun 06 02:31:11 PM PDT 24
Finished Jun 06 02:31:19 PM PDT 24
Peak memory 218144 kb
Host smart-5a439892-86a7-4355-a028-49aa712e6e0e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233997202 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_errors.2233997202
Directory /workspace/1.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.3473057766
Short name T913
Test name
Test status
Simulation time 23326890 ps
CPU time 1.45 seconds
Started Jun 06 02:31:15 PM PDT 24
Finished Jun 06 02:31:25 PM PDT 24
Peak memory 218336 kb
Host smart-423acfe0-ce42-4e30-ae24-08ffed910812
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473057766 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 10.lc_ctrl_csr_mem_rw_with_rand_reset.3473057766
Directory /workspace/10.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.4242292413
Short name T956
Test name
Test status
Simulation time 93718024 ps
CPU time 0.83 seconds
Started Jun 06 02:31:15 PM PDT 24
Finished Jun 06 02:31:23 PM PDT 24
Peak memory 209892 kb
Host smart-ba221700-26b9-4346-a628-33fada8e2098
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242292413 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_csr_rw.4242292413
Directory /workspace/10.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.430337238
Short name T215
Test name
Test status
Simulation time 56258224 ps
CPU time 1.09 seconds
Started Jun 06 02:31:33 PM PDT 24
Finished Jun 06 02:31:39 PM PDT 24
Peak memory 209952 kb
Host smart-05b46dc9-5d5f-42f5-8640-1bb9fe21d546
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430337238 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl
_same_csr_outstanding.430337238
Directory /workspace/10.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.2138726431
Short name T991
Test name
Test status
Simulation time 53004747 ps
CPU time 2.37 seconds
Started Jun 06 02:31:13 PM PDT 24
Finished Jun 06 02:31:23 PM PDT 24
Peak memory 218124 kb
Host smart-22e1efc3-444c-46b7-865c-239bfb628105
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138726431 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_errors.2138726431
Directory /workspace/10.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.2889821600
Short name T151
Test name
Test status
Simulation time 119107540 ps
CPU time 1.81 seconds
Started Jun 06 02:31:16 PM PDT 24
Finished Jun 06 02:31:26 PM PDT 24
Peak memory 218560 kb
Host smart-4db28797-106c-4739-b75e-97515186ca92
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889821600 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 11.lc_ctrl_csr_mem_rw_with_rand_reset.2889821600
Directory /workspace/11.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.276025595
Short name T137
Test name
Test status
Simulation time 48139275 ps
CPU time 0.98 seconds
Started Jun 06 02:31:25 PM PDT 24
Finished Jun 06 02:31:31 PM PDT 24
Peak memory 209884 kb
Host smart-43435b43-4cc5-4f83-9cf1-86f6e9122c89
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276025595 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_csr_rw.276025595
Directory /workspace/11.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.2942100963
Short name T216
Test name
Test status
Simulation time 22542111 ps
CPU time 1.54 seconds
Started Jun 06 02:31:25 PM PDT 24
Finished Jun 06 02:31:33 PM PDT 24
Peak memory 218192 kb
Host smart-431a50bf-a503-467a-8757-af8711189a39
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942100963 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctr
l_same_csr_outstanding.2942100963
Directory /workspace/11.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.1465152223
Short name T901
Test name
Test status
Simulation time 41032826 ps
CPU time 1.38 seconds
Started Jun 06 02:31:24 PM PDT 24
Finished Jun 06 02:31:32 PM PDT 24
Peak memory 219568 kb
Host smart-e41f5624-871e-4bd6-8c33-e67ef5b543d0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465152223 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 12.lc_ctrl_csr_mem_rw_with_rand_reset.1465152223
Directory /workspace/12.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.1968490223
Short name T211
Test name
Test status
Simulation time 51589768 ps
CPU time 0.95 seconds
Started Jun 06 02:31:21 PM PDT 24
Finished Jun 06 02:31:29 PM PDT 24
Peak memory 209896 kb
Host smart-fbf656da-014e-4f40-9b02-7ff96c693744
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968490223 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_csr_rw.1968490223
Directory /workspace/12.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.1216083852
Short name T217
Test name
Test status
Simulation time 42802827 ps
CPU time 1.99 seconds
Started Jun 06 02:31:29 PM PDT 24
Finished Jun 06 02:31:36 PM PDT 24
Peak memory 218152 kb
Host smart-e790ccca-3d60-4add-aa82-cdcb04baeecd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216083852 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctr
l_same_csr_outstanding.1216083852
Directory /workspace/12.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.2159661002
Short name T944
Test name
Test status
Simulation time 52996220 ps
CPU time 3.24 seconds
Started Jun 06 02:31:16 PM PDT 24
Finished Jun 06 02:31:27 PM PDT 24
Peak memory 218296 kb
Host smart-7e641add-0687-42d6-9a26-c01000849aa9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159661002 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_errors.2159661002
Directory /workspace/12.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.3740870084
Short name T127
Test name
Test status
Simulation time 19869462 ps
CPU time 1.31 seconds
Started Jun 06 02:31:33 PM PDT 24
Finished Jun 06 02:31:39 PM PDT 24
Peak memory 218328 kb
Host smart-d8a7f3dd-f75c-4884-96e2-f597dda0045a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740870084 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 13.lc_ctrl_csr_mem_rw_with_rand_reset.3740870084
Directory /workspace/13.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.3187515969
Short name T912
Test name
Test status
Simulation time 21834211 ps
CPU time 0.87 seconds
Started Jun 06 02:31:29 PM PDT 24
Finished Jun 06 02:31:35 PM PDT 24
Peak memory 209652 kb
Host smart-861f19c7-8172-4440-8d95-38e4ad10b987
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187515969 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_csr_rw.3187515969
Directory /workspace/13.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.2738421629
Short name T968
Test name
Test status
Simulation time 43963436 ps
CPU time 1.32 seconds
Started Jun 06 02:31:29 PM PDT 24
Finished Jun 06 02:31:36 PM PDT 24
Peak memory 217804 kb
Host smart-19b66ad3-9412-45e6-82b4-24a9abbdb753
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738421629 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctr
l_same_csr_outstanding.2738421629
Directory /workspace/13.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.2994259917
Short name T147
Test name
Test status
Simulation time 101008694 ps
CPU time 1.86 seconds
Started Jun 06 02:31:38 PM PDT 24
Finished Jun 06 02:31:44 PM PDT 24
Peak memory 218412 kb
Host smart-0b5ae860-900c-4732-bdd4-14bf22d26ac9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994259917 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_errors.2994259917
Directory /workspace/13.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.3422712728
Short name T908
Test name
Test status
Simulation time 22646135 ps
CPU time 1.27 seconds
Started Jun 06 02:31:29 PM PDT 24
Finished Jun 06 02:31:35 PM PDT 24
Peak memory 218848 kb
Host smart-a9e839cb-8506-4fe0-a9a2-085cb873a996
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422712728 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 14.lc_ctrl_csr_mem_rw_with_rand_reset.3422712728
Directory /workspace/14.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.1340871404
Short name T906
Test name
Test status
Simulation time 12226672 ps
CPU time 0.83 seconds
Started Jun 06 02:31:18 PM PDT 24
Finished Jun 06 02:31:26 PM PDT 24
Peak memory 209636 kb
Host smart-2060c39c-da62-429a-951b-a2f588337d02
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340871404 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_csr_rw.1340871404
Directory /workspace/14.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.3642453006
Short name T927
Test name
Test status
Simulation time 246362046 ps
CPU time 1.69 seconds
Started Jun 06 02:31:27 PM PDT 24
Finished Jun 06 02:31:34 PM PDT 24
Peak memory 217884 kb
Host smart-047949e3-3991-496e-94c2-3dd80a53249d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642453006 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctr
l_same_csr_outstanding.3642453006
Directory /workspace/14.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.1383377578
Short name T128
Test name
Test status
Simulation time 150645332 ps
CPU time 2.39 seconds
Started Jun 06 02:31:32 PM PDT 24
Finished Jun 06 02:31:39 PM PDT 24
Peak memory 218176 kb
Host smart-2eeeafe2-134a-4fe4-b8bf-c27bf23c134d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383377578 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_errors.1383377578
Directory /workspace/14.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.968413690
Short name T903
Test name
Test status
Simulation time 69613550 ps
CPU time 1.66 seconds
Started Jun 06 02:31:36 PM PDT 24
Finished Jun 06 02:31:42 PM PDT 24
Peak memory 218280 kb
Host smart-259fa834-0356-466e-bcc3-dc7b15b91964
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968413690 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 15.lc_ctrl_csr_mem_rw_with_rand_reset.968413690
Directory /workspace/15.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.411783704
Short name T878
Test name
Test status
Simulation time 39136303 ps
CPU time 0.85 seconds
Started Jun 06 02:31:25 PM PDT 24
Finished Jun 06 02:31:32 PM PDT 24
Peak memory 209208 kb
Host smart-13792b98-5924-4bc0-9463-c24efd271cca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411783704 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_csr_rw.411783704
Directory /workspace/15.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.547843611
Short name T220
Test name
Test status
Simulation time 73996948 ps
CPU time 1.31 seconds
Started Jun 06 02:31:32 PM PDT 24
Finished Jun 06 02:31:38 PM PDT 24
Peak memory 218168 kb
Host smart-1a5e7121-0c44-4622-bac9-724a73b5f64a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547843611 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl
_same_csr_outstanding.547843611
Directory /workspace/15.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.3303288868
Short name T979
Test name
Test status
Simulation time 112756491 ps
CPU time 4.31 seconds
Started Jun 06 02:31:35 PM PDT 24
Finished Jun 06 02:31:44 PM PDT 24
Peak memory 218132 kb
Host smart-e33bcf2c-2ee1-4644-9627-7f0fa7a07b94
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303288868 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_errors.3303288868
Directory /workspace/15.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.225534151
Short name T965
Test name
Test status
Simulation time 75965765 ps
CPU time 1.02 seconds
Started Jun 06 02:31:42 PM PDT 24
Finished Jun 06 02:31:48 PM PDT 24
Peak memory 218276 kb
Host smart-a8dc527d-36d4-4843-b803-7eb4f0d3d8e2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225534151 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 16.lc_ctrl_csr_mem_rw_with_rand_reset.225534151
Directory /workspace/16.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.4096103379
Short name T219
Test name
Test status
Simulation time 14012038 ps
CPU time 1.01 seconds
Started Jun 06 02:31:27 PM PDT 24
Finished Jun 06 02:31:34 PM PDT 24
Peak memory 209480 kb
Host smart-dfa4cbef-5edb-4533-beba-697077ed609b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096103379 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_csr_rw.4096103379
Directory /workspace/16.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.3403776425
Short name T914
Test name
Test status
Simulation time 159802627 ps
CPU time 1.54 seconds
Started Jun 06 02:31:32 PM PDT 24
Finished Jun 06 02:31:38 PM PDT 24
Peak memory 209948 kb
Host smart-d81d6876-e8cd-4b5f-b1db-975c486c8fce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403776425 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctr
l_same_csr_outstanding.3403776425
Directory /workspace/16.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.516710430
Short name T974
Test name
Test status
Simulation time 206861807 ps
CPU time 4.11 seconds
Started Jun 06 02:31:36 PM PDT 24
Finished Jun 06 02:31:45 PM PDT 24
Peak memory 218432 kb
Host smart-c493e756-7a10-4c7f-b52d-3a78ff808b57
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516710430 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_errors.516710430
Directory /workspace/16.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.1398910109
Short name T171
Test name
Test status
Simulation time 69418111 ps
CPU time 1.3 seconds
Started Jun 06 02:31:31 PM PDT 24
Finished Jun 06 02:31:37 PM PDT 24
Peak memory 218228 kb
Host smart-3fc11262-8650-4137-bf57-75030f1cd55a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398910109 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 17.lc_ctrl_csr_mem_rw_with_rand_reset.1398910109
Directory /workspace/17.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.1846096761
Short name T933
Test name
Test status
Simulation time 27023947 ps
CPU time 0.87 seconds
Started Jun 06 02:31:46 PM PDT 24
Finished Jun 06 02:31:52 PM PDT 24
Peak memory 209692 kb
Host smart-a150f6bc-74cb-4c14-aa75-3c88b613bcd7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846096761 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_csr_rw.1846096761
Directory /workspace/17.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.2163009060
Short name T928
Test name
Test status
Simulation time 91476529 ps
CPU time 1.23 seconds
Started Jun 06 02:31:32 PM PDT 24
Finished Jun 06 02:31:38 PM PDT 24
Peak memory 209964 kb
Host smart-17d7b92b-f610-49dd-bc40-99295c3d7817
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163009060 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctr
l_same_csr_outstanding.2163009060
Directory /workspace/17.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.199294790
Short name T929
Test name
Test status
Simulation time 126720188 ps
CPU time 3.39 seconds
Started Jun 06 02:31:33 PM PDT 24
Finished Jun 06 02:31:41 PM PDT 24
Peak memory 218364 kb
Host smart-d935d730-b9a7-4bd1-8bb1-94be5de05a1e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199294790 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_errors.199294790
Directory /workspace/17.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.3308007506
Short name T152
Test name
Test status
Simulation time 251426109 ps
CPU time 1.8 seconds
Started Jun 06 02:31:23 PM PDT 24
Finished Jun 06 02:31:32 PM PDT 24
Peak memory 222200 kb
Host smart-d2c217cf-33ed-4121-8c09-2e573827cf67
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308007506 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_intg
_err.3308007506
Directory /workspace/17.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.1817250467
Short name T958
Test name
Test status
Simulation time 32938571 ps
CPU time 1.25 seconds
Started Jun 06 02:31:43 PM PDT 24
Finished Jun 06 02:31:50 PM PDT 24
Peak memory 218232 kb
Host smart-06ab1958-8990-402f-96e8-e901d5b62987
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817250467 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 18.lc_ctrl_csr_mem_rw_with_rand_reset.1817250467
Directory /workspace/18.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.380932096
Short name T910
Test name
Test status
Simulation time 154084600 ps
CPU time 1.14 seconds
Started Jun 06 02:31:28 PM PDT 24
Finished Jun 06 02:31:35 PM PDT 24
Peak memory 209908 kb
Host smart-80a5a6ca-cfe4-41e4-87ec-c4e2c5bb2cdb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380932096 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl
_same_csr_outstanding.380932096
Directory /workspace/18.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.3578040640
Short name T125
Test name
Test status
Simulation time 66329423 ps
CPU time 2.38 seconds
Started Jun 06 02:31:33 PM PDT 24
Finished Jun 06 02:31:40 PM PDT 24
Peak memory 218148 kb
Host smart-b15a64d5-0219-4430-8d07-942400192e35
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578040640 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_errors.3578040640
Directory /workspace/18.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.2241582452
Short name T139
Test name
Test status
Simulation time 268610023 ps
CPU time 2.63 seconds
Started Jun 06 02:31:29 PM PDT 24
Finished Jun 06 02:31:36 PM PDT 24
Peak memory 222604 kb
Host smart-33d124bc-44ba-4682-8d57-1b4be6bac47c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241582452 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_intg
_err.2241582452
Directory /workspace/18.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.2039972708
Short name T207
Test name
Test status
Simulation time 63105621 ps
CPU time 0.98 seconds
Started Jun 06 02:31:21 PM PDT 24
Finished Jun 06 02:31:29 PM PDT 24
Peak memory 209884 kb
Host smart-91b78de7-b2f1-4297-988e-a6a6d9d5cd40
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039972708 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_csr_rw.2039972708
Directory /workspace/19.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.1792912681
Short name T919
Test name
Test status
Simulation time 78634119 ps
CPU time 1.24 seconds
Started Jun 06 02:31:20 PM PDT 24
Finished Jun 06 02:31:28 PM PDT 24
Peak memory 218160 kb
Host smart-cdfbf98d-bec8-4436-b356-e3d9ed473d92
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792912681 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctr
l_same_csr_outstanding.1792912681
Directory /workspace/19.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.2446166702
Short name T922
Test name
Test status
Simulation time 40954234 ps
CPU time 2.76 seconds
Started Jun 06 02:31:33 PM PDT 24
Finished Jun 06 02:31:40 PM PDT 24
Peak memory 218668 kb
Host smart-e5221081-3106-408e-b7c6-e17df50ec9ef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446166702 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_errors.2446166702
Directory /workspace/19.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.3997603096
Short name T225
Test name
Test status
Simulation time 45979776 ps
CPU time 1 seconds
Started Jun 06 02:31:12 PM PDT 24
Finished Jun 06 02:31:20 PM PDT 24
Peak memory 209136 kb
Host smart-c029cba8-e9c1-46b3-9e4c-c47b4829b678
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997603096 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_aliasin
g.3997603096
Directory /workspace/2.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.2008176702
Short name T169
Test name
Test status
Simulation time 574518543 ps
CPU time 1.84 seconds
Started Jun 06 02:31:15 PM PDT 24
Finished Jun 06 02:31:25 PM PDT 24
Peak memory 209832 kb
Host smart-940857da-2dba-405f-a913-920148781d1c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008176702 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_bit_bas
h.2008176702
Directory /workspace/2.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.2145380419
Short name T948
Test name
Test status
Simulation time 20924327 ps
CPU time 1.02 seconds
Started Jun 06 02:31:08 PM PDT 24
Finished Jun 06 02:31:13 PM PDT 24
Peak memory 210620 kb
Host smart-12c1f19e-03de-4ec3-b7ff-463428f783ed
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145380419 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_hw_rese
t.2145380419
Directory /workspace/2.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.1976681739
Short name T945
Test name
Test status
Simulation time 18338267 ps
CPU time 1.03 seconds
Started Jun 06 02:31:14 PM PDT 24
Finished Jun 06 02:31:22 PM PDT 24
Peak memory 218236 kb
Host smart-b86d7603-d946-4968-beb0-165e5e13bcc8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976681739 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 2.lc_ctrl_csr_mem_rw_with_rand_reset.1976681739
Directory /workspace/2.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.2787685135
Short name T206
Test name
Test status
Simulation time 14266695 ps
CPU time 1.06 seconds
Started Jun 06 02:31:07 PM PDT 24
Finished Jun 06 02:31:11 PM PDT 24
Peak memory 209888 kb
Host smart-3578d576-3bfa-40d6-8f7a-36723611e3b3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787685135 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_rw.2787685135
Directory /workspace/2.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.2973751874
Short name T997
Test name
Test status
Simulation time 28996883 ps
CPU time 1.35 seconds
Started Jun 06 02:31:13 PM PDT 24
Finished Jun 06 02:31:22 PM PDT 24
Peak memory 208936 kb
Host smart-2dc6748f-4d29-4f96-847b-5ab600d62874
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973751874 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.lc_ctrl_jtag_alert_test.2973751874
Directory /workspace/2.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.1959470561
Short name T905
Test name
Test status
Simulation time 2326352652 ps
CPU time 22.8 seconds
Started Jun 06 02:31:15 PM PDT 24
Finished Jun 06 02:31:46 PM PDT 24
Peak memory 217724 kb
Host smart-96a413f8-8546-4ca3-a3c3-efe577331292
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959470561 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_aliasing.1959470561
Directory /workspace/2.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.3445594401
Short name T907
Test name
Test status
Simulation time 624950048 ps
CPU time 6.06 seconds
Started Jun 06 02:31:15 PM PDT 24
Finished Jun 06 02:31:29 PM PDT 24
Peak memory 209764 kb
Host smart-15c57703-2012-4ac6-882a-270585e12e28
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445594401 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_bit_bash.3445594401
Directory /workspace/2.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.958818113
Short name T984
Test name
Test status
Simulation time 74099933 ps
CPU time 2.13 seconds
Started Jun 06 02:31:00 PM PDT 24
Finished Jun 06 02:31:05 PM PDT 24
Peak memory 217976 kb
Host smart-7241639c-c3ab-4e28-8e8a-f8c1c5bddbe5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958818113 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 2.lc_ctrl_jtag_csr_hw_reset.958818113
Directory /workspace/2.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2193066891
Short name T893
Test name
Test status
Simulation time 67191881 ps
CPU time 1.64 seconds
Started Jun 06 02:31:21 PM PDT 24
Finished Jun 06 02:31:30 PM PDT 24
Peak memory 220328 kb
Host smart-9f0983e9-2aee-4375-aeba-514dc7d705e7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219306
6891 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2193066891
Directory /workspace/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.1687490710
Short name T960
Test name
Test status
Simulation time 621727856 ps
CPU time 3.16 seconds
Started Jun 06 02:31:05 PM PDT 24
Finished Jun 06 02:31:11 PM PDT 24
Peak memory 209780 kb
Host smart-1330f5a2-0b35-481c-8619-a4cc132c39c6
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687490710 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.lc_ctrl_jtag_csr_rw.1687490710
Directory /workspace/2.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.1959523642
Short name T212
Test name
Test status
Simulation time 20441254 ps
CPU time 1.16 seconds
Started Jun 06 02:31:14 PM PDT 24
Finished Jun 06 02:31:22 PM PDT 24
Peak memory 209748 kb
Host smart-598f9ab4-a94d-4516-a20c-433fb3856970
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959523642 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.lc_ctrl_jtag_same_csr_outstanding.1959523642
Directory /workspace/2.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.1993915775
Short name T963
Test name
Test status
Simulation time 84550680 ps
CPU time 1.04 seconds
Started Jun 06 02:31:14 PM PDT 24
Finished Jun 06 02:31:22 PM PDT 24
Peak memory 209908 kb
Host smart-49cc3a7a-c23c-46e4-86bf-6608eb15ca31
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993915775 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl
_same_csr_outstanding.1993915775
Directory /workspace/2.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.856109270
Short name T124
Test name
Test status
Simulation time 128573688 ps
CPU time 3.19 seconds
Started Jun 06 02:31:25 PM PDT 24
Finished Jun 06 02:31:34 PM PDT 24
Peak memory 218324 kb
Host smart-591cf3f8-d823-48e3-9766-edf4a4605ea3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856109270 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_errors.856109270
Directory /workspace/2.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.2951616514
Short name T158
Test name
Test status
Simulation time 85955764 ps
CPU time 2.22 seconds
Started Jun 06 02:31:04 PM PDT 24
Finished Jun 06 02:31:09 PM PDT 24
Peak memory 218096 kb
Host smart-fb7dfc86-dd18-49ef-af6f-af90d04d41f0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951616514 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_intg_
err.2951616514
Directory /workspace/2.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.967380600
Short name T882
Test name
Test status
Simulation time 127616841 ps
CPU time 1.6 seconds
Started Jun 06 02:31:08 PM PDT 24
Finished Jun 06 02:31:13 PM PDT 24
Peak memory 209880 kb
Host smart-ed96a9ef-4553-4278-98ae-2435868d4117
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967380600 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_aliasing
.967380600
Directory /workspace/3.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.2127210634
Short name T966
Test name
Test status
Simulation time 442067971 ps
CPU time 1.44 seconds
Started Jun 06 02:31:11 PM PDT 24
Finished Jun 06 02:31:19 PM PDT 24
Peak memory 209080 kb
Host smart-b17149e0-2e78-42fc-81ae-9563a22cb9d4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127210634 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_bit_bas
h.2127210634
Directory /workspace/3.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.766932802
Short name T972
Test name
Test status
Simulation time 15301398 ps
CPU time 1.12 seconds
Started Jun 06 02:31:10 PM PDT 24
Finished Jun 06 02:31:16 PM PDT 24
Peak memory 218756 kb
Host smart-b53197c4-2d9c-430b-a1a3-3bf1600d5691
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766932802 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_hw_reset
.766932802
Directory /workspace/3.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.1305112141
Short name T930
Test name
Test status
Simulation time 24486103 ps
CPU time 1.11 seconds
Started Jun 06 02:31:06 PM PDT 24
Finished Jun 06 02:31:09 PM PDT 24
Peak memory 219256 kb
Host smart-842fbd87-caa5-49e9-8120-f1356c1a7339
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305112141 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 3.lc_ctrl_csr_mem_rw_with_rand_reset.1305112141
Directory /workspace/3.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.1513405924
Short name T205
Test name
Test status
Simulation time 20620348 ps
CPU time 0.82 seconds
Started Jun 06 02:31:14 PM PDT 24
Finished Jun 06 02:31:23 PM PDT 24
Peak memory 209700 kb
Host smart-3ac145be-091f-4ee2-8222-873d5ee9cb46
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513405924 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_rw.1513405924
Directory /workspace/3.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.2222953725
Short name T888
Test name
Test status
Simulation time 173151455 ps
CPU time 1.07 seconds
Started Jun 06 02:31:11 PM PDT 24
Finished Jun 06 02:31:17 PM PDT 24
Peak memory 209896 kb
Host smart-8ee4900b-2b91-4f28-902d-dda5dc27ecf2
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222953725 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.lc_ctrl_jtag_alert_test.2222953725
Directory /workspace/3.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.1936325202
Short name T993
Test name
Test status
Simulation time 481710915 ps
CPU time 3.41 seconds
Started Jun 06 02:31:13 PM PDT 24
Finished Jun 06 02:31:24 PM PDT 24
Peak memory 209432 kb
Host smart-22c9e764-67a3-4fdc-9c2c-c1a0e460e50f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936325202 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_aliasing.1936325202
Directory /workspace/3.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.4156005187
Short name T970
Test name
Test status
Simulation time 9061011758 ps
CPU time 33.24 seconds
Started Jun 06 02:31:13 PM PDT 24
Finished Jun 06 02:31:54 PM PDT 24
Peak memory 209868 kb
Host smart-d39c5e94-c4cf-44ad-950d-8a053c7205d5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156005187 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_bit_bash.4156005187
Directory /workspace/3.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.4170382744
Short name T949
Test name
Test status
Simulation time 160735766 ps
CPU time 1.78 seconds
Started Jun 06 02:31:07 PM PDT 24
Finished Jun 06 02:31:12 PM PDT 24
Peak memory 211324 kb
Host smart-f76540b6-f7a8-4727-acf2-47eb5d16ed81
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170382744 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_hw_reset.4170382744
Directory /workspace/3.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3561539654
Short name T982
Test name
Test status
Simulation time 301138634 ps
CPU time 2.61 seconds
Started Jun 06 02:31:09 PM PDT 24
Finished Jun 06 02:31:16 PM PDT 24
Peak memory 218232 kb
Host smart-8927296e-cfe7-4d77-befb-435a3e4b46b3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356153
9654 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3561539654
Directory /workspace/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.1232468808
Short name T936
Test name
Test status
Simulation time 190637427 ps
CPU time 1.18 seconds
Started Jun 06 02:31:07 PM PDT 24
Finished Jun 06 02:31:12 PM PDT 24
Peak memory 217096 kb
Host smart-b2debccb-a53f-4d3d-aee7-a74404eb697c
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232468808 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.lc_ctrl_jtag_csr_rw.1232468808
Directory /workspace/3.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.1753197423
Short name T213
Test name
Test status
Simulation time 76625813 ps
CPU time 0.94 seconds
Started Jun 06 02:31:09 PM PDT 24
Finished Jun 06 02:31:14 PM PDT 24
Peak memory 209936 kb
Host smart-a8e79abc-ef13-462f-bc97-da159af78530
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753197423 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.lc_ctrl_jtag_same_csr_outstanding.1753197423
Directory /workspace/3.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.127334493
Short name T995
Test name
Test status
Simulation time 302884653 ps
CPU time 1.06 seconds
Started Jun 06 02:31:12 PM PDT 24
Finished Jun 06 02:31:20 PM PDT 24
Peak memory 217908 kb
Host smart-9d69ef6c-5687-4a17-b6a9-cbf2e6b2cb2e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127334493 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
same_csr_outstanding.127334493
Directory /workspace/3.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.2093296049
Short name T136
Test name
Test status
Simulation time 24424067 ps
CPU time 1.55 seconds
Started Jun 06 02:31:25 PM PDT 24
Finished Jun 06 02:31:33 PM PDT 24
Peak memory 219248 kb
Host smart-2d8fa2f0-53db-4357-a2e1-83bc21043388
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093296049 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_errors.2093296049
Directory /workspace/3.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.3165809346
Short name T144
Test name
Test status
Simulation time 42318237 ps
CPU time 2.39 seconds
Started Jun 06 02:31:09 PM PDT 24
Finished Jun 06 02:31:16 PM PDT 24
Peak memory 222488 kb
Host smart-c52b33eb-d6ec-4d65-927a-dfd213c4c9ab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165809346 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_intg_
err.3165809346
Directory /workspace/3.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.1502231394
Short name T898
Test name
Test status
Simulation time 48992756 ps
CPU time 1.08 seconds
Started Jun 06 02:31:14 PM PDT 24
Finished Jun 06 02:31:23 PM PDT 24
Peak memory 209876 kb
Host smart-f510bc0f-356d-4c03-b2a8-92814c27c7cd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502231394 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_aliasin
g.1502231394
Directory /workspace/4.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.834061217
Short name T170
Test name
Test status
Simulation time 161437892 ps
CPU time 1.82 seconds
Started Jun 06 02:31:08 PM PDT 24
Finished Jun 06 02:31:13 PM PDT 24
Peak memory 217264 kb
Host smart-783f29af-6e35-4ca4-979f-9b3aae4637e9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834061217 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_bit_bash
.834061217
Directory /workspace/4.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.3379344871
Short name T917
Test name
Test status
Simulation time 123774024 ps
CPU time 1.01 seconds
Started Jun 06 02:31:13 PM PDT 24
Finished Jun 06 02:31:22 PM PDT 24
Peak memory 210556 kb
Host smart-5197d4c4-9c61-48b3-bf9b-28b095953472
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379344871 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_hw_rese
t.3379344871
Directory /workspace/4.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.3740703661
Short name T890
Test name
Test status
Simulation time 180379830 ps
CPU time 1.3 seconds
Started Jun 06 02:31:13 PM PDT 24
Finished Jun 06 02:31:22 PM PDT 24
Peak memory 219104 kb
Host smart-801f6605-f7f6-4583-8823-fbc7591a1eaf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740703661 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 4.lc_ctrl_csr_mem_rw_with_rand_reset.3740703661
Directory /workspace/4.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.3388943869
Short name T899
Test name
Test status
Simulation time 60126330 ps
CPU time 1.06 seconds
Started Jun 06 02:31:05 PM PDT 24
Finished Jun 06 02:31:08 PM PDT 24
Peak memory 209972 kb
Host smart-da787c97-b730-43e6-8e60-e8d47e54b17a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388943869 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_rw.3388943869
Directory /workspace/4.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.1175094979
Short name T911
Test name
Test status
Simulation time 68550985 ps
CPU time 1.42 seconds
Started Jun 06 02:31:06 PM PDT 24
Finished Jun 06 02:31:10 PM PDT 24
Peak memory 209736 kb
Host smart-2a4a4770-0348-4f39-8c1c-548f06104919
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175094979 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.lc_ctrl_jtag_alert_test.1175094979
Directory /workspace/4.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.3309052474
Short name T909
Test name
Test status
Simulation time 525814197 ps
CPU time 5.39 seconds
Started Jun 06 02:31:09 PM PDT 24
Finished Jun 06 02:31:26 PM PDT 24
Peak memory 208884 kb
Host smart-f18c82dc-2bd0-4691-8444-c7786f96a764
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309052474 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_aliasing.3309052474
Directory /workspace/4.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.1368491396
Short name T226
Test name
Test status
Simulation time 7817830057 ps
CPU time 5.43 seconds
Started Jun 06 02:31:13 PM PDT 24
Finished Jun 06 02:31:26 PM PDT 24
Peak memory 217276 kb
Host smart-ab37aa3d-7ba4-48cd-83e6-8f5d6011207b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368491396 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_bit_bash.1368491396
Directory /workspace/4.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.173524694
Short name T886
Test name
Test status
Simulation time 136178634 ps
CPU time 1.77 seconds
Started Jun 06 02:31:09 PM PDT 24
Finished Jun 06 02:31:16 PM PDT 24
Peak memory 211368 kb
Host smart-848ff771-8b84-4c7a-80ff-fb4285ec0d5b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173524694 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 4.lc_ctrl_jtag_csr_hw_reset.173524694
Directory /workspace/4.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2380884144
Short name T934
Test name
Test status
Simulation time 313011093 ps
CPU time 1.5 seconds
Started Jun 06 02:31:08 PM PDT 24
Finished Jun 06 02:31:14 PM PDT 24
Peak memory 218304 kb
Host smart-291e79cf-b698-4b65-8202-8515c5c0a3cd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238088
4144 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2380884144
Directory /workspace/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.1042256092
Short name T894
Test name
Test status
Simulation time 197278067 ps
CPU time 1.5 seconds
Started Jun 06 02:31:10 PM PDT 24
Finished Jun 06 02:31:17 PM PDT 24
Peak memory 209760 kb
Host smart-bd7c71f5-1d04-40f0-b5e1-2c675718d90a
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042256092 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.lc_ctrl_jtag_csr_rw.1042256092
Directory /workspace/4.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.389452889
Short name T992
Test name
Test status
Simulation time 86617582 ps
CPU time 1.86 seconds
Started Jun 06 02:31:15 PM PDT 24
Finished Jun 06 02:31:26 PM PDT 24
Peak memory 210008 kb
Host smart-195ebee9-036b-4ad0-b9db-3182b47cac15
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389452889 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.lc_ctrl_jtag_same_csr_outstanding.389452889
Directory /workspace/4.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.1652076214
Short name T996
Test name
Test status
Simulation time 94780213 ps
CPU time 0.95 seconds
Started Jun 06 02:31:08 PM PDT 24
Finished Jun 06 02:31:13 PM PDT 24
Peak memory 210000 kb
Host smart-5536da0c-f76f-47f9-97dc-8781cf710c7a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652076214 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl
_same_csr_outstanding.1652076214
Directory /workspace/4.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.975907873
Short name T943
Test name
Test status
Simulation time 198700446 ps
CPU time 2.66 seconds
Started Jun 06 02:31:13 PM PDT 24
Finished Jun 06 02:31:22 PM PDT 24
Peak memory 218124 kb
Host smart-88409bf5-5b13-40a8-b5dd-66dbe8a94355
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975907873 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_errors.975907873
Directory /workspace/4.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.1840234494
Short name T143
Test name
Test status
Simulation time 101229838 ps
CPU time 2.94 seconds
Started Jun 06 02:31:14 PM PDT 24
Finished Jun 06 02:31:25 PM PDT 24
Peak memory 222916 kb
Host smart-079c2846-dd5e-4f54-b79e-c9535bd3beb3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840234494 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_intg_
err.1840234494
Directory /workspace/4.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.3841596080
Short name T998
Test name
Test status
Simulation time 28935919 ps
CPU time 1.63 seconds
Started Jun 06 02:31:15 PM PDT 24
Finished Jun 06 02:31:25 PM PDT 24
Peak memory 219128 kb
Host smart-c4fcd116-c38b-4bc6-919d-276dc75d6588
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841596080 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 5.lc_ctrl_csr_mem_rw_with_rand_reset.3841596080
Directory /workspace/5.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.1122553834
Short name T983
Test name
Test status
Simulation time 23883518 ps
CPU time 1.01 seconds
Started Jun 06 02:31:06 PM PDT 24
Finished Jun 06 02:31:09 PM PDT 24
Peak memory 209820 kb
Host smart-8894e933-d867-43d1-8b4c-deb255f91219
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122553834 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_csr_rw.1122553834
Directory /workspace/5.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.189129127
Short name T881
Test name
Test status
Simulation time 198966879 ps
CPU time 1.78 seconds
Started Jun 06 02:31:10 PM PDT 24
Finished Jun 06 02:31:16 PM PDT 24
Peak memory 209720 kb
Host smart-c21fce81-016a-47b5-809e-415959f9c568
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189129127 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 5.lc_ctrl_jtag_alert_test.189129127
Directory /workspace/5.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.3297118837
Short name T994
Test name
Test status
Simulation time 806120070 ps
CPU time 11.77 seconds
Started Jun 06 02:31:14 PM PDT 24
Finished Jun 06 02:31:34 PM PDT 24
Peak memory 209476 kb
Host smart-46d5d971-34a5-4c21-bb45-5b4b167dd2e2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297118837 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_aliasing.3297118837
Directory /workspace/5.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.1105432070
Short name T976
Test name
Test status
Simulation time 1458914626 ps
CPU time 7.33 seconds
Started Jun 06 02:31:10 PM PDT 24
Finished Jun 06 02:31:23 PM PDT 24
Peak memory 209408 kb
Host smart-13bf6b85-02d3-4ae1-9045-5890e814637a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105432070 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_bit_bash.1105432070
Directory /workspace/5.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.2731872940
Short name T883
Test name
Test status
Simulation time 87007479 ps
CPU time 1.73 seconds
Started Jun 06 02:31:15 PM PDT 24
Finished Jun 06 02:31:25 PM PDT 24
Peak memory 211216 kb
Host smart-7ad78e28-1dbc-4f73-ba4a-e7e944e70792
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731872940 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_hw_reset.2731872940
Directory /workspace/5.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1815792943
Short name T940
Test name
Test status
Simulation time 253186514 ps
CPU time 2.13 seconds
Started Jun 06 02:31:07 PM PDT 24
Finished Jun 06 02:31:13 PM PDT 24
Peak memory 222096 kb
Host smart-81f12671-8c3e-40dd-9644-bd4ddb107543
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181579
2943 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1815792943
Directory /workspace/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.1094540168
Short name T892
Test name
Test status
Simulation time 219092760 ps
CPU time 2.19 seconds
Started Jun 06 02:31:07 PM PDT 24
Finished Jun 06 02:31:13 PM PDT 24
Peak memory 209780 kb
Host smart-9e0d5996-c315-42d2-a020-d0708da30e8e
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094540168 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.lc_ctrl_jtag_csr_rw.1094540168
Directory /workspace/5.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.3520575217
Short name T924
Test name
Test status
Simulation time 37216827 ps
CPU time 1.82 seconds
Started Jun 06 02:31:07 PM PDT 24
Finished Jun 06 02:31:13 PM PDT 24
Peak memory 209928 kb
Host smart-fe8bb13d-a167-4c2c-9a3b-b20ee3eba11f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520575217 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.lc_ctrl_jtag_same_csr_outstanding.3520575217
Directory /workspace/5.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.2984452241
Short name T937
Test name
Test status
Simulation time 138765857 ps
CPU time 1.77 seconds
Started Jun 06 02:31:14 PM PDT 24
Finished Jun 06 02:31:23 PM PDT 24
Peak memory 212024 kb
Host smart-32e6cdbc-552e-418f-b994-61d14864e9e2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984452241 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl
_same_csr_outstanding.2984452241
Directory /workspace/5.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.1024230278
Short name T988
Test name
Test status
Simulation time 112349347 ps
CPU time 2.59 seconds
Started Jun 06 02:31:11 PM PDT 24
Finished Jun 06 02:31:20 PM PDT 24
Peak memory 218104 kb
Host smart-cead2d35-4a47-40e6-96ed-b8b38159d086
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024230278 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_errors.1024230278
Directory /workspace/5.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.2060321453
Short name T148
Test name
Test status
Simulation time 110580097 ps
CPU time 1.99 seconds
Started Jun 06 02:31:07 PM PDT 24
Finished Jun 06 02:31:13 PM PDT 24
Peak memory 218212 kb
Host smart-e467cc8e-830c-461b-b7f3-e2033d1d608d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060321453 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_intg_
err.2060321453
Directory /workspace/5.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.244174778
Short name T975
Test name
Test status
Simulation time 30032917 ps
CPU time 1.15 seconds
Started Jun 06 02:31:07 PM PDT 24
Finished Jun 06 02:31:11 PM PDT 24
Peak memory 218312 kb
Host smart-24d9888f-b975-458b-9f0e-8aca10699fd3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244174778 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 6.lc_ctrl_csr_mem_rw_with_rand_reset.244174778
Directory /workspace/6.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.3221903004
Short name T203
Test name
Test status
Simulation time 16680174 ps
CPU time 1.03 seconds
Started Jun 06 02:31:14 PM PDT 24
Finished Jun 06 02:31:22 PM PDT 24
Peak memory 209840 kb
Host smart-3c210e3d-3be6-4cb2-a61b-b2307531e8b7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221903004 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_csr_rw.3221903004
Directory /workspace/6.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.3040295879
Short name T946
Test name
Test status
Simulation time 74850642 ps
CPU time 0.9 seconds
Started Jun 06 02:31:06 PM PDT 24
Finished Jun 06 02:31:09 PM PDT 24
Peak memory 208996 kb
Host smart-2309d32c-759e-4581-919d-f33d29db1d3c
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040295879 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.lc_ctrl_jtag_alert_test.3040295879
Directory /workspace/6.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.1560346219
Short name T980
Test name
Test status
Simulation time 1451804719 ps
CPU time 11.67 seconds
Started Jun 06 02:31:15 PM PDT 24
Finished Jun 06 02:31:34 PM PDT 24
Peak memory 217104 kb
Host smart-b8525a90-e0cf-4569-9734-8db416aaa36a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560346219 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_aliasing.1560346219
Directory /workspace/6.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.1741278876
Short name T952
Test name
Test status
Simulation time 3730392835 ps
CPU time 21.22 seconds
Started Jun 06 02:31:08 PM PDT 24
Finished Jun 06 02:31:33 PM PDT 24
Peak memory 209888 kb
Host smart-6e8bb774-a913-46b6-a83f-60593fb43052
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741278876 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_bit_bash.1741278876
Directory /workspace/6.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.2606050689
Short name T955
Test name
Test status
Simulation time 47016345 ps
CPU time 1.31 seconds
Started Jun 06 02:31:09 PM PDT 24
Finished Jun 06 02:31:16 PM PDT 24
Peak memory 211152 kb
Host smart-b5fb0059-5228-42ed-a66e-315ba834d93d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606050689 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_hw_reset.2606050689
Directory /workspace/6.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3294440086
Short name T161
Test name
Test status
Simulation time 136423444 ps
CPU time 1.62 seconds
Started Jun 06 02:31:12 PM PDT 24
Finished Jun 06 02:31:21 PM PDT 24
Peak memory 219304 kb
Host smart-c6c53197-33ce-49cb-9a63-989743e9b0ef
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329444
0086 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3294440086
Directory /workspace/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.1913124392
Short name T938
Test name
Test status
Simulation time 391374883 ps
CPU time 1.24 seconds
Started Jun 06 02:31:15 PM PDT 24
Finished Jun 06 02:31:24 PM PDT 24
Peak memory 209776 kb
Host smart-39d916fd-0ed1-4c07-8635-480e6197b92c
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913124392 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.lc_ctrl_jtag_csr_rw.1913124392
Directory /workspace/6.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.287418321
Short name T954
Test name
Test status
Simulation time 47204567 ps
CPU time 1.48 seconds
Started Jun 06 02:31:11 PM PDT 24
Finished Jun 06 02:31:19 PM PDT 24
Peak memory 211980 kb
Host smart-851beeb1-c44e-4e4d-8119-6354c3ac07bb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287418321 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.lc_ctrl_jtag_same_csr_outstanding.287418321
Directory /workspace/6.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.1425841471
Short name T999
Test name
Test status
Simulation time 390629245 ps
CPU time 1.42 seconds
Started Jun 06 02:31:07 PM PDT 24
Finished Jun 06 02:31:12 PM PDT 24
Peak memory 209936 kb
Host smart-dec179e4-1dce-4cc8-b16b-84b74f1fa3a1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425841471 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl
_same_csr_outstanding.1425841471
Directory /workspace/6.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.2020849519
Short name T978
Test name
Test status
Simulation time 118348144 ps
CPU time 3.41 seconds
Started Jun 06 02:31:15 PM PDT 24
Finished Jun 06 02:31:26 PM PDT 24
Peak memory 218412 kb
Host smart-de13b362-dd53-478a-94be-d95656593daf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020849519 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_errors.2020849519
Directory /workspace/6.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.2127883986
Short name T926
Test name
Test status
Simulation time 28461384 ps
CPU time 1.65 seconds
Started Jun 06 02:31:14 PM PDT 24
Finished Jun 06 02:31:23 PM PDT 24
Peak memory 218412 kb
Host smart-cc778c0e-6c9a-4457-96f7-554ba99de139
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127883986 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 7.lc_ctrl_csr_mem_rw_with_rand_reset.2127883986
Directory /workspace/7.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.2324757052
Short name T204
Test name
Test status
Simulation time 13903936 ps
CPU time 1.07 seconds
Started Jun 06 02:31:16 PM PDT 24
Finished Jun 06 02:31:25 PM PDT 24
Peak memory 209888 kb
Host smart-de63effa-946a-4dd8-8a08-7558f128b7aa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324757052 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_csr_rw.2324757052
Directory /workspace/7.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.3413307627
Short name T877
Test name
Test status
Simulation time 120717802 ps
CPU time 1.81 seconds
Started Jun 06 02:31:09 PM PDT 24
Finished Jun 06 02:31:16 PM PDT 24
Peak memory 208948 kb
Host smart-f9bad622-9161-4758-bdfa-87a3e068d7fa
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413307627 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.lc_ctrl_jtag_alert_test.3413307627
Directory /workspace/7.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.2770932624
Short name T884
Test name
Test status
Simulation time 2437633360 ps
CPU time 5.72 seconds
Started Jun 06 02:31:10 PM PDT 24
Finished Jun 06 02:31:21 PM PDT 24
Peak memory 217276 kb
Host smart-a50056d8-deaf-4845-86a6-6f713f809f18
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770932624 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_aliasing.2770932624
Directory /workspace/7.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.3374107881
Short name T885
Test name
Test status
Simulation time 10762554488 ps
CPU time 8.76 seconds
Started Jun 06 02:31:04 PM PDT 24
Finished Jun 06 02:31:15 PM PDT 24
Peak memory 210212 kb
Host smart-0f6baed1-3f72-4d68-90d7-60ca05b97546
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374107881 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_bit_bash.3374107881
Directory /workspace/7.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.1348869355
Short name T879
Test name
Test status
Simulation time 274256123 ps
CPU time 1.45 seconds
Started Jun 06 02:31:15 PM PDT 24
Finished Jun 06 02:31:24 PM PDT 24
Peak memory 218076 kb
Host smart-2be69bd0-1cd2-4736-9332-1805d9e68d07
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348869355 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_hw_reset.1348869355
Directory /workspace/7.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2119196089
Short name T985
Test name
Test status
Simulation time 505701081 ps
CPU time 3.09 seconds
Started Jun 06 02:31:05 PM PDT 24
Finished Jun 06 02:31:10 PM PDT 24
Peak memory 218208 kb
Host smart-23dfe65b-49ad-4110-af22-3f1c8fd67937
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211919
6089 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2119196089
Directory /workspace/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.2841315411
Short name T921
Test name
Test status
Simulation time 151208400 ps
CPU time 1.46 seconds
Started Jun 06 02:31:21 PM PDT 24
Finished Jun 06 02:31:30 PM PDT 24
Peak memory 209688 kb
Host smart-4c110760-bad0-493c-b674-ac3fb7384dac
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841315411 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.lc_ctrl_jtag_csr_rw.2841315411
Directory /workspace/7.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.3480698256
Short name T990
Test name
Test status
Simulation time 44833277 ps
CPU time 1.46 seconds
Started Jun 06 02:31:09 PM PDT 24
Finished Jun 06 02:31:15 PM PDT 24
Peak memory 218160 kb
Host smart-ab9ac5d5-5e33-49f3-b122-a63254897b68
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480698256 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.lc_ctrl_jtag_same_csr_outstanding.3480698256
Directory /workspace/7.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.1893063061
Short name T971
Test name
Test status
Simulation time 65622787 ps
CPU time 1.38 seconds
Started Jun 06 02:31:11 PM PDT 24
Finished Jun 06 02:31:17 PM PDT 24
Peak memory 217912 kb
Host smart-6e23606b-8305-4227-b47d-57a72f83be2c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893063061 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl
_same_csr_outstanding.1893063061
Directory /workspace/7.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.3662574392
Short name T935
Test name
Test status
Simulation time 272470932 ps
CPU time 2.4 seconds
Started Jun 06 02:31:14 PM PDT 24
Finished Jun 06 02:31:24 PM PDT 24
Peak memory 218148 kb
Host smart-ec7f24f0-49d2-40f4-92c4-85a8f3df718d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662574392 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_errors.3662574392
Directory /workspace/7.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.3639080559
Short name T157
Test name
Test status
Simulation time 67353129 ps
CPU time 1.99 seconds
Started Jun 06 02:31:11 PM PDT 24
Finished Jun 06 02:31:18 PM PDT 24
Peak memory 221868 kb
Host smart-3582bbce-9ebe-4f6d-9e0b-65415e351240
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639080559 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_intg_
err.3639080559
Directory /workspace/7.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.3807311269
Short name T146
Test name
Test status
Simulation time 54244604 ps
CPU time 1.39 seconds
Started Jun 06 02:31:12 PM PDT 24
Finished Jun 06 02:31:21 PM PDT 24
Peak memory 220288 kb
Host smart-f0cc4d49-9523-42c6-8c35-7a0ae1b760a0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807311269 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 8.lc_ctrl_csr_mem_rw_with_rand_reset.3807311269
Directory /workspace/8.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.1933677811
Short name T915
Test name
Test status
Simulation time 35237896 ps
CPU time 0.93 seconds
Started Jun 06 02:31:14 PM PDT 24
Finished Jun 06 02:31:23 PM PDT 24
Peak memory 209880 kb
Host smart-7055240e-a8ef-4c2e-b157-ede1ddb662ae
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933677811 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_csr_rw.1933677811
Directory /workspace/8.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.807898825
Short name T880
Test name
Test status
Simulation time 296173588 ps
CPU time 1.24 seconds
Started Jun 06 02:31:13 PM PDT 24
Finished Jun 06 02:31:21 PM PDT 24
Peak memory 209712 kb
Host smart-7126595c-5d4e-4cef-913b-e495123a60ab
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807898825 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 8.lc_ctrl_jtag_alert_test.807898825
Directory /workspace/8.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.1229771279
Short name T977
Test name
Test status
Simulation time 365501208 ps
CPU time 8.56 seconds
Started Jun 06 02:31:08 PM PDT 24
Finished Jun 06 02:31:20 PM PDT 24
Peak memory 209476 kb
Host smart-113906a1-276d-459b-8346-24716287c3c1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229771279 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_aliasing.1229771279
Directory /workspace/8.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.1808765057
Short name T987
Test name
Test status
Simulation time 16869973887 ps
CPU time 27.39 seconds
Started Jun 06 02:31:14 PM PDT 24
Finished Jun 06 02:31:49 PM PDT 24
Peak memory 209188 kb
Host smart-fb4cdde1-033c-45cc-ade1-e6b5aa97e198
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808765057 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_bit_bash.1808765057
Directory /workspace/8.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.360356542
Short name T902
Test name
Test status
Simulation time 186313389 ps
CPU time 4.73 seconds
Started Jun 06 02:31:12 PM PDT 24
Finished Jun 06 02:31:23 PM PDT 24
Peak memory 211492 kb
Host smart-70d7bd52-2d96-42ac-9e8d-55c75f6a8ab9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360356542 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 8.lc_ctrl_jtag_csr_hw_reset.360356542
Directory /workspace/8.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3839944727
Short name T897
Test name
Test status
Simulation time 116986798 ps
CPU time 4.02 seconds
Started Jun 06 02:31:12 PM PDT 24
Finished Jun 06 02:31:24 PM PDT 24
Peak memory 223628 kb
Host smart-b1a5981b-3c9f-464d-88ae-3aeb6a36e8ae
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383994
4727 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3839944727
Directory /workspace/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.1094272254
Short name T887
Test name
Test status
Simulation time 53936262 ps
CPU time 1.36 seconds
Started Jun 06 02:31:16 PM PDT 24
Finished Jun 06 02:31:25 PM PDT 24
Peak memory 209772 kb
Host smart-490346dd-b556-483c-821a-29e894700cdc
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094272254 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.lc_ctrl_jtag_csr_rw.1094272254
Directory /workspace/8.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.1659114117
Short name T925
Test name
Test status
Simulation time 99768526 ps
CPU time 1.51 seconds
Started Jun 06 02:31:12 PM PDT 24
Finished Jun 06 02:31:21 PM PDT 24
Peak memory 212116 kb
Host smart-e79cea99-a0ac-4e69-8a7f-71f0f2bb3da8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659114117 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.lc_ctrl_jtag_same_csr_outstanding.1659114117
Directory /workspace/8.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.1730531756
Short name T221
Test name
Test status
Simulation time 141261237 ps
CPU time 1.07 seconds
Started Jun 06 02:31:12 PM PDT 24
Finished Jun 06 02:31:20 PM PDT 24
Peak memory 209708 kb
Host smart-04da2d66-a7bf-48c0-bd55-a32cfb9cb918
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730531756 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl
_same_csr_outstanding.1730531756
Directory /workspace/8.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.317646792
Short name T140
Test name
Test status
Simulation time 122318215 ps
CPU time 3.34 seconds
Started Jun 06 02:31:14 PM PDT 24
Finished Jun 06 02:31:25 PM PDT 24
Peak memory 218236 kb
Host smart-1af85c71-53c6-4678-bdd3-7a5a3cb97ee4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317646792 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_errors.317646792
Directory /workspace/8.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.4022448218
Short name T149
Test name
Test status
Simulation time 90821591 ps
CPU time 3.02 seconds
Started Jun 06 02:31:20 PM PDT 24
Finished Jun 06 02:31:30 PM PDT 24
Peak memory 218104 kb
Host smart-5ef84901-4a93-466d-83e3-8e63336d388f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022448218 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_intg_
err.4022448218
Directory /workspace/8.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.2231222900
Short name T931
Test name
Test status
Simulation time 171694570 ps
CPU time 1.35 seconds
Started Jun 06 02:31:17 PM PDT 24
Finished Jun 06 02:31:26 PM PDT 24
Peak memory 219228 kb
Host smart-3a1efde9-70f9-4c00-955f-ffdd395f3ec6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231222900 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 9.lc_ctrl_csr_mem_rw_with_rand_reset.2231222900
Directory /workspace/9.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.1243409340
Short name T967
Test name
Test status
Simulation time 103685440 ps
CPU time 0.88 seconds
Started Jun 06 02:31:09 PM PDT 24
Finished Jun 06 02:31:15 PM PDT 24
Peak memory 209564 kb
Host smart-b665e5f9-5d95-439b-8948-08af8d7fff5a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243409340 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_csr_rw.1243409340
Directory /workspace/9.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.697244801
Short name T162
Test name
Test status
Simulation time 59167208 ps
CPU time 0.87 seconds
Started Jun 06 02:31:10 PM PDT 24
Finished Jun 06 02:31:16 PM PDT 24
Peak memory 209688 kb
Host smart-e1ecb527-b182-462b-8c1d-cd8b61287fc8
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697244801 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 9.lc_ctrl_jtag_alert_test.697244801
Directory /workspace/9.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.1969564707
Short name T951
Test name
Test status
Simulation time 1775976680 ps
CPU time 8.33 seconds
Started Jun 06 02:31:13 PM PDT 24
Finished Jun 06 02:31:29 PM PDT 24
Peak memory 217180 kb
Host smart-0ecfd51e-0b20-44ed-bd46-7b3df87c3f44
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969564707 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_aliasing.1969564707
Directory /workspace/9.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.3807572310
Short name T953
Test name
Test status
Simulation time 2196884515 ps
CPU time 45.71 seconds
Started Jun 06 02:31:13 PM PDT 24
Finished Jun 06 02:32:06 PM PDT 24
Peak memory 209688 kb
Host smart-f53a0b1f-1392-46ed-adfb-fd03c9b7f537
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807572310 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_bit_bash.3807572310
Directory /workspace/9.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.475199665
Short name T989
Test name
Test status
Simulation time 87560484 ps
CPU time 1.45 seconds
Started Jun 06 02:31:14 PM PDT 24
Finished Jun 06 02:31:24 PM PDT 24
Peak memory 211200 kb
Host smart-f2dac758-02fe-4e99-8507-5ab9ebd966d3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475199665 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 9.lc_ctrl_jtag_csr_hw_reset.475199665
Directory /workspace/9.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.1704341024
Short name T939
Test name
Test status
Simulation time 37170359 ps
CPU time 1.23 seconds
Started Jun 06 02:31:08 PM PDT 24
Finished Jun 06 02:31:13 PM PDT 24
Peak memory 209776 kb
Host smart-4b02f6c2-39b0-4a69-bbde-0093d4d0d4b1
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704341024 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.lc_ctrl_jtag_csr_rw.1704341024
Directory /workspace/9.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.3288102199
Short name T218
Test name
Test status
Simulation time 29573663 ps
CPU time 1.42 seconds
Started Jun 06 02:31:23 PM PDT 24
Finished Jun 06 02:31:31 PM PDT 24
Peak memory 210020 kb
Host smart-a65512af-526e-4cbc-96da-3484d617620a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288102199 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.lc_ctrl_jtag_same_csr_outstanding.3288102199
Directory /workspace/9.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.4147940088
Short name T981
Test name
Test status
Simulation time 26307060 ps
CPU time 1.18 seconds
Started Jun 06 02:31:18 PM PDT 24
Finished Jun 06 02:31:27 PM PDT 24
Peak memory 217900 kb
Host smart-4712333f-bebe-4c76-ae87-3852f4e7a101
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147940088 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl
_same_csr_outstanding.4147940088
Directory /workspace/9.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.3383917703
Short name T969
Test name
Test status
Simulation time 624338566 ps
CPU time 3.67 seconds
Started Jun 06 02:31:16 PM PDT 24
Finished Jun 06 02:31:28 PM PDT 24
Peak memory 218088 kb
Host smart-e2c4a7ea-af34-42fe-b0e0-57b325d25f29
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383917703 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_errors.3383917703
Directory /workspace/9.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.2311360152
Short name T142
Test name
Test status
Simulation time 59430486 ps
CPU time 2.63 seconds
Started Jun 06 02:31:13 PM PDT 24
Finished Jun 06 02:31:22 PM PDT 24
Peak memory 218248 kb
Host smart-abd2e555-0552-444c-9798-eb074133276c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311360152 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_intg_
err.2311360152
Directory /workspace/9.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_alert_test.2043793846
Short name T845
Test name
Test status
Simulation time 17081192 ps
CPU time 1.08 seconds
Started Jun 06 01:09:21 PM PDT 24
Finished Jun 06 01:09:24 PM PDT 24
Peak memory 208628 kb
Host smart-ed0ca773-4ca9-4986-a8f9-e1a3ed8e0978
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043793846 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_alert_test.2043793846
Directory /workspace/0.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.lc_ctrl_errors.1206078349
Short name T691
Test name
Test status
Simulation time 232739270 ps
CPU time 8.47 seconds
Started Jun 06 01:09:01 PM PDT 24
Finished Jun 06 01:09:10 PM PDT 24
Peak memory 218016 kb
Host smart-5e1b110e-a3c5-48e0-9b8e-e839dd469e37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206078349 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_errors.1206078349
Directory /workspace/0.lc_ctrl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_access.1314265692
Short name T27
Test name
Test status
Simulation time 1500561661 ps
CPU time 2.57 seconds
Started Jun 06 01:09:13 PM PDT 24
Finished Jun 06 01:09:16 PM PDT 24
Peak memory 209512 kb
Host smart-0751d565-83e3-4e63-8a8b-24d624b0f257
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314265692 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_access.1314265692
Directory /workspace/0.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_errors.1493351880
Short name T49
Test name
Test status
Simulation time 12689785552 ps
CPU time 35.63 seconds
Started Jun 06 01:09:13 PM PDT 24
Finished Jun 06 01:09:49 PM PDT 24
Peak memory 218880 kb
Host smart-1220fa9a-f52c-4825-84a7-2409cbcc384b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493351880 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_er
rors.1493351880
Directory /workspace/0.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_priority.79712712
Short name T544
Test name
Test status
Simulation time 474069452 ps
CPU time 5.89 seconds
Started Jun 06 01:09:12 PM PDT 24
Finished Jun 06 01:09:19 PM PDT 24
Peak memory 217116 kb
Host smart-14f89884-74fa-449d-b435-823e4637688c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79712712 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priority
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_priority.79712712
Directory /workspace/0.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_prog_failure.1569407247
Short name T486
Test name
Test status
Simulation time 553605878 ps
CPU time 4.78 seconds
Started Jun 06 01:09:13 PM PDT 24
Finished Jun 06 01:09:19 PM PDT 24
Peak memory 217856 kb
Host smart-2d05f222-2410-49e8-a72c-f5e840adb2f1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569407247 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag
_prog_failure.1569407247
Directory /workspace/0.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_regwen_during_op.455128585
Short name T71
Test name
Test status
Simulation time 848750204 ps
CPU time 12.38 seconds
Started Jun 06 01:09:11 PM PDT 24
Finished Jun 06 01:09:24 PM PDT 24
Peak memory 217636 kb
Host smart-cd385249-a732-4808-92ee-2b64610f0af5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455128585 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_j
tag_regwen_during_op.455128585
Directory /workspace/0.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_smoke.2990111944
Short name T414
Test name
Test status
Simulation time 544241669 ps
CPU time 4.41 seconds
Started Jun 06 01:09:13 PM PDT 24
Finished Jun 06 01:09:18 PM PDT 24
Peak memory 217624 kb
Host smart-0435e3c2-bec4-446c-b076-2e15d5a569a1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990111944 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_smoke.
2990111944
Directory /workspace/0.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_failure.1434247965
Short name T629
Test name
Test status
Simulation time 1168813884 ps
CPU time 40.64 seconds
Started Jun 06 01:09:11 PM PDT 24
Finished Jun 06 01:09:52 PM PDT 24
Peak memory 252736 kb
Host smart-842504a9-ca30-426d-8567-2f6fa7722be7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434247965 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jta
g_state_failure.1434247965
Directory /workspace/0.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_post_trans.4018281017
Short name T622
Test name
Test status
Simulation time 564870947 ps
CPU time 12.33 seconds
Started Jun 06 01:09:13 PM PDT 24
Finished Jun 06 01:09:26 PM PDT 24
Peak memory 245996 kb
Host smart-b302ad2d-96db-469e-b38e-ffb4ff6381af
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018281017 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_state_post_trans.4018281017
Directory /workspace/0.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_prog_failure.2285651091
Short name T354
Test name
Test status
Simulation time 15019967 ps
CPU time 1.59 seconds
Started Jun 06 01:09:01 PM PDT 24
Finished Jun 06 01:09:03 PM PDT 24
Peak memory 218212 kb
Host smart-99d7ffbe-0bb3-4df8-97b9-452f4abb7982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285651091 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_prog_failure.2285651091
Directory /workspace/0.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_regwen_during_op.3538740200
Short name T202
Test name
Test status
Simulation time 215023510 ps
CPU time 5.52 seconds
Started Jun 06 01:09:13 PM PDT 24
Finished Jun 06 01:09:19 PM PDT 24
Peak memory 222824 kb
Host smart-6fd8287c-9809-42a1-8f19-dc694319ba35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538740200 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_regwen_during_op.3538740200
Directory /workspace/0.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_cm.2665351373
Short name T96
Test name
Test status
Simulation time 520543067 ps
CPU time 22.64 seconds
Started Jun 06 01:09:20 PM PDT 24
Finished Jun 06 01:09:43 PM PDT 24
Peak memory 268188 kb
Host smart-25088285-ed22-4ae4-ba1a-1803ddb19ddc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665351373 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_cm.2665351373
Directory /workspace/0.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_mubi.872317103
Short name T538
Test name
Test status
Simulation time 408557003 ps
CPU time 18.12 seconds
Started Jun 06 01:09:12 PM PDT 24
Finished Jun 06 01:09:31 PM PDT 24
Peak memory 218976 kb
Host smart-41bdfcf2-0558-4311-a3bd-84577c4b2cd4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872317103 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_mubi.872317103
Directory /workspace/0.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_digest.1138025323
Short name T106
Test name
Test status
Simulation time 226831015 ps
CPU time 7.55 seconds
Started Jun 06 01:09:20 PM PDT 24
Finished Jun 06 01:09:29 PM PDT 24
Peak memory 217940 kb
Host smart-a7d409ba-ca2f-4af6-a7af-0eb4b108c31e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138025323 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_di
gest.1138025323
Directory /workspace/0.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_mux.3205130937
Short name T415
Test name
Test status
Simulation time 356444565 ps
CPU time 9.83 seconds
Started Jun 06 01:09:22 PM PDT 24
Finished Jun 06 01:09:34 PM PDT 24
Peak memory 218300 kb
Host smart-4ff73e67-cf05-4acf-b7e0-4987d6a06359
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205130937 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_mux.3
205130937
Directory /workspace/0.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/0.lc_ctrl_security_escalation.896000484
Short name T570
Test name
Test status
Simulation time 1063681554 ps
CPU time 11.94 seconds
Started Jun 06 01:09:01 PM PDT 24
Finished Jun 06 01:09:14 PM PDT 24
Peak memory 224700 kb
Host smart-8811079d-8e72-4c1a-bff1-4fb811c9fc2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896000484 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_security_escalation.896000484
Directory /workspace/0.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/0.lc_ctrl_smoke.2680096327
Short name T739
Test name
Test status
Simulation time 38618833 ps
CPU time 1.68 seconds
Started Jun 06 01:09:01 PM PDT 24
Finished Jun 06 01:09:04 PM PDT 24
Peak memory 213588 kb
Host smart-b9e62a63-a0f4-48e5-b0d2-ef6fbe343ad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680096327 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_smoke.2680096327
Directory /workspace/0.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_failure.342851488
Short name T654
Test name
Test status
Simulation time 227397465 ps
CPU time 20.84 seconds
Started Jun 06 01:09:01 PM PDT 24
Finished Jun 06 01:09:23 PM PDT 24
Peak memory 250916 kb
Host smart-25bc9db7-ab7a-4364-9d18-87076942cde1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342851488 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_failure.342851488
Directory /workspace/0.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_post_trans.1145061525
Short name T251
Test name
Test status
Simulation time 425274232 ps
CPU time 6.36 seconds
Started Jun 06 01:09:02 PM PDT 24
Finished Jun 06 01:09:09 PM PDT 24
Peak memory 250740 kb
Host smart-9ba528d4-6b2f-4b77-9ef2-673a6c831342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145061525 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_post_trans.1145061525
Directory /workspace/0.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all.3614934609
Short name T298
Test name
Test status
Simulation time 3056364438 ps
CPU time 95.87 seconds
Started Jun 06 01:09:24 PM PDT 24
Finished Jun 06 01:11:00 PM PDT 24
Peak memory 246480 kb
Host smart-3558a67a-bc39-4839-b1a6-eeb4bb73c817
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614934609 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.lc_ctrl_stress_all.3614934609
Directory /workspace/0.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.lc_ctrl_volatile_unlock_smoke.2782384118
Short name T193
Test name
Test status
Simulation time 13465691 ps
CPU time 0.82 seconds
Started Jun 06 01:09:00 PM PDT 24
Finished Jun 06 01:09:02 PM PDT 24
Peak memory 208684 kb
Host smart-0d950eaa-127a-47a7-b5b6-acafd1a788d0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782384118 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ct
rl_volatile_unlock_smoke.2782384118
Directory /workspace/0.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_alert_test.3358178493
Short name T365
Test name
Test status
Simulation time 50923618 ps
CPU time 0.84 seconds
Started Jun 06 01:09:34 PM PDT 24
Finished Jun 06 01:09:36 PM PDT 24
Peak memory 209540 kb
Host smart-27d109ad-42d8-4a33-9c42-326b11a8f065
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358178493 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_alert_test.3358178493
Directory /workspace/1.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.lc_ctrl_claim_transition_if.3342072804
Short name T488
Test name
Test status
Simulation time 10437291 ps
CPU time 0.94 seconds
Started Jun 06 01:09:20 PM PDT 24
Finished Jun 06 01:09:22 PM PDT 24
Peak memory 208724 kb
Host smart-751fc957-f04d-4d39-80e8-5ca433fa6368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342072804 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_claim_transition_if.3342072804
Directory /workspace/1.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/1.lc_ctrl_errors.3128992458
Short name T740
Test name
Test status
Simulation time 670360505 ps
CPU time 10.36 seconds
Started Jun 06 01:09:22 PM PDT 24
Finished Jun 06 01:09:34 PM PDT 24
Peak memory 218004 kb
Host smart-0df0631f-b486-4e3a-a4d8-fb3a519ccf87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128992458 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_errors.3128992458
Directory /workspace/1.lc_ctrl_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_access.2348855456
Short name T655
Test name
Test status
Simulation time 175179566 ps
CPU time 2.99 seconds
Started Jun 06 01:09:23 PM PDT 24
Finished Jun 06 01:09:27 PM PDT 24
Peak memory 209496 kb
Host smart-dd7055a0-bda9-422b-8bbc-1d12b24c00d7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348855456 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_access.2348855456
Directory /workspace/1.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_errors.738734033
Short name T561
Test name
Test status
Simulation time 1788649338 ps
CPU time 48.27 seconds
Started Jun 06 01:09:22 PM PDT 24
Finished Jun 06 01:10:11 PM PDT 24
Peak memory 217904 kb
Host smart-54bd21d0-dd9a-4a00-ad6f-a371e9360cf9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738734033 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_err
ors.738734033
Directory /workspace/1.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_priority.3306701800
Short name T422
Test name
Test status
Simulation time 867124636 ps
CPU time 5.09 seconds
Started Jun 06 01:09:21 PM PDT 24
Finished Jun 06 01:09:27 PM PDT 24
Peak memory 217388 kb
Host smart-7ef2cb6f-e63e-4537-a187-abcf6952a157
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306701800 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_priority.3
306701800
Directory /workspace/1.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_prog_failure.2105397486
Short name T726
Test name
Test status
Simulation time 494260757 ps
CPU time 4.72 seconds
Started Jun 06 01:09:21 PM PDT 24
Finished Jun 06 01:09:27 PM PDT 24
Peak memory 217976 kb
Host smart-47e5c411-96aa-4fb1-a46b-87cbcbba4afe
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105397486 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag
_prog_failure.2105397486
Directory /workspace/1.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_regwen_during_op.1599943228
Short name T765
Test name
Test status
Simulation time 1227386045 ps
CPU time 15.44 seconds
Started Jun 06 01:09:30 PM PDT 24
Finished Jun 06 01:09:46 PM PDT 24
Peak memory 217636 kb
Host smart-8d809d4d-36ba-4f69-899d-3b25cfbf3218
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599943228 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_regwen_during_op.1599943228
Directory /workspace/1.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_smoke.1321402414
Short name T618
Test name
Test status
Simulation time 3166646151 ps
CPU time 8.21 seconds
Started Jun 06 01:09:21 PM PDT 24
Finished Jun 06 01:09:30 PM PDT 24
Peak memory 217720 kb
Host smart-bb41c7f3-3fb8-4e71-9565-204b275824b1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321402414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_smoke.
1321402414
Directory /workspace/1.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_failure.1264309517
Short name T338
Test name
Test status
Simulation time 9608237165 ps
CPU time 57.05 seconds
Started Jun 06 01:09:21 PM PDT 24
Finished Jun 06 01:10:19 PM PDT 24
Peak memory 280940 kb
Host smart-61e45af1-c407-4c43-a177-c2d4ac70df12
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264309517 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jta
g_state_failure.1264309517
Directory /workspace/1.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_post_trans.4142413736
Short name T791
Test name
Test status
Simulation time 647087479 ps
CPU time 16.04 seconds
Started Jun 06 01:09:23 PM PDT 24
Finished Jun 06 01:09:40 PM PDT 24
Peak memory 250932 kb
Host smart-84efd792-f412-4f01-a502-b7c02fc6ef68
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142413736 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_state_post_trans.4142413736
Directory /workspace/1.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_prog_failure.1368048962
Short name T758
Test name
Test status
Simulation time 89606343 ps
CPU time 3.08 seconds
Started Jun 06 01:09:21 PM PDT 24
Finished Jun 06 01:09:25 PM PDT 24
Peak memory 217944 kb
Host smart-b1c04512-53f1-4c98-b64e-046bf8434583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368048962 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_prog_failure.1368048962
Directory /workspace/1.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_regwen_during_op.769880347
Short name T744
Test name
Test status
Simulation time 793129748 ps
CPU time 13.61 seconds
Started Jun 06 01:09:21 PM PDT 24
Finished Jun 06 01:09:36 PM PDT 24
Peak memory 217580 kb
Host smart-25806fd2-6326-4678-a422-0900c45e1235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769880347 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_regwen_during_op.769880347
Directory /workspace/1.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_cm.3426458710
Short name T111
Test name
Test status
Simulation time 652400129 ps
CPU time 38.69 seconds
Started Jun 06 01:09:31 PM PDT 24
Finished Jun 06 01:10:11 PM PDT 24
Peak memory 270796 kb
Host smart-f9d26028-820e-4c8f-a3ee-62ac31c815ca
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426458710 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_cm.3426458710
Directory /workspace/1.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_mubi.1127790088
Short name T593
Test name
Test status
Simulation time 552753248 ps
CPU time 14.26 seconds
Started Jun 06 01:09:30 PM PDT 24
Finished Jun 06 01:09:45 PM PDT 24
Peak memory 226100 kb
Host smart-1b844e9e-f5ca-4a63-9290-f57895f79674
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127790088 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_mubi.1127790088
Directory /workspace/1.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_digest.4057599003
Short name T402
Test name
Test status
Simulation time 201778161 ps
CPU time 6.79 seconds
Started Jun 06 01:09:30 PM PDT 24
Finished Jun 06 01:09:38 PM PDT 24
Peak memory 217928 kb
Host smart-658decc0-57a9-4d32-af1d-d7d411612ba3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057599003 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_di
gest.4057599003
Directory /workspace/1.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_mux.535715447
Short name T469
Test name
Test status
Simulation time 412956900 ps
CPU time 10.92 seconds
Started Jun 06 01:09:28 PM PDT 24
Finished Jun 06 01:09:39 PM PDT 24
Peak memory 218012 kb
Host smart-b43ef46a-d9ed-48b3-9c99-b581b460ee81
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535715447 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_mux.535715447
Directory /workspace/1.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/1.lc_ctrl_security_escalation.2950691050
Short name T753
Test name
Test status
Simulation time 340309177 ps
CPU time 12.03 seconds
Started Jun 06 01:09:22 PM PDT 24
Finished Jun 06 01:09:35 PM PDT 24
Peak memory 226068 kb
Host smart-aea8a079-357e-45e8-b070-e4eb0cd8eaae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950691050 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_security_escalation.2950691050
Directory /workspace/1.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/1.lc_ctrl_smoke.2646628082
Short name T314
Test name
Test status
Simulation time 832762988 ps
CPU time 3.41 seconds
Started Jun 06 01:09:22 PM PDT 24
Finished Jun 06 01:09:26 PM PDT 24
Peak memory 217644 kb
Host smart-841041e2-7f29-4e92-9990-3a7091348c9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646628082 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_smoke.2646628082
Directory /workspace/1.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_failure.3220354166
Short name T721
Test name
Test status
Simulation time 504742717 ps
CPU time 17.3 seconds
Started Jun 06 01:09:22 PM PDT 24
Finished Jun 06 01:09:40 PM PDT 24
Peak memory 251124 kb
Host smart-a54d39df-6c91-4dbf-a1c6-75a89b4b6c93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220354166 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_failure.3220354166
Directory /workspace/1.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_post_trans.1528305831
Short name T305
Test name
Test status
Simulation time 231325659 ps
CPU time 3.49 seconds
Started Jun 06 01:09:23 PM PDT 24
Finished Jun 06 01:09:27 PM PDT 24
Peak memory 226428 kb
Host smart-d3172f76-92ef-40f4-867a-acafe8727932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528305831 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_post_trans.1528305831
Directory /workspace/1.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_stress_all.3279682311
Short name T377
Test name
Test status
Simulation time 5441237555 ps
CPU time 59.62 seconds
Started Jun 06 01:09:31 PM PDT 24
Finished Jun 06 01:10:31 PM PDT 24
Peak memory 251052 kb
Host smart-c285bab0-9608-45e6-b37b-f0a8e2618493
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279682311 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.lc_ctrl_stress_all.3279682311
Directory /workspace/1.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.lc_ctrl_stress_all_with_rand_reset.1265225019
Short name T184
Test name
Test status
Simulation time 56832484595 ps
CPU time 1071.12 seconds
Started Jun 06 01:09:29 PM PDT 24
Finished Jun 06 01:27:21 PM PDT 24
Peak memory 283964 kb
Host smart-b61bbbd5-6e4e-4515-971b-617a7da77d02
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1265225019 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_stress_all_with_rand_reset.1265225019
Directory /workspace/1.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.lc_ctrl_volatile_unlock_smoke.3397597947
Short name T117
Test name
Test status
Simulation time 118904792 ps
CPU time 0.74 seconds
Started Jun 06 01:09:23 PM PDT 24
Finished Jun 06 01:09:25 PM PDT 24
Peak memory 208284 kb
Host smart-2cd8ced6-9704-4fdc-9a3f-2ba6f2a134cd
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397597947 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ct
rl_volatile_unlock_smoke.3397597947
Directory /workspace/1.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_alert_test.380706468
Short name T594
Test name
Test status
Simulation time 62490069 ps
CPU time 0.98 seconds
Started Jun 06 01:11:02 PM PDT 24
Finished Jun 06 01:11:04 PM PDT 24
Peak memory 208568 kb
Host smart-662e2255-7e4d-450e-99b9-0604c0430874
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380706468 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_alert_test.380706468
Directory /workspace/10.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.lc_ctrl_errors.112847371
Short name T856
Test name
Test status
Simulation time 1609002822 ps
CPU time 11.85 seconds
Started Jun 06 01:11:00 PM PDT 24
Finished Jun 06 01:11:13 PM PDT 24
Peak memory 217972 kb
Host smart-0905efe4-4956-4608-80a4-38b3e9c28e95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112847371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_errors.112847371
Directory /workspace/10.lc_ctrl_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_access.1945196135
Short name T633
Test name
Test status
Simulation time 151267008 ps
CPU time 2.65 seconds
Started Jun 06 01:10:59 PM PDT 24
Finished Jun 06 01:11:03 PM PDT 24
Peak memory 209496 kb
Host smart-f8bac4ba-275e-465b-a15c-1de6050060e0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945196135 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_access.1945196135
Directory /workspace/10.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_prog_failure.3798130923
Short name T343
Test name
Test status
Simulation time 1090412125 ps
CPU time 27.69 seconds
Started Jun 06 01:10:58 PM PDT 24
Finished Jun 06 01:11:27 PM PDT 24
Peak memory 217892 kb
Host smart-b2149215-2cc0-4139-ac00-ed6c13e90ddd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798130923 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jta
g_prog_failure.3798130923
Directory /workspace/10.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_smoke.2973744794
Short name T756
Test name
Test status
Simulation time 358393006 ps
CPU time 3.37 seconds
Started Jun 06 01:11:00 PM PDT 24
Finished Jun 06 01:11:04 PM PDT 24
Peak memory 217648 kb
Host smart-2f80ee2f-3fb6-452d-9532-9b4376979ca3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973744794 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_smoke
.2973744794
Directory /workspace/10.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_failure.1548426833
Short name T115
Test name
Test status
Simulation time 3269823248 ps
CPU time 56.11 seconds
Started Jun 06 01:10:59 PM PDT 24
Finished Jun 06 01:11:56 PM PDT 24
Peak memory 271564 kb
Host smart-504b34cc-d73c-4036-a920-216dfbdd06eb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548426833 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jt
ag_state_failure.1548426833
Directory /workspace/10.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_post_trans.4054162705
Short name T746
Test name
Test status
Simulation time 1416248348 ps
CPU time 15.1 seconds
Started Jun 06 01:11:02 PM PDT 24
Finished Jun 06 01:11:18 PM PDT 24
Peak memory 250904 kb
Host smart-1f230d3d-0c6f-43e4-9feb-13cc36ce1bb4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054162705 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl
_jtag_state_post_trans.4054162705
Directory /workspace/10.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_prog_failure.3508648547
Short name T638
Test name
Test status
Simulation time 41498955 ps
CPU time 1.87 seconds
Started Jun 06 01:10:57 PM PDT 24
Finished Jun 06 01:11:00 PM PDT 24
Peak memory 217972 kb
Host smart-a76075ec-e287-4d98-af7f-b020eecec4de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508648547 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_prog_failure.3508648547
Directory /workspace/10.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_mubi.3427440121
Short name T468
Test name
Test status
Simulation time 2559159941 ps
CPU time 17.11 seconds
Started Jun 06 01:11:00 PM PDT 24
Finished Jun 06 01:11:18 PM PDT 24
Peak memory 219320 kb
Host smart-a908e1b8-100d-4afb-9ccc-39c49af233df
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427440121 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_mubi.3427440121
Directory /workspace/10.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_digest.3097872731
Short name T843
Test name
Test status
Simulation time 1229159353 ps
CPU time 8.56 seconds
Started Jun 06 01:11:01 PM PDT 24
Finished Jun 06 01:11:10 PM PDT 24
Peak memory 218156 kb
Host smart-64ac17dc-fd90-475a-b7c5-3f9b644d3623
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097872731 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_d
igest.3097872731
Directory /workspace/10.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_mux.4124752886
Short name T529
Test name
Test status
Simulation time 732395164 ps
CPU time 13.16 seconds
Started Jun 06 01:10:59 PM PDT 24
Finished Jun 06 01:11:13 PM PDT 24
Peak memory 218064 kb
Host smart-117eaf92-a586-4bf4-abe0-d4e168087809
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124752886 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_mux.
4124752886
Directory /workspace/10.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/10.lc_ctrl_security_escalation.1974615066
Short name T540
Test name
Test status
Simulation time 358151350 ps
CPU time 8.73 seconds
Started Jun 06 01:10:59 PM PDT 24
Finished Jun 06 01:11:09 PM PDT 24
Peak memory 218092 kb
Host smart-52944c23-a793-4ea0-ab7c-04a62aa38fe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974615066 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_security_escalation.1974615066
Directory /workspace/10.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/10.lc_ctrl_smoke.2779560742
Short name T92
Test name
Test status
Simulation time 124023317 ps
CPU time 6.24 seconds
Started Jun 06 01:11:00 PM PDT 24
Finished Jun 06 01:11:08 PM PDT 24
Peak memory 217688 kb
Host smart-0dd932fb-47a3-4784-af9d-594157cce4b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779560742 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_smoke.2779560742
Directory /workspace/10.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_failure.1047884969
Short name T525
Test name
Test status
Simulation time 676690475 ps
CPU time 22.68 seconds
Started Jun 06 01:10:59 PM PDT 24
Finished Jun 06 01:11:23 PM PDT 24
Peak memory 250928 kb
Host smart-8047c66f-3e29-4417-8f4f-0fa7f1ad3704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047884969 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_failure.1047884969
Directory /workspace/10.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_post_trans.4241490687
Short name T853
Test name
Test status
Simulation time 303265107 ps
CPU time 7.97 seconds
Started Jun 06 01:11:01 PM PDT 24
Finished Jun 06 01:11:10 PM PDT 24
Peak memory 250976 kb
Host smart-7afd67bd-b751-4551-b762-75daa9f0f201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241490687 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_post_trans.4241490687
Directory /workspace/10.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all.4217434704
Short name T459
Test name
Test status
Simulation time 4904922756 ps
CPU time 41.92 seconds
Started Jun 06 01:10:58 PM PDT 24
Finished Jun 06 01:11:41 PM PDT 24
Peak memory 251032 kb
Host smart-17d86b27-71c2-4fbe-8e96-c6fa2e11409a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217434704 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.lc_ctrl_stress_all.4217434704
Directory /workspace/10.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all_with_rand_reset.860879633
Short name T164
Test name
Test status
Simulation time 131400796135 ps
CPU time 1123.41 seconds
Started Jun 06 01:10:57 PM PDT 24
Finished Jun 06 01:29:42 PM PDT 24
Peak memory 628000 kb
Host smart-fd2956b4-8a7d-486d-8abb-8a5e52ab8b26
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=860879633 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_stress_all_with_rand_reset.860879633
Directory /workspace/10.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.lc_ctrl_volatile_unlock_smoke.116599730
Short name T671
Test name
Test status
Simulation time 15880850 ps
CPU time 0.96 seconds
Started Jun 06 01:11:05 PM PDT 24
Finished Jun 06 01:11:07 PM PDT 24
Peak memory 211556 kb
Host smart-d383eec8-3432-4258-a373-8ac554ef264e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116599730 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ct
rl_volatile_unlock_smoke.116599730
Directory /workspace/10.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_alert_test.182112577
Short name T175
Test name
Test status
Simulation time 41297902 ps
CPU time 0.85 seconds
Started Jun 06 01:11:10 PM PDT 24
Finished Jun 06 01:11:12 PM PDT 24
Peak memory 208480 kb
Host smart-9a4d0af0-6dd0-422d-83de-d50d8e191753
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182112577 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_alert_test.182112577
Directory /workspace/11.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.lc_ctrl_errors.1028639752
Short name T842
Test name
Test status
Simulation time 2028447560 ps
CPU time 9.75 seconds
Started Jun 06 01:11:09 PM PDT 24
Finished Jun 06 01:11:20 PM PDT 24
Peak memory 217924 kb
Host smart-5ebf1bb2-b5e8-4fc0-a7f5-ca9d4fe44577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028639752 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_errors.1028639752
Directory /workspace/11.lc_ctrl_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_access.2234122530
Short name T72
Test name
Test status
Simulation time 114128404 ps
CPU time 1.17 seconds
Started Jun 06 01:11:09 PM PDT 24
Finished Jun 06 01:11:11 PM PDT 24
Peak memory 209468 kb
Host smart-9a7a286e-5c41-4206-b432-f9de3aba430e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234122530 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_access.2234122530
Directory /workspace/11.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_errors.2327789932
Short name T358
Test name
Test status
Simulation time 2320891151 ps
CPU time 37 seconds
Started Jun 06 01:11:08 PM PDT 24
Finished Jun 06 01:11:47 PM PDT 24
Peak memory 218000 kb
Host smart-f74326d4-f722-4eeb-b202-0c1697327307
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327789932 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_e
rrors.2327789932
Directory /workspace/11.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_prog_failure.3574552746
Short name T411
Test name
Test status
Simulation time 6230809823 ps
CPU time 6.57 seconds
Started Jun 06 01:11:08 PM PDT 24
Finished Jun 06 01:11:16 PM PDT 24
Peak memory 218156 kb
Host smart-b22f4a73-c5e1-455b-852c-29398b30a2dd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574552746 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jta
g_prog_failure.3574552746
Directory /workspace/11.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_smoke.3543634779
Short name T323
Test name
Test status
Simulation time 250202101 ps
CPU time 3.86 seconds
Started Jun 06 01:11:09 PM PDT 24
Finished Jun 06 01:11:14 PM PDT 24
Peak memory 217700 kb
Host smart-d7d4fd0d-2204-40fe-9988-7dd6c85422fe
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543634779 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_smoke
.3543634779
Directory /workspace/11.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_failure.3499546115
Short name T443
Test name
Test status
Simulation time 8796905866 ps
CPU time 58.71 seconds
Started Jun 06 01:11:08 PM PDT 24
Finished Jun 06 01:12:08 PM PDT 24
Peak memory 283616 kb
Host smart-d5d9b9fe-e8cd-4761-ac8d-5e5f94500abb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499546115 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jt
ag_state_failure.3499546115
Directory /workspace/11.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_post_trans.998948423
Short name T278
Test name
Test status
Simulation time 1037538265 ps
CPU time 19.62 seconds
Started Jun 06 01:11:09 PM PDT 24
Finished Jun 06 01:11:30 PM PDT 24
Peak memory 247640 kb
Host smart-0a7d1b7a-ec75-4438-bf01-e1fd444a77dd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998948423 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_
jtag_state_post_trans.998948423
Directory /workspace/11.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_prog_failure.3382483728
Short name T476
Test name
Test status
Simulation time 1055995863 ps
CPU time 3.65 seconds
Started Jun 06 01:11:07 PM PDT 24
Finished Jun 06 01:11:12 PM PDT 24
Peak memory 217956 kb
Host smart-058f5165-a9e6-428f-b185-f5c5cb1c0a25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382483728 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_prog_failure.3382483728
Directory /workspace/11.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_mubi.2175951273
Short name T326
Test name
Test status
Simulation time 681180617 ps
CPU time 16.32 seconds
Started Jun 06 01:11:07 PM PDT 24
Finished Jun 06 01:11:25 PM PDT 24
Peak memory 226076 kb
Host smart-41ddc219-d4eb-47da-9b03-bdde6a91bd23
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175951273 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_mubi.2175951273
Directory /workspace/11.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_digest.3145538132
Short name T647
Test name
Test status
Simulation time 584314320 ps
CPU time 8.88 seconds
Started Jun 06 01:11:14 PM PDT 24
Finished Jun 06 01:11:24 PM PDT 24
Peak memory 217916 kb
Host smart-4b121aac-e765-4056-aaa2-3230d974c5e3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145538132 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_d
igest.3145538132
Directory /workspace/11.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_mux.1684133505
Short name T764
Test name
Test status
Simulation time 558154944 ps
CPU time 12.5 seconds
Started Jun 06 01:11:09 PM PDT 24
Finished Jun 06 01:11:23 PM PDT 24
Peak memory 217936 kb
Host smart-4ea3146e-4090-493a-9da3-063d10a81ca0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684133505 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_mux.
1684133505
Directory /workspace/11.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/11.lc_ctrl_security_escalation.3048807066
Short name T698
Test name
Test status
Simulation time 234129148 ps
CPU time 10.69 seconds
Started Jun 06 01:11:14 PM PDT 24
Finished Jun 06 01:11:25 PM PDT 24
Peak memory 224824 kb
Host smart-975302a6-c361-43bd-b2c9-be32c2d048a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048807066 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_security_escalation.3048807066
Directory /workspace/11.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/11.lc_ctrl_smoke.2124808309
Short name T667
Test name
Test status
Simulation time 184592458 ps
CPU time 3.03 seconds
Started Jun 06 01:10:58 PM PDT 24
Finished Jun 06 01:11:02 PM PDT 24
Peak memory 214148 kb
Host smart-8b3747a1-54a9-4c8b-a069-5078e4386f5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124808309 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_smoke.2124808309
Directory /workspace/11.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_failure.167844850
Short name T400
Test name
Test status
Simulation time 1552078258 ps
CPU time 31.67 seconds
Started Jun 06 01:11:09 PM PDT 24
Finished Jun 06 01:11:42 PM PDT 24
Peak memory 250984 kb
Host smart-dc4b025a-5e45-453f-bebb-8448e85f7d53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167844850 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_failure.167844850
Directory /workspace/11.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_post_trans.5926959
Short name T403
Test name
Test status
Simulation time 150792665 ps
CPU time 7.13 seconds
Started Jun 06 01:11:09 PM PDT 24
Finished Jun 06 01:11:18 PM PDT 24
Peak memory 250816 kb
Host smart-36f0a303-b9d1-45e0-a891-5c7dc050ef8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5926959 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_post_trans.5926959
Directory /workspace/11.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_stress_all.638160034
Short name T473
Test name
Test status
Simulation time 21736309084 ps
CPU time 110.6 seconds
Started Jun 06 01:11:08 PM PDT 24
Finished Jun 06 01:13:00 PM PDT 24
Peak memory 260280 kb
Host smart-4d7954b1-b8d1-43dd-90b0-6f54f71fb54f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638160034 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.lc_ctrl_stress_all.638160034
Directory /workspace/11.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.lc_ctrl_volatile_unlock_smoke.1060357303
Short name T241
Test name
Test status
Simulation time 32694724 ps
CPU time 0.87 seconds
Started Jun 06 01:11:02 PM PDT 24
Finished Jun 06 01:11:04 PM PDT 24
Peak memory 208588 kb
Host smart-9c3bb681-d513-4ccf-ab03-ee42a3df434c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060357303 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_c
trl_volatile_unlock_smoke.1060357303
Directory /workspace/11.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_alert_test.4869329
Short name T416
Test name
Test status
Simulation time 23995134 ps
CPU time 0.98 seconds
Started Jun 06 01:11:14 PM PDT 24
Finished Jun 06 01:11:16 PM PDT 24
Peak memory 208560 kb
Host smart-18c2297e-0848-4718-9dbe-ad7a51dc94f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4869329 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_alert_test.4869329
Directory /workspace/12.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.lc_ctrl_errors.1575257649
Short name T676
Test name
Test status
Simulation time 627718983 ps
CPU time 14.52 seconds
Started Jun 06 01:11:08 PM PDT 24
Finished Jun 06 01:11:24 PM PDT 24
Peak memory 217944 kb
Host smart-c5cc59bf-d985-47e2-b128-7dc73f08acea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575257649 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_errors.1575257649
Directory /workspace/12.lc_ctrl_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_access.3126124021
Short name T113
Test name
Test status
Simulation time 91197012 ps
CPU time 2.02 seconds
Started Jun 06 01:11:07 PM PDT 24
Finished Jun 06 01:11:11 PM PDT 24
Peak memory 209496 kb
Host smart-b0fd063c-a033-4687-94a2-a70b99bf6737
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126124021 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_access.3126124021
Directory /workspace/12.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_errors.1512854645
Short name T429
Test name
Test status
Simulation time 2922703790 ps
CPU time 42.56 seconds
Started Jun 06 01:11:12 PM PDT 24
Finished Jun 06 01:11:55 PM PDT 24
Peak memory 219168 kb
Host smart-8d7fbb1e-cba8-4e73-bad4-8dc41c6414b9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512854645 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_e
rrors.1512854645
Directory /workspace/12.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_prog_failure.1244247792
Short name T410
Test name
Test status
Simulation time 1705094866 ps
CPU time 7.18 seconds
Started Jun 06 01:11:08 PM PDT 24
Finished Jun 06 01:11:17 PM PDT 24
Peak memory 218000 kb
Host smart-72255f6d-daa8-4d8e-b62d-00379b1fd984
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244247792 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jta
g_prog_failure.1244247792
Directory /workspace/12.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_smoke.2488475324
Short name T568
Test name
Test status
Simulation time 117893447 ps
CPU time 2.59 seconds
Started Jun 06 01:11:07 PM PDT 24
Finished Jun 06 01:11:11 PM PDT 24
Peak memory 217644 kb
Host smart-d0df7fde-6a55-41f7-82a7-378cb12912ce
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488475324 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_smoke
.2488475324
Directory /workspace/12.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_failure.1111405100
Short name T766
Test name
Test status
Simulation time 5135569556 ps
CPU time 52.16 seconds
Started Jun 06 01:11:10 PM PDT 24
Finished Jun 06 01:12:03 PM PDT 24
Peak memory 267344 kb
Host smart-f60755de-293c-4a01-8e49-064df0d375a1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111405100 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jt
ag_state_failure.1111405100
Directory /workspace/12.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_post_trans.2138757663
Short name T866
Test name
Test status
Simulation time 545787226 ps
CPU time 21.5 seconds
Started Jun 06 01:11:11 PM PDT 24
Finished Jun 06 01:11:33 PM PDT 24
Peak memory 250912 kb
Host smart-028dd151-fce1-4289-8a28-19c2a486c880
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138757663 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl
_jtag_state_post_trans.2138757663
Directory /workspace/12.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_prog_failure.2388877959
Short name T767
Test name
Test status
Simulation time 289963982 ps
CPU time 3.55 seconds
Started Jun 06 01:11:10 PM PDT 24
Finished Jun 06 01:11:14 PM PDT 24
Peak memory 218068 kb
Host smart-b69cbc93-4de5-407f-a559-7160e135280c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388877959 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_prog_failure.2388877959
Directory /workspace/12.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_mubi.1607145084
Short name T237
Test name
Test status
Simulation time 658977484 ps
CPU time 9.71 seconds
Started Jun 06 01:11:17 PM PDT 24
Finished Jun 06 01:11:27 PM PDT 24
Peak memory 226160 kb
Host smart-0c49e990-b610-468b-816f-3fba328aa67b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607145084 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_mubi.1607145084
Directory /workspace/12.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_digest.3356153091
Short name T599
Test name
Test status
Simulation time 1189433269 ps
CPU time 14.03 seconds
Started Jun 06 01:11:16 PM PDT 24
Finished Jun 06 01:11:31 PM PDT 24
Peak memory 226012 kb
Host smart-51c235c3-9bce-4a77-bf6b-e90ee60d2cf7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356153091 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_d
igest.3356153091
Directory /workspace/12.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_mux.2764702244
Short name T748
Test name
Test status
Simulation time 980977734 ps
CPU time 9.7 seconds
Started Jun 06 01:11:17 PM PDT 24
Finished Jun 06 01:11:28 PM PDT 24
Peak memory 218028 kb
Host smart-e3d71a86-bd78-43ad-a10e-19e97e9246f4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764702244 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_mux.
2764702244
Directory /workspace/12.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/12.lc_ctrl_security_escalation.3732008651
Short name T760
Test name
Test status
Simulation time 452038808 ps
CPU time 8.72 seconds
Started Jun 06 01:11:10 PM PDT 24
Finished Jun 06 01:11:20 PM PDT 24
Peak memory 218080 kb
Host smart-6077e61c-70c9-4243-ad7a-711ca64723b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732008651 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_security_escalation.3732008651
Directory /workspace/12.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/12.lc_ctrl_smoke.130187307
Short name T431
Test name
Test status
Simulation time 97209477 ps
CPU time 2.4 seconds
Started Jun 06 01:11:10 PM PDT 24
Finished Jun 06 01:11:14 PM PDT 24
Peak memory 214316 kb
Host smart-f17b6807-8449-43c2-bfa9-6d068123d8ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130187307 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_smoke.130187307
Directory /workspace/12.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_failure.215027759
Short name T625
Test name
Test status
Simulation time 1044500689 ps
CPU time 24.69 seconds
Started Jun 06 01:11:10 PM PDT 24
Finished Jun 06 01:11:36 PM PDT 24
Peak memory 250912 kb
Host smart-2541a10f-9742-49b6-801b-7a40746700a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215027759 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_failure.215027759
Directory /workspace/12.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_post_trans.2501399911
Short name T663
Test name
Test status
Simulation time 80999059 ps
CPU time 3.23 seconds
Started Jun 06 01:11:09 PM PDT 24
Finished Jun 06 01:11:14 PM PDT 24
Peak memory 222608 kb
Host smart-4d21272c-4d7e-4ffd-b46f-517ff5bbe3d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501399911 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_post_trans.2501399911
Directory /workspace/12.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_stress_all.2846265368
Short name T639
Test name
Test status
Simulation time 7106807736 ps
CPU time 155.36 seconds
Started Jun 06 01:11:16 PM PDT 24
Finished Jun 06 01:13:52 PM PDT 24
Peak memory 281428 kb
Host smart-cc9571db-462d-4b0c-bed4-c163939f69c1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846265368 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.lc_ctrl_stress_all.2846265368
Directory /workspace/12.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.lc_ctrl_stress_all_with_rand_reset.687991208
Short name T54
Test name
Test status
Simulation time 51887020769 ps
CPU time 635.63 seconds
Started Jun 06 01:11:18 PM PDT 24
Finished Jun 06 01:21:55 PM PDT 24
Peak memory 281692 kb
Host smart-24f28457-7cdd-4ed2-a0d8-c531b857e051
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=687991208 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_stress_all_with_rand_reset.687991208
Directory /workspace/12.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.lc_ctrl_volatile_unlock_smoke.2308237935
Short name T876
Test name
Test status
Simulation time 19994632 ps
CPU time 0.99 seconds
Started Jun 06 01:11:10 PM PDT 24
Finished Jun 06 01:11:12 PM PDT 24
Peak memory 211428 kb
Host smart-49bcea66-1c1f-47dc-b8ba-99f39186de1f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308237935 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_c
trl_volatile_unlock_smoke.2308237935
Directory /workspace/12.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_alert_test.3044393207
Short name T460
Test name
Test status
Simulation time 94768114 ps
CPU time 1.04 seconds
Started Jun 06 01:11:32 PM PDT 24
Finished Jun 06 01:11:34 PM PDT 24
Peak memory 208904 kb
Host smart-96b65a15-d829-4b2c-a6a4-9d68ea68cadb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044393207 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_alert_test.3044393207
Directory /workspace/13.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.lc_ctrl_errors.3902827777
Short name T677
Test name
Test status
Simulation time 762963342 ps
CPU time 8.2 seconds
Started Jun 06 01:11:15 PM PDT 24
Finished Jun 06 01:11:24 PM PDT 24
Peak memory 217992 kb
Host smart-7bcd9999-f3fa-40d7-af36-ebe270b3536f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902827777 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_errors.3902827777
Directory /workspace/13.lc_ctrl_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_access.1409348913
Short name T619
Test name
Test status
Simulation time 1201874313 ps
CPU time 4.92 seconds
Started Jun 06 01:11:15 PM PDT 24
Finished Jun 06 01:11:21 PM PDT 24
Peak memory 209504 kb
Host smart-ee8d2f7b-21ae-4f81-a403-c847a87c7ad6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409348913 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_access.1409348913
Directory /workspace/13.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_errors.1825284173
Short name T682
Test name
Test status
Simulation time 10998564929 ps
CPU time 78.5 seconds
Started Jun 06 01:11:15 PM PDT 24
Finished Jun 06 01:12:34 PM PDT 24
Peak memory 218932 kb
Host smart-2a0cd6c1-67d0-4e3f-9587-073a2784f03f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825284173 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_e
rrors.1825284173
Directory /workspace/13.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_prog_failure.274822758
Short name T412
Test name
Test status
Simulation time 171050044 ps
CPU time 3.88 seconds
Started Jun 06 01:11:17 PM PDT 24
Finished Jun 06 01:11:22 PM PDT 24
Peak memory 218000 kb
Host smart-0ffce75f-2bc2-4f9b-a8ea-a5efa6579b27
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274822758 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag
_prog_failure.274822758
Directory /workspace/13.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_smoke.2401457209
Short name T80
Test name
Test status
Simulation time 245836886 ps
CPU time 4.12 seconds
Started Jun 06 01:11:18 PM PDT 24
Finished Jun 06 01:11:23 PM PDT 24
Peak memory 217672 kb
Host smart-cf000e3e-aeac-4904-84b4-c3667821e855
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401457209 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_smoke
.2401457209
Directory /workspace/13.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_failure.4146994445
Short name T31
Test name
Test status
Simulation time 1645865824 ps
CPU time 52.49 seconds
Started Jun 06 01:11:16 PM PDT 24
Finished Jun 06 01:12:09 PM PDT 24
Peak memory 269008 kb
Host smart-97e259dc-c48b-41d1-8787-f37525a1091e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146994445 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jt
ag_state_failure.4146994445
Directory /workspace/13.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_post_trans.3948876836
Short name T256
Test name
Test status
Simulation time 1299027834 ps
CPU time 6.41 seconds
Started Jun 06 01:11:16 PM PDT 24
Finished Jun 06 01:11:23 PM PDT 24
Peak memory 222736 kb
Host smart-a8805b7e-5cde-49c6-9a1c-e27d31557e6d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948876836 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl
_jtag_state_post_trans.3948876836
Directory /workspace/13.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_mubi.1890351276
Short name T717
Test name
Test status
Simulation time 1006313210 ps
CPU time 13.33 seconds
Started Jun 06 01:11:31 PM PDT 24
Finished Jun 06 01:11:45 PM PDT 24
Peak memory 226308 kb
Host smart-a74d0592-02b9-4b91-892f-dd1f5b3afdc2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890351276 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_mubi.1890351276
Directory /workspace/13.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_digest.1469901090
Short name T135
Test name
Test status
Simulation time 589364404 ps
CPU time 13.2 seconds
Started Jun 06 01:11:29 PM PDT 24
Finished Jun 06 01:11:43 PM PDT 24
Peak memory 225988 kb
Host smart-e665b90b-264e-4557-8449-93a5098dedc9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469901090 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_d
igest.1469901090
Directory /workspace/13.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_mux.3655884148
Short name T177
Test name
Test status
Simulation time 231174569 ps
CPU time 6.65 seconds
Started Jun 06 01:11:26 PM PDT 24
Finished Jun 06 01:11:34 PM PDT 24
Peak memory 217928 kb
Host smart-b15ef46f-bb2f-48b3-bd4b-0fafeeb16635
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655884148 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_mux.
3655884148
Directory /workspace/13.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/13.lc_ctrl_security_escalation.2923798628
Short name T397
Test name
Test status
Simulation time 1142758471 ps
CPU time 15.21 seconds
Started Jun 06 01:11:17 PM PDT 24
Finished Jun 06 01:11:33 PM PDT 24
Peak memory 218100 kb
Host smart-086efda1-d065-4aeb-bcbf-878322bca965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923798628 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_security_escalation.2923798628
Directory /workspace/13.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/13.lc_ctrl_smoke.1950010806
Short name T653
Test name
Test status
Simulation time 1144617190 ps
CPU time 11.24 seconds
Started Jun 06 01:11:17 PM PDT 24
Finished Jun 06 01:11:29 PM PDT 24
Peak memory 217664 kb
Host smart-dac95f9f-dd49-4f12-9954-cc899f8625f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950010806 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_smoke.1950010806
Directory /workspace/13.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_failure.1077089204
Short name T273
Test name
Test status
Simulation time 257755710 ps
CPU time 25.56 seconds
Started Jun 06 01:11:17 PM PDT 24
Finished Jun 06 01:11:43 PM PDT 24
Peak memory 250964 kb
Host smart-25478d83-75b6-465b-b1f7-7653f66fc90a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077089204 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_failure.1077089204
Directory /workspace/13.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_post_trans.3275277423
Short name T524
Test name
Test status
Simulation time 62090708 ps
CPU time 3.77 seconds
Started Jun 06 01:11:15 PM PDT 24
Finished Jun 06 01:11:20 PM PDT 24
Peak memory 218012 kb
Host smart-64b4fb6f-5408-4c58-a363-71138e2c5b62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275277423 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_post_trans.3275277423
Directory /workspace/13.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all.3090517104
Short name T423
Test name
Test status
Simulation time 4484389017 ps
CPU time 84.42 seconds
Started Jun 06 01:11:27 PM PDT 24
Finished Jun 06 01:12:53 PM PDT 24
Peak memory 275604 kb
Host smart-b3b96661-e5c2-44bb-9df5-58c436783b67
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090517104 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.lc_ctrl_stress_all.3090517104
Directory /workspace/13.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.lc_ctrl_volatile_unlock_smoke.2391040582
Short name T10
Test name
Test status
Simulation time 37841607 ps
CPU time 0.87 seconds
Started Jun 06 01:11:20 PM PDT 24
Finished Jun 06 01:11:22 PM PDT 24
Peak memory 211624 kb
Host smart-54c37ad1-7b89-4e7a-984b-df0e6a6dfdd6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391040582 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_c
trl_volatile_unlock_smoke.2391040582
Directory /workspace/13.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_alert_test.1039350078
Short name T77
Test name
Test status
Simulation time 81836728 ps
CPU time 0.94 seconds
Started Jun 06 01:11:28 PM PDT 24
Finished Jun 06 01:11:30 PM PDT 24
Peak memory 209536 kb
Host smart-c6b739e9-e1fa-4767-be7f-5424a64cdda1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039350078 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_alert_test.1039350078
Directory /workspace/14.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.lc_ctrl_errors.1009347969
Short name T623
Test name
Test status
Simulation time 435632346 ps
CPU time 11.32 seconds
Started Jun 06 01:11:28 PM PDT 24
Finished Jun 06 01:11:40 PM PDT 24
Peak memory 217956 kb
Host smart-5b9d3f90-4c13-4ae8-bbaa-7d0221dc2b53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009347969 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_errors.1009347969
Directory /workspace/14.lc_ctrl_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_access.89337583
Short name T388
Test name
Test status
Simulation time 876400112 ps
CPU time 5.87 seconds
Started Jun 06 01:11:26 PM PDT 24
Finished Jun 06 01:11:33 PM PDT 24
Peak memory 209540 kb
Host smart-e309aad4-26b1-446b-978b-23f528d54342
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89337583 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_access.89337583
Directory /workspace/14.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_errors.1291378812
Short name T447
Test name
Test status
Simulation time 1899149546 ps
CPU time 37.2 seconds
Started Jun 06 01:11:29 PM PDT 24
Finished Jun 06 01:12:07 PM PDT 24
Peak memory 217944 kb
Host smart-a1b89548-cb6d-4b7a-aa4a-a0489fbbdf4a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291378812 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_e
rrors.1291378812
Directory /workspace/14.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_prog_failure.575504908
Short name T434
Test name
Test status
Simulation time 386913712 ps
CPU time 5.74 seconds
Started Jun 06 01:11:27 PM PDT 24
Finished Jun 06 01:11:34 PM PDT 24
Peak memory 217944 kb
Host smart-90dd6910-fe8a-4429-a98f-b854481ae251
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575504908 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag
_prog_failure.575504908
Directory /workspace/14.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_smoke.2928220162
Short name T178
Test name
Test status
Simulation time 2297589742 ps
CPU time 16.03 seconds
Started Jun 06 01:11:26 PM PDT 24
Finished Jun 06 01:11:43 PM PDT 24
Peak memory 217708 kb
Host smart-9c933c16-b81d-4a3c-a971-ce3e3e7f23f0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928220162 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_smoke
.2928220162
Directory /workspace/14.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_failure.867000918
Short name T381
Test name
Test status
Simulation time 15592272724 ps
CPU time 49.36 seconds
Started Jun 06 01:11:27 PM PDT 24
Finished Jun 06 01:12:17 PM PDT 24
Peak memory 276668 kb
Host smart-82728e6d-9524-47e0-b5cd-7b51cf6d4730
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867000918 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jta
g_state_failure.867000918
Directory /workspace/14.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_post_trans.927231501
Short name T507
Test name
Test status
Simulation time 2369719339 ps
CPU time 17.29 seconds
Started Jun 06 01:11:27 PM PDT 24
Finished Jun 06 01:11:46 PM PDT 24
Peak memory 222652 kb
Host smart-9e6ca941-ef2e-4894-a7e6-10e89315a764
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927231501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_
jtag_state_post_trans.927231501
Directory /workspace/14.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_prog_failure.697238857
Short name T817
Test name
Test status
Simulation time 177048312 ps
CPU time 2.25 seconds
Started Jun 06 01:11:27 PM PDT 24
Finished Jun 06 01:11:30 PM PDT 24
Peak memory 217872 kb
Host smart-23aba3d3-d30d-45ac-acf0-0c09ffcd8af9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697238857 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_prog_failure.697238857
Directory /workspace/14.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_mubi.3070654526
Short name T690
Test name
Test status
Simulation time 1255255425 ps
CPU time 10.56 seconds
Started Jun 06 01:11:27 PM PDT 24
Finished Jun 06 01:11:39 PM PDT 24
Peak memory 218620 kb
Host smart-af7de841-0780-4f21-9c50-5118ed73acf8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070654526 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_mubi.3070654526
Directory /workspace/14.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_digest.1194381702
Short name T635
Test name
Test status
Simulation time 237617811 ps
CPU time 9 seconds
Started Jun 06 01:11:32 PM PDT 24
Finished Jun 06 01:11:42 PM PDT 24
Peak memory 217948 kb
Host smart-0382218f-9ddd-464f-a20a-a9f006609cc9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194381702 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_d
igest.1194381702
Directory /workspace/14.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/14.lc_ctrl_security_escalation.2419577270
Short name T313
Test name
Test status
Simulation time 230421823 ps
CPU time 9.11 seconds
Started Jun 06 01:11:28 PM PDT 24
Finished Jun 06 01:11:38 PM PDT 24
Peak memory 218156 kb
Host smart-fd684350-5366-4154-9a46-9030cb019925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419577270 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_security_escalation.2419577270
Directory /workspace/14.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/14.lc_ctrl_smoke.3521095479
Short name T546
Test name
Test status
Simulation time 44689685 ps
CPU time 3.15 seconds
Started Jun 06 01:11:28 PM PDT 24
Finished Jun 06 01:11:32 PM PDT 24
Peak memory 214796 kb
Host smart-e213b2a1-59ce-4d95-9640-8ca02c9b7caa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521095479 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_smoke.3521095479
Directory /workspace/14.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_failure.2587863928
Short name T356
Test name
Test status
Simulation time 2327971705 ps
CPU time 28.35 seconds
Started Jun 06 01:11:32 PM PDT 24
Finished Jun 06 01:12:01 PM PDT 24
Peak memory 251056 kb
Host smart-72578bce-663b-4c6f-a3e3-0be0b4973311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587863928 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_failure.2587863928
Directory /workspace/14.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_post_trans.189082629
Short name T283
Test name
Test status
Simulation time 160796253 ps
CPU time 8.59 seconds
Started Jun 06 01:11:28 PM PDT 24
Finished Jun 06 01:11:37 PM PDT 24
Peak memory 250684 kb
Host smart-cbd1541b-9a3b-452d-8899-7aa24ff0386a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189082629 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_post_trans.189082629
Directory /workspace/14.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_stress_all.597089052
Short name T874
Test name
Test status
Simulation time 1304642155 ps
CPU time 13.85 seconds
Started Jun 06 01:11:28 PM PDT 24
Finished Jun 06 01:11:43 PM PDT 24
Peak memory 226112 kb
Host smart-ede2f78f-8661-485e-b522-96cc9c54af25
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597089052 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.lc_ctrl_stress_all.597089052
Directory /workspace/14.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.lc_ctrl_volatile_unlock_smoke.421583834
Short name T846
Test name
Test status
Simulation time 15614767 ps
CPU time 0.96 seconds
Started Jun 06 01:11:27 PM PDT 24
Finished Jun 06 01:11:29 PM PDT 24
Peak memory 211432 kb
Host smart-3bc76ae6-a2e1-4bdb-afe9-3dd8fd1dc3a8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421583834 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ct
rl_volatile_unlock_smoke.421583834
Directory /workspace/14.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_alert_test.1716302780
Short name T239
Test name
Test status
Simulation time 16833583 ps
CPU time 0.92 seconds
Started Jun 06 01:11:36 PM PDT 24
Finished Jun 06 01:11:38 PM PDT 24
Peak memory 208592 kb
Host smart-7eff01e4-20a4-4e42-b3bc-1f0df34019a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716302780 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_alert_test.1716302780
Directory /workspace/15.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.lc_ctrl_errors.1241820721
Short name T384
Test name
Test status
Simulation time 8888227182 ps
CPU time 15.21 seconds
Started Jun 06 01:11:38 PM PDT 24
Finished Jun 06 01:11:55 PM PDT 24
Peak memory 218316 kb
Host smart-8ac8a32c-d3c4-49da-aa1c-e08767aa9ef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241820721 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_errors.1241820721
Directory /workspace/15.lc_ctrl_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_access.3175672394
Short name T394
Test name
Test status
Simulation time 334878285 ps
CPU time 4.74 seconds
Started Jun 06 01:11:38 PM PDT 24
Finished Jun 06 01:11:44 PM PDT 24
Peak memory 217100 kb
Host smart-2f1d02d5-621d-4ce5-9128-1f12dd102960
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175672394 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_access.3175672394
Directory /workspace/15.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_errors.780259946
Short name T512
Test name
Test status
Simulation time 3303602160 ps
CPU time 28.12 seconds
Started Jun 06 01:11:36 PM PDT 24
Finished Jun 06 01:12:05 PM PDT 24
Peak memory 218444 kb
Host smart-1bd9eb6c-d278-4608-98a1-8503a38f41a1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780259946 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_er
rors.780259946
Directory /workspace/15.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_prog_failure.365443127
Short name T22
Test name
Test status
Simulation time 212805266 ps
CPU time 4.87 seconds
Started Jun 06 01:12:01 PM PDT 24
Finished Jun 06 01:12:08 PM PDT 24
Peak memory 217956 kb
Host smart-d45bcb06-5673-467c-a4da-b6019a52fa47
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365443127 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag
_prog_failure.365443127
Directory /workspace/15.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_smoke.2000031974
Short name T81
Test name
Test status
Simulation time 336265446 ps
CPU time 4.78 seconds
Started Jun 06 01:11:36 PM PDT 24
Finished Jun 06 01:11:43 PM PDT 24
Peak memory 217652 kb
Host smart-86aac9f5-a1bb-4aa7-b847-306d4750ffc7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000031974 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_smoke
.2000031974
Directory /workspace/15.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_failure.697492721
Short name T318
Test name
Test status
Simulation time 8459112958 ps
CPU time 78.8 seconds
Started Jun 06 01:11:48 PM PDT 24
Finished Jun 06 01:13:10 PM PDT 24
Peak memory 277136 kb
Host smart-f89bb94f-b3ef-412f-9f29-f14eb5e14356
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697492721 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jta
g_state_failure.697492721
Directory /workspace/15.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_post_trans.1285251027
Short name T392
Test name
Test status
Simulation time 3471548971 ps
CPU time 12.51 seconds
Started Jun 06 01:11:48 PM PDT 24
Finished Jun 06 01:12:04 PM PDT 24
Peak memory 246248 kb
Host smart-1aa7e9c9-0ff8-403f-8be7-362c4c96cf09
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285251027 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl
_jtag_state_post_trans.1285251027
Directory /workspace/15.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_prog_failure.3250890231
Short name T261
Test name
Test status
Simulation time 93041213 ps
CPU time 4.2 seconds
Started Jun 06 01:11:25 PM PDT 24
Finished Jun 06 01:11:30 PM PDT 24
Peak memory 218024 kb
Host smart-f6e7c4c1-31fa-4f48-97fe-eef5c9e92e32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250890231 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_prog_failure.3250890231
Directory /workspace/15.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_mubi.1567270012
Short name T302
Test name
Test status
Simulation time 832308387 ps
CPU time 12.24 seconds
Started Jun 06 01:11:51 PM PDT 24
Finished Jun 06 01:12:06 PM PDT 24
Peak memory 217884 kb
Host smart-a944a755-a068-463f-b12f-0303627c2125
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567270012 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_mubi.1567270012
Directory /workspace/15.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_digest.3000822315
Short name T187
Test name
Test status
Simulation time 239222456 ps
CPU time 9.16 seconds
Started Jun 06 01:11:38 PM PDT 24
Finished Jun 06 01:11:49 PM PDT 24
Peak memory 225924 kb
Host smart-4b0d80b6-643b-4df1-a813-4b5ed720de47
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000822315 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_d
igest.3000822315
Directory /workspace/15.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_mux.1159221654
Short name T837
Test name
Test status
Simulation time 1340593482 ps
CPU time 10.69 seconds
Started Jun 06 01:11:37 PM PDT 24
Finished Jun 06 01:11:50 PM PDT 24
Peak memory 218036 kb
Host smart-388b83e5-b790-4d70-8e66-96c0cb427f06
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159221654 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_mux.
1159221654
Directory /workspace/15.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/15.lc_ctrl_security_escalation.3608626392
Short name T316
Test name
Test status
Simulation time 264973760 ps
CPU time 10.06 seconds
Started Jun 06 01:11:39 PM PDT 24
Finished Jun 06 01:11:51 PM PDT 24
Peak memory 218144 kb
Host smart-fc2db1be-90ea-46f9-8bc8-6059ee084a8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608626392 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_security_escalation.3608626392
Directory /workspace/15.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/15.lc_ctrl_smoke.860102126
Short name T585
Test name
Test status
Simulation time 98379401 ps
CPU time 4.32 seconds
Started Jun 06 01:11:26 PM PDT 24
Finished Jun 06 01:11:32 PM PDT 24
Peak memory 217732 kb
Host smart-59561f42-2ef4-4aaf-843c-83a6e4306bbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860102126 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_smoke.860102126
Directory /workspace/15.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_failure.4110654105
Short name T421
Test name
Test status
Simulation time 180695220 ps
CPU time 19.72 seconds
Started Jun 06 01:11:32 PM PDT 24
Finished Jun 06 01:11:53 PM PDT 24
Peak memory 246284 kb
Host smart-d7cbe840-e7b4-458e-9c20-4a46d3c74b3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110654105 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_failure.4110654105
Directory /workspace/15.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_post_trans.239728583
Short name T12
Test name
Test status
Simulation time 54278174 ps
CPU time 6.89 seconds
Started Jun 06 01:11:28 PM PDT 24
Finished Jun 06 01:11:36 PM PDT 24
Peak memory 250604 kb
Host smart-3c5815fb-7905-47bd-b15b-797acc39113b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239728583 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_post_trans.239728583
Directory /workspace/15.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all.2155247568
Short name T587
Test name
Test status
Simulation time 70134351525 ps
CPU time 479.23 seconds
Started Jun 06 01:11:40 PM PDT 24
Finished Jun 06 01:19:41 PM PDT 24
Peak memory 267644 kb
Host smart-cdde9b53-38cc-4e2c-a58c-6091a8f65414
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155247568 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.lc_ctrl_stress_all.2155247568
Directory /workspace/15.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all_with_rand_reset.1600921884
Short name T815
Test name
Test status
Simulation time 137116899464 ps
CPU time 347.27 seconds
Started Jun 06 01:11:38 PM PDT 24
Finished Jun 06 01:17:27 PM PDT 24
Peak memory 457048 kb
Host smart-80bc525f-5ec0-4387-904a-3a334403c153
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1600921884 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_stress_all_with_rand_reset.1600921884
Directory /workspace/15.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.lc_ctrl_volatile_unlock_smoke.3971167541
Short name T697
Test name
Test status
Simulation time 51230730 ps
CPU time 0.88 seconds
Started Jun 06 01:11:27 PM PDT 24
Finished Jun 06 01:11:29 PM PDT 24
Peak memory 211520 kb
Host smart-da162943-9445-4df7-987d-eb9c0bdcdb26
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971167541 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_c
trl_volatile_unlock_smoke.3971167541
Directory /workspace/15.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_alert_test.3032003739
Short name T346
Test name
Test status
Simulation time 20646750 ps
CPU time 0.88 seconds
Started Jun 06 01:11:37 PM PDT 24
Finished Jun 06 01:11:40 PM PDT 24
Peak memory 208624 kb
Host smart-c143c72b-e4ff-41be-9aca-251517ff9681
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032003739 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_alert_test.3032003739
Directory /workspace/16.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.lc_ctrl_errors.334821932
Short name T798
Test name
Test status
Simulation time 561182663 ps
CPU time 10.32 seconds
Started Jun 06 01:11:36 PM PDT 24
Finished Jun 06 01:11:47 PM PDT 24
Peak memory 217964 kb
Host smart-ec7b82da-0394-4e71-a034-34ac11f63542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334821932 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_errors.334821932
Directory /workspace/16.lc_ctrl_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_access.2767265992
Short name T709
Test name
Test status
Simulation time 2099832977 ps
CPU time 11.23 seconds
Started Jun 06 01:11:36 PM PDT 24
Finished Jun 06 01:11:49 PM PDT 24
Peak memory 209524 kb
Host smart-ae17f2f3-4ea0-4151-b396-9fc122bcd705
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767265992 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_access.2767265992
Directory /workspace/16.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_errors.3891881063
Short name T763
Test name
Test status
Simulation time 10361060127 ps
CPU time 39.42 seconds
Started Jun 06 01:11:38 PM PDT 24
Finished Jun 06 01:12:19 PM PDT 24
Peak memory 218424 kb
Host smart-1c1a27c5-a829-45ee-84f9-7ef75717023e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891881063 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_e
rrors.3891881063
Directory /workspace/16.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_prog_failure.3503476245
Short name T584
Test name
Test status
Simulation time 2650292011 ps
CPU time 16.31 seconds
Started Jun 06 01:11:36 PM PDT 24
Finished Jun 06 01:11:54 PM PDT 24
Peak memory 218100 kb
Host smart-bd5781f4-8a60-414e-9e03-1576573d0be2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503476245 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jta
g_prog_failure.3503476245
Directory /workspace/16.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_smoke.479212145
Short name T826
Test name
Test status
Simulation time 363630187 ps
CPU time 5.82 seconds
Started Jun 06 01:11:48 PM PDT 24
Finished Jun 06 01:11:57 PM PDT 24
Peak memory 217536 kb
Host smart-2e9b6721-8df3-450e-b64d-64da404181ef
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479212145 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_smoke.
479212145
Directory /workspace/16.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_failure.1371511409
Short name T516
Test name
Test status
Simulation time 3197569822 ps
CPU time 39.78 seconds
Started Jun 06 01:11:37 PM PDT 24
Finished Jun 06 01:12:19 PM PDT 24
Peak memory 267348 kb
Host smart-e857aae0-bbef-4b19-a0ab-8707525a9518
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371511409 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jt
ag_state_failure.1371511409
Directory /workspace/16.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_post_trans.3069267414
Short name T368
Test name
Test status
Simulation time 475935091 ps
CPU time 12.21 seconds
Started Jun 06 01:11:41 PM PDT 24
Finished Jun 06 01:11:56 PM PDT 24
Peak memory 250404 kb
Host smart-855c2580-6fc1-409f-9d11-5d3fd38b490a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069267414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl
_jtag_state_post_trans.3069267414
Directory /workspace/16.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_prog_failure.519954281
Short name T602
Test name
Test status
Simulation time 93487762 ps
CPU time 3.23 seconds
Started Jun 06 01:11:37 PM PDT 24
Finished Jun 06 01:11:42 PM PDT 24
Peak memory 218112 kb
Host smart-e0dbbb72-3592-4f6d-bc0f-513ee724d6bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519954281 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_prog_failure.519954281
Directory /workspace/16.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_mubi.256009240
Short name T350
Test name
Test status
Simulation time 5211698907 ps
CPU time 18.62 seconds
Started Jun 06 01:11:38 PM PDT 24
Finished Jun 06 01:11:58 PM PDT 24
Peak memory 219244 kb
Host smart-9eedffcd-4867-496d-9b53-d68c8e85f6b0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256009240 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_mubi.256009240
Directory /workspace/16.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_digest.1471916379
Short name T15
Test name
Test status
Simulation time 2938498110 ps
CPU time 10.82 seconds
Started Jun 06 01:11:36 PM PDT 24
Finished Jun 06 01:11:49 PM PDT 24
Peak memory 218052 kb
Host smart-d5cee4fc-f5f5-40f1-899f-02ef0d301b17
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471916379 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_d
igest.1471916379
Directory /workspace/16.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_mux.456695552
Short name T575
Test name
Test status
Simulation time 505868268 ps
CPU time 9.59 seconds
Started Jun 06 01:11:36 PM PDT 24
Finished Jun 06 01:11:46 PM PDT 24
Peak memory 217984 kb
Host smart-8482c9df-5abc-40f7-839b-1e8ab57878b6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456695552 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_mux.456695552
Directory /workspace/16.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/16.lc_ctrl_security_escalation.3770955779
Short name T850
Test name
Test status
Simulation time 479690761 ps
CPU time 6.26 seconds
Started Jun 06 01:11:41 PM PDT 24
Finished Jun 06 01:11:50 PM PDT 24
Peak memory 218060 kb
Host smart-a3a69802-2c02-45bf-af55-85d400938bb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770955779 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_security_escalation.3770955779
Directory /workspace/16.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/16.lc_ctrl_smoke.1825896764
Short name T74
Test name
Test status
Simulation time 62894004 ps
CPU time 1.23 seconds
Started Jun 06 01:11:37 PM PDT 24
Finished Jun 06 01:11:40 PM PDT 24
Peak memory 217836 kb
Host smart-55df24fc-fe49-4478-b5a7-539e1ce90c64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825896764 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_smoke.1825896764
Directory /workspace/16.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_failure.3782930692
Short name T281
Test name
Test status
Simulation time 203476621 ps
CPU time 26.57 seconds
Started Jun 06 01:11:36 PM PDT 24
Finished Jun 06 01:12:04 PM PDT 24
Peak memory 251004 kb
Host smart-90fb8e1f-a85f-49f7-85f5-4cd4c7b6ffd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3782930692 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_failure.3782930692
Directory /workspace/16.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_post_trans.3397687511
Short name T259
Test name
Test status
Simulation time 224813473 ps
CPU time 6.44 seconds
Started Jun 06 01:11:37 PM PDT 24
Finished Jun 06 01:11:45 PM PDT 24
Peak memory 250560 kb
Host smart-bf5b899e-6f6b-4a06-867a-2e20eee45d93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397687511 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_post_trans.3397687511
Directory /workspace/16.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_stress_all.3765415313
Short name T708
Test name
Test status
Simulation time 896253916 ps
CPU time 49.12 seconds
Started Jun 06 01:11:37 PM PDT 24
Finished Jun 06 01:12:28 PM PDT 24
Peak memory 251076 kb
Host smart-e67dc34f-778e-4be2-92c3-6bbbfbdd7e7e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765415313 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.lc_ctrl_stress_all.3765415313
Directory /workspace/16.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.lc_ctrl_stress_all_with_rand_reset.1372552094
Short name T91
Test name
Test status
Simulation time 136191267613 ps
CPU time 603.71 seconds
Started Jun 06 01:11:48 PM PDT 24
Finished Jun 06 01:21:55 PM PDT 24
Peak memory 513196 kb
Host smart-92f435e0-ea2d-4d8b-a915-4303560cb328
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1372552094 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_stress_all_with_rand_reset.1372552094
Directory /workspace/16.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.lc_ctrl_volatile_unlock_smoke.2482371354
Short name T185
Test name
Test status
Simulation time 14375387 ps
CPU time 0.79 seconds
Started Jun 06 01:11:40 PM PDT 24
Finished Jun 06 01:11:44 PM PDT 24
Peak memory 208740 kb
Host smart-87769fbc-ce26-4663-9dbf-d8494e215943
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482371354 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_c
trl_volatile_unlock_smoke.2482371354
Directory /workspace/16.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_alert_test.2101947994
Short name T99
Test name
Test status
Simulation time 41988318 ps
CPU time 0.83 seconds
Started Jun 06 01:11:49 PM PDT 24
Finished Jun 06 01:11:53 PM PDT 24
Peak memory 208592 kb
Host smart-dc3d8bdd-b14f-4c8e-a015-8fd2cd638b3e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101947994 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_alert_test.2101947994
Directory /workspace/17.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_access.245474550
Short name T820
Test name
Test status
Simulation time 211771635 ps
CPU time 2.19 seconds
Started Jun 06 01:11:49 PM PDT 24
Finished Jun 06 01:11:55 PM PDT 24
Peak memory 216856 kb
Host smart-380e43b8-f0d9-434f-9917-2946b8a3a204
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245474550 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_access.245474550
Directory /workspace/17.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_errors.3596302570
Short name T775
Test name
Test status
Simulation time 922746709 ps
CPU time 28.44 seconds
Started Jun 06 01:11:50 PM PDT 24
Finished Jun 06 01:12:22 PM PDT 24
Peak memory 217928 kb
Host smart-a4e8f452-6d60-40cd-a14f-c1aaf81dddb4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596302570 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_e
rrors.3596302570
Directory /workspace/17.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_prog_failure.941062087
Short name T456
Test name
Test status
Simulation time 991237681 ps
CPU time 7.06 seconds
Started Jun 06 01:11:50 PM PDT 24
Finished Jun 06 01:12:00 PM PDT 24
Peak memory 217952 kb
Host smart-6c0084d1-e95c-4f58-aa45-6160d12bd489
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941062087 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag
_prog_failure.941062087
Directory /workspace/17.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_smoke.1396740320
Short name T797
Test name
Test status
Simulation time 298377432 ps
CPU time 4.82 seconds
Started Jun 06 01:11:37 PM PDT 24
Finished Jun 06 01:11:44 PM PDT 24
Peak memory 217644 kb
Host smart-14a49cc3-87a4-4ad9-b415-7b524ebc1ef1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396740320 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_smoke
.1396740320
Directory /workspace/17.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_failure.3294487651
Short name T248
Test name
Test status
Simulation time 2903624374 ps
CPU time 36.23 seconds
Started Jun 06 01:11:35 PM PDT 24
Finished Jun 06 01:12:13 PM PDT 24
Peak memory 275548 kb
Host smart-86de718d-d534-46d4-bd5c-fa4628da62f0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294487651 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jt
ag_state_failure.3294487651
Directory /workspace/17.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_post_trans.3000979744
Short name T735
Test name
Test status
Simulation time 416711000 ps
CPU time 13.19 seconds
Started Jun 06 01:11:51 PM PDT 24
Finished Jun 06 01:12:07 PM PDT 24
Peak memory 250916 kb
Host smart-3c3bbe6d-1d88-4f05-861a-559572e42aac
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000979744 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl
_jtag_state_post_trans.3000979744
Directory /workspace/17.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_prog_failure.408640040
Short name T687
Test name
Test status
Simulation time 211665109 ps
CPU time 3.09 seconds
Started Jun 06 01:11:48 PM PDT 24
Finished Jun 06 01:11:54 PM PDT 24
Peak memory 217872 kb
Host smart-1eed83ca-5a02-48e8-b6bf-372429d30c54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408640040 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_prog_failure.408640040
Directory /workspace/17.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_digest.1104676839
Short name T404
Test name
Test status
Simulation time 345697479 ps
CPU time 10.84 seconds
Started Jun 06 01:11:51 PM PDT 24
Finished Jun 06 01:12:05 PM PDT 24
Peak memory 217892 kb
Host smart-f4b91d69-62e0-4146-a738-f7525e5174db
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104676839 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_d
igest.1104676839
Directory /workspace/17.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_mux.2704585133
Short name T375
Test name
Test status
Simulation time 1378497955 ps
CPU time 13.83 seconds
Started Jun 06 01:11:49 PM PDT 24
Finished Jun 06 01:12:06 PM PDT 24
Peak memory 217992 kb
Host smart-a1490c79-8944-4607-acb7-34663002c06a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704585133 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_mux.
2704585133
Directory /workspace/17.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/17.lc_ctrl_security_escalation.498635512
Short name T182
Test name
Test status
Simulation time 726656930 ps
CPU time 10.94 seconds
Started Jun 06 01:11:41 PM PDT 24
Finished Jun 06 01:11:55 PM PDT 24
Peak memory 218136 kb
Host smart-fb7e9652-c4a8-4379-bab2-7fffa3357923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498635512 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_security_escalation.498635512
Directory /workspace/17.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/17.lc_ctrl_smoke.2908800145
Short name T805
Test name
Test status
Simulation time 48690359 ps
CPU time 2.57 seconds
Started Jun 06 01:11:35 PM PDT 24
Finished Jun 06 01:11:39 PM PDT 24
Peak memory 217792 kb
Host smart-49c1660b-df2c-4c58-9f10-184fc804d2ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908800145 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_smoke.2908800145
Directory /workspace/17.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_failure.1413000641
Short name T724
Test name
Test status
Simulation time 1164656270 ps
CPU time 30.35 seconds
Started Jun 06 01:11:40 PM PDT 24
Finished Jun 06 01:12:13 PM PDT 24
Peak memory 251024 kb
Host smart-bb217591-3893-4149-8d61-9b80ae0cec4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413000641 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_failure.1413000641
Directory /workspace/17.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_post_trans.1270034159
Short name T851
Test name
Test status
Simulation time 77839466 ps
CPU time 7.59 seconds
Started Jun 06 01:11:36 PM PDT 24
Finished Jun 06 01:11:45 PM PDT 24
Peak memory 250500 kb
Host smart-08d8d43e-8e72-4038-86bd-80a127326fbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270034159 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_post_trans.1270034159
Directory /workspace/17.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all.45832715
Short name T335
Test name
Test status
Simulation time 13477207187 ps
CPU time 204.28 seconds
Started Jun 06 01:11:50 PM PDT 24
Finished Jun 06 01:15:18 PM PDT 24
Peak memory 220072 kb
Host smart-d12dbae8-8aec-486a-aeed-bdbde63e52b8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45832715 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_T
EST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
7.lc_ctrl_stress_all.45832715
Directory /workspace/17.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.lc_ctrl_volatile_unlock_smoke.3053470363
Short name T729
Test name
Test status
Simulation time 17100583 ps
CPU time 0.96 seconds
Started Jun 06 01:11:35 PM PDT 24
Finished Jun 06 01:11:37 PM PDT 24
Peak memory 211488 kb
Host smart-d478a275-8c1a-421b-be7e-158f78ba5987
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053470363 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_c
trl_volatile_unlock_smoke.3053470363
Directory /workspace/17.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_alert_test.3689784262
Short name T337
Test name
Test status
Simulation time 46487489 ps
CPU time 1.06 seconds
Started Jun 06 01:12:03 PM PDT 24
Finished Jun 06 01:12:06 PM PDT 24
Peak memory 208716 kb
Host smart-ab000432-7195-4456-8482-ca387e9bc4dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689784262 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_alert_test.3689784262
Directory /workspace/18.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.lc_ctrl_errors.1062977724
Short name T819
Test name
Test status
Simulation time 1457755555 ps
CPU time 8.52 seconds
Started Jun 06 01:11:50 PM PDT 24
Finished Jun 06 01:12:02 PM PDT 24
Peak memory 218024 kb
Host smart-52077cb7-c3c3-478e-b425-3ca5eddde3b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062977724 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_errors.1062977724
Directory /workspace/18.lc_ctrl_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_access.2783504658
Short name T24
Test name
Test status
Simulation time 4412715621 ps
CPU time 25.71 seconds
Started Jun 06 01:11:51 PM PDT 24
Finished Jun 06 01:12:20 PM PDT 24
Peak memory 217756 kb
Host smart-6ba04795-ea81-4f19-9945-2358b19c0e4f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783504658 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_access.2783504658
Directory /workspace/18.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_errors.2428710075
Short name T660
Test name
Test status
Simulation time 7663946837 ps
CPU time 32.38 seconds
Started Jun 06 01:11:48 PM PDT 24
Finished Jun 06 01:12:22 PM PDT 24
Peak memory 218976 kb
Host smart-18c90737-b042-4d85-898a-7ad1e673dc9e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428710075 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_e
rrors.2428710075
Directory /workspace/18.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_prog_failure.1858450153
Short name T608
Test name
Test status
Simulation time 1003784643 ps
CPU time 8.71 seconds
Started Jun 06 01:11:50 PM PDT 24
Finished Jun 06 01:12:02 PM PDT 24
Peak memory 217960 kb
Host smart-66f8bc88-2f11-43bd-92c4-0d955fb7fb52
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858450153 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jta
g_prog_failure.1858450153
Directory /workspace/18.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_smoke.2010538812
Short name T605
Test name
Test status
Simulation time 118395795 ps
CPU time 4.25 seconds
Started Jun 06 01:11:49 PM PDT 24
Finished Jun 06 01:11:57 PM PDT 24
Peak memory 217628 kb
Host smart-1b9c17a5-0974-414a-832a-843b08a01f2b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010538812 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_smoke
.2010538812
Directory /workspace/18.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_failure.959226595
Short name T777
Test name
Test status
Simulation time 3771139597 ps
CPU time 30.58 seconds
Started Jun 06 01:11:51 PM PDT 24
Finished Jun 06 01:12:25 PM PDT 24
Peak memory 250920 kb
Host smart-3c390001-f9e9-4bed-a5f5-8ef7e3a4af5d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959226595 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jta
g_state_failure.959226595
Directory /workspace/18.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_post_trans.4206042087
Short name T583
Test name
Test status
Simulation time 1811389383 ps
CPU time 11.81 seconds
Started Jun 06 01:11:54 PM PDT 24
Finished Jun 06 01:12:08 PM PDT 24
Peak memory 250472 kb
Host smart-030daf00-4316-40d7-b1f6-c10dc1107bb3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206042087 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl
_jtag_state_post_trans.4206042087
Directory /workspace/18.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_prog_failure.3734028227
Short name T702
Test name
Test status
Simulation time 246795811 ps
CPU time 3.23 seconds
Started Jun 06 01:11:50 PM PDT 24
Finished Jun 06 01:11:57 PM PDT 24
Peak memory 217964 kb
Host smart-39a716e0-1152-4338-857b-c73e0a60856b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734028227 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_prog_failure.3734028227
Directory /workspace/18.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_mubi.4250447336
Short name T504
Test name
Test status
Simulation time 1391073252 ps
CPU time 16.68 seconds
Started Jun 06 01:11:51 PM PDT 24
Finished Jun 06 01:12:11 PM PDT 24
Peak memory 218112 kb
Host smart-dfc40296-1b32-49e3-96e2-c5035320bd5f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250447336 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_mubi.4250447336
Directory /workspace/18.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_digest.581193723
Short name T441
Test name
Test status
Simulation time 840269663 ps
CPU time 21.59 seconds
Started Jun 06 01:12:01 PM PDT 24
Finished Jun 06 01:12:24 PM PDT 24
Peak memory 217948 kb
Host smart-871fc6bb-cb12-4752-a76c-b0b9782c7e2b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581193723 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_di
gest.581193723
Directory /workspace/18.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_mux.1971974322
Short name T833
Test name
Test status
Simulation time 1544183116 ps
CPU time 11.42 seconds
Started Jun 06 01:11:52 PM PDT 24
Finished Jun 06 01:12:06 PM PDT 24
Peak memory 217988 kb
Host smart-1c3d9bf6-9cf8-4566-8c2c-a9836fdd162b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971974322 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_mux.
1971974322
Directory /workspace/18.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/18.lc_ctrl_security_escalation.2418119821
Short name T624
Test name
Test status
Simulation time 217233837 ps
CPU time 10.63 seconds
Started Jun 06 01:11:50 PM PDT 24
Finished Jun 06 01:12:04 PM PDT 24
Peak memory 226072 kb
Host smart-7c9869ec-49e3-4de3-8e2f-cf73f042952f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418119821 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_security_escalation.2418119821
Directory /workspace/18.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/18.lc_ctrl_smoke.3787257498
Short name T769
Test name
Test status
Simulation time 32695324 ps
CPU time 2.65 seconds
Started Jun 06 01:11:51 PM PDT 24
Finished Jun 06 01:11:57 PM PDT 24
Peak memory 214092 kb
Host smart-09cadc96-2d78-4feb-aa89-9969c454aa38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787257498 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_smoke.3787257498
Directory /workspace/18.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_failure.1294126848
Short name T574
Test name
Test status
Simulation time 482663552 ps
CPU time 27.48 seconds
Started Jun 06 01:11:49 PM PDT 24
Finished Jun 06 01:12:20 PM PDT 24
Peak memory 250936 kb
Host smart-40a0e8b4-afcc-4e91-9e98-6d2b01332387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294126848 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_failure.1294126848
Directory /workspace/18.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_post_trans.3646108338
Short name T489
Test name
Test status
Simulation time 202367934 ps
CPU time 6.32 seconds
Started Jun 06 01:11:50 PM PDT 24
Finished Jun 06 01:12:00 PM PDT 24
Peak memory 242824 kb
Host smart-f9d15da2-13ea-48df-8549-1f0241b35bf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646108338 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_post_trans.3646108338
Directory /workspace/18.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all.3526949541
Short name T73
Test name
Test status
Simulation time 40199756149 ps
CPU time 318.64 seconds
Started Jun 06 01:12:01 PM PDT 24
Finished Jun 06 01:17:22 PM PDT 24
Peak memory 251032 kb
Host smart-287478da-96b9-4b95-95bf-f29e1e475ebd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526949541 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.lc_ctrl_stress_all.3526949541
Directory /workspace/18.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.lc_ctrl_volatile_unlock_smoke.2935489849
Short name T327
Test name
Test status
Simulation time 23261426 ps
CPU time 0.91 seconds
Started Jun 06 01:11:52 PM PDT 24
Finished Jun 06 01:11:56 PM PDT 24
Peak memory 208792 kb
Host smart-235dd7b6-4c6e-426c-9dbe-51f19e73101b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935489849 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_c
trl_volatile_unlock_smoke.2935489849
Directory /workspace/18.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_alert_test.909049696
Short name T291
Test name
Test status
Simulation time 15601912 ps
CPU time 1.09 seconds
Started Jun 06 01:12:02 PM PDT 24
Finished Jun 06 01:12:05 PM PDT 24
Peak memory 208680 kb
Host smart-cc3c872c-1c1a-4d3a-b261-b548f9d132c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909049696 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_alert_test.909049696
Directory /workspace/19.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.lc_ctrl_errors.527799602
Short name T390
Test name
Test status
Simulation time 2073593639 ps
CPU time 17.45 seconds
Started Jun 06 01:12:03 PM PDT 24
Finished Jun 06 01:12:23 PM PDT 24
Peak memory 217868 kb
Host smart-f391b23f-079c-489a-abd7-5814d7733852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=527799602 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_errors.527799602
Directory /workspace/19.lc_ctrl_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_access.2345063749
Short name T7
Test name
Test status
Simulation time 598109520 ps
CPU time 2.87 seconds
Started Jun 06 01:12:00 PM PDT 24
Finished Jun 06 01:12:04 PM PDT 24
Peak memory 209516 kb
Host smart-aa234383-1634-4ee9-98d5-095b52c12be7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345063749 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_access.2345063749
Directory /workspace/19.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_errors.1424397663
Short name T23
Test name
Test status
Simulation time 2102444246 ps
CPU time 24.91 seconds
Started Jun 06 01:12:10 PM PDT 24
Finished Jun 06 01:12:37 PM PDT 24
Peak memory 217884 kb
Host smart-f4cb2a81-b4b1-4806-a720-d4aea63cd273
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424397663 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_e
rrors.1424397663
Directory /workspace/19.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_prog_failure.1543340087
Short name T586
Test name
Test status
Simulation time 4129255278 ps
CPU time 12.21 seconds
Started Jun 06 01:12:00 PM PDT 24
Finished Jun 06 01:12:14 PM PDT 24
Peak memory 217860 kb
Host smart-17fcb7de-3b2d-4e8d-abe0-322961d36c91
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543340087 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jta
g_prog_failure.1543340087
Directory /workspace/19.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_smoke.456397504
Short name T757
Test name
Test status
Simulation time 578511564 ps
CPU time 4.4 seconds
Started Jun 06 01:12:14 PM PDT 24
Finished Jun 06 01:12:20 PM PDT 24
Peak memory 217584 kb
Host smart-651b1519-710c-496e-9a55-c726f806ce46
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456397504 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_smoke.
456397504
Directory /workspace/19.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_failure.4286869895
Short name T329
Test name
Test status
Simulation time 1825429401 ps
CPU time 62.25 seconds
Started Jun 06 01:12:11 PM PDT 24
Finished Jun 06 01:13:16 PM PDT 24
Peak memory 283676 kb
Host smart-aba56174-7d18-46a5-a615-2d22563e4dbb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286869895 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jt
ag_state_failure.4286869895
Directory /workspace/19.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_post_trans.2813626274
Short name T484
Test name
Test status
Simulation time 921202513 ps
CPU time 19.93 seconds
Started Jun 06 01:12:03 PM PDT 24
Finished Jun 06 01:12:26 PM PDT 24
Peak memory 250984 kb
Host smart-6bf41c54-6a30-4f1b-8d2f-d02bf1b04318
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813626274 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl
_jtag_state_post_trans.2813626274
Directory /workspace/19.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_prog_failure.3950455725
Short name T606
Test name
Test status
Simulation time 465487394 ps
CPU time 2.88 seconds
Started Jun 06 01:12:01 PM PDT 24
Finished Jun 06 01:12:05 PM PDT 24
Peak memory 217964 kb
Host smart-0b610bdf-3f04-4900-a4ce-efb2eb79f145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950455725 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_prog_failure.3950455725
Directory /workspace/19.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_mubi.2704280211
Short name T453
Test name
Test status
Simulation time 2298752149 ps
CPU time 15.78 seconds
Started Jun 06 01:12:12 PM PDT 24
Finished Jun 06 01:12:30 PM PDT 24
Peak memory 218932 kb
Host smart-266de5f2-2c22-4112-afcb-ed18806e194c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704280211 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_mubi.2704280211
Directory /workspace/19.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_digest.1602047477
Short name T425
Test name
Test status
Simulation time 524921036 ps
CPU time 10.32 seconds
Started Jun 06 01:12:07 PM PDT 24
Finished Jun 06 01:12:20 PM PDT 24
Peak memory 225912 kb
Host smart-7c4d0e96-991d-4051-8851-7716a1df11c4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602047477 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_d
igest.1602047477
Directory /workspace/19.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_mux.164883199
Short name T517
Test name
Test status
Simulation time 804464162 ps
CPU time 6.53 seconds
Started Jun 06 01:12:09 PM PDT 24
Finished Jun 06 01:12:17 PM PDT 24
Peak memory 217992 kb
Host smart-e2099851-ed60-448b-89ef-c7063d10688e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164883199 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_mux.164883199
Directory /workspace/19.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/19.lc_ctrl_security_escalation.336650085
Short name T700
Test name
Test status
Simulation time 503940206 ps
CPU time 10 seconds
Started Jun 06 01:12:07 PM PDT 24
Finished Jun 06 01:12:20 PM PDT 24
Peak memory 217940 kb
Host smart-c3d531d7-b9b6-4ff6-b846-9bb777455db0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336650085 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_security_escalation.336650085
Directory /workspace/19.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/19.lc_ctrl_smoke.2441686413
Short name T437
Test name
Test status
Simulation time 531129692 ps
CPU time 5.09 seconds
Started Jun 06 01:12:02 PM PDT 24
Finished Jun 06 01:12:09 PM PDT 24
Peak memory 218164 kb
Host smart-47be0a9e-a7cb-4d0b-a26c-c220eea4f9a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441686413 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_smoke.2441686413
Directory /workspace/19.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_failure.3909853473
Short name T715
Test name
Test status
Simulation time 528763607 ps
CPU time 28.96 seconds
Started Jun 06 01:12:04 PM PDT 24
Finished Jun 06 01:12:35 PM PDT 24
Peak memory 250980 kb
Host smart-fb136370-00c5-42ff-a6f4-43a40ba55484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909853473 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_failure.3909853473
Directory /workspace/19.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_post_trans.4112992129
Short name T351
Test name
Test status
Simulation time 68052404 ps
CPU time 6.95 seconds
Started Jun 06 01:12:03 PM PDT 24
Finished Jun 06 01:12:12 PM PDT 24
Peak memory 250408 kb
Host smart-5a45cdbd-e2ff-4f9a-a147-03d339b6a4db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112992129 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_post_trans.4112992129
Directory /workspace/19.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all.4219286469
Short name T21
Test name
Test status
Simulation time 3819045007 ps
CPU time 127.9 seconds
Started Jun 06 01:12:04 PM PDT 24
Finished Jun 06 01:14:15 PM PDT 24
Peak memory 251036 kb
Host smart-f8bace49-9a5a-475e-860c-d2a5ab139faf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219286469 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.lc_ctrl_stress_all.4219286469
Directory /workspace/19.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.lc_ctrl_volatile_unlock_smoke.2626501150
Short name T542
Test name
Test status
Simulation time 13851940 ps
CPU time 0.98 seconds
Started Jun 06 01:12:01 PM PDT 24
Finished Jun 06 01:12:03 PM PDT 24
Peak memory 208600 kb
Host smart-ce4962ce-d504-45aa-92dd-dabc51ae3f05
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626501150 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_c
trl_volatile_unlock_smoke.2626501150
Directory /workspace/19.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_alert_test.3277698746
Short name T300
Test name
Test status
Simulation time 29100731 ps
CPU time 1.31 seconds
Started Jun 06 01:09:43 PM PDT 24
Finished Jun 06 01:09:46 PM PDT 24
Peak memory 208696 kb
Host smart-e2c65bf6-c31f-40ca-b4a8-e7db641d4dd9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277698746 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_alert_test.3277698746
Directory /workspace/2.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.lc_ctrl_errors.1037834717
Short name T319
Test name
Test status
Simulation time 355896744 ps
CPU time 12.61 seconds
Started Jun 06 01:09:30 PM PDT 24
Finished Jun 06 01:09:44 PM PDT 24
Peak memory 217984 kb
Host smart-0c94fdbe-dcd2-4ed6-a57a-6a9e64a311cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037834717 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_errors.1037834717
Directory /workspace/2.lc_ctrl_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_access.1106989545
Short name T103
Test name
Test status
Simulation time 516739912 ps
CPU time 6.51 seconds
Started Jun 06 01:09:45 PM PDT 24
Finished Jun 06 01:09:52 PM PDT 24
Peak memory 209480 kb
Host smart-14d84279-221d-4c45-9c04-518afb685172
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106989545 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_access.1106989545
Directory /workspace/2.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_errors.2823661067
Short name T607
Test name
Test status
Simulation time 10262633098 ps
CPU time 22.39 seconds
Started Jun 06 01:09:43 PM PDT 24
Finished Jun 06 01:10:07 PM PDT 24
Peak memory 218164 kb
Host smart-54f5681b-03e3-4664-9129-565d191c5242
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823661067 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_er
rors.2823661067
Directory /workspace/2.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_priority.2667907718
Short name T527
Test name
Test status
Simulation time 1605957231 ps
CPU time 6.26 seconds
Started Jun 06 01:09:45 PM PDT 24
Finished Jun 06 01:09:52 PM PDT 24
Peak memory 217300 kb
Host smart-0077ee69-33ef-4f77-8786-5707ae3410f1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667907718 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_priority.2
667907718
Directory /workspace/2.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_prog_failure.2692908303
Short name T399
Test name
Test status
Simulation time 2170390102 ps
CPU time 16.14 seconds
Started Jun 06 01:09:42 PM PDT 24
Finished Jun 06 01:10:00 PM PDT 24
Peak memory 217996 kb
Host smart-c90711c2-1a5c-4b90-8727-91ec850eeb56
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692908303 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag
_prog_failure.2692908303
Directory /workspace/2.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_regwen_during_op.3858847722
Short name T5
Test name
Test status
Simulation time 8872256895 ps
CPU time 9.25 seconds
Started Jun 06 01:09:44 PM PDT 24
Finished Jun 06 01:09:54 PM PDT 24
Peak memory 217652 kb
Host smart-843e4b43-893b-4210-aa7f-758e5aa5d250
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858847722 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_regwen_during_op.3858847722
Directory /workspace/2.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_smoke.1179044779
Short name T478
Test name
Test status
Simulation time 371038533 ps
CPU time 6.62 seconds
Started Jun 06 01:09:42 PM PDT 24
Finished Jun 06 01:09:49 PM PDT 24
Peak memory 217660 kb
Host smart-e291768d-03df-471c-b038-8f3651a65d03
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179044779 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_smoke.
1179044779
Directory /workspace/2.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_failure.3566240005
Short name T569
Test name
Test status
Simulation time 38541382080 ps
CPU time 72.37 seconds
Started Jun 06 01:09:44 PM PDT 24
Finished Jun 06 01:10:57 PM PDT 24
Peak memory 267404 kb
Host smart-7d7a799f-50ad-41e8-a3fe-e8c266dabdb3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566240005 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jta
g_state_failure.3566240005
Directory /workspace/2.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_post_trans.321252128
Short name T293
Test name
Test status
Simulation time 1144364921 ps
CPU time 17.46 seconds
Started Jun 06 01:09:43 PM PDT 24
Finished Jun 06 01:10:01 PM PDT 24
Peak memory 226328 kb
Host smart-134546d0-2c71-4744-b943-35ef63e54986
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321252128 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_j
tag_state_post_trans.321252128
Directory /workspace/2.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_prog_failure.2641807659
Short name T186
Test name
Test status
Simulation time 635653410 ps
CPU time 2.94 seconds
Started Jun 06 01:09:30 PM PDT 24
Finished Jun 06 01:09:34 PM PDT 24
Peak memory 218024 kb
Host smart-7640c462-873d-4dd5-bfe3-3dbd84b9eb96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641807659 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_prog_failure.2641807659
Directory /workspace/2.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_regwen_during_op.2723430800
Short name T119
Test name
Test status
Simulation time 2289462723 ps
CPU time 10.3 seconds
Started Jun 06 01:09:42 PM PDT 24
Finished Jun 06 01:09:54 PM PDT 24
Peak memory 217704 kb
Host smart-24343cdd-6af3-4847-81d3-2ebeae70d753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723430800 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_regwen_during_op.2723430800
Directory /workspace/2.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_cm.734942231
Short name T97
Test name
Test status
Simulation time 214212895 ps
CPU time 41.6 seconds
Started Jun 06 01:09:42 PM PDT 24
Finished Jun 06 01:10:25 PM PDT 24
Peak memory 269648 kb
Host smart-d2efc72f-ef40-4014-8f5c-f2a998c2286b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734942231 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_cm.734942231
Directory /workspace/2.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_mubi.2416078987
Short name T511
Test name
Test status
Simulation time 3462213818 ps
CPU time 17.38 seconds
Started Jun 06 01:09:44 PM PDT 24
Finished Jun 06 01:10:02 PM PDT 24
Peak memory 219332 kb
Host smart-08977f76-473b-493b-a9f7-7ba259823d96
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416078987 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_mubi.2416078987
Directory /workspace/2.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_digest.1219532579
Short name T750
Test name
Test status
Simulation time 784379663 ps
CPU time 9.72 seconds
Started Jun 06 01:09:44 PM PDT 24
Finished Jun 06 01:09:55 PM PDT 24
Peak memory 225908 kb
Host smart-1034d015-0e44-4516-bd73-f460c8c258e1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219532579 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_di
gest.1219532579
Directory /workspace/2.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_mux.4274822310
Short name T348
Test name
Test status
Simulation time 559859492 ps
CPU time 8.16 seconds
Started Jun 06 01:09:44 PM PDT 24
Finished Jun 06 01:09:53 PM PDT 24
Peak memory 218036 kb
Host smart-939ec39c-255c-49d6-93f1-2afee07b0be2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274822310 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_mux.4
274822310
Directory /workspace/2.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/2.lc_ctrl_security_escalation.776427346
Short name T249
Test name
Test status
Simulation time 529340427 ps
CPU time 6.99 seconds
Started Jun 06 01:09:30 PM PDT 24
Finished Jun 06 01:09:38 PM PDT 24
Peak memory 218112 kb
Host smart-a06128ab-c7f1-4c99-aa92-9933ac020e79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776427346 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_security_escalation.776427346
Directory /workspace/2.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/2.lc_ctrl_smoke.3476359759
Short name T79
Test name
Test status
Simulation time 169623708 ps
CPU time 1.26 seconds
Started Jun 06 01:09:29 PM PDT 24
Finished Jun 06 01:09:31 PM PDT 24
Peak memory 217716 kb
Host smart-678a7613-1d5e-4591-b9fb-8adb2b743af2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476359759 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_smoke.3476359759
Directory /workspace/2.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_failure.3030889680
Short name T553
Test name
Test status
Simulation time 153396899 ps
CPU time 16.53 seconds
Started Jun 06 01:09:31 PM PDT 24
Finished Jun 06 01:09:48 PM PDT 24
Peak memory 250964 kb
Host smart-d69195ff-c08e-4dcc-b6c2-ea6e6b5c300e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030889680 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_failure.3030889680
Directory /workspace/2.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_post_trans.3544922731
Short name T296
Test name
Test status
Simulation time 263549109 ps
CPU time 8.27 seconds
Started Jun 06 01:09:34 PM PDT 24
Finished Jun 06 01:09:43 PM PDT 24
Peak memory 251024 kb
Host smart-443e900d-2b1c-4449-9c79-6ed032f04829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544922731 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_post_trans.3544922731
Directory /workspace/2.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all.2124474444
Short name T547
Test name
Test status
Simulation time 4049894763 ps
CPU time 91.94 seconds
Started Jun 06 01:09:44 PM PDT 24
Finished Jun 06 01:11:17 PM PDT 24
Peak memory 251024 kb
Host smart-c3c97daf-6522-43a3-a501-6d18cec25dc6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124474444 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.lc_ctrl_stress_all.2124474444
Directory /workspace/2.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all_with_rand_reset.3842313631
Short name T167
Test name
Test status
Simulation time 27778326142 ps
CPU time 606.49 seconds
Started Jun 06 01:09:45 PM PDT 24
Finished Jun 06 01:19:53 PM PDT 24
Peak memory 293488 kb
Host smart-b3e8c8b6-040b-43a7-8b88-021da0fb1d9a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3842313631 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_stress_all_with_rand_reset.3842313631
Directory /workspace/2.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.lc_ctrl_volatile_unlock_smoke.4279233391
Short name T554
Test name
Test status
Simulation time 50980007 ps
CPU time 0.8 seconds
Started Jun 06 01:09:30 PM PDT 24
Finished Jun 06 01:09:32 PM PDT 24
Peak memory 208480 kb
Host smart-e93c8019-2c63-4e1f-a016-2d50225ba777
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279233391 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ct
rl_volatile_unlock_smoke.4279233391
Directory /workspace/2.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_alert_test.1320337513
Short name T781
Test name
Test status
Simulation time 205606281 ps
CPU time 0.89 seconds
Started Jun 06 01:12:04 PM PDT 24
Finished Jun 06 01:12:07 PM PDT 24
Peak memory 209496 kb
Host smart-dcd2102d-f672-4656-868b-6cbf1541c87f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320337513 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_alert_test.1320337513
Directory /workspace/20.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.lc_ctrl_errors.2497563656
Short name T609
Test name
Test status
Simulation time 665220432 ps
CPU time 24.84 seconds
Started Jun 06 01:12:02 PM PDT 24
Finished Jun 06 01:12:29 PM PDT 24
Peak memory 218000 kb
Host smart-3f1b6b75-d760-40a2-af6f-01b95e298fbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497563656 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_errors.2497563656
Directory /workspace/20.lc_ctrl_errors/latest

Test location /workspace/coverage/default/20.lc_ctrl_jtag_access.2932967648
Short name T29
Test name
Test status
Simulation time 1356533391 ps
CPU time 8.47 seconds
Started Jun 06 01:12:03 PM PDT 24
Finished Jun 06 01:12:14 PM PDT 24
Peak memory 209496 kb
Host smart-7624a5ee-ef99-430f-9ec0-a4b6a386642d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932967648 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_jtag_access.2932967648
Directory /workspace/20.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/20.lc_ctrl_prog_failure.2287455233
Short name T405
Test name
Test status
Simulation time 180207176 ps
CPU time 2.9 seconds
Started Jun 06 01:12:04 PM PDT 24
Finished Jun 06 01:12:09 PM PDT 24
Peak memory 218060 kb
Host smart-c6faf373-ddb0-43d9-8848-cfadaab89fcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287455233 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_prog_failure.2287455233
Directory /workspace/20.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_mubi.1343202965
Short name T339
Test name
Test status
Simulation time 494739077 ps
CPU time 19.12 seconds
Started Jun 06 01:12:12 PM PDT 24
Finished Jun 06 01:12:33 PM PDT 24
Peak memory 226016 kb
Host smart-452ed46c-ae5c-4167-8e09-4c70261d54cd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343202965 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_mubi.1343202965
Directory /workspace/20.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_digest.1067799554
Short name T499
Test name
Test status
Simulation time 652347143 ps
CPU time 12.28 seconds
Started Jun 06 01:12:01 PM PDT 24
Finished Jun 06 01:12:15 PM PDT 24
Peak memory 217932 kb
Host smart-b45629fe-c3c0-4d68-8546-32b7a0dfd2dc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067799554 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_d
igest.1067799554
Directory /workspace/20.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_mux.293232163
Short name T347
Test name
Test status
Simulation time 1279756269 ps
CPU time 10.9 seconds
Started Jun 06 01:12:01 PM PDT 24
Finished Jun 06 01:12:13 PM PDT 24
Peak memory 218028 kb
Host smart-9c7cd068-5f81-4b34-bdb9-04364055cb78
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293232163 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_mux.293232163
Directory /workspace/20.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/20.lc_ctrl_security_escalation.1164870453
Short name T666
Test name
Test status
Simulation time 1473054000 ps
CPU time 14.51 seconds
Started Jun 06 01:12:02 PM PDT 24
Finished Jun 06 01:12:18 PM PDT 24
Peak memory 218104 kb
Host smart-4ce2ac39-e2e9-4910-a177-6f7f799c1eaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164870453 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_security_escalation.1164870453
Directory /workspace/20.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/20.lc_ctrl_smoke.379260536
Short name T107
Test name
Test status
Simulation time 60370514 ps
CPU time 2.91 seconds
Started Jun 06 01:12:04 PM PDT 24
Finished Jun 06 01:12:09 PM PDT 24
Peak memory 217736 kb
Host smart-ae4007f8-478b-4e3c-9449-f69a812ca858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379260536 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_smoke.379260536
Directory /workspace/20.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_failure.3585224818
Short name T477
Test name
Test status
Simulation time 475118014 ps
CPU time 22.7 seconds
Started Jun 06 01:12:13 PM PDT 24
Finished Jun 06 01:12:38 PM PDT 24
Peak memory 250916 kb
Host smart-39a4f93f-64f3-4efb-9e82-d87f185e29b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585224818 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_failure.3585224818
Directory /workspace/20.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_post_trans.1993617356
Short name T277
Test name
Test status
Simulation time 255907902 ps
CPU time 7.22 seconds
Started Jun 06 01:12:04 PM PDT 24
Finished Jun 06 01:12:14 PM PDT 24
Peak memory 244416 kb
Host smart-576d8f68-6de1-4f11-a8d5-e366fea6371f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993617356 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_post_trans.1993617356
Directory /workspace/20.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/20.lc_ctrl_stress_all.559782278
Short name T741
Test name
Test status
Simulation time 5216638921 ps
CPU time 47.36 seconds
Started Jun 06 01:12:01 PM PDT 24
Finished Jun 06 01:12:50 PM PDT 24
Peak memory 250620 kb
Host smart-6b17ee03-16ad-4be9-b082-1efd98f32ae5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559782278 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.lc_ctrl_stress_all.559782278
Directory /workspace/20.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.lc_ctrl_volatile_unlock_smoke.1498034322
Short name T782
Test name
Test status
Simulation time 91945401 ps
CPU time 0.86 seconds
Started Jun 06 01:12:02 PM PDT 24
Finished Jun 06 01:12:05 PM PDT 24
Peak memory 211468 kb
Host smart-821857fb-56c7-4a81-82e3-bec0ac248a6f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498034322 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_c
trl_volatile_unlock_smoke.1498034322
Directory /workspace/20.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_alert_test.989595738
Short name T847
Test name
Test status
Simulation time 20244622 ps
CPU time 1.17 seconds
Started Jun 06 01:12:12 PM PDT 24
Finished Jun 06 01:12:15 PM PDT 24
Peak memory 209508 kb
Host smart-2ed8c962-105a-40b9-bd15-32262d1aa9a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989595738 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_alert_test.989595738
Directory /workspace/21.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.lc_ctrl_errors.3611429270
Short name T860
Test name
Test status
Simulation time 1483225504 ps
CPU time 10.96 seconds
Started Jun 06 01:12:10 PM PDT 24
Finished Jun 06 01:12:24 PM PDT 24
Peak memory 218060 kb
Host smart-aa28359e-772b-4733-b33d-2d14076435b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611429270 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_errors.3611429270
Directory /workspace/21.lc_ctrl_errors/latest

Test location /workspace/coverage/default/21.lc_ctrl_jtag_access.1754349446
Short name T391
Test name
Test status
Simulation time 126255365 ps
CPU time 1.1 seconds
Started Jun 06 01:12:10 PM PDT 24
Finished Jun 06 01:12:13 PM PDT 24
Peak memory 216832 kb
Host smart-eb7436f7-7763-4b6f-9004-fb31def19ec6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754349446 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_jtag_access.1754349446
Directory /workspace/21.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/21.lc_ctrl_prog_failure.3570701535
Short name T710
Test name
Test status
Simulation time 57432671 ps
CPU time 1.55 seconds
Started Jun 06 01:12:00 PM PDT 24
Finished Jun 06 01:12:03 PM PDT 24
Peak memory 218044 kb
Host smart-db0e4dae-101b-4367-858e-ce5bf32041c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570701535 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_prog_failure.3570701535
Directory /workspace/21.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_mubi.3951106957
Short name T532
Test name
Test status
Simulation time 805915671 ps
CPU time 20.11 seconds
Started Jun 06 01:12:08 PM PDT 24
Finished Jun 06 01:12:30 PM PDT 24
Peak memory 218880 kb
Host smart-f5eb0fe5-5e38-4dcd-9236-9e38cbfbd058
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951106957 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_mubi.3951106957
Directory /workspace/21.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_digest.1538549376
Short name T796
Test name
Test status
Simulation time 652722149 ps
CPU time 10.76 seconds
Started Jun 06 01:12:14 PM PDT 24
Finished Jun 06 01:12:27 PM PDT 24
Peak memory 217860 kb
Host smart-25ef2d06-b5c1-46db-8cb9-d03ae0580ce8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538549376 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_d
igest.1538549376
Directory /workspace/21.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_mux.2343358903
Short name T445
Test name
Test status
Simulation time 2003434114 ps
CPU time 15.28 seconds
Started Jun 06 01:12:10 PM PDT 24
Finished Jun 06 01:12:28 PM PDT 24
Peak memory 218028 kb
Host smart-758345e2-1931-41d9-8a82-df5a91dd7026
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343358903 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_mux.
2343358903
Directory /workspace/21.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/21.lc_ctrl_security_escalation.1090604946
Short name T658
Test name
Test status
Simulation time 5494607187 ps
CPU time 10.82 seconds
Started Jun 06 01:12:08 PM PDT 24
Finished Jun 06 01:12:21 PM PDT 24
Peak memory 218124 kb
Host smart-59f83391-9d73-4f2f-9f03-300182f018fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090604946 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_security_escalation.1090604946
Directory /workspace/21.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/21.lc_ctrl_smoke.475981267
Short name T810
Test name
Test status
Simulation time 220502683 ps
CPU time 3.05 seconds
Started Jun 06 01:12:05 PM PDT 24
Finished Jun 06 01:12:10 PM PDT 24
Peak memory 217708 kb
Host smart-8af16db6-87df-4bc6-95ab-0a88bbe6d429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475981267 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_smoke.475981267
Directory /workspace/21.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_failure.2464184703
Short name T275
Test name
Test status
Simulation time 310751467 ps
CPU time 29.01 seconds
Started Jun 06 01:12:00 PM PDT 24
Finished Jun 06 01:12:31 PM PDT 24
Peak memory 251028 kb
Host smart-bfdd25dd-f921-486e-8b16-6208b1f4e02e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464184703 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_failure.2464184703
Directory /workspace/21.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_post_trans.3534148072
Short name T620
Test name
Test status
Simulation time 267855539 ps
CPU time 9.23 seconds
Started Jun 06 01:12:02 PM PDT 24
Finished Jun 06 01:12:13 PM PDT 24
Peak memory 245616 kb
Host smart-a4fa6a68-ae38-477c-bf33-fceb6dccd470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534148072 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_post_trans.3534148072
Directory /workspace/21.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/21.lc_ctrl_stress_all.363601565
Short name T734
Test name
Test status
Simulation time 2673801643 ps
CPU time 57.46 seconds
Started Jun 06 01:12:09 PM PDT 24
Finished Jun 06 01:13:09 PM PDT 24
Peak memory 267468 kb
Host smart-f3f85c7d-d545-4b4d-bcb6-b7cf85987203
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363601565 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.lc_ctrl_stress_all.363601565
Directory /workspace/21.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.lc_ctrl_stress_all_with_rand_reset.62890072
Short name T806
Test name
Test status
Simulation time 13093498058 ps
CPU time 478.74 seconds
Started Jun 06 01:12:09 PM PDT 24
Finished Jun 06 01:20:10 PM PDT 24
Peak memory 496860 kb
Host smart-e5153ba9-f93b-47ad-b849-a063300a46ac
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=62890072 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_stress_all_with_rand_reset.62890072
Directory /workspace/21.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.lc_ctrl_volatile_unlock_smoke.3015449642
Short name T369
Test name
Test status
Simulation time 81257298 ps
CPU time 1.04 seconds
Started Jun 06 01:12:11 PM PDT 24
Finished Jun 06 01:12:14 PM PDT 24
Peak memory 211536 kb
Host smart-06b315f7-00dc-43ea-813d-dd5a766c2bc5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015449642 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_c
trl_volatile_unlock_smoke.3015449642
Directory /workspace/21.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_alert_test.2088216397
Short name T627
Test name
Test status
Simulation time 27940276 ps
CPU time 0.95 seconds
Started Jun 06 01:12:08 PM PDT 24
Finished Jun 06 01:12:11 PM PDT 24
Peak memory 208568 kb
Host smart-33abc6e9-dc72-4314-88a1-70454cfa4e52
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088216397 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_alert_test.2088216397
Directory /workspace/22.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.lc_ctrl_errors.1298786295
Short name T678
Test name
Test status
Simulation time 1998447326 ps
CPU time 14.74 seconds
Started Jun 06 01:12:08 PM PDT 24
Finished Jun 06 01:12:25 PM PDT 24
Peak memory 218088 kb
Host smart-e02937ad-4b8b-4522-b9d9-6402d9248a85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298786295 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_errors.1298786295
Directory /workspace/22.lc_ctrl_errors/latest

Test location /workspace/coverage/default/22.lc_ctrl_jtag_access.1558448347
Short name T201
Test name
Test status
Simulation time 53390862 ps
CPU time 1.68 seconds
Started Jun 06 01:12:08 PM PDT 24
Finished Jun 06 01:12:12 PM PDT 24
Peak memory 216776 kb
Host smart-4f659cea-b297-4b6f-a67b-aa91640d642a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558448347 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_jtag_access.1558448347
Directory /workspace/22.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/22.lc_ctrl_prog_failure.2387176205
Short name T254
Test name
Test status
Simulation time 73049365 ps
CPU time 2.08 seconds
Started Jun 06 01:12:10 PM PDT 24
Finished Jun 06 01:12:14 PM PDT 24
Peak memory 217956 kb
Host smart-179b39e1-478a-491c-935a-abcf10ac5797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387176205 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_prog_failure.2387176205
Directory /workspace/22.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_mubi.3966696857
Short name T628
Test name
Test status
Simulation time 1869555323 ps
CPU time 13.61 seconds
Started Jun 06 01:12:10 PM PDT 24
Finished Jun 06 01:12:26 PM PDT 24
Peak memory 218976 kb
Host smart-b888827d-f6e2-4811-8a4e-dcb7699cc71c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966696857 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_mubi.3966696857
Directory /workspace/22.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_digest.3119322197
Short name T571
Test name
Test status
Simulation time 2382751217 ps
CPU time 19.88 seconds
Started Jun 06 01:12:09 PM PDT 24
Finished Jun 06 01:12:31 PM PDT 24
Peak memory 226092 kb
Host smart-1f701ef9-cb62-42e9-b5d3-c0bdd14f0670
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119322197 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_d
igest.3119322197
Directory /workspace/22.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_mux.1917058310
Short name T444
Test name
Test status
Simulation time 755919981 ps
CPU time 9.18 seconds
Started Jun 06 01:12:15 PM PDT 24
Finished Jun 06 01:12:27 PM PDT 24
Peak memory 217940 kb
Host smart-31a8ef64-9aaa-487a-b093-7b577d8bee30
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917058310 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_mux.
1917058310
Directory /workspace/22.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/22.lc_ctrl_security_escalation.659837084
Short name T728
Test name
Test status
Simulation time 215769848 ps
CPU time 5.63 seconds
Started Jun 06 01:12:08 PM PDT 24
Finished Jun 06 01:12:16 PM PDT 24
Peak memory 218096 kb
Host smart-20496bed-4be7-4f9e-af42-19e167ea98f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659837084 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_security_escalation.659837084
Directory /workspace/22.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/22.lc_ctrl_smoke.2557849248
Short name T69
Test name
Test status
Simulation time 354042898 ps
CPU time 2.69 seconds
Started Jun 06 01:12:09 PM PDT 24
Finished Jun 06 01:12:13 PM PDT 24
Peak memory 217692 kb
Host smart-0ad44db2-2f6a-4b34-ad38-156844dd01e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557849248 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_smoke.2557849248
Directory /workspace/22.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_failure.175673924
Short name T95
Test name
Test status
Simulation time 540181022 ps
CPU time 17.07 seconds
Started Jun 06 01:12:16 PM PDT 24
Finished Jun 06 01:12:36 PM PDT 24
Peak memory 250908 kb
Host smart-88a7b890-b86c-444c-b08d-70a3b166a7ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175673924 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_failure.175673924
Directory /workspace/22.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_post_trans.1043095594
Short name T304
Test name
Test status
Simulation time 78494078 ps
CPU time 3.23 seconds
Started Jun 06 01:12:10 PM PDT 24
Finished Jun 06 01:12:15 PM PDT 24
Peak memory 222536 kb
Host smart-4db2e192-d392-4a35-bfdc-efaf07353940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043095594 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_post_trans.1043095594
Directory /workspace/22.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/22.lc_ctrl_stress_all.1503278857
Short name T35
Test name
Test status
Simulation time 5789138832 ps
CPU time 81.81 seconds
Started Jun 06 01:12:10 PM PDT 24
Finished Jun 06 01:13:34 PM PDT 24
Peak memory 275604 kb
Host smart-04b10f07-5e36-4aa3-9af8-d69ebadc6f1f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503278857 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.lc_ctrl_stress_all.1503278857
Directory /workspace/22.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.lc_ctrl_stress_all_with_rand_reset.392494567
Short name T176
Test name
Test status
Simulation time 177720443826 ps
CPU time 338.62 seconds
Started Jun 06 01:12:15 PM PDT 24
Finished Jun 06 01:17:57 PM PDT 24
Peak memory 283804 kb
Host smart-3c523c9d-5551-4c92-abe0-63fa44652c59
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=392494567 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_stress_all_with_rand_reset.392494567
Directory /workspace/22.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.lc_ctrl_volatile_unlock_smoke.4187330800
Short name T83
Test name
Test status
Simulation time 41895602 ps
CPU time 1.04 seconds
Started Jun 06 01:12:08 PM PDT 24
Finished Jun 06 01:12:11 PM PDT 24
Peak memory 211644 kb
Host smart-8cc2ace3-f633-491f-8fa3-78884e40a6cd
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187330800 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_c
trl_volatile_unlock_smoke.4187330800
Directory /workspace/22.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_alert_test.2553490161
Short name T519
Test name
Test status
Simulation time 114049364 ps
CPU time 0.93 seconds
Started Jun 06 01:12:15 PM PDT 24
Finished Jun 06 01:12:20 PM PDT 24
Peak memory 209444 kb
Host smart-6432dffa-3ab7-4aec-bd60-dd3cd9311aaf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553490161 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_alert_test.2553490161
Directory /workspace/23.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.lc_ctrl_errors.685857823
Short name T592
Test name
Test status
Simulation time 4691360363 ps
CPU time 10.84 seconds
Started Jun 06 01:12:09 PM PDT 24
Finished Jun 06 01:12:23 PM PDT 24
Peak memory 217940 kb
Host smart-810b7782-982a-4cae-a431-1100502f1e2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685857823 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_errors.685857823
Directory /workspace/23.lc_ctrl_errors/latest

Test location /workspace/coverage/default/23.lc_ctrl_jtag_access.747344195
Short name T601
Test name
Test status
Simulation time 154184886 ps
CPU time 2.75 seconds
Started Jun 06 01:12:08 PM PDT 24
Finished Jun 06 01:12:13 PM PDT 24
Peak memory 209476 kb
Host smart-c3abf06d-8fca-4002-a629-5b2b32974bb1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747344195 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_jtag_access.747344195
Directory /workspace/23.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/23.lc_ctrl_prog_failure.1370253793
Short name T545
Test name
Test status
Simulation time 32752921 ps
CPU time 1.91 seconds
Started Jun 06 01:12:08 PM PDT 24
Finished Jun 06 01:12:12 PM PDT 24
Peak memory 217904 kb
Host smart-bb91dd1f-6345-4f27-9cbc-b7abe2a1d862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370253793 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_prog_failure.1370253793
Directory /workspace/23.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_mubi.302314845
Short name T309
Test name
Test status
Simulation time 694421790 ps
CPU time 8.98 seconds
Started Jun 06 01:12:10 PM PDT 24
Finished Jun 06 01:12:21 PM PDT 24
Peak memory 226092 kb
Host smart-39a4d2c2-ae60-49bd-8319-7559bca38a37
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302314845 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_mubi.302314845
Directory /workspace/23.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_digest.3816507025
Short name T870
Test name
Test status
Simulation time 1596730707 ps
CPU time 12.23 seconds
Started Jun 06 01:12:16 PM PDT 24
Finished Jun 06 01:12:31 PM PDT 24
Peak memory 226036 kb
Host smart-e4e6cafd-6c2c-46d3-9eef-5de66cb8269c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816507025 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_d
igest.3816507025
Directory /workspace/23.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_mux.2595236390
Short name T65
Test name
Test status
Simulation time 1621543190 ps
CPU time 9.77 seconds
Started Jun 06 01:12:19 PM PDT 24
Finished Jun 06 01:12:31 PM PDT 24
Peak memory 218216 kb
Host smart-72f5b829-aaaa-46ef-974e-9623703c8bb6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595236390 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_mux.
2595236390
Directory /workspace/23.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/23.lc_ctrl_security_escalation.4170860065
Short name T331
Test name
Test status
Simulation time 585136624 ps
CPU time 7.98 seconds
Started Jun 06 01:12:08 PM PDT 24
Finished Jun 06 01:12:18 PM PDT 24
Peak memory 218084 kb
Host smart-0925e185-ad8b-4bc2-9c59-1ede400e0ab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170860065 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_security_escalation.4170860065
Directory /workspace/23.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/23.lc_ctrl_smoke.2608775202
Short name T779
Test name
Test status
Simulation time 41306824 ps
CPU time 1.64 seconds
Started Jun 06 01:12:09 PM PDT 24
Finished Jun 06 01:12:13 PM PDT 24
Peak memory 217644 kb
Host smart-6f57ec83-13ea-4b13-930b-87a63f8102de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608775202 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_smoke.2608775202
Directory /workspace/23.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_failure.750358825
Short name T564
Test name
Test status
Simulation time 951572902 ps
CPU time 27.03 seconds
Started Jun 06 01:12:11 PM PDT 24
Finished Jun 06 01:12:40 PM PDT 24
Peak memory 251016 kb
Host smart-4edf9a98-fa51-4a9f-ae48-21e568568213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750358825 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_failure.750358825
Directory /workspace/23.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_post_trans.2989267951
Short name T857
Test name
Test status
Simulation time 1007202020 ps
CPU time 8.2 seconds
Started Jun 06 01:12:09 PM PDT 24
Finished Jun 06 01:12:20 PM PDT 24
Peak memory 250936 kb
Host smart-f5d04310-1402-487d-8b1c-5f340ee98ea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989267951 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_post_trans.2989267951
Directory /workspace/23.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all.2996213299
Short name T831
Test name
Test status
Simulation time 24843072950 ps
CPU time 104.69 seconds
Started Jun 06 01:12:17 PM PDT 24
Finished Jun 06 01:14:05 PM PDT 24
Peak memory 251232 kb
Host smart-d7eb8466-a494-4176-8195-13ee754d2360
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996213299 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.lc_ctrl_stress_all.2996213299
Directory /workspace/23.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.lc_ctrl_volatile_unlock_smoke.1397678461
Short name T387
Test name
Test status
Simulation time 32371077 ps
CPU time 0.74 seconds
Started Jun 06 01:12:09 PM PDT 24
Finished Jun 06 01:12:12 PM PDT 24
Peak memory 208468 kb
Host smart-69bd4653-9fab-4e8d-b661-8f2f4111a8bd
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397678461 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_c
trl_volatile_unlock_smoke.1397678461
Directory /workspace/23.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_alert_test.828874320
Short name T271
Test name
Test status
Simulation time 18960935 ps
CPU time 1.16 seconds
Started Jun 06 01:12:18 PM PDT 24
Finished Jun 06 01:12:22 PM PDT 24
Peak memory 209504 kb
Host smart-0d26e7df-1268-4ada-bd96-059c699b9a99
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828874320 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_alert_test.828874320
Directory /workspace/24.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.lc_ctrl_errors.178082923
Short name T165
Test name
Test status
Simulation time 1369105611 ps
CPU time 11.61 seconds
Started Jun 06 01:12:17 PM PDT 24
Finished Jun 06 01:12:32 PM PDT 24
Peak memory 217912 kb
Host smart-4ef03b41-bbe0-4a3d-8afa-0334cae5d3db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178082923 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_errors.178082923
Directory /workspace/24.lc_ctrl_errors/latest

Test location /workspace/coverage/default/24.lc_ctrl_jtag_access.588349365
Short name T600
Test name
Test status
Simulation time 232358040 ps
CPU time 6.66 seconds
Started Jun 06 01:12:16 PM PDT 24
Finished Jun 06 01:12:27 PM PDT 24
Peak memory 217056 kb
Host smart-2d5c22e0-6da7-4215-b8b4-acc34f79f90f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588349365 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_jtag_access.588349365
Directory /workspace/24.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/24.lc_ctrl_prog_failure.1889184963
Short name T787
Test name
Test status
Simulation time 160446906 ps
CPU time 1.99 seconds
Started Jun 06 01:12:20 PM PDT 24
Finished Jun 06 01:12:24 PM PDT 24
Peak memory 218212 kb
Host smart-ddba7c73-bea0-410c-a51d-0aa01a98ecf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889184963 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_prog_failure.1889184963
Directory /workspace/24.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_mubi.3118888349
Short name T707
Test name
Test status
Simulation time 1010518694 ps
CPU time 12.39 seconds
Started Jun 06 01:12:17 PM PDT 24
Finished Jun 06 01:12:33 PM PDT 24
Peak memory 218932 kb
Host smart-c2bdeb0e-865c-4942-a741-1bf236af49d2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118888349 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_mubi.3118888349
Directory /workspace/24.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_digest.1168809967
Short name T800
Test name
Test status
Simulation time 1151848803 ps
CPU time 10.19 seconds
Started Jun 06 01:12:17 PM PDT 24
Finished Jun 06 01:12:31 PM PDT 24
Peak memory 226012 kb
Host smart-db6aed88-0658-4b96-9877-8e90dd711a5a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168809967 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_d
igest.1168809967
Directory /workspace/24.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_mux.507635196
Short name T190
Test name
Test status
Simulation time 1037397499 ps
CPU time 6.4 seconds
Started Jun 06 01:12:18 PM PDT 24
Finished Jun 06 01:12:28 PM PDT 24
Peak memory 217980 kb
Host smart-d3a9db93-cf0c-452a-ad04-234c315a8670
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507635196 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_mux.507635196
Directory /workspace/24.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/24.lc_ctrl_security_escalation.958195406
Short name T46
Test name
Test status
Simulation time 945085458 ps
CPU time 10.95 seconds
Started Jun 06 01:12:19 PM PDT 24
Finished Jun 06 01:12:33 PM PDT 24
Peak memory 218064 kb
Host smart-2cacebd1-b021-45f8-ab47-af43190118fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958195406 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_security_escalation.958195406
Directory /workspace/24.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/24.lc_ctrl_smoke.2920079716
Short name T382
Test name
Test status
Simulation time 153433438 ps
CPU time 4.8 seconds
Started Jun 06 01:12:16 PM PDT 24
Finished Jun 06 01:12:25 PM PDT 24
Peak memory 217740 kb
Host smart-d9dc9c30-0c9b-4427-b3c2-5c1ca47376ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920079716 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_smoke.2920079716
Directory /workspace/24.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_failure.4213316104
Short name T558
Test name
Test status
Simulation time 445349293 ps
CPU time 28.72 seconds
Started Jun 06 01:12:18 PM PDT 24
Finished Jun 06 01:12:50 PM PDT 24
Peak memory 250944 kb
Host smart-4034a2ee-6126-4eaa-89ad-b674cd619f0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213316104 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_failure.4213316104
Directory /workspace/24.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_post_trans.2053188566
Short name T718
Test name
Test status
Simulation time 338552150 ps
CPU time 6.78 seconds
Started Jun 06 01:12:17 PM PDT 24
Finished Jun 06 01:12:28 PM PDT 24
Peak memory 245516 kb
Host smart-f57c7f21-86bb-46ea-bd71-fbde4e4cfb76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053188566 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_post_trans.2053188566
Directory /workspace/24.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all.3647989165
Short name T301
Test name
Test status
Simulation time 4405740397 ps
CPU time 37.29 seconds
Started Jun 06 01:12:17 PM PDT 24
Finished Jun 06 01:12:58 PM PDT 24
Peak memory 250476 kb
Host smart-e705a3dc-b3fc-42a9-ba97-7642af4ed831
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647989165 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.lc_ctrl_stress_all.3647989165
Directory /workspace/24.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.lc_ctrl_volatile_unlock_smoke.3761016770
Short name T39
Test name
Test status
Simulation time 30254264 ps
CPU time 0.81 seconds
Started Jun 06 01:12:17 PM PDT 24
Finished Jun 06 01:12:21 PM PDT 24
Peak memory 208352 kb
Host smart-f0e58f02-42f2-4e4f-bbdd-9cd02dfbe24c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761016770 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_c
trl_volatile_unlock_smoke.3761016770
Directory /workspace/24.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_alert_test.1575611633
Short name T330
Test name
Test status
Simulation time 25915891 ps
CPU time 0.91 seconds
Started Jun 06 01:12:26 PM PDT 24
Finished Jun 06 01:12:28 PM PDT 24
Peak memory 209320 kb
Host smart-3a217974-83cc-4a6f-9052-945b5026f00c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575611633 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_alert_test.1575611633
Directory /workspace/25.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.lc_ctrl_errors.1300322638
Short name T380
Test name
Test status
Simulation time 1455169598 ps
CPU time 14.48 seconds
Started Jun 06 01:12:24 PM PDT 24
Finished Jun 06 01:12:40 PM PDT 24
Peak memory 217920 kb
Host smart-ba52b487-b93e-4b10-9f2e-a91f76200262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1300322638 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_errors.1300322638
Directory /workspace/25.lc_ctrl_errors/latest

Test location /workspace/coverage/default/25.lc_ctrl_jtag_access.1365942338
Short name T818
Test name
Test status
Simulation time 475879460 ps
CPU time 2.22 seconds
Started Jun 06 01:12:20 PM PDT 24
Finished Jun 06 01:12:24 PM PDT 24
Peak memory 209628 kb
Host smart-ba4de4ff-a39d-48bc-b21a-bfe44908ea76
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365942338 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_jtag_access.1365942338
Directory /workspace/25.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/25.lc_ctrl_prog_failure.546715998
Short name T307
Test name
Test status
Simulation time 19463539 ps
CPU time 1.74 seconds
Started Jun 06 01:12:16 PM PDT 24
Finished Jun 06 01:12:22 PM PDT 24
Peak memory 218092 kb
Host smart-7e687e2f-3146-4da5-9aa8-2e08eb92d9bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546715998 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_prog_failure.546715998
Directory /workspace/25.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_mubi.1263673211
Short name T493
Test name
Test status
Simulation time 611154451 ps
CPU time 9.94 seconds
Started Jun 06 01:12:18 PM PDT 24
Finished Jun 06 01:12:31 PM PDT 24
Peak memory 217956 kb
Host smart-731a3c15-cba7-47c2-945b-6adc676f3467
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263673211 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_mubi.1263673211
Directory /workspace/25.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_digest.1502862053
Short name T45
Test name
Test status
Simulation time 3953493511 ps
CPU time 10.44 seconds
Started Jun 06 01:12:29 PM PDT 24
Finished Jun 06 01:12:41 PM PDT 24
Peak memory 218008 kb
Host smart-c86aee81-762c-44b4-b6df-1b571e2938d4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502862053 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_d
igest.1502862053
Directory /workspace/25.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_mux.2128109961
Short name T495
Test name
Test status
Simulation time 430970710 ps
CPU time 11.9 seconds
Started Jun 06 01:12:25 PM PDT 24
Finished Jun 06 01:12:38 PM PDT 24
Peak memory 218028 kb
Host smart-1719e1a2-41ae-4c50-8359-2a275cebfa65
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128109961 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_mux.
2128109961
Directory /workspace/25.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/25.lc_ctrl_security_escalation.1699619163
Short name T59
Test name
Test status
Simulation time 237304078 ps
CPU time 8.04 seconds
Started Jun 06 01:12:17 PM PDT 24
Finished Jun 06 01:12:29 PM PDT 24
Peak memory 218156 kb
Host smart-e043fd28-eaab-42c8-a34d-868594e4f3d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699619163 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_security_escalation.1699619163
Directory /workspace/25.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/25.lc_ctrl_smoke.753275797
Short name T745
Test name
Test status
Simulation time 176577660 ps
CPU time 2.6 seconds
Started Jun 06 01:12:18 PM PDT 24
Finished Jun 06 01:12:24 PM PDT 24
Peak memory 217748 kb
Host smart-c119cd1d-1f73-4d3b-b145-3d36897139de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753275797 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_smoke.753275797
Directory /workspace/25.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_failure.3042054839
Short name T191
Test name
Test status
Simulation time 525806116 ps
CPU time 29.02 seconds
Started Jun 06 01:12:17 PM PDT 24
Finished Jun 06 01:12:50 PM PDT 24
Peak memory 250872 kb
Host smart-05b44f5c-339a-41ee-940e-98a507506539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042054839 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_failure.3042054839
Directory /workspace/25.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_post_trans.3739697477
Short name T497
Test name
Test status
Simulation time 122503265 ps
CPU time 10.23 seconds
Started Jun 06 01:12:17 PM PDT 24
Finished Jun 06 01:12:31 PM PDT 24
Peak memory 250968 kb
Host smart-27c0cb18-2a05-4c06-ad41-ff0dc06e71a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739697477 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_post_trans.3739697477
Directory /workspace/25.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/25.lc_ctrl_stress_all.1282322224
Short name T102
Test name
Test status
Simulation time 9667357153 ps
CPU time 247.7 seconds
Started Jun 06 01:12:27 PM PDT 24
Finished Jun 06 01:16:36 PM PDT 24
Peak memory 283664 kb
Host smart-3043a992-e70e-4d19-bc77-e251cb2b8342
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282322224 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.lc_ctrl_stress_all.1282322224
Directory /workspace/25.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.lc_ctrl_volatile_unlock_smoke.568932363
Short name T642
Test name
Test status
Simulation time 12099786 ps
CPU time 0.95 seconds
Started Jun 06 01:12:18 PM PDT 24
Finished Jun 06 01:12:22 PM PDT 24
Peak memory 211604 kb
Host smart-ac472638-c5bc-41e7-b99c-ae89009e0f61
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568932363 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ct
rl_volatile_unlock_smoke.568932363
Directory /workspace/25.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_alert_test.1532217037
Short name T732
Test name
Test status
Simulation time 21425178 ps
CPU time 1.19 seconds
Started Jun 06 01:12:27 PM PDT 24
Finished Jun 06 01:12:30 PM PDT 24
Peak memory 208688 kb
Host smart-03b1d96a-802c-4a9e-bdb1-4931ebc1e440
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532217037 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_alert_test.1532217037
Directory /workspace/26.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.lc_ctrl_errors.659374806
Short name T265
Test name
Test status
Simulation time 477111298 ps
CPU time 8.56 seconds
Started Jun 06 01:12:27 PM PDT 24
Finished Jun 06 01:12:38 PM PDT 24
Peak memory 218156 kb
Host smart-2d98a0ae-179f-4149-8fca-c7f2b30ad878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659374806 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_errors.659374806
Directory /workspace/26.lc_ctrl_errors/latest

Test location /workspace/coverage/default/26.lc_ctrl_jtag_access.2468551015
Short name T720
Test name
Test status
Simulation time 3542844795 ps
CPU time 3.69 seconds
Started Jun 06 01:12:27 PM PDT 24
Finished Jun 06 01:12:32 PM PDT 24
Peak memory 217296 kb
Host smart-ac9f1167-b56d-4eda-90b5-e1a43ffa1329
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468551015 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_jtag_access.2468551015
Directory /workspace/26.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/26.lc_ctrl_prog_failure.1446982751
Short name T566
Test name
Test status
Simulation time 63585845 ps
CPU time 2.29 seconds
Started Jun 06 01:12:27 PM PDT 24
Finished Jun 06 01:12:30 PM PDT 24
Peak memory 217992 kb
Host smart-06b79ba8-56c8-4517-a6e9-7056eb4db4de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446982751 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_prog_failure.1446982751
Directory /workspace/26.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_mubi.3259010814
Short name T385
Test name
Test status
Simulation time 348629028 ps
CPU time 11.97 seconds
Started Jun 06 01:12:26 PM PDT 24
Finished Jun 06 01:12:39 PM PDT 24
Peak memory 226136 kb
Host smart-3011487a-be18-46bb-ab4a-5b80bbd61be2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259010814 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_mubi.3259010814
Directory /workspace/26.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_digest.1339582171
Short name T591
Test name
Test status
Simulation time 1687969323 ps
CPU time 11.79 seconds
Started Jun 06 01:12:27 PM PDT 24
Finished Jun 06 01:12:41 PM PDT 24
Peak memory 217972 kb
Host smart-c1285228-7f4a-4667-b4de-7fd02d112b56
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339582171 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_d
igest.1339582171
Directory /workspace/26.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_mux.155333212
Short name T814
Test name
Test status
Simulation time 410394742 ps
CPU time 11.11 seconds
Started Jun 06 01:12:28 PM PDT 24
Finished Jun 06 01:12:40 PM PDT 24
Peak memory 217988 kb
Host smart-39f8f5db-33f2-45f6-927a-101d9677ac97
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155333212 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_mux.155333212
Directory /workspace/26.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/26.lc_ctrl_security_escalation.1091987667
Short name T109
Test name
Test status
Simulation time 1488547563 ps
CPU time 12.39 seconds
Started Jun 06 01:12:28 PM PDT 24
Finished Jun 06 01:12:42 PM PDT 24
Peak memory 225800 kb
Host smart-0aaae09d-fd70-4865-b791-ad95099bb46d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091987667 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_security_escalation.1091987667
Directory /workspace/26.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/26.lc_ctrl_smoke.2583546752
Short name T64
Test name
Test status
Simulation time 104734016 ps
CPU time 2.28 seconds
Started Jun 06 01:12:28 PM PDT 24
Finished Jun 06 01:12:31 PM PDT 24
Peak memory 213888 kb
Host smart-a3f02d05-2186-44a0-9c29-a207996ef611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583546752 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_smoke.2583546752
Directory /workspace/26.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_failure.3302515770
Short name T452
Test name
Test status
Simulation time 572760623 ps
CPU time 17.74 seconds
Started Jun 06 01:12:25 PM PDT 24
Finished Jun 06 01:12:44 PM PDT 24
Peak memory 251004 kb
Host smart-ae7c3b59-5dd0-42b7-9e51-17c0a1b95ca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302515770 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_failure.3302515770
Directory /workspace/26.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_post_trans.2470782714
Short name T555
Test name
Test status
Simulation time 205210915 ps
CPU time 8.03 seconds
Started Jun 06 01:12:25 PM PDT 24
Finished Jun 06 01:12:34 PM PDT 24
Peak memory 250964 kb
Host smart-925d991a-b6ce-412f-8068-072db91b938b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470782714 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_post_trans.2470782714
Directory /workspace/26.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all.36941655
Short name T195
Test name
Test status
Simulation time 32120741866 ps
CPU time 62.16 seconds
Started Jun 06 01:12:25 PM PDT 24
Finished Jun 06 01:13:28 PM PDT 24
Peak memory 251044 kb
Host smart-bb13ef23-530e-4e85-af72-3cf1741d3d78
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36941655 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_T
EST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
6.lc_ctrl_stress_all.36941655
Directory /workspace/26.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all_with_rand_reset.1129576817
Short name T611
Test name
Test status
Simulation time 35567018482 ps
CPU time 1371.92 seconds
Started Jun 06 01:12:28 PM PDT 24
Finished Jun 06 01:35:21 PM PDT 24
Peak memory 660760 kb
Host smart-41e7a60d-48c3-477e-a458-633bc33f5787
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1129576817 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_stress_all_with_rand_reset.1129576817
Directory /workspace/26.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.lc_ctrl_volatile_unlock_smoke.1032263393
Short name T48
Test name
Test status
Simulation time 28075730 ps
CPU time 0.87 seconds
Started Jun 06 01:12:26 PM PDT 24
Finished Jun 06 01:12:29 PM PDT 24
Peak memory 208736 kb
Host smart-1f047109-66e3-4667-9b5b-c98e9971a206
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032263393 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_c
trl_volatile_unlock_smoke.1032263393
Directory /workspace/26.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_alert_test.2542463856
Short name T100
Test name
Test status
Simulation time 42904898 ps
CPU time 0.98 seconds
Started Jun 06 01:12:38 PM PDT 24
Finished Jun 06 01:12:40 PM PDT 24
Peak memory 208552 kb
Host smart-37c97be4-3731-4b2f-80f9-f063466aee93
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542463856 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_alert_test.2542463856
Directory /workspace/27.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.lc_ctrl_errors.2449870485
Short name T197
Test name
Test status
Simulation time 282160706 ps
CPU time 8.74 seconds
Started Jun 06 01:12:27 PM PDT 24
Finished Jun 06 01:12:37 PM PDT 24
Peak memory 218072 kb
Host smart-c2a662e6-757a-4420-9c19-61a8c80e6852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449870485 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_errors.2449870485
Directory /workspace/27.lc_ctrl_errors/latest

Test location /workspace/coverage/default/27.lc_ctrl_jtag_access.3172077680
Short name T372
Test name
Test status
Simulation time 200692272 ps
CPU time 2.89 seconds
Started Jun 06 01:12:26 PM PDT 24
Finished Jun 06 01:12:31 PM PDT 24
Peak memory 209468 kb
Host smart-58ceba3f-32f3-4929-84da-6b9d6810aaf4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172077680 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_jtag_access.3172077680
Directory /workspace/27.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/27.lc_ctrl_prog_failure.3203954944
Short name T373
Test name
Test status
Simulation time 139669280 ps
CPU time 2.4 seconds
Started Jun 06 01:12:28 PM PDT 24
Finished Jun 06 01:12:32 PM PDT 24
Peak memory 218024 kb
Host smart-cc6f3b1f-f74a-41f6-aca8-4ecaee29b42e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203954944 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_prog_failure.3203954944
Directory /workspace/27.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_mubi.3771486034
Short name T393
Test name
Test status
Simulation time 368930756 ps
CPU time 13.45 seconds
Started Jun 06 01:12:28 PM PDT 24
Finished Jun 06 01:12:43 PM PDT 24
Peak memory 226104 kb
Host smart-a5b2df4d-bee8-4130-ba27-da644eb58b3c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771486034 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_mubi.3771486034
Directory /workspace/27.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_digest.2423336888
Short name T282
Test name
Test status
Simulation time 1607324716 ps
CPU time 9.55 seconds
Started Jun 06 01:12:37 PM PDT 24
Finished Jun 06 01:12:48 PM PDT 24
Peak memory 217904 kb
Host smart-172884ca-4cb5-4357-9547-6792e38d3b60
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423336888 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_d
igest.2423336888
Directory /workspace/27.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_mux.2911994164
Short name T674
Test name
Test status
Simulation time 259052864 ps
CPU time 10.29 seconds
Started Jun 06 01:12:27 PM PDT 24
Finished Jun 06 01:12:39 PM PDT 24
Peak memory 217876 kb
Host smart-0541bc0b-ae61-42a7-808a-9a82052a4b4c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911994164 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_mux.
2911994164
Directory /workspace/27.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/27.lc_ctrl_security_escalation.2564215250
Short name T359
Test name
Test status
Simulation time 403563156 ps
CPU time 7.68 seconds
Started Jun 06 01:12:29 PM PDT 24
Finished Jun 06 01:12:38 PM PDT 24
Peak memory 218040 kb
Host smart-759e3ce4-925e-41ca-a5c0-f21aae5baa8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564215250 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_security_escalation.2564215250
Directory /workspace/27.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/27.lc_ctrl_smoke.1576157773
Short name T90
Test name
Test status
Simulation time 36792204 ps
CPU time 2.17 seconds
Started Jun 06 01:12:25 PM PDT 24
Finished Jun 06 01:12:29 PM PDT 24
Peak memory 217736 kb
Host smart-626436d8-8313-4650-af18-1790536c403f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576157773 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_smoke.1576157773
Directory /workspace/27.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_failure.3530438114
Short name T449
Test name
Test status
Simulation time 384710461 ps
CPU time 32.78 seconds
Started Jun 06 01:12:28 PM PDT 24
Finished Jun 06 01:13:02 PM PDT 24
Peak memory 251008 kb
Host smart-817405cd-ac7d-4630-8ccc-8fce6bc01ae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530438114 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_failure.3530438114
Directory /workspace/27.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_post_trans.1251220046
Short name T120
Test name
Test status
Simulation time 286012882 ps
CPU time 4.05 seconds
Started Jun 06 01:12:28 PM PDT 24
Finished Jun 06 01:12:33 PM PDT 24
Peak memory 218208 kb
Host smart-b0dff476-93b7-4f5f-ac48-0c07635261e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251220046 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_post_trans.1251220046
Directory /workspace/27.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all.1679707574
Short name T694
Test name
Test status
Simulation time 194100510927 ps
CPU time 743.32 seconds
Started Jun 06 01:12:35 PM PDT 24
Finished Jun 06 01:24:59 PM PDT 24
Peak memory 313792 kb
Host smart-290397db-2cc9-4d18-8e06-6e61a3d1f90f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679707574 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.lc_ctrl_stress_all.1679707574
Directory /workspace/27.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.lc_ctrl_volatile_unlock_smoke.943718544
Short name T491
Test name
Test status
Simulation time 21302641 ps
CPU time 0.85 seconds
Started Jun 06 01:12:27 PM PDT 24
Finished Jun 06 01:12:30 PM PDT 24
Peak memory 208352 kb
Host smart-727a6dbe-3ebc-4183-90e2-b1bd48535194
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943718544 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ct
rl_volatile_unlock_smoke.943718544
Directory /workspace/27.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_alert_test.190888611
Short name T650
Test name
Test status
Simulation time 43866743 ps
CPU time 1.02 seconds
Started Jun 06 01:12:36 PM PDT 24
Finished Jun 06 01:12:38 PM PDT 24
Peak memory 209396 kb
Host smart-4b87b90c-5a1b-4706-8e19-0f6dfd2746a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190888611 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_alert_test.190888611
Directory /workspace/28.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.lc_ctrl_errors.4123852571
Short name T451
Test name
Test status
Simulation time 3131693941 ps
CPU time 18.88 seconds
Started Jun 06 01:12:34 PM PDT 24
Finished Jun 06 01:12:53 PM PDT 24
Peak memory 218976 kb
Host smart-0bccedc0-f903-4637-868f-72847c12758e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123852571 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_errors.4123852571
Directory /workspace/28.lc_ctrl_errors/latest

Test location /workspace/coverage/default/28.lc_ctrl_jtag_access.986106369
Short name T25
Test name
Test status
Simulation time 259959780 ps
CPU time 3.15 seconds
Started Jun 06 01:12:36 PM PDT 24
Finished Jun 06 01:12:40 PM PDT 24
Peak memory 209508 kb
Host smart-9f4467ff-b74f-49b4-b81a-85e48e2bc4f8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986106369 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_jtag_access.986106369
Directory /workspace/28.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/28.lc_ctrl_prog_failure.1047350791
Short name T770
Test name
Test status
Simulation time 449086869 ps
CPU time 3.6 seconds
Started Jun 06 01:12:38 PM PDT 24
Finished Jun 06 01:12:43 PM PDT 24
Peak memory 218216 kb
Host smart-33191a7c-4209-4283-9751-ae066f11e2e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047350791 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_prog_failure.1047350791
Directory /workspace/28.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_mubi.3401255210
Short name T67
Test name
Test status
Simulation time 1015534795 ps
CPU time 11.14 seconds
Started Jun 06 01:12:38 PM PDT 24
Finished Jun 06 01:12:50 PM PDT 24
Peak memory 226272 kb
Host smart-de9803bc-7744-43f3-ada6-2fbf8c76aa0c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401255210 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_mubi.3401255210
Directory /workspace/28.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_digest.2783212570
Short name T292
Test name
Test status
Simulation time 3558799759 ps
CPU time 27.55 seconds
Started Jun 06 01:12:38 PM PDT 24
Finished Jun 06 01:13:06 PM PDT 24
Peak memory 218364 kb
Host smart-1c224091-e5a5-4955-a79f-e429fb2849d6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783212570 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_d
igest.2783212570
Directory /workspace/28.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_mux.3578361998
Short name T604
Test name
Test status
Simulation time 1025632425 ps
CPU time 9.67 seconds
Started Jun 06 01:12:33 PM PDT 24
Finished Jun 06 01:12:43 PM PDT 24
Peak memory 218008 kb
Host smart-df9e7b82-8792-4735-a31f-6fff919ce5a5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578361998 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_mux.
3578361998
Directory /workspace/28.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/28.lc_ctrl_security_escalation.2503457087
Short name T743
Test name
Test status
Simulation time 1068140697 ps
CPU time 13.47 seconds
Started Jun 06 01:12:37 PM PDT 24
Finished Jun 06 01:12:51 PM PDT 24
Peak memory 217940 kb
Host smart-615a9e05-47a4-40da-8846-fccae37483d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503457087 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_security_escalation.2503457087
Directory /workspace/28.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/28.lc_ctrl_smoke.4084042466
Short name T790
Test name
Test status
Simulation time 50846684 ps
CPU time 2.02 seconds
Started Jun 06 01:12:34 PM PDT 24
Finished Jun 06 01:12:37 PM PDT 24
Peak memory 217708 kb
Host smart-692f14d0-eb66-4352-96da-ab838401d00a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084042466 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_smoke.4084042466
Directory /workspace/28.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_failure.966009162
Short name T179
Test name
Test status
Simulation time 213128872 ps
CPU time 15.11 seconds
Started Jun 06 01:12:37 PM PDT 24
Finished Jun 06 01:12:53 PM PDT 24
Peak memory 243884 kb
Host smart-29bbb3a3-af29-46a2-af88-9837e3a76cc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966009162 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_failure.966009162
Directory /workspace/28.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_post_trans.1763842348
Short name T617
Test name
Test status
Simulation time 309336531 ps
CPU time 7.42 seconds
Started Jun 06 01:12:38 PM PDT 24
Finished Jun 06 01:12:46 PM PDT 24
Peak memory 250960 kb
Host smart-414a5ec7-63a8-4beb-af61-6a30e5f77682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763842348 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_post_trans.1763842348
Directory /workspace/28.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/28.lc_ctrl_stress_all.655586403
Short name T670
Test name
Test status
Simulation time 6758655550 ps
CPU time 39.4 seconds
Started Jun 06 01:12:35 PM PDT 24
Finished Jun 06 01:13:15 PM PDT 24
Peak memory 220312 kb
Host smart-7dc44e33-8c8b-49cc-8db0-47ae087a5665
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655586403 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.lc_ctrl_stress_all.655586403
Directory /workspace/28.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.lc_ctrl_volatile_unlock_smoke.2450514947
Short name T722
Test name
Test status
Simulation time 193964767 ps
CPU time 0.91 seconds
Started Jun 06 01:12:35 PM PDT 24
Finished Jun 06 01:12:36 PM PDT 24
Peak memory 211400 kb
Host smart-37e1a325-3d68-48a4-8f21-1cf65f643e07
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450514947 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_c
trl_volatile_unlock_smoke.2450514947
Directory /workspace/28.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_alert_test.2958385303
Short name T258
Test name
Test status
Simulation time 19198833 ps
CPU time 1.16 seconds
Started Jun 06 01:12:44 PM PDT 24
Finished Jun 06 01:12:46 PM PDT 24
Peak memory 209616 kb
Host smart-aa7c56a5-7a1d-423a-82a0-9dc3031150d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958385303 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_alert_test.2958385303
Directory /workspace/29.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.lc_ctrl_errors.4178978588
Short name T450
Test name
Test status
Simulation time 1169337586 ps
CPU time 12.3 seconds
Started Jun 06 01:12:43 PM PDT 24
Finished Jun 06 01:12:56 PM PDT 24
Peak memory 218016 kb
Host smart-02b96d2c-08c0-4477-b880-5eb16bb9e7f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178978588 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_errors.4178978588
Directory /workspace/29.lc_ctrl_errors/latest

Test location /workspace/coverage/default/29.lc_ctrl_jtag_access.1246743336
Short name T8
Test name
Test status
Simulation time 2639332499 ps
CPU time 16.49 seconds
Started Jun 06 01:12:44 PM PDT 24
Finished Jun 06 01:13:02 PM PDT 24
Peak memory 209604 kb
Host smart-c1a34ad1-995e-4c9b-b94b-a49673f818e4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246743336 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_jtag_access.1246743336
Directory /workspace/29.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/29.lc_ctrl_prog_failure.1534864196
Short name T828
Test name
Test status
Simulation time 1142023992 ps
CPU time 3.08 seconds
Started Jun 06 01:12:36 PM PDT 24
Finished Jun 06 01:12:40 PM PDT 24
Peak memory 218000 kb
Host smart-afd595d4-1c1d-4197-b5f2-9303f1c02a33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534864196 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_prog_failure.1534864196
Directory /workspace/29.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_mubi.2176799436
Short name T578
Test name
Test status
Simulation time 2385370607 ps
CPU time 16.19 seconds
Started Jun 06 01:12:44 PM PDT 24
Finished Jun 06 01:13:02 PM PDT 24
Peak memory 219496 kb
Host smart-79210336-e9e7-4254-a291-aba16a974a3a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176799436 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_mubi.2176799436
Directory /workspace/29.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_mux.4227082511
Short name T432
Test name
Test status
Simulation time 359576859 ps
CPU time 10.51 seconds
Started Jun 06 01:12:45 PM PDT 24
Finished Jun 06 01:12:57 PM PDT 24
Peak memory 217964 kb
Host smart-76f13418-753c-4498-8b59-084d367516e2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227082511 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_mux.
4227082511
Directory /workspace/29.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/29.lc_ctrl_security_escalation.2679145624
Short name T867
Test name
Test status
Simulation time 2584821858 ps
CPU time 9.03 seconds
Started Jun 06 01:12:44 PM PDT 24
Finished Jun 06 01:12:54 PM PDT 24
Peak memory 218188 kb
Host smart-dc6d60c4-53e9-4d90-ac6b-0457fb6dabc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679145624 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_security_escalation.2679145624
Directory /workspace/29.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/29.lc_ctrl_smoke.1258945113
Short name T270
Test name
Test status
Simulation time 49286078 ps
CPU time 3.82 seconds
Started Jun 06 01:12:37 PM PDT 24
Finished Jun 06 01:12:42 PM PDT 24
Peak memory 217776 kb
Host smart-2663d39f-f01a-4d38-91ba-4c767b5709e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258945113 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_smoke.1258945113
Directory /workspace/29.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_failure.1935762086
Short name T664
Test name
Test status
Simulation time 818596490 ps
CPU time 25.1 seconds
Started Jun 06 01:12:35 PM PDT 24
Finished Jun 06 01:13:01 PM PDT 24
Peak memory 251000 kb
Host smart-20485a3a-cd35-4396-bad2-c5725f222065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935762086 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_failure.1935762086
Directory /workspace/29.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_post_trans.3315616184
Short name T577
Test name
Test status
Simulation time 264960932 ps
CPU time 7.28 seconds
Started Jun 06 01:12:36 PM PDT 24
Finished Jun 06 01:12:44 PM PDT 24
Peak memory 246792 kb
Host smart-13bc05b6-9d95-4973-9b79-56b72c909d94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315616184 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_post_trans.3315616184
Directory /workspace/29.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/29.lc_ctrl_stress_all.1709524626
Short name T523
Test name
Test status
Simulation time 6422525515 ps
CPU time 124.67 seconds
Started Jun 06 01:12:48 PM PDT 24
Finished Jun 06 01:14:54 PM PDT 24
Peak memory 270692 kb
Host smart-422cfd8d-cfd9-463c-af5e-a7e1f1fb3a77
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709524626 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.lc_ctrl_stress_all.1709524626
Directory /workspace/29.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.lc_ctrl_volatile_unlock_smoke.1913172592
Short name T40
Test name
Test status
Simulation time 42062335 ps
CPU time 0.92 seconds
Started Jun 06 01:12:34 PM PDT 24
Finished Jun 06 01:12:36 PM PDT 24
Peak memory 208568 kb
Host smart-ee247d5c-66ba-45a6-8f8f-9d8479ce4e77
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913172592 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_c
trl_volatile_unlock_smoke.1913172592
Directory /workspace/29.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_alert_test.2868435226
Short name T396
Test name
Test status
Simulation time 29224609 ps
CPU time 1.09 seconds
Started Jun 06 01:09:54 PM PDT 24
Finished Jun 06 01:09:56 PM PDT 24
Peak memory 208680 kb
Host smart-1ab1c8db-d28b-4166-86ba-f1023fbf496f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868435226 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_alert_test.2868435226
Directory /workspace/3.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.lc_ctrl_claim_transition_if.2076637896
Short name T228
Test name
Test status
Simulation time 20916068 ps
CPU time 0.93 seconds
Started Jun 06 01:09:54 PM PDT 24
Finished Jun 06 01:09:56 PM PDT 24
Peak memory 208728 kb
Host smart-4a6fafa4-5693-45fb-95cd-7273cda6c2a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076637896 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_claim_transition_if.2076637896
Directory /workspace/3.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/3.lc_ctrl_errors.1139684605
Short name T288
Test name
Test status
Simulation time 288991560 ps
CPU time 9.94 seconds
Started Jun 06 01:09:55 PM PDT 24
Finished Jun 06 01:10:06 PM PDT 24
Peak memory 217944 kb
Host smart-96b8748b-f329-41af-ae1e-19aa18009317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139684605 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_errors.1139684605
Directory /workspace/3.lc_ctrl_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_access.532555765
Short name T868
Test name
Test status
Simulation time 2528987431 ps
CPU time 7 seconds
Started Jun 06 01:09:54 PM PDT 24
Finished Jun 06 01:10:02 PM PDT 24
Peak memory 217632 kb
Host smart-6f77fcea-e9e0-47d6-8588-3e4af3b91c46
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532555765 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_access.532555765
Directory /workspace/3.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_errors.2892912083
Short name T42
Test name
Test status
Simulation time 2369355535 ps
CPU time 36.47 seconds
Started Jun 06 01:09:55 PM PDT 24
Finished Jun 06 01:10:32 PM PDT 24
Peak memory 218916 kb
Host smart-d7a5a0e5-ce15-4a69-a227-58bd57698829
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892912083 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_er
rors.2892912083
Directory /workspace/3.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_priority.482174226
Short name T472
Test name
Test status
Simulation time 768846513 ps
CPU time 13.33 seconds
Started Jun 06 01:09:55 PM PDT 24
Finished Jun 06 01:10:10 PM PDT 24
Peak memory 217152 kb
Host smart-eff0f2e9-c2fc-4f93-8783-bea59cd8ee73
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482174226 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_priority.482174226
Directory /workspace/3.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_prog_failure.224420152
Short name T502
Test name
Test status
Simulation time 130913700 ps
CPU time 2.33 seconds
Started Jun 06 01:09:54 PM PDT 24
Finished Jun 06 01:09:58 PM PDT 24
Peak memory 217972 kb
Host smart-1439ed40-89c7-4a9b-8d0b-6664a084e912
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224420152 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_
prog_failure.224420152
Directory /workspace/3.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_regwen_during_op.2646135584
Short name T268
Test name
Test status
Simulation time 1157319640 ps
CPU time 35.03 seconds
Started Jun 06 01:09:54 PM PDT 24
Finished Jun 06 01:10:30 PM PDT 24
Peak memory 217676 kb
Host smart-0e2c3677-ad11-4bd9-8add-e6bac91dd168
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646135584 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_regwen_during_op.2646135584
Directory /workspace/3.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_smoke.333592178
Short name T725
Test name
Test status
Simulation time 456665960 ps
CPU time 4.39 seconds
Started Jun 06 01:09:57 PM PDT 24
Finished Jun 06 01:10:02 PM PDT 24
Peak memory 217564 kb
Host smart-532f97f0-c56b-4e67-8b2d-eefa9b0e7c04
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333592178 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_smoke.333592178
Directory /workspace/3.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_failure.1272501055
Short name T515
Test name
Test status
Simulation time 1660044915 ps
CPU time 36.27 seconds
Started Jun 06 01:09:54 PM PDT 24
Finished Jun 06 01:10:32 PM PDT 24
Peak memory 276272 kb
Host smart-2a5b23b4-2c4c-4226-9287-d5623c8f6124
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272501055 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jta
g_state_failure.1272501055
Directory /workspace/3.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_post_trans.3606984655
Short name T389
Test name
Test status
Simulation time 367779633 ps
CPU time 11.78 seconds
Started Jun 06 01:09:54 PM PDT 24
Finished Jun 06 01:10:07 PM PDT 24
Peak memory 250136 kb
Host smart-e4801871-ea3b-4367-b9b4-998a254e72b8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606984655 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_state_post_trans.3606984655
Directory /workspace/3.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_prog_failure.434094065
Short name T506
Test name
Test status
Simulation time 44629773 ps
CPU time 1.9 seconds
Started Jun 06 01:09:55 PM PDT 24
Finished Jun 06 01:09:58 PM PDT 24
Peak memory 218044 kb
Host smart-061b8cef-437a-4182-891c-b1d2b553d971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434094065 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_prog_failure.434094065
Directory /workspace/3.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_regwen_during_op.862060327
Short name T646
Test name
Test status
Simulation time 169688379 ps
CPU time 6.02 seconds
Started Jun 06 01:09:56 PM PDT 24
Finished Jun 06 01:10:03 PM PDT 24
Peak memory 218076 kb
Host smart-291d0724-6aa2-4b6c-8253-d04cb9cdcf8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862060327 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_regwen_during_op.862060327
Directory /workspace/3.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_mubi.1860739429
Short name T696
Test name
Test status
Simulation time 1306764152 ps
CPU time 10.98 seconds
Started Jun 06 01:09:56 PM PDT 24
Finished Jun 06 01:10:08 PM PDT 24
Peak memory 226120 kb
Host smart-99eb92e5-18ac-43dc-9f05-74bb51d00741
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860739429 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_mubi.1860739429
Directory /workspace/3.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_digest.3841639139
Short name T340
Test name
Test status
Simulation time 3417253142 ps
CPU time 9.52 seconds
Started Jun 06 01:09:55 PM PDT 24
Finished Jun 06 01:10:06 PM PDT 24
Peak memory 217976 kb
Host smart-f9df4c2d-a27d-4133-b3ae-9c3711a9227e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841639139 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_di
gest.3841639139
Directory /workspace/3.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_mux.1041922697
Short name T802
Test name
Test status
Simulation time 294986132 ps
CPU time 8.26 seconds
Started Jun 06 01:09:54 PM PDT 24
Finished Jun 06 01:10:03 PM PDT 24
Peak memory 218232 kb
Host smart-8468c122-d5f4-4fc7-b2bb-a26ab048699e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041922697 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_mux.1
041922697
Directory /workspace/3.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/3.lc_ctrl_security_escalation.2721140173
Short name T324
Test name
Test status
Simulation time 406897582 ps
CPU time 11.56 seconds
Started Jun 06 01:09:54 PM PDT 24
Finished Jun 06 01:10:07 PM PDT 24
Peak memory 218036 kb
Host smart-0f3ebeb5-e97c-434a-9be4-33a1082e02ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721140173 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_security_escalation.2721140173
Directory /workspace/3.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/3.lc_ctrl_smoke.1162229269
Short name T104
Test name
Test status
Simulation time 81136091 ps
CPU time 2.64 seconds
Started Jun 06 01:09:43 PM PDT 24
Finished Jun 06 01:09:47 PM PDT 24
Peak memory 213836 kb
Host smart-5a75fa9d-884d-4b78-a3f3-7f6de9f87751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162229269 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_smoke.1162229269
Directory /workspace/3.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_failure.1036056878
Short name T673
Test name
Test status
Simulation time 226150456 ps
CPU time 23.98 seconds
Started Jun 06 01:09:59 PM PDT 24
Finished Jun 06 01:10:24 PM PDT 24
Peak memory 250984 kb
Host smart-955bfb7e-026b-4f99-8619-02f47033c404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036056878 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_failure.1036056878
Directory /workspace/3.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_post_trans.692032810
Short name T563
Test name
Test status
Simulation time 65121314 ps
CPU time 10.04 seconds
Started Jun 06 01:09:55 PM PDT 24
Finished Jun 06 01:10:06 PM PDT 24
Peak memory 251008 kb
Host smart-cca32316-96ea-4468-aadd-778acd5a5e4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692032810 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_post_trans.692032810
Directory /workspace/3.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_stress_all.1927673661
Short name T612
Test name
Test status
Simulation time 3279819768 ps
CPU time 82.21 seconds
Started Jun 06 01:10:02 PM PDT 24
Finished Jun 06 01:11:25 PM PDT 24
Peak memory 279768 kb
Host smart-b376f040-b05d-40e8-a14e-c9839a1faca2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927673661 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.lc_ctrl_stress_all.1927673661
Directory /workspace/3.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.lc_ctrl_volatile_unlock_smoke.1565663379
Short name T573
Test name
Test status
Simulation time 13373997 ps
CPU time 0.99 seconds
Started Jun 06 01:09:55 PM PDT 24
Finished Jun 06 01:09:57 PM PDT 24
Peak memory 208592 kb
Host smart-af5c91a2-fe1f-4799-91bb-fc1f56a96bf1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565663379 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ct
rl_volatile_unlock_smoke.1565663379
Directory /workspace/3.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_alert_test.207355773
Short name T841
Test name
Test status
Simulation time 19557238 ps
CPU time 1.12 seconds
Started Jun 06 01:12:49 PM PDT 24
Finished Jun 06 01:12:51 PM PDT 24
Peak memory 208712 kb
Host smart-94c52ec2-3fe9-4666-87c7-7c78cca23415
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207355773 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_alert_test.207355773
Directory /workspace/30.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.lc_ctrl_errors.1443795159
Short name T615
Test name
Test status
Simulation time 582773484 ps
CPU time 11.4 seconds
Started Jun 06 01:12:46 PM PDT 24
Finished Jun 06 01:12:59 PM PDT 24
Peak memory 218020 kb
Host smart-5c43be7d-3413-4c49-b292-d9cfdb864b5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443795159 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_errors.1443795159
Directory /workspace/30.lc_ctrl_errors/latest

Test location /workspace/coverage/default/30.lc_ctrl_jtag_access.2672242860
Short name T28
Test name
Test status
Simulation time 2052385303 ps
CPU time 8.76 seconds
Started Jun 06 01:12:44 PM PDT 24
Finished Jun 06 01:12:54 PM PDT 24
Peak memory 209464 kb
Host smart-10070e77-5c1f-43fd-8f3e-0e799f9487f0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672242860 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_jtag_access.2672242860
Directory /workspace/30.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/30.lc_ctrl_prog_failure.3879209862
Short name T503
Test name
Test status
Simulation time 54648740 ps
CPU time 3.13 seconds
Started Jun 06 01:12:48 PM PDT 24
Finished Jun 06 01:12:52 PM PDT 24
Peak memory 218028 kb
Host smart-4bdcf530-3b41-40cc-9aa8-58c199858464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879209862 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_prog_failure.3879209862
Directory /workspace/30.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_mubi.204642768
Short name T844
Test name
Test status
Simulation time 1524003414 ps
CPU time 17.97 seconds
Started Jun 06 01:12:43 PM PDT 24
Finished Jun 06 01:13:01 PM PDT 24
Peak memory 218992 kb
Host smart-d08b5f08-da60-448a-8c5b-2d63a70770de
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204642768 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_mubi.204642768
Directory /workspace/30.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_digest.2182820297
Short name T457
Test name
Test status
Simulation time 402243849 ps
CPU time 11.5 seconds
Started Jun 06 01:12:44 PM PDT 24
Finished Jun 06 01:12:57 PM PDT 24
Peak memory 226012 kb
Host smart-4c429703-26d6-4167-9805-8080c5f7536a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182820297 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_d
igest.2182820297
Directory /workspace/30.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_mux.3349168054
Short name T514
Test name
Test status
Simulation time 1416719965 ps
CPU time 23.52 seconds
Started Jun 06 01:12:49 PM PDT 24
Finished Jun 06 01:13:14 PM PDT 24
Peak memory 217936 kb
Host smart-284bccce-8d4b-40c4-96e6-a984dfa16ba4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349168054 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_mux.
3349168054
Directory /workspace/30.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/30.lc_ctrl_smoke.3293905662
Short name T276
Test name
Test status
Simulation time 430192296 ps
CPU time 6.68 seconds
Started Jun 06 01:12:45 PM PDT 24
Finished Jun 06 01:12:53 PM PDT 24
Peak memory 217708 kb
Host smart-5d27b498-8ff7-410e-9009-46ea42d52ab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293905662 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_smoke.3293905662
Directory /workspace/30.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_failure.2761159059
Short name T662
Test name
Test status
Simulation time 733677484 ps
CPU time 26.7 seconds
Started Jun 06 01:12:48 PM PDT 24
Finished Jun 06 01:13:15 PM PDT 24
Peak memory 251000 kb
Host smart-8e3347c1-11e6-438e-b23e-2cac8c805eb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761159059 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_failure.2761159059
Directory /workspace/30.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_post_trans.953137269
Short name T166
Test name
Test status
Simulation time 464598161 ps
CPU time 5.92 seconds
Started Jun 06 01:12:44 PM PDT 24
Finished Jun 06 01:12:51 PM PDT 24
Peak memory 250420 kb
Host smart-150c2eec-752e-473f-bf4e-1c2aaee368c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=953137269 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_post_trans.953137269
Directory /workspace/30.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all.3791050549
Short name T771
Test name
Test status
Simulation time 14628975315 ps
CPU time 95.56 seconds
Started Jun 06 01:12:44 PM PDT 24
Finished Jun 06 01:14:21 PM PDT 24
Peak memory 248816 kb
Host smart-7d467373-c15a-48b7-9743-edc0d596e535
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791050549 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.lc_ctrl_stress_all.3791050549
Directory /workspace/30.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.lc_ctrl_volatile_unlock_smoke.1471929828
Short name T773
Test name
Test status
Simulation time 25343317 ps
CPU time 1.08 seconds
Started Jun 06 01:12:47 PM PDT 24
Finished Jun 06 01:12:49 PM PDT 24
Peak memory 211524 kb
Host smart-33964585-b242-40b4-9ce3-fd87285b6322
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471929828 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_c
trl_volatile_unlock_smoke.1471929828
Directory /workspace/30.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_alert_test.3091265928
Short name T196
Test name
Test status
Simulation time 135542201 ps
CPU time 1.43 seconds
Started Jun 06 01:12:55 PM PDT 24
Finished Jun 06 01:12:58 PM PDT 24
Peak memory 208636 kb
Host smart-e2b590f1-3141-4f96-bb80-750b927ad284
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091265928 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_alert_test.3091265928
Directory /workspace/31.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.lc_ctrl_errors.3770702892
Short name T723
Test name
Test status
Simulation time 363486408 ps
CPU time 9.38 seconds
Started Jun 06 01:12:53 PM PDT 24
Finished Jun 06 01:13:03 PM PDT 24
Peak memory 218064 kb
Host smart-cbd8c269-1a90-48e7-8600-4d535975d305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770702892 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_errors.3770702892
Directory /workspace/31.lc_ctrl_errors/latest

Test location /workspace/coverage/default/31.lc_ctrl_jtag_access.2041876887
Short name T557
Test name
Test status
Simulation time 156228363 ps
CPU time 4.5 seconds
Started Jun 06 01:12:55 PM PDT 24
Finished Jun 06 01:13:01 PM PDT 24
Peak memory 209564 kb
Host smart-1727078a-ca83-47b0-8a6c-79d5e007b0e1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041876887 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_jtag_access.2041876887
Directory /workspace/31.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_mubi.1537468273
Short name T505
Test name
Test status
Simulation time 522952934 ps
CPU time 10.72 seconds
Started Jun 06 01:12:52 PM PDT 24
Finished Jun 06 01:13:03 PM PDT 24
Peak memory 218916 kb
Host smart-2f71a7ef-b0f9-419e-8e10-13b93d2008c5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537468273 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_mubi.1537468273
Directory /workspace/31.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_digest.264847558
Short name T299
Test name
Test status
Simulation time 281490595 ps
CPU time 7.16 seconds
Started Jun 06 01:12:52 PM PDT 24
Finished Jun 06 01:13:00 PM PDT 24
Peak memory 217932 kb
Host smart-b4a1edd6-da00-41a4-b963-af63922a5d00
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264847558 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_di
gest.264847558
Directory /workspace/31.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_mux.1002583893
Short name T172
Test name
Test status
Simulation time 273019131 ps
CPU time 10.48 seconds
Started Jun 06 01:12:55 PM PDT 24
Finished Jun 06 01:13:07 PM PDT 24
Peak memory 218024 kb
Host smart-b0c15484-9660-40e1-9868-5c33aac11989
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002583893 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_mux.
1002583893
Directory /workspace/31.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/31.lc_ctrl_security_escalation.1814887468
Short name T37
Test name
Test status
Simulation time 1154520510 ps
CPU time 12.06 seconds
Started Jun 06 01:12:54 PM PDT 24
Finished Jun 06 01:13:07 PM PDT 24
Peak memory 218108 kb
Host smart-7f63f259-738b-4c8d-a622-a434fd16d2ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814887468 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_security_escalation.1814887468
Directory /workspace/31.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/31.lc_ctrl_smoke.2993566401
Short name T579
Test name
Test status
Simulation time 181413637 ps
CPU time 4.4 seconds
Started Jun 06 01:12:44 PM PDT 24
Finished Jun 06 01:12:49 PM PDT 24
Peak memory 217680 kb
Host smart-2811b7c5-651f-4c7e-b868-595f71ab6801
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993566401 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_smoke.2993566401
Directory /workspace/31.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_failure.3746502442
Short name T552
Test name
Test status
Simulation time 243341025 ps
CPU time 25.18 seconds
Started Jun 06 01:12:47 PM PDT 24
Finished Jun 06 01:13:13 PM PDT 24
Peak memory 250996 kb
Host smart-bf73af9b-a5e6-4e54-86d5-523e241513fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746502442 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_failure.3746502442
Directory /workspace/31.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_post_trans.965296366
Short name T686
Test name
Test status
Simulation time 92900952 ps
CPU time 7.66 seconds
Started Jun 06 01:12:45 PM PDT 24
Finished Jun 06 01:12:54 PM PDT 24
Peak memory 250932 kb
Host smart-0409acc2-032f-44e2-8df2-7b8342dd8913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965296366 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_post_trans.965296366
Directory /workspace/31.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/31.lc_ctrl_stress_all.1782405142
Short name T448
Test name
Test status
Simulation time 2502152732 ps
CPU time 15.91 seconds
Started Jun 06 01:12:56 PM PDT 24
Finished Jun 06 01:13:14 PM PDT 24
Peak memory 250728 kb
Host smart-ad102696-5c77-4c48-a535-ff91b785d98f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782405142 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.lc_ctrl_stress_all.1782405142
Directory /workspace/31.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.lc_ctrl_volatile_unlock_smoke.2522979754
Short name T520
Test name
Test status
Simulation time 24183471 ps
CPU time 1.01 seconds
Started Jun 06 01:12:46 PM PDT 24
Finished Jun 06 01:12:48 PM PDT 24
Peak memory 208548 kb
Host smart-a8f87dbe-fd7f-4545-962f-766e83147043
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522979754 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_c
trl_volatile_unlock_smoke.2522979754
Directory /workspace/31.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_alert_test.1472657890
Short name T582
Test name
Test status
Simulation time 14086193 ps
CPU time 0.85 seconds
Started Jun 06 01:12:54 PM PDT 24
Finished Jun 06 01:12:56 PM PDT 24
Peak memory 208684 kb
Host smart-dc65d827-6384-422b-ad62-180da5378911
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472657890 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_alert_test.1472657890
Directory /workspace/32.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.lc_ctrl_errors.1945473078
Short name T804
Test name
Test status
Simulation time 1136159747 ps
CPU time 13.37 seconds
Started Jun 06 01:12:55 PM PDT 24
Finished Jun 06 01:13:10 PM PDT 24
Peak memory 218020 kb
Host smart-dde8fe74-dafa-48e0-8eb1-974485e62e9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945473078 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_errors.1945473078
Directory /workspace/32.lc_ctrl_errors/latest

Test location /workspace/coverage/default/32.lc_ctrl_jtag_access.221896199
Short name T665
Test name
Test status
Simulation time 2599883311 ps
CPU time 8.03 seconds
Started Jun 06 01:12:57 PM PDT 24
Finished Jun 06 01:13:07 PM PDT 24
Peak memory 217360 kb
Host smart-e3c3be6d-f472-4c04-9ca3-0be495adefdc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221896199 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_jtag_access.221896199
Directory /workspace/32.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/32.lc_ctrl_prog_failure.461398681
Short name T480
Test name
Test status
Simulation time 35249023 ps
CPU time 2.28 seconds
Started Jun 06 01:12:52 PM PDT 24
Finished Jun 06 01:12:55 PM PDT 24
Peak memory 218040 kb
Host smart-559f87ab-f23b-4471-a4a6-b8a788d3610d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461398681 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_prog_failure.461398681
Directory /workspace/32.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_mubi.823393999
Short name T597
Test name
Test status
Simulation time 412392923 ps
CPU time 17.15 seconds
Started Jun 06 01:12:52 PM PDT 24
Finished Jun 06 01:13:10 PM PDT 24
Peak memory 226016 kb
Host smart-2d16f784-d778-4af2-938d-777b604489cc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823393999 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_mubi.823393999
Directory /workspace/32.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_digest.165659364
Short name T827
Test name
Test status
Simulation time 516455023 ps
CPU time 10.82 seconds
Started Jun 06 01:12:56 PM PDT 24
Finished Jun 06 01:13:09 PM PDT 24
Peak memory 226052 kb
Host smart-8770b6ce-8f64-4b2a-a0f1-cf716b2efc0c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165659364 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_di
gest.165659364
Directory /workspace/32.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_mux.1640053881
Short name T614
Test name
Test status
Simulation time 248606787 ps
CPU time 9.84 seconds
Started Jun 06 01:12:54 PM PDT 24
Finished Jun 06 01:13:04 PM PDT 24
Peak memory 217888 kb
Host smart-e9c6fd0e-25db-475d-a7f8-f785acf41bd0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640053881 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_mux.
1640053881
Directory /workspace/32.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/32.lc_ctrl_security_escalation.1945090476
Short name T408
Test name
Test status
Simulation time 1378563632 ps
CPU time 13.67 seconds
Started Jun 06 01:12:53 PM PDT 24
Finished Jun 06 01:13:07 PM PDT 24
Peak memory 218048 kb
Host smart-b4cb0607-d323-424a-aa30-e3f2db93c11f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945090476 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_security_escalation.1945090476
Directory /workspace/32.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/32.lc_ctrl_smoke.3770777304
Short name T634
Test name
Test status
Simulation time 247370755 ps
CPU time 3.71 seconds
Started Jun 06 01:12:55 PM PDT 24
Finished Jun 06 01:13:00 PM PDT 24
Peak memory 217732 kb
Host smart-1e08770d-36ed-4c32-9634-e32df2771ffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770777304 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_smoke.3770777304
Directory /workspace/32.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_failure.3446414190
Short name T246
Test name
Test status
Simulation time 279412021 ps
CPU time 27.53 seconds
Started Jun 06 01:12:54 PM PDT 24
Finished Jun 06 01:13:22 PM PDT 24
Peak memory 251204 kb
Host smart-042011ea-dab7-4af9-8c4f-601542ed560b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446414190 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_failure.3446414190
Directory /workspace/32.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_post_trans.647476429
Short name T812
Test name
Test status
Simulation time 70250451 ps
CPU time 7.49 seconds
Started Jun 06 01:12:53 PM PDT 24
Finished Jun 06 01:13:02 PM PDT 24
Peak memory 250968 kb
Host smart-59a9c410-9271-4799-b5d4-8a4d4cd639ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647476429 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_post_trans.647476429
Directory /workspace/32.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all.845697972
Short name T70
Test name
Test status
Simulation time 1118273021 ps
CPU time 19.93 seconds
Started Jun 06 01:12:57 PM PDT 24
Finished Jun 06 01:13:18 PM PDT 24
Peak memory 250460 kb
Host smart-7bfd078c-22e9-4f17-b5bb-7ee8b7f2d8be
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845697972 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.lc_ctrl_stress_all.845697972
Directory /workspace/32.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.lc_ctrl_volatile_unlock_smoke.2671329007
Short name T672
Test name
Test status
Simulation time 41123045 ps
CPU time 0.9 seconds
Started Jun 06 01:12:54 PM PDT 24
Finished Jun 06 01:12:56 PM PDT 24
Peak memory 208552 kb
Host smart-c426b66b-3155-4332-9252-074341ee5be2
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671329007 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_c
trl_volatile_unlock_smoke.2671329007
Directory /workspace/32.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_alert_test.371018175
Short name T334
Test name
Test status
Simulation time 68655846 ps
CPU time 0.93 seconds
Started Jun 06 01:12:57 PM PDT 24
Finished Jun 06 01:13:00 PM PDT 24
Peak memory 208584 kb
Host smart-f79d0590-f643-4b49-bc7b-4f5ce00b2d23
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371018175 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_alert_test.371018175
Directory /workspace/33.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.lc_ctrl_errors.2419089569
Short name T374
Test name
Test status
Simulation time 1228262848 ps
CPU time 14.08 seconds
Started Jun 06 01:12:53 PM PDT 24
Finished Jun 06 01:13:08 PM PDT 24
Peak memory 218060 kb
Host smart-b7981957-b7e7-4523-95fa-38ee66d0e60e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419089569 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_errors.2419089569
Directory /workspace/33.lc_ctrl_errors/latest

Test location /workspace/coverage/default/33.lc_ctrl_jtag_access.35827575
Short name T840
Test name
Test status
Simulation time 150791042 ps
CPU time 2.41 seconds
Started Jun 06 01:12:55 PM PDT 24
Finished Jun 06 01:12:59 PM PDT 24
Peak memory 209548 kb
Host smart-1dc99085-8d46-4f42-b8c5-efe209951905
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35827575 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_jtag_access.35827575
Directory /workspace/33.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/33.lc_ctrl_prog_failure.4081946506
Short name T409
Test name
Test status
Simulation time 215317018 ps
CPU time 3.03 seconds
Started Jun 06 01:12:51 PM PDT 24
Finished Jun 06 01:12:55 PM PDT 24
Peak memory 218024 kb
Host smart-288b3c13-bc8c-4dfc-8b76-f4b0854512e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081946506 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_prog_failure.4081946506
Directory /workspace/33.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_mubi.2624081442
Short name T513
Test name
Test status
Simulation time 434532558 ps
CPU time 16.02 seconds
Started Jun 06 01:12:53 PM PDT 24
Finished Jun 06 01:13:09 PM PDT 24
Peak memory 218884 kb
Host smart-985ce22a-9b45-445a-861d-51387b07504e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624081442 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_mubi.2624081442
Directory /workspace/33.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_digest.354528625
Short name T705
Test name
Test status
Simulation time 1136302885 ps
CPU time 9.7 seconds
Started Jun 06 01:12:56 PM PDT 24
Finished Jun 06 01:13:07 PM PDT 24
Peak memory 217884 kb
Host smart-ec82754f-7b8e-428f-a609-5dd4a130d76a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354528625 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_di
gest.354528625
Directory /workspace/33.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_mux.2240576904
Short name T825
Test name
Test status
Simulation time 809320384 ps
CPU time 6.13 seconds
Started Jun 06 01:12:54 PM PDT 24
Finished Jun 06 01:13:01 PM PDT 24
Peak memory 217988 kb
Host smart-caffdbcb-db7e-4d39-92cd-3f8bc82f973c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240576904 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_mux.
2240576904
Directory /workspace/33.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/33.lc_ctrl_security_escalation.1999303120
Short name T704
Test name
Test status
Simulation time 1809910493 ps
CPU time 10.71 seconds
Started Jun 06 01:12:53 PM PDT 24
Finished Jun 06 01:13:05 PM PDT 24
Peak memory 218048 kb
Host smart-0a1391a5-5bec-457c-ac5a-440d9204bd2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999303120 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_security_escalation.1999303120
Directory /workspace/33.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/33.lc_ctrl_smoke.1000816181
Short name T436
Test name
Test status
Simulation time 110272483 ps
CPU time 1.83 seconds
Started Jun 06 01:12:54 PM PDT 24
Finished Jun 06 01:12:57 PM PDT 24
Peak memory 213648 kb
Host smart-b670b8df-4912-43e9-881f-4c6a525ebdfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000816181 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_smoke.1000816181
Directory /workspace/33.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_failure.3517845344
Short name T470
Test name
Test status
Simulation time 499360537 ps
CPU time 26.4 seconds
Started Jun 06 01:12:55 PM PDT 24
Finished Jun 06 01:13:23 PM PDT 24
Peak memory 251004 kb
Host smart-bf640783-4b38-4db7-b740-f7312f8b74e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517845344 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_failure.3517845344
Directory /workspace/33.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_post_trans.246850374
Short name T255
Test name
Test status
Simulation time 81621498 ps
CPU time 3.17 seconds
Started Jun 06 01:12:53 PM PDT 24
Finished Jun 06 01:12:57 PM PDT 24
Peak memory 222444 kb
Host smart-1962811c-1875-40e1-8795-adc12b70a9bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246850374 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_post_trans.246850374
Directory /workspace/33.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all.456243290
Short name T835
Test name
Test status
Simulation time 14487064292 ps
CPU time 108.21 seconds
Started Jun 06 01:12:53 PM PDT 24
Finished Jun 06 01:14:42 PM PDT 24
Peak memory 250884 kb
Host smart-8c488984-8748-48be-ade8-4808a1a75798
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456243290 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.lc_ctrl_stress_all.456243290
Directory /workspace/33.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.lc_ctrl_volatile_unlock_smoke.2215737879
Short name T47
Test name
Test status
Simulation time 21342263 ps
CPU time 0.92 seconds
Started Jun 06 01:12:52 PM PDT 24
Finished Jun 06 01:12:54 PM PDT 24
Peak memory 208508 kb
Host smart-ef0babc4-e078-46f8-951a-b61a08b176da
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215737879 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_c
trl_volatile_unlock_smoke.2215737879
Directory /workspace/33.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_alert_test.257058525
Short name T257
Test name
Test status
Simulation time 88026982 ps
CPU time 0.9 seconds
Started Jun 06 01:13:02 PM PDT 24
Finished Jun 06 01:13:04 PM PDT 24
Peak memory 208708 kb
Host smart-466bf503-2e4e-49a0-ab2c-9ab6e109aed5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257058525 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_alert_test.257058525
Directory /workspace/34.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.lc_ctrl_errors.2656564670
Short name T716
Test name
Test status
Simulation time 206705274 ps
CPU time 11.01 seconds
Started Jun 06 01:13:12 PM PDT 24
Finished Jun 06 01:13:24 PM PDT 24
Peak memory 217908 kb
Host smart-ec38a2b1-4186-4a2f-8461-1dc8588fc6a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656564670 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_errors.2656564670
Directory /workspace/34.lc_ctrl_errors/latest

Test location /workspace/coverage/default/34.lc_ctrl_jtag_access.4071163892
Short name T474
Test name
Test status
Simulation time 257204960 ps
CPU time 3.44 seconds
Started Jun 06 01:13:02 PM PDT 24
Finished Jun 06 01:13:07 PM PDT 24
Peak memory 209496 kb
Host smart-8ec9f58a-abc8-42dc-ba78-f22db5d1cf9e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071163892 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_jtag_access.4071163892
Directory /workspace/34.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/34.lc_ctrl_prog_failure.3874299821
Short name T262
Test name
Test status
Simulation time 105253110 ps
CPU time 4.61 seconds
Started Jun 06 01:13:01 PM PDT 24
Finished Jun 06 01:13:07 PM PDT 24
Peak memory 217932 kb
Host smart-19ccd064-808d-4cea-8f93-04aba0173818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874299821 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_prog_failure.3874299821
Directory /workspace/34.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_mubi.893341199
Short name T105
Test name
Test status
Simulation time 615588969 ps
CPU time 23.71 seconds
Started Jun 06 01:13:00 PM PDT 24
Finished Jun 06 01:13:25 PM PDT 24
Peak memory 226052 kb
Host smart-1d5dd305-28eb-4c92-8235-11d8c53ff686
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893341199 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_mubi.893341199
Directory /workspace/34.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_digest.473627692
Short name T367
Test name
Test status
Simulation time 539020720 ps
CPU time 10.75 seconds
Started Jun 06 01:13:04 PM PDT 24
Finished Jun 06 01:13:16 PM PDT 24
Peak memory 216600 kb
Host smart-3d8eff12-c003-41f2-80f5-ec56d218dc0a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473627692 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_di
gest.473627692
Directory /workspace/34.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_mux.606424034
Short name T366
Test name
Test status
Simulation time 679053046 ps
CPU time 11.82 seconds
Started Jun 06 01:13:02 PM PDT 24
Finished Jun 06 01:13:15 PM PDT 24
Peak memory 217988 kb
Host smart-1c1adc07-18fd-4261-8008-f0c931fcb401
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606424034 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_mux.606424034
Directory /workspace/34.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/34.lc_ctrl_security_escalation.2020839673
Short name T644
Test name
Test status
Simulation time 281210689 ps
CPU time 9.94 seconds
Started Jun 06 01:13:01 PM PDT 24
Finished Jun 06 01:13:13 PM PDT 24
Peak memory 218072 kb
Host smart-370f0221-7454-497b-aa8c-a09dcc6b8955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020839673 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_security_escalation.2020839673
Directory /workspace/34.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/34.lc_ctrl_smoke.2569490604
Short name T772
Test name
Test status
Simulation time 98743153 ps
CPU time 4.27 seconds
Started Jun 06 01:12:58 PM PDT 24
Finished Jun 06 01:13:03 PM PDT 24
Peak memory 217744 kb
Host smart-4303d8cb-c48b-4004-9fad-df6c2df804ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569490604 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_smoke.2569490604
Directory /workspace/34.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_failure.2122310249
Short name T16
Test name
Test status
Simulation time 321614539 ps
CPU time 25.18 seconds
Started Jun 06 01:12:59 PM PDT 24
Finished Jun 06 01:13:26 PM PDT 24
Peak memory 250916 kb
Host smart-4315d314-839f-4eee-a8fe-e701748222e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122310249 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_failure.2122310249
Directory /workspace/34.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_post_trans.2081759655
Short name T714
Test name
Test status
Simulation time 57804948 ps
CPU time 6.53 seconds
Started Jun 06 01:13:04 PM PDT 24
Finished Jun 06 01:13:12 PM PDT 24
Peak memory 245868 kb
Host smart-c01fdfb0-d4c6-41cd-afd9-a4d5fc672a59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081759655 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_post_trans.2081759655
Directory /workspace/34.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all.1511594511
Short name T76
Test name
Test status
Simulation time 16931350411 ps
CPU time 190.82 seconds
Started Jun 06 01:13:02 PM PDT 24
Finished Jun 06 01:16:14 PM PDT 24
Peak memory 283788 kb
Host smart-659ecb43-3474-4953-be4c-b9ff2c158b53
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511594511 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.lc_ctrl_stress_all.1511594511
Directory /workspace/34.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.lc_ctrl_volatile_unlock_smoke.1148732069
Short name T240
Test name
Test status
Simulation time 12873724 ps
CPU time 0.95 seconds
Started Jun 06 01:12:57 PM PDT 24
Finished Jun 06 01:12:59 PM PDT 24
Peak memory 208564 kb
Host smart-52fdcf3e-5dcb-41c1-89c8-07e28f93941b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148732069 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_c
trl_volatile_unlock_smoke.1148732069
Directory /workspace/34.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_alert_test.2878934122
Short name T242
Test name
Test status
Simulation time 52327624 ps
CPU time 1.07 seconds
Started Jun 06 01:13:01 PM PDT 24
Finished Jun 06 01:13:03 PM PDT 24
Peak memory 209492 kb
Host smart-e0b36349-4665-49af-a527-4c3b08449676
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878934122 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_alert_test.2878934122
Directory /workspace/35.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.lc_ctrl_errors.1400679497
Short name T386
Test name
Test status
Simulation time 415381365 ps
CPU time 13.07 seconds
Started Jun 06 01:13:03 PM PDT 24
Finished Jun 06 01:13:17 PM PDT 24
Peak memory 218100 kb
Host smart-9b8d7676-3615-4c1b-9faa-0e024e9e2801
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1400679497 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_errors.1400679497
Directory /workspace/35.lc_ctrl_errors/latest

Test location /workspace/coverage/default/35.lc_ctrl_jtag_access.1686316620
Short name T533
Test name
Test status
Simulation time 107477722 ps
CPU time 3.41 seconds
Started Jun 06 01:13:00 PM PDT 24
Finished Jun 06 01:13:05 PM PDT 24
Peak memory 216872 kb
Host smart-f94f4b7e-b6a1-4db3-8884-baaa7f836758
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686316620 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_jtag_access.1686316620
Directory /workspace/35.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/35.lc_ctrl_prog_failure.4125263331
Short name T322
Test name
Test status
Simulation time 62743827 ps
CPU time 1.5 seconds
Started Jun 06 01:13:02 PM PDT 24
Finished Jun 06 01:13:04 PM PDT 24
Peak memory 218064 kb
Host smart-9e5927cc-b3b7-4360-a802-317f9e387d6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125263331 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_prog_failure.4125263331
Directory /workspace/35.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_mubi.1210726432
Short name T794
Test name
Test status
Simulation time 1207234701 ps
CPU time 8.59 seconds
Started Jun 06 01:13:01 PM PDT 24
Finished Jun 06 01:13:11 PM PDT 24
Peak memory 226060 kb
Host smart-d65f2af9-1360-4136-90e6-ad68d34b22e6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210726432 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_mubi.1210726432
Directory /workspace/35.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_digest.2923173320
Short name T192
Test name
Test status
Simulation time 1988205033 ps
CPU time 10.29 seconds
Started Jun 06 01:13:01 PM PDT 24
Finished Jun 06 01:13:13 PM PDT 24
Peak memory 217808 kb
Host smart-14d9c064-97b9-4fa3-bcff-2fcffcd37b19
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923173320 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_d
igest.2923173320
Directory /workspace/35.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_mux.4056318207
Short name T755
Test name
Test status
Simulation time 1337148508 ps
CPU time 21.22 seconds
Started Jun 06 01:13:02 PM PDT 24
Finished Jun 06 01:13:25 PM PDT 24
Peak memory 218056 kb
Host smart-8c63e522-a5a3-436c-9f70-320bfd92da35
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056318207 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_mux.
4056318207
Directory /workspace/35.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/35.lc_ctrl_security_escalation.1163424579
Short name T58
Test name
Test status
Simulation time 662270011 ps
CPU time 12.66 seconds
Started Jun 06 01:13:00 PM PDT 24
Finished Jun 06 01:13:14 PM PDT 24
Peak memory 218156 kb
Host smart-ec87504d-763e-4bcc-9a82-26bbd3bba9c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163424579 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_security_escalation.1163424579
Directory /workspace/35.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/35.lc_ctrl_smoke.1158826477
Short name T417
Test name
Test status
Simulation time 120272492 ps
CPU time 2.48 seconds
Started Jun 06 01:13:01 PM PDT 24
Finished Jun 06 01:13:05 PM PDT 24
Peak memory 217648 kb
Host smart-ac331de1-71dc-4a98-9d50-c0963fa8a393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158826477 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_smoke.1158826477
Directory /workspace/35.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_failure.4185593086
Short name T430
Test name
Test status
Simulation time 602942235 ps
CPU time 33.81 seconds
Started Jun 06 01:13:02 PM PDT 24
Finished Jun 06 01:13:37 PM PDT 24
Peak memory 250980 kb
Host smart-ee20ba54-6a55-45be-9daf-c2ada1498d5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185593086 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_failure.4185593086
Directory /workspace/35.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_post_trans.1711064990
Short name T341
Test name
Test status
Simulation time 104772651 ps
CPU time 11.77 seconds
Started Jun 06 01:13:02 PM PDT 24
Finished Jun 06 01:13:15 PM PDT 24
Peak memory 250992 kb
Host smart-e1d9540d-bdc1-4895-98f4-6be3ce971400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711064990 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_post_trans.1711064990
Directory /workspace/35.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all.3987075180
Short name T247
Test name
Test status
Simulation time 77008785406 ps
CPU time 136.86 seconds
Started Jun 06 01:13:03 PM PDT 24
Finished Jun 06 01:15:21 PM PDT 24
Peak memory 283800 kb
Host smart-4dc2cf34-7639-499c-87d8-9d89af83f46b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987075180 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.lc_ctrl_stress_all.3987075180
Directory /workspace/35.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.lc_ctrl_volatile_unlock_smoke.1902801203
Short name T736
Test name
Test status
Simulation time 33265643 ps
CPU time 0.77 seconds
Started Jun 06 01:13:00 PM PDT 24
Finished Jun 06 01:13:01 PM PDT 24
Peak memory 208364 kb
Host smart-60cc9229-9e65-4904-ac32-83df1a5e4f90
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902801203 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_c
trl_volatile_unlock_smoke.1902801203
Directory /workspace/35.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_alert_test.2172660488
Short name T681
Test name
Test status
Simulation time 40068219 ps
CPU time 1.03 seconds
Started Jun 06 01:13:14 PM PDT 24
Finished Jun 06 01:13:16 PM PDT 24
Peak memory 208756 kb
Host smart-4bda880b-7363-459d-9d85-67cbf110b6de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172660488 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_alert_test.2172660488
Directory /workspace/36.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.lc_ctrl_errors.489120176
Short name T494
Test name
Test status
Simulation time 1886350415 ps
CPU time 11.25 seconds
Started Jun 06 01:13:14 PM PDT 24
Finished Jun 06 01:13:26 PM PDT 24
Peak memory 218012 kb
Host smart-234a102a-593d-4c59-aaa3-62a3bd9978a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489120176 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_errors.489120176
Directory /workspace/36.lc_ctrl_errors/latest

Test location /workspace/coverage/default/36.lc_ctrl_jtag_access.3912969397
Short name T783
Test name
Test status
Simulation time 208804534 ps
CPU time 5.66 seconds
Started Jun 06 01:13:16 PM PDT 24
Finished Jun 06 01:13:22 PM PDT 24
Peak memory 216968 kb
Host smart-154c5995-17ae-493d-9699-e5067cd4073d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912969397 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_jtag_access.3912969397
Directory /workspace/36.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/36.lc_ctrl_prog_failure.930663471
Short name T610
Test name
Test status
Simulation time 360216771 ps
CPU time 4.35 seconds
Started Jun 06 01:13:14 PM PDT 24
Finished Jun 06 01:13:20 PM PDT 24
Peak memory 218228 kb
Host smart-67cf0bac-8fcc-4cd0-bbfc-ad2427a674bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930663471 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_prog_failure.930663471
Directory /workspace/36.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_mubi.30225835
Short name T118
Test name
Test status
Simulation time 3753092908 ps
CPU time 8.44 seconds
Started Jun 06 01:13:13 PM PDT 24
Finished Jun 06 01:13:23 PM PDT 24
Peak memory 219976 kb
Host smart-04362ff4-5ac6-4f27-9858-125f716716a8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30225835 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_mubi.30225835
Directory /workspace/36.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_digest.34191947
Short name T357
Test name
Test status
Simulation time 341466809 ps
CPU time 13.17 seconds
Started Jun 06 01:13:13 PM PDT 24
Finished Jun 06 01:13:28 PM PDT 24
Peak memory 217888 kb
Host smart-fdbabb09-14ee-4b9c-aa46-ada1994b90a8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34191947 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_dig
est_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_dig
est.34191947
Directory /workspace/36.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_mux.600621868
Short name T730
Test name
Test status
Simulation time 1647052877 ps
CPU time 8.28 seconds
Started Jun 06 01:13:14 PM PDT 24
Finished Jun 06 01:13:23 PM PDT 24
Peak memory 218004 kb
Host smart-4968cdf8-ee7e-4127-8e3e-8b155a6d0c63
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600621868 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_mux.600621868
Directory /workspace/36.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/36.lc_ctrl_security_escalation.1307395728
Short name T235
Test name
Test status
Simulation time 235561545 ps
CPU time 9.33 seconds
Started Jun 06 01:13:14 PM PDT 24
Finished Jun 06 01:13:25 PM PDT 24
Peak memory 218072 kb
Host smart-4963383d-d00d-4d8c-8303-c849ae708e43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307395728 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_security_escalation.1307395728
Directory /workspace/36.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/36.lc_ctrl_smoke.3963432286
Short name T562
Test name
Test status
Simulation time 174370841 ps
CPU time 1.81 seconds
Started Jun 06 01:13:03 PM PDT 24
Finished Jun 06 01:13:06 PM PDT 24
Peak memory 217836 kb
Host smart-d8313812-95c2-43f5-96f5-4dbff30eb645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963432286 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_smoke.3963432286
Directory /workspace/36.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_failure.3809631478
Short name T616
Test name
Test status
Simulation time 334598955 ps
CPU time 14.09 seconds
Started Jun 06 01:13:04 PM PDT 24
Finished Jun 06 01:13:19 PM PDT 24
Peak memory 250988 kb
Host smart-1b2645b4-9b12-4ac5-a707-e00858e6b36c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809631478 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_failure.3809631478
Directory /workspace/36.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_post_trans.1660465942
Short name T754
Test name
Test status
Simulation time 161534859 ps
CPU time 6.95 seconds
Started Jun 06 01:13:12 PM PDT 24
Finished Jun 06 01:13:20 PM PDT 24
Peak memory 250820 kb
Host smart-63d55d3b-a8ed-4b01-b7ef-8720d4ac3e75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660465942 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_post_trans.1660465942
Directory /workspace/36.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all.3542491654
Short name T482
Test name
Test status
Simulation time 42199971372 ps
CPU time 529.34 seconds
Started Jun 06 01:13:13 PM PDT 24
Finished Jun 06 01:22:04 PM PDT 24
Peak memory 251068 kb
Host smart-3b36a79b-09cd-4e60-86a8-b0d61c65d506
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542491654 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.lc_ctrl_stress_all.3542491654
Directory /workspace/36.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all_with_rand_reset.3530917899
Short name T703
Test name
Test status
Simulation time 95944059194 ps
CPU time 9663.77 seconds
Started Jun 06 01:13:12 PM PDT 24
Finished Jun 06 03:54:17 PM PDT 24
Peak memory 644364 kb
Host smart-74aa1eb8-fdd9-4127-ad68-d78f8208fdcf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3530917899 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_stress_all_with_rand_reset.3530917899
Directory /workspace/36.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.lc_ctrl_volatile_unlock_smoke.1377892051
Short name T685
Test name
Test status
Simulation time 51825138 ps
CPU time 0.93 seconds
Started Jun 06 01:13:03 PM PDT 24
Finished Jun 06 01:13:05 PM PDT 24
Peak memory 211484 kb
Host smart-5b8d180c-38c4-4a7f-a1c9-6a4466e05cf6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377892051 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_c
trl_volatile_unlock_smoke.1377892051
Directory /workspace/36.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_alert_test.2944228793
Short name T706
Test name
Test status
Simulation time 22504368 ps
CPU time 1.18 seconds
Started Jun 06 01:13:14 PM PDT 24
Finished Jun 06 01:13:16 PM PDT 24
Peak memory 208656 kb
Host smart-da69e271-916d-4dc7-896e-611b907443b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944228793 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_alert_test.2944228793
Directory /workspace/37.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.lc_ctrl_errors.3885288737
Short name T290
Test name
Test status
Simulation time 537052858 ps
CPU time 13.76 seconds
Started Jun 06 01:13:14 PM PDT 24
Finished Jun 06 01:13:29 PM PDT 24
Peak memory 217936 kb
Host smart-77191dcf-33df-4621-9f0a-ec6a522ab238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885288737 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_errors.3885288737
Directory /workspace/37.lc_ctrl_errors/latest

Test location /workspace/coverage/default/37.lc_ctrl_jtag_access.3435970302
Short name T875
Test name
Test status
Simulation time 1753880918 ps
CPU time 5.19 seconds
Started Jun 06 01:13:14 PM PDT 24
Finished Jun 06 01:13:21 PM PDT 24
Peak memory 209732 kb
Host smart-1b7e2477-b966-4e82-866d-77bc9997e9c9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435970302 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_jtag_access.3435970302
Directory /workspace/37.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/37.lc_ctrl_prog_failure.2717972515
Short name T648
Test name
Test status
Simulation time 410193241 ps
CPU time 4.07 seconds
Started Jun 06 01:13:14 PM PDT 24
Finished Jun 06 01:13:19 PM PDT 24
Peak memory 218020 kb
Host smart-73617ad8-00ba-4e92-a422-59e2da2a883c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717972515 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_prog_failure.2717972515
Directory /workspace/37.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_mubi.1783415879
Short name T859
Test name
Test status
Simulation time 915835088 ps
CPU time 14.58 seconds
Started Jun 06 01:13:13 PM PDT 24
Finished Jun 06 01:13:29 PM PDT 24
Peak memory 226052 kb
Host smart-a5b47042-46a8-446a-8980-c5f31e173468
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783415879 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_mubi.1783415879
Directory /workspace/37.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_digest.3298069813
Short name T613
Test name
Test status
Simulation time 1255891953 ps
CPU time 9.81 seconds
Started Jun 06 01:13:14 PM PDT 24
Finished Jun 06 01:13:25 PM PDT 24
Peak memory 226016 kb
Host smart-8b9150a8-cb7e-4d5e-8d84-c3db97501e49
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298069813 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_d
igest.3298069813
Directory /workspace/37.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_mux.4176527058
Short name T834
Test name
Test status
Simulation time 317190179 ps
CPU time 6.76 seconds
Started Jun 06 01:13:14 PM PDT 24
Finished Jun 06 01:13:22 PM PDT 24
Peak memory 218000 kb
Host smart-8863504a-fdbc-4cb4-9dec-8b8d22c65853
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176527058 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_mux.
4176527058
Directory /workspace/37.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/37.lc_ctrl_security_escalation.1400016401
Short name T284
Test name
Test status
Simulation time 3484226606 ps
CPU time 6.03 seconds
Started Jun 06 01:13:12 PM PDT 24
Finished Jun 06 01:13:19 PM PDT 24
Peak memory 218184 kb
Host smart-84ef2fa4-cd20-4f9f-9858-5dde50d8e942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1400016401 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_security_escalation.1400016401
Directory /workspace/37.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/37.lc_ctrl_smoke.2883867358
Short name T871
Test name
Test status
Simulation time 132498485 ps
CPU time 1.84 seconds
Started Jun 06 01:13:14 PM PDT 24
Finished Jun 06 01:13:17 PM PDT 24
Peak memory 213884 kb
Host smart-ed784adc-03ab-43e2-99af-68c20df95330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883867358 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_smoke.2883867358
Directory /workspace/37.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_failure.1260271062
Short name T355
Test name
Test status
Simulation time 761661883 ps
CPU time 17 seconds
Started Jun 06 01:13:14 PM PDT 24
Finished Jun 06 01:13:32 PM PDT 24
Peak memory 250964 kb
Host smart-b1ab4b82-7005-42f7-b92a-f692381037bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260271062 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_failure.1260271062
Directory /workspace/37.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_post_trans.4107293432
Short name T865
Test name
Test status
Simulation time 102248905 ps
CPU time 7.77 seconds
Started Jun 06 01:13:13 PM PDT 24
Finished Jun 06 01:13:22 PM PDT 24
Peak memory 250936 kb
Host smart-9a92c417-5e2f-42be-9b71-5334ec526c66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107293432 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_post_trans.4107293432
Directory /workspace/37.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all.1420936819
Short name T325
Test name
Test status
Simulation time 37060178625 ps
CPU time 179.47 seconds
Started Jun 06 01:13:12 PM PDT 24
Finished Jun 06 01:16:12 PM PDT 24
Peak memory 250836 kb
Host smart-ef76c985-5e48-4d9f-bebe-9987948e322d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420936819 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.lc_ctrl_stress_all.1420936819
Directory /workspace/37.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.lc_ctrl_volatile_unlock_smoke.3894007439
Short name T737
Test name
Test status
Simulation time 16076410 ps
CPU time 1.02 seconds
Started Jun 06 01:13:16 PM PDT 24
Finished Jun 06 01:13:18 PM PDT 24
Peak memory 211432 kb
Host smart-ac1ccc37-e12f-41b3-a23c-913adad6410e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894007439 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_c
trl_volatile_unlock_smoke.3894007439
Directory /workspace/37.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_errors.1642534509
Short name T530
Test name
Test status
Simulation time 507464456 ps
CPU time 14.28 seconds
Started Jun 06 01:13:12 PM PDT 24
Finished Jun 06 01:13:27 PM PDT 24
Peak memory 217956 kb
Host smart-37ed4fce-51e8-4f4d-9a47-542fcc9d3234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642534509 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_errors.1642534509
Directory /workspace/38.lc_ctrl_errors/latest

Test location /workspace/coverage/default/38.lc_ctrl_jtag_access.1586396161
Short name T559
Test name
Test status
Simulation time 408436185 ps
CPU time 10.7 seconds
Started Jun 06 01:13:23 PM PDT 24
Finished Jun 06 01:13:35 PM PDT 24
Peak memory 217228 kb
Host smart-817ed425-a514-446f-81a6-052933307a82
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586396161 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_jtag_access.1586396161
Directory /workspace/38.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/38.lc_ctrl_prog_failure.105031226
Short name T626
Test name
Test status
Simulation time 79755152 ps
CPU time 3.11 seconds
Started Jun 06 01:13:14 PM PDT 24
Finished Jun 06 01:13:18 PM PDT 24
Peak memory 218076 kb
Host smart-7f568f96-4fb4-4566-8f81-b2fd34da2fe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105031226 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_prog_failure.105031226
Directory /workspace/38.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_mubi.1789523084
Short name T362
Test name
Test status
Simulation time 416635991 ps
CPU time 18.62 seconds
Started Jun 06 01:13:12 PM PDT 24
Finished Jun 06 01:13:32 PM PDT 24
Peak memory 218220 kb
Host smart-8af9c2ec-8568-4e02-980b-7c2b946fa31e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789523084 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_mubi.1789523084
Directory /workspace/38.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_digest.3555098214
Short name T312
Test name
Test status
Simulation time 1937544486 ps
CPU time 10.66 seconds
Started Jun 06 01:13:16 PM PDT 24
Finished Jun 06 01:13:27 PM PDT 24
Peak memory 217964 kb
Host smart-1090b43a-01f3-41d8-97d5-e4b079e7561d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555098214 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_d
igest.3555098214
Directory /workspace/38.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_mux.3197644536
Short name T66
Test name
Test status
Simulation time 1765294169 ps
CPU time 6.95 seconds
Started Jun 06 01:13:13 PM PDT 24
Finished Jun 06 01:13:21 PM PDT 24
Peak memory 218012 kb
Host smart-e7b4c020-3de1-4cc7-9e90-5fe79ceb841b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197644536 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_mux.
3197644536
Directory /workspace/38.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/38.lc_ctrl_smoke.216686920
Short name T854
Test name
Test status
Simulation time 41268489 ps
CPU time 2.87 seconds
Started Jun 06 01:13:14 PM PDT 24
Finished Jun 06 01:13:18 PM PDT 24
Peak memory 214304 kb
Host smart-d70a33a4-b49a-4d61-9865-9b0712e7d4da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216686920 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_smoke.216686920
Directory /workspace/38.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_failure.3661387095
Short name T684
Test name
Test status
Simulation time 571546935 ps
CPU time 23.58 seconds
Started Jun 06 01:13:18 PM PDT 24
Finished Jun 06 01:13:43 PM PDT 24
Peak memory 250972 kb
Host smart-68710c3e-df41-4fde-a726-d082444ed450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661387095 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_failure.3661387095
Directory /workspace/38.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_post_trans.120039975
Short name T521
Test name
Test status
Simulation time 109643172 ps
CPU time 6.88 seconds
Started Jun 06 01:13:15 PM PDT 24
Finished Jun 06 01:13:23 PM PDT 24
Peak memory 246512 kb
Host smart-a42c6065-6d8e-4cbd-8a8a-187f81b19133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120039975 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_post_trans.120039975
Directory /workspace/38.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all.3021963156
Short name T183
Test name
Test status
Simulation time 7807404509 ps
CPU time 175.47 seconds
Started Jun 06 01:13:23 PM PDT 24
Finished Jun 06 01:16:20 PM PDT 24
Peak memory 254740 kb
Host smart-7777c268-b68f-4cfe-888c-eafcab4cf77f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021963156 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.lc_ctrl_stress_all.3021963156
Directory /workspace/38.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.lc_ctrl_volatile_unlock_smoke.2808958095
Short name T528
Test name
Test status
Simulation time 52836908 ps
CPU time 0.92 seconds
Started Jun 06 01:13:13 PM PDT 24
Finished Jun 06 01:13:15 PM PDT 24
Peak memory 211540 kb
Host smart-a9046cb3-2122-4f0b-8e0f-072b7e7ad90f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808958095 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_c
trl_volatile_unlock_smoke.2808958095
Directory /workspace/38.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_alert_test.3029788077
Short name T194
Test name
Test status
Simulation time 97025767 ps
CPU time 0.98 seconds
Started Jun 06 01:13:29 PM PDT 24
Finished Jun 06 01:13:31 PM PDT 24
Peak memory 208696 kb
Host smart-49f0fae3-9230-4690-9053-ef89451485e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029788077 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_alert_test.3029788077
Directory /workspace/39.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.lc_ctrl_errors.2578496441
Short name T807
Test name
Test status
Simulation time 316995824 ps
CPU time 10.71 seconds
Started Jun 06 01:13:23 PM PDT 24
Finished Jun 06 01:13:35 PM PDT 24
Peak memory 218208 kb
Host smart-7a211a6b-a318-4070-b7ab-4a8d693d28a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578496441 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_errors.2578496441
Directory /workspace/39.lc_ctrl_errors/latest

Test location /workspace/coverage/default/39.lc_ctrl_jtag_access.1495068166
Short name T222
Test name
Test status
Simulation time 1118724650 ps
CPU time 3.4 seconds
Started Jun 06 01:13:23 PM PDT 24
Finished Jun 06 01:13:27 PM PDT 24
Peak memory 209496 kb
Host smart-6068d71a-091d-4aee-ad2e-cb7034bf9759
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495068166 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_jtag_access.1495068166
Directory /workspace/39.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/39.lc_ctrl_prog_failure.1725368891
Short name T541
Test name
Test status
Simulation time 31470035 ps
CPU time 2.15 seconds
Started Jun 06 01:13:20 PM PDT 24
Finished Jun 06 01:13:23 PM PDT 24
Peak memory 217976 kb
Host smart-29542e65-27a1-432f-913d-c67ff836a131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725368891 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_prog_failure.1725368891
Directory /workspace/39.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_mubi.2913454352
Short name T68
Test name
Test status
Simulation time 360739564 ps
CPU time 14.81 seconds
Started Jun 06 01:13:27 PM PDT 24
Finished Jun 06 01:13:42 PM PDT 24
Peak memory 226044 kb
Host smart-7beb3f55-bca2-4a14-9216-b9051332443a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913454352 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_mubi.2913454352
Directory /workspace/39.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_digest.4132298729
Short name T869
Test name
Test status
Simulation time 2657377673 ps
CPU time 15.05 seconds
Started Jun 06 01:13:23 PM PDT 24
Finished Jun 06 01:13:39 PM PDT 24
Peak memory 226064 kb
Host smart-92b6e8fe-f56b-4e5f-a8f8-29c8ba73d999
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132298729 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_d
igest.4132298729
Directory /workspace/39.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_mux.4186597753
Short name T551
Test name
Test status
Simulation time 2225726787 ps
CPU time 10.99 seconds
Started Jun 06 01:13:21 PM PDT 24
Finished Jun 06 01:13:33 PM PDT 24
Peak memory 218048 kb
Host smart-fa76a849-1dec-4826-a058-a6601840a649
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186597753 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_mux.
4186597753
Directory /workspace/39.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/39.lc_ctrl_security_escalation.377219134
Short name T463
Test name
Test status
Simulation time 236091726 ps
CPU time 7.29 seconds
Started Jun 06 01:13:23 PM PDT 24
Finished Jun 06 01:13:31 PM PDT 24
Peak memory 218112 kb
Host smart-62eae3d1-a8dd-4815-92f1-37e161127453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377219134 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_security_escalation.377219134
Directory /workspace/39.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/39.lc_ctrl_smoke.2147173968
Short name T572
Test name
Test status
Simulation time 93130895 ps
CPU time 3.03 seconds
Started Jun 06 01:13:22 PM PDT 24
Finished Jun 06 01:13:26 PM PDT 24
Peak memory 214340 kb
Host smart-9e348fa0-2cdb-454d-9517-51b5b2bd95e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147173968 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_smoke.2147173968
Directory /workspace/39.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_failure.3377697406
Short name T435
Test name
Test status
Simulation time 677292703 ps
CPU time 19.34 seconds
Started Jun 06 01:13:30 PM PDT 24
Finished Jun 06 01:13:50 PM PDT 24
Peak memory 251096 kb
Host smart-b4a95d28-c536-446d-a952-797d90b91804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377697406 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_failure.3377697406
Directory /workspace/39.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_post_trans.1239344074
Short name T263
Test name
Test status
Simulation time 87320486 ps
CPU time 7.26 seconds
Started Jun 06 01:13:21 PM PDT 24
Finished Jun 06 01:13:29 PM PDT 24
Peak memory 246900 kb
Host smart-2f91ede4-3745-4136-97fe-6e755a0ac62d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239344074 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_post_trans.1239344074
Directory /workspace/39.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all.1109994792
Short name T632
Test name
Test status
Simulation time 9545462119 ps
CPU time 338.53 seconds
Started Jun 06 01:13:21 PM PDT 24
Finished Jun 06 01:19:00 PM PDT 24
Peak memory 251000 kb
Host smart-d51a736a-5f4f-4734-afe2-990222e89025
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109994792 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.lc_ctrl_stress_all.1109994792
Directory /workspace/39.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.lc_ctrl_volatile_unlock_smoke.3317404810
Short name T264
Test name
Test status
Simulation time 65359997 ps
CPU time 0.94 seconds
Started Jun 06 01:13:29 PM PDT 24
Finished Jun 06 01:13:31 PM PDT 24
Peak memory 212608 kb
Host smart-6d1d7a54-9008-42b0-a9e4-374ca3dd3eb7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317404810 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_c
trl_volatile_unlock_smoke.3317404810
Directory /workspace/39.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_alert_test.836487822
Short name T808
Test name
Test status
Simulation time 171841122 ps
CPU time 1.25 seconds
Started Jun 06 01:10:10 PM PDT 24
Finished Jun 06 01:10:12 PM PDT 24
Peak memory 208700 kb
Host smart-859c62a3-ec99-430e-9aaa-952b599b7d8b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836487822 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_alert_test.836487822
Directory /workspace/4.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.lc_ctrl_errors.3177904700
Short name T53
Test name
Test status
Simulation time 696577832 ps
CPU time 12.32 seconds
Started Jun 06 01:10:01 PM PDT 24
Finished Jun 06 01:10:15 PM PDT 24
Peak memory 217928 kb
Host smart-a3f00040-726d-4bbf-b0ad-5b7587172ecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177904700 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_errors.3177904700
Directory /workspace/4.lc_ctrl_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_access.2338191140
Short name T862
Test name
Test status
Simulation time 452883559 ps
CPU time 5.72 seconds
Started Jun 06 01:10:11 PM PDT 24
Finished Jun 06 01:10:18 PM PDT 24
Peak memory 209508 kb
Host smart-556c566d-f609-43c4-9f7e-b35fcf133b13
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338191140 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_access.2338191140
Directory /workspace/4.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_errors.995775855
Short name T303
Test name
Test status
Simulation time 9792031992 ps
CPU time 68.51 seconds
Started Jun 06 01:10:02 PM PDT 24
Finished Jun 06 01:11:12 PM PDT 24
Peak memory 218932 kb
Host smart-ae8de5e2-beba-4e91-ae33-f92a50087c7d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995775855 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_err
ors.995775855
Directory /workspace/4.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_priority.2461533605
Short name T749
Test name
Test status
Simulation time 3101090553 ps
CPU time 34.08 seconds
Started Jun 06 01:10:03 PM PDT 24
Finished Jun 06 01:10:38 PM PDT 24
Peak memory 217836 kb
Host smart-a9dab049-6b7e-4d1a-9bf6-97998577b401
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461533605 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_priority.2
461533605
Directory /workspace/4.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_prog_failure.3845282124
Short name T680
Test name
Test status
Simulation time 890301284 ps
CPU time 4.64 seconds
Started Jun 06 01:10:03 PM PDT 24
Finished Jun 06 01:10:09 PM PDT 24
Peak memory 217940 kb
Host smart-d965b703-71b5-4806-a6ab-9c7acf35d9de
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845282124 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag
_prog_failure.3845282124
Directory /workspace/4.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_regwen_during_op.2047722192
Short name T679
Test name
Test status
Simulation time 998367660 ps
CPU time 19.51 seconds
Started Jun 06 01:10:02 PM PDT 24
Finished Jun 06 01:10:23 PM PDT 24
Peak memory 217580 kb
Host smart-66888d36-b692-46dd-9030-34989c3414d2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047722192 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_regwen_during_op.2047722192
Directory /workspace/4.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_smoke.1095865961
Short name T371
Test name
Test status
Simulation time 559434400 ps
CPU time 2.08 seconds
Started Jun 06 01:10:11 PM PDT 24
Finished Jun 06 01:10:14 PM PDT 24
Peak memory 217652 kb
Host smart-d54d4e51-31ad-437b-8b85-e1d0529cbb01
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095865961 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_smoke.
1095865961
Directory /workspace/4.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_failure.1224313031
Short name T863
Test name
Test status
Simulation time 858807135 ps
CPU time 38.12 seconds
Started Jun 06 01:10:04 PM PDT 24
Finished Jun 06 01:10:43 PM PDT 24
Peak memory 250892 kb
Host smart-3eb12c79-83e9-4b8a-9e55-d1bd9bff9584
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224313031 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jta
g_state_failure.1224313031
Directory /workspace/4.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_post_trans.1660329651
Short name T496
Test name
Test status
Simulation time 444450465 ps
CPU time 11.06 seconds
Started Jun 06 01:10:01 PM PDT 24
Finished Jun 06 01:10:13 PM PDT 24
Peak memory 248580 kb
Host smart-b08fadfa-c8d0-4951-9310-3ce0d68e06e8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660329651 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_state_post_trans.1660329651
Directory /workspace/4.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_prog_failure.2995487129
Short name T310
Test name
Test status
Simulation time 128703988 ps
CPU time 2.12 seconds
Started Jun 06 01:10:11 PM PDT 24
Finished Jun 06 01:10:14 PM PDT 24
Peak memory 218044 kb
Host smart-d740295b-e1fe-4036-b88b-8340fe22d7bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995487129 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_prog_failure.2995487129
Directory /workspace/4.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_regwen_during_op.2178262199
Short name T590
Test name
Test status
Simulation time 951050888 ps
CPU time 9.47 seconds
Started Jun 06 01:10:03 PM PDT 24
Finished Jun 06 01:10:13 PM PDT 24
Peak memory 217680 kb
Host smart-3480ce02-0de4-41db-8f52-20c12f7260bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178262199 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_regwen_during_op.2178262199
Directory /workspace/4.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_cm.2345467154
Short name T110
Test name
Test status
Simulation time 1224254872 ps
CPU time 48.77 seconds
Started Jun 06 01:10:10 PM PDT 24
Finished Jun 06 01:11:00 PM PDT 24
Peak memory 270312 kb
Host smart-5aae5f3e-5955-4501-a517-79bc954a6dcb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345467154 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_cm.2345467154
Directory /workspace/4.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_mubi.490008336
Short name T759
Test name
Test status
Simulation time 621121498 ps
CPU time 10.84 seconds
Started Jun 06 01:10:11 PM PDT 24
Finished Jun 06 01:10:23 PM PDT 24
Peak memory 218932 kb
Host smart-8f619ac6-32d7-4893-8212-3fdf5ab4216c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490008336 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_mubi.490008336
Directory /workspace/4.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_digest.3755433488
Short name T688
Test name
Test status
Simulation time 1286348948 ps
CPU time 9 seconds
Started Jun 06 01:10:10 PM PDT 24
Finished Jun 06 01:10:20 PM PDT 24
Peak memory 217940 kb
Host smart-d4a6e7da-a6a4-4b57-8c00-741bf201b6fe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755433488 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_di
gest.3755433488
Directory /workspace/4.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_mux.2297585055
Short name T349
Test name
Test status
Simulation time 317857988 ps
CPU time 11.29 seconds
Started Jun 06 01:10:11 PM PDT 24
Finished Jun 06 01:10:23 PM PDT 24
Peak memory 217996 kb
Host smart-63d1fcc4-8b3f-49c5-a187-b5cfa6f32d41
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297585055 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_mux.2
297585055
Directory /workspace/4.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/4.lc_ctrl_security_escalation.975394107
Short name T379
Test name
Test status
Simulation time 918515663 ps
CPU time 11.43 seconds
Started Jun 06 01:10:03 PM PDT 24
Finished Jun 06 01:10:15 PM PDT 24
Peak memory 218084 kb
Host smart-3f96a586-a65b-47f5-8f52-7f3e1f780294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975394107 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_security_escalation.975394107
Directory /workspace/4.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/4.lc_ctrl_smoke.1007069451
Short name T433
Test name
Test status
Simulation time 214184872 ps
CPU time 2.66 seconds
Started Jun 06 01:09:57 PM PDT 24
Finished Jun 06 01:10:00 PM PDT 24
Peak memory 213968 kb
Host smart-8b414be5-90e5-4839-9839-f0c8c24768a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007069451 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_smoke.1007069451
Directory /workspace/4.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_failure.3639569418
Short name T442
Test name
Test status
Simulation time 1394413361 ps
CPU time 33.03 seconds
Started Jun 06 01:09:55 PM PDT 24
Finished Jun 06 01:10:29 PM PDT 24
Peak memory 250992 kb
Host smart-1de6d6ce-466f-4767-80c2-2ac904ee7752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639569418 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_failure.3639569418
Directory /workspace/4.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_post_trans.1319895544
Short name T727
Test name
Test status
Simulation time 695853359 ps
CPU time 7.2 seconds
Started Jun 06 01:10:03 PM PDT 24
Finished Jun 06 01:10:11 PM PDT 24
Peak memory 247056 kb
Host smart-e7653ad3-00da-48e1-8dd9-a0da191279d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1319895544 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_post_trans.1319895544
Directory /workspace/4.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_stress_all.3206056014
Short name T589
Test name
Test status
Simulation time 7121603787 ps
CPU time 88.34 seconds
Started Jun 06 01:10:17 PM PDT 24
Finished Jun 06 01:11:46 PM PDT 24
Peak memory 226052 kb
Host smart-4ac2ae13-53b5-4643-b6c8-15d9ce4d5993
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206056014 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.lc_ctrl_stress_all.3206056014
Directory /workspace/4.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.lc_ctrl_volatile_unlock_smoke.2136390764
Short name T801
Test name
Test status
Simulation time 21662971 ps
CPU time 0.89 seconds
Started Jun 06 01:09:55 PM PDT 24
Finished Jun 06 01:09:57 PM PDT 24
Peak memory 211548 kb
Host smart-0ffeebab-22f6-4ccd-b972-849fd5bd1240
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136390764 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ct
rl_volatile_unlock_smoke.2136390764
Directory /workspace/4.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_alert_test.2401020688
Short name T250
Test name
Test status
Simulation time 61046369 ps
CPU time 1.5 seconds
Started Jun 06 01:13:27 PM PDT 24
Finished Jun 06 01:13:29 PM PDT 24
Peak memory 208720 kb
Host smart-778f5008-f27f-4d19-b159-3147d43dfd51
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401020688 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_alert_test.2401020688
Directory /workspace/40.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.lc_ctrl_errors.1863605415
Short name T738
Test name
Test status
Simulation time 479611565 ps
CPU time 11.29 seconds
Started Jun 06 01:13:26 PM PDT 24
Finished Jun 06 01:13:38 PM PDT 24
Peak memory 217944 kb
Host smart-cdb1a9b4-683c-408c-a50c-2ca3aafec064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863605415 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_errors.1863605415
Directory /workspace/40.lc_ctrl_errors/latest

Test location /workspace/coverage/default/40.lc_ctrl_jtag_access.763288976
Short name T461
Test name
Test status
Simulation time 1186444025 ps
CPU time 14.1 seconds
Started Jun 06 01:13:30 PM PDT 24
Finished Jun 06 01:13:45 PM PDT 24
Peak memory 209488 kb
Host smart-f9ec64ec-e5f6-4c24-9f10-500a3eb4d5ae
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763288976 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_jtag_access.763288976
Directory /workspace/40.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/40.lc_ctrl_prog_failure.864315462
Short name T279
Test name
Test status
Simulation time 111789110 ps
CPU time 3.54 seconds
Started Jun 06 01:13:24 PM PDT 24
Finished Jun 06 01:13:29 PM PDT 24
Peak memory 218000 kb
Host smart-f6bc4416-6914-476a-a687-7293dbf58cdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864315462 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_prog_failure.864315462
Directory /workspace/40.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_mubi.2648030987
Short name T598
Test name
Test status
Simulation time 1522683900 ps
CPU time 13.9 seconds
Started Jun 06 01:13:24 PM PDT 24
Finished Jun 06 01:13:39 PM PDT 24
Peak memory 218940 kb
Host smart-90d6abe9-faae-4956-967b-b2c761665c6d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648030987 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_mubi.2648030987
Directory /workspace/40.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_digest.2435529772
Short name T852
Test name
Test status
Simulation time 642356884 ps
CPU time 8.87 seconds
Started Jun 06 01:13:23 PM PDT 24
Finished Jun 06 01:13:34 PM PDT 24
Peak memory 225864 kb
Host smart-8e7ab1fc-de6e-4447-a299-7e3b7e70d830
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435529772 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_d
igest.2435529772
Directory /workspace/40.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_mux.3020874321
Short name T336
Test name
Test status
Simulation time 1501952532 ps
CPU time 9.92 seconds
Started Jun 06 01:13:20 PM PDT 24
Finished Jun 06 01:13:31 PM PDT 24
Peak memory 218024 kb
Host smart-1039674b-3256-4213-b8a7-f613901d857d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020874321 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_mux.
3020874321
Directory /workspace/40.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/40.lc_ctrl_security_escalation.769573569
Short name T774
Test name
Test status
Simulation time 997689250 ps
CPU time 10.49 seconds
Started Jun 06 01:13:21 PM PDT 24
Finished Jun 06 01:13:33 PM PDT 24
Peak memory 218108 kb
Host smart-01cf996a-aefe-4909-b4e9-90dd2f4beaa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769573569 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_security_escalation.769573569
Directory /workspace/40.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/40.lc_ctrl_smoke.3591665882
Short name T839
Test name
Test status
Simulation time 62848509 ps
CPU time 2.13 seconds
Started Jun 06 01:13:22 PM PDT 24
Finished Jun 06 01:13:25 PM PDT 24
Peak memory 217688 kb
Host smart-c8dc3cdf-d975-4767-959f-9742f7a9b89c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591665882 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_smoke.3591665882
Directory /workspace/40.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_failure.3920367504
Short name T33
Test name
Test status
Simulation time 625797752 ps
CPU time 27.48 seconds
Started Jun 06 01:13:24 PM PDT 24
Finished Jun 06 01:13:52 PM PDT 24
Peak memory 250992 kb
Host smart-594548a0-a294-47e2-a0c3-053abc320f3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920367504 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_failure.3920367504
Directory /workspace/40.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_post_trans.2860048289
Short name T370
Test name
Test status
Simulation time 67309188 ps
CPU time 7.65 seconds
Started Jun 06 01:13:21 PM PDT 24
Finished Jun 06 01:13:30 PM PDT 24
Peak memory 251008 kb
Host smart-a7884618-40d4-428a-bf68-0a207906eb5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860048289 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_post_trans.2860048289
Directory /workspace/40.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/40.lc_ctrl_stress_all.3428927870
Short name T712
Test name
Test status
Simulation time 16083800653 ps
CPU time 42.87 seconds
Started Jun 06 01:13:23 PM PDT 24
Finished Jun 06 01:14:07 PM PDT 24
Peak memory 238948 kb
Host smart-4e205f0b-0a20-4a8c-ba4a-04b52e81a611
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428927870 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.lc_ctrl_stress_all.3428927870
Directory /workspace/40.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.lc_ctrl_stress_all_with_rand_reset.2537491993
Short name T168
Test name
Test status
Simulation time 20044165088 ps
CPU time 674.73 seconds
Started Jun 06 01:13:27 PM PDT 24
Finished Jun 06 01:24:43 PM PDT 24
Peak memory 316648 kb
Host smart-843edb54-c8d2-42fb-8915-7ae0c92a87f7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2537491993 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_stress_all_with_rand_reset.2537491993
Directory /workspace/40.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.lc_ctrl_alert_test.2552266648
Short name T189
Test name
Test status
Simulation time 136953650 ps
CPU time 1.09 seconds
Started Jun 06 01:13:28 PM PDT 24
Finished Jun 06 01:13:30 PM PDT 24
Peak memory 208668 kb
Host smart-1cfe4044-8fdc-4849-a292-d7a683cd5050
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552266648 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_alert_test.2552266648
Directory /workspace/41.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.lc_ctrl_errors.4216889911
Short name T637
Test name
Test status
Simulation time 208857505 ps
CPU time 10.95 seconds
Started Jun 06 01:13:22 PM PDT 24
Finished Jun 06 01:13:34 PM PDT 24
Peak memory 217992 kb
Host smart-30fbc911-d895-4d1b-87de-997383b579d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216889911 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_errors.4216889911
Directory /workspace/41.lc_ctrl_errors/latest

Test location /workspace/coverage/default/41.lc_ctrl_jtag_access.3080636247
Short name T481
Test name
Test status
Simulation time 405394719 ps
CPU time 11.04 seconds
Started Jun 06 01:13:22 PM PDT 24
Finished Jun 06 01:13:34 PM PDT 24
Peak memory 209496 kb
Host smart-2a3213ad-8225-4d1e-a383-fa950775729f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080636247 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_jtag_access.3080636247
Directory /workspace/41.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/41.lc_ctrl_prog_failure.1829074815
Short name T320
Test name
Test status
Simulation time 488678568 ps
CPU time 3.03 seconds
Started Jun 06 01:13:21 PM PDT 24
Finished Jun 06 01:13:25 PM PDT 24
Peak memory 218068 kb
Host smart-e52788d3-f815-4dc6-af25-fd1919ade76d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829074815 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_prog_failure.1829074815
Directory /workspace/41.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_mubi.914215363
Short name T822
Test name
Test status
Simulation time 6679950062 ps
CPU time 15.87 seconds
Started Jun 06 01:13:30 PM PDT 24
Finished Jun 06 01:13:47 PM PDT 24
Peak memory 219240 kb
Host smart-4cb2fcd8-511a-4f5a-905d-266da7861865
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914215363 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_mubi.914215363
Directory /workspace/41.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_digest.2633229451
Short name T792
Test name
Test status
Simulation time 1301997357 ps
CPU time 7.5 seconds
Started Jun 06 01:13:26 PM PDT 24
Finished Jun 06 01:13:34 PM PDT 24
Peak memory 217684 kb
Host smart-9ddb96a5-c9a9-4a15-a6a7-b3d0faff8a7f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633229451 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_d
igest.2633229451
Directory /workspace/41.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_mux.59411705
Short name T701
Test name
Test status
Simulation time 736618912 ps
CPU time 6.23 seconds
Started Jun 06 01:13:23 PM PDT 24
Finished Jun 06 01:13:30 PM PDT 24
Peak memory 218000 kb
Host smart-38248a1b-9a4a-423c-ba82-d1648eb9ceb1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59411705 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_mux.59411705
Directory /workspace/41.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/41.lc_ctrl_security_escalation.3056788484
Short name T407
Test name
Test status
Simulation time 702471025 ps
CPU time 13.29 seconds
Started Jun 06 01:13:20 PM PDT 24
Finished Jun 06 01:13:35 PM PDT 24
Peak memory 226116 kb
Host smart-eb293f9e-6f69-450a-9044-6df037955ff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056788484 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_security_escalation.3056788484
Directory /workspace/41.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/41.lc_ctrl_smoke.1328049929
Short name T576
Test name
Test status
Simulation time 332997826 ps
CPU time 2.33 seconds
Started Jun 06 01:13:22 PM PDT 24
Finished Jun 06 01:13:25 PM PDT 24
Peak memory 214344 kb
Host smart-48685002-e038-4ddd-8431-71fbabf787b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328049929 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_smoke.1328049929
Directory /workspace/41.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_failure.1328011865
Short name T872
Test name
Test status
Simulation time 667072679 ps
CPU time 20.83 seconds
Started Jun 06 01:13:27 PM PDT 24
Finished Jun 06 01:13:48 PM PDT 24
Peak memory 250712 kb
Host smart-b59d311d-98e3-42d2-aeb8-5ef6bdf40ecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328011865 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_failure.1328011865
Directory /workspace/41.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_post_trans.1141528842
Short name T294
Test name
Test status
Simulation time 317521310 ps
CPU time 6.62 seconds
Started Jun 06 01:13:26 PM PDT 24
Finished Jun 06 01:13:33 PM PDT 24
Peak memory 250276 kb
Host smart-3b54b769-9dcf-47e9-9ac4-2bda15128850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141528842 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_post_trans.1141528842
Directory /workspace/41.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all.1939969308
Short name T518
Test name
Test status
Simulation time 36577298639 ps
CPU time 245.79 seconds
Started Jun 06 01:13:23 PM PDT 24
Finished Jun 06 01:17:30 PM PDT 24
Peak memory 273700 kb
Host smart-e1e9428c-caa5-4688-bb96-3eaeb24c26de
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939969308 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.lc_ctrl_stress_all.1939969308
Directory /workspace/41.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.lc_ctrl_volatile_unlock_smoke.4260294217
Short name T315
Test name
Test status
Simulation time 37170100 ps
CPU time 0.77 seconds
Started Jun 06 01:13:21 PM PDT 24
Finished Jun 06 01:13:23 PM PDT 24
Peak memory 208280 kb
Host smart-057a2358-706a-44fb-b19c-d7b63dcbc0a5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260294217 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_c
trl_volatile_unlock_smoke.4260294217
Directory /workspace/41.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_alert_test.489254102
Short name T731
Test name
Test status
Simulation time 21511767 ps
CPU time 0.79 seconds
Started Jun 06 01:13:31 PM PDT 24
Finished Jun 06 01:13:33 PM PDT 24
Peak memory 209372 kb
Host smart-c27ea764-ccdc-4c96-9508-3e81dd4931fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489254102 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_alert_test.489254102
Directory /workspace/42.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.lc_ctrl_errors.4189073044
Short name T198
Test name
Test status
Simulation time 251521407 ps
CPU time 9.02 seconds
Started Jun 06 01:13:37 PM PDT 24
Finished Jun 06 01:13:46 PM PDT 24
Peak memory 217932 kb
Host smart-a28cbfac-679a-4387-b596-f25057988806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189073044 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_errors.4189073044
Directory /workspace/42.lc_ctrl_errors/latest

Test location /workspace/coverage/default/42.lc_ctrl_jtag_access.892066593
Short name T30
Test name
Test status
Simulation time 12201736411 ps
CPU time 11.75 seconds
Started Jun 06 01:13:31 PM PDT 24
Finished Jun 06 01:13:44 PM PDT 24
Peak memory 209552 kb
Host smart-ea4cc97d-5f83-4a48-a21c-1c01e7e0a412
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892066593 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_jtag_access.892066593
Directory /workspace/42.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/42.lc_ctrl_prog_failure.3671719580
Short name T645
Test name
Test status
Simulation time 54418705 ps
CPU time 1.39 seconds
Started Jun 06 01:13:30 PM PDT 24
Finished Jun 06 01:13:33 PM PDT 24
Peak memory 218036 kb
Host smart-8cbf0c48-24f1-4306-abd4-2421068dc8ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671719580 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_prog_failure.3671719580
Directory /workspace/42.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_mubi.3153144868
Short name T536
Test name
Test status
Simulation time 451028365 ps
CPU time 17.69 seconds
Started Jun 06 01:13:31 PM PDT 24
Finished Jun 06 01:13:50 PM PDT 24
Peak memory 217940 kb
Host smart-f4cae455-cbe9-4d21-ab8a-151b269bd043
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153144868 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_mubi.3153144868
Directory /workspace/42.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_digest.2469852759
Short name T535
Test name
Test status
Simulation time 3132212309 ps
CPU time 18.1 seconds
Started Jun 06 01:13:31 PM PDT 24
Finished Jun 06 01:13:50 PM PDT 24
Peak memory 218872 kb
Host smart-847ef4be-8ddc-45d6-94c1-eb80f37d22d7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469852759 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_d
igest.2469852759
Directory /workspace/42.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_mux.1830862588
Short name T864
Test name
Test status
Simulation time 706584375 ps
CPU time 7.67 seconds
Started Jun 06 01:13:30 PM PDT 24
Finished Jun 06 01:13:39 PM PDT 24
Peak memory 217972 kb
Host smart-3f5d0948-5b21-45bc-aa72-0252321ff254
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830862588 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_mux.
1830862588
Directory /workspace/42.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/42.lc_ctrl_security_escalation.2503977633
Short name T36
Test name
Test status
Simulation time 542877029 ps
CPU time 7.16 seconds
Started Jun 06 01:13:37 PM PDT 24
Finished Jun 06 01:13:44 PM PDT 24
Peak memory 217968 kb
Host smart-b62ca17e-831e-4587-a3a0-8185f2a60917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503977633 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_security_escalation.2503977633
Directory /workspace/42.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/42.lc_ctrl_smoke.2607653466
Short name T34
Test name
Test status
Simulation time 36073307 ps
CPU time 2.12 seconds
Started Jun 06 01:13:32 PM PDT 24
Finished Jun 06 01:13:35 PM PDT 24
Peak memory 213752 kb
Host smart-54a65205-9004-4a88-b58f-71e8f50ae930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607653466 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_smoke.2607653466
Directory /workspace/42.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_failure.2151635658
Short name T848
Test name
Test status
Simulation time 689754551 ps
CPU time 31.78 seconds
Started Jun 06 01:13:36 PM PDT 24
Finished Jun 06 01:14:09 PM PDT 24
Peak memory 250900 kb
Host smart-abf1dbbd-8c6b-4155-9881-d28d474349ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151635658 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_failure.2151635658
Directory /workspace/42.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_post_trans.1133884099
Short name T426
Test name
Test status
Simulation time 51139884 ps
CPU time 6.25 seconds
Started Jun 06 01:13:30 PM PDT 24
Finished Jun 06 01:13:38 PM PDT 24
Peak memory 250048 kb
Host smart-7c67883c-0c76-4413-922f-0de344a6b9aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133884099 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_post_trans.1133884099
Directory /workspace/42.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/42.lc_ctrl_stress_all.1306823626
Short name T621
Test name
Test status
Simulation time 14707969615 ps
CPU time 497.77 seconds
Started Jun 06 01:13:30 PM PDT 24
Finished Jun 06 01:21:50 PM PDT 24
Peak memory 266796 kb
Host smart-3e32c55e-47a6-427b-a198-eb50a3d6ebe4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306823626 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.lc_ctrl_stress_all.1306823626
Directory /workspace/42.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.lc_ctrl_stress_all_with_rand_reset.3734070593
Short name T163
Test name
Test status
Simulation time 24519383373 ps
CPU time 688.65 seconds
Started Jun 06 01:13:30 PM PDT 24
Finished Jun 06 01:25:00 PM PDT 24
Peak memory 422220 kb
Host smart-05a84db4-8bce-4bbd-97f1-ce34bb7c80d9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3734070593 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_stress_all_with_rand_reset.3734070593
Directory /workspace/42.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.lc_ctrl_volatile_unlock_smoke.286093122
Short name T454
Test name
Test status
Simulation time 33590875 ps
CPU time 0.82 seconds
Started Jun 06 01:13:29 PM PDT 24
Finished Jun 06 01:13:31 PM PDT 24
Peak memory 207968 kb
Host smart-0e2b24d6-77f0-4568-9dab-86fb118ec1f6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286093122 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ct
rl_volatile_unlock_smoke.286093122
Directory /workspace/42.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_alert_test.722907262
Short name T287
Test name
Test status
Simulation time 33260421 ps
CPU time 0.9 seconds
Started Jun 06 01:13:41 PM PDT 24
Finished Jun 06 01:13:43 PM PDT 24
Peak memory 208696 kb
Host smart-8a5cdfdd-524d-4d6e-9243-268d2d5e2b2c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722907262 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_alert_test.722907262
Directory /workspace/43.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.lc_ctrl_errors.3505161763
Short name T500
Test name
Test status
Simulation time 2189032627 ps
CPU time 15.39 seconds
Started Jun 06 01:13:32 PM PDT 24
Finished Jun 06 01:13:48 PM PDT 24
Peak memory 218024 kb
Host smart-7ae5c031-167b-49d9-bd40-1e2657a000ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3505161763 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_errors.3505161763
Directory /workspace/43.lc_ctrl_errors/latest

Test location /workspace/coverage/default/43.lc_ctrl_jtag_access.589472325
Short name T510
Test name
Test status
Simulation time 1028792367 ps
CPU time 7.25 seconds
Started Jun 06 01:13:42 PM PDT 24
Finished Jun 06 01:13:51 PM PDT 24
Peak memory 217000 kb
Host smart-acafe644-403a-45e1-a8e1-9d519aecce9b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589472325 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_jtag_access.589472325
Directory /workspace/43.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/43.lc_ctrl_prog_failure.499260111
Short name T420
Test name
Test status
Simulation time 32242413 ps
CPU time 1.99 seconds
Started Jun 06 01:13:33 PM PDT 24
Finished Jun 06 01:13:36 PM PDT 24
Peak memory 218212 kb
Host smart-2940b665-f1df-4e45-8dff-044f3fac4fa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499260111 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_prog_failure.499260111
Directory /workspace/43.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_mubi.391103325
Short name T683
Test name
Test status
Simulation time 3877668946 ps
CPU time 16.78 seconds
Started Jun 06 01:13:41 PM PDT 24
Finished Jun 06 01:13:59 PM PDT 24
Peak memory 219980 kb
Host smart-7da0bdf0-662a-4ba5-8be1-c1f2b2e419e8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391103325 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_mubi.391103325
Directory /workspace/43.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_digest.3387256109
Short name T780
Test name
Test status
Simulation time 366677866 ps
CPU time 14.35 seconds
Started Jun 06 01:13:41 PM PDT 24
Finished Jun 06 01:13:57 PM PDT 24
Peak memory 217960 kb
Host smart-988050f7-c0d5-4f18-b5ca-cef5f913d8ad
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387256109 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_d
igest.3387256109
Directory /workspace/43.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_mux.1463906603
Short name T788
Test name
Test status
Simulation time 239763089 ps
CPU time 9.01 seconds
Started Jun 06 01:13:41 PM PDT 24
Finished Jun 06 01:13:51 PM PDT 24
Peak memory 218036 kb
Host smart-a10c789a-3048-4a53-a893-bb2011f9afc5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463906603 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_mux.
1463906603
Directory /workspace/43.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/43.lc_ctrl_security_escalation.3831315919
Short name T352
Test name
Test status
Simulation time 359594664 ps
CPU time 9.03 seconds
Started Jun 06 01:13:39 PM PDT 24
Finished Jun 06 01:13:49 PM PDT 24
Peak memory 218276 kb
Host smart-526a38dc-02c8-43dd-9901-55d2abdb4b03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831315919 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_security_escalation.3831315919
Directory /workspace/43.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/43.lc_ctrl_smoke.3583763657
Short name T836
Test name
Test status
Simulation time 58755072 ps
CPU time 1.85 seconds
Started Jun 06 01:13:37 PM PDT 24
Finished Jun 06 01:13:40 PM PDT 24
Peak memory 213808 kb
Host smart-ec0f6bfb-3452-4b3a-9465-1576fc9a5cf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583763657 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_smoke.3583763657
Directory /workspace/43.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_failure.2207849993
Short name T94
Test name
Test status
Simulation time 542866198 ps
CPU time 18.56 seconds
Started Jun 06 01:13:37 PM PDT 24
Finished Jun 06 01:13:57 PM PDT 24
Peak memory 250896 kb
Host smart-128fa1ea-066e-4d9f-81e8-42f7f5a7c083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207849993 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_failure.2207849993
Directory /workspace/43.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_post_trans.2180293877
Short name T280
Test name
Test status
Simulation time 42181485 ps
CPU time 5.96 seconds
Started Jun 06 01:13:31 PM PDT 24
Finished Jun 06 01:13:38 PM PDT 24
Peak memory 246948 kb
Host smart-a595a4c2-834a-4ae8-a664-c49c108144c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180293877 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_post_trans.2180293877
Directory /workspace/43.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all.267923339
Short name T328
Test name
Test status
Simulation time 18312146008 ps
CPU time 189.27 seconds
Started Jun 06 01:13:41 PM PDT 24
Finished Jun 06 01:16:52 PM PDT 24
Peak memory 251056 kb
Host smart-bfc894a1-e0b4-40c7-b87e-441d8a2d3008
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267923339 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.lc_ctrl_stress_all.267923339
Directory /workspace/43.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.lc_ctrl_volatile_unlock_smoke.61399314
Short name T173
Test name
Test status
Simulation time 15898688 ps
CPU time 0.81 seconds
Started Jun 06 01:13:31 PM PDT 24
Finished Jun 06 01:13:33 PM PDT 24
Peak memory 208496 kb
Host smart-36b4d4be-c592-46d4-9fe7-56b80ed5c8bb
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61399314 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vol
atile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctr
l_volatile_unlock_smoke.61399314
Directory /workspace/43.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_alert_test.1467468223
Short name T556
Test name
Test status
Simulation time 30347260 ps
CPU time 1.05 seconds
Started Jun 06 01:13:45 PM PDT 24
Finished Jun 06 01:13:48 PM PDT 24
Peak memory 208568 kb
Host smart-405458b5-b9fa-4bca-bd13-8c25fd1b1a4c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467468223 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_alert_test.1467468223
Directory /workspace/44.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.lc_ctrl_errors.2941968130
Short name T699
Test name
Test status
Simulation time 401717021 ps
CPU time 12.57 seconds
Started Jun 06 01:13:42 PM PDT 24
Finished Jun 06 01:13:56 PM PDT 24
Peak memory 217976 kb
Host smart-f1693a94-b886-4f93-b90c-e7587c61ec52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941968130 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_errors.2941968130
Directory /workspace/44.lc_ctrl_errors/latest

Test location /workspace/coverage/default/44.lc_ctrl_jtag_access.3286569849
Short name T462
Test name
Test status
Simulation time 1489851590 ps
CPU time 11.5 seconds
Started Jun 06 01:13:43 PM PDT 24
Finished Jun 06 01:13:56 PM PDT 24
Peak memory 217044 kb
Host smart-9b7d88ec-16db-4ca9-a06c-83c87b2cab6e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286569849 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_jtag_access.3286569849
Directory /workspace/44.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/44.lc_ctrl_prog_failure.2092091410
Short name T188
Test name
Test status
Simulation time 80073562 ps
CPU time 4.02 seconds
Started Jun 06 01:13:40 PM PDT 24
Finished Jun 06 01:13:45 PM PDT 24
Peak memory 218052 kb
Host smart-61c9d644-cdb8-4131-8e30-38522113e145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092091410 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_prog_failure.2092091410
Directory /workspace/44.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_mubi.2424876188
Short name T114
Test name
Test status
Simulation time 793161653 ps
CPU time 16.72 seconds
Started Jun 06 01:13:40 PM PDT 24
Finished Jun 06 01:13:57 PM PDT 24
Peak memory 226052 kb
Host smart-5776361d-1127-4dab-a07b-aba8c4670d35
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424876188 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_mubi.2424876188
Directory /workspace/44.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_digest.1806450618
Short name T308
Test name
Test status
Simulation time 328365729 ps
CPU time 11.99 seconds
Started Jun 06 01:13:53 PM PDT 24
Finished Jun 06 01:14:06 PM PDT 24
Peak memory 225384 kb
Host smart-ffee3991-7095-4f8c-9b31-c6dfc6d795c2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806450618 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_d
igest.1806450618
Directory /workspace/44.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_mux.1991967943
Short name T297
Test name
Test status
Simulation time 1440345961 ps
CPU time 10.45 seconds
Started Jun 06 01:13:40 PM PDT 24
Finished Jun 06 01:13:52 PM PDT 24
Peak memory 218096 kb
Host smart-d66335dd-c2f8-4633-95c6-09b643606e89
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991967943 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_mux.
1991967943
Directory /workspace/44.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/44.lc_ctrl_security_escalation.311837438
Short name T560
Test name
Test status
Simulation time 273359247 ps
CPU time 9.87 seconds
Started Jun 06 01:13:44 PM PDT 24
Finished Jun 06 01:13:56 PM PDT 24
Peak memory 217944 kb
Host smart-0efc911c-429d-4262-a655-419105c98cf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311837438 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_security_escalation.311837438
Directory /workspace/44.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/44.lc_ctrl_smoke.2212884635
Short name T742
Test name
Test status
Simulation time 60524745 ps
CPU time 3.49 seconds
Started Jun 06 01:13:40 PM PDT 24
Finished Jun 06 01:13:45 PM PDT 24
Peak memory 214484 kb
Host smart-6ae65111-6fd2-4b3f-8cf8-4e085fdb0aaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212884635 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_smoke.2212884635
Directory /workspace/44.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_failure.359159085
Short name T768
Test name
Test status
Simulation time 823003822 ps
CPU time 26.64 seconds
Started Jun 06 01:13:42 PM PDT 24
Finished Jun 06 01:14:10 PM PDT 24
Peak memory 250996 kb
Host smart-53a4ef48-1af7-4b5b-a9ea-165440d4de16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359159085 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_failure.359159085
Directory /workspace/44.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_stress_all.2654970900
Short name T490
Test name
Test status
Simulation time 34125678575 ps
CPU time 359.18 seconds
Started Jun 06 01:13:41 PM PDT 24
Finished Jun 06 01:19:41 PM PDT 24
Peak memory 276588 kb
Host smart-e9d6a3c7-40c3-4eb5-8a61-d14eb72a917f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654970900 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.lc_ctrl_stress_all.2654970900
Directory /workspace/44.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.lc_ctrl_stress_all_with_rand_reset.548277908
Short name T101
Test name
Test status
Simulation time 33477898250 ps
CPU time 1688.77 seconds
Started Jun 06 01:13:40 PM PDT 24
Finished Jun 06 01:41:51 PM PDT 24
Peak memory 905680 kb
Host smart-746670af-4861-48a1-b1aa-5c7403b4f39d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=548277908 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_stress_all_with_rand_reset.548277908
Directory /workspace/44.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.lc_ctrl_volatile_unlock_smoke.324149469
Short name T861
Test name
Test status
Simulation time 37452781 ps
CPU time 0.86 seconds
Started Jun 06 01:13:43 PM PDT 24
Finished Jun 06 01:13:46 PM PDT 24
Peak memory 211536 kb
Host smart-bf52fc7d-9b35-45c1-b5f4-8b3916d18fba
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324149469 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ct
rl_volatile_unlock_smoke.324149469
Directory /workspace/44.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_alert_test.3384718011
Short name T311
Test name
Test status
Simulation time 185753712 ps
CPU time 0.9 seconds
Started Jun 06 01:13:40 PM PDT 24
Finished Jun 06 01:13:42 PM PDT 24
Peak memory 208712 kb
Host smart-1748251b-0155-48fe-aec5-36aceb49be90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384718011 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_alert_test.3384718011
Directory /workspace/45.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.lc_ctrl_errors.2102981540
Short name T424
Test name
Test status
Simulation time 1716020506 ps
CPU time 10.66 seconds
Started Jun 06 01:13:41 PM PDT 24
Finished Jun 06 01:13:53 PM PDT 24
Peak memory 217952 kb
Host smart-0b727be9-e868-4313-ab59-f66dfc108808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102981540 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_errors.2102981540
Directory /workspace/45.lc_ctrl_errors/latest

Test location /workspace/coverage/default/45.lc_ctrl_jtag_access.1248009560
Short name T565
Test name
Test status
Simulation time 3180701772 ps
CPU time 5.76 seconds
Started Jun 06 01:13:40 PM PDT 24
Finished Jun 06 01:13:47 PM PDT 24
Peak memory 209532 kb
Host smart-ecd2aeb9-4e34-47e8-9b8d-78be2dd1d955
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248009560 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_jtag_access.1248009560
Directory /workspace/45.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/45.lc_ctrl_prog_failure.3949051525
Short name T567
Test name
Test status
Simulation time 60031901 ps
CPU time 3.23 seconds
Started Jun 06 01:13:40 PM PDT 24
Finished Jun 06 01:13:44 PM PDT 24
Peak memory 218016 kb
Host smart-9fbdeeb2-1ec0-4c13-8867-79fc863d7c52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949051525 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_prog_failure.3949051525
Directory /workspace/45.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_mubi.2282803881
Short name T649
Test name
Test status
Simulation time 395178841 ps
CPU time 17.65 seconds
Started Jun 06 01:13:41 PM PDT 24
Finished Jun 06 01:14:00 PM PDT 24
Peak memory 218864 kb
Host smart-9cd51e06-27e5-4930-870d-5d00ced2c209
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282803881 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_mubi.2282803881
Directory /workspace/45.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_digest.810000931
Short name T200
Test name
Test status
Simulation time 834820451 ps
CPU time 9 seconds
Started Jun 06 01:13:39 PM PDT 24
Finished Jun 06 01:13:49 PM PDT 24
Peak memory 217888 kb
Host smart-9270176a-c3be-4d1b-bf59-d22a9950a244
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810000931 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_di
gest.810000931
Directory /workspace/45.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_mux.117972958
Short name T333
Test name
Test status
Simulation time 1136250680 ps
CPU time 7.48 seconds
Started Jun 06 01:13:39 PM PDT 24
Finished Jun 06 01:13:47 PM PDT 24
Peak memory 217936 kb
Host smart-70d64315-4aac-47c9-8d9a-13a7071df1e4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117972958 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_mux.117972958
Directory /workspace/45.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/45.lc_ctrl_security_escalation.1524988574
Short name T643
Test name
Test status
Simulation time 1609626765 ps
CPU time 13.87 seconds
Started Jun 06 01:13:44 PM PDT 24
Finished Jun 06 01:13:59 PM PDT 24
Peak memory 218080 kb
Host smart-234932ea-6aef-4a3a-b878-5113b622ec74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524988574 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_security_escalation.1524988574
Directory /workspace/45.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/45.lc_ctrl_smoke.2311339715
Short name T630
Test name
Test status
Simulation time 60330183 ps
CPU time 3.29 seconds
Started Jun 06 01:13:42 PM PDT 24
Finished Jun 06 01:13:46 PM PDT 24
Peak memory 217684 kb
Host smart-de0badec-071e-4c69-a779-6b500d641a06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311339715 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_smoke.2311339715
Directory /workspace/45.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_failure.4271214011
Short name T289
Test name
Test status
Simulation time 947668581 ps
CPU time 29.99 seconds
Started Jun 06 01:13:42 PM PDT 24
Finished Jun 06 01:14:13 PM PDT 24
Peak memory 250916 kb
Host smart-371fae47-260f-4473-ae14-3eb09cf8df5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271214011 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_failure.4271214011
Directory /workspace/45.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_post_trans.2454813251
Short name T762
Test name
Test status
Simulation time 116348682 ps
CPU time 2.98 seconds
Started Jun 06 01:13:39 PM PDT 24
Finished Jun 06 01:13:42 PM PDT 24
Peak memory 222820 kb
Host smart-86782b50-db0a-4009-92a0-669dc754ab80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454813251 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_post_trans.2454813251
Directory /workspace/45.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/45.lc_ctrl_stress_all.3360537480
Short name T274
Test name
Test status
Simulation time 4782277959 ps
CPU time 95.15 seconds
Started Jun 06 01:13:39 PM PDT 24
Finished Jun 06 01:15:15 PM PDT 24
Peak memory 226148 kb
Host smart-543bdcf6-3fa9-4fe4-a203-7ae04cd2d70d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360537480 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.lc_ctrl_stress_all.3360537480
Directory /workspace/45.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.lc_ctrl_volatile_unlock_smoke.2234281461
Short name T260
Test name
Test status
Simulation time 15698654 ps
CPU time 0.81 seconds
Started Jun 06 01:13:38 PM PDT 24
Finished Jun 06 01:13:40 PM PDT 24
Peak memory 208516 kb
Host smart-469f4896-6a2e-4070-91f2-ecffa6432f7f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234281461 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_c
trl_volatile_unlock_smoke.2234281461
Directory /workspace/45.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_alert_test.2757814267
Short name T483
Test name
Test status
Simulation time 37385127 ps
CPU time 0.82 seconds
Started Jun 06 01:13:53 PM PDT 24
Finished Jun 06 01:13:55 PM PDT 24
Peak memory 208644 kb
Host smart-b14f7f53-642a-4867-b3eb-3ac4bffdf328
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757814267 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_alert_test.2757814267
Directory /workspace/46.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.lc_ctrl_errors.3169170297
Short name T51
Test name
Test status
Simulation time 344796560 ps
CPU time 13.74 seconds
Started Jun 06 01:13:52 PM PDT 24
Finished Jun 06 01:14:06 PM PDT 24
Peak memory 218016 kb
Host smart-a4dea83d-408e-44ef-b3ee-4528eed28bf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169170297 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_errors.3169170297
Directory /workspace/46.lc_ctrl_errors/latest

Test location /workspace/coverage/default/46.lc_ctrl_jtag_access.3424868205
Short name T803
Test name
Test status
Simulation time 346149799 ps
CPU time 3.04 seconds
Started Jun 06 01:13:57 PM PDT 24
Finished Jun 06 01:14:01 PM PDT 24
Peak memory 216996 kb
Host smart-0b4a4bf5-6030-4cfb-9503-f40cce70ec70
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424868205 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_jtag_access.3424868205
Directory /workspace/46.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/46.lc_ctrl_prog_failure.1371754000
Short name T849
Test name
Test status
Simulation time 88716539 ps
CPU time 3.28 seconds
Started Jun 06 01:13:52 PM PDT 24
Finished Jun 06 01:13:56 PM PDT 24
Peak memory 217976 kb
Host smart-02b2f541-4311-45a4-81db-975cb089080b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371754000 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_prog_failure.1371754000
Directory /workspace/46.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_mubi.2823855116
Short name T799
Test name
Test status
Simulation time 350910088 ps
CPU time 15.66 seconds
Started Jun 06 01:13:54 PM PDT 24
Finished Jun 06 01:14:11 PM PDT 24
Peak memory 218884 kb
Host smart-c884309b-ea2b-4abc-83e5-9b729014a7c3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823855116 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_mubi.2823855116
Directory /workspace/46.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_digest.1081650912
Short name T487
Test name
Test status
Simulation time 437658563 ps
CPU time 12.15 seconds
Started Jun 06 01:13:53 PM PDT 24
Finished Jun 06 01:14:06 PM PDT 24
Peak memory 217872 kb
Host smart-fd922312-213a-4884-a168-b929cdfb56d3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081650912 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_d
igest.1081650912
Directory /workspace/46.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_mux.1496496953
Short name T471
Test name
Test status
Simulation time 197000191 ps
CPU time 7.82 seconds
Started Jun 06 01:13:54 PM PDT 24
Finished Jun 06 01:14:03 PM PDT 24
Peak memory 218052 kb
Host smart-a97afa05-e599-452f-8a8d-5b48700b4aed
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496496953 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_mux.
1496496953
Directory /workspace/46.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/46.lc_ctrl_security_escalation.253683818
Short name T733
Test name
Test status
Simulation time 1558272027 ps
CPU time 15.11 seconds
Started Jun 06 01:13:53 PM PDT 24
Finished Jun 06 01:14:09 PM PDT 24
Peak memory 218024 kb
Host smart-90133fb5-739c-41a0-8e10-55360a83ea2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253683818 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_security_escalation.253683818
Directory /workspace/46.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/46.lc_ctrl_smoke.3299194121
Short name T43
Test name
Test status
Simulation time 60375935 ps
CPU time 3.55 seconds
Started Jun 06 01:13:39 PM PDT 24
Finished Jun 06 01:13:44 PM PDT 24
Peak memory 214308 kb
Host smart-82d00045-2e03-4d7d-8d95-9d1df581f5d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299194121 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_smoke.3299194121
Directory /workspace/46.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_failure.3928715583
Short name T719
Test name
Test status
Simulation time 1285167529 ps
CPU time 26.92 seconds
Started Jun 06 01:13:58 PM PDT 24
Finished Jun 06 01:14:26 PM PDT 24
Peak memory 251012 kb
Host smart-2f842b31-2090-469f-bd37-843b00942f89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928715583 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_failure.3928715583
Directory /workspace/46.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_post_trans.1766189580
Short name T692
Test name
Test status
Simulation time 46971018 ps
CPU time 6.67 seconds
Started Jun 06 01:13:58 PM PDT 24
Finished Jun 06 01:14:06 PM PDT 24
Peak memory 250500 kb
Host smart-381a3188-e11e-48a7-a9b3-48a497bd265d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766189580 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_post_trans.1766189580
Directory /workspace/46.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all.4038362387
Short name T550
Test name
Test status
Simulation time 9455380624 ps
CPU time 139.73 seconds
Started Jun 06 01:13:55 PM PDT 24
Finished Jun 06 01:16:16 PM PDT 24
Peak memory 229760 kb
Host smart-78c8636a-45a8-42be-8971-355a2855d2cf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038362387 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.lc_ctrl_stress_all.4038362387
Directory /workspace/46.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.lc_ctrl_volatile_unlock_smoke.1382672015
Short name T317
Test name
Test status
Simulation time 90120475 ps
CPU time 1.17 seconds
Started Jun 06 01:13:44 PM PDT 24
Finished Jun 06 01:13:46 PM PDT 24
Peak memory 212568 kb
Host smart-f8b28e5f-4209-46d9-b6d2-685bd44538ad
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382672015 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_c
trl_volatile_unlock_smoke.1382672015
Directory /workspace/46.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_alert_test.400840949
Short name T657
Test name
Test status
Simulation time 50353961 ps
CPU time 0.99 seconds
Started Jun 06 01:13:53 PM PDT 24
Finished Jun 06 01:13:55 PM PDT 24
Peak memory 208712 kb
Host smart-20b46255-ff8c-4116-ad5f-cc638480444e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400840949 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_alert_test.400840949
Directory /workspace/47.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.lc_ctrl_errors.2112177515
Short name T428
Test name
Test status
Simulation time 363760141 ps
CPU time 16.11 seconds
Started Jun 06 01:13:58 PM PDT 24
Finished Jun 06 01:14:15 PM PDT 24
Peak memory 218032 kb
Host smart-b95e4aa3-aad2-4c79-a389-2d8e741eb602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112177515 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_errors.2112177515
Directory /workspace/47.lc_ctrl_errors/latest

Test location /workspace/coverage/default/47.lc_ctrl_jtag_access.627741241
Short name T858
Test name
Test status
Simulation time 1058074581 ps
CPU time 7.41 seconds
Started Jun 06 01:13:55 PM PDT 24
Finished Jun 06 01:14:03 PM PDT 24
Peak memory 209512 kb
Host smart-849727ad-ce79-4086-960e-e24b3cb37d8a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627741241 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_jtag_access.627741241
Directory /workspace/47.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/47.lc_ctrl_prog_failure.1325512086
Short name T345
Test name
Test status
Simulation time 80785708 ps
CPU time 2.14 seconds
Started Jun 06 01:13:54 PM PDT 24
Finished Jun 06 01:13:58 PM PDT 24
Peak memory 217924 kb
Host smart-e9d51060-4239-420f-935f-876a94b644b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325512086 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_prog_failure.1325512086
Directory /workspace/47.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_mubi.2570700615
Short name T855
Test name
Test status
Simulation time 389945667 ps
CPU time 13.17 seconds
Started Jun 06 01:13:56 PM PDT 24
Finished Jun 06 01:14:11 PM PDT 24
Peak memory 226084 kb
Host smart-b3747522-3700-4b54-8172-410ce8ba003a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570700615 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_mubi.2570700615
Directory /workspace/47.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_digest.1651535947
Short name T438
Test name
Test status
Simulation time 1324486219 ps
CPU time 10.81 seconds
Started Jun 06 01:13:53 PM PDT 24
Finished Jun 06 01:14:04 PM PDT 24
Peak memory 217948 kb
Host smart-0810fea9-16a7-4226-b2a1-af3b7bb35233
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651535947 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_d
igest.1651535947
Directory /workspace/47.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_mux.1977315685
Short name T784
Test name
Test status
Simulation time 504144894 ps
CPU time 14.85 seconds
Started Jun 06 01:13:56 PM PDT 24
Finished Jun 06 01:14:12 PM PDT 24
Peak memory 218004 kb
Host smart-3366558f-2d48-4c9a-b145-285aa1c419d8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977315685 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_mux.
1977315685
Directory /workspace/47.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/47.lc_ctrl_security_escalation.1046936185
Short name T11
Test name
Test status
Simulation time 2429241780 ps
CPU time 8.79 seconds
Started Jun 06 01:13:55 PM PDT 24
Finished Jun 06 01:14:05 PM PDT 24
Peak memory 218128 kb
Host smart-738b152e-c1c1-4aab-85ca-f55541fe30c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046936185 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_security_escalation.1046936185
Directory /workspace/47.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/47.lc_ctrl_smoke.1946168453
Short name T795
Test name
Test status
Simulation time 47758275 ps
CPU time 1.11 seconds
Started Jun 06 01:13:55 PM PDT 24
Finished Jun 06 01:13:57 PM PDT 24
Peak memory 217732 kb
Host smart-6627f5f8-0458-4433-81e9-ec007011ecf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946168453 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_smoke.1946168453
Directory /workspace/47.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_failure.3467236194
Short name T475
Test name
Test status
Simulation time 465083150 ps
CPU time 18.59 seconds
Started Jun 06 01:13:53 PM PDT 24
Finished Jun 06 01:14:12 PM PDT 24
Peak memory 251008 kb
Host smart-95c182e2-af2f-4dd8-b065-fe3c6cdc568c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467236194 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_failure.3467236194
Directory /workspace/47.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_post_trans.3018631288
Short name T498
Test name
Test status
Simulation time 351559183 ps
CPU time 6.96 seconds
Started Jun 06 01:13:57 PM PDT 24
Finished Jun 06 01:14:05 PM PDT 24
Peak memory 250468 kb
Host smart-8cf51a19-4c5d-47a0-9af9-ed8d7b713a5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018631288 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_post_trans.3018631288
Directory /workspace/47.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/47.lc_ctrl_stress_all_with_rand_reset.1685060468
Short name T123
Test name
Test status
Simulation time 118713121766 ps
CPU time 987.76 seconds
Started Jun 06 01:13:54 PM PDT 24
Finished Jun 06 01:30:22 PM PDT 24
Peak memory 447664 kb
Host smart-259d9776-0320-4da1-9d1c-d752564891d1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1685060468 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_stress_all_with_rand_reset.1685060468
Directory /workspace/47.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.lc_ctrl_volatile_unlock_smoke.1415956584
Short name T656
Test name
Test status
Simulation time 21884370 ps
CPU time 0.78 seconds
Started Jun 06 01:13:54 PM PDT 24
Finished Jun 06 01:13:55 PM PDT 24
Peak memory 207772 kb
Host smart-59c83d70-d0cb-4466-ad93-c8d1de4e55fb
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415956584 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_c
trl_volatile_unlock_smoke.1415956584
Directory /workspace/47.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_alert_test.4274356836
Short name T603
Test name
Test status
Simulation time 26185246 ps
CPU time 1.35 seconds
Started Jun 06 01:13:56 PM PDT 24
Finished Jun 06 01:13:59 PM PDT 24
Peak memory 208824 kb
Host smart-1a143b4f-6ded-4646-b145-3ed59d3af7b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274356836 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_alert_test.4274356836
Directory /workspace/48.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.lc_ctrl_errors.3010808721
Short name T266
Test name
Test status
Simulation time 341094331 ps
CPU time 9.38 seconds
Started Jun 06 01:13:53 PM PDT 24
Finished Jun 06 01:14:03 PM PDT 24
Peak memory 217992 kb
Host smart-3caf83bb-0d34-45d5-8ded-c46dcab8ffb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010808721 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_errors.3010808721
Directory /workspace/48.lc_ctrl_errors/latest

Test location /workspace/coverage/default/48.lc_ctrl_jtag_access.1589495714
Short name T669
Test name
Test status
Simulation time 345634175 ps
CPU time 8.65 seconds
Started Jun 06 01:13:53 PM PDT 24
Finished Jun 06 01:14:02 PM PDT 24
Peak memory 209520 kb
Host smart-5726d94b-ae6e-4a85-8cc0-708873d368ce
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589495714 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_jtag_access.1589495714
Directory /workspace/48.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/48.lc_ctrl_prog_failure.2000500495
Short name T595
Test name
Test status
Simulation time 168568180 ps
CPU time 3.36 seconds
Started Jun 06 01:13:58 PM PDT 24
Finished Jun 06 01:14:02 PM PDT 24
Peak memory 218104 kb
Host smart-0d47ff9e-ecf9-4cf7-b413-6aaa6d465317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000500495 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_prog_failure.2000500495
Directory /workspace/48.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_mubi.2014031776
Short name T661
Test name
Test status
Simulation time 1438642365 ps
CPU time 16.7 seconds
Started Jun 06 01:13:55 PM PDT 24
Finished Jun 06 01:14:13 PM PDT 24
Peak memory 225708 kb
Host smart-cbb7a317-35c7-476f-a03b-fcba389e8637
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014031776 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_mubi.2014031776
Directory /workspace/48.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_digest.1055376783
Short name T398
Test name
Test status
Simulation time 1476799120 ps
CPU time 7.99 seconds
Started Jun 06 01:13:57 PM PDT 24
Finished Jun 06 01:14:05 PM PDT 24
Peak memory 217948 kb
Host smart-a87f5aa5-c7ba-49e3-afdd-7e447f857846
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055376783 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_d
igest.1055376783
Directory /workspace/48.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_mux.1007981778
Short name T824
Test name
Test status
Simulation time 311118625 ps
CPU time 7.91 seconds
Started Jun 06 01:13:54 PM PDT 24
Finished Jun 06 01:14:03 PM PDT 24
Peak memory 218016 kb
Host smart-d7a71c1c-899d-4679-aeda-04587ad136ab
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007981778 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_mux.
1007981778
Directory /workspace/48.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/48.lc_ctrl_security_escalation.3247949773
Short name T361
Test name
Test status
Simulation time 4471585979 ps
CPU time 12.28 seconds
Started Jun 06 01:13:58 PM PDT 24
Finished Jun 06 01:14:11 PM PDT 24
Peak memory 225844 kb
Host smart-fd66646d-5a7a-4ba7-8d88-c6ad2b01e2ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247949773 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_security_escalation.3247949773
Directory /workspace/48.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/48.lc_ctrl_smoke.1531804256
Short name T223
Test name
Test status
Simulation time 60540822 ps
CPU time 1.17 seconds
Started Jun 06 01:13:58 PM PDT 24
Finished Jun 06 01:14:00 PM PDT 24
Peak memory 213440 kb
Host smart-1b37161e-04d3-4f74-ab7d-72e8672aa746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531804256 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_smoke.1531804256
Directory /workspace/48.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_failure.3896072711
Short name T378
Test name
Test status
Simulation time 274582452 ps
CPU time 15.22 seconds
Started Jun 06 01:13:56 PM PDT 24
Finished Jun 06 01:14:12 PM PDT 24
Peak memory 251096 kb
Host smart-37811b13-5977-4c07-9d6e-f3ee8cda0304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896072711 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_failure.3896072711
Directory /workspace/48.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_post_trans.1092214039
Short name T406
Test name
Test status
Simulation time 319755727 ps
CPU time 6.89 seconds
Started Jun 06 01:13:54 PM PDT 24
Finished Jun 06 01:14:01 PM PDT 24
Peak memory 250384 kb
Host smart-ef6a624d-62ee-4ab4-8d46-cb0227ae5385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092214039 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_post_trans.1092214039
Directory /workspace/48.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all.154173754
Short name T332
Test name
Test status
Simulation time 134114514064 ps
CPU time 292.87 seconds
Started Jun 06 01:13:53 PM PDT 24
Finished Jun 06 01:18:46 PM PDT 24
Peak memory 283704 kb
Host smart-7d76ac23-0d62-4c3d-a9d7-face61799448
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154173754 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.lc_ctrl_stress_all.154173754
Directory /workspace/48.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.lc_ctrl_volatile_unlock_smoke.439437866
Short name T439
Test name
Test status
Simulation time 44945255 ps
CPU time 0.99 seconds
Started Jun 06 01:13:55 PM PDT 24
Finished Jun 06 01:13:57 PM PDT 24
Peak memory 211544 kb
Host smart-a0ed59c7-30d4-452b-b58a-f8bdef9d4e4a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439437866 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ct
rl_volatile_unlock_smoke.439437866
Directory /workspace/48.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_alert_test.3425725325
Short name T75
Test name
Test status
Simulation time 36479801 ps
CPU time 1.1 seconds
Started Jun 06 01:14:04 PM PDT 24
Finished Jun 06 01:14:06 PM PDT 24
Peak memory 208552 kb
Host smart-4368038c-3223-46e6-aa2f-4145c6975619
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425725325 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_alert_test.3425725325
Directory /workspace/49.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.lc_ctrl_errors.1133516118
Short name T581
Test name
Test status
Simulation time 242832218 ps
CPU time 12.04 seconds
Started Jun 06 01:14:05 PM PDT 24
Finished Jun 06 01:14:19 PM PDT 24
Peak memory 218060 kb
Host smart-6cc2884b-bcc0-472a-b4c1-68b967249694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133516118 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_errors.1133516118
Directory /workspace/49.lc_ctrl_errors/latest

Test location /workspace/coverage/default/49.lc_ctrl_jtag_access.548906532
Short name T413
Test name
Test status
Simulation time 910655020 ps
CPU time 20.61 seconds
Started Jun 06 01:14:02 PM PDT 24
Finished Jun 06 01:14:24 PM PDT 24
Peak memory 217028 kb
Host smart-030a84dc-d792-4ff5-a5a8-1b535559f93e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548906532 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_jtag_access.548906532
Directory /workspace/49.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/49.lc_ctrl_prog_failure.1443445868
Short name T238
Test name
Test status
Simulation time 110926848 ps
CPU time 4.65 seconds
Started Jun 06 01:14:01 PM PDT 24
Finished Jun 06 01:14:06 PM PDT 24
Peak memory 217928 kb
Host smart-5a744bb3-3271-418e-bf37-b1da38ee71a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443445868 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_prog_failure.1443445868
Directory /workspace/49.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_mubi.3038005962
Short name T353
Test name
Test status
Simulation time 1556079638 ps
CPU time 13.48 seconds
Started Jun 06 01:14:04 PM PDT 24
Finished Jun 06 01:14:19 PM PDT 24
Peak memory 218928 kb
Host smart-89203164-fa5f-4e39-9508-7002009efb17
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038005962 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_mubi.3038005962
Directory /workspace/49.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_digest.456473828
Short name T778
Test name
Test status
Simulation time 1190196951 ps
CPU time 12.31 seconds
Started Jun 06 01:14:03 PM PDT 24
Finished Jun 06 01:14:17 PM PDT 24
Peak memory 217956 kb
Host smart-e641dbe4-ff14-44ac-873b-319e37f154b5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456473828 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_di
gest.456473828
Directory /workspace/49.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_mux.844431671
Short name T395
Test name
Test status
Simulation time 1461104549 ps
CPU time 8.87 seconds
Started Jun 06 01:14:03 PM PDT 24
Finished Jun 06 01:14:13 PM PDT 24
Peak memory 217964 kb
Host smart-68d91b84-c642-47cf-aa2d-12a84d4e1294
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844431671 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_mux.844431671
Directory /workspace/49.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/49.lc_ctrl_security_escalation.3193137453
Short name T418
Test name
Test status
Simulation time 2379556699 ps
CPU time 13.25 seconds
Started Jun 06 01:14:04 PM PDT 24
Finished Jun 06 01:14:18 PM PDT 24
Peak memory 218116 kb
Host smart-6aaa5efb-0b0f-41e7-b2ba-71d951aa8ae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193137453 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_security_escalation.3193137453
Directory /workspace/49.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/49.lc_ctrl_smoke.664184493
Short name T32
Test name
Test status
Simulation time 54202648 ps
CPU time 2.59 seconds
Started Jun 06 01:13:53 PM PDT 24
Finished Jun 06 01:13:56 PM PDT 24
Peak memory 214192 kb
Host smart-555d5785-ce20-4d2e-9592-51235817c46c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664184493 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_smoke.664184493
Directory /workspace/49.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_failure.74878279
Short name T466
Test name
Test status
Simulation time 550505383 ps
CPU time 24.14 seconds
Started Jun 06 01:14:02 PM PDT 24
Finished Jun 06 01:14:28 PM PDT 24
Peak memory 250992 kb
Host smart-0833efb7-1260-48d0-a9bb-d0dbf7c36848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74878279 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_failure.74878279
Directory /workspace/49.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_post_trans.864516552
Short name T531
Test name
Test status
Simulation time 126895627 ps
CPU time 7.78 seconds
Started Jun 06 01:14:03 PM PDT 24
Finished Jun 06 01:14:12 PM PDT 24
Peak memory 250744 kb
Host smart-31514b47-d08c-42d2-a6e1-ba31f8ecd04e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864516552 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_post_trans.864516552
Directory /workspace/49.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/49.lc_ctrl_stress_all.1142068310
Short name T522
Test name
Test status
Simulation time 29860045047 ps
CPU time 132.55 seconds
Started Jun 06 01:14:04 PM PDT 24
Finished Jun 06 01:16:18 PM PDT 24
Peak memory 251564 kb
Host smart-ca5d206b-48bd-43ad-8c87-16a80cebd26b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142068310 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.lc_ctrl_stress_all.1142068310
Directory /workspace/49.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.lc_ctrl_volatile_unlock_smoke.697020123
Short name T180
Test name
Test status
Simulation time 31526580 ps
CPU time 0.82 seconds
Started Jun 06 01:14:04 PM PDT 24
Finished Jun 06 01:14:06 PM PDT 24
Peak memory 207836 kb
Host smart-e7138ed7-984f-4ae9-a447-3ffd29a5620a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697020123 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ct
rl_volatile_unlock_smoke.697020123
Directory /workspace/49.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_alert_test.3720938501
Short name T492
Test name
Test status
Simulation time 15378251 ps
CPU time 1 seconds
Started Jun 06 01:10:22 PM PDT 24
Finished Jun 06 01:10:24 PM PDT 24
Peak memory 208684 kb
Host smart-4422f81d-3daf-43e3-a05d-6e98ca91ea46
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720938501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_alert_test.3720938501
Directory /workspace/5.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.lc_ctrl_claim_transition_if.674016814
Short name T227
Test name
Test status
Simulation time 33871240 ps
CPU time 0.88 seconds
Started Jun 06 01:10:11 PM PDT 24
Finished Jun 06 01:10:13 PM PDT 24
Peak memory 208624 kb
Host smart-5348a12b-2b9b-4164-9ab7-e54fb37fe7c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674016814 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_claim_transition_if.674016814
Directory /workspace/5.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/5.lc_ctrl_errors.1498863561
Short name T747
Test name
Test status
Simulation time 203480471 ps
CPU time 8.4 seconds
Started Jun 06 01:10:14 PM PDT 24
Finished Jun 06 01:10:23 PM PDT 24
Peak memory 217996 kb
Host smart-24cce05b-c322-4236-8ac3-fb366a60ee2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498863561 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_errors.1498863561
Directory /workspace/5.lc_ctrl_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_errors.2356568105
Short name T809
Test name
Test status
Simulation time 8930648926 ps
CPU time 68.92 seconds
Started Jun 06 01:10:09 PM PDT 24
Finished Jun 06 01:11:19 PM PDT 24
Peak memory 219464 kb
Host smart-5dd1e8df-998e-4a57-9e74-88230adc178e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356568105 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_er
rors.2356568105
Directory /workspace/5.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_priority.3709265182
Short name T816
Test name
Test status
Simulation time 452070358 ps
CPU time 2.03 seconds
Started Jun 06 01:10:11 PM PDT 24
Finished Jun 06 01:10:14 PM PDT 24
Peak memory 217180 kb
Host smart-e5156c37-c0f9-4c23-b360-28ad172ca1bb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709265182 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_priority.3
709265182
Directory /workspace/5.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_prog_failure.2985630579
Short name T360
Test name
Test status
Simulation time 288794820 ps
CPU time 5.38 seconds
Started Jun 06 01:10:12 PM PDT 24
Finished Jun 06 01:10:19 PM PDT 24
Peak memory 217904 kb
Host smart-bc7cb6f7-b49e-48fb-b556-144b63254e4b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985630579 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag
_prog_failure.2985630579
Directory /workspace/5.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_regwen_during_op.947102495
Short name T87
Test name
Test status
Simulation time 3456348163 ps
CPU time 15.35 seconds
Started Jun 06 01:10:23 PM PDT 24
Finished Jun 06 01:10:39 PM PDT 24
Peak memory 217804 kb
Host smart-66d1d54b-6b21-481f-9f58-50b19f242c74
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947102495 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_j
tag_regwen_during_op.947102495
Directory /workspace/5.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_smoke.3980086104
Short name T174
Test name
Test status
Simulation time 681841168 ps
CPU time 15.26 seconds
Started Jun 06 01:10:24 PM PDT 24
Finished Jun 06 01:10:40 PM PDT 24
Peak memory 217536 kb
Host smart-216e6948-e92e-4b4c-ba4e-95c2f33fa9d4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980086104 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_smoke.
3980086104
Directory /workspace/5.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_post_trans.122414615
Short name T4
Test name
Test status
Simulation time 779570092 ps
CPU time 13.43 seconds
Started Jun 06 01:10:11 PM PDT 24
Finished Jun 06 01:10:25 PM PDT 24
Peak memory 251136 kb
Host smart-e004072c-71ab-4f1d-8e29-fa7b446da106
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122414615 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_j
tag_state_post_trans.122414615
Directory /workspace/5.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_prog_failure.3146118632
Short name T13
Test name
Test status
Simulation time 94715924 ps
CPU time 2.42 seconds
Started Jun 06 01:10:11 PM PDT 24
Finished Jun 06 01:10:15 PM PDT 24
Peak memory 218032 kb
Host smart-f2c32e5a-3484-45ce-92e9-69a92eea28e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146118632 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_prog_failure.3146118632
Directory /workspace/5.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_regwen_during_op.3190959750
Short name T363
Test name
Test status
Simulation time 268827598 ps
CPU time 11.44 seconds
Started Jun 06 01:10:11 PM PDT 24
Finished Jun 06 01:10:24 PM PDT 24
Peak memory 217708 kb
Host smart-866afeee-805c-4aca-a478-34e35460d134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190959750 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_regwen_during_op.3190959750
Directory /workspace/5.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_mubi.2851305399
Short name T508
Test name
Test status
Simulation time 618571500 ps
CPU time 13.17 seconds
Started Jun 06 01:10:23 PM PDT 24
Finished Jun 06 01:10:37 PM PDT 24
Peak memory 218892 kb
Host smart-fa530e57-ff14-40bb-8fa2-3774e18341d7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851305399 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_mubi.2851305399
Directory /workspace/5.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_digest.409291891
Short name T364
Test name
Test status
Simulation time 1384984827 ps
CPU time 9.4 seconds
Started Jun 06 01:10:23 PM PDT 24
Finished Jun 06 01:10:33 PM PDT 24
Peak memory 226044 kb
Host smart-85b04cb4-8b09-4968-8e53-410495dbed15
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409291891 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_dig
est.409291891
Directory /workspace/5.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_mux.407616470
Short name T813
Test name
Test status
Simulation time 477967347 ps
CPU time 8.35 seconds
Started Jun 06 01:10:26 PM PDT 24
Finished Jun 06 01:10:35 PM PDT 24
Peak memory 218000 kb
Host smart-ef872b0c-ba60-454d-b267-9ab38b130b17
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407616470 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_mux.407616470
Directory /workspace/5.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/5.lc_ctrl_security_escalation.4080662155
Short name T465
Test name
Test status
Simulation time 261977092 ps
CPU time 11.3 seconds
Started Jun 06 01:10:12 PM PDT 24
Finished Jun 06 01:10:25 PM PDT 24
Peak memory 218216 kb
Host smart-551c2fb9-ede6-41d3-9376-e5e7df421235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080662155 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_security_escalation.4080662155
Directory /workspace/5.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/5.lc_ctrl_smoke.1345087981
Short name T640
Test name
Test status
Simulation time 264209843 ps
CPU time 1.9 seconds
Started Jun 06 01:10:12 PM PDT 24
Finished Jun 06 01:10:15 PM PDT 24
Peak memory 217740 kb
Host smart-f9f182a8-59a7-4159-a1c7-d311ccde5d7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345087981 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_smoke.1345087981
Directory /workspace/5.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_failure.1854333087
Short name T651
Test name
Test status
Simulation time 1111692015 ps
CPU time 30.89 seconds
Started Jun 06 01:10:13 PM PDT 24
Finished Jun 06 01:10:45 PM PDT 24
Peak memory 251024 kb
Host smart-2c1c21ea-88c0-4c9a-b86f-fcba13e24209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854333087 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_failure.1854333087
Directory /workspace/5.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_post_trans.3552566028
Short name T272
Test name
Test status
Simulation time 168903827 ps
CPU time 8.17 seconds
Started Jun 06 01:10:11 PM PDT 24
Finished Jun 06 01:10:20 PM PDT 24
Peak memory 246576 kb
Host smart-3e61caae-9cd2-478c-a739-782179108e98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552566028 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_post_trans.3552566028
Directory /workspace/5.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_stress_all.970719059
Short name T543
Test name
Test status
Simulation time 7168148893 ps
CPU time 78.93 seconds
Started Jun 06 01:10:22 PM PDT 24
Finished Jun 06 01:11:42 PM PDT 24
Peak memory 246860 kb
Host smart-50f417b4-8f19-4463-8ead-87dd31c5fd45
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970719059 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.lc_ctrl_stress_all.970719059
Directory /workspace/5.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.lc_ctrl_stress_all_with_rand_reset.615983076
Short name T78
Test name
Test status
Simulation time 31867571008 ps
CPU time 1053.44 seconds
Started Jun 06 01:10:25 PM PDT 24
Finished Jun 06 01:28:00 PM PDT 24
Peak memory 610916 kb
Host smart-2001cbb1-cad8-4dca-8792-d9c59cbdae2c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=615983076 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_stress_all_with_rand_reset.615983076
Directory /workspace/5.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.lc_ctrl_volatile_unlock_smoke.3765496782
Short name T89
Test name
Test status
Simulation time 23555908 ps
CPU time 0.91 seconds
Started Jun 06 01:10:11 PM PDT 24
Finished Jun 06 01:10:13 PM PDT 24
Peak memory 211468 kb
Host smart-373900e2-3b1f-45b3-9eff-6bd127323e23
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765496782 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ct
rl_volatile_unlock_smoke.3765496782
Directory /workspace/5.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_alert_test.3551468238
Short name T752
Test name
Test status
Simulation time 48535954 ps
CPU time 0.83 seconds
Started Jun 06 01:10:31 PM PDT 24
Finished Jun 06 01:10:33 PM PDT 24
Peak memory 208436 kb
Host smart-fe204b57-952d-406a-9226-cd6c22a511c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551468238 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_alert_test.3551468238
Directory /workspace/6.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.lc_ctrl_claim_transition_if.1153973965
Short name T232
Test name
Test status
Simulation time 11478404 ps
CPU time 0.8 seconds
Started Jun 06 01:10:24 PM PDT 24
Finished Jun 06 01:10:26 PM PDT 24
Peak memory 208668 kb
Host smart-d114a88d-8014-49d8-964f-2094de5b4499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153973965 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_claim_transition_if.1153973965
Directory /workspace/6.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/6.lc_ctrl_errors.617916838
Short name T509
Test name
Test status
Simulation time 450702326 ps
CPU time 18.87 seconds
Started Jun 06 01:10:23 PM PDT 24
Finished Jun 06 01:10:43 PM PDT 24
Peak memory 217984 kb
Host smart-ee327866-9c37-43d6-9ab6-522ab1226c32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617916838 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_errors.617916838
Directory /workspace/6.lc_ctrl_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_access.3287184544
Short name T6
Test name
Test status
Simulation time 3002016245 ps
CPU time 6.66 seconds
Started Jun 06 01:10:33 PM PDT 24
Finished Jun 06 01:10:40 PM PDT 24
Peak memory 209644 kb
Host smart-c8cd4465-5927-49d2-b0ce-679c0e728ed9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287184544 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_access.3287184544
Directory /workspace/6.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_errors.3957906275
Short name T689
Test name
Test status
Simulation time 946423968 ps
CPU time 21.24 seconds
Started Jun 06 01:10:33 PM PDT 24
Finished Jun 06 01:10:55 PM PDT 24
Peak memory 217948 kb
Host smart-d7b610cc-9786-467d-b480-ec9482d16775
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957906275 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_er
rors.3957906275
Directory /workspace/6.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_priority.770515638
Short name T485
Test name
Test status
Simulation time 1877876932 ps
CPU time 11.91 seconds
Started Jun 06 01:10:31 PM PDT 24
Finished Jun 06 01:10:44 PM PDT 24
Peak memory 217732 kb
Host smart-4b4f0c88-69eb-4bcf-8e03-942cd4234240
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770515638 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_priority.770515638
Directory /workspace/6.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_prog_failure.2795045182
Short name T580
Test name
Test status
Simulation time 385701592 ps
CPU time 5.92 seconds
Started Jun 06 01:10:23 PM PDT 24
Finished Jun 06 01:10:30 PM PDT 24
Peak memory 217964 kb
Host smart-57400cf0-fdf6-4487-8612-5a2daeef49c0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795045182 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag
_prog_failure.2795045182
Directory /workspace/6.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_regwen_during_op.3564826340
Short name T17
Test name
Test status
Simulation time 8711013421 ps
CPU time 37.4 seconds
Started Jun 06 01:10:33 PM PDT 24
Finished Jun 06 01:11:11 PM PDT 24
Peak memory 217700 kb
Host smart-956415e8-345a-4a24-9717-c5e3fb297a71
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564826340 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_regwen_during_op.3564826340
Directory /workspace/6.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_smoke.454986311
Short name T761
Test name
Test status
Simulation time 646145037 ps
CPU time 18.02 seconds
Started Jun 06 01:10:23 PM PDT 24
Finished Jun 06 01:10:42 PM PDT 24
Peak memory 217668 kb
Host smart-47bffbcb-84d1-470e-b576-9a26d40adfe1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454986311 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_smoke.454986311
Directory /workspace/6.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_failure.455993996
Short name T286
Test name
Test status
Simulation time 7516451641 ps
CPU time 70.43 seconds
Started Jun 06 01:10:24 PM PDT 24
Finished Jun 06 01:11:35 PM PDT 24
Peak memory 250952 kb
Host smart-d3ab1a13-83ba-4c02-b922-0618cae81400
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455993996 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag
_state_failure.455993996
Directory /workspace/6.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_post_trans.260457813
Short name T19
Test name
Test status
Simulation time 1069403794 ps
CPU time 12.79 seconds
Started Jun 06 01:10:53 PM PDT 24
Finished Jun 06 01:11:06 PM PDT 24
Peak memory 250968 kb
Host smart-b01840b2-f1f2-43ec-a6d0-7d64dd880bba
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260457813 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_j
tag_state_post_trans.260457813
Directory /workspace/6.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_prog_failure.629780286
Short name T269
Test name
Test status
Simulation time 23589539 ps
CPU time 2 seconds
Started Jun 06 01:10:23 PM PDT 24
Finished Jun 06 01:10:26 PM PDT 24
Peak memory 217992 kb
Host smart-dac71623-7666-4ee2-972d-b1529f8206e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629780286 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_prog_failure.629780286
Directory /workspace/6.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_regwen_during_op.3456854669
Short name T789
Test name
Test status
Simulation time 406202981 ps
CPU time 9.82 seconds
Started Jun 06 01:10:22 PM PDT 24
Finished Jun 06 01:10:33 PM PDT 24
Peak memory 214076 kb
Host smart-bce20679-1b5c-450f-b2cf-871455ef4130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456854669 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_regwen_during_op.3456854669
Directory /workspace/6.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_mubi.390908083
Short name T108
Test name
Test status
Simulation time 1256045047 ps
CPU time 14.47 seconds
Started Jun 06 01:10:33 PM PDT 24
Finished Jun 06 01:10:49 PM PDT 24
Peak memory 218980 kb
Host smart-717c8054-005f-4dd8-8d9a-41747a82da6c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390908083 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_mubi.390908083
Directory /workspace/6.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_digest.2970346652
Short name T41
Test name
Test status
Simulation time 635462368 ps
CPU time 11.27 seconds
Started Jun 06 01:10:32 PM PDT 24
Finished Jun 06 01:10:44 PM PDT 24
Peak memory 217972 kb
Host smart-7db645c8-442e-4c0b-907d-28c0199d8add
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970346652 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_di
gest.2970346652
Directory /workspace/6.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_mux.2841376427
Short name T838
Test name
Test status
Simulation time 908298133 ps
CPU time 6.64 seconds
Started Jun 06 01:10:33 PM PDT 24
Finished Jun 06 01:10:40 PM PDT 24
Peak memory 218064 kb
Host smart-e38c9297-997d-4a33-b0bc-afe5f19894c8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841376427 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_mux.2
841376427
Directory /workspace/6.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/6.lc_ctrl_security_escalation.2472802306
Short name T539
Test name
Test status
Simulation time 545306257 ps
CPU time 18.58 seconds
Started Jun 06 01:10:24 PM PDT 24
Finished Jun 06 01:10:43 PM PDT 24
Peak memory 218088 kb
Host smart-65656e4d-bec9-4217-b51e-a4bb32c4b618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472802306 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_security_escalation.2472802306
Directory /workspace/6.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/6.lc_ctrl_smoke.2130061465
Short name T526
Test name
Test status
Simulation time 34975540 ps
CPU time 2.8 seconds
Started Jun 06 01:10:23 PM PDT 24
Finished Jun 06 01:10:27 PM PDT 24
Peak memory 214544 kb
Host smart-f0c3161e-a0af-4954-abca-f073485dea39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130061465 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_smoke.2130061465
Directory /workspace/6.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_failure.218050562
Short name T455
Test name
Test status
Simulation time 1248982143 ps
CPU time 32.25 seconds
Started Jun 06 01:10:24 PM PDT 24
Finished Jun 06 01:10:57 PM PDT 24
Peak memory 250960 kb
Host smart-64b55de7-e48a-43f8-8281-88377f149d54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218050562 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_failure.218050562
Directory /workspace/6.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_post_trans.3603719192
Short name T419
Test name
Test status
Simulation time 357584128 ps
CPU time 3.45 seconds
Started Jun 06 01:10:24 PM PDT 24
Finished Jun 06 01:10:28 PM PDT 24
Peak memory 222280 kb
Host smart-372f0879-35c8-4f23-878b-159fa16d5c9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603719192 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_post_trans.3603719192
Directory /workspace/6.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all.1778303406
Short name T252
Test name
Test status
Simulation time 10237818960 ps
CPU time 122.53 seconds
Started Jun 06 01:10:33 PM PDT 24
Finished Jun 06 01:12:36 PM PDT 24
Peak memory 251044 kb
Host smart-19e165d0-e3e7-45ed-9a09-7353f6e8228e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778303406 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.lc_ctrl_stress_all.1778303406
Directory /workspace/6.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.lc_ctrl_volatile_unlock_smoke.1978652801
Short name T112
Test name
Test status
Simulation time 15649518 ps
CPU time 0.94 seconds
Started Jun 06 01:10:23 PM PDT 24
Finished Jun 06 01:10:25 PM PDT 24
Peak memory 212456 kb
Host smart-7feb8b11-d90a-4fc0-84b0-f2b4f0e4a67a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978652801 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ct
rl_volatile_unlock_smoke.1978652801
Directory /workspace/6.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_alert_test.3594794713
Short name T785
Test name
Test status
Simulation time 43332591 ps
CPU time 1 seconds
Started Jun 06 01:10:46 PM PDT 24
Finished Jun 06 01:10:48 PM PDT 24
Peak memory 209480 kb
Host smart-05d65622-c6cc-4726-abaa-0db7049c6776
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594794713 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_alert_test.3594794713
Directory /workspace/7.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.lc_ctrl_errors.4033075307
Short name T751
Test name
Test status
Simulation time 1683933138 ps
CPU time 17.65 seconds
Started Jun 06 01:10:35 PM PDT 24
Finished Jun 06 01:10:54 PM PDT 24
Peak memory 217972 kb
Host smart-0255b29f-afcd-402f-828a-09caced5507b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033075307 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_errors.4033075307
Directory /workspace/7.lc_ctrl_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_access.3671251613
Short name T427
Test name
Test status
Simulation time 318577214 ps
CPU time 3.57 seconds
Started Jun 06 01:10:45 PM PDT 24
Finished Jun 06 01:10:49 PM PDT 24
Peak memory 209392 kb
Host smart-5664f2ec-b1e7-4c37-a188-849b06b59040
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671251613 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_access.3671251613
Directory /workspace/7.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_errors.3887884172
Short name T711
Test name
Test status
Simulation time 1127118397 ps
CPU time 32.87 seconds
Started Jun 06 01:10:44 PM PDT 24
Finished Jun 06 01:11:18 PM PDT 24
Peak memory 217672 kb
Host smart-86c6c3cc-6a3e-4622-af63-5eaadfcae9a7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887884172 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_er
rors.3887884172
Directory /workspace/7.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_priority.4029685312
Short name T383
Test name
Test status
Simulation time 650137366 ps
CPU time 9.31 seconds
Started Jun 06 01:10:41 PM PDT 24
Finished Jun 06 01:10:51 PM PDT 24
Peak memory 217000 kb
Host smart-e6302eb1-d919-44ab-822b-18d757651805
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029685312 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_priority.4
029685312
Directory /workspace/7.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_prog_failure.1756299388
Short name T588
Test name
Test status
Simulation time 446860020 ps
CPU time 12.15 seconds
Started Jun 06 01:10:44 PM PDT 24
Finished Jun 06 01:10:57 PM PDT 24
Peak memory 217828 kb
Host smart-6db23592-4b18-462d-98f5-7338224ac1e1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756299388 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag
_prog_failure.1756299388
Directory /workspace/7.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_regwen_during_op.600122069
Short name T88
Test name
Test status
Simulation time 1237357901 ps
CPU time 34.47 seconds
Started Jun 06 01:10:39 PM PDT 24
Finished Jun 06 01:11:14 PM PDT 24
Peak memory 217600 kb
Host smart-87765206-fcdd-498e-8032-f8fafd6c4cc0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600122069 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_j
tag_regwen_during_op.600122069
Directory /workspace/7.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_smoke.2437634368
Short name T631
Test name
Test status
Simulation time 208669449 ps
CPU time 1.97 seconds
Started Jun 06 01:10:44 PM PDT 24
Finished Jun 06 01:10:47 PM PDT 24
Peak memory 217424 kb
Host smart-37a3cc51-af4b-48e9-b2c2-cacb60f943a3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437634368 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_smoke.
2437634368
Directory /workspace/7.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_failure.4205767752
Short name T548
Test name
Test status
Simulation time 2029961505 ps
CPU time 42.73 seconds
Started Jun 06 01:10:31 PM PDT 24
Finished Jun 06 01:11:15 PM PDT 24
Peak memory 250924 kb
Host smart-fa4d467e-421d-40e8-927e-1872d9095c7a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205767752 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jta
g_state_failure.4205767752
Directory /workspace/7.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_post_trans.2300747704
Short name T793
Test name
Test status
Simulation time 2063064709 ps
CPU time 21.77 seconds
Started Jun 06 01:10:31 PM PDT 24
Finished Jun 06 01:10:54 PM PDT 24
Peak memory 250500 kb
Host smart-31791fff-a10f-4f71-82f8-bacd13fe1d7d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300747704 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_state_post_trans.2300747704
Directory /workspace/7.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_prog_failure.2373291689
Short name T695
Test name
Test status
Simulation time 132836327 ps
CPU time 1.85 seconds
Started Jun 06 01:10:35 PM PDT 24
Finished Jun 06 01:10:37 PM PDT 24
Peak memory 217976 kb
Host smart-7454734d-e000-47ce-9618-bf8cff6ca9c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373291689 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_prog_failure.2373291689
Directory /workspace/7.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_regwen_during_op.1844471386
Short name T401
Test name
Test status
Simulation time 337590817 ps
CPU time 18.66 seconds
Started Jun 06 01:10:33 PM PDT 24
Finished Jun 06 01:10:53 PM PDT 24
Peak memory 217708 kb
Host smart-842c4bd8-a9da-4795-b618-0316302ba7cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844471386 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_regwen_during_op.1844471386
Directory /workspace/7.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_mubi.2034591083
Short name T306
Test name
Test status
Simulation time 1197339662 ps
CPU time 9.17 seconds
Started Jun 06 01:10:39 PM PDT 24
Finished Jun 06 01:10:49 PM PDT 24
Peak memory 218212 kb
Host smart-c67392ef-ce59-49dc-82a6-edfd6c286ba3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034591083 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_mubi.2034591083
Directory /workspace/7.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_digest.4129131546
Short name T668
Test name
Test status
Simulation time 1259991888 ps
CPU time 16.01 seconds
Started Jun 06 01:10:44 PM PDT 24
Finished Jun 06 01:11:00 PM PDT 24
Peak memory 225580 kb
Host smart-d8f83632-1cb5-42c0-95f1-592aac1a76a5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129131546 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_di
gest.4129131546
Directory /workspace/7.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_mux.473193820
Short name T873
Test name
Test status
Simulation time 1586751702 ps
CPU time 10.2 seconds
Started Jun 06 01:10:42 PM PDT 24
Finished Jun 06 01:10:53 PM PDT 24
Peak memory 217988 kb
Host smart-026e673a-c251-4af3-86b4-0c284976f534
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473193820 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_mux.473193820
Directory /workspace/7.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/7.lc_ctrl_security_escalation.3131065395
Short name T713
Test name
Test status
Simulation time 274660057 ps
CPU time 7.71 seconds
Started Jun 06 01:10:34 PM PDT 24
Finished Jun 06 01:10:42 PM PDT 24
Peak memory 218064 kb
Host smart-3e8dbdac-d71d-4483-af88-afe058b150cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131065395 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_security_escalation.3131065395
Directory /workspace/7.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/7.lc_ctrl_smoke.1701130615
Short name T321
Test name
Test status
Simulation time 178957426 ps
CPU time 3.44 seconds
Started Jun 06 01:10:32 PM PDT 24
Finished Jun 06 01:10:36 PM PDT 24
Peak memory 218136 kb
Host smart-bd1d039f-4d2c-47fb-8050-5340b2eb2067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701130615 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_smoke.1701130615
Directory /workspace/7.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_failure.145991673
Short name T122
Test name
Test status
Simulation time 287820921 ps
CPU time 33.01 seconds
Started Jun 06 01:10:30 PM PDT 24
Finished Jun 06 01:11:04 PM PDT 24
Peak memory 250972 kb
Host smart-e2eb10b6-6b47-4786-a20c-9077a70f44ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145991673 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_failure.145991673
Directory /workspace/7.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_post_trans.4019892783
Short name T596
Test name
Test status
Simulation time 295149772 ps
CPU time 9.43 seconds
Started Jun 06 01:10:32 PM PDT 24
Finished Jun 06 01:10:42 PM PDT 24
Peak memory 251004 kb
Host smart-f1880ef9-cf9c-483d-9733-86c235303a44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019892783 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_post_trans.4019892783
Directory /workspace/7.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_stress_all.2565358994
Short name T479
Test name
Test status
Simulation time 9645242406 ps
CPU time 77.2 seconds
Started Jun 06 01:10:41 PM PDT 24
Finished Jun 06 01:12:00 PM PDT 24
Peak memory 268664 kb
Host smart-d2a7106d-c315-4dbe-a26d-bc3031facdcf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565358994 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.lc_ctrl_stress_all.2565358994
Directory /workspace/7.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.lc_ctrl_volatile_unlock_smoke.3996934592
Short name T458
Test name
Test status
Simulation time 18030227 ps
CPU time 1.01 seconds
Started Jun 06 01:10:32 PM PDT 24
Finished Jun 06 01:10:34 PM PDT 24
Peak memory 212628 kb
Host smart-0afa8f8d-8f84-4332-92e3-dc87cc4001c0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996934592 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ct
rl_volatile_unlock_smoke.3996934592
Directory /workspace/7.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_alert_test.966881737
Short name T786
Test name
Test status
Simulation time 19671603 ps
CPU time 1.07 seconds
Started Jun 06 01:10:50 PM PDT 24
Finished Jun 06 01:10:52 PM PDT 24
Peak memory 208652 kb
Host smart-65b78a32-1ccf-4ef4-ab86-f34e81687907
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966881737 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_alert_test.966881737
Directory /workspace/8.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.lc_ctrl_claim_transition_if.3217818754
Short name T82
Test name
Test status
Simulation time 13738350 ps
CPU time 1 seconds
Started Jun 06 01:10:40 PM PDT 24
Finished Jun 06 01:10:42 PM PDT 24
Peak memory 208708 kb
Host smart-c0f1e0d6-a454-4da7-8ab6-46a4e24861fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217818754 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_claim_transition_if.3217818754
Directory /workspace/8.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/8.lc_ctrl_errors.1886816897
Short name T116
Test name
Test status
Simulation time 411433214 ps
CPU time 13.47 seconds
Started Jun 06 01:10:48 PM PDT 24
Finished Jun 06 01:11:03 PM PDT 24
Peak memory 217956 kb
Host smart-8531f7c0-4500-4cee-8f21-f69628301c3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886816897 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_errors.1886816897
Directory /workspace/8.lc_ctrl_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_access.3162779030
Short name T9
Test name
Test status
Simulation time 456331855 ps
CPU time 2.31 seconds
Started Jun 06 01:10:41 PM PDT 24
Finished Jun 06 01:10:45 PM PDT 24
Peak memory 216852 kb
Host smart-ee1f9f77-7fe6-43b8-b94d-2b3f67e0139f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162779030 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_access.3162779030
Directory /workspace/8.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_errors.1706270240
Short name T823
Test name
Test status
Simulation time 25360339817 ps
CPU time 31.63 seconds
Started Jun 06 01:10:41 PM PDT 24
Finished Jun 06 01:11:14 PM PDT 24
Peak memory 217936 kb
Host smart-d50038b4-175b-44ef-b37b-d254c3371b54
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706270240 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_er
rors.1706270240
Directory /workspace/8.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_priority.3759883076
Short name T829
Test name
Test status
Simulation time 327345241 ps
CPU time 8.57 seconds
Started Jun 06 01:10:41 PM PDT 24
Finished Jun 06 01:10:50 PM PDT 24
Peak memory 217248 kb
Host smart-0f450e13-07a2-4d66-a817-8377fb71bfaf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759883076 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_priority.3
759883076
Directory /workspace/8.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_prog_failure.2298003749
Short name T467
Test name
Test status
Simulation time 630927749 ps
CPU time 2.68 seconds
Started Jun 06 01:10:41 PM PDT 24
Finished Jun 06 01:10:45 PM PDT 24
Peak memory 218232 kb
Host smart-c495fbd8-3182-4881-8ee4-732ea545ddb0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298003749 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag
_prog_failure.2298003749
Directory /workspace/8.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_regwen_during_op.888308079
Short name T549
Test name
Test status
Simulation time 3146756443 ps
CPU time 12.01 seconds
Started Jun 06 01:10:41 PM PDT 24
Finished Jun 06 01:10:54 PM PDT 24
Peak memory 217696 kb
Host smart-3f57fdc4-963e-43c3-b743-49a21b0815b6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888308079 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_j
tag_regwen_during_op.888308079
Directory /workspace/8.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_smoke.875037779
Short name T652
Test name
Test status
Simulation time 1685063104 ps
CPU time 5.09 seconds
Started Jun 06 01:10:41 PM PDT 24
Finished Jun 06 01:10:47 PM PDT 24
Peak memory 217584 kb
Host smart-31502d60-cdad-4bef-b04c-edc7a15f1016
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875037779 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_smoke.875037779
Directory /workspace/8.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_failure.292449798
Short name T830
Test name
Test status
Simulation time 1566842789 ps
CPU time 70.86 seconds
Started Jun 06 01:10:40 PM PDT 24
Finished Jun 06 01:11:52 PM PDT 24
Peak memory 269176 kb
Host smart-60608046-13d7-4d4e-873c-62aa8449c4b1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292449798 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag
_state_failure.292449798
Directory /workspace/8.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_post_trans.1285619933
Short name T245
Test name
Test status
Simulation time 767044993 ps
CPU time 11.32 seconds
Started Jun 06 01:10:40 PM PDT 24
Finished Jun 06 01:10:53 PM PDT 24
Peak memory 221608 kb
Host smart-9b72231a-b36e-4bb2-b567-56265b142537
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285619933 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_state_post_trans.1285619933
Directory /workspace/8.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_prog_failure.554427996
Short name T267
Test name
Test status
Simulation time 66942529 ps
CPU time 3.52 seconds
Started Jun 06 01:10:40 PM PDT 24
Finished Jun 06 01:10:45 PM PDT 24
Peak memory 217992 kb
Host smart-f72a4ab8-960d-433b-b539-b8946ca4e14c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554427996 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_prog_failure.554427996
Directory /workspace/8.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_regwen_during_op.3924773567
Short name T86
Test name
Test status
Simulation time 601984339 ps
CPU time 16.57 seconds
Started Jun 06 01:10:42 PM PDT 24
Finished Jun 06 01:11:00 PM PDT 24
Peak memory 217704 kb
Host smart-60327360-e804-4d8a-86db-c87886fb1cdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924773567 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_regwen_during_op.3924773567
Directory /workspace/8.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_mubi.2378769908
Short name T641
Test name
Test status
Simulation time 595351632 ps
CPU time 8.74 seconds
Started Jun 06 01:10:39 PM PDT 24
Finished Jun 06 01:10:49 PM PDT 24
Peak memory 226036 kb
Host smart-1c7b49ca-aa8f-4c62-9339-13a7e92b0487
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378769908 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_mubi.2378769908
Directory /workspace/8.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_digest.696369502
Short name T464
Test name
Test status
Simulation time 2815644956 ps
CPU time 13.17 seconds
Started Jun 06 01:10:52 PM PDT 24
Finished Jun 06 01:11:06 PM PDT 24
Peak memory 225948 kb
Host smart-3a8f65ad-954e-40bf-b824-7c32345a17b7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696369502 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_dig
est.696369502
Directory /workspace/8.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_mux.2490539737
Short name T57
Test name
Test status
Simulation time 971835311 ps
CPU time 15.51 seconds
Started Jun 06 01:10:40 PM PDT 24
Finished Jun 06 01:10:57 PM PDT 24
Peak memory 218076 kb
Host smart-8678bffc-5257-4890-ae67-2057c98bc872
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490539737 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_mux.2
490539737
Directory /workspace/8.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/8.lc_ctrl_smoke.1461219747
Short name T537
Test name
Test status
Simulation time 102958384 ps
CPU time 2.32 seconds
Started Jun 06 01:10:41 PM PDT 24
Finished Jun 06 01:10:45 PM PDT 24
Peak memory 213896 kb
Host smart-9346ca00-e8ec-4e67-83f0-d9355bdf249c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461219747 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_smoke.1461219747
Directory /workspace/8.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_failure.3606187198
Short name T534
Test name
Test status
Simulation time 1274932649 ps
CPU time 33 seconds
Started Jun 06 01:10:41 PM PDT 24
Finished Jun 06 01:11:15 PM PDT 24
Peak memory 250968 kb
Host smart-188f661e-d2ac-4506-8c49-35617f04dfc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606187198 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_failure.3606187198
Directory /workspace/8.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_post_trans.1470173624
Short name T659
Test name
Test status
Simulation time 155728186 ps
CPU time 7.16 seconds
Started Jun 06 01:10:43 PM PDT 24
Finished Jun 06 01:10:51 PM PDT 24
Peak memory 250500 kb
Host smart-0c901258-5f30-4a44-839b-a8f3d3e027eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470173624 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_post_trans.1470173624
Directory /workspace/8.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_volatile_unlock_smoke.2721297087
Short name T693
Test name
Test status
Simulation time 15253375 ps
CPU time 1.12 seconds
Started Jun 06 01:10:46 PM PDT 24
Finished Jun 06 01:10:48 PM PDT 24
Peak memory 211508 kb
Host smart-7929bc86-c19d-42f9-b42f-a4fafc5298ed
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721297087 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ct
rl_volatile_unlock_smoke.2721297087
Directory /workspace/8.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_alert_test.4210706747
Short name T224
Test name
Test status
Simulation time 27058981 ps
CPU time 0.95 seconds
Started Jun 06 01:10:57 PM PDT 24
Finished Jun 06 01:10:59 PM PDT 24
Peak memory 208616 kb
Host smart-aacde025-5f49-49ae-8ecf-546d928325d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210706747 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_alert_test.4210706747
Directory /workspace/9.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.lc_ctrl_claim_transition_if.3897679889
Short name T231
Test name
Test status
Simulation time 13763309 ps
CPU time 0.99 seconds
Started Jun 06 01:10:48 PM PDT 24
Finished Jun 06 01:10:51 PM PDT 24
Peak memory 208688 kb
Host smart-4cab5f02-7328-496f-bc71-5bc64a2f889f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897679889 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_claim_transition_if.3897679889
Directory /workspace/9.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/9.lc_ctrl_errors.3634565421
Short name T376
Test name
Test status
Simulation time 736953059 ps
CPU time 9.86 seconds
Started Jun 06 01:10:49 PM PDT 24
Finished Jun 06 01:11:00 PM PDT 24
Peak memory 217964 kb
Host smart-fbe4bdc4-2e35-4114-b4fd-b4ea24b70274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634565421 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_errors.3634565421
Directory /workspace/9.lc_ctrl_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_access.619004058
Short name T440
Test name
Test status
Simulation time 735991842 ps
CPU time 2.77 seconds
Started Jun 06 01:10:49 PM PDT 24
Finished Jun 06 01:10:53 PM PDT 24
Peak memory 209556 kb
Host smart-4af2d076-258c-4d3a-baed-f53b0f90afd3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619004058 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_access.619004058
Directory /workspace/9.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_errors.4215500706
Short name T50
Test name
Test status
Simulation time 5083846355 ps
CPU time 23.8 seconds
Started Jun 06 01:10:49 PM PDT 24
Finished Jun 06 01:11:15 PM PDT 24
Peak memory 218932 kb
Host smart-02588a09-5f94-4e13-a7de-5d44f1dc0bcd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215500706 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_er
rors.4215500706
Directory /workspace/9.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_priority.3689718951
Short name T253
Test name
Test status
Simulation time 2642699465 ps
CPU time 22.36 seconds
Started Jun 06 01:10:50 PM PDT 24
Finished Jun 06 01:11:14 PM PDT 24
Peak memory 217808 kb
Host smart-89a393a2-2538-44ba-8b95-f6c5ef91dda5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689718951 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_priority.3
689718951
Directory /workspace/9.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_prog_failure.2110774530
Short name T243
Test name
Test status
Simulation time 308166092 ps
CPU time 9.3 seconds
Started Jun 06 01:10:49 PM PDT 24
Finished Jun 06 01:10:59 PM PDT 24
Peak memory 217888 kb
Host smart-844f2745-43f8-48b1-81ff-52602043715c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110774530 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag
_prog_failure.2110774530
Directory /workspace/9.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_regwen_during_op.2517007567
Short name T85
Test name
Test status
Simulation time 1062193321 ps
CPU time 32.38 seconds
Started Jun 06 01:10:47 PM PDT 24
Finished Jun 06 01:11:21 PM PDT 24
Peak memory 217608 kb
Host smart-7ece95c4-5f74-4fa2-9fd9-7671cc162680
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517007567 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_regwen_during_op.2517007567
Directory /workspace/9.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_smoke.3996000444
Short name T84
Test name
Test status
Simulation time 1581894103 ps
CPU time 7.63 seconds
Started Jun 06 01:10:50 PM PDT 24
Finished Jun 06 01:10:59 PM PDT 24
Peak memory 217648 kb
Host smart-db6a91c1-51f8-4f39-9382-14d51c90a05d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996000444 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_smoke.
3996000444
Directory /workspace/9.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_failure.2709277240
Short name T199
Test name
Test status
Simulation time 2380553080 ps
CPU time 33.54 seconds
Started Jun 06 01:10:49 PM PDT 24
Finished Jun 06 01:11:24 PM PDT 24
Peak memory 267788 kb
Host smart-cff38b34-e0b3-4e3f-925f-bc46c2bf7de9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709277240 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jta
g_state_failure.2709277240
Directory /workspace/9.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_post_trans.275339373
Short name T295
Test name
Test status
Simulation time 1972748848 ps
CPU time 15.8 seconds
Started Jun 06 01:10:52 PM PDT 24
Finished Jun 06 01:11:08 PM PDT 24
Peak memory 250888 kb
Host smart-2d251a28-f25d-41e9-83e1-bdb6379c2da7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275339373 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_j
tag_state_post_trans.275339373
Directory /workspace/9.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_prog_failure.1020915276
Short name T244
Test name
Test status
Simulation time 40933490 ps
CPU time 1.9 seconds
Started Jun 06 01:10:49 PM PDT 24
Finished Jun 06 01:10:52 PM PDT 24
Peak memory 218212 kb
Host smart-9ea78742-fa27-40e5-83c9-f7e55ba24a35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020915276 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_prog_failure.1020915276
Directory /workspace/9.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_regwen_during_op.3383107205
Short name T344
Test name
Test status
Simulation time 322651865 ps
CPU time 18.83 seconds
Started Jun 06 01:10:48 PM PDT 24
Finished Jun 06 01:11:08 PM PDT 24
Peak memory 214496 kb
Host smart-8c5ab2db-2e91-4cbf-b124-51d31b562131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383107205 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_regwen_during_op.3383107205
Directory /workspace/9.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_mubi.3158702634
Short name T52
Test name
Test status
Simulation time 734886038 ps
CPU time 19.37 seconds
Started Jun 06 01:10:49 PM PDT 24
Finished Jun 06 01:11:10 PM PDT 24
Peak memory 218112 kb
Host smart-dba684d3-9347-474c-ba1e-d636d0b088a0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158702634 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_mubi.3158702634
Directory /workspace/9.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_digest.2912047678
Short name T446
Test name
Test status
Simulation time 260027510 ps
CPU time 11.63 seconds
Started Jun 06 01:10:49 PM PDT 24
Finished Jun 06 01:11:02 PM PDT 24
Peak memory 217884 kb
Host smart-fc046d65-462d-4e85-8927-2f9636af7153
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912047678 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_di
gest.2912047678
Directory /workspace/9.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_mux.2590252285
Short name T811
Test name
Test status
Simulation time 5680284465 ps
CPU time 14.64 seconds
Started Jun 06 01:10:49 PM PDT 24
Finished Jun 06 01:11:05 PM PDT 24
Peak memory 218040 kb
Host smart-56ed061f-b1e7-4bc7-aadb-58f4abc000cb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590252285 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_mux.2
590252285
Directory /workspace/9.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/9.lc_ctrl_security_escalation.185092859
Short name T501
Test name
Test status
Simulation time 413565053 ps
CPU time 6.89 seconds
Started Jun 06 01:10:51 PM PDT 24
Finished Jun 06 01:10:59 PM PDT 24
Peak memory 217952 kb
Host smart-95873bb5-4c22-46c8-8c97-c5f3af181783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185092859 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_security_escalation.185092859
Directory /workspace/9.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/9.lc_ctrl_smoke.632193639
Short name T636
Test name
Test status
Simulation time 149020656 ps
CPU time 2.82 seconds
Started Jun 06 01:10:49 PM PDT 24
Finished Jun 06 01:10:54 PM PDT 24
Peak memory 217692 kb
Host smart-12244a80-53c7-4934-afd8-fec886cbbdb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632193639 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_smoke.632193639
Directory /workspace/9.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_failure.1693702996
Short name T821
Test name
Test status
Simulation time 1710134043 ps
CPU time 33.08 seconds
Started Jun 06 01:10:49 PM PDT 24
Finished Jun 06 01:11:23 PM PDT 24
Peak memory 250912 kb
Host smart-77f47727-93c1-4aff-9879-f298ed58f1a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693702996 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_failure.1693702996
Directory /workspace/9.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_post_trans.721576653
Short name T832
Test name
Test status
Simulation time 259154958 ps
CPU time 3.42 seconds
Started Jun 06 01:10:50 PM PDT 24
Finished Jun 06 01:10:55 PM PDT 24
Peak memory 222136 kb
Host smart-dbfa4a6c-f1f0-41c6-925a-248b92fb70f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721576653 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_post_trans.721576653
Directory /workspace/9.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_stress_all.1940885093
Short name T675
Test name
Test status
Simulation time 20354210430 ps
CPU time 318.08 seconds
Started Jun 06 01:10:50 PM PDT 24
Finished Jun 06 01:16:10 PM PDT 24
Peak memory 250976 kb
Host smart-b4ce90e6-4fea-4e1a-adc9-843095c54ede
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940885093 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.lc_ctrl_stress_all.1940885093
Directory /workspace/9.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.lc_ctrl_stress_all_with_rand_reset.1023729248
Short name T63
Test name
Test status
Simulation time 163164667020 ps
CPU time 922.66 seconds
Started Jun 06 01:11:01 PM PDT 24
Finished Jun 06 01:26:24 PM PDT 24
Peak memory 513264 kb
Host smart-a9ce2944-ec08-4e98-b576-e9940f9251a6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1023729248 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_stress_all_with_rand_reset.1023729248
Directory /workspace/9.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.lc_ctrl_volatile_unlock_smoke.2410962900
Short name T776
Test name
Test status
Simulation time 16829238 ps
CPU time 0.92 seconds
Started Jun 06 01:10:47 PM PDT 24
Finished Jun 06 01:10:49 PM PDT 24
Peak memory 208508 kb
Host smart-a7994583-cc75-4581-ad13-b754d5f2a162
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410962900 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ct
rl_volatile_unlock_smoke.2410962900
Directory /workspace/9.lc_ctrl_volatile_unlock_smoke/latest
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