Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

97103656

1

T1

44859

T2

860

T3

52814

auto[1]

1333396

1

T4

11628

T10

792

T11

198

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

97099805

1

T1

44859

T2

860

T3

52814

auto[1]

1337247

1

T4

12112

T10

1089

T11

198

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	6957579	1			T1	7951		T2	155		T3	8001
auto[IdleSt]	20793030	1			T1	2614		T2	705		T3	9159
auto[ClkMuxSt]	34345	1			T1	84		T3	78		T4	69
auto[CntIncrSt]	34123	1			T1	84		T3	78		T4	68
auto[CntProgSt]	1599058	1			T1	19833		T3	156		T4	1087
auto[TransCheckSt]	26589	1			T1	84		T3	78		T4	33
auto[TokenHashSt]	38883287	1			T1	1259		T3	20270		T4	7587
auto[FlashRmaSt]	27669	1			T1	73		T4	42		T11	7
auto[TokenCheck0St]	12300	1			T1	33		T4	25		T11	7
auto[TokenCheck1St]	9147	1			T1	10		T4	24		T11	7
auto[TransProgSt]	391944	1			T4	45		T11	132		T14	23
auto[PostTransSt]	12262341	1			T1	12834		T3	14994		T10	1487
auto[ScrapSt]	235571	1			T4	3		T6	306		T7	299
auto[EscalateSt]	6466000	1			T4	16726		T10	2691		T11	675
auto[InvalidSt]	10702311	1			T11	341		T7	71		T17	262165

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1758	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	10702311	1			T11	341		T7	71		T17	262165
EscalateSt	6466000	1			T4	16726		T10	2691		T11	675
ScrapSt	235571	1			T4	3		T6	306		T7	299
PostTransSt	12262341	1			T1	12834		T3	14994		T10	1487
TransProgSt	391944	1			T4	45		T11	132		T14	23
TokenCheck1St	9147	1			T1	10		T4	24		T11	7
TokenCheck0St	12300	1			T1	33		T4	25		T11	7
FlashRmaSt	27669	1			T1	73		T4	42		T11	7
TokenHashSt	38883287	1			T1	1259		T3	20270		T4	7587
TransCheckSt	26589	1			T1	84		T3	78		T4	33
CntProgSt	1599058	1			T1	19833		T3	156		T4	1087
CntIncrSt	34123	1			T1	84		T3	78		T4	68
ClkMuxSt	34345	1			T1	84		T3	78		T4	69
IdleSt	20793030	1			T1	2614		T2	705		T3	9159
ResetSt	6957579	1			T1	7951		T2	155		T3	8001
arcs[ResetSt=>IdleSt]	51302	1			T1	85		T2	1		T3	79
arcs[IdleSt=>ScrapSt]	286	1			T4	1		T6	1		T7	1
arcs[IdleSt=>ClkMuxSt]	34193	1			T1	84		T3	78		T4	69
arcs[ClkMuxSt=>CntIncrSt]	34123	1			T1	84		T3	78		T4	68
arcs[CntIncrSt=>PostTransSt]	1697	1			T14	9		T15	12		T17	12
arcs[CntIncrSt=>CntProgSt]	32372	1			T1	84		T3	78		T4	68
arcs[CntProgSt=>PostTransSt]	4590	1			T10	19		T14	9		T15	10
arcs[CntProgSt=>TransCheckSt]	26589	1			T1	84		T3	78		T4	33
arcs[TransCheckSt=>PostTransSt]	3620	1			T1	42		T13	45		T14	5
arcs[TransCheckSt=>TokenHashSt]	22873	1			T1	42		T3	78		T4	33
arcs[TokenHashSt=>PostTransSt]	9770	1			T1	9		T3	78		T12	72
arcs[TokenHashSt=>FlashRmaSt]	12420	1			T1	33		T4	25		T11	7
arcs[FlashRmaSt=>TokenCheck0St]	12300	1			T1	33		T4	25		T11	7
arcs[TokenCheck0St=>PostTransSt]	3120	1			T1	23		T13	26		T14	4
arcs[TokenCheck0St=>TokenCheck1St]	9147	1			T1	10		T4	24		T11	7
arcs[TokenCheck1St=>PostTransSt]	648	1			T1	10		T13	18		T18	3
arcs[TransProgSt=>PostTransSt]	7556	1			T11	7		T14	13		T15	6
arcs[IdleSt=>EscalateSt]	161	1			T4	6		T35	5		T50	6
arcs[ClkMuxSt=>EscalateSt]	70	1			T4	1		T35	3		T49	2
arcs[CntIncrSt=>EscalateSt]	54	1			T35	1		T50	1		T51	3
arcs[CntProgSt=>EscalateSt]	1193	1			T4	35		T35	28		T49	36
arcs[TransCheckSt=>EscalateSt]	96	1			T35	2		T50	1		T55	3
arcs[TokenHashSt=>EscalateSt]	683	1			T4	8		T35	11		T49	6
arcs[FlashRmaSt=>EscalateSt]	120	1			T35	5		T49	3		T50	4
arcs[TokenCheck0St=>EscalateSt]	33	1			T4	1		T49	2		T54	1
arcs[TokenCheck1St=>EscalateSt]	157	1			T4	6		T35	5		T49	3
arcs[TransProgSt=>EscalateSt]	786	1			T4	18		T35	19		T49	12
arcs[PostTransSt=>EscalateSt]	4794	1			T10	19		T14	13		T15	10
arcs[InvalidSt=>EscalateSt]	12806	1			T11	4		T7	1		T17	73

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	6957393	1			T1	7951		T2	155		T3	8001
auto[0]	auto[IdleSt]	20792920	1			T1	2614		T2	705		T3	9159
auto[0]	auto[ClkMuxSt]	34300	1			T1	84		T3	78		T4	69
auto[0]	auto[CntIncrSt]	34092	1			T1	84		T3	78		T4	68
auto[0]	auto[CntProgSt]	1598238	1			T1	19833		T3	156		T4	1060
auto[0]	auto[TransCheckSt]	26523	1			T1	84		T3	78		T4	33
auto[0]	auto[TokenHashSt]	38882845	1			T1	1259		T3	20270		T4	7581
auto[0]	auto[FlashRmaSt]	27589	1			T1	73		T4	42		T11	7
auto[0]	auto[TokenCheck0St]	12280	1			T1	33		T4	25		T11	7
auto[0]	auto[TokenCheck1St]	9046	1			T1	10		T4	21		T11	7
auto[0]	auto[TransProgSt]	391432	1			T4	32		T11	132		T14	23
auto[0]	auto[PostTransSt]	12259948	1			T1	12834		T3	14994		T10	1479
auto[0]	auto[ScrapSt]	235525	1			T4	2		T6	306		T7	299
auto[0]	auto[EscalateSt]	5143863	1			T4	5157		T10	1907		T11	479
auto[0]	auto[InvalidSt]	10695904	1			T11	339		T7	71		T17	262122
auto[1]	auto[ResetSt]	186	1			T4	5		T35	4		T49	2
auto[1]	auto[IdleSt]	110	1			T4	4		T35	3		T50	4
auto[1]	auto[ClkMuxSt]	45	1			T35	2		T49	1		T50	1
auto[1]	auto[CntIncrSt]	31	1			T50	1		T51	2		T55	2
auto[1]	auto[CntProgSt]	820	1			T4	27		T35	14		T49	28
auto[1]	auto[TransCheckSt]	66	1			T35	2		T50	1		T55	1
auto[1]	auto[TokenHashSt]	442	1			T4	6		T35	9		T49	3
auto[1]	auto[FlashRmaSt]	80	1			T35	1		T49	2		T50	2
auto[1]	auto[TokenCheck0St]	20	1			T49	2		T54	1		T214	1
auto[1]	auto[TokenCheck1St]	101	1			T4	3		T35	4		T49	3
auto[1]	auto[TransProgSt]	512	1			T4	13		T35	11		T49	10
auto[1]	auto[PostTransSt]	2393	1			T10	8		T14	6		T15	6
auto[1]	auto[ScrapSt]	46	1			T4	1		T35	1		T49	2
auto[1]	auto[EscalateSt]	1322137	1			T4	11569		T10	784		T11	196
auto[1]	auto[InvalidSt]	6407	1			T11	2		T17	43		T48	1

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	6957395	1			T1	7951		T2	155		T3	8001
auto[0]	auto[IdleSt]	20792928	1			T1	2614		T2	705		T3	9159
auto[0]	auto[ClkMuxSt]	34298	1			T1	84		T3	78		T4	68
auto[0]	auto[CntIncrSt]	34082	1			T1	84		T3	78		T4	68
auto[0]	auto[CntProgSt]	1598288	1			T1	19833		T3	156		T4	1068
auto[0]	auto[TransCheckSt]	26519	1			T1	84		T3	78		T4	33
auto[0]	auto[TokenHashSt]	38882831	1			T1	1259		T3	20270		T4	7581
auto[0]	auto[FlashRmaSt]	27595	1			T1	73		T4	42		T11	7
auto[0]	auto[TokenCheck0St]	12277	1			T1	33		T4	24		T11	7
auto[0]	auto[TokenCheck1St]	9040	1			T1	10		T4	18		T11	7
auto[0]	auto[TransProgSt]	391434	1			T4	29		T11	132		T14	23
auto[0]	auto[PostTransSt]	12259877	1			T1	12834		T3	14994		T10	1476
auto[0]	auto[ScrapSt]	235531	1			T4	3		T6	306		T7	299
auto[0]	auto[EscalateSt]	5140040	1			T4	4673		T10	1613		T11	479
auto[0]	auto[InvalidSt]	10695912	1			T11	339		T7	70		T17	262135
auto[1]	auto[ResetSt]	184	1			T4	7		T35	7		T49	3
auto[1]	auto[IdleSt]	102	1			T4	3		T35	5		T50	5
auto[1]	auto[ClkMuxSt]	47	1			T4	1		T35	2		T49	1
auto[1]	auto[CntIncrSt]	41	1			T35	1		T51	3		T55	1
auto[1]	auto[CntProgSt]	770	1			T4	19		T35	21		T49	23
auto[1]	auto[TransCheckSt]	70	1			T35	1		T55	3		T215	1
auto[1]	auto[TokenHashSt]	456	1			T4	6		T35	10		T49	4
auto[1]	auto[FlashRmaSt]	74	1			T35	4		T49	2		T50	3
auto[1]	auto[TokenCheck0St]	23	1			T4	1		T49	1		T214	1
auto[1]	auto[TokenCheck1St]	107	1			T4	6		T35	3		T49	2
auto[1]	auto[TransProgSt]	510	1			T4	16		T35	12		T49	8
auto[1]	auto[PostTransSt]	2464	1			T10	11		T14	7		T15	4
auto[1]	auto[ScrapSt]	40	1			T35	1		T49	2		T50	1
auto[1]	auto[EscalateSt]	1325960	1			T4	12053		T10	1078		T11	196
auto[1]	auto[InvalidSt]	6399	1			T11	2		T7	1		T17	30