Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.93 97.89 95.68 93.34 97.67 98.55 98.76 96.64


Total test records in report: 997
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html
T812 /workspace/coverage/default/5.lc_ctrl_sec_mubi.4167054975 Jun 07 07:29:26 PM PDT 24 Jun 07 07:29:43 PM PDT 24 1248923822 ps
T813 /workspace/coverage/default/23.lc_ctrl_volatile_unlock_smoke.3361313821 Jun 07 07:30:57 PM PDT 24 Jun 07 07:31:00 PM PDT 24 42213121 ps
T814 /workspace/coverage/default/18.lc_ctrl_jtag_state_failure.3192219808 Jun 07 07:30:34 PM PDT 24 Jun 07 07:31:07 PM PDT 24 1106682324 ps
T815 /workspace/coverage/default/31.lc_ctrl_alert_test.1191813087 Jun 07 07:31:25 PM PDT 24 Jun 07 07:31:28 PM PDT 24 229505043 ps
T816 /workspace/coverage/default/29.lc_ctrl_sec_token_mux.1642667537 Jun 07 07:31:14 PM PDT 24 Jun 07 07:31:23 PM PDT 24 216766082 ps
T817 /workspace/coverage/default/20.lc_ctrl_security_escalation.2761551184 Jun 07 07:30:48 PM PDT 24 Jun 07 07:31:01 PM PDT 24 282137011 ps
T818 /workspace/coverage/default/11.lc_ctrl_security_escalation.885027357 Jun 07 07:30:11 PM PDT 24 Jun 07 07:30:26 PM PDT 24 422553047 ps
T819 /workspace/coverage/default/33.lc_ctrl_prog_failure.2597804583 Jun 07 07:31:28 PM PDT 24 Jun 07 07:31:36 PM PDT 24 261310208 ps
T820 /workspace/coverage/default/20.lc_ctrl_prog_failure.1968561235 Jun 07 07:30:38 PM PDT 24 Jun 07 07:30:43 PM PDT 24 214807992 ps
T821 /workspace/coverage/default/1.lc_ctrl_sec_mubi.2261126183 Jun 07 07:29:09 PM PDT 24 Jun 07 07:29:30 PM PDT 24 781266147 ps
T822 /workspace/coverage/default/2.lc_ctrl_alert_test.739153211 Jun 07 07:29:21 PM PDT 24 Jun 07 07:29:25 PM PDT 24 31242230 ps
T823 /workspace/coverage/default/1.lc_ctrl_prog_failure.3788834983 Jun 07 07:29:07 PM PDT 24 Jun 07 07:29:13 PM PDT 24 23713521 ps
T824 /workspace/coverage/default/3.lc_ctrl_jtag_errors.827203391 Jun 07 07:29:22 PM PDT 24 Jun 07 07:29:47 PM PDT 24 1056264304 ps
T825 /workspace/coverage/default/47.lc_ctrl_state_failure.3421085206 Jun 07 07:32:09 PM PDT 24 Jun 07 07:32:38 PM PDT 24 850372556 ps
T826 /workspace/coverage/default/21.lc_ctrl_sec_mubi.2698903123 Jun 07 07:30:47 PM PDT 24 Jun 07 07:31:03 PM PDT 24 453378860 ps
T827 /workspace/coverage/default/20.lc_ctrl_state_post_trans.1484015328 Jun 07 07:30:39 PM PDT 24 Jun 07 07:30:44 PM PDT 24 49980599 ps
T46 /workspace/coverage/default/35.lc_ctrl_stress_all_with_rand_reset.3790376085 Jun 07 07:31:35 PM PDT 24 Jun 07 07:39:54 PM PDT 24 72047972497 ps
T828 /workspace/coverage/default/28.lc_ctrl_sec_token_digest.2131737852 Jun 07 07:31:13 PM PDT 24 Jun 07 07:31:27 PM PDT 24 974049433 ps
T829 /workspace/coverage/default/42.lc_ctrl_sec_mubi.1591457637 Jun 07 07:32:10 PM PDT 24 Jun 07 07:32:24 PM PDT 24 1010193254 ps
T830 /workspace/coverage/default/9.lc_ctrl_state_post_trans.2166196341 Jun 07 07:29:52 PM PDT 24 Jun 07 07:30:03 PM PDT 24 62259005 ps
T831 /workspace/coverage/default/10.lc_ctrl_sec_token_mux.1427625874 Jun 07 07:30:00 PM PDT 24 Jun 07 07:30:11 PM PDT 24 621368819 ps
T832 /workspace/coverage/default/28.lc_ctrl_errors.2381326961 Jun 07 07:31:15 PM PDT 24 Jun 07 07:31:31 PM PDT 24 1251871505 ps
T833 /workspace/coverage/default/15.lc_ctrl_prog_failure.2426243808 Jun 07 07:30:24 PM PDT 24 Jun 07 07:30:29 PM PDT 24 208869328 ps
T834 /workspace/coverage/default/21.lc_ctrl_sec_token_mux.65116325 Jun 07 07:30:45 PM PDT 24 Jun 07 07:30:55 PM PDT 24 232467009 ps
T835 /workspace/coverage/default/46.lc_ctrl_sec_mubi.3931904314 Jun 07 07:32:08 PM PDT 24 Jun 07 07:32:26 PM PDT 24 904711001 ps
T836 /workspace/coverage/default/17.lc_ctrl_sec_mubi.233057658 Jun 07 07:30:34 PM PDT 24 Jun 07 07:30:47 PM PDT 24 204347558 ps
T837 /workspace/coverage/default/32.lc_ctrl_smoke.2184125280 Jun 07 07:31:24 PM PDT 24 Jun 07 07:31:27 PM PDT 24 87670619 ps
T838 /workspace/coverage/default/10.lc_ctrl_state_failure.2453754638 Jun 07 07:30:00 PM PDT 24 Jun 07 07:30:28 PM PDT 24 1062958944 ps
T839 /workspace/coverage/default/6.lc_ctrl_jtag_smoke.4264159727 Jun 07 07:29:35 PM PDT 24 Jun 07 07:29:42 PM PDT 24 114787157 ps
T840 /workspace/coverage/default/38.lc_ctrl_errors.265115862 Jun 07 07:31:43 PM PDT 24 Jun 07 07:31:55 PM PDT 24 432005108 ps
T841 /workspace/coverage/default/32.lc_ctrl_jtag_access.949030968 Jun 07 07:31:24 PM PDT 24 Jun 07 07:31:29 PM PDT 24 175643314 ps
T842 /workspace/coverage/default/6.lc_ctrl_errors.2305900687 Jun 07 07:29:35 PM PDT 24 Jun 07 07:29:54 PM PDT 24 727718138 ps
T843 /workspace/coverage/default/5.lc_ctrl_alert_test.2314371268 Jun 07 07:29:32 PM PDT 24 Jun 07 07:29:36 PM PDT 24 26593301 ps
T844 /workspace/coverage/default/8.lc_ctrl_jtag_errors.1388230480 Jun 07 07:29:48 PM PDT 24 Jun 07 07:30:42 PM PDT 24 9793674016 ps
T845 /workspace/coverage/default/47.lc_ctrl_errors.2919814710 Jun 07 07:32:09 PM PDT 24 Jun 07 07:32:21 PM PDT 24 354122004 ps
T846 /workspace/coverage/default/47.lc_ctrl_security_escalation.1580442055 Jun 07 07:32:09 PM PDT 24 Jun 07 07:32:21 PM PDT 24 1646153409 ps
T847 /workspace/coverage/default/10.lc_ctrl_jtag_smoke.2547225685 Jun 07 07:30:00 PM PDT 24 Jun 07 07:30:05 PM PDT 24 322907460 ps
T848 /workspace/coverage/default/11.lc_ctrl_sec_mubi.1002635415 Jun 07 07:30:05 PM PDT 24 Jun 07 07:30:23 PM PDT 24 679429075 ps
T849 /workspace/coverage/default/2.lc_ctrl_sec_token_mux.1843483119 Jun 07 07:29:19 PM PDT 24 Jun 07 07:29:31 PM PDT 24 796389006 ps
T850 /workspace/coverage/default/6.lc_ctrl_volatile_unlock_smoke.3155955750 Jun 07 07:29:31 PM PDT 24 Jun 07 07:29:35 PM PDT 24 24882704 ps
T851 /workspace/coverage/default/7.lc_ctrl_jtag_access.3053436769 Jun 07 07:29:41 PM PDT 24 Jun 07 07:29:50 PM PDT 24 789336354 ps
T852 /workspace/coverage/default/6.lc_ctrl_sec_token_mux.4240604426 Jun 07 07:29:34 PM PDT 24 Jun 07 07:29:47 PM PDT 24 499999296 ps
T853 /workspace/coverage/default/3.lc_ctrl_jtag_access.2083855852 Jun 07 07:29:22 PM PDT 24 Jun 07 07:29:28 PM PDT 24 997128303 ps
T854 /workspace/coverage/default/2.lc_ctrl_regwen_during_op.2814749245 Jun 07 07:29:08 PM PDT 24 Jun 07 07:29:24 PM PDT 24 1077242544 ps
T855 /workspace/coverage/default/14.lc_ctrl_state_post_trans.40574913 Jun 07 07:30:18 PM PDT 24 Jun 07 07:30:24 PM PDT 24 59549249 ps
T856 /workspace/coverage/default/15.lc_ctrl_security_escalation.3013556961 Jun 07 07:30:24 PM PDT 24 Jun 07 07:30:39 PM PDT 24 429443294 ps
T857 /workspace/coverage/default/18.lc_ctrl_jtag_smoke.1083409098 Jun 07 07:30:31 PM PDT 24 Jun 07 07:30:49 PM PDT 24 2507845977 ps
T858 /workspace/coverage/default/8.lc_ctrl_smoke.3246408347 Jun 07 07:29:42 PM PDT 24 Jun 07 07:29:47 PM PDT 24 271421400 ps
T859 /workspace/coverage/default/24.lc_ctrl_prog_failure.1001936878 Jun 07 07:30:54 PM PDT 24 Jun 07 07:31:02 PM PDT 24 276811723 ps
T860 /workspace/coverage/default/40.lc_ctrl_errors.3826997724 Jun 07 07:32:08 PM PDT 24 Jun 07 07:32:30 PM PDT 24 440687296 ps
T861 /workspace/coverage/default/11.lc_ctrl_state_failure.813513951 Jun 07 07:30:09 PM PDT 24 Jun 07 07:30:43 PM PDT 24 659792110 ps
T862 /workspace/coverage/default/44.lc_ctrl_prog_failure.3876312476 Jun 07 07:32:07 PM PDT 24 Jun 07 07:32:12 PM PDT 24 81035852 ps
T863 /workspace/coverage/default/35.lc_ctrl_sec_token_digest.3915643342 Jun 07 07:31:33 PM PDT 24 Jun 07 07:31:51 PM PDT 24 1642032273 ps
T864 /workspace/coverage/default/32.lc_ctrl_sec_token_mux.2799911758 Jun 07 07:31:27 PM PDT 24 Jun 07 07:31:43 PM PDT 24 421276595 ps
T47 /workspace/coverage/default/1.lc_ctrl_errors.1104296654 Jun 07 07:29:05 PM PDT 24 Jun 07 07:29:34 PM PDT 24 2049060986 ps
T865 /workspace/coverage/default/49.lc_ctrl_smoke.939036288 Jun 07 07:32:22 PM PDT 24 Jun 07 07:32:32 PM PDT 24 66907614 ps
T866 /workspace/coverage/default/21.lc_ctrl_security_escalation.1598858672 Jun 07 07:30:44 PM PDT 24 Jun 07 07:30:58 PM PDT 24 535938562 ps
T867 /workspace/coverage/default/42.lc_ctrl_jtag_access.853691964 Jun 07 07:32:11 PM PDT 24 Jun 07 07:32:19 PM PDT 24 56076421 ps
T868 /workspace/coverage/default/42.lc_ctrl_alert_test.1664179470 Jun 07 07:32:15 PM PDT 24 Jun 07 07:32:21 PM PDT 24 36929013 ps
T869 /workspace/coverage/default/22.lc_ctrl_prog_failure.2049715598 Jun 07 07:30:47 PM PDT 24 Jun 07 07:30:52 PM PDT 24 40360057 ps
T870 /workspace/coverage/default/27.lc_ctrl_sec_token_digest.2725110354 Jun 07 07:31:09 PM PDT 24 Jun 07 07:31:20 PM PDT 24 1467054204 ps
T871 /workspace/coverage/default/12.lc_ctrl_smoke.1896044126 Jun 07 07:30:07 PM PDT 24 Jun 07 07:30:09 PM PDT 24 35023842 ps
T121 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.259569848 Jun 07 07:19:19 PM PDT 24 Jun 07 07:19:37 PM PDT 24 27150576 ps
T148 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.2703219676 Jun 07 07:18:29 PM PDT 24 Jun 07 07:18:37 PM PDT 24 51277110 ps
T114 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.2721296742 Jun 07 07:19:27 PM PDT 24 Jun 07 07:19:48 PM PDT 24 199986880 ps
T122 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.515035327 Jun 07 07:18:30 PM PDT 24 Jun 07 07:18:57 PM PDT 24 3896543620 ps
T144 /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.1176334578 Jun 07 07:18:17 PM PDT 24 Jun 07 07:18:27 PM PDT 24 48553731 ps
T158 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.2318106653 Jun 07 07:18:21 PM PDT 24 Jun 07 07:18:32 PM PDT 24 50278201 ps
T872 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.2999256690 Jun 07 07:18:43 PM PDT 24 Jun 07 07:18:49 PM PDT 24 21322560 ps
T143 /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.4125034741 Jun 07 07:19:20 PM PDT 24 Jun 07 07:19:37 PM PDT 24 44127850 ps
T115 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.3425866877 Jun 07 07:18:41 PM PDT 24 Jun 07 07:18:48 PM PDT 24 43141434 ps
T873 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.588100205 Jun 07 07:18:42 PM PDT 24 Jun 07 07:18:47 PM PDT 24 77075811 ps
T116 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.1972057104 Jun 07 07:18:13 PM PDT 24 Jun 07 07:18:25 PM PDT 24 59164317 ps
T172 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.3438400948 Jun 07 07:19:32 PM PDT 24 Jun 07 07:19:54 PM PDT 24 116285831 ps
T119 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.1283062367 Jun 07 07:19:31 PM PDT 24 Jun 07 07:19:52 PM PDT 24 115213793 ps
T147 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.3540173400 Jun 07 07:18:59 PM PDT 24 Jun 07 07:19:07 PM PDT 24 124039235 ps
T874 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.460356099 Jun 07 07:18:18 PM PDT 24 Jun 07 07:18:29 PM PDT 24 65736268 ps
T145 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.896423998 Jun 07 07:18:54 PM PDT 24 Jun 07 07:19:03 PM PDT 24 1037422284 ps
T117 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.1825412995 Jun 07 07:19:19 PM PDT 24 Jun 07 07:19:38 PM PDT 24 245605040 ps
T207 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.402452582 Jun 07 07:18:42 PM PDT 24 Jun 07 07:19:05 PM PDT 24 1800828596 ps
T875 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.11192537 Jun 07 07:19:07 PM PDT 24 Jun 07 07:19:27 PM PDT 24 19757267824 ps
T173 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.3143094809 Jun 07 07:19:20 PM PDT 24 Jun 07 07:19:38 PM PDT 24 62318435 ps
T120 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.3662852190 Jun 07 07:18:59 PM PDT 24 Jun 07 07:19:06 PM PDT 24 59688857 ps
T200 /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.1208183559 Jun 07 07:18:59 PM PDT 24 Jun 07 07:19:06 PM PDT 24 25579023 ps
T192 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.1151301013 Jun 07 07:19:28 PM PDT 24 Jun 07 07:19:48 PM PDT 24 39116454 ps
T201 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.1149970669 Jun 07 07:18:41 PM PDT 24 Jun 07 07:18:47 PM PDT 24 40636907 ps
T876 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.4152564868 Jun 07 07:19:09 PM PDT 24 Jun 07 07:19:32 PM PDT 24 518237502 ps
T877 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.2613581294 Jun 07 07:19:10 PM PDT 24 Jun 07 07:19:21 PM PDT 24 134855392 ps
T123 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.574263070 Jun 07 07:19:19 PM PDT 24 Jun 07 07:19:40 PM PDT 24 264356838 ps
T878 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.2090234821 Jun 07 07:18:11 PM PDT 24 Jun 07 07:19:11 PM PDT 24 23696913206 ps
T146 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.1180634916 Jun 07 07:18:49 PM PDT 24 Jun 07 07:18:56 PM PDT 24 178508330 ps
T159 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.377233636 Jun 07 07:19:08 PM PDT 24 Jun 07 07:19:19 PM PDT 24 27016320 ps
T879 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.1181373702 Jun 07 07:18:42 PM PDT 24 Jun 07 07:18:48 PM PDT 24 33572641 ps
T202 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.2690552162 Jun 07 07:18:21 PM PDT 24 Jun 07 07:18:31 PM PDT 24 26311431 ps
T182 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.63346856 Jun 07 07:19:19 PM PDT 24 Jun 07 07:19:36 PM PDT 24 22077615 ps
T880 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2283179660 Jun 07 07:18:50 PM PDT 24 Jun 07 07:19:00 PM PDT 24 747966232 ps
T881 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.2595020175 Jun 07 07:18:27 PM PDT 24 Jun 07 07:18:36 PM PDT 24 93376648 ps
T882 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.603271586 Jun 07 07:18:49 PM PDT 24 Jun 07 07:19:01 PM PDT 24 303185640 ps
T124 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.1386518684 Jun 07 07:18:30 PM PDT 24 Jun 07 07:18:39 PM PDT 24 54216641 ps
T883 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.576080119 Jun 07 07:19:08 PM PDT 24 Jun 07 07:19:19 PM PDT 24 53505429 ps
T884 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.319235449 Jun 07 07:19:19 PM PDT 24 Jun 07 07:19:37 PM PDT 24 13729787 ps
T885 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.1592079186 Jun 07 07:19:12 PM PDT 24 Jun 07 07:19:24 PM PDT 24 74427273 ps
T886 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.3535711348 Jun 07 07:18:51 PM PDT 24 Jun 07 07:19:06 PM PDT 24 966992989 ps
T203 /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.191885690 Jun 07 07:19:31 PM PDT 24 Jun 07 07:19:52 PM PDT 24 54703588 ps
T887 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1396690646 Jun 07 07:18:23 PM PDT 24 Jun 07 07:18:34 PM PDT 24 50331209 ps
T888 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.879476524 Jun 07 07:19:14 PM PDT 24 Jun 07 07:19:29 PM PDT 24 42167361 ps
T204 /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.4239606795 Jun 07 07:18:21 PM PDT 24 Jun 07 07:18:31 PM PDT 24 22692689 ps
T889 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.925270162 Jun 07 07:18:13 PM PDT 24 Jun 07 07:18:25 PM PDT 24 201933425 ps
T133 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.3836228719 Jun 07 07:19:35 PM PDT 24 Jun 07 07:19:58 PM PDT 24 21496459 ps
T160 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.3511681999 Jun 07 07:18:49 PM PDT 24 Jun 07 07:18:56 PM PDT 24 287016984 ps
T205 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.4034666857 Jun 07 07:19:19 PM PDT 24 Jun 07 07:19:37 PM PDT 24 15295076 ps
T125 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.2813729408 Jun 07 07:18:51 PM PDT 24 Jun 07 07:18:59 PM PDT 24 918290307 ps
T118 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.3518040663 Jun 07 07:18:28 PM PDT 24 Jun 07 07:18:39 PM PDT 24 101329701 ps
T161 /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.1851408441 Jun 07 07:19:22 PM PDT 24 Jun 07 07:19:40 PM PDT 24 47882321 ps
T130 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.2504764691 Jun 07 07:18:17 PM PDT 24 Jun 07 07:18:30 PM PDT 24 844405744 ps
T162 /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.4148052851 Jun 07 07:18:29 PM PDT 24 Jun 07 07:18:37 PM PDT 24 482562050 ps
T890 /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.2412601843 Jun 07 07:19:32 PM PDT 24 Jun 07 07:19:54 PM PDT 24 20647677 ps
T891 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.4051467621 Jun 07 07:19:08 PM PDT 24 Jun 07 07:19:20 PM PDT 24 332253047 ps
T892 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.2604152697 Jun 07 07:19:22 PM PDT 24 Jun 07 07:19:42 PM PDT 24 25307499 ps
T893 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.3890813213 Jun 07 07:18:29 PM PDT 24 Jun 07 07:18:37 PM PDT 24 33087375 ps
T894 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.3844041377 Jun 07 07:19:08 PM PDT 24 Jun 07 07:19:21 PM PDT 24 119690349 ps
T895 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.1658227135 Jun 07 07:18:49 PM PDT 24 Jun 07 07:18:57 PM PDT 24 486343425 ps
T137 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.3293950873 Jun 07 07:18:19 PM PDT 24 Jun 07 07:18:30 PM PDT 24 46686606 ps
T896 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.1904572518 Jun 07 07:19:18 PM PDT 24 Jun 07 07:19:34 PM PDT 24 18669838 ps
T897 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.3654593 Jun 07 07:18:29 PM PDT 24 Jun 07 07:18:38 PM PDT 24 266977544 ps
T898 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.1675327063 Jun 07 07:18:39 PM PDT 24 Jun 07 07:18:46 PM PDT 24 359202692 ps
T899 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.465540348 Jun 07 07:18:37 PM PDT 24 Jun 07 07:18:44 PM PDT 24 166166780 ps
T900 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.3770949313 Jun 07 07:18:27 PM PDT 24 Jun 07 07:18:36 PM PDT 24 100952635 ps
T139 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.1108429452 Jun 07 07:19:10 PM PDT 24 Jun 07 07:19:23 PM PDT 24 419510173 ps
T901 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.804806958 Jun 07 07:18:22 PM PDT 24 Jun 07 07:18:33 PM PDT 24 67827414 ps
T902 /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.489788529 Jun 07 07:19:19 PM PDT 24 Jun 07 07:19:37 PM PDT 24 43471690 ps
T138 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.3397056132 Jun 07 07:19:18 PM PDT 24 Jun 07 07:19:35 PM PDT 24 113795600 ps
T903 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.3486714563 Jun 07 07:18:51 PM PDT 24 Jun 07 07:18:57 PM PDT 24 56123722 ps
T904 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.4197243678 Jun 07 07:18:40 PM PDT 24 Jun 07 07:18:47 PM PDT 24 446844381 ps
T136 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.1192656805 Jun 07 07:19:20 PM PDT 24 Jun 07 07:19:41 PM PDT 24 554978924 ps
T905 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.555924803 Jun 07 07:18:14 PM PDT 24 Jun 07 07:18:25 PM PDT 24 19746937 ps
T906 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.259173446 Jun 07 07:18:30 PM PDT 24 Jun 07 07:18:38 PM PDT 24 65718831 ps
T907 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.217747620 Jun 07 07:18:59 PM PDT 24 Jun 07 07:19:05 PM PDT 24 19190881 ps
T908 /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.3096175376 Jun 07 07:19:08 PM PDT 24 Jun 07 07:19:19 PM PDT 24 34858251 ps
T909 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.3995969183 Jun 07 07:18:51 PM PDT 24 Jun 07 07:18:57 PM PDT 24 151178307 ps
T910 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.1415062312 Jun 07 07:18:28 PM PDT 24 Jun 07 07:18:48 PM PDT 24 962149220 ps
T911 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.3629525227 Jun 07 07:18:32 PM PDT 24 Jun 07 07:18:38 PM PDT 24 33121314 ps
T912 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.3677215915 Jun 07 07:18:30 PM PDT 24 Jun 07 07:18:40 PM PDT 24 70999214 ps
T913 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.601870491 Jun 07 07:19:08 PM PDT 24 Jun 07 07:19:31 PM PDT 24 1302645996 ps
T914 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.3364665499 Jun 07 07:19:25 PM PDT 24 Jun 07 07:19:44 PM PDT 24 26030748 ps
T915 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.1380451200 Jun 07 07:18:37 PM PDT 24 Jun 07 07:18:43 PM PDT 24 33059084 ps
T916 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.3619812831 Jun 07 07:18:29 PM PDT 24 Jun 07 07:18:37 PM PDT 24 22041375 ps
T917 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.3929766917 Jun 07 07:18:21 PM PDT 24 Jun 07 07:18:31 PM PDT 24 80341823 ps
T918 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.990848490 Jun 07 07:19:11 PM PDT 24 Jun 07 07:19:24 PM PDT 24 174754624 ps
T919 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.3852415741 Jun 07 07:18:54 PM PDT 24 Jun 07 07:19:01 PM PDT 24 66495302 ps
T920 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.1899379309 Jun 07 07:19:02 PM PDT 24 Jun 07 07:19:28 PM PDT 24 830812112 ps
T140 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.3015771844 Jun 07 07:19:20 PM PDT 24 Jun 07 07:19:40 PM PDT 24 117598901 ps
T921 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.2694330728 Jun 07 07:19:23 PM PDT 24 Jun 07 07:19:44 PM PDT 24 609260337 ps
T922 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.979478333 Jun 07 07:18:12 PM PDT 24 Jun 07 07:18:24 PM PDT 24 173291561 ps
T923 /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.4161625642 Jun 07 07:19:11 PM PDT 24 Jun 07 07:19:23 PM PDT 24 42114819 ps
T924 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2784796701 Jun 07 07:18:31 PM PDT 24 Jun 07 07:18:39 PM PDT 24 72287497 ps
T925 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.213002527 Jun 07 07:19:31 PM PDT 24 Jun 07 07:19:52 PM PDT 24 52967841 ps
T926 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.1982124836 Jun 07 07:18:41 PM PDT 24 Jun 07 07:18:48 PM PDT 24 138438589 ps
T927 /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.3153510308 Jun 07 07:18:43 PM PDT 24 Jun 07 07:18:48 PM PDT 24 29809120 ps
T193 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.3741939483 Jun 07 07:18:50 PM PDT 24 Jun 07 07:18:56 PM PDT 24 19435474 ps
T194 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.2702922507 Jun 07 07:19:34 PM PDT 24 Jun 07 07:19:55 PM PDT 24 38492765 ps
T928 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.650397 Jun 07 07:19:21 PM PDT 24 Jun 07 07:19:40 PM PDT 24 84724827 ps
T929 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.325133733 Jun 07 07:18:49 PM PDT 24 Jun 07 07:18:56 PM PDT 24 63316326 ps
T930 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.2833758392 Jun 07 07:18:08 PM PDT 24 Jun 07 07:18:24 PM PDT 24 137020855 ps
T128 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.57207488 Jun 07 07:19:31 PM PDT 24 Jun 07 07:19:55 PM PDT 24 240168055 ps
T931 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.2658196778 Jun 07 07:18:52 PM PDT 24 Jun 07 07:18:59 PM PDT 24 38465767 ps
T213 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.311667641 Jun 07 07:19:20 PM PDT 24 Jun 07 07:19:38 PM PDT 24 90674268 ps
T932 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.1767042406 Jun 07 07:19:20 PM PDT 24 Jun 07 07:19:40 PM PDT 24 76053529 ps
T131 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.257314746 Jun 07 07:19:19 PM PDT 24 Jun 07 07:19:39 PM PDT 24 262882265 ps
T933 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.54485131 Jun 07 07:19:10 PM PDT 24 Jun 07 07:19:22 PM PDT 24 36085938 ps
T934 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.3683988966 Jun 07 07:19:00 PM PDT 24 Jun 07 07:19:06 PM PDT 24 13809072 ps
T935 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.1917088557 Jun 07 07:18:51 PM PDT 24 Jun 07 07:19:06 PM PDT 24 894730119 ps
T134 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.2665083671 Jun 07 07:19:11 PM PDT 24 Jun 07 07:19:24 PM PDT 24 396638408 ps
T936 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.817300225 Jun 07 07:18:10 PM PDT 24 Jun 07 07:18:23 PM PDT 24 335159739 ps
T195 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.1147293434 Jun 07 07:18:16 PM PDT 24 Jun 07 07:18:27 PM PDT 24 35943085 ps
T937 /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.441642278 Jun 07 07:19:25 PM PDT 24 Jun 07 07:19:43 PM PDT 24 130104870 ps
T938 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.3198346431 Jun 07 07:19:10 PM PDT 24 Jun 07 07:19:25 PM PDT 24 655613148 ps
T939 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.4274298904 Jun 07 07:18:12 PM PDT 24 Jun 07 07:18:35 PM PDT 24 1146043537 ps
T940 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.3000181162 Jun 07 07:18:19 PM PDT 24 Jun 07 07:18:30 PM PDT 24 38321877 ps
T196 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.1978929382 Jun 07 07:19:33 PM PDT 24 Jun 07 07:19:55 PM PDT 24 43059270 ps
T197 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.3808698828 Jun 07 07:18:41 PM PDT 24 Jun 07 07:18:47 PM PDT 24 15816047 ps
T941 /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.2809086150 Jun 07 07:18:49 PM PDT 24 Jun 07 07:18:55 PM PDT 24 24006295 ps
T942 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.3007043783 Jun 07 07:18:41 PM PDT 24 Jun 07 07:18:47 PM PDT 24 29963038 ps
T943 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.730448193 Jun 07 07:19:11 PM PDT 24 Jun 07 07:19:23 PM PDT 24 52514761 ps
T944 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.1644471872 Jun 07 07:18:59 PM PDT 24 Jun 07 07:19:08 PM PDT 24 102008857 ps
T945 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.2150485918 Jun 07 07:19:30 PM PDT 24 Jun 07 07:19:52 PM PDT 24 212445309 ps
T946 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.2582392536 Jun 07 07:18:31 PM PDT 24 Jun 07 07:18:38 PM PDT 24 27278136 ps
T947 /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.897126342 Jun 07 07:19:25 PM PDT 24 Jun 07 07:19:44 PM PDT 24 99528952 ps
T198 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.302247146 Jun 07 07:18:18 PM PDT 24 Jun 07 07:18:28 PM PDT 24 11776294 ps
T948 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.4094136128 Jun 07 07:19:19 PM PDT 24 Jun 07 07:19:36 PM PDT 24 155968744 ps
T949 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2253235956 Jun 07 07:18:41 PM PDT 24 Jun 07 07:18:48 PM PDT 24 916119521 ps
T950 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1477227679 Jun 07 07:19:11 PM PDT 24 Jun 07 07:19:25 PM PDT 24 751032485 ps
T199 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.1431559950 Jun 07 07:18:19 PM PDT 24 Jun 07 07:18:30 PM PDT 24 17993031 ps
T126 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.913346633 Jun 07 07:18:14 PM PDT 24 Jun 07 07:18:27 PM PDT 24 287091844 ps
T951 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.1392962006 Jun 07 07:18:29 PM PDT 24 Jun 07 07:18:38 PM PDT 24 155352830 ps
T952 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.771264366 Jun 07 07:19:12 PM PDT 24 Jun 07 07:19:25 PM PDT 24 36871032 ps
T132 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.1079842274 Jun 07 07:18:31 PM PDT 24 Jun 07 07:18:40 PM PDT 24 1111875261 ps
T135 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.536570542 Jun 07 07:19:09 PM PDT 24 Jun 07 07:19:22 PM PDT 24 509322236 ps
T953 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.2703774064 Jun 07 07:18:50 PM PDT 24 Jun 07 07:19:02 PM PDT 24 1828318076 ps
T954 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.352755674 Jun 07 07:19:28 PM PDT 24 Jun 07 07:19:48 PM PDT 24 11020578 ps
T955 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.2660733081 Jun 07 07:18:39 PM PDT 24 Jun 07 07:18:44 PM PDT 24 13682244 ps
T956 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3195510447 Jun 07 07:19:02 PM PDT 24 Jun 07 07:19:10 PM PDT 24 101630999 ps
T129 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.3166934087 Jun 07 07:18:58 PM PDT 24 Jun 07 07:19:07 PM PDT 24 727642498 ps
T957 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.746391529 Jun 07 07:19:09 PM PDT 24 Jun 07 07:19:22 PM PDT 24 57156876 ps
T958 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.1338360085 Jun 07 07:19:20 PM PDT 24 Jun 07 07:19:38 PM PDT 24 37031664 ps
T959 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.605251292 Jun 07 07:19:11 PM PDT 24 Jun 07 07:19:23 PM PDT 24 236774557 ps
T960 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.1612415658 Jun 07 07:19:22 PM PDT 24 Jun 07 07:19:41 PM PDT 24 46559782 ps
T141 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.2749108390 Jun 07 07:18:49 PM PDT 24 Jun 07 07:18:57 PM PDT 24 288527181 ps
T961 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1792419591 Jun 07 07:18:30 PM PDT 24 Jun 07 07:18:39 PM PDT 24 361941367 ps
T962 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.2439114550 Jun 07 07:19:00 PM PDT 24 Jun 07 07:19:08 PM PDT 24 57659072 ps
T963 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.159160632 Jun 07 07:18:50 PM PDT 24 Jun 07 07:18:57 PM PDT 24 219730389 ps
T964 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.3896508473 Jun 07 07:18:48 PM PDT 24 Jun 07 07:18:55 PM PDT 24 30644580 ps
T965 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.1784093685 Jun 07 07:19:03 PM PDT 24 Jun 07 07:19:11 PM PDT 24 278890203 ps
T966 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.3439433829 Jun 07 07:18:59 PM PDT 24 Jun 07 07:19:11 PM PDT 24 870524111 ps
T967 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.2400525466 Jun 07 07:19:21 PM PDT 24 Jun 07 07:19:39 PM PDT 24 39846571 ps
T968 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.2793255149 Jun 07 07:18:30 PM PDT 24 Jun 07 07:18:38 PM PDT 24 284610485 ps
T127 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.3604006194 Jun 07 07:19:24 PM PDT 24 Jun 07 07:19:45 PM PDT 24 115805682 ps
T969 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.1948362675 Jun 07 07:18:50 PM PDT 24 Jun 07 07:18:56 PM PDT 24 45980300 ps
T970 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.816376109 Jun 07 07:18:14 PM PDT 24 Jun 07 07:18:25 PM PDT 24 44231850 ps
T971 /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.4080382938 Jun 07 07:19:31 PM PDT 24 Jun 07 07:19:52 PM PDT 24 74650210 ps
T972 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.610967616 Jun 07 07:19:20 PM PDT 24 Jun 07 07:19:38 PM PDT 24 67987105 ps
T973 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.1323219431 Jun 07 07:18:51 PM PDT 24 Jun 07 07:18:57 PM PDT 24 23815302 ps
T974 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.3243464099 Jun 07 07:18:30 PM PDT 24 Jun 07 07:18:40 PM PDT 24 477811554 ps
T975 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.4222129322 Jun 07 07:19:10 PM PDT 24 Jun 07 07:19:22 PM PDT 24 14503416 ps
T976 /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.3059918771 Jun 07 07:18:50 PM PDT 24 Jun 07 07:18:56 PM PDT 24 19964328 ps
T977 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.3809992651 Jun 07 07:18:19 PM PDT 24 Jun 07 07:18:29 PM PDT 24 62727947 ps
T978 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.3149233726 Jun 07 07:19:10 PM PDT 24 Jun 07 07:19:23 PM PDT 24 47510978 ps
T979 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.1714707148 Jun 07 07:19:19 PM PDT 24 Jun 07 07:19:37 PM PDT 24 41463267 ps
T980 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.2027940009 Jun 07 07:18:19 PM PDT 24 Jun 07 07:18:34 PM PDT 24 421493739 ps
T981 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.2933356870 Jun 07 07:18:41 PM PDT 24 Jun 07 07:18:48 PM PDT 24 656398018 ps
T982 /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.4098840069 Jun 07 07:19:18 PM PDT 24 Jun 07 07:19:35 PM PDT 24 65352943 ps
T983 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.1598273659 Jun 07 07:18:29 PM PDT 24 Jun 07 07:18:55 PM PDT 24 3307480800 ps
T984 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.2100794985 Jun 07 07:18:37 PM PDT 24 Jun 07 07:18:58 PM PDT 24 661131100 ps
T985 /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.3674912972 Jun 07 07:19:30 PM PDT 24 Jun 07 07:19:50 PM PDT 24 91275625 ps
T986 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.2744546044 Jun 07 07:19:29 PM PDT 24 Jun 07 07:19:50 PM PDT 24 25097824 ps
T987 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.2091156896 Jun 07 07:19:30 PM PDT 24 Jun 07 07:19:50 PM PDT 24 18695055 ps
T142 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.2044729515 Jun 07 07:19:19 PM PDT 24 Jun 07 07:19:38 PM PDT 24 596183554 ps
T988 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.4084720994 Jun 07 07:19:19 PM PDT 24 Jun 07 07:19:38 PM PDT 24 298522931 ps
T989 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.2343708671 Jun 07 07:18:10 PM PDT 24 Jun 07 07:18:22 PM PDT 24 142170153 ps
T990 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.487534650 Jun 07 07:18:19 PM PDT 24 Jun 07 07:18:31 PM PDT 24 184918455 ps
T991 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.724472001 Jun 07 07:19:10 PM PDT 24 Jun 07 07:19:37 PM PDT 24 691495666 ps
T992 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.3598089652 Jun 07 07:19:21 PM PDT 24 Jun 07 07:19:39 PM PDT 24 35944687 ps
T993 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.4243748676 Jun 07 07:19:13 PM PDT 24 Jun 07 07:19:27 PM PDT 24 113402812 ps
T994 /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.715135095 Jun 07 07:19:19 PM PDT 24 Jun 07 07:19:36 PM PDT 24 37281070 ps
T995 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.3775307686 Jun 07 07:19:32 PM PDT 24 Jun 07 07:19:54 PM PDT 24 47323492 ps
T996 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.3095502953 Jun 07 07:18:41 PM PDT 24 Jun 07 07:18:54 PM PDT 24 4237392017 ps
T997 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.1828039761 Jun 07 07:18:21 PM PDT 24 Jun 07 07:18:33 PM PDT 24 1213859087 ps

Test location /workspace/coverage/default/18.lc_ctrl_errors.374004014
Short name T14
Test name
Test status
Simulation time 964265358 ps
CPU time 9.82 seconds
Started Jun 07 07:30:31 PM PDT 24
Finished Jun 07 07:30:44 PM PDT 24
Peak memory 218532 kb
Host smart-179809da-39e3-4539-9977-58da24413b42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374004014 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_errors.374004014
Directory /workspace/18.lc_ctrl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all.3452798578
Short name T21
Test name
Test status
Simulation time 6553050009 ps
CPU time 83.99 seconds
Started Jun 07 07:29:11 PM PDT 24
Finished Jun 07 07:30:39 PM PDT 24
Peak memory 243244 kb
Host smart-94951d17-0a5f-492e-b305-057edc251b72
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452798578 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.lc_ctrl_stress_all.3452798578
Directory /workspace/0.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.lc_ctrl_security_escalation.3573911921
Short name T35
Test name
Test status
Simulation time 402557596 ps
CPU time 13.78 seconds
Started Jun 07 07:31:40 PM PDT 24
Finished Jun 07 07:31:55 PM PDT 24
Peak memory 225724 kb
Host smart-9e8658ea-58d9-446f-b690-9f9c202ff678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573911921 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_security_escalation.3573911921
Directory /workspace/38.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all_with_rand_reset.2777895285
Short name T42
Test name
Test status
Simulation time 20941071950 ps
CPU time 385.27 seconds
Started Jun 07 07:31:16 PM PDT 24
Finished Jun 07 07:37:43 PM PDT 24
Peak memory 282568 kb
Host smart-31248aa7-b65e-4d39-a5f3-bc7d57076599
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2777895285 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_stress_all_with_rand_reset.2777895285
Directory /workspace/30.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_mubi.1085736735
Short name T39
Test name
Test status
Simulation time 2069067328 ps
CPU time 15.69 seconds
Started Jun 07 07:29:27 PM PDT 24
Finished Jun 07 07:29:47 PM PDT 24
Peak memory 219396 kb
Host smart-228c4ad6-da1c-459b-8de5-58408a0b0006
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085736735 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_mubi.1085736735
Directory /workspace/4.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.2721296742
Short name T114
Test name
Test status
Simulation time 199986880 ps
CPU time 2.74 seconds
Started Jun 07 07:19:27 PM PDT 24
Finished Jun 07 07:19:48 PM PDT 24
Peak memory 222344 kb
Host smart-17a1d658-64ff-4250-a324-aba27b900f95
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721296742 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_intg
_err.2721296742
Directory /workspace/17.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/17.lc_ctrl_security_escalation.3212623941
Short name T4
Test name
Test status
Simulation time 2606273668 ps
CPU time 10 seconds
Started Jun 07 07:30:29 PM PDT 24
Finished Jun 07 07:30:42 PM PDT 24
Peak memory 218836 kb
Host smart-3ce972c1-e3e4-46f3-b4d8-e9818e6bdcf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212623941 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_security_escalation.3212623941
Directory /workspace/17.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/12.lc_ctrl_volatile_unlock_smoke.2209057309
Short name T31
Test name
Test status
Simulation time 46346343 ps
CPU time 0.82 seconds
Started Jun 07 07:30:12 PM PDT 24
Finished Jun 07 07:30:14 PM PDT 24
Peak memory 209428 kb
Host smart-7d9eaae9-1e18-44fc-8736-70341aeb809e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209057309 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_c
trl_volatile_unlock_smoke.2209057309
Directory /workspace/12.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_cm.3517217339
Short name T53
Test name
Test status
Simulation time 404874850 ps
CPU time 40 seconds
Started Jun 07 07:29:05 PM PDT 24
Finished Jun 07 07:29:50 PM PDT 24
Peak memory 270520 kb
Host smart-dc670748-e2da-45ed-a56b-4c13640b9bbb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517217339 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_cm.3517217339
Directory /workspace/0.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_access.3962897952
Short name T5
Test name
Test status
Simulation time 3032478811 ps
CPU time 7.69 seconds
Started Jun 07 07:29:24 PM PDT 24
Finished Jun 07 07:29:34 PM PDT 24
Peak memory 218208 kb
Host smart-a8781e2e-0097-4f8a-a1dc-94efdec71444
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962897952 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_access.3962897952
Directory /workspace/4.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.1825412995
Short name T117
Test name
Test status
Simulation time 245605040 ps
CPU time 3.52 seconds
Started Jun 07 07:19:19 PM PDT 24
Finished Jun 07 07:19:38 PM PDT 24
Peak memory 218108 kb
Host smart-b291cd7c-4bf9-4f6a-94bb-0306e14e2224
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825412995 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_errors.1825412995
Directory /workspace/15.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/22.lc_ctrl_stress_all_with_rand_reset.521964671
Short name T92
Test name
Test status
Simulation time 158370818294 ps
CPU time 1929.7 seconds
Started Jun 07 07:30:56 PM PDT 24
Finished Jun 07 08:03:09 PM PDT 24
Peak memory 857044 kb
Host smart-53ebf076-4cc2-455a-adeb-91fff0c9b238
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=521964671 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_stress_all_with_rand_reset.521964671
Directory /workspace/22.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_mux.31410467
Short name T1
Test name
Test status
Simulation time 623074693 ps
CPU time 12.32 seconds
Started Jun 07 07:30:29 PM PDT 24
Finished Jun 07 07:30:44 PM PDT 24
Peak memory 218724 kb
Host smart-7c3c4ee8-8f10-4df2-b907-ba8879338e66
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31410467 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_mux.31410467
Directory /workspace/17.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/9.lc_ctrl_alert_test.1214941790
Short name T88
Test name
Test status
Simulation time 32088561 ps
CPU time 1.16 seconds
Started Jun 07 07:30:00 PM PDT 24
Finished Jun 07 07:30:04 PM PDT 24
Peak memory 209420 kb
Host smart-a7bdab94-2af7-457f-a110-21a14508859a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214941790 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_alert_test.1214941790
Directory /workspace/9.lc_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.515035327
Short name T122
Test name
Test status
Simulation time 3896543620 ps
CPU time 20.73 seconds
Started Jun 07 07:18:30 PM PDT 24
Finished Jun 07 07:18:57 PM PDT 24
Peak memory 209916 kb
Host smart-96d07f0b-eeea-4c04-909a-4c6f68fd9623
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515035327 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 2.lc_ctrl_jtag_csr_aliasing.515035327
Directory /workspace/2.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.3741939483
Short name T193
Test name
Test status
Simulation time 19435474 ps
CPU time 0.9 seconds
Started Jun 07 07:18:50 PM PDT 24
Finished Jun 07 07:18:56 PM PDT 24
Peak memory 209696 kb
Host smart-ac1cf369-1e6b-49f9-9206-19b38544f39f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741939483 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_csr_rw.3741939483
Directory /workspace/5.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/default/9.lc_ctrl_stress_all_with_rand_reset.4039119955
Short name T44
Test name
Test status
Simulation time 155607197925 ps
CPU time 801.09 seconds
Started Jun 07 07:30:01 PM PDT 24
Finished Jun 07 07:43:25 PM PDT 24
Peak memory 422608 kb
Host smart-dd7f6ba4-56f5-454e-977f-b696ef1f8f65
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4039119955 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_stress_all_with_rand_reset.4039119955
Directory /workspace/9.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.536570542
Short name T135
Test name
Test status
Simulation time 509322236 ps
CPU time 4.24 seconds
Started Jun 07 07:19:09 PM PDT 24
Finished Jun 07 07:19:22 PM PDT 24
Peak memory 221920 kb
Host smart-f5cf1c7d-953f-4c12-beb3-0e46ecf37f8f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536570542 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_intg_e
rr.536570542
Directory /workspace/8.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/4.lc_ctrl_stress_all.2814085850
Short name T17
Test name
Test status
Simulation time 44223297340 ps
CPU time 176.65 seconds
Started Jun 07 07:29:28 PM PDT 24
Finished Jun 07 07:32:28 PM PDT 24
Peak memory 308772 kb
Host smart-3b039420-7307-44d3-ba75-828dbc29c859
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814085850 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.lc_ctrl_stress_all.2814085850
Directory /workspace/4.lc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.1192656805
Short name T136
Test name
Test status
Simulation time 554978924 ps
CPU time 4.56 seconds
Started Jun 07 07:19:20 PM PDT 24
Finished Jun 07 07:19:41 PM PDT 24
Peak memory 218128 kb
Host smart-40605123-ba66-432b-84c5-b60cf0493fae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192656805 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_intg
_err.1192656805
Directory /workspace/12.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/35.lc_ctrl_security_escalation.332027795
Short name T326
Test name
Test status
Simulation time 1174210561 ps
CPU time 11.75 seconds
Started Jun 07 07:31:35 PM PDT 24
Finished Jun 07 07:31:48 PM PDT 24
Peak memory 225888 kb
Host smart-6a01359f-a6f9-4af2-8b8e-6bfde9e297ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332027795 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_security_escalation.332027795
Directory /workspace/35.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all.3904183023
Short name T109
Test name
Test status
Simulation time 4270300219 ps
CPU time 118.23 seconds
Started Jun 07 07:32:19 PM PDT 24
Finished Jun 07 07:34:22 PM PDT 24
Peak memory 267848 kb
Host smart-702e384e-0464-412e-9e84-937611370632
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904183023 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.lc_ctrl_stress_all.3904183023
Directory /workspace/48.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all_with_rand_reset.3401056563
Short name T113
Test name
Test status
Simulation time 140418963382 ps
CPU time 1189.02 seconds
Started Jun 07 07:32:17 PM PDT 24
Finished Jun 07 07:52:12 PM PDT 24
Peak memory 576964 kb
Host smart-985991b4-d4d5-4301-9607-776c761cfae1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3401056563 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_stress_all_with_rand_reset.3401056563
Directory /workspace/48.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.1079842274
Short name T132
Test name
Test status
Simulation time 1111875261 ps
CPU time 3.07 seconds
Started Jun 07 07:18:31 PM PDT 24
Finished Jun 07 07:18:40 PM PDT 24
Peak memory 223128 kb
Host smart-5d761d25-dba0-4379-a8d1-7eb4331b3ae5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079842274 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_intg_
err.1079842274
Directory /workspace/2.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.2749108390
Short name T141
Test name
Test status
Simulation time 288527181 ps
CPU time 2.62 seconds
Started Jun 07 07:18:49 PM PDT 24
Finished Jun 07 07:18:57 PM PDT 24
Peak memory 218148 kb
Host smart-a01be2d2-ed3f-4def-a2e3-ca26af174e63
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749108390 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_intg_
err.2749108390
Directory /workspace/5.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.1176334578
Short name T144
Test name
Test status
Simulation time 48553731 ps
CPU time 0.93 seconds
Started Jun 07 07:18:17 PM PDT 24
Finished Jun 07 07:18:27 PM PDT 24
Peak memory 209684 kb
Host smart-3e2967af-1a17-4226-9959-18287bafdf5a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176334578 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl
_same_csr_outstanding.1176334578
Directory /workspace/0.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/8.lc_ctrl_claim_transition_if.1161546263
Short name T2
Test name
Test status
Simulation time 17225429 ps
CPU time 0.95 seconds
Started Jun 07 07:29:43 PM PDT 24
Finished Jun 07 07:29:47 PM PDT 24
Peak memory 209424 kb
Host smart-c36ab55a-72b6-4937-bc63-a488ae7a54ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161546263 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_claim_transition_if.1161546263
Directory /workspace/8.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.913346633
Short name T126
Test name
Test status
Simulation time 287091844 ps
CPU time 2.48 seconds
Started Jun 07 07:18:14 PM PDT 24
Finished Jun 07 07:18:27 PM PDT 24
Peak memory 222608 kb
Host smart-550d8e62-1ae3-4f35-9229-1c3eaedb3c03
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913346633 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_intg_e
rr.913346633
Directory /workspace/0.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.2504764691
Short name T130
Test name
Test status
Simulation time 844405744 ps
CPU time 3.99 seconds
Started Jun 07 07:18:17 PM PDT 24
Finished Jun 07 07:18:30 PM PDT 24
Peak memory 218152 kb
Host smart-a9d2d66e-44e9-4c72-8b60-f1db18fd73ed
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504764691 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_errors.2504764691
Directory /workspace/1.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.57207488
Short name T128
Test name
Test status
Simulation time 240168055 ps
CPU time 4.24 seconds
Started Jun 07 07:19:31 PM PDT 24
Finished Jun 07 07:19:55 PM PDT 24
Peak memory 218116 kb
Host smart-37a3eb37-7348-47ed-a644-8ad1b256d37f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57207488 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_intg_e
rr.57207488
Directory /workspace/19.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.3518040663
Short name T118
Test name
Test status
Simulation time 101329701 ps
CPU time 4.1 seconds
Started Jun 07 07:18:28 PM PDT 24
Finished Jun 07 07:18:39 PM PDT 24
Peak memory 218144 kb
Host smart-7e54ae00-103d-4f00-b138-dc1827d0dbab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518040663 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_intg_
err.3518040663
Directory /workspace/3.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_claim_transition_if.1475219221
Short name T209
Test name
Test status
Simulation time 10316940 ps
CPU time 0.78 seconds
Started Jun 07 07:28:59 PM PDT 24
Finished Jun 07 07:29:03 PM PDT 24
Peak memory 209420 kb
Host smart-cbc83319-8239-42ff-b4ad-6f5ae73664c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475219221 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_claim_transition_if.1475219221
Directory /workspace/0.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/1.lc_ctrl_claim_transition_if.386478177
Short name T211
Test name
Test status
Simulation time 17661476 ps
CPU time 1 seconds
Started Jun 07 07:29:10 PM PDT 24
Finished Jun 07 07:29:15 PM PDT 24
Peak memory 209376 kb
Host smart-6c0bf6e1-9059-4ade-ae60-d182a081b0ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386478177 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_claim_transition_if.386478177
Directory /workspace/1.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_mubi.1012514517
Short name T61
Test name
Test status
Simulation time 2937183697 ps
CPU time 20.14 seconds
Started Jun 07 07:29:57 PM PDT 24
Finished Jun 07 07:30:20 PM PDT 24
Peak memory 226568 kb
Host smart-0b517c4b-1335-41d2-9824-5eff4e468b1f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012514517 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_mubi.1012514517
Directory /workspace/10.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/3.lc_ctrl_claim_transition_if.3812898900
Short name T212
Test name
Test status
Simulation time 19137145 ps
CPU time 0.95 seconds
Started Jun 07 07:29:22 PM PDT 24
Finished Jun 07 07:29:26 PM PDT 24
Peak memory 209440 kb
Host smart-3bbcb345-0bb7-4a17-8c64-e1f531da9ae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812898900 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_claim_transition_if.3812898900
Directory /workspace/3.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/4.lc_ctrl_claim_transition_if.1740935284
Short name T171
Test name
Test status
Simulation time 68345153 ps
CPU time 0.82 seconds
Started Jun 07 07:29:24 PM PDT 24
Finished Jun 07 07:29:28 PM PDT 24
Peak memory 209484 kb
Host smart-300d4ff6-20ee-4337-823a-464d2d349a91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740935284 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_claim_transition_if.1740935284
Directory /workspace/4.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/7.lc_ctrl_claim_transition_if.429223745
Short name T210
Test name
Test status
Simulation time 13139213 ps
CPU time 0.84 seconds
Started Jun 07 07:29:46 PM PDT 24
Finished Jun 07 07:29:50 PM PDT 24
Peak memory 209348 kb
Host smart-88f14f78-3abb-45b5-9f21-17f4973d3275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429223745 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_claim_transition_if.429223745
Directory /workspace/7.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all.3940869707
Short name T7
Test name
Test status
Simulation time 2673837232 ps
CPU time 51.01 seconds
Started Jun 07 07:31:13 PM PDT 24
Finished Jun 07 07:32:07 PM PDT 24
Peak memory 225252 kb
Host smart-d3ffecc3-2b2c-42a0-af5b-1cc35db22968
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940869707 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.lc_ctrl_stress_all.3940869707
Directory /workspace/27.lc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.3293950873
Short name T137
Test name
Test status
Simulation time 46686606 ps
CPU time 2.25 seconds
Started Jun 07 07:18:19 PM PDT 24
Finished Jun 07 07:18:30 PM PDT 24
Peak memory 218208 kb
Host smart-1bd98779-6518-4227-a2b5-e2b9a4eb0178
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293950873 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_intg_
err.3293950873
Directory /workspace/1.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.3604006194
Short name T127
Test name
Test status
Simulation time 115805682 ps
CPU time 3.05 seconds
Started Jun 07 07:19:24 PM PDT 24
Finished Jun 07 07:19:45 PM PDT 24
Peak memory 222408 kb
Host smart-ad317993-27d7-432f-a765-fa9e4d3d78cd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604006194 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_intg
_err.3604006194
Directory /workspace/11.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.257314746
Short name T131
Test name
Test status
Simulation time 262882265 ps
CPU time 2.65 seconds
Started Jun 07 07:19:19 PM PDT 24
Finished Jun 07 07:19:39 PM PDT 24
Peak memory 218188 kb
Host smart-4d1c5e7a-93ca-4df8-8034-1b2046e42db6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257314746 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_intg_
err.257314746
Directory /workspace/15.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.1108429452
Short name T139
Test name
Test status
Simulation time 419510173 ps
CPU time 2.66 seconds
Started Jun 07 07:19:10 PM PDT 24
Finished Jun 07 07:19:23 PM PDT 24
Peak memory 222664 kb
Host smart-b9c600a7-a597-41a2-a399-8c0dc95d45bb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108429452 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_intg_
err.1108429452
Directory /workspace/7.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/1.lc_ctrl_errors.1104296654
Short name T47
Test name
Test status
Simulation time 2049060986 ps
CPU time 24.23 seconds
Started Jun 07 07:29:05 PM PDT 24
Finished Jun 07 07:29:34 PM PDT 24
Peak memory 218632 kb
Host smart-a3a94f50-7b93-4e67-8101-749132bdcfbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104296654 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_errors.1104296654
Directory /workspace/1.lc_ctrl_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_errors.682029994
Short name T38
Test name
Test status
Simulation time 699189036 ps
CPU time 10.1 seconds
Started Jun 07 07:30:14 PM PDT 24
Finished Jun 07 07:30:27 PM PDT 24
Peak memory 218728 kb
Host smart-a4e3d3fd-7335-4f85-91e7-9dad6d182e7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682029994 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_errors.682029994
Directory /workspace/14.lc_ctrl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.1431559950
Short name T199
Test name
Test status
Simulation time 17993031 ps
CPU time 1.32 seconds
Started Jun 07 07:18:19 PM PDT 24
Finished Jun 07 07:18:30 PM PDT 24
Peak memory 209964 kb
Host smart-27d292e3-a718-446a-8165-1997550f17bc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431559950 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_aliasin
g.1431559950
Directory /workspace/0.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.460356099
Short name T874
Test name
Test status
Simulation time 65736268 ps
CPU time 2.07 seconds
Started Jun 07 07:18:18 PM PDT 24
Finished Jun 07 07:18:29 PM PDT 24
Peak memory 209068 kb
Host smart-cec544aa-a366-4132-a440-1888a93fb562
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460356099 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_bit_bash
.460356099
Directory /workspace/0.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.2343708671
Short name T989
Test name
Test status
Simulation time 142170153 ps
CPU time 1 seconds
Started Jun 07 07:18:10 PM PDT 24
Finished Jun 07 07:18:22 PM PDT 24
Peak memory 210492 kb
Host smart-2ab0ee14-5076-4fe2-81bd-45bb7ed88e1c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343708671 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_hw_rese
t.2343708671
Directory /workspace/0.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.3000181162
Short name T940
Test name
Test status
Simulation time 38321877 ps
CPU time 1.44 seconds
Started Jun 07 07:18:19 PM PDT 24
Finished Jun 07 07:18:30 PM PDT 24
Peak memory 218256 kb
Host smart-a9ab62a1-58d8-4c39-ac2a-83c48eb596df
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000181162 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 0.lc_ctrl_csr_mem_rw_with_rand_reset.3000181162
Directory /workspace/0.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.555924803
Short name T905
Test name
Test status
Simulation time 19746937 ps
CPU time 1.01 seconds
Started Jun 07 07:18:14 PM PDT 24
Finished Jun 07 07:18:25 PM PDT 24
Peak memory 209636 kb
Host smart-fdce23d3-23df-4db6-b92b-44e0d9752aa8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555924803 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_rw.555924803
Directory /workspace/0.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.817300225
Short name T936
Test name
Test status
Simulation time 335159739 ps
CPU time 1.5 seconds
Started Jun 07 07:18:10 PM PDT 24
Finished Jun 07 07:18:23 PM PDT 24
Peak memory 209720 kb
Host smart-5118bcd6-e27b-46f9-a846-4da050f97f12
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817300225 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 0.lc_ctrl_jtag_alert_test.817300225
Directory /workspace/0.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.4274298904
Short name T939
Test name
Test status
Simulation time 1146043537 ps
CPU time 12.69 seconds
Started Jun 07 07:18:12 PM PDT 24
Finished Jun 07 07:18:35 PM PDT 24
Peak memory 209540 kb
Host smart-c6badc8e-ced5-4497-8b1a-3eeaaa05e0e9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274298904 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_aliasing.4274298904
Directory /workspace/0.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.2090234821
Short name T878
Test name
Test status
Simulation time 23696913206 ps
CPU time 49.4 seconds
Started Jun 07 07:18:11 PM PDT 24
Finished Jun 07 07:19:11 PM PDT 24
Peak memory 217936 kb
Host smart-fa9864b3-d4dc-430b-9aa3-5dabfef4faed
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090234821 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_bit_bash.2090234821
Directory /workspace/0.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.2833758392
Short name T930
Test name
Test status
Simulation time 137020855 ps
CPU time 3.79 seconds
Started Jun 07 07:18:08 PM PDT 24
Finished Jun 07 07:18:24 PM PDT 24
Peak memory 218004 kb
Host smart-2f96b982-1d10-4f55-8b7b-29ac05e61244
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833758392 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_hw_reset.2833758392
Directory /workspace/0.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.925270162
Short name T889
Test name
Test status
Simulation time 201933425 ps
CPU time 1.94 seconds
Started Jun 07 07:18:13 PM PDT 24
Finished Jun 07 07:18:25 PM PDT 24
Peak memory 218172 kb
Host smart-a57226e4-3d92-47b2-8e23-96866105eab9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925270
162 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.925270162
Directory /workspace/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.979478333
Short name T922
Test name
Test status
Simulation time 173291561 ps
CPU time 1.63 seconds
Started Jun 07 07:18:12 PM PDT 24
Finished Jun 07 07:18:24 PM PDT 24
Peak memory 217840 kb
Host smart-092218ec-0add-4223-9f41-65b669f97138
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979478333 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.lc_ctrl_jtag_csr_rw.979478333
Directory /workspace/0.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.816376109
Short name T970
Test name
Test status
Simulation time 44231850 ps
CPU time 1.09 seconds
Started Jun 07 07:18:14 PM PDT 24
Finished Jun 07 07:18:25 PM PDT 24
Peak memory 209940 kb
Host smart-3273b0c4-8614-4f56-a0de-2b8514610d9a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816376109 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.lc_ctrl_jtag_same_csr_outstanding.816376109
Directory /workspace/0.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.1972057104
Short name T116
Test name
Test status
Simulation time 59164317 ps
CPU time 1.94 seconds
Started Jun 07 07:18:13 PM PDT 24
Finished Jun 07 07:18:25 PM PDT 24
Peak memory 218096 kb
Host smart-17311eb0-ff80-4f53-988a-de69c8af9adb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972057104 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_errors.1972057104
Directory /workspace/0.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.3809992651
Short name T977
Test name
Test status
Simulation time 62727947 ps
CPU time 1.18 seconds
Started Jun 07 07:18:19 PM PDT 24
Finished Jun 07 07:18:29 PM PDT 24
Peak memory 217836 kb
Host smart-2a8902f9-9c81-44fe-a858-0d1135f9b8bf
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809992651 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_aliasin
g.3809992651
Directory /workspace/1.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.2318106653
Short name T158
Test name
Test status
Simulation time 50278201 ps
CPU time 1.99 seconds
Started Jun 07 07:18:21 PM PDT 24
Finished Jun 07 07:18:32 PM PDT 24
Peak memory 209788 kb
Host smart-359cbcec-57e3-4a02-a2d3-4888b4e75ea7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318106653 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_bit_bas
h.2318106653
Directory /workspace/1.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.1147293434
Short name T195
Test name
Test status
Simulation time 35943085 ps
CPU time 1.02 seconds
Started Jun 07 07:18:16 PM PDT 24
Finished Jun 07 07:18:27 PM PDT 24
Peak memory 210788 kb
Host smart-0df36448-cd6a-4ccb-9b56-431f98b397ce
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147293434 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_hw_rese
t.1147293434
Directory /workspace/1.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.3929766917
Short name T917
Test name
Test status
Simulation time 80341823 ps
CPU time 1.44 seconds
Started Jun 07 07:18:21 PM PDT 24
Finished Jun 07 07:18:31 PM PDT 24
Peak memory 218324 kb
Host smart-b618852c-dea2-445f-acb9-4f41480c4391
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929766917 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 1.lc_ctrl_csr_mem_rw_with_rand_reset.3929766917
Directory /workspace/1.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.302247146
Short name T198
Test name
Test status
Simulation time 11776294 ps
CPU time 0.99 seconds
Started Jun 07 07:18:18 PM PDT 24
Finished Jun 07 07:18:28 PM PDT 24
Peak memory 209836 kb
Host smart-0c726291-020d-4fe4-b0ba-8acee0d2a734
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302247146 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_rw.302247146
Directory /workspace/1.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.2595020175
Short name T881
Test name
Test status
Simulation time 93376648 ps
CPU time 1.8 seconds
Started Jun 07 07:18:27 PM PDT 24
Finished Jun 07 07:18:36 PM PDT 24
Peak memory 209760 kb
Host smart-1809c33e-524f-453e-a961-e35cbcf529fe
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595020175 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.lc_ctrl_jtag_alert_test.2595020175
Directory /workspace/1.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.1828039761
Short name T997
Test name
Test status
Simulation time 1213859087 ps
CPU time 3.16 seconds
Started Jun 07 07:18:21 PM PDT 24
Finished Jun 07 07:18:33 PM PDT 24
Peak memory 209464 kb
Host smart-b89f63a2-3062-41c6-88ed-abcf9c174888
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828039761 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_aliasing.1828039761
Directory /workspace/1.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.2027940009
Short name T980
Test name
Test status
Simulation time 421493739 ps
CPU time 5.35 seconds
Started Jun 07 07:18:19 PM PDT 24
Finished Jun 07 07:18:34 PM PDT 24
Peak memory 209780 kb
Host smart-dd065df6-d6d8-4866-84a1-70a516df628b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027940009 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_bit_bash.2027940009
Directory /workspace/1.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.487534650
Short name T990
Test name
Test status
Simulation time 184918455 ps
CPU time 2.42 seconds
Started Jun 07 07:18:19 PM PDT 24
Finished Jun 07 07:18:31 PM PDT 24
Peak memory 218032 kb
Host smart-da17ce03-2085-4705-8cec-e4e6bce00e22
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487534650 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 1.lc_ctrl_jtag_csr_hw_reset.487534650
Directory /workspace/1.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1396690646
Short name T887
Test name
Test status
Simulation time 50331209 ps
CPU time 2.1 seconds
Started Jun 07 07:18:23 PM PDT 24
Finished Jun 07 07:18:34 PM PDT 24
Peak memory 219292 kb
Host smart-d413f167-22a0-42db-ad8a-00cdc8873d21
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139669
0646 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1396690646
Directory /workspace/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.804806958
Short name T901
Test name
Test status
Simulation time 67827414 ps
CPU time 2.12 seconds
Started Jun 07 07:18:22 PM PDT 24
Finished Jun 07 07:18:33 PM PDT 24
Peak memory 217856 kb
Host smart-3b032d40-4a95-4cf7-a4e2-148d28bbe8b7
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804806958 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.lc_ctrl_jtag_csr_rw.804806958
Directory /workspace/1.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.2690552162
Short name T202
Test name
Test status
Simulation time 26311431 ps
CPU time 1.41 seconds
Started Jun 07 07:18:21 PM PDT 24
Finished Jun 07 07:18:31 PM PDT 24
Peak memory 218124 kb
Host smart-40019ccc-5b86-402b-b4fd-950c0f45c980
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690552162 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.lc_ctrl_jtag_same_csr_outstanding.2690552162
Directory /workspace/1.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.4239606795
Short name T204
Test name
Test status
Simulation time 22692689 ps
CPU time 1.5 seconds
Started Jun 07 07:18:21 PM PDT 24
Finished Jun 07 07:18:31 PM PDT 24
Peak memory 212096 kb
Host smart-88c5a7b1-eac6-43c2-b276-5fcb910ceedd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239606795 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl
_same_csr_outstanding.4239606795
Directory /workspace/1.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.63346856
Short name T182
Test name
Test status
Simulation time 22077615 ps
CPU time 1.02 seconds
Started Jun 07 07:19:19 PM PDT 24
Finished Jun 07 07:19:36 PM PDT 24
Peak memory 219360 kb
Host smart-c4bd1ce8-a82e-4303-9dde-c390b5aa8734
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63346856 -assert nopostproc +UVM_TESTNAME=l
c_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.lc_ctrl_csr_mem_rw_with_rand_reset.63346856
Directory /workspace/10.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.2400525466
Short name T967
Test name
Test status
Simulation time 39846571 ps
CPU time 0.86 seconds
Started Jun 07 07:19:21 PM PDT 24
Finished Jun 07 07:19:39 PM PDT 24
Peak memory 209700 kb
Host smart-3490e239-6c96-4455-b7d7-186fd20993af
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400525466 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_csr_rw.2400525466
Directory /workspace/10.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.4098840069
Short name T982
Test name
Test status
Simulation time 65352943 ps
CPU time 1.46 seconds
Started Jun 07 07:19:18 PM PDT 24
Finished Jun 07 07:19:35 PM PDT 24
Peak memory 209888 kb
Host smart-e367443f-6315-44fa-bea1-88a6d2ecabc0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098840069 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctr
l_same_csr_outstanding.4098840069
Directory /workspace/10.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.2694330728
Short name T921
Test name
Test status
Simulation time 609260337 ps
CPU time 3.14 seconds
Started Jun 07 07:19:23 PM PDT 24
Finished Jun 07 07:19:44 PM PDT 24
Peak memory 219052 kb
Host smart-3df8b93c-224e-419b-9fd0-c6d710ff13cf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694330728 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_errors.2694330728
Directory /workspace/10.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.3015771844
Short name T140
Test name
Test status
Simulation time 117598901 ps
CPU time 4.13 seconds
Started Jun 07 07:19:20 PM PDT 24
Finished Jun 07 07:19:40 PM PDT 24
Peak memory 218244 kb
Host smart-be1a738d-9915-451d-9e2a-aa04742aaf60
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015771844 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_intg
_err.3015771844
Directory /workspace/10.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.4094136128
Short name T948
Test name
Test status
Simulation time 155968744 ps
CPU time 1.44 seconds
Started Jun 07 07:19:19 PM PDT 24
Finished Jun 07 07:19:36 PM PDT 24
Peak memory 220256 kb
Host smart-8230a78a-121f-4129-a6f0-57b2951bbc53
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094136128 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 11.lc_ctrl_csr_mem_rw_with_rand_reset.4094136128
Directory /workspace/11.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.319235449
Short name T884
Test name
Test status
Simulation time 13729787 ps
CPU time 0.83 seconds
Started Jun 07 07:19:19 PM PDT 24
Finished Jun 07 07:19:37 PM PDT 24
Peak memory 209288 kb
Host smart-664b448c-5f73-44da-bb49-8e78d8778655
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319235449 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_csr_rw.319235449
Directory /workspace/11.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.489788529
Short name T902
Test name
Test status
Simulation time 43471690 ps
CPU time 1.45 seconds
Started Jun 07 07:19:19 PM PDT 24
Finished Jun 07 07:19:37 PM PDT 24
Peak memory 209560 kb
Host smart-dae49d10-cea1-4573-bd7e-ee30ec48ed76
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489788529 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl
_same_csr_outstanding.489788529
Directory /workspace/11.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.1714707148
Short name T979
Test name
Test status
Simulation time 41463267 ps
CPU time 2.38 seconds
Started Jun 07 07:19:19 PM PDT 24
Finished Jun 07 07:19:37 PM PDT 24
Peak memory 219124 kb
Host smart-b48332e6-5ecd-452f-ac2e-815cf8b2ab85
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714707148 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_errors.1714707148
Directory /workspace/11.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.2604152697
Short name T892
Test name
Test status
Simulation time 25307499 ps
CPU time 1.28 seconds
Started Jun 07 07:19:22 PM PDT 24
Finished Jun 07 07:19:42 PM PDT 24
Peak memory 220060 kb
Host smart-84e3fd13-4a7a-46fc-9f48-ac54100ccbee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604152697 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 12.lc_ctrl_csr_mem_rw_with_rand_reset.2604152697
Directory /workspace/12.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.259569848
Short name T121
Test name
Test status
Simulation time 27150576 ps
CPU time 1.07 seconds
Started Jun 07 07:19:19 PM PDT 24
Finished Jun 07 07:19:37 PM PDT 24
Peak memory 209620 kb
Host smart-b3ba70a6-4fbb-4c17-ba17-b23382b5c13e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259569848 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_csr_rw.259569848
Directory /workspace/12.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.715135095
Short name T994
Test name
Test status
Simulation time 37281070 ps
CPU time 1.24 seconds
Started Jun 07 07:19:19 PM PDT 24
Finished Jun 07 07:19:36 PM PDT 24
Peak memory 212004 kb
Host smart-a7871783-7fd9-47ba-ac5c-e4bfe6aeac0f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715135095 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl
_same_csr_outstanding.715135095
Directory /workspace/12.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.574263070
Short name T123
Test name
Test status
Simulation time 264356838 ps
CPU time 3.38 seconds
Started Jun 07 07:19:19 PM PDT 24
Finished Jun 07 07:19:40 PM PDT 24
Peak memory 218188 kb
Host smart-740a2f25-5361-430a-a8a0-b6aad135451d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574263070 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_errors.574263070
Directory /workspace/12.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.1338360085
Short name T958
Test name
Test status
Simulation time 37031664 ps
CPU time 1.41 seconds
Started Jun 07 07:19:20 PM PDT 24
Finished Jun 07 07:19:38 PM PDT 24
Peak memory 218296 kb
Host smart-27f845a2-3200-402e-960a-1966609941ca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338360085 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 13.lc_ctrl_csr_mem_rw_with_rand_reset.1338360085
Directory /workspace/13.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.1612415658
Short name T960
Test name
Test status
Simulation time 46559782 ps
CPU time 0.83 seconds
Started Jun 07 07:19:22 PM PDT 24
Finished Jun 07 07:19:41 PM PDT 24
Peak memory 209716 kb
Host smart-3ede4e69-9bcc-4497-aa1a-4ee8cd979386
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612415658 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_csr_rw.1612415658
Directory /workspace/13.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.441642278
Short name T937
Test name
Test status
Simulation time 130104870 ps
CPU time 1.16 seconds
Started Jun 07 07:19:25 PM PDT 24
Finished Jun 07 07:19:43 PM PDT 24
Peak memory 209932 kb
Host smart-55e2537c-2981-4f83-bf15-e3f3859a9451
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441642278 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl
_same_csr_outstanding.441642278
Directory /workspace/13.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.650397
Short name T928
Test name
Test status
Simulation time 84724827 ps
CPU time 2.39 seconds
Started Jun 07 07:19:21 PM PDT 24
Finished Jun 07 07:19:40 PM PDT 24
Peak memory 218152 kb
Host smart-bedebb80-71a2-4709-b012-1ec3fddaa524
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650397 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_errors.650397
Directory /workspace/13.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.311667641
Short name T213
Test name
Test status
Simulation time 90674268 ps
CPU time 1.92 seconds
Started Jun 07 07:19:20 PM PDT 24
Finished Jun 07 07:19:38 PM PDT 24
Peak memory 221888 kb
Host smart-19fcd942-86db-4d84-b4f4-27da02827764
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311667641 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_intg_
err.311667641
Directory /workspace/13.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.3143094809
Short name T173
Test name
Test status
Simulation time 62318435 ps
CPU time 1.34 seconds
Started Jun 07 07:19:20 PM PDT 24
Finished Jun 07 07:19:38 PM PDT 24
Peak memory 218292 kb
Host smart-821c4622-c357-4a9f-a47e-8e474306de9b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143094809 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 14.lc_ctrl_csr_mem_rw_with_rand_reset.3143094809
Directory /workspace/14.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.3598089652
Short name T992
Test name
Test status
Simulation time 35944687 ps
CPU time 0.87 seconds
Started Jun 07 07:19:21 PM PDT 24
Finished Jun 07 07:19:39 PM PDT 24
Peak memory 209732 kb
Host smart-6deae320-6519-48cf-8572-015d0a9f7275
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598089652 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_csr_rw.3598089652
Directory /workspace/14.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.1851408441
Short name T161
Test name
Test status
Simulation time 47882321 ps
CPU time 1.47 seconds
Started Jun 07 07:19:22 PM PDT 24
Finished Jun 07 07:19:40 PM PDT 24
Peak memory 211920 kb
Host smart-5d5cdc5a-5b65-48b6-b38f-ca634c83e860
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851408441 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctr
l_same_csr_outstanding.1851408441
Directory /workspace/14.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.4084720994
Short name T988
Test name
Test status
Simulation time 298522931 ps
CPU time 3.2 seconds
Started Jun 07 07:19:19 PM PDT 24
Finished Jun 07 07:19:38 PM PDT 24
Peak memory 218168 kb
Host smart-1f310b01-7f0b-49a6-b7b5-549fdb157d1c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084720994 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_errors.4084720994
Directory /workspace/14.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.2044729515
Short name T142
Test name
Test status
Simulation time 596183554 ps
CPU time 3.89 seconds
Started Jun 07 07:19:19 PM PDT 24
Finished Jun 07 07:19:38 PM PDT 24
Peak memory 218164 kb
Host smart-f3716efa-af22-49c5-84ca-ed2cecdda5bb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044729515 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_intg
_err.2044729515
Directory /workspace/14.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.3364665499
Short name T914
Test name
Test status
Simulation time 26030748 ps
CPU time 2.16 seconds
Started Jun 07 07:19:25 PM PDT 24
Finished Jun 07 07:19:44 PM PDT 24
Peak memory 218380 kb
Host smart-7fd82cc9-943d-4fd5-b165-4bac77ad4742
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364665499 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 15.lc_ctrl_csr_mem_rw_with_rand_reset.3364665499
Directory /workspace/15.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.4034666857
Short name T205
Test name
Test status
Simulation time 15295076 ps
CPU time 0.86 seconds
Started Jun 07 07:19:19 PM PDT 24
Finished Jun 07 07:19:37 PM PDT 24
Peak memory 209884 kb
Host smart-a27b6dfc-3049-45e2-b3aa-cee7f765a1af
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034666857 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_csr_rw.4034666857
Directory /workspace/15.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.897126342
Short name T947
Test name
Test status
Simulation time 99528952 ps
CPU time 1.48 seconds
Started Jun 07 07:19:25 PM PDT 24
Finished Jun 07 07:19:44 PM PDT 24
Peak memory 209936 kb
Host smart-2a7c929e-d0d0-4359-b995-545af22544c9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897126342 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl
_same_csr_outstanding.897126342
Directory /workspace/15.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.2744546044
Short name T986
Test name
Test status
Simulation time 25097824 ps
CPU time 1.15 seconds
Started Jun 07 07:19:29 PM PDT 24
Finished Jun 07 07:19:50 PM PDT 24
Peak memory 219488 kb
Host smart-d8d17247-bc09-4fe4-be81-4f7b6db8c4fe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744546044 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 16.lc_ctrl_csr_mem_rw_with_rand_reset.2744546044
Directory /workspace/16.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.1978929382
Short name T196
Test name
Test status
Simulation time 43059270 ps
CPU time 0.97 seconds
Started Jun 07 07:19:33 PM PDT 24
Finished Jun 07 07:19:55 PM PDT 24
Peak memory 209508 kb
Host smart-df31a76f-f248-40fa-9308-9093170c097d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978929382 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_csr_rw.1978929382
Directory /workspace/16.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.4080382938
Short name T971
Test name
Test status
Simulation time 74650210 ps
CPU time 1.24 seconds
Started Jun 07 07:19:31 PM PDT 24
Finished Jun 07 07:19:52 PM PDT 24
Peak memory 210008 kb
Host smart-9f1eb5f6-25f6-4b20-bee7-f02e8dc6e5c0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080382938 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctr
l_same_csr_outstanding.4080382938
Directory /workspace/16.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.1767042406
Short name T932
Test name
Test status
Simulation time 76053529 ps
CPU time 3.2 seconds
Started Jun 07 07:19:20 PM PDT 24
Finished Jun 07 07:19:40 PM PDT 24
Peak memory 218140 kb
Host smart-7f8b055e-3bf6-4c1b-9f7a-738b1682c88d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767042406 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_errors.1767042406
Directory /workspace/16.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.3397056132
Short name T138
Test name
Test status
Simulation time 113795600 ps
CPU time 2.65 seconds
Started Jun 07 07:19:18 PM PDT 24
Finished Jun 07 07:19:35 PM PDT 24
Peak memory 218108 kb
Host smart-f4a9f931-397f-4bc6-9dc1-6a2f880c6c0f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397056132 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_intg
_err.3397056132
Directory /workspace/16.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.1283062367
Short name T119
Test name
Test status
Simulation time 115213793 ps
CPU time 1.86 seconds
Started Jun 07 07:19:31 PM PDT 24
Finished Jun 07 07:19:52 PM PDT 24
Peak memory 225536 kb
Host smart-2211f3db-fd2c-4ffd-94c1-7decdd0f1923
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283062367 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 17.lc_ctrl_csr_mem_rw_with_rand_reset.1283062367
Directory /workspace/17.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.352755674
Short name T954
Test name
Test status
Simulation time 11020578 ps
CPU time 0.97 seconds
Started Jun 07 07:19:28 PM PDT 24
Finished Jun 07 07:19:48 PM PDT 24
Peak memory 209888 kb
Host smart-4f9ec5fb-cde1-4887-8f2c-6317dc8b1079
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352755674 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_csr_rw.352755674
Directory /workspace/17.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.191885690
Short name T203
Test name
Test status
Simulation time 54703588 ps
CPU time 1.01 seconds
Started Jun 07 07:19:31 PM PDT 24
Finished Jun 07 07:19:52 PM PDT 24
Peak memory 209912 kb
Host smart-eea21c00-049e-49d8-9273-24af75e8be19
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191885690 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl
_same_csr_outstanding.191885690
Directory /workspace/17.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.3775307686
Short name T995
Test name
Test status
Simulation time 47323492 ps
CPU time 1.67 seconds
Started Jun 07 07:19:32 PM PDT 24
Finished Jun 07 07:19:54 PM PDT 24
Peak memory 218104 kb
Host smart-16fb0870-2ed3-424c-a586-c16b501bea02
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775307686 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_errors.3775307686
Directory /workspace/17.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.2091156896
Short name T987
Test name
Test status
Simulation time 18695055 ps
CPU time 1.55 seconds
Started Jun 07 07:19:30 PM PDT 24
Finished Jun 07 07:19:50 PM PDT 24
Peak memory 218268 kb
Host smart-098a7596-6f0a-4e45-8ab5-c3f90ce87904
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091156896 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 18.lc_ctrl_csr_mem_rw_with_rand_reset.2091156896
Directory /workspace/18.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.2702922507
Short name T194
Test name
Test status
Simulation time 38492765 ps
CPU time 0.86 seconds
Started Jun 07 07:19:34 PM PDT 24
Finished Jun 07 07:19:55 PM PDT 24
Peak memory 209612 kb
Host smart-78d9c827-0b9d-4fb4-9deb-74c56c047801
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702922507 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_csr_rw.2702922507
Directory /workspace/18.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.3674912972
Short name T985
Test name
Test status
Simulation time 91275625 ps
CPU time 1.25 seconds
Started Jun 07 07:19:30 PM PDT 24
Finished Jun 07 07:19:50 PM PDT 24
Peak memory 212000 kb
Host smart-f8153b8c-ff5d-42d0-baeb-1e66b312a94b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674912972 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctr
l_same_csr_outstanding.3674912972
Directory /workspace/18.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.3836228719
Short name T133
Test name
Test status
Simulation time 21496459 ps
CPU time 1.73 seconds
Started Jun 07 07:19:35 PM PDT 24
Finished Jun 07 07:19:58 PM PDT 24
Peak memory 218164 kb
Host smart-f504016e-8bbf-4794-8263-e89b7a584a3d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836228719 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_errors.3836228719
Directory /workspace/18.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.2150485918
Short name T945
Test name
Test status
Simulation time 212445309 ps
CPU time 2.79 seconds
Started Jun 07 07:19:30 PM PDT 24
Finished Jun 07 07:19:52 PM PDT 24
Peak memory 218136 kb
Host smart-a195218b-c6e4-45c7-975e-9f7232844f4e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150485918 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_intg
_err.2150485918
Directory /workspace/18.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.3438400948
Short name T172
Test name
Test status
Simulation time 116285831 ps
CPU time 1.37 seconds
Started Jun 07 07:19:32 PM PDT 24
Finished Jun 07 07:19:54 PM PDT 24
Peak memory 219916 kb
Host smart-207a5983-452e-43fb-95a9-681746f8f41b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438400948 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 19.lc_ctrl_csr_mem_rw_with_rand_reset.3438400948
Directory /workspace/19.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.1151301013
Short name T192
Test name
Test status
Simulation time 39116454 ps
CPU time 0.97 seconds
Started Jun 07 07:19:28 PM PDT 24
Finished Jun 07 07:19:48 PM PDT 24
Peak memory 209592 kb
Host smart-644fdf17-e3d1-4c19-bc97-a052adcfb9af
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151301013 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_csr_rw.1151301013
Directory /workspace/19.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.2412601843
Short name T890
Test name
Test status
Simulation time 20647677 ps
CPU time 1.28 seconds
Started Jun 07 07:19:32 PM PDT 24
Finished Jun 07 07:19:54 PM PDT 24
Peak memory 212236 kb
Host smart-8ca77444-3929-45d1-92cb-11ca6ae28046
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412601843 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctr
l_same_csr_outstanding.2412601843
Directory /workspace/19.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.213002527
Short name T925
Test name
Test status
Simulation time 52967841 ps
CPU time 1.87 seconds
Started Jun 07 07:19:31 PM PDT 24
Finished Jun 07 07:19:52 PM PDT 24
Peak memory 218120 kb
Host smart-c744cbb1-60b0-4550-b88c-6ee6de528224
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213002527 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_errors.213002527
Directory /workspace/19.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.1380451200
Short name T915
Test name
Test status
Simulation time 33059084 ps
CPU time 1.28 seconds
Started Jun 07 07:18:37 PM PDT 24
Finished Jun 07 07:18:43 PM PDT 24
Peak memory 210024 kb
Host smart-344fe710-1a66-4607-9c10-bb6fcf2291b9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380451200 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_aliasin
g.1380451200
Directory /workspace/2.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.3654593
Short name T897
Test name
Test status
Simulation time 266977544 ps
CPU time 1.83 seconds
Started Jun 07 07:18:29 PM PDT 24
Finished Jun 07 07:18:38 PM PDT 24
Peak memory 217288 kb
Host smart-5ea14bac-f0d5-4510-94f8-8566d78b0f39
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654593 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_bit_bash.3654593
Directory /workspace/2.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.2582392536
Short name T946
Test name
Test status
Simulation time 27278136 ps
CPU time 1.12 seconds
Started Jun 07 07:18:31 PM PDT 24
Finished Jun 07 07:18:38 PM PDT 24
Peak memory 210540 kb
Host smart-b4516811-7fd6-4c07-a5b3-c210c7e6038f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582392536 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_hw_rese
t.2582392536
Directory /workspace/2.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.465540348
Short name T899
Test name
Test status
Simulation time 166166780 ps
CPU time 1.56 seconds
Started Jun 07 07:18:37 PM PDT 24
Finished Jun 07 07:18:44 PM PDT 24
Peak memory 219564 kb
Host smart-6037a0be-a84a-48e6-991d-62e989fb6683
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465540348 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 2.lc_ctrl_csr_mem_rw_with_rand_reset.465540348
Directory /workspace/2.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.3770949313
Short name T900
Test name
Test status
Simulation time 100952635 ps
CPU time 0.9 seconds
Started Jun 07 07:18:27 PM PDT 24
Finished Jun 07 07:18:36 PM PDT 24
Peak memory 209884 kb
Host smart-3bbd3e01-14d2-4fd1-ad8e-9fc0fa650ba0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770949313 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_rw.3770949313
Directory /workspace/2.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.259173446
Short name T906
Test name
Test status
Simulation time 65718831 ps
CPU time 1.54 seconds
Started Jun 07 07:18:30 PM PDT 24
Finished Jun 07 07:18:38 PM PDT 24
Peak memory 209720 kb
Host smart-0c91c91d-0297-47b2-8eb4-552721515a02
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259173446 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 2.lc_ctrl_jtag_alert_test.259173446
Directory /workspace/2.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.1598273659
Short name T983
Test name
Test status
Simulation time 3307480800 ps
CPU time 19.34 seconds
Started Jun 07 07:18:29 PM PDT 24
Finished Jun 07 07:18:55 PM PDT 24
Peak memory 209952 kb
Host smart-7ae2b8de-e913-43e0-b1eb-dc3d57854437
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598273659 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_bit_bash.1598273659
Directory /workspace/2.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.2793255149
Short name T968
Test name
Test status
Simulation time 284610485 ps
CPU time 1.94 seconds
Started Jun 07 07:18:30 PM PDT 24
Finished Jun 07 07:18:38 PM PDT 24
Peak memory 218024 kb
Host smart-be6e57a0-b219-4f68-b698-755ca3f7fb41
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793255149 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_hw_reset.2793255149
Directory /workspace/2.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1792419591
Short name T961
Test name
Test status
Simulation time 361941367 ps
CPU time 2.5 seconds
Started Jun 07 07:18:30 PM PDT 24
Finished Jun 07 07:18:39 PM PDT 24
Peak memory 223792 kb
Host smart-08e2fa31-a53c-4972-a39c-03b3d5048b20
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179241
9591 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1792419591
Directory /workspace/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.3629525227
Short name T911
Test name
Test status
Simulation time 33121314 ps
CPU time 1.05 seconds
Started Jun 07 07:18:32 PM PDT 24
Finished Jun 07 07:18:38 PM PDT 24
Peak memory 217948 kb
Host smart-096387be-e832-46a1-a3e3-2e07a07a245e
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629525227 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.lc_ctrl_jtag_csr_rw.3629525227
Directory /workspace/2.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.3619812831
Short name T916
Test name
Test status
Simulation time 22041375 ps
CPU time 1.23 seconds
Started Jun 07 07:18:29 PM PDT 24
Finished Jun 07 07:18:37 PM PDT 24
Peak memory 211896 kb
Host smart-b7e669df-822d-4446-a85c-d7fbc165ed93
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619812831 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.lc_ctrl_jtag_same_csr_outstanding.3619812831
Directory /workspace/2.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.4148052851
Short name T162
Test name
Test status
Simulation time 482562050 ps
CPU time 1.48 seconds
Started Jun 07 07:18:29 PM PDT 24
Finished Jun 07 07:18:37 PM PDT 24
Peak memory 211952 kb
Host smart-31174925-2571-4de1-acaf-be9d226e0968
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148052851 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl
_same_csr_outstanding.4148052851
Directory /workspace/2.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.1386518684
Short name T124
Test name
Test status
Simulation time 54216641 ps
CPU time 1.96 seconds
Started Jun 07 07:18:30 PM PDT 24
Finished Jun 07 07:18:39 PM PDT 24
Peak memory 218236 kb
Host smart-02929703-eadb-4182-962d-c6dfd758c040
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386518684 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_errors.1386518684
Directory /workspace/2.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.1181373702
Short name T879
Test name
Test status
Simulation time 33572641 ps
CPU time 1.43 seconds
Started Jun 07 07:18:42 PM PDT 24
Finished Jun 07 07:18:48 PM PDT 24
Peak memory 217628 kb
Host smart-4d0a5078-2b6e-43a5-9cb5-3757cd8a70c1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181373702 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_aliasin
g.1181373702
Directory /workspace/3.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.2999256690
Short name T872
Test name
Test status
Simulation time 21322560 ps
CPU time 1.16 seconds
Started Jun 07 07:18:43 PM PDT 24
Finished Jun 07 07:18:49 PM PDT 24
Peak memory 209084 kb
Host smart-1eff02fa-5716-4c3f-8ef2-f7902e268d1b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999256690 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_bit_bas
h.2999256690
Directory /workspace/3.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.588100205
Short name T873
Test name
Test status
Simulation time 77075811 ps
CPU time 1 seconds
Started Jun 07 07:18:42 PM PDT 24
Finished Jun 07 07:18:47 PM PDT 24
Peak memory 211980 kb
Host smart-184f4b59-ff0a-4e7f-81da-04a5e1fb3fe5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588100205 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_hw_reset
.588100205
Directory /workspace/3.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.3007043783
Short name T942
Test name
Test status
Simulation time 29963038 ps
CPU time 1.89 seconds
Started Jun 07 07:18:41 PM PDT 24
Finished Jun 07 07:18:47 PM PDT 24
Peak memory 218220 kb
Host smart-3e54c2dd-1a8a-4087-806d-eeb726e03876
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007043783 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 3.lc_ctrl_csr_mem_rw_with_rand_reset.3007043783
Directory /workspace/3.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.2660733081
Short name T955
Test name
Test status
Simulation time 13682244 ps
CPU time 0.94 seconds
Started Jun 07 07:18:39 PM PDT 24
Finished Jun 07 07:18:44 PM PDT 24
Peak memory 209836 kb
Host smart-3db78abe-fc4a-41eb-b184-8cec68dceab6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660733081 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_rw.2660733081
Directory /workspace/3.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.2703219676
Short name T148
Test name
Test status
Simulation time 51277110 ps
CPU time 1.22 seconds
Started Jun 07 07:18:29 PM PDT 24
Finished Jun 07 07:18:37 PM PDT 24
Peak memory 209772 kb
Host smart-e3f5f3bf-8916-4fbc-adac-2764236eb648
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703219676 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.lc_ctrl_jtag_alert_test.2703219676
Directory /workspace/3.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.2100794985
Short name T984
Test name
Test status
Simulation time 661131100 ps
CPU time 16.18 seconds
Started Jun 07 07:18:37 PM PDT 24
Finished Jun 07 07:18:58 PM PDT 24
Peak memory 209608 kb
Host smart-5aec9973-15ea-43f6-bb63-576700943066
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100794985 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_aliasing.2100794985
Directory /workspace/3.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.1415062312
Short name T910
Test name
Test status
Simulation time 962149220 ps
CPU time 12.7 seconds
Started Jun 07 07:18:28 PM PDT 24
Finished Jun 07 07:18:48 PM PDT 24
Peak memory 209504 kb
Host smart-9644cb63-9a36-4911-b118-e043bd037707
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415062312 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_bit_bash.1415062312
Directory /workspace/3.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.3243464099
Short name T974
Test name
Test status
Simulation time 477811554 ps
CPU time 3.56 seconds
Started Jun 07 07:18:30 PM PDT 24
Finished Jun 07 07:18:40 PM PDT 24
Peak memory 218008 kb
Host smart-bdfdee11-8a98-43e2-b8d7-a16d6e8f429f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243464099 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_hw_reset.3243464099
Directory /workspace/3.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2784796701
Short name T924
Test name
Test status
Simulation time 72287497 ps
CPU time 2.47 seconds
Started Jun 07 07:18:31 PM PDT 24
Finished Jun 07 07:18:39 PM PDT 24
Peak memory 219236 kb
Host smart-e9f9804b-0a30-49d1-821b-93327982941b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278479
6701 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2784796701
Directory /workspace/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.3890813213
Short name T893
Test name
Test status
Simulation time 33087375 ps
CPU time 1.15 seconds
Started Jun 07 07:18:29 PM PDT 24
Finished Jun 07 07:18:37 PM PDT 24
Peak memory 217832 kb
Host smart-943d1d25-0376-4881-bc2b-e91a65262f44
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890813213 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.lc_ctrl_jtag_csr_rw.3890813213
Directory /workspace/3.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.1392962006
Short name T951
Test name
Test status
Simulation time 155352830 ps
CPU time 2.11 seconds
Started Jun 07 07:18:29 PM PDT 24
Finished Jun 07 07:18:38 PM PDT 24
Peak memory 211904 kb
Host smart-835a08c1-b7db-4e42-b54a-12cb62949406
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392962006 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.lc_ctrl_jtag_same_csr_outstanding.1392962006
Directory /workspace/3.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.3153510308
Short name T927
Test name
Test status
Simulation time 29809120 ps
CPU time 1.13 seconds
Started Jun 07 07:18:43 PM PDT 24
Finished Jun 07 07:18:48 PM PDT 24
Peak memory 217824 kb
Host smart-1f72f625-f30e-4ae4-83bd-a8622d01f963
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153510308 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl
_same_csr_outstanding.3153510308
Directory /workspace/3.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.3677215915
Short name T912
Test name
Test status
Simulation time 70999214 ps
CPU time 3.04 seconds
Started Jun 07 07:18:30 PM PDT 24
Finished Jun 07 07:18:40 PM PDT 24
Peak memory 218228 kb
Host smart-fa82b83a-1c1b-4541-92c5-8d8a4a569345
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677215915 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_errors.3677215915
Directory /workspace/3.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.1323219431
Short name T973
Test name
Test status
Simulation time 23815302 ps
CPU time 1.1 seconds
Started Jun 07 07:18:51 PM PDT 24
Finished Jun 07 07:18:57 PM PDT 24
Peak memory 209880 kb
Host smart-57966c1f-317e-4888-9f19-eecd7a9aff78
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323219431 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_aliasin
g.1323219431
Directory /workspace/4.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.2658196778
Short name T931
Test name
Test status
Simulation time 38465767 ps
CPU time 1.38 seconds
Started Jun 07 07:18:52 PM PDT 24
Finished Jun 07 07:18:59 PM PDT 24
Peak memory 209700 kb
Host smart-0743d0d1-3493-4726-af5c-5921007e7e8e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658196778 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_bit_bas
h.2658196778
Directory /workspace/4.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.3808698828
Short name T197
Test name
Test status
Simulation time 15816047 ps
CPU time 0.94 seconds
Started Jun 07 07:18:41 PM PDT 24
Finished Jun 07 07:18:47 PM PDT 24
Peak memory 210292 kb
Host smart-1ba3042c-bfdb-45b3-91cd-d6e687473e1c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808698828 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_hw_rese
t.3808698828
Directory /workspace/4.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.3896508473
Short name T964
Test name
Test status
Simulation time 30644580 ps
CPU time 1.57 seconds
Started Jun 07 07:18:48 PM PDT 24
Finished Jun 07 07:18:55 PM PDT 24
Peak memory 220368 kb
Host smart-4901c0e9-0870-4f95-8a27-7f3dc7f058c8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896508473 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 4.lc_ctrl_csr_mem_rw_with_rand_reset.3896508473
Directory /workspace/4.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.1948362675
Short name T969
Test name
Test status
Simulation time 45980300 ps
CPU time 0.93 seconds
Started Jun 07 07:18:50 PM PDT 24
Finished Jun 07 07:18:56 PM PDT 24
Peak memory 209436 kb
Host smart-b40454c4-5046-486b-bfd8-11bdb8d22cc4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948362675 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_rw.1948362675
Directory /workspace/4.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.2933356870
Short name T981
Test name
Test status
Simulation time 656398018 ps
CPU time 2.69 seconds
Started Jun 07 07:18:41 PM PDT 24
Finished Jun 07 07:18:48 PM PDT 24
Peak memory 209840 kb
Host smart-fd86d1d6-2c3d-463f-b006-d0f5098c24cf
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933356870 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.lc_ctrl_jtag_alert_test.2933356870
Directory /workspace/4.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.3095502953
Short name T996
Test name
Test status
Simulation time 4237392017 ps
CPU time 7.69 seconds
Started Jun 07 07:18:41 PM PDT 24
Finished Jun 07 07:18:54 PM PDT 24
Peak memory 209916 kb
Host smart-835697ae-5182-4c88-9eb5-af11d7421b19
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095502953 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_aliasing.3095502953
Directory /workspace/4.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.402452582
Short name T207
Test name
Test status
Simulation time 1800828596 ps
CPU time 18.42 seconds
Started Jun 07 07:18:42 PM PDT 24
Finished Jun 07 07:19:05 PM PDT 24
Peak memory 209400 kb
Host smart-7199d34a-d9d6-4896-8c31-ac430d315a9c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402452582 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 4.lc_ctrl_jtag_csr_bit_bash.402452582
Directory /workspace/4.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.1675327063
Short name T898
Test name
Test status
Simulation time 359202692 ps
CPU time 1.9 seconds
Started Jun 07 07:18:39 PM PDT 24
Finished Jun 07 07:18:46 PM PDT 24
Peak memory 217988 kb
Host smart-4f6031d5-1e10-4549-8415-4338577a808e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675327063 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_hw_reset.1675327063
Directory /workspace/4.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2253235956
Short name T949
Test name
Test status
Simulation time 916119521 ps
CPU time 2.29 seconds
Started Jun 07 07:18:41 PM PDT 24
Finished Jun 07 07:18:48 PM PDT 24
Peak memory 218332 kb
Host smart-da461a42-a8d2-4300-a828-d8b2deacf1fb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225323
5956 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2253235956
Directory /workspace/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.4197243678
Short name T904
Test name
Test status
Simulation time 446844381 ps
CPU time 1.91 seconds
Started Jun 07 07:18:40 PM PDT 24
Finished Jun 07 07:18:47 PM PDT 24
Peak memory 209772 kb
Host smart-3a5c2f3c-f71e-4c52-9d98-2bcc5e1cc6a3
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197243678 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.lc_ctrl_jtag_csr_rw.4197243678
Directory /workspace/4.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.1149970669
Short name T201
Test name
Test status
Simulation time 40636907 ps
CPU time 1.37 seconds
Started Jun 07 07:18:41 PM PDT 24
Finished Jun 07 07:18:47 PM PDT 24
Peak memory 209940 kb
Host smart-f50a006b-6715-479b-a797-09198f478feb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149970669 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.lc_ctrl_jtag_same_csr_outstanding.1149970669
Directory /workspace/4.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.3059918771
Short name T976
Test name
Test status
Simulation time 19964328 ps
CPU time 1.22 seconds
Started Jun 07 07:18:50 PM PDT 24
Finished Jun 07 07:18:56 PM PDT 24
Peak memory 209928 kb
Host smart-75e0669e-6f63-4c3f-95a9-bcaf2295fda9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059918771 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl
_same_csr_outstanding.3059918771
Directory /workspace/4.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.1982124836
Short name T926
Test name
Test status
Simulation time 138438589 ps
CPU time 2.38 seconds
Started Jun 07 07:18:41 PM PDT 24
Finished Jun 07 07:18:48 PM PDT 24
Peak memory 218148 kb
Host smart-0961886e-624e-48c8-8292-45f885453da8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982124836 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_errors.1982124836
Directory /workspace/4.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.3425866877
Short name T115
Test name
Test status
Simulation time 43141434 ps
CPU time 2.19 seconds
Started Jun 07 07:18:41 PM PDT 24
Finished Jun 07 07:18:48 PM PDT 24
Peak memory 222604 kb
Host smart-44e52913-5263-45ec-a3b6-3a0a155e41b0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425866877 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_intg_
err.3425866877
Directory /workspace/4.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.3511681999
Short name T160
Test name
Test status
Simulation time 287016984 ps
CPU time 1.58 seconds
Started Jun 07 07:18:49 PM PDT 24
Finished Jun 07 07:18:56 PM PDT 24
Peak memory 218200 kb
Host smart-ec5fd22e-1771-43e2-b40b-368170878ae0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511681999 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 5.lc_ctrl_csr_mem_rw_with_rand_reset.3511681999
Directory /workspace/5.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.3852415741
Short name T919
Test name
Test status
Simulation time 66495302 ps
CPU time 1.48 seconds
Started Jun 07 07:18:54 PM PDT 24
Finished Jun 07 07:19:01 PM PDT 24
Peak memory 209584 kb
Host smart-60525333-4ac0-4fc5-8e05-23dbe47c9f2c
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852415741 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.lc_ctrl_jtag_alert_test.3852415741
Directory /workspace/5.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.603271586
Short name T882
Test name
Test status
Simulation time 303185640 ps
CPU time 7.33 seconds
Started Jun 07 07:18:49 PM PDT 24
Finished Jun 07 07:19:01 PM PDT 24
Peak memory 209836 kb
Host smart-9c224148-5adb-49e2-bd3e-1d448c6815d1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603271586 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 5.lc_ctrl_jtag_csr_aliasing.603271586
Directory /workspace/5.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.3535711348
Short name T886
Test name
Test status
Simulation time 966992989 ps
CPU time 9.32 seconds
Started Jun 07 07:18:51 PM PDT 24
Finished Jun 07 07:19:06 PM PDT 24
Peak memory 217528 kb
Host smart-680e4fb4-a455-467a-b6a0-972dd4a06a1f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535711348 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_bit_bash.3535711348
Directory /workspace/5.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.1658227135
Short name T895
Test name
Test status
Simulation time 486343425 ps
CPU time 2.73 seconds
Started Jun 07 07:18:49 PM PDT 24
Finished Jun 07 07:18:57 PM PDT 24
Peak memory 217972 kb
Host smart-2d9b1528-2998-4c73-9119-10666a033d39
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658227135 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_hw_reset.1658227135
Directory /workspace/5.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2283179660
Short name T880
Test name
Test status
Simulation time 747966232 ps
CPU time 5.18 seconds
Started Jun 07 07:18:50 PM PDT 24
Finished Jun 07 07:19:00 PM PDT 24
Peak memory 218528 kb
Host smart-de0cb17d-e5a5-42b2-a90f-8fde168ec09a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228317
9660 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2283179660
Directory /workspace/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.3995969183
Short name T909
Test name
Test status
Simulation time 151178307 ps
CPU time 1.59 seconds
Started Jun 07 07:18:51 PM PDT 24
Finished Jun 07 07:18:57 PM PDT 24
Peak memory 217856 kb
Host smart-ae1cd231-c8b9-4029-9c5b-b39709403d6d
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995969183 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.lc_ctrl_jtag_csr_rw.3995969183
Directory /workspace/5.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.325133733
Short name T929
Test name
Test status
Simulation time 63316326 ps
CPU time 1.31 seconds
Started Jun 07 07:18:49 PM PDT 24
Finished Jun 07 07:18:56 PM PDT 24
Peak memory 211892 kb
Host smart-6653497a-0923-4249-878f-71e5c9b72a0c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325133733 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.lc_ctrl_jtag_same_csr_outstanding.325133733
Directory /workspace/5.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.2809086150
Short name T941
Test name
Test status
Simulation time 24006295 ps
CPU time 1.07 seconds
Started Jun 07 07:18:49 PM PDT 24
Finished Jun 07 07:18:55 PM PDT 24
Peak memory 209720 kb
Host smart-d604a509-9adf-4539-a659-a481d3340657
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809086150 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl
_same_csr_outstanding.2809086150
Directory /workspace/5.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.2813729408
Short name T125
Test name
Test status
Simulation time 918290307 ps
CPU time 2.58 seconds
Started Jun 07 07:18:51 PM PDT 24
Finished Jun 07 07:18:59 PM PDT 24
Peak memory 218216 kb
Host smart-507a25c3-c5e6-4b21-b012-d51ddc895e57
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813729408 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_errors.2813729408
Directory /workspace/5.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.3662852190
Short name T120
Test name
Test status
Simulation time 59688857 ps
CPU time 1.44 seconds
Started Jun 07 07:18:59 PM PDT 24
Finished Jun 07 07:19:06 PM PDT 24
Peak memory 218268 kb
Host smart-e5adc796-b467-46d8-82da-eb6da195f0ae
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662852190 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 6.lc_ctrl_csr_mem_rw_with_rand_reset.3662852190
Directory /workspace/6.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.3683988966
Short name T934
Test name
Test status
Simulation time 13809072 ps
CPU time 0.9 seconds
Started Jun 07 07:19:00 PM PDT 24
Finished Jun 07 07:19:06 PM PDT 24
Peak memory 209884 kb
Host smart-e47818ca-bb19-4eb7-91e5-5703fa9f0e5d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683988966 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_csr_rw.3683988966
Directory /workspace/6.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.2439114550
Short name T962
Test name
Test status
Simulation time 57659072 ps
CPU time 2.02 seconds
Started Jun 07 07:19:00 PM PDT 24
Finished Jun 07 07:19:08 PM PDT 24
Peak memory 209736 kb
Host smart-c672d797-8114-4d20-8d2e-7f8be02938d8
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439114550 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.lc_ctrl_jtag_alert_test.2439114550
Directory /workspace/6.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.2703774064
Short name T953
Test name
Test status
Simulation time 1828318076 ps
CPU time 7.69 seconds
Started Jun 07 07:18:50 PM PDT 24
Finished Jun 07 07:19:02 PM PDT 24
Peak memory 209440 kb
Host smart-990d3994-c578-49b9-9af4-fd596e1c09c3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703774064 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_aliasing.2703774064
Directory /workspace/6.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.1917088557
Short name T935
Test name
Test status
Simulation time 894730119 ps
CPU time 10.21 seconds
Started Jun 07 07:18:51 PM PDT 24
Finished Jun 07 07:19:06 PM PDT 24
Peak memory 217624 kb
Host smart-4bce33cc-084d-4d25-9439-a9c2492e6e36
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917088557 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_bit_bash.1917088557
Directory /workspace/6.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.1180634916
Short name T146
Test name
Test status
Simulation time 178508330 ps
CPU time 1.97 seconds
Started Jun 07 07:18:49 PM PDT 24
Finished Jun 07 07:18:56 PM PDT 24
Peak memory 217944 kb
Host smart-114c375f-6527-4a03-ad94-4d9b38b5fcfa
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180634916 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_hw_reset.1180634916
Directory /workspace/6.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.159160632
Short name T963
Test name
Test status
Simulation time 219730389 ps
CPU time 2.31 seconds
Started Jun 07 07:18:50 PM PDT 24
Finished Jun 07 07:18:57 PM PDT 24
Peak memory 222784 kb
Host smart-0aee7692-835e-4416-8d60-59a208d20704
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159160
632 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.159160632
Directory /workspace/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.896423998
Short name T145
Test name
Test status
Simulation time 1037422284 ps
CPU time 3.38 seconds
Started Jun 07 07:18:54 PM PDT 24
Finished Jun 07 07:19:03 PM PDT 24
Peak memory 209676 kb
Host smart-726d860e-cdcc-4127-ba10-ca3da76772bd
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896423998 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.lc_ctrl_jtag_csr_rw.896423998
Directory /workspace/6.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.3486714563
Short name T903
Test name
Test status
Simulation time 56123722 ps
CPU time 0.98 seconds
Started Jun 07 07:18:51 PM PDT 24
Finished Jun 07 07:18:57 PM PDT 24
Peak memory 209968 kb
Host smart-a5ae7175-41ed-4ddd-9a15-5cece6154f85
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486714563 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.lc_ctrl_jtag_same_csr_outstanding.3486714563
Directory /workspace/6.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.1208183559
Short name T200
Test name
Test status
Simulation time 25579023 ps
CPU time 1.18 seconds
Started Jun 07 07:18:59 PM PDT 24
Finished Jun 07 07:19:06 PM PDT 24
Peak memory 209680 kb
Host smart-ade5dcdc-c222-444e-a599-b6f910513d45
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208183559 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl
_same_csr_outstanding.1208183559
Directory /workspace/6.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.1644471872
Short name T944
Test name
Test status
Simulation time 102008857 ps
CPU time 3.22 seconds
Started Jun 07 07:18:59 PM PDT 24
Finished Jun 07 07:19:08 PM PDT 24
Peak memory 218256 kb
Host smart-efa6143f-434e-4898-87f7-185369d18a11
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644471872 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_errors.1644471872
Directory /workspace/6.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.3166934087
Short name T129
Test name
Test status
Simulation time 727642498 ps
CPU time 2.77 seconds
Started Jun 07 07:18:58 PM PDT 24
Finished Jun 07 07:19:07 PM PDT 24
Peak memory 223028 kb
Host smart-c83df9cc-06b9-44d0-82e3-75ab30e8b34f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166934087 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_intg_
err.3166934087
Directory /workspace/6.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.879476524
Short name T888
Test name
Test status
Simulation time 42167361 ps
CPU time 1.67 seconds
Started Jun 07 07:19:14 PM PDT 24
Finished Jun 07 07:19:29 PM PDT 24
Peak memory 218264 kb
Host smart-3469dc7b-54d1-443b-97e5-8da92abcd017
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879476524 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 7.lc_ctrl_csr_mem_rw_with_rand_reset.879476524
Directory /workspace/7.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.377233636
Short name T159
Test name
Test status
Simulation time 27016320 ps
CPU time 0.91 seconds
Started Jun 07 07:19:08 PM PDT 24
Finished Jun 07 07:19:19 PM PDT 24
Peak memory 209384 kb
Host smart-06487764-e331-45ef-9d90-d7a40047ded8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377233636 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_csr_rw.377233636
Directory /workspace/7.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.2613581294
Short name T877
Test name
Test status
Simulation time 134855392 ps
CPU time 1.06 seconds
Started Jun 07 07:19:10 PM PDT 24
Finished Jun 07 07:19:21 PM PDT 24
Peak memory 209124 kb
Host smart-98eef609-3787-46d8-b5ab-a5a34105913a
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613581294 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.lc_ctrl_jtag_alert_test.2613581294
Directory /workspace/7.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.3439433829
Short name T966
Test name
Test status
Simulation time 870524111 ps
CPU time 6.66 seconds
Started Jun 07 07:18:59 PM PDT 24
Finished Jun 07 07:19:11 PM PDT 24
Peak memory 217520 kb
Host smart-10057fde-4461-4808-9d5f-7e71f0a7ff56
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439433829 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_aliasing.3439433829
Directory /workspace/7.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.1899379309
Short name T920
Test name
Test status
Simulation time 830812112 ps
CPU time 21.15 seconds
Started Jun 07 07:19:02 PM PDT 24
Finished Jun 07 07:19:28 PM PDT 24
Peak memory 209584 kb
Host smart-eb533a3c-ba69-4a4c-b344-0c0e7ed6474b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899379309 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_bit_bash.1899379309
Directory /workspace/7.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.3540173400
Short name T147
Test name
Test status
Simulation time 124039235 ps
CPU time 2.82 seconds
Started Jun 07 07:18:59 PM PDT 24
Finished Jun 07 07:19:07 PM PDT 24
Peak memory 217972 kb
Host smart-5201111b-aa9d-4cdb-99f7-e25ace7c5204
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540173400 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_hw_reset.3540173400
Directory /workspace/7.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3195510447
Short name T956
Test name
Test status
Simulation time 101630999 ps
CPU time 2.09 seconds
Started Jun 07 07:19:02 PM PDT 24
Finished Jun 07 07:19:10 PM PDT 24
Peak memory 209960 kb
Host smart-44689984-29cc-4951-a2ec-8cbf69f8c47b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319551
0447 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3195510447
Directory /workspace/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.1784093685
Short name T965
Test name
Test status
Simulation time 278890203 ps
CPU time 2.04 seconds
Started Jun 07 07:19:03 PM PDT 24
Finished Jun 07 07:19:11 PM PDT 24
Peak memory 209772 kb
Host smart-f09adda4-9538-4399-bb07-c2eb952c0f90
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784093685 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.lc_ctrl_jtag_csr_rw.1784093685
Directory /workspace/7.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.217747620
Short name T907
Test name
Test status
Simulation time 19190881 ps
CPU time 1.03 seconds
Started Jun 07 07:18:59 PM PDT 24
Finished Jun 07 07:19:05 PM PDT 24
Peak memory 210064 kb
Host smart-53b09793-f341-4571-9aaa-056aa6c0a702
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217747620 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.lc_ctrl_jtag_same_csr_outstanding.217747620
Directory /workspace/7.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.3096175376
Short name T908
Test name
Test status
Simulation time 34858251 ps
CPU time 1.19 seconds
Started Jun 07 07:19:08 PM PDT 24
Finished Jun 07 07:19:19 PM PDT 24
Peak memory 209752 kb
Host smart-37895cc5-f0e7-40d5-8897-7354fd62273a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096175376 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl
_same_csr_outstanding.3096175376
Directory /workspace/7.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.3844041377
Short name T894
Test name
Test status
Simulation time 119690349 ps
CPU time 3.47 seconds
Started Jun 07 07:19:08 PM PDT 24
Finished Jun 07 07:19:21 PM PDT 24
Peak memory 218120 kb
Host smart-8ab7c487-ff04-471a-94f3-712f7285e8f6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844041377 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_errors.3844041377
Directory /workspace/7.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.576080119
Short name T883
Test name
Test status
Simulation time 53505429 ps
CPU time 1.19 seconds
Started Jun 07 07:19:08 PM PDT 24
Finished Jun 07 07:19:19 PM PDT 24
Peak memory 218372 kb
Host smart-d643e928-886b-4b1f-9421-961b2cb23491
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576080119 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 8.lc_ctrl_csr_mem_rw_with_rand_reset.576080119
Directory /workspace/8.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.1592079186
Short name T885
Test name
Test status
Simulation time 74427273 ps
CPU time 0.96 seconds
Started Jun 07 07:19:12 PM PDT 24
Finished Jun 07 07:19:24 PM PDT 24
Peak memory 209460 kb
Host smart-2d18d757-49d3-4ff1-894b-703c047f09aa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592079186 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_csr_rw.1592079186
Directory /workspace/8.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.4243748676
Short name T993
Test name
Test status
Simulation time 113402812 ps
CPU time 1.31 seconds
Started Jun 07 07:19:13 PM PDT 24
Finished Jun 07 07:19:27 PM PDT 24
Peak memory 209916 kb
Host smart-b5d71045-cfc7-4695-acdb-0089586ede58
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243748676 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.lc_ctrl_jtag_alert_test.4243748676
Directory /workspace/8.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.4152564868
Short name T876
Test name
Test status
Simulation time 518237502 ps
CPU time 12.57 seconds
Started Jun 07 07:19:09 PM PDT 24
Finished Jun 07 07:19:32 PM PDT 24
Peak memory 209624 kb
Host smart-b0fa00b6-f6ca-463d-9a2e-426173c18763
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152564868 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_aliasing.4152564868
Directory /workspace/8.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.11192537
Short name T875
Test name
Test status
Simulation time 19757267824 ps
CPU time 11.1 seconds
Started Jun 07 07:19:07 PM PDT 24
Finished Jun 07 07:19:27 PM PDT 24
Peak memory 209888 kb
Host smart-2b036caf-429c-486f-8727-a907b0fdc3c8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11192537 -assert nopostproc +UVM_TESTNAME=lc_ctrl_bas
e_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 8.lc_ctrl_jtag_csr_bit_bash.11192537
Directory /workspace/8.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.3198346431
Short name T938
Test name
Test status
Simulation time 655613148 ps
CPU time 4.34 seconds
Started Jun 07 07:19:10 PM PDT 24
Finished Jun 07 07:19:25 PM PDT 24
Peak memory 218024 kb
Host smart-239a6f7c-3039-4feb-83ae-70e2dad3ccd9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198346431 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_hw_reset.3198346431
Directory /workspace/8.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.746391529
Short name T957
Test name
Test status
Simulation time 57156876 ps
CPU time 2.22 seconds
Started Jun 07 07:19:09 PM PDT 24
Finished Jun 07 07:19:22 PM PDT 24
Peak memory 219660 kb
Host smart-da473af9-b954-4763-8cb7-b69feb4177da
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746391
529 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.746391529
Directory /workspace/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.54485131
Short name T933
Test name
Test status
Simulation time 36085938 ps
CPU time 1.1 seconds
Started Jun 07 07:19:10 PM PDT 24
Finished Jun 07 07:19:22 PM PDT 24
Peak memory 209792 kb
Host smart-723ea095-3b90-4aef-9dfb-1b54f341b6d5
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54485131 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test
+UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -
cm_name 8.lc_ctrl_jtag_csr_rw.54485131
Directory /workspace/8.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.771264366
Short name T952
Test name
Test status
Simulation time 36871032 ps
CPU time 1.8 seconds
Started Jun 07 07:19:12 PM PDT 24
Finished Jun 07 07:19:25 PM PDT 24
Peak memory 218192 kb
Host smart-b9eeabda-277c-42ca-8188-92a708794749
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771264366 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.lc_ctrl_jtag_same_csr_outstanding.771264366
Directory /workspace/8.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.4161625642
Short name T923
Test name
Test status
Simulation time 42114819 ps
CPU time 1.16 seconds
Started Jun 07 07:19:11 PM PDT 24
Finished Jun 07 07:19:23 PM PDT 24
Peak memory 209684 kb
Host smart-6ed001b9-9ba6-478e-bb02-c454750f21fe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161625642 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl
_same_csr_outstanding.4161625642
Directory /workspace/8.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.990848490
Short name T918
Test name
Test status
Simulation time 174754624 ps
CPU time 2.89 seconds
Started Jun 07 07:19:11 PM PDT 24
Finished Jun 07 07:19:24 PM PDT 24
Peak memory 218232 kb
Host smart-a8533d39-d5d0-4094-8c1a-429d9929ac22
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990848490 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_errors.990848490
Directory /workspace/8.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.610967616
Short name T972
Test name
Test status
Simulation time 67987105 ps
CPU time 1.28 seconds
Started Jun 07 07:19:20 PM PDT 24
Finished Jun 07 07:19:38 PM PDT 24
Peak memory 219312 kb
Host smart-48d2ad22-bc70-46d2-968f-ac7ed2081f92
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610967616 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 9.lc_ctrl_csr_mem_rw_with_rand_reset.610967616
Directory /workspace/9.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.1904572518
Short name T896
Test name
Test status
Simulation time 18669838 ps
CPU time 0.92 seconds
Started Jun 07 07:19:18 PM PDT 24
Finished Jun 07 07:19:34 PM PDT 24
Peak memory 209884 kb
Host smart-52988ef8-59cd-457c-9f59-8e1837a1a782
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904572518 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_csr_rw.1904572518
Directory /workspace/9.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.4051467621
Short name T891
Test name
Test status
Simulation time 332253047 ps
CPU time 2.56 seconds
Started Jun 07 07:19:08 PM PDT 24
Finished Jun 07 07:19:20 PM PDT 24
Peak memory 217476 kb
Host smart-a1ad64a8-eabb-4c8e-bb3c-b2260cea02b1
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051467621 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.lc_ctrl_jtag_alert_test.4051467621
Directory /workspace/9.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.601870491
Short name T913
Test name
Test status
Simulation time 1302645996 ps
CPU time 12.61 seconds
Started Jun 07 07:19:08 PM PDT 24
Finished Jun 07 07:19:31 PM PDT 24
Peak memory 209560 kb
Host smart-99d911e7-ba66-410d-9563-6c21f7bb6fe1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601870491 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 9.lc_ctrl_jtag_csr_aliasing.601870491
Directory /workspace/9.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.724472001
Short name T991
Test name
Test status
Simulation time 691495666 ps
CPU time 17.15 seconds
Started Jun 07 07:19:10 PM PDT 24
Finished Jun 07 07:19:37 PM PDT 24
Peak memory 217724 kb
Host smart-b5b2cca3-4f80-45c8-b1ca-d572d4bde01f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724472001 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 9.lc_ctrl_jtag_csr_bit_bash.724472001
Directory /workspace/9.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.3149233726
Short name T978
Test name
Test status
Simulation time 47510978 ps
CPU time 1.88 seconds
Started Jun 07 07:19:10 PM PDT 24
Finished Jun 07 07:19:23 PM PDT 24
Peak memory 211224 kb
Host smart-08dc22dc-4a8b-4402-b11d-e28b57eeebe0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149233726 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_hw_reset.3149233726
Directory /workspace/9.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1477227679
Short name T950
Test name
Test status
Simulation time 751032485 ps
CPU time 2.91 seconds
Started Jun 07 07:19:11 PM PDT 24
Finished Jun 07 07:19:25 PM PDT 24
Peak memory 218228 kb
Host smart-9574742b-888d-4f58-8e44-61f7a29ab76c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147722
7679 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1477227679
Directory /workspace/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.605251292
Short name T959
Test name
Test status
Simulation time 236774557 ps
CPU time 1.38 seconds
Started Jun 07 07:19:11 PM PDT 24
Finished Jun 07 07:19:23 PM PDT 24
Peak memory 217832 kb
Host smart-031197e5-e05c-4eab-979b-1554a69641cb
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605251292 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.lc_ctrl_jtag_csr_rw.605251292
Directory /workspace/9.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.4222129322
Short name T975
Test name
Test status
Simulation time 14503416 ps
CPU time 1.21 seconds
Started Jun 07 07:19:10 PM PDT 24
Finished Jun 07 07:19:22 PM PDT 24
Peak memory 209980 kb
Host smart-9e8c162f-b625-4784-bfb0-48b85e48be63
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222129322 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.lc_ctrl_jtag_same_csr_outstanding.4222129322
Directory /workspace/9.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.4125034741
Short name T143
Test name
Test status
Simulation time 44127850 ps
CPU time 1.21 seconds
Started Jun 07 07:19:20 PM PDT 24
Finished Jun 07 07:19:37 PM PDT 24
Peak memory 209716 kb
Host smart-f283b5a8-ae86-4a0a-9a70-9d8097904694
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125034741 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl
_same_csr_outstanding.4125034741
Directory /workspace/9.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.730448193
Short name T943
Test name
Test status
Simulation time 52514761 ps
CPU time 1.97 seconds
Started Jun 07 07:19:11 PM PDT 24
Finished Jun 07 07:19:23 PM PDT 24
Peak memory 219400 kb
Host smart-611b777e-4354-4c88-a251-07603311386d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730448193 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_errors.730448193
Directory /workspace/9.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.2665083671
Short name T134
Test name
Test status
Simulation time 396638408 ps
CPU time 2.36 seconds
Started Jun 07 07:19:11 PM PDT 24
Finished Jun 07 07:19:24 PM PDT 24
Peak memory 221984 kb
Host smart-7545b2b1-b2aa-40d1-bdf6-3f990afcafb3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665083671 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_intg_
err.2665083671
Directory /workspace/9.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_alert_test.3992146853
Short name T566
Test name
Test status
Simulation time 63403821 ps
CPU time 0.89 seconds
Started Jun 07 07:29:05 PM PDT 24
Finished Jun 07 07:29:11 PM PDT 24
Peak memory 209244 kb
Host smart-120d89bd-025f-4d7e-9642-b49365b74630
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992146853 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_alert_test.3992146853
Directory /workspace/0.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.lc_ctrl_errors.1741199673
Short name T282
Test name
Test status
Simulation time 469523119 ps
CPU time 11.31 seconds
Started Jun 07 07:28:55 PM PDT 24
Finished Jun 07 07:29:10 PM PDT 24
Peak memory 218704 kb
Host smart-ae77f46e-1d36-4add-8072-ad1e0fdae795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741199673 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_errors.1741199673
Directory /workspace/0.lc_ctrl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_access.1707762242
Short name T371
Test name
Test status
Simulation time 332879951 ps
CPU time 3.47 seconds
Started Jun 07 07:29:09 PM PDT 24
Finished Jun 07 07:29:17 PM PDT 24
Peak memory 217568 kb
Host smart-f4fe4959-6922-456a-bf06-5c637b672eb1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707762242 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_access.1707762242
Directory /workspace/0.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_errors.586878233
Short name T661
Test name
Test status
Simulation time 11949212881 ps
CPU time 72.87 seconds
Started Jun 07 07:29:06 PM PDT 24
Finished Jun 07 07:30:24 PM PDT 24
Peak memory 219444 kb
Host smart-ab8bb3d0-d6fd-4f9b-aeda-2ca769da91c6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586878233 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_err
ors.586878233
Directory /workspace/0.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_priority.1939375232
Short name T427
Test name
Test status
Simulation time 595660089 ps
CPU time 2.47 seconds
Started Jun 07 07:29:08 PM PDT 24
Finished Jun 07 07:29:15 PM PDT 24
Peak memory 218260 kb
Host smart-adcfc40b-4ea7-40ca-aa26-ec6e7faa6b37
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939375232 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_priority.1
939375232
Directory /workspace/0.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_prog_failure.3092966265
Short name T347
Test name
Test status
Simulation time 2369410366 ps
CPU time 10.23 seconds
Started Jun 07 07:29:06 PM PDT 24
Finished Jun 07 07:29:21 PM PDT 24
Peak memory 218772 kb
Host smart-ff401683-deec-4db8-99c5-abb1541b6475
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092966265 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag
_prog_failure.3092966265
Directory /workspace/0.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_regwen_during_op.593760676
Short name T516
Test name
Test status
Simulation time 3861407745 ps
CPU time 15.39 seconds
Started Jun 07 07:29:05 PM PDT 24
Finished Jun 07 07:29:25 PM PDT 24
Peak memory 218304 kb
Host smart-663f561e-3cdf-46ec-a8ad-fae822dbdd08
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593760676 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_j
tag_regwen_during_op.593760676
Directory /workspace/0.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_smoke.3240055464
Short name T452
Test name
Test status
Simulation time 609020856 ps
CPU time 2.89 seconds
Started Jun 07 07:29:00 PM PDT 24
Finished Jun 07 07:29:06 PM PDT 24
Peak memory 218132 kb
Host smart-d61bc9df-694a-419b-b998-b360d02e67bd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240055464 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_smoke.
3240055464
Directory /workspace/0.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_failure.3271159626
Short name T658
Test name
Test status
Simulation time 4712416969 ps
CPU time 84.92 seconds
Started Jun 07 07:29:08 PM PDT 24
Finished Jun 07 07:30:38 PM PDT 24
Peak memory 284096 kb
Host smart-26ad245f-6119-4c2f-b546-aeac90870aa7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271159626 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jta
g_state_failure.3271159626
Directory /workspace/0.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_post_trans.1564682359
Short name T152
Test name
Test status
Simulation time 405202969 ps
CPU time 14.39 seconds
Started Jun 07 07:29:08 PM PDT 24
Finished Jun 07 07:29:27 PM PDT 24
Peak memory 251380 kb
Host smart-a06928ad-76a9-45dd-b8d2-bd29c910be78
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564682359 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_state_post_trans.1564682359
Directory /workspace/0.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_prog_failure.1232873540
Short name T735
Test name
Test status
Simulation time 27973356 ps
CPU time 1.74 seconds
Started Jun 07 07:29:01 PM PDT 24
Finished Jun 07 07:29:06 PM PDT 24
Peak memory 218612 kb
Host smart-5b927c82-af87-46b2-8142-a253683a5057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232873540 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_prog_failure.1232873540
Directory /workspace/0.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_regwen_during_op.2173894853
Short name T811
Test name
Test status
Simulation time 2114830084 ps
CPU time 20.28 seconds
Started Jun 07 07:29:02 PM PDT 24
Finished Jun 07 07:29:26 PM PDT 24
Peak memory 218244 kb
Host smart-ca18aa22-a956-4dae-a219-60e643b2b483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173894853 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_regwen_during_op.2173894853
Directory /workspace/0.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_mubi.3727475329
Short name T601
Test name
Test status
Simulation time 669645482 ps
CPU time 13.19 seconds
Started Jun 07 07:29:06 PM PDT 24
Finished Jun 07 07:29:24 PM PDT 24
Peak memory 219496 kb
Host smart-ebef5fc8-072d-48d5-b1f5-d84a4234f18a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727475329 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_mubi.3727475329
Directory /workspace/0.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_digest.166097632
Short name T577
Test name
Test status
Simulation time 1312999255 ps
CPU time 14.13 seconds
Started Jun 07 07:29:06 PM PDT 24
Finished Jun 07 07:29:25 PM PDT 24
Peak memory 218720 kb
Host smart-b7fa8737-2066-4971-bcc2-473fa73c7071
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166097632 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_dig
est.166097632
Directory /workspace/0.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_mux.3626453190
Short name T579
Test name
Test status
Simulation time 1824442038 ps
CPU time 14.7 seconds
Started Jun 07 07:29:04 PM PDT 24
Finished Jun 07 07:29:23 PM PDT 24
Peak memory 218708 kb
Host smart-c4442b4a-b7e2-417d-a699-68360dceab63
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626453190 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_mux.3
626453190
Directory /workspace/0.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/0.lc_ctrl_security_escalation.683839442
Short name T650
Test name
Test status
Simulation time 487284099 ps
CPU time 16.79 seconds
Started Jun 07 07:28:58 PM PDT 24
Finished Jun 07 07:29:18 PM PDT 24
Peak memory 218856 kb
Host smart-796dc535-919c-4c85-8710-ecec10b94149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683839442 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_security_escalation.683839442
Directory /workspace/0.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/0.lc_ctrl_smoke.3341156897
Short name T645
Test name
Test status
Simulation time 409589754 ps
CPU time 3.3 seconds
Started Jun 07 07:28:55 PM PDT 24
Finished Jun 07 07:29:02 PM PDT 24
Peak memory 223540 kb
Host smart-0407d855-bdfe-4be4-a68a-c538cd4f1895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341156897 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_smoke.3341156897
Directory /workspace/0.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_failure.3944584141
Short name T375
Test name
Test status
Simulation time 275102135 ps
CPU time 31.49 seconds
Started Jun 07 07:28:59 PM PDT 24
Finished Jun 07 07:29:34 PM PDT 24
Peak memory 251440 kb
Host smart-e2409744-0d8b-4d93-ba0f-3dda76c49d98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944584141 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_failure.3944584141
Directory /workspace/0.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_post_trans.4052186041
Short name T608
Test name
Test status
Simulation time 1173594429 ps
CPU time 7 seconds
Started Jun 07 07:28:56 PM PDT 24
Finished Jun 07 07:29:06 PM PDT 24
Peak memory 247520 kb
Host smart-3e8ae744-bdc6-4a77-8023-9ef28b0a8e08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052186041 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_post_trans.4052186041
Directory /workspace/0.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_volatile_unlock_smoke.3527602110
Short name T615
Test name
Test status
Simulation time 16539828 ps
CPU time 0.99 seconds
Started Jun 07 07:28:59 PM PDT 24
Finished Jun 07 07:29:03 PM PDT 24
Peak memory 212308 kb
Host smart-b3a6ab97-b1a9-4393-9173-a6ac1be34b71
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527602110 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ct
rl_volatile_unlock_smoke.3527602110
Directory /workspace/0.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_alert_test.3513153160
Short name T546
Test name
Test status
Simulation time 12500678 ps
CPU time 0.84 seconds
Started Jun 07 07:29:05 PM PDT 24
Finished Jun 07 07:29:11 PM PDT 24
Peak memory 209144 kb
Host smart-56732eca-6ee9-41bd-9244-7f2388225345
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513153160 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_alert_test.3513153160
Directory /workspace/1.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_access.3424615809
Short name T446
Test name
Test status
Simulation time 1220308988 ps
CPU time 5.89 seconds
Started Jun 07 07:29:08 PM PDT 24
Finished Jun 07 07:29:18 PM PDT 24
Peak memory 217624 kb
Host smart-f7956b69-9554-440e-9880-392cf7d9fb5c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424615809 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_access.3424615809
Directory /workspace/1.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_errors.1986673123
Short name T805
Test name
Test status
Simulation time 1962373758 ps
CPU time 31.93 seconds
Started Jun 07 07:29:06 PM PDT 24
Finished Jun 07 07:29:43 PM PDT 24
Peak memory 219332 kb
Host smart-5efb41e0-97e0-4d84-9c52-4fcfbcc072c9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986673123 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_er
rors.1986673123
Directory /workspace/1.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_priority.1305722996
Short name T635
Test name
Test status
Simulation time 155326037 ps
CPU time 4.74 seconds
Started Jun 07 07:29:07 PM PDT 24
Finished Jun 07 07:29:17 PM PDT 24
Peak memory 218232 kb
Host smart-990da897-c522-40de-917e-2f6cc6eccf7d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305722996 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_priority.1
305722996
Directory /workspace/1.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_prog_failure.28752292
Short name T617
Test name
Test status
Simulation time 3651132085 ps
CPU time 10.26 seconds
Started Jun 07 07:29:05 PM PDT 24
Finished Jun 07 07:29:21 PM PDT 24
Peak memory 218744 kb
Host smart-b5f009ff-ec5c-4e45-8d22-e375d74f50dd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28752292 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_p
rog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_p
rog_failure.28752292
Directory /workspace/1.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_regwen_during_op.3087712813
Short name T441
Test name
Test status
Simulation time 3890350794 ps
CPU time 13.71 seconds
Started Jun 07 07:29:11 PM PDT 24
Finished Jun 07 07:29:29 PM PDT 24
Peak memory 218228 kb
Host smart-8a3f7818-ac86-4f9e-a4d4-12d2fff9df23
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087712813 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_regwen_during_op.3087712813
Directory /workspace/1.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_smoke.990721119
Short name T639
Test name
Test status
Simulation time 479347845 ps
CPU time 7.12 seconds
Started Jun 07 07:29:04 PM PDT 24
Finished Jun 07 07:29:16 PM PDT 24
Peak memory 218136 kb
Host smart-609a743f-233e-4c14-a0d6-efe66c511b0f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990721119 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_smoke.990721119
Directory /workspace/1.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_failure.3178790948
Short name T360
Test name
Test status
Simulation time 8323374186 ps
CPU time 88.02 seconds
Started Jun 07 07:29:04 PM PDT 24
Finished Jun 07 07:30:37 PM PDT 24
Peak memory 270088 kb
Host smart-436acca9-5bcd-4d1d-bd8f-5791490b498b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178790948 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jta
g_state_failure.3178790948
Directory /workspace/1.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_post_trans.3174054104
Short name T249
Test name
Test status
Simulation time 823717501 ps
CPU time 15.86 seconds
Started Jun 07 07:29:05 PM PDT 24
Finished Jun 07 07:29:27 PM PDT 24
Peak memory 251400 kb
Host smart-fa7ea83e-2200-4bc6-9a3c-2a679b530923
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174054104 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_state_post_trans.3174054104
Directory /workspace/1.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_prog_failure.3788834983
Short name T823
Test name
Test status
Simulation time 23713521 ps
CPU time 1.59 seconds
Started Jun 07 07:29:07 PM PDT 24
Finished Jun 07 07:29:13 PM PDT 24
Peak memory 222128 kb
Host smart-acec74b9-b265-40b2-931c-fa2f388484ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788834983 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_prog_failure.3788834983
Directory /workspace/1.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_regwen_during_op.3536978903
Short name T100
Test name
Test status
Simulation time 1334554061 ps
CPU time 6.91 seconds
Started Jun 07 07:29:09 PM PDT 24
Finished Jun 07 07:29:21 PM PDT 24
Peak memory 218184 kb
Host smart-6c319661-5a37-4076-99b1-1b25c3e03bf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536978903 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_regwen_during_op.3536978903
Directory /workspace/1.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_cm.1690522631
Short name T87
Test name
Test status
Simulation time 436103008 ps
CPU time 24.95 seconds
Started Jun 07 07:29:07 PM PDT 24
Finished Jun 07 07:29:36 PM PDT 24
Peak memory 284808 kb
Host smart-321924e2-1445-4c0f-a7dc-6c0b9f3905ce
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690522631 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_cm.1690522631
Directory /workspace/1.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_mubi.2261126183
Short name T821
Test name
Test status
Simulation time 781266147 ps
CPU time 16.93 seconds
Started Jun 07 07:29:09 PM PDT 24
Finished Jun 07 07:29:30 PM PDT 24
Peak memory 219468 kb
Host smart-bc4b83da-ddbe-47c6-a45c-2b05db8f591e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261126183 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_mubi.2261126183
Directory /workspace/1.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_digest.397487003
Short name T313
Test name
Test status
Simulation time 1304324167 ps
CPU time 13.04 seconds
Started Jun 07 07:29:09 PM PDT 24
Finished Jun 07 07:29:26 PM PDT 24
Peak memory 218728 kb
Host smart-7e936cb2-afbe-46af-9023-ccd33ff63594
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397487003 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_dig
est.397487003
Directory /workspace/1.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_mux.486974507
Short name T706
Test name
Test status
Simulation time 263364090 ps
CPU time 10.08 seconds
Started Jun 07 07:29:08 PM PDT 24
Finished Jun 07 07:29:23 PM PDT 24
Peak memory 226512 kb
Host smart-cd4ae563-c5b0-486c-b830-8df6fdcdcc36
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486974507 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_mux.486974507
Directory /workspace/1.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/1.lc_ctrl_security_escalation.2355498863
Short name T349
Test name
Test status
Simulation time 314890454 ps
CPU time 7.65 seconds
Started Jun 07 07:29:11 PM PDT 24
Finished Jun 07 07:29:22 PM PDT 24
Peak memory 225364 kb
Host smart-d477b5ec-4451-4875-bbd4-d90f185d3322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355498863 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_security_escalation.2355498863
Directory /workspace/1.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/1.lc_ctrl_smoke.3196192659
Short name T776
Test name
Test status
Simulation time 304965492 ps
CPU time 3.16 seconds
Started Jun 07 07:29:04 PM PDT 24
Finished Jun 07 07:29:12 PM PDT 24
Peak memory 215056 kb
Host smart-da166405-bfcc-4cd7-9e84-075a03814ea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196192659 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_smoke.3196192659
Directory /workspace/1.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_failure.196713769
Short name T537
Test name
Test status
Simulation time 1566362728 ps
CPU time 23.23 seconds
Started Jun 07 07:29:07 PM PDT 24
Finished Jun 07 07:29:35 PM PDT 24
Peak memory 251448 kb
Host smart-c20eb5e7-174f-42fa-8b8d-5c816623b382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196713769 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_failure.196713769
Directory /workspace/1.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_post_trans.4232627675
Short name T506
Test name
Test status
Simulation time 327020748 ps
CPU time 3.13 seconds
Started Jun 07 07:29:05 PM PDT 24
Finished Jun 07 07:29:14 PM PDT 24
Peak memory 226824 kb
Host smart-e198af4e-3f58-4a1f-b128-8de88d065d4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232627675 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_post_trans.4232627675
Directory /workspace/1.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_stress_all.4057660090
Short name T491
Test name
Test status
Simulation time 24686575041 ps
CPU time 197.59 seconds
Started Jun 07 07:29:04 PM PDT 24
Finished Jun 07 07:32:26 PM PDT 24
Peak memory 268500 kb
Host smart-8b571ca3-fbe1-440b-8511-30bceb8e6c8c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057660090 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.lc_ctrl_stress_all.4057660090
Directory /workspace/1.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.lc_ctrl_volatile_unlock_smoke.1088485548
Short name T226
Test name
Test status
Simulation time 22683702 ps
CPU time 1.23 seconds
Started Jun 07 07:29:04 PM PDT 24
Finished Jun 07 07:29:10 PM PDT 24
Peak memory 213464 kb
Host smart-56cf7831-f285-4557-a77d-b8d6a584677d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088485548 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ct
rl_volatile_unlock_smoke.1088485548
Directory /workspace/1.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_alert_test.914308884
Short name T438
Test name
Test status
Simulation time 75971717 ps
CPU time 1.17 seconds
Started Jun 07 07:29:59 PM PDT 24
Finished Jun 07 07:30:04 PM PDT 24
Peak memory 209436 kb
Host smart-8fc1fe94-d31a-466e-8e75-7f722bdff15e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914308884 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_alert_test.914308884
Directory /workspace/10.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.lc_ctrl_errors.2047066610
Short name T400
Test name
Test status
Simulation time 373754734 ps
CPU time 11.39 seconds
Started Jun 07 07:29:59 PM PDT 24
Finished Jun 07 07:30:14 PM PDT 24
Peak memory 218648 kb
Host smart-990d2b92-bc21-4872-94a8-d53cb9d0ab99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047066610 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_errors.2047066610
Directory /workspace/10.lc_ctrl_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_access.2567862049
Short name T513
Test name
Test status
Simulation time 732580978 ps
CPU time 4.91 seconds
Started Jun 07 07:29:59 PM PDT 24
Finished Jun 07 07:30:06 PM PDT 24
Peak memory 217940 kb
Host smart-113502c0-c52e-48e0-8573-21922672b789
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567862049 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_access.2567862049
Directory /workspace/10.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_errors.754825423
Short name T382
Test name
Test status
Simulation time 4012757924 ps
CPU time 29.19 seconds
Started Jun 07 07:29:59 PM PDT 24
Finished Jun 07 07:30:31 PM PDT 24
Peak memory 219060 kb
Host smart-6d66db20-327e-41bd-8a89-dea32f172646
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754825423 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_er
rors.754825423
Directory /workspace/10.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_prog_failure.1315066194
Short name T243
Test name
Test status
Simulation time 639119875 ps
CPU time 6.38 seconds
Started Jun 07 07:29:58 PM PDT 24
Finished Jun 07 07:30:07 PM PDT 24
Peak memory 223648 kb
Host smart-77b2fd2a-387a-4c9b-9678-ee13165e846f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315066194 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jta
g_prog_failure.1315066194
Directory /workspace/10.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_smoke.2547225685
Short name T847
Test name
Test status
Simulation time 322907460 ps
CPU time 1.81 seconds
Started Jun 07 07:30:00 PM PDT 24
Finished Jun 07 07:30:05 PM PDT 24
Peak memory 218220 kb
Host smart-ea616471-ceb3-4d12-987b-5aaa5e0a1b73
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547225685 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_smoke
.2547225685
Directory /workspace/10.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_failure.708851212
Short name T409
Test name
Test status
Simulation time 30694802659 ps
CPU time 125.06 seconds
Started Jun 07 07:29:59 PM PDT 24
Finished Jun 07 07:32:07 PM PDT 24
Peak memory 284072 kb
Host smart-f4df9786-853c-41ba-9d2e-3938926f1092
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708851212 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jta
g_state_failure.708851212
Directory /workspace/10.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_post_trans.539224192
Short name T482
Test name
Test status
Simulation time 407233493 ps
CPU time 8.42 seconds
Started Jun 07 07:30:00 PM PDT 24
Finished Jun 07 07:30:11 PM PDT 24
Peak memory 218632 kb
Host smart-a2c218f8-484b-4141-a198-c4e571a8640c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539224192 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_
jtag_state_post_trans.539224192
Directory /workspace/10.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_prog_failure.3349455660
Short name T496
Test name
Test status
Simulation time 140057634 ps
CPU time 2.08 seconds
Started Jun 07 07:29:59 PM PDT 24
Finished Jun 07 07:30:04 PM PDT 24
Peak memory 222656 kb
Host smart-9b104cad-eca6-45e8-abb2-0ae295e91e85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349455660 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_prog_failure.3349455660
Directory /workspace/10.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_digest.251767105
Short name T235
Test name
Test status
Simulation time 628786716 ps
CPU time 13.54 seconds
Started Jun 07 07:30:00 PM PDT 24
Finished Jun 07 07:30:17 PM PDT 24
Peak memory 218692 kb
Host smart-e86048b2-fa55-4da9-baa1-3269f5a7a0bf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251767105 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_di
gest.251767105
Directory /workspace/10.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_mux.1427625874
Short name T831
Test name
Test status
Simulation time 621368819 ps
CPU time 9.09 seconds
Started Jun 07 07:30:00 PM PDT 24
Finished Jun 07 07:30:11 PM PDT 24
Peak memory 218764 kb
Host smart-ec563d21-6489-4ad5-ab9b-e8c72d843c56
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427625874 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_mux.
1427625874
Directory /workspace/10.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/10.lc_ctrl_security_escalation.4112765951
Short name T178
Test name
Test status
Simulation time 806842863 ps
CPU time 17.26 seconds
Started Jun 07 07:29:58 PM PDT 24
Finished Jun 07 07:30:18 PM PDT 24
Peak memory 225724 kb
Host smart-346cfa68-e625-4f4a-9201-cc2a18f5df1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112765951 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_security_escalation.4112765951
Directory /workspace/10.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/10.lc_ctrl_smoke.485483477
Short name T729
Test name
Test status
Simulation time 464529066 ps
CPU time 2.44 seconds
Started Jun 07 07:29:59 PM PDT 24
Finished Jun 07 07:30:05 PM PDT 24
Peak memory 218268 kb
Host smart-0177d169-6fa7-40e6-a5cd-3c1a1b4cfc98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485483477 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_smoke.485483477
Directory /workspace/10.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_failure.2453754638
Short name T838
Test name
Test status
Simulation time 1062958944 ps
CPU time 25.03 seconds
Started Jun 07 07:30:00 PM PDT 24
Finished Jun 07 07:30:28 PM PDT 24
Peak memory 251364 kb
Host smart-a160028c-8fd6-4f1d-8204-7d4c95d6f899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453754638 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_failure.2453754638
Directory /workspace/10.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_post_trans.788707802
Short name T801
Test name
Test status
Simulation time 247180581 ps
CPU time 3.25 seconds
Started Jun 07 07:29:58 PM PDT 24
Finished Jun 07 07:30:04 PM PDT 24
Peak memory 218580 kb
Host smart-f443d36d-53d9-4493-b457-86ae2434b8ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788707802 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_post_trans.788707802
Directory /workspace/10.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all.2427632766
Short name T693
Test name
Test status
Simulation time 22040772073 ps
CPU time 395.85 seconds
Started Jun 07 07:29:59 PM PDT 24
Finished Jun 07 07:36:38 PM PDT 24
Peak memory 268972 kb
Host smart-138185fb-03f8-440a-a5ae-03085dd3702d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427632766 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.lc_ctrl_stress_all.2427632766
Directory /workspace/10.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.lc_ctrl_volatile_unlock_smoke.4234570490
Short name T37
Test name
Test status
Simulation time 15147379 ps
CPU time 0.98 seconds
Started Jun 07 07:29:59 PM PDT 24
Finished Jun 07 07:30:03 PM PDT 24
Peak memory 212436 kb
Host smart-7970dad3-eecc-4719-a687-d8b46e4a442c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234570490 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_c
trl_volatile_unlock_smoke.4234570490
Directory /workspace/10.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_alert_test.98524044
Short name T68
Test name
Test status
Simulation time 54979798 ps
CPU time 1.08 seconds
Started Jun 07 07:30:12 PM PDT 24
Finished Jun 07 07:30:14 PM PDT 24
Peak memory 209508 kb
Host smart-794fc366-76c9-4141-8f2e-670bc7329974
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98524044 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_alert_test.98524044
Directory /workspace/11.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.lc_ctrl_errors.2122554773
Short name T265
Test name
Test status
Simulation time 2539181655 ps
CPU time 17.7 seconds
Started Jun 07 07:30:08 PM PDT 24
Finished Jun 07 07:30:27 PM PDT 24
Peak memory 219408 kb
Host smart-3033fbf0-555f-40c4-9375-6c5f54d437cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122554773 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_errors.2122554773
Directory /workspace/11.lc_ctrl_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_access.3844546741
Short name T362
Test name
Test status
Simulation time 5589333069 ps
CPU time 13.86 seconds
Started Jun 07 07:30:07 PM PDT 24
Finished Jun 07 07:30:22 PM PDT 24
Peak memory 218260 kb
Host smart-73726d00-fed0-47a8-81cb-cbdd6f04c8e6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844546741 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_access.3844546741
Directory /workspace/11.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_errors.2897533942
Short name T343
Test name
Test status
Simulation time 6503420067 ps
CPU time 91.41 seconds
Started Jun 07 07:30:08 PM PDT 24
Finished Jun 07 07:31:41 PM PDT 24
Peak memory 219268 kb
Host smart-4fac982e-eaa5-4386-9ed9-b10409934016
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897533942 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_e
rrors.2897533942
Directory /workspace/11.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_prog_failure.4000747394
Short name T542
Test name
Test status
Simulation time 133568701 ps
CPU time 3.3 seconds
Started Jun 07 07:30:10 PM PDT 24
Finished Jun 07 07:30:15 PM PDT 24
Peak memory 218704 kb
Host smart-edeea6b5-bedf-4fed-8daf-34fa1f275b7b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000747394 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jta
g_prog_failure.4000747394
Directory /workspace/11.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_smoke.1356303752
Short name T77
Test name
Test status
Simulation time 140250202 ps
CPU time 2.88 seconds
Started Jun 07 07:30:09 PM PDT 24
Finished Jun 07 07:30:14 PM PDT 24
Peak memory 218248 kb
Host smart-e9e79828-315f-4f78-a53b-c563eae554f0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356303752 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_smoke
.1356303752
Directory /workspace/11.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_failure.1128905240
Short name T712
Test name
Test status
Simulation time 2253982617 ps
CPU time 35.46 seconds
Started Jun 07 07:30:07 PM PDT 24
Finished Jun 07 07:30:44 PM PDT 24
Peak memory 252040 kb
Host smart-e5ba0916-144d-47e6-8bb9-17138a7af8c8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128905240 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jt
ag_state_failure.1128905240
Directory /workspace/11.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_post_trans.1660489169
Short name T727
Test name
Test status
Simulation time 796518764 ps
CPU time 14.4 seconds
Started Jun 07 07:30:07 PM PDT 24
Finished Jun 07 07:30:23 PM PDT 24
Peak memory 251384 kb
Host smart-0cf17031-a5da-4260-a6c9-5e3b25ddf9b3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660489169 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl
_jtag_state_post_trans.1660489169
Directory /workspace/11.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_prog_failure.3838954562
Short name T280
Test name
Test status
Simulation time 515673372 ps
CPU time 3.28 seconds
Started Jun 07 07:30:09 PM PDT 24
Finished Jun 07 07:30:14 PM PDT 24
Peak memory 218672 kb
Host smart-878974e7-71ba-4be4-813b-bd9f3172d7ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838954562 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_prog_failure.3838954562
Directory /workspace/11.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_mubi.1002635415
Short name T848
Test name
Test status
Simulation time 679429075 ps
CPU time 15.98 seconds
Started Jun 07 07:30:05 PM PDT 24
Finished Jun 07 07:30:23 PM PDT 24
Peak memory 226536 kb
Host smart-d80bc4c6-1222-435c-8a29-0885c1e80315
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002635415 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_mubi.1002635415
Directory /workspace/11.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_digest.1489854770
Short name T383
Test name
Test status
Simulation time 591883112 ps
CPU time 9.91 seconds
Started Jun 07 07:30:11 PM PDT 24
Finished Jun 07 07:30:22 PM PDT 24
Peak memory 218728 kb
Host smart-79e25c25-00b2-467f-8208-b3268f409256
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489854770 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_d
igest.1489854770
Directory /workspace/11.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_mux.3542480847
Short name T502
Test name
Test status
Simulation time 361577739 ps
CPU time 13.45 seconds
Started Jun 07 07:30:07 PM PDT 24
Finished Jun 07 07:30:22 PM PDT 24
Peak memory 218732 kb
Host smart-cd062bc5-62f1-42ee-bd09-001cee40ba85
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542480847 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_mux.
3542480847
Directory /workspace/11.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/11.lc_ctrl_security_escalation.885027357
Short name T818
Test name
Test status
Simulation time 422553047 ps
CPU time 13.29 seconds
Started Jun 07 07:30:11 PM PDT 24
Finished Jun 07 07:30:26 PM PDT 24
Peak memory 218816 kb
Host smart-ed8d7b85-a195-44cd-ae9f-a3550f287baf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885027357 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_security_escalation.885027357
Directory /workspace/11.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/11.lc_ctrl_smoke.1577465397
Short name T687
Test name
Test status
Simulation time 90866718 ps
CPU time 1.46 seconds
Started Jun 07 07:30:09 PM PDT 24
Finished Jun 07 07:30:12 PM PDT 24
Peak memory 218200 kb
Host smart-18f625d0-c456-431d-92ed-890458983e32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577465397 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_smoke.1577465397
Directory /workspace/11.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_failure.813513951
Short name T861
Test name
Test status
Simulation time 659792110 ps
CPU time 32.75 seconds
Started Jun 07 07:30:09 PM PDT 24
Finished Jun 07 07:30:43 PM PDT 24
Peak memory 251384 kb
Host smart-5c44aa58-4664-4e12-8f0a-989ec8377355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813513951 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_failure.813513951
Directory /workspace/11.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_post_trans.636959683
Short name T367
Test name
Test status
Simulation time 65399537 ps
CPU time 6.93 seconds
Started Jun 07 07:30:08 PM PDT 24
Finished Jun 07 07:30:17 PM PDT 24
Peak memory 246852 kb
Host smart-bd9cde2c-1ea4-4c12-967d-6e5fbf0df4fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636959683 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_post_trans.636959683
Directory /workspace/11.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_stress_all.2014459878
Short name T287
Test name
Test status
Simulation time 15127751858 ps
CPU time 146.6 seconds
Started Jun 07 07:30:07 PM PDT 24
Finished Jun 07 07:32:35 PM PDT 24
Peak memory 282348 kb
Host smart-4f58f967-aa51-4c24-a134-c6f1fc36253f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014459878 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.lc_ctrl_stress_all.2014459878
Directory /workspace/11.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.lc_ctrl_volatile_unlock_smoke.1516297898
Short name T606
Test name
Test status
Simulation time 17177581 ps
CPU time 1.23 seconds
Started Jun 07 07:30:12 PM PDT 24
Finished Jun 07 07:30:15 PM PDT 24
Peak memory 212532 kb
Host smart-52720cbf-4718-4f9a-9404-cf48817ad96b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516297898 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_c
trl_volatile_unlock_smoke.1516297898
Directory /workspace/11.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_alert_test.3134579130
Short name T89
Test name
Test status
Simulation time 78090191 ps
CPU time 0.95 seconds
Started Jun 07 07:30:15 PM PDT 24
Finished Jun 07 07:30:18 PM PDT 24
Peak memory 209368 kb
Host smart-aad3f94d-73d2-404e-ae73-fdd3f37fe2d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134579130 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_alert_test.3134579130
Directory /workspace/12.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.lc_ctrl_errors.4173656849
Short name T393
Test name
Test status
Simulation time 372310370 ps
CPU time 12.22 seconds
Started Jun 07 07:30:10 PM PDT 24
Finished Jun 07 07:30:24 PM PDT 24
Peak memory 218696 kb
Host smart-6555c387-01c0-44e9-af31-133091ca5947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173656849 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_errors.4173656849
Directory /workspace/12.lc_ctrl_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_access.414128524
Short name T23
Test name
Test status
Simulation time 3587945935 ps
CPU time 11.12 seconds
Started Jun 07 07:30:05 PM PDT 24
Finished Jun 07 07:30:18 PM PDT 24
Peak memory 218260 kb
Host smart-89d74b79-076a-40d6-ab65-5050b4ea9f96
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414128524 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_access.414128524
Directory /workspace/12.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_errors.1864605437
Short name T183
Test name
Test status
Simulation time 2318900265 ps
CPU time 38.2 seconds
Started Jun 07 07:30:10 PM PDT 24
Finished Jun 07 07:30:50 PM PDT 24
Peak memory 219532 kb
Host smart-0068fc04-4cd2-43ba-9f20-7475c4cedbe5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864605437 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_e
rrors.1864605437
Directory /workspace/12.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_prog_failure.1019023122
Short name T357
Test name
Test status
Simulation time 3839503382 ps
CPU time 13.25 seconds
Started Jun 07 07:30:09 PM PDT 24
Finished Jun 07 07:30:24 PM PDT 24
Peak memory 219416 kb
Host smart-6097472e-7185-4462-9234-30846c1f39bd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019023122 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jta
g_prog_failure.1019023122
Directory /workspace/12.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_smoke.44011656
Short name T336
Test name
Test status
Simulation time 1090417585 ps
CPU time 8.2 seconds
Started Jun 07 07:30:05 PM PDT 24
Finished Jun 07 07:30:15 PM PDT 24
Peak memory 218192 kb
Host smart-5d0d02b7-898c-4d90-8e06-21579a4a1f4e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44011656 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_smoke.44011656
Directory /workspace/12.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_failure.1435145356
Short name T710
Test name
Test status
Simulation time 3774725464 ps
CPU time 53.88 seconds
Started Jun 07 07:30:09 PM PDT 24
Finished Jun 07 07:31:05 PM PDT 24
Peak memory 277404 kb
Host smart-35ad0b08-ef14-4a3a-b318-26021fe04c63
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435145356 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jt
ag_state_failure.1435145356
Directory /workspace/12.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_post_trans.3221937697
Short name T270
Test name
Test status
Simulation time 661082088 ps
CPU time 7.54 seconds
Started Jun 07 07:30:11 PM PDT 24
Finished Jun 07 07:30:20 PM PDT 24
Peak memory 223544 kb
Host smart-09ad43d0-04aa-41cd-99d4-4823e3ca5304
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221937697 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl
_jtag_state_post_trans.3221937697
Directory /workspace/12.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_prog_failure.3512129741
Short name T16
Test name
Test status
Simulation time 64291644 ps
CPU time 2.8 seconds
Started Jun 07 07:30:08 PM PDT 24
Finished Jun 07 07:30:12 PM PDT 24
Peak memory 218612 kb
Host smart-99bd5a10-cf02-4b4d-bd20-f63cf6fc021e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512129741 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_prog_failure.3512129741
Directory /workspace/12.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_mubi.321620692
Short name T654
Test name
Test status
Simulation time 620946175 ps
CPU time 13.74 seconds
Started Jun 07 07:30:15 PM PDT 24
Finished Jun 07 07:30:31 PM PDT 24
Peak memory 226552 kb
Host smart-83e0e0c9-8099-405c-a617-bf89df5bb45b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321620692 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_mubi.321620692
Directory /workspace/12.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_digest.372034191
Short name T749
Test name
Test status
Simulation time 2048570369 ps
CPU time 11.57 seconds
Started Jun 07 07:30:14 PM PDT 24
Finished Jun 07 07:30:28 PM PDT 24
Peak memory 218688 kb
Host smart-195bb0f1-0ce6-42ec-8aea-b3832608a7ba
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372034191 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_di
gest.372034191
Directory /workspace/12.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_mux.1590193604
Short name T761
Test name
Test status
Simulation time 1152815448 ps
CPU time 9.82 seconds
Started Jun 07 07:30:12 PM PDT 24
Finished Jun 07 07:30:27 PM PDT 24
Peak memory 226540 kb
Host smart-90bc50dc-3a0c-4acd-b42d-c7b4c1291729
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590193604 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_mux.
1590193604
Directory /workspace/12.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/12.lc_ctrl_security_escalation.1012493201
Short name T50
Test name
Test status
Simulation time 2087347394 ps
CPU time 7.86 seconds
Started Jun 07 07:30:06 PM PDT 24
Finished Jun 07 07:30:16 PM PDT 24
Peak memory 225396 kb
Host smart-b58a8d2a-b2e2-4396-8eb2-7b0651b74cea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012493201 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_security_escalation.1012493201
Directory /workspace/12.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/12.lc_ctrl_smoke.1896044126
Short name T871
Test name
Test status
Simulation time 35023842 ps
CPU time 1.23 seconds
Started Jun 07 07:30:07 PM PDT 24
Finished Jun 07 07:30:09 PM PDT 24
Peak memory 218192 kb
Host smart-a3d788f6-d903-4f66-b6ee-347453192ec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896044126 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_smoke.1896044126
Directory /workspace/12.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_failure.1497643909
Short name T510
Test name
Test status
Simulation time 957274507 ps
CPU time 29.77 seconds
Started Jun 07 07:30:06 PM PDT 24
Finished Jun 07 07:30:38 PM PDT 24
Peak memory 251464 kb
Host smart-a9bf02bd-d6d8-46e4-8246-6eac9a1d011e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497643909 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_failure.1497643909
Directory /workspace/12.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_post_trans.2826738312
Short name T418
Test name
Test status
Simulation time 87818707 ps
CPU time 6.86 seconds
Started Jun 07 07:30:10 PM PDT 24
Finished Jun 07 07:30:18 PM PDT 24
Peak memory 251400 kb
Host smart-de8e5423-7dd4-4be6-b7c9-6b393b7c9ecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826738312 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_post_trans.2826738312
Directory /workspace/12.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_stress_all_with_rand_reset.3868211173
Short name T151
Test name
Test status
Simulation time 12445383935 ps
CPU time 450.53 seconds
Started Jun 07 07:30:13 PM PDT 24
Finished Jun 07 07:37:46 PM PDT 24
Peak memory 284328 kb
Host smart-768bf607-cec0-4fdc-a2b4-d81ea3b51f11
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3868211173 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_stress_all_with_rand_reset.3868211173
Directory /workspace/12.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.lc_ctrl_alert_test.1689507095
Short name T390
Test name
Test status
Simulation time 20975182 ps
CPU time 1 seconds
Started Jun 07 07:30:17 PM PDT 24
Finished Jun 07 07:30:21 PM PDT 24
Peak memory 209408 kb
Host smart-109fee54-736d-4f1d-a35c-35a6256ea816
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689507095 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_alert_test.1689507095
Directory /workspace/13.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.lc_ctrl_errors.16897343
Short name T651
Test name
Test status
Simulation time 689561705 ps
CPU time 11.62 seconds
Started Jun 07 07:30:16 PM PDT 24
Finished Jun 07 07:30:30 PM PDT 24
Peak memory 218676 kb
Host smart-f423775b-e000-42f3-9476-48110f58aead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16897343 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_errors.16897343
Directory /workspace/13.lc_ctrl_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_access.4078893507
Short name T688
Test name
Test status
Simulation time 107045811 ps
CPU time 1.77 seconds
Started Jun 07 07:30:16 PM PDT 24
Finished Jun 07 07:30:20 PM PDT 24
Peak memory 217544 kb
Host smart-de091a5d-d7e6-4f00-be87-b8d9d4bf01d6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078893507 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_access.4078893507
Directory /workspace/13.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_errors.3975189517
Short name T662
Test name
Test status
Simulation time 2540619605 ps
CPU time 53.09 seconds
Started Jun 07 07:30:14 PM PDT 24
Finished Jun 07 07:31:09 PM PDT 24
Peak memory 219436 kb
Host smart-a235d489-04fb-40f6-887f-0bc3a3a3bb57
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975189517 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_e
rrors.3975189517
Directory /workspace/13.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_prog_failure.4266168870
Short name T717
Test name
Test status
Simulation time 1944883899 ps
CPU time 5.39 seconds
Started Jun 07 07:30:13 PM PDT 24
Finished Jun 07 07:30:20 PM PDT 24
Peak memory 218724 kb
Host smart-8add8175-aec6-4bdd-a40b-4f6bece019c6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266168870 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jta
g_prog_failure.4266168870
Directory /workspace/13.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_smoke.1997882932
Short name T448
Test name
Test status
Simulation time 448423942 ps
CPU time 5.68 seconds
Started Jun 07 07:30:15 PM PDT 24
Finished Jun 07 07:30:23 PM PDT 24
Peak memory 218184 kb
Host smart-12d5fbf2-cbc4-4675-9e97-237bc6a5b5f0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997882932 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_smoke
.1997882932
Directory /workspace/13.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_failure.232715166
Short name T22
Test name
Test status
Simulation time 5978273539 ps
CPU time 104.97 seconds
Started Jun 07 07:30:15 PM PDT 24
Finished Jun 07 07:32:02 PM PDT 24
Peak memory 284248 kb
Host smart-83807a57-7e16-492b-9262-3819713b75bf
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232715166 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jta
g_state_failure.232715166
Directory /workspace/13.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_post_trans.2529713958
Short name T721
Test name
Test status
Simulation time 4357952433 ps
CPU time 19.61 seconds
Started Jun 07 07:30:17 PM PDT 24
Finished Jun 07 07:30:40 PM PDT 24
Peak memory 251084 kb
Host smart-993bd35b-3157-4f21-b8ce-ae818bc60228
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529713958 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl
_jtag_state_post_trans.2529713958
Directory /workspace/13.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_prog_failure.1269592468
Short name T523
Test name
Test status
Simulation time 56342616 ps
CPU time 2.38 seconds
Started Jun 07 07:30:15 PM PDT 24
Finished Jun 07 07:30:21 PM PDT 24
Peak memory 222728 kb
Host smart-4423c396-4e51-46e4-adc4-d19aa87ba7aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269592468 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_prog_failure.1269592468
Directory /workspace/13.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_mubi.3468352648
Short name T456
Test name
Test status
Simulation time 1477365756 ps
CPU time 18.05 seconds
Started Jun 07 07:30:13 PM PDT 24
Finished Jun 07 07:30:34 PM PDT 24
Peak memory 219376 kb
Host smart-f1d6d44a-f96a-4b6f-a6d8-79ea702733dd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468352648 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_mubi.3468352648
Directory /workspace/13.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_digest.2409611598
Short name T609
Test name
Test status
Simulation time 304774189 ps
CPU time 10.11 seconds
Started Jun 07 07:30:14 PM PDT 24
Finished Jun 07 07:30:27 PM PDT 24
Peak memory 226540 kb
Host smart-ccfae2f2-3e46-41b8-a64a-65a543b31cc0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409611598 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_d
igest.2409611598
Directory /workspace/13.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_mux.120866863
Short name T450
Test name
Test status
Simulation time 1545225325 ps
CPU time 12.97 seconds
Started Jun 07 07:30:14 PM PDT 24
Finished Jun 07 07:30:29 PM PDT 24
Peak memory 218712 kb
Host smart-4802ec55-d9cf-411c-8a1c-b2768e443514
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120866863 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_mux.120866863
Directory /workspace/13.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/13.lc_ctrl_security_escalation.3959186258
Short name T643
Test name
Test status
Simulation time 379951437 ps
CPU time 9.17 seconds
Started Jun 07 07:30:14 PM PDT 24
Finished Jun 07 07:30:25 PM PDT 24
Peak memory 218736 kb
Host smart-b46a0fef-a2c6-4a25-82b7-7a1ea1f044fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959186258 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_security_escalation.3959186258
Directory /workspace/13.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/13.lc_ctrl_smoke.1520222596
Short name T262
Test name
Test status
Simulation time 112462765 ps
CPU time 7.36 seconds
Started Jun 07 07:30:16 PM PDT 24
Finished Jun 07 07:30:26 PM PDT 24
Peak memory 218164 kb
Host smart-5c5922d2-24d9-4ebf-a210-60099d11156a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520222596 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_smoke.1520222596
Directory /workspace/13.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_failure.2056079947
Short name T772
Test name
Test status
Simulation time 4510732876 ps
CPU time 32.19 seconds
Started Jun 07 07:30:14 PM PDT 24
Finished Jun 07 07:30:49 PM PDT 24
Peak memory 251464 kb
Host smart-e938b23e-53d5-4a30-87d2-435c3ca074ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056079947 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_failure.2056079947
Directory /workspace/13.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_post_trans.4112582557
Short name T492
Test name
Test status
Simulation time 275359950 ps
CPU time 6.16 seconds
Started Jun 07 07:30:15 PM PDT 24
Finished Jun 07 07:30:25 PM PDT 24
Peak memory 247304 kb
Host smart-7c6cf29b-cf19-466f-a3e4-3faea3a9fe25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112582557 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_post_trans.4112582557
Directory /workspace/13.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all.3744255578
Short name T105
Test name
Test status
Simulation time 44547282429 ps
CPU time 392.11 seconds
Started Jun 07 07:30:18 PM PDT 24
Finished Jun 07 07:36:53 PM PDT 24
Peak memory 279468 kb
Host smart-fd473139-8753-4916-a5c9-6d842773901a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744255578 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.lc_ctrl_stress_all.3744255578
Directory /workspace/13.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all_with_rand_reset.1193022042
Short name T149
Test name
Test status
Simulation time 80523781930 ps
CPU time 1618.46 seconds
Started Jun 07 07:30:16 PM PDT 24
Finished Jun 07 07:57:18 PM PDT 24
Peak memory 530096 kb
Host smart-f0dd24fb-2167-4277-82a1-3dbb14979808
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1193022042 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_stress_all_with_rand_reset.1193022042
Directory /workspace/13.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.lc_ctrl_volatile_unlock_smoke.290363534
Short name T73
Test name
Test status
Simulation time 42401331 ps
CPU time 1.07 seconds
Started Jun 07 07:30:16 PM PDT 24
Finished Jun 07 07:30:20 PM PDT 24
Peak memory 212440 kb
Host smart-0051cbd0-cd1c-4446-b1c4-edcdbe8a5877
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290363534 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ct
rl_volatile_unlock_smoke.290363534
Directory /workspace/13.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_alert_test.973011552
Short name T540
Test name
Test status
Simulation time 132664189 ps
CPU time 0.92 seconds
Started Jun 07 07:30:16 PM PDT 24
Finished Jun 07 07:30:20 PM PDT 24
Peak memory 209440 kb
Host smart-b5429c60-b42d-43bc-903a-bfc579a18e3d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973011552 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_alert_test.973011552
Directory /workspace/14.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_access.3453132171
Short name T652
Test name
Test status
Simulation time 1832481022 ps
CPU time 21.45 seconds
Started Jun 07 07:30:16 PM PDT 24
Finished Jun 07 07:30:41 PM PDT 24
Peak memory 217868 kb
Host smart-16ff9b58-8a9f-4c4c-8929-a54eb90f7d6d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453132171 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_access.3453132171
Directory /workspace/14.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_errors.2644906345
Short name T774
Test name
Test status
Simulation time 7509186042 ps
CPU time 54.75 seconds
Started Jun 07 07:30:17 PM PDT 24
Finished Jun 07 07:31:15 PM PDT 24
Peak memory 219364 kb
Host smart-e803a9bd-7560-4709-93c4-a809042de45e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644906345 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_e
rrors.2644906345
Directory /workspace/14.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_prog_failure.1115261987
Short name T107
Test name
Test status
Simulation time 816734309 ps
CPU time 11.82 seconds
Started Jun 07 07:30:15 PM PDT 24
Finished Jun 07 07:30:29 PM PDT 24
Peak memory 218736 kb
Host smart-2e11e0f8-08f2-4c51-a78d-7891760eba2a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115261987 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jta
g_prog_failure.1115261987
Directory /workspace/14.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_smoke.1060316091
Short name T611
Test name
Test status
Simulation time 1068136570 ps
CPU time 7.3 seconds
Started Jun 07 07:30:18 PM PDT 24
Finished Jun 07 07:30:28 PM PDT 24
Peak memory 218228 kb
Host smart-86c577e2-0279-4c96-840f-c037df36d4e6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060316091 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_smoke
.1060316091
Directory /workspace/14.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_failure.1142011487
Short name T258
Test name
Test status
Simulation time 2051674103 ps
CPU time 43.18 seconds
Started Jun 07 07:30:15 PM PDT 24
Finished Jun 07 07:31:01 PM PDT 24
Peak memory 277004 kb
Host smart-c620d728-60e3-41b5-9e03-1bbbb28ea35c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142011487 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jt
ag_state_failure.1142011487
Directory /workspace/14.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_post_trans.1087360552
Short name T463
Test name
Test status
Simulation time 1823886601 ps
CPU time 20.25 seconds
Started Jun 07 07:30:19 PM PDT 24
Finished Jun 07 07:30:42 PM PDT 24
Peak memory 251392 kb
Host smart-3484bf20-a2da-4809-a38a-4573ac693344
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087360552 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl
_jtag_state_post_trans.1087360552
Directory /workspace/14.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_prog_failure.1902299380
Short name T220
Test name
Test status
Simulation time 514142126 ps
CPU time 2.31 seconds
Started Jun 07 07:30:15 PM PDT 24
Finished Jun 07 07:30:20 PM PDT 24
Peak memory 218552 kb
Host smart-0f9b254e-d334-4bf0-9f98-8aeea4c50e50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902299380 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_prog_failure.1902299380
Directory /workspace/14.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_mubi.2336664483
Short name T184
Test name
Test status
Simulation time 438901461 ps
CPU time 9.72 seconds
Started Jun 07 07:30:16 PM PDT 24
Finished Jun 07 07:30:28 PM PDT 24
Peak memory 219396 kb
Host smart-7c8e13a7-b4d6-48f0-8482-7099a640ddcc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336664483 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_mubi.2336664483
Directory /workspace/14.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_digest.3039292408
Short name T222
Test name
Test status
Simulation time 1257273772 ps
CPU time 13.07 seconds
Started Jun 07 07:30:17 PM PDT 24
Finished Jun 07 07:30:33 PM PDT 24
Peak memory 218724 kb
Host smart-accc2e4c-e3a6-48cc-a67a-5868912e6789
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039292408 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_d
igest.3039292408
Directory /workspace/14.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_mux.970158167
Short name T276
Test name
Test status
Simulation time 298407245 ps
CPU time 8.32 seconds
Started Jun 07 07:30:18 PM PDT 24
Finished Jun 07 07:30:29 PM PDT 24
Peak memory 226476 kb
Host smart-8f04b475-8424-4d1f-b778-663ffcfccecb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970158167 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_mux.970158167
Directory /workspace/14.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/14.lc_ctrl_security_escalation.1293167552
Short name T54
Test name
Test status
Simulation time 554890423 ps
CPU time 12.4 seconds
Started Jun 07 07:30:18 PM PDT 24
Finished Jun 07 07:30:33 PM PDT 24
Peak memory 226344 kb
Host smart-bedd6d59-0145-4c7e-8f1d-dd98ea01ca51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293167552 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_security_escalation.1293167552
Directory /workspace/14.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/14.lc_ctrl_smoke.1535965827
Short name T565
Test name
Test status
Simulation time 123469777 ps
CPU time 7 seconds
Started Jun 07 07:30:14 PM PDT 24
Finished Jun 07 07:30:24 PM PDT 24
Peak memory 218224 kb
Host smart-ba983d66-2b46-4d78-9b39-4300ce7c5525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535965827 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_smoke.1535965827
Directory /workspace/14.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_failure.1413365716
Short name T257
Test name
Test status
Simulation time 267572190 ps
CPU time 29.23 seconds
Started Jun 07 07:30:17 PM PDT 24
Finished Jun 07 07:30:49 PM PDT 24
Peak memory 251420 kb
Host smart-a3547956-e990-4b24-ad4b-f273b4a64bf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413365716 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_failure.1413365716
Directory /workspace/14.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_post_trans.40574913
Short name T855
Test name
Test status
Simulation time 59549249 ps
CPU time 3.26 seconds
Started Jun 07 07:30:18 PM PDT 24
Finished Jun 07 07:30:24 PM PDT 24
Peak memory 221792 kb
Host smart-ac7d1373-8385-4464-9b42-cf16221901be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40574913 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_post_trans.40574913
Directory /workspace/14.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_stress_all.3895444491
Short name T511
Test name
Test status
Simulation time 4494819540 ps
CPU time 88.22 seconds
Started Jun 07 07:30:19 PM PDT 24
Finished Jun 07 07:31:49 PM PDT 24
Peak memory 251444 kb
Host smart-ab4a6452-b493-49b0-8eee-da891459be85
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895444491 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.lc_ctrl_stress_all.3895444491
Directory /workspace/14.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.lc_ctrl_stress_all_with_rand_reset.3539171716
Short name T112
Test name
Test status
Simulation time 132324801372 ps
CPU time 1082.71 seconds
Started Jun 07 07:30:22 PM PDT 24
Finished Jun 07 07:48:27 PM PDT 24
Peak memory 286132 kb
Host smart-f3b3c893-26de-471d-9c07-2f4137de1890
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3539171716 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_stress_all_with_rand_reset.3539171716
Directory /workspace/14.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.lc_ctrl_volatile_unlock_smoke.538931422
Short name T318
Test name
Test status
Simulation time 13783050 ps
CPU time 0.78 seconds
Started Jun 07 07:30:17 PM PDT 24
Finished Jun 07 07:30:20 PM PDT 24
Peak memory 209532 kb
Host smart-46d2d62c-d312-45d8-8419-32b597b506cf
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538931422 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ct
rl_volatile_unlock_smoke.538931422
Directory /workspace/14.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_alert_test.3102029488
Short name T470
Test name
Test status
Simulation time 20579836 ps
CPU time 1.23 seconds
Started Jun 07 07:30:26 PM PDT 24
Finished Jun 07 07:30:31 PM PDT 24
Peak memory 209432 kb
Host smart-bb413b3f-592d-4437-8f51-21deec4701ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102029488 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_alert_test.3102029488
Directory /workspace/15.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.lc_ctrl_errors.2730626867
Short name T730
Test name
Test status
Simulation time 1743346053 ps
CPU time 16.81 seconds
Started Jun 07 07:30:25 PM PDT 24
Finished Jun 07 07:30:44 PM PDT 24
Peak memory 226488 kb
Host smart-b5b32970-e9bb-4d7e-862d-2162f8e9194d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730626867 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_errors.2730626867
Directory /workspace/15.lc_ctrl_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_access.1171715443
Short name T27
Test name
Test status
Simulation time 1396414012 ps
CPU time 9.48 seconds
Started Jun 07 07:30:31 PM PDT 24
Finished Jun 07 07:30:43 PM PDT 24
Peak memory 217968 kb
Host smart-89825e68-de53-4615-ae5b-5c181471fd3f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171715443 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_access.1171715443
Directory /workspace/15.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_errors.4098511057
Short name T732
Test name
Test status
Simulation time 14779309697 ps
CPU time 29.1 seconds
Started Jun 07 07:30:29 PM PDT 24
Finished Jun 07 07:31:02 PM PDT 24
Peak memory 219404 kb
Host smart-91bdf13d-05fc-419f-8ba0-791026deeccc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098511057 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_e
rrors.4098511057
Directory /workspace/15.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_prog_failure.2386464423
Short name T372
Test name
Test status
Simulation time 230668645 ps
CPU time 5.01 seconds
Started Jun 07 07:30:28 PM PDT 24
Finished Jun 07 07:30:37 PM PDT 24
Peak memory 218796 kb
Host smart-0bc39365-094f-4d9b-8e2d-167bb7b5b61e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386464423 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jta
g_prog_failure.2386464423
Directory /workspace/15.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_smoke.348306540
Short name T274
Test name
Test status
Simulation time 2407984289 ps
CPU time 5.77 seconds
Started Jun 07 07:30:26 PM PDT 24
Finished Jun 07 07:30:35 PM PDT 24
Peak memory 218280 kb
Host smart-aa2c00cd-afed-4c67-a900-df43d92a3d72
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348306540 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_smoke.
348306540
Directory /workspace/15.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_failure.1676904848
Short name T332
Test name
Test status
Simulation time 4569372955 ps
CPU time 50.26 seconds
Started Jun 07 07:30:28 PM PDT 24
Finished Jun 07 07:31:22 PM PDT 24
Peak memory 273708 kb
Host smart-0617ba04-a668-404c-beeb-cf558e3ec544
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676904848 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jt
ag_state_failure.1676904848
Directory /workspace/15.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_post_trans.3123862117
Short name T465
Test name
Test status
Simulation time 2795163687 ps
CPU time 18.63 seconds
Started Jun 07 07:30:25 PM PDT 24
Finished Jun 07 07:30:47 PM PDT 24
Peak memory 218772 kb
Host smart-da399e56-12f8-43cc-9283-e5ebd5045f49
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123862117 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl
_jtag_state_post_trans.3123862117
Directory /workspace/15.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_prog_failure.2426243808
Short name T833
Test name
Test status
Simulation time 208869328 ps
CPU time 2.68 seconds
Started Jun 07 07:30:24 PM PDT 24
Finished Jun 07 07:30:29 PM PDT 24
Peak memory 218640 kb
Host smart-e9cc828c-8408-4ee8-9fee-c28bf2e22db5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426243808 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_prog_failure.2426243808
Directory /workspace/15.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_mubi.386079028
Short name T41
Test name
Test status
Simulation time 1308259890 ps
CPU time 14.24 seconds
Started Jun 07 07:30:26 PM PDT 24
Finished Jun 07 07:30:43 PM PDT 24
Peak memory 226492 kb
Host smart-c21d6676-1123-491f-99b4-778df90924eb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386079028 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_mubi.386079028
Directory /workspace/15.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_digest.808227816
Short name T442
Test name
Test status
Simulation time 698102250 ps
CPU time 19 seconds
Started Jun 07 07:30:26 PM PDT 24
Finished Jun 07 07:30:48 PM PDT 24
Peak memory 218728 kb
Host smart-49c02224-439c-4e75-bec5-7376f68d1076
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808227816 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_di
gest.808227816
Directory /workspace/15.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_mux.3225994510
Short name T186
Test name
Test status
Simulation time 889478273 ps
CPU time 6.4 seconds
Started Jun 07 07:30:23 PM PDT 24
Finished Jun 07 07:30:32 PM PDT 24
Peak memory 218660 kb
Host smart-9ba73498-8b1d-4638-8fcd-0c916e7226fd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225994510 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_mux.
3225994510
Directory /workspace/15.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/15.lc_ctrl_security_escalation.3013556961
Short name T856
Test name
Test status
Simulation time 429443294 ps
CPU time 11.83 seconds
Started Jun 07 07:30:24 PM PDT 24
Finished Jun 07 07:30:39 PM PDT 24
Peak memory 218756 kb
Host smart-541fe607-737d-46f4-bceb-dc587890cf69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013556961 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_security_escalation.3013556961
Directory /workspace/15.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/15.lc_ctrl_smoke.3182961104
Short name T368
Test name
Test status
Simulation time 132084358 ps
CPU time 7.89 seconds
Started Jun 07 07:30:15 PM PDT 24
Finished Jun 07 07:30:26 PM PDT 24
Peak memory 218224 kb
Host smart-caa4814f-0dfb-41a9-9bc4-27d32d87ce89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182961104 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_smoke.3182961104
Directory /workspace/15.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_failure.449674404
Short name T329
Test name
Test status
Simulation time 271682125 ps
CPU time 24.26 seconds
Started Jun 07 07:30:23 PM PDT 24
Finished Jun 07 07:30:50 PM PDT 24
Peak memory 251408 kb
Host smart-694c9356-b90b-463c-a5f4-920e68c1dfe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449674404 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_failure.449674404
Directory /workspace/15.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_post_trans.2178904935
Short name T636
Test name
Test status
Simulation time 70030118 ps
CPU time 7.81 seconds
Started Jun 07 07:30:25 PM PDT 24
Finished Jun 07 07:30:36 PM PDT 24
Peak memory 251252 kb
Host smart-e77182e2-b323-4c67-b1b1-0ad4b36cdfca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178904935 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_post_trans.2178904935
Directory /workspace/15.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all.4112408464
Short name T544
Test name
Test status
Simulation time 15414984968 ps
CPU time 52.04 seconds
Started Jun 07 07:30:25 PM PDT 24
Finished Jun 07 07:31:20 PM PDT 24
Peak memory 251532 kb
Host smart-c625044e-bfac-4bdf-b520-fa8b31947449
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112408464 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.lc_ctrl_stress_all.4112408464
Directory /workspace/15.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.lc_ctrl_volatile_unlock_smoke.1877320610
Short name T285
Test name
Test status
Simulation time 15459159 ps
CPU time 1 seconds
Started Jun 07 07:30:19 PM PDT 24
Finished Jun 07 07:30:22 PM PDT 24
Peak memory 212508 kb
Host smart-47743690-ffe9-43c5-b829-017beb9124bf
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877320610 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_c
trl_volatile_unlock_smoke.1877320610
Directory /workspace/15.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_alert_test.3378986356
Short name T286
Test name
Test status
Simulation time 27062833 ps
CPU time 1.29 seconds
Started Jun 07 07:30:34 PM PDT 24
Finished Jun 07 07:30:37 PM PDT 24
Peak memory 209404 kb
Host smart-231d27ab-0783-4630-b840-281f658bb96f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378986356 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_alert_test.3378986356
Directory /workspace/16.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.lc_ctrl_errors.2619513978
Short name T464
Test name
Test status
Simulation time 483278016 ps
CPU time 12.74 seconds
Started Jun 07 07:30:27 PM PDT 24
Finished Jun 07 07:30:43 PM PDT 24
Peak memory 218680 kb
Host smart-c8950242-f767-45db-bc7c-ab30343b0739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619513978 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_errors.2619513978
Directory /workspace/16.lc_ctrl_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_access.2422399040
Short name T406
Test name
Test status
Simulation time 1237759918 ps
CPU time 15.47 seconds
Started Jun 07 07:30:26 PM PDT 24
Finished Jun 07 07:30:45 PM PDT 24
Peak memory 217780 kb
Host smart-003e4684-0609-46c4-99df-e2fa298725dc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422399040 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_access.2422399040
Directory /workspace/16.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_errors.3467103385
Short name T803
Test name
Test status
Simulation time 5987641879 ps
CPU time 28.35 seconds
Started Jun 07 07:30:29 PM PDT 24
Finished Jun 07 07:31:00 PM PDT 24
Peak memory 226592 kb
Host smart-6e8081a4-7649-44c5-a42f-8121f2233b12
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467103385 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_e
rrors.3467103385
Directory /workspace/16.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_prog_failure.660576916
Short name T341
Test name
Test status
Simulation time 4232798642 ps
CPU time 13.48 seconds
Started Jun 07 07:30:27 PM PDT 24
Finished Jun 07 07:30:44 PM PDT 24
Peak memory 218736 kb
Host smart-af7fff9e-eb24-4366-b066-5275b1425ec3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660576916 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag
_prog_failure.660576916
Directory /workspace/16.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_smoke.2542599524
Short name T602
Test name
Test status
Simulation time 142722303 ps
CPU time 2.15 seconds
Started Jun 07 07:30:26 PM PDT 24
Finished Jun 07 07:30:31 PM PDT 24
Peak memory 218232 kb
Host smart-491cba99-c4c7-4b0c-ad41-f6fa0f1cc516
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542599524 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_smoke
.2542599524
Directory /workspace/16.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_failure.2677237624
Short name T780
Test name
Test status
Simulation time 5978968296 ps
CPU time 110.97 seconds
Started Jun 07 07:30:26 PM PDT 24
Finished Jun 07 07:32:21 PM PDT 24
Peak memory 278548 kb
Host smart-3d8fe6d5-d3d3-44b7-88d6-a917c9b0fa69
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677237624 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jt
ag_state_failure.2677237624
Directory /workspace/16.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_post_trans.3422879699
Short name T621
Test name
Test status
Simulation time 773507562 ps
CPU time 21.66 seconds
Started Jun 07 07:30:25 PM PDT 24
Finished Jun 07 07:30:50 PM PDT 24
Peak memory 251028 kb
Host smart-192052ab-bc07-40e5-94c9-3542a902dd80
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422879699 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl
_jtag_state_post_trans.3422879699
Directory /workspace/16.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_prog_failure.3542863070
Short name T715
Test name
Test status
Simulation time 323286366 ps
CPU time 2.7 seconds
Started Jun 07 07:30:27 PM PDT 24
Finished Jun 07 07:30:34 PM PDT 24
Peak memory 218608 kb
Host smart-40f5f244-c4cb-4dbc-b6f0-7ffa1f7c6f4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542863070 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_prog_failure.3542863070
Directory /workspace/16.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_mubi.4088412832
Short name T342
Test name
Test status
Simulation time 293402956 ps
CPU time 9.48 seconds
Started Jun 07 07:30:23 PM PDT 24
Finished Jun 07 07:30:35 PM PDT 24
Peak memory 226528 kb
Host smart-39bcd1f4-b210-4e96-b7ce-0abcc416beb0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088412832 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_mubi.4088412832
Directory /workspace/16.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_digest.1277723237
Short name T260
Test name
Test status
Simulation time 647345471 ps
CPU time 13.02 seconds
Started Jun 07 07:30:28 PM PDT 24
Finished Jun 07 07:30:45 PM PDT 24
Peak memory 226516 kb
Host smart-55e4f1ff-ded7-41db-8165-b7ba2af64ddc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277723237 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_d
igest.1277723237
Directory /workspace/16.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_mux.3699703426
Short name T648
Test name
Test status
Simulation time 602947062 ps
CPU time 9.58 seconds
Started Jun 07 07:30:27 PM PDT 24
Finished Jun 07 07:30:40 PM PDT 24
Peak memory 226504 kb
Host smart-7b5c627c-b7ab-42d4-acab-bab4cad5105b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699703426 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_mux.
3699703426
Directory /workspace/16.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/16.lc_ctrl_security_escalation.3242099396
Short name T55
Test name
Test status
Simulation time 236983465 ps
CPU time 9.41 seconds
Started Jun 07 07:30:27 PM PDT 24
Finished Jun 07 07:30:39 PM PDT 24
Peak memory 226540 kb
Host smart-44fbaed8-9bfb-409d-98b3-6ae3e3d45aa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242099396 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_security_escalation.3242099396
Directory /workspace/16.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/16.lc_ctrl_smoke.4218951434
Short name T756
Test name
Test status
Simulation time 52651623 ps
CPU time 2.93 seconds
Started Jun 07 07:30:25 PM PDT 24
Finished Jun 07 07:30:31 PM PDT 24
Peak memory 223556 kb
Host smart-0e6026f8-343b-437a-a641-d3513869a99d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218951434 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_smoke.4218951434
Directory /workspace/16.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_failure.3285170151
Short name T294
Test name
Test status
Simulation time 247077962 ps
CPU time 29.18 seconds
Started Jun 07 07:30:26 PM PDT 24
Finished Jun 07 07:30:59 PM PDT 24
Peak memory 251540 kb
Host smart-2fa2f3ca-24cb-4274-8270-bb0111b31300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285170151 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_failure.3285170151
Directory /workspace/16.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_post_trans.3217939663
Short name T483
Test name
Test status
Simulation time 403922847 ps
CPU time 8.77 seconds
Started Jun 07 07:30:28 PM PDT 24
Finished Jun 07 07:30:40 PM PDT 24
Peak memory 251372 kb
Host smart-0d6e5574-16d9-4528-9bbe-9312da3a64c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217939663 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_post_trans.3217939663
Directory /workspace/16.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_stress_all.173107120
Short name T379
Test name
Test status
Simulation time 4038240572 ps
CPU time 81.49 seconds
Started Jun 07 07:30:26 PM PDT 24
Finished Jun 07 07:31:50 PM PDT 24
Peak memory 251504 kb
Host smart-6a7a8726-7c4a-45d2-9b57-0544816206ba
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173107120 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.lc_ctrl_stress_all.173107120
Directory /workspace/16.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.lc_ctrl_stress_all_with_rand_reset.2545568573
Short name T466
Test name
Test status
Simulation time 59755457570 ps
CPU time 914.16 seconds
Started Jun 07 07:30:25 PM PDT 24
Finished Jun 07 07:45:42 PM PDT 24
Peak memory 276384 kb
Host smart-39a03f3d-85ff-4181-b017-bb47f23710f4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2545568573 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_stress_all_with_rand_reset.2545568573
Directory /workspace/16.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.lc_ctrl_volatile_unlock_smoke.65726595
Short name T558
Test name
Test status
Simulation time 37804424 ps
CPU time 0.85 seconds
Started Jun 07 07:30:25 PM PDT 24
Finished Jun 07 07:30:28 PM PDT 24
Peak memory 208744 kb
Host smart-8338872f-7964-4641-a271-3c19da29212d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65726595 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vol
atile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctr
l_volatile_unlock_smoke.65726595
Directory /workspace/16.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_alert_test.915158533
Short name T335
Test name
Test status
Simulation time 181399971 ps
CPU time 1.06 seconds
Started Jun 07 07:30:29 PM PDT 24
Finished Jun 07 07:30:33 PM PDT 24
Peak memory 209380 kb
Host smart-b82dad5b-4fd8-494e-9da1-a2e9ff1fd1f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915158533 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_alert_test.915158533
Directory /workspace/17.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.lc_ctrl_errors.1416048685
Short name T154
Test name
Test status
Simulation time 3017432338 ps
CPU time 12.54 seconds
Started Jun 07 07:30:33 PM PDT 24
Finished Jun 07 07:30:48 PM PDT 24
Peak memory 219408 kb
Host smart-bb30c749-b26f-43f6-96cd-515b9a68df66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416048685 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_errors.1416048685
Directory /workspace/17.lc_ctrl_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_access.2186947370
Short name T676
Test name
Test status
Simulation time 699139648 ps
CPU time 9.94 seconds
Started Jun 07 07:30:30 PM PDT 24
Finished Jun 07 07:30:43 PM PDT 24
Peak memory 217952 kb
Host smart-161d5bef-557e-4b76-9692-4d850a7a24cc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186947370 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_access.2186947370
Directory /workspace/17.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_errors.1574906933
Short name T530
Test name
Test status
Simulation time 13792209579 ps
CPU time 54.01 seconds
Started Jun 07 07:30:34 PM PDT 24
Finished Jun 07 07:31:30 PM PDT 24
Peak memory 220152 kb
Host smart-15b08eb4-2b4b-46b6-a9ad-4eee382175a1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574906933 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_e
rrors.1574906933
Directory /workspace/17.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_prog_failure.723965648
Short name T696
Test name
Test status
Simulation time 564956812 ps
CPU time 16.32 seconds
Started Jun 07 07:30:33 PM PDT 24
Finished Jun 07 07:30:52 PM PDT 24
Peak memory 218716 kb
Host smart-c450389a-ffcf-4454-9ae9-276e952d811b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723965648 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag
_prog_failure.723965648
Directory /workspace/17.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_smoke.1935708081
Short name T797
Test name
Test status
Simulation time 84333654 ps
CPU time 1.88 seconds
Started Jun 07 07:30:30 PM PDT 24
Finished Jun 07 07:30:35 PM PDT 24
Peak memory 218176 kb
Host smart-61a00d20-e0a0-4fe8-9c90-6ec7844a8c3b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935708081 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_smoke
.1935708081
Directory /workspace/17.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_failure.1387152718
Short name T153
Test name
Test status
Simulation time 1087891204 ps
CPU time 34.95 seconds
Started Jun 07 07:30:34 PM PDT 24
Finished Jun 07 07:31:11 PM PDT 24
Peak memory 276564 kb
Host smart-649e1b0e-ec73-4d50-a639-a1a6386c681a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387152718 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jt
ag_state_failure.1387152718
Directory /workspace/17.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_post_trans.3580114325
Short name T719
Test name
Test status
Simulation time 1785980325 ps
CPU time 31.37 seconds
Started Jun 07 07:30:28 PM PDT 24
Finished Jun 07 07:31:03 PM PDT 24
Peak memory 251352 kb
Host smart-e6424367-abe8-438f-833c-216a4c6a16d4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580114325 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl
_jtag_state_post_trans.3580114325
Directory /workspace/17.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_prog_failure.499098513
Short name T218
Test name
Test status
Simulation time 108451174 ps
CPU time 1.44 seconds
Started Jun 07 07:30:30 PM PDT 24
Finished Jun 07 07:30:34 PM PDT 24
Peak memory 218724 kb
Host smart-8aba3524-da32-4b17-9644-d56fce7899d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499098513 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_prog_failure.499098513
Directory /workspace/17.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_mubi.233057658
Short name T836
Test name
Test status
Simulation time 204347558 ps
CPU time 10.32 seconds
Started Jun 07 07:30:34 PM PDT 24
Finished Jun 07 07:30:47 PM PDT 24
Peak memory 218740 kb
Host smart-00bc5909-b044-41e8-b471-cfe8cf0e4226
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233057658 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_mubi.233057658
Directory /workspace/17.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_digest.4204180321
Short name T562
Test name
Test status
Simulation time 443951446 ps
CPU time 7.88 seconds
Started Jun 07 07:30:32 PM PDT 24
Finished Jun 07 07:30:43 PM PDT 24
Peak memory 218664 kb
Host smart-282544d3-e40a-4128-a102-62e57e409317
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204180321 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_d
igest.4204180321
Directory /workspace/17.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/17.lc_ctrl_smoke.4049872192
Short name T787
Test name
Test status
Simulation time 1304168788 ps
CPU time 9.88 seconds
Started Jun 07 07:30:27 PM PDT 24
Finished Jun 07 07:30:41 PM PDT 24
Peak memory 218200 kb
Host smart-7b6ec30c-ed10-49b2-912e-b54625fd9b7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049872192 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_smoke.4049872192
Directory /workspace/17.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_failure.4287702175
Short name T702
Test name
Test status
Simulation time 270409686 ps
CPU time 28.17 seconds
Started Jun 07 07:30:30 PM PDT 24
Finished Jun 07 07:31:05 PM PDT 24
Peak memory 251412 kb
Host smart-69846e36-e4da-4de9-b5e7-960a3e935231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287702175 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_failure.4287702175
Directory /workspace/17.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_post_trans.2851033570
Short name T381
Test name
Test status
Simulation time 609199645 ps
CPU time 7.29 seconds
Started Jun 07 07:30:29 PM PDT 24
Finished Jun 07 07:30:40 PM PDT 24
Peak memory 246596 kb
Host smart-81bc0936-fa5e-44e6-90d0-c52a5e82df24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851033570 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_post_trans.2851033570
Directory /workspace/17.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all.1036821451
Short name T327
Test name
Test status
Simulation time 17843583566 ps
CPU time 102.04 seconds
Started Jun 07 07:30:30 PM PDT 24
Finished Jun 07 07:32:16 PM PDT 24
Peak memory 267860 kb
Host smart-0bc6fbb8-ae3c-4831-a49d-51ee6777aeee
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036821451 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.lc_ctrl_stress_all.1036821451
Directory /workspace/17.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.lc_ctrl_volatile_unlock_smoke.4181065608
Short name T295
Test name
Test status
Simulation time 46103196 ps
CPU time 0.83 seconds
Started Jun 07 07:30:33 PM PDT 24
Finished Jun 07 07:30:37 PM PDT 24
Peak memory 209328 kb
Host smart-f8edfd26-e665-406d-bee5-49c3176c29da
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181065608 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_c
trl_volatile_unlock_smoke.4181065608
Directory /workspace/17.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_alert_test.1944662417
Short name T90
Test name
Test status
Simulation time 98559613 ps
CPU time 0.93 seconds
Started Jun 07 07:30:36 PM PDT 24
Finished Jun 07 07:30:39 PM PDT 24
Peak memory 209368 kb
Host smart-2606196c-6fa0-49f2-a304-9d6fe70e6f11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944662417 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_alert_test.1944662417
Directory /workspace/18.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_access.704372382
Short name T24
Test name
Test status
Simulation time 685500878 ps
CPU time 14.74 seconds
Started Jun 07 07:30:38 PM PDT 24
Finished Jun 07 07:30:55 PM PDT 24
Peak memory 217760 kb
Host smart-b3d3bc71-bc66-476c-9dec-01d8ccce6df5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704372382 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_access.704372382
Directory /workspace/18.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_errors.1321680226
Short name T179
Test name
Test status
Simulation time 1830239026 ps
CPU time 29.26 seconds
Started Jun 07 07:30:37 PM PDT 24
Finished Jun 07 07:31:09 PM PDT 24
Peak memory 218684 kb
Host smart-7a932eae-121d-4c15-8e82-66063aa74a56
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321680226 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_e
rrors.1321680226
Directory /workspace/18.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_prog_failure.4272451360
Short name T19
Test name
Test status
Simulation time 687712346 ps
CPU time 5.6 seconds
Started Jun 07 07:30:39 PM PDT 24
Finished Jun 07 07:30:47 PM PDT 24
Peak memory 218712 kb
Host smart-ef03cdaf-6be4-4eb4-9df4-4411e2e91338
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272451360 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jta
g_prog_failure.4272451360
Directory /workspace/18.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_smoke.1083409098
Short name T857
Test name
Test status
Simulation time 2507845977 ps
CPU time 15.33 seconds
Started Jun 07 07:30:31 PM PDT 24
Finished Jun 07 07:30:49 PM PDT 24
Peak memory 218192 kb
Host smart-36879ade-8044-47ea-93c9-c25f3418af98
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083409098 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_smoke
.1083409098
Directory /workspace/18.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_failure.3192219808
Short name T814
Test name
Test status
Simulation time 1106682324 ps
CPU time 31.49 seconds
Started Jun 07 07:30:34 PM PDT 24
Finished Jun 07 07:31:07 PM PDT 24
Peak memory 251372 kb
Host smart-e302c917-3868-4bb8-9636-8f274ebc18de
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192219808 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jt
ag_state_failure.3192219808
Directory /workspace/18.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_post_trans.697895102
Short name T525
Test name
Test status
Simulation time 1344874861 ps
CPU time 30.1 seconds
Started Jun 07 07:30:35 PM PDT 24
Finished Jun 07 07:31:07 PM PDT 24
Peak memory 251424 kb
Host smart-28a321fa-e910-4670-a724-2989847a288e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697895102 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_
jtag_state_post_trans.697895102
Directory /workspace/18.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_prog_failure.2263237319
Short name T315
Test name
Test status
Simulation time 16532159 ps
CPU time 1.57 seconds
Started Jun 07 07:30:31 PM PDT 24
Finished Jun 07 07:30:36 PM PDT 24
Peak memory 222016 kb
Host smart-0ab7b1ed-7ad4-425e-a23e-6747ca90b38b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263237319 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_prog_failure.2263237319
Directory /workspace/18.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_mubi.58107501
Short name T736
Test name
Test status
Simulation time 388150013 ps
CPU time 17.91 seconds
Started Jun 07 07:30:36 PM PDT 24
Finished Jun 07 07:30:56 PM PDT 24
Peak memory 219472 kb
Host smart-8ca81b10-2176-47bb-8812-95b0cd3a76e6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58107501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_mubi.58107501
Directory /workspace/18.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_digest.165823529
Short name T251
Test name
Test status
Simulation time 570919963 ps
CPU time 13.25 seconds
Started Jun 07 07:30:37 PM PDT 24
Finished Jun 07 07:30:53 PM PDT 24
Peak memory 218672 kb
Host smart-582d2f9a-97ba-4e6c-8ec6-1a5d7b926690
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165823529 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_di
gest.165823529
Directory /workspace/18.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_mux.3799106015
Short name T428
Test name
Test status
Simulation time 1401618866 ps
CPU time 9.59 seconds
Started Jun 07 07:30:37 PM PDT 24
Finished Jun 07 07:30:49 PM PDT 24
Peak memory 226496 kb
Host smart-ed0796d3-1b68-4c20-9830-174307d2db17
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799106015 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_mux.
3799106015
Directory /workspace/18.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/18.lc_ctrl_security_escalation.2179908590
Short name T263
Test name
Test status
Simulation time 337054961 ps
CPU time 10.67 seconds
Started Jun 07 07:30:30 PM PDT 24
Finished Jun 07 07:30:44 PM PDT 24
Peak memory 225720 kb
Host smart-4daa6e03-0e5e-47b7-a28d-ddfcae682d92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179908590 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_security_escalation.2179908590
Directory /workspace/18.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/18.lc_ctrl_smoke.4134355179
Short name T794
Test name
Test status
Simulation time 268622588 ps
CPU time 3.05 seconds
Started Jun 07 07:30:30 PM PDT 24
Finished Jun 07 07:30:36 PM PDT 24
Peak memory 215680 kb
Host smart-d6d1b57b-3ccf-4d4b-b5de-ae4feebc7264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134355179 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_smoke.4134355179
Directory /workspace/18.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_failure.1978252776
Short name T322
Test name
Test status
Simulation time 420751224 ps
CPU time 20.03 seconds
Started Jun 07 07:30:29 PM PDT 24
Finished Jun 07 07:30:53 PM PDT 24
Peak memory 251388 kb
Host smart-9e372063-6ad0-41cc-b43e-504640179c87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978252776 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_failure.1978252776
Directory /workspace/18.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_post_trans.640531592
Short name T515
Test name
Test status
Simulation time 200763961 ps
CPU time 7.18 seconds
Started Jun 07 07:30:30 PM PDT 24
Finished Jun 07 07:30:40 PM PDT 24
Peak memory 250860 kb
Host smart-0dde2f62-a551-47fd-9bf6-45ffb36791b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640531592 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_post_trans.640531592
Directory /workspace/18.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all.3587246969
Short name T190
Test name
Test status
Simulation time 2850672101 ps
CPU time 48.54 seconds
Started Jun 07 07:30:37 PM PDT 24
Finished Jun 07 07:31:28 PM PDT 24
Peak memory 251444 kb
Host smart-2ae3dfc3-570f-41c0-8289-7f8c2dc987e3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587246969 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.lc_ctrl_stress_all.3587246969
Directory /workspace/18.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.lc_ctrl_volatile_unlock_smoke.654506856
Short name T32
Test name
Test status
Simulation time 13572256 ps
CPU time 0.95 seconds
Started Jun 07 07:30:33 PM PDT 24
Finished Jun 07 07:30:36 PM PDT 24
Peak memory 212416 kb
Host smart-69be4da4-be4f-4a72-b0b6-7771b33de250
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654506856 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ct
rl_volatile_unlock_smoke.654506856
Directory /workspace/18.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_alert_test.4211745890
Short name T187
Test name
Test status
Simulation time 19035754 ps
CPU time 1.19 seconds
Started Jun 07 07:30:39 PM PDT 24
Finished Jun 07 07:30:43 PM PDT 24
Peak memory 209488 kb
Host smart-8a82d5e0-68ed-4641-8ae3-13aa2b8458c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211745890 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_alert_test.4211745890
Directory /workspace/19.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.lc_ctrl_errors.2027705472
Short name T301
Test name
Test status
Simulation time 1338317303 ps
CPU time 18.08 seconds
Started Jun 07 07:30:38 PM PDT 24
Finished Jun 07 07:30:59 PM PDT 24
Peak memory 218720 kb
Host smart-c896e7dd-7f4e-4755-a4da-0dd10b8d72f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027705472 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_errors.2027705472
Directory /workspace/19.lc_ctrl_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_access.2507544748
Short name T742
Test name
Test status
Simulation time 464436082 ps
CPU time 3.42 seconds
Started Jun 07 07:30:36 PM PDT 24
Finished Jun 07 07:30:42 PM PDT 24
Peak memory 217500 kb
Host smart-dd5e1829-564e-4571-a343-c53651657c39
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507544748 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_access.2507544748
Directory /workspace/19.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_errors.681083739
Short name T340
Test name
Test status
Simulation time 1407706033 ps
CPU time 24.46 seconds
Started Jun 07 07:30:35 PM PDT 24
Finished Jun 07 07:31:02 PM PDT 24
Peak memory 226204 kb
Host smart-4fdce49d-5745-45ea-9ccc-d7c1285f8004
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681083739 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_er
rors.681083739
Directory /workspace/19.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_prog_failure.2565056685
Short name T304
Test name
Test status
Simulation time 147407491 ps
CPU time 5.04 seconds
Started Jun 07 07:30:36 PM PDT 24
Finished Jun 07 07:30:44 PM PDT 24
Peak memory 218700 kb
Host smart-7b9eec06-d06e-40e7-97b0-a3b24746a372
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565056685 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jta
g_prog_failure.2565056685
Directory /workspace/19.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_smoke.3044625846
Short name T455
Test name
Test status
Simulation time 195129545 ps
CPU time 1.68 seconds
Started Jun 07 07:30:38 PM PDT 24
Finished Jun 07 07:30:43 PM PDT 24
Peak memory 218160 kb
Host smart-169779aa-6241-47be-819b-3e16c5ce9683
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044625846 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_smoke
.3044625846
Directory /workspace/19.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_failure.3745828091
Short name T766
Test name
Test status
Simulation time 3356380417 ps
CPU time 65.62 seconds
Started Jun 07 07:30:38 PM PDT 24
Finished Jun 07 07:31:46 PM PDT 24
Peak memory 273832 kb
Host smart-904a2c2d-dd36-4778-b021-4bac8b04ea92
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745828091 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jt
ag_state_failure.3745828091
Directory /workspace/19.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_post_trans.925229817
Short name T429
Test name
Test status
Simulation time 656879382 ps
CPU time 24.73 seconds
Started Jun 07 07:30:38 PM PDT 24
Finished Jun 07 07:31:05 PM PDT 24
Peak memory 245164 kb
Host smart-6e983bcc-5903-4e2b-a85c-90742e905de1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925229817 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_
jtag_state_post_trans.925229817
Directory /workspace/19.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_prog_failure.4284303614
Short name T434
Test name
Test status
Simulation time 166813633 ps
CPU time 2.67 seconds
Started Jun 07 07:30:38 PM PDT 24
Finished Jun 07 07:30:43 PM PDT 24
Peak memory 218648 kb
Host smart-a1edd656-f7cc-4ee7-98d2-ea367827be5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284303614 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_prog_failure.4284303614
Directory /workspace/19.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_mubi.3967985361
Short name T288
Test name
Test status
Simulation time 883225175 ps
CPU time 14.18 seconds
Started Jun 07 07:30:38 PM PDT 24
Finished Jun 07 07:30:54 PM PDT 24
Peak memory 219404 kb
Host smart-53406478-1ccf-4a66-9f90-a1c5e1964a53
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967985361 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_mubi.3967985361
Directory /workspace/19.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_digest.1981679108
Short name T56
Test name
Test status
Simulation time 300910669 ps
CPU time 12.67 seconds
Started Jun 07 07:30:37 PM PDT 24
Finished Jun 07 07:30:52 PM PDT 24
Peak memory 218752 kb
Host smart-eae38057-193a-47a2-a13f-247f23edad85
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981679108 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_d
igest.1981679108
Directory /workspace/19.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_mux.2237824161
Short name T444
Test name
Test status
Simulation time 1176681507 ps
CPU time 7.75 seconds
Started Jun 07 07:30:37 PM PDT 24
Finished Jun 07 07:30:48 PM PDT 24
Peak memory 218712 kb
Host smart-075ed49a-e0a9-41bf-a482-6e0326a756d8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237824161 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_mux.
2237824161
Directory /workspace/19.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/19.lc_ctrl_security_escalation.3733002420
Short name T419
Test name
Test status
Simulation time 225096626 ps
CPU time 8.49 seconds
Started Jun 07 07:30:39 PM PDT 24
Finished Jun 07 07:30:50 PM PDT 24
Peak memory 226044 kb
Host smart-bd3a546c-2ba0-4782-821c-4f87e0414ca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733002420 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_security_escalation.3733002420
Directory /workspace/19.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/19.lc_ctrl_smoke.3212868018
Short name T739
Test name
Test status
Simulation time 72661376 ps
CPU time 2.75 seconds
Started Jun 07 07:30:37 PM PDT 24
Finished Jun 07 07:30:42 PM PDT 24
Peak memory 214960 kb
Host smart-7889b2bf-e912-46ea-9b25-99a982d8d6ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212868018 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_smoke.3212868018
Directory /workspace/19.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_failure.705546800
Short name T670
Test name
Test status
Simulation time 837084170 ps
CPU time 17.07 seconds
Started Jun 07 07:30:38 PM PDT 24
Finished Jun 07 07:30:58 PM PDT 24
Peak memory 251472 kb
Host smart-420c1973-fcb4-4279-8498-80776cb16160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705546800 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_failure.705546800
Directory /workspace/19.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_post_trans.3036766956
Short name T720
Test name
Test status
Simulation time 83032046 ps
CPU time 3.44 seconds
Started Jun 07 07:30:38 PM PDT 24
Finished Jun 07 07:30:44 PM PDT 24
Peak memory 222696 kb
Host smart-cc0dab0e-6a03-4700-838d-0bf1764790d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036766956 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_post_trans.3036766956
Directory /workspace/19.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all.4133505186
Short name T20
Test name
Test status
Simulation time 3267499367 ps
CPU time 26.17 seconds
Started Jun 07 07:30:40 PM PDT 24
Finished Jun 07 07:31:09 PM PDT 24
Peak memory 226648 kb
Host smart-7943ba0a-ee1a-4206-b2b9-0d2b0eb2cb2a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133505186 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.lc_ctrl_stress_all.4133505186
Directory /workspace/19.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.lc_ctrl_volatile_unlock_smoke.1981724837
Short name T660
Test name
Test status
Simulation time 15741947 ps
CPU time 0.93 seconds
Started Jun 07 07:30:38 PM PDT 24
Finished Jun 07 07:30:42 PM PDT 24
Peak memory 212312 kb
Host smart-f5c92cca-01e4-4c86-a82b-0a73b988065e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981724837 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_c
trl_volatile_unlock_smoke.1981724837
Directory /workspace/19.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_alert_test.739153211
Short name T822
Test name
Test status
Simulation time 31242230 ps
CPU time 1.05 seconds
Started Jun 07 07:29:21 PM PDT 24
Finished Jun 07 07:29:25 PM PDT 24
Peak memory 209504 kb
Host smart-d4e96624-9f75-4479-998b-091f03e062d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739153211 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_alert_test.739153211
Directory /workspace/2.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.lc_ctrl_claim_transition_if.1380112214
Short name T67
Test name
Test status
Simulation time 43755196 ps
CPU time 0.92 seconds
Started Jun 07 07:29:20 PM PDT 24
Finished Jun 07 07:29:23 PM PDT 24
Peak memory 209376 kb
Host smart-aa374596-2eeb-494b-b085-06fe7c601567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380112214 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_claim_transition_if.1380112214
Directory /workspace/2.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/2.lc_ctrl_errors.3347622535
Short name T241
Test name
Test status
Simulation time 1176652136 ps
CPU time 10.1 seconds
Started Jun 07 07:29:05 PM PDT 24
Finished Jun 07 07:29:20 PM PDT 24
Peak memory 218716 kb
Host smart-49ec5676-6e91-4d4a-b28c-b2a8d9bbf59c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347622535 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_errors.3347622535
Directory /workspace/2.lc_ctrl_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_access.1327045853
Short name T788
Test name
Test status
Simulation time 428640707 ps
CPU time 9.73 seconds
Started Jun 07 07:29:18 PM PDT 24
Finished Jun 07 07:29:30 PM PDT 24
Peak memory 217876 kb
Host smart-f925c54f-ba33-4e15-9274-db5ca1e5e986
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327045853 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_access.1327045853
Directory /workspace/2.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_errors.2358661624
Short name T366
Test name
Test status
Simulation time 2670225802 ps
CPU time 50.24 seconds
Started Jun 07 07:29:18 PM PDT 24
Finished Jun 07 07:30:10 PM PDT 24
Peak memory 219420 kb
Host smart-8048b40f-975b-455e-b797-34a9fb2ce5ca
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358661624 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_er
rors.2358661624
Directory /workspace/2.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_priority.1376987109
Short name T474
Test name
Test status
Simulation time 1068978718 ps
CPU time 6.14 seconds
Started Jun 07 07:29:21 PM PDT 24
Finished Jun 07 07:29:30 PM PDT 24
Peak memory 218272 kb
Host smart-2111d4bc-1685-4fa3-a5de-2930dd2f3d30
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376987109 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_priority.1
376987109
Directory /workspace/2.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_prog_failure.3956475604
Short name T445
Test name
Test status
Simulation time 350175137 ps
CPU time 7.1 seconds
Started Jun 07 07:29:18 PM PDT 24
Finished Jun 07 07:29:26 PM PDT 24
Peak memory 218760 kb
Host smart-df3b886c-08a2-45ec-a0ff-7e0fa0f475db
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956475604 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag
_prog_failure.3956475604
Directory /workspace/2.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_regwen_during_op.1612507531
Short name T468
Test name
Test status
Simulation time 1275628838 ps
CPU time 37.5 seconds
Started Jun 07 07:29:18 PM PDT 24
Finished Jun 07 07:29:58 PM PDT 24
Peak memory 218176 kb
Host smart-9f5a6870-ac55-4e26-ba03-27079b96fb57
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612507531 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_regwen_during_op.1612507531
Directory /workspace/2.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_smoke.216204864
Short name T70
Test name
Test status
Simulation time 539844172 ps
CPU time 3.65 seconds
Started Jun 07 07:29:20 PM PDT 24
Finished Jun 07 07:29:26 PM PDT 24
Peak memory 218184 kb
Host smart-9bb0312f-dcff-4340-b75b-f15fd1294472
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216204864 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_smoke.216204864
Directory /workspace/2.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_failure.1543596761
Short name T762
Test name
Test status
Simulation time 4281574585 ps
CPU time 45.81 seconds
Started Jun 07 07:29:19 PM PDT 24
Finished Jun 07 07:30:07 PM PDT 24
Peak memory 251588 kb
Host smart-32257035-401d-434f-90f7-79be391b1fef
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543596761 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jta
g_state_failure.1543596761
Directory /workspace/2.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_post_trans.419852252
Short name T748
Test name
Test status
Simulation time 3072617261 ps
CPU time 10.27 seconds
Started Jun 07 07:29:18 PM PDT 24
Finished Jun 07 07:29:29 PM PDT 24
Peak memory 218800 kb
Host smart-3ab4175c-e78f-4ac2-b4bc-66a07c78dbdf
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419852252 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_j
tag_state_post_trans.419852252
Directory /workspace/2.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_prog_failure.463775230
Short name T232
Test name
Test status
Simulation time 360985536 ps
CPU time 3.26 seconds
Started Jun 07 07:29:06 PM PDT 24
Finished Jun 07 07:29:14 PM PDT 24
Peak memory 223160 kb
Host smart-419305c3-8943-4a30-9621-ea49d9deb83f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463775230 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_prog_failure.463775230
Directory /workspace/2.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_regwen_during_op.2814749245
Short name T854
Test name
Test status
Simulation time 1077242544 ps
CPU time 11.59 seconds
Started Jun 07 07:29:08 PM PDT 24
Finished Jun 07 07:29:24 PM PDT 24
Peak memory 218156 kb
Host smart-8feecadc-44ed-4a83-8da6-1d283b59a78a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814749245 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_regwen_during_op.2814749245
Directory /workspace/2.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_cm.3772621519
Short name T52
Test name
Test status
Simulation time 141716433 ps
CPU time 23.75 seconds
Started Jun 07 07:29:20 PM PDT 24
Finished Jun 07 07:29:47 PM PDT 24
Peak memory 269436 kb
Host smart-ae60969d-d0c4-4425-9842-26ca22c49833
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772621519 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_cm.3772621519
Directory /workspace/2.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_mubi.716839359
Short name T671
Test name
Test status
Simulation time 377807092 ps
CPU time 8.12 seconds
Started Jun 07 07:29:19 PM PDT 24
Finished Jun 07 07:29:30 PM PDT 24
Peak memory 218700 kb
Host smart-a636539d-45b3-48f6-a5c8-c10e6db0e34e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716839359 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_mubi.716839359
Directory /workspace/2.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_digest.1634305232
Short name T603
Test name
Test status
Simulation time 356245446 ps
CPU time 14.78 seconds
Started Jun 07 07:29:19 PM PDT 24
Finished Jun 07 07:29:37 PM PDT 24
Peak memory 218776 kb
Host smart-a451db36-37ef-49a4-997d-a3886e4dc59e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634305232 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_di
gest.1634305232
Directory /workspace/2.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_mux.1843483119
Short name T849
Test name
Test status
Simulation time 796389006 ps
CPU time 9.18 seconds
Started Jun 07 07:29:19 PM PDT 24
Finished Jun 07 07:29:31 PM PDT 24
Peak memory 218700 kb
Host smart-8b58b938-00c6-446e-bfbb-efee2a469cfb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843483119 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_mux.1
843483119
Directory /workspace/2.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/2.lc_ctrl_security_escalation.878083464
Short name T759
Test name
Test status
Simulation time 341354145 ps
CPU time 13.28 seconds
Started Jun 07 07:29:04 PM PDT 24
Finished Jun 07 07:29:22 PM PDT 24
Peak memory 226452 kb
Host smart-1c594c21-4226-4947-9f69-bb1ab64339c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878083464 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_security_escalation.878083464
Directory /workspace/2.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/2.lc_ctrl_smoke.4083735762
Short name T176
Test name
Test status
Simulation time 184926290 ps
CPU time 2.53 seconds
Started Jun 07 07:29:12 PM PDT 24
Finished Jun 07 07:29:17 PM PDT 24
Peak memory 215236 kb
Host smart-9c8b1f58-c32f-40ad-aa0c-3ad11f38e6c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083735762 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_smoke.4083735762
Directory /workspace/2.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_failure.692996309
Short name T284
Test name
Test status
Simulation time 1257923329 ps
CPU time 34.53 seconds
Started Jun 07 07:29:07 PM PDT 24
Finished Jun 07 07:29:46 PM PDT 24
Peak memory 251452 kb
Host smart-9d9effc4-2a5c-48f7-8936-05dae0fcce6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692996309 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_failure.692996309
Directory /workspace/2.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_post_trans.3281138562
Short name T741
Test name
Test status
Simulation time 104639899 ps
CPU time 8.08 seconds
Started Jun 07 07:29:09 PM PDT 24
Finished Jun 07 07:29:22 PM PDT 24
Peak memory 247236 kb
Host smart-6a031a87-6e79-4cb7-a07e-370f29ab000d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281138562 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_post_trans.3281138562
Directory /workspace/2.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all.454898560
Short name T293
Test name
Test status
Simulation time 8626133922 ps
CPU time 66.25 seconds
Started Jun 07 07:29:19 PM PDT 24
Finished Jun 07 07:30:27 PM PDT 24
Peak memory 268564 kb
Host smart-4554dc33-df5c-48f6-89e0-64c4b5f417ec
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454898560 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.lc_ctrl_stress_all.454898560
Directory /workspace/2.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.lc_ctrl_volatile_unlock_smoke.2428023123
Short name T804
Test name
Test status
Simulation time 12028308 ps
CPU time 0.97 seconds
Started Jun 07 07:29:09 PM PDT 24
Finished Jun 07 07:29:14 PM PDT 24
Peak memory 209412 kb
Host smart-4de88cfc-6b05-4e3a-8343-1b5e3f10defb
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428023123 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ct
rl_volatile_unlock_smoke.2428023123
Directory /workspace/2.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_alert_test.630654845
Short name T619
Test name
Test status
Simulation time 31639354 ps
CPU time 1.08 seconds
Started Jun 07 07:30:43 PM PDT 24
Finished Jun 07 07:30:47 PM PDT 24
Peak memory 209456 kb
Host smart-ac8fa8fa-4632-46f9-934d-528db5369010
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630654845 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_alert_test.630654845
Directory /workspace/20.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.lc_ctrl_errors.186485551
Short name T365
Test name
Test status
Simulation time 388162703 ps
CPU time 11.42 seconds
Started Jun 07 07:30:44 PM PDT 24
Finished Jun 07 07:30:58 PM PDT 24
Peak memory 218756 kb
Host smart-f5626dc1-7067-4ef0-babc-91f05535b409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186485551 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_errors.186485551
Directory /workspace/20.lc_ctrl_errors/latest

Test location /workspace/coverage/default/20.lc_ctrl_jtag_access.3395588694
Short name T594
Test name
Test status
Simulation time 494596294 ps
CPU time 3.87 seconds
Started Jun 07 07:30:44 PM PDT 24
Finished Jun 07 07:30:50 PM PDT 24
Peak memory 217780 kb
Host smart-9f780515-8300-454d-a68f-dcb0c05974a5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395588694 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_jtag_access.3395588694
Directory /workspace/20.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/20.lc_ctrl_prog_failure.1968561235
Short name T820
Test name
Test status
Simulation time 214807992 ps
CPU time 2.77 seconds
Started Jun 07 07:30:38 PM PDT 24
Finished Jun 07 07:30:43 PM PDT 24
Peak memory 218732 kb
Host smart-7eec2e49-8039-4091-a08d-6702cca53388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968561235 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_prog_failure.1968561235
Directory /workspace/20.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_mubi.4050217264
Short name T691
Test name
Test status
Simulation time 266298200 ps
CPU time 12.73 seconds
Started Jun 07 07:30:43 PM PDT 24
Finished Jun 07 07:30:58 PM PDT 24
Peak memory 226532 kb
Host smart-9e1990f5-bc3c-4f75-ab56-6ffa7cf62687
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050217264 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_mubi.4050217264
Directory /workspace/20.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_digest.3825325581
Short name T576
Test name
Test status
Simulation time 532624542 ps
CPU time 12.6 seconds
Started Jun 07 07:30:44 PM PDT 24
Finished Jun 07 07:30:59 PM PDT 24
Peak memory 218692 kb
Host smart-885be1f5-5c75-41b6-899c-2d23ae6048a7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825325581 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_d
igest.3825325581
Directory /workspace/20.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_mux.2814973263
Short name T297
Test name
Test status
Simulation time 1061104396 ps
CPU time 6.5 seconds
Started Jun 07 07:30:54 PM PDT 24
Finished Jun 07 07:31:03 PM PDT 24
Peak memory 225592 kb
Host smart-22946440-a2c4-47b4-b825-9438d1cdac43
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814973263 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_mux.
2814973263
Directory /workspace/20.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/20.lc_ctrl_security_escalation.2761551184
Short name T817
Test name
Test status
Simulation time 282137011 ps
CPU time 9.63 seconds
Started Jun 07 07:30:48 PM PDT 24
Finished Jun 07 07:31:01 PM PDT 24
Peak memory 226520 kb
Host smart-bb357cea-6512-4b08-b565-6000b9362baf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761551184 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_security_escalation.2761551184
Directory /workspace/20.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/20.lc_ctrl_smoke.833069170
Short name T461
Test name
Test status
Simulation time 115262726 ps
CPU time 3.85 seconds
Started Jun 07 07:30:38 PM PDT 24
Finished Jun 07 07:30:44 PM PDT 24
Peak memory 218196 kb
Host smart-7e0259e9-8e40-4f90-8b95-b0b3ecb3aa9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833069170 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_smoke.833069170
Directory /workspace/20.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_failure.3792025421
Short name T299
Test name
Test status
Simulation time 858711402 ps
CPU time 21.63 seconds
Started Jun 07 07:30:37 PM PDT 24
Finished Jun 07 07:31:02 PM PDT 24
Peak memory 251396 kb
Host smart-a4889c44-654d-4992-ae8d-fc042239964f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792025421 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_failure.3792025421
Directory /workspace/20.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_post_trans.1484015328
Short name T827
Test name
Test status
Simulation time 49980599 ps
CPU time 2.51 seconds
Started Jun 07 07:30:39 PM PDT 24
Finished Jun 07 07:30:44 PM PDT 24
Peak memory 226884 kb
Host smart-4f300e5d-f580-485a-a94a-fc23117ef2df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484015328 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_post_trans.1484015328
Directory /workspace/20.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/20.lc_ctrl_stress_all.1937804609
Short name T486
Test name
Test status
Simulation time 598791033 ps
CPU time 16.3 seconds
Started Jun 07 07:30:44 PM PDT 24
Finished Jun 07 07:31:02 PM PDT 24
Peak memory 250856 kb
Host smart-7084a83a-5ae8-40ec-b166-5e49c9b58216
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937804609 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.lc_ctrl_stress_all.1937804609
Directory /workspace/20.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.lc_ctrl_volatile_unlock_smoke.2844738451
Short name T499
Test name
Test status
Simulation time 97361422 ps
CPU time 0.79 seconds
Started Jun 07 07:30:38 PM PDT 24
Finished Jun 07 07:30:42 PM PDT 24
Peak memory 209316 kb
Host smart-674f5814-84c1-44c5-bb42-e959869b3ba7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844738451 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_c
trl_volatile_unlock_smoke.2844738451
Directory /workspace/20.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_alert_test.884376436
Short name T384
Test name
Test status
Simulation time 46153188 ps
CPU time 1.03 seconds
Started Jun 07 07:30:47 PM PDT 24
Finished Jun 07 07:30:51 PM PDT 24
Peak memory 209392 kb
Host smart-d6774da4-a9c0-427b-a856-aaf3761ef4c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884376436 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_alert_test.884376436
Directory /workspace/21.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.lc_ctrl_errors.3913421339
Short name T167
Test name
Test status
Simulation time 1653930704 ps
CPU time 14.75 seconds
Started Jun 07 07:30:50 PM PDT 24
Finished Jun 07 07:31:07 PM PDT 24
Peak memory 218648 kb
Host smart-2bce6064-0bfc-4622-b225-e4883326d938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913421339 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_errors.3913421339
Directory /workspace/21.lc_ctrl_errors/latest

Test location /workspace/coverage/default/21.lc_ctrl_jtag_access.4280407956
Short name T659
Test name
Test status
Simulation time 212745196 ps
CPU time 1.28 seconds
Started Jun 07 07:30:44 PM PDT 24
Finished Jun 07 07:30:47 PM PDT 24
Peak memory 217512 kb
Host smart-0957e3d8-5328-4c6c-8e49-f9d84bc3d777
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280407956 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_jtag_access.4280407956
Directory /workspace/21.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/21.lc_ctrl_prog_failure.1291588745
Short name T738
Test name
Test status
Simulation time 88120508 ps
CPU time 2.81 seconds
Started Jun 07 07:30:49 PM PDT 24
Finished Jun 07 07:30:55 PM PDT 24
Peak memory 218692 kb
Host smart-d149be3a-2198-4ee8-9ddc-94d7780b79e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291588745 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_prog_failure.1291588745
Directory /workspace/21.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_mubi.2698903123
Short name T826
Test name
Test status
Simulation time 453378860 ps
CPU time 12.36 seconds
Started Jun 07 07:30:47 PM PDT 24
Finished Jun 07 07:31:03 PM PDT 24
Peak memory 218788 kb
Host smart-48bbf96d-bad6-4d9c-aa4e-d6e0ed1c32fd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698903123 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_mubi.2698903123
Directory /workspace/21.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_digest.485025350
Short name T747
Test name
Test status
Simulation time 273164653 ps
CPU time 13.06 seconds
Started Jun 07 07:30:54 PM PDT 24
Finished Jun 07 07:31:10 PM PDT 24
Peak memory 218688 kb
Host smart-53276189-bd83-43b3-a0a7-f138b7b8c3de
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485025350 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_di
gest.485025350
Directory /workspace/21.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_mux.65116325
Short name T834
Test name
Test status
Simulation time 232467009 ps
CPU time 7.47 seconds
Started Jun 07 07:30:45 PM PDT 24
Finished Jun 07 07:30:55 PM PDT 24
Peak memory 225624 kb
Host smart-0751ee5e-ca7a-44a2-994e-675634c8307e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65116325 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_mux.65116325
Directory /workspace/21.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/21.lc_ctrl_security_escalation.1598858672
Short name T866
Test name
Test status
Simulation time 535938562 ps
CPU time 11.7 seconds
Started Jun 07 07:30:44 PM PDT 24
Finished Jun 07 07:30:58 PM PDT 24
Peak memory 226528 kb
Host smart-77d78e1f-8226-4b56-ad36-ceef9381ff5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598858672 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_security_escalation.1598858672
Directory /workspace/21.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/21.lc_ctrl_smoke.808404559
Short name T497
Test name
Test status
Simulation time 234682251 ps
CPU time 3.78 seconds
Started Jun 07 07:30:46 PM PDT 24
Finished Jun 07 07:30:53 PM PDT 24
Peak memory 218204 kb
Host smart-bf674cac-9c0c-412f-a9d3-48cbaae1206b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808404559 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_smoke.808404559
Directory /workspace/21.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_failure.3092179539
Short name T495
Test name
Test status
Simulation time 308513444 ps
CPU time 31.24 seconds
Started Jun 07 07:30:43 PM PDT 24
Finished Jun 07 07:31:17 PM PDT 24
Peak memory 251456 kb
Host smart-c8177071-4891-4876-8bdd-272100bded02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092179539 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_failure.3092179539
Directory /workspace/21.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_post_trans.754047888
Short name T310
Test name
Test status
Simulation time 53811443 ps
CPU time 8.21 seconds
Started Jun 07 07:30:45 PM PDT 24
Finished Jun 07 07:30:55 PM PDT 24
Peak memory 251432 kb
Host smart-71e36d14-708c-40f9-b74d-1da9716635da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754047888 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_post_trans.754047888
Directory /workspace/21.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/21.lc_ctrl_stress_all.2033694852
Short name T289
Test name
Test status
Simulation time 44221983112 ps
CPU time 208.27 seconds
Started Jun 07 07:30:44 PM PDT 24
Finished Jun 07 07:34:15 PM PDT 24
Peak memory 268904 kb
Host smart-35d741ce-f765-4642-ba02-454b5da92b6a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033694852 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.lc_ctrl_stress_all.2033694852
Directory /workspace/21.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.lc_ctrl_volatile_unlock_smoke.928813660
Short name T189
Test name
Test status
Simulation time 13366028 ps
CPU time 0.83 seconds
Started Jun 07 07:31:02 PM PDT 24
Finished Jun 07 07:31:07 PM PDT 24
Peak memory 209332 kb
Host smart-d4edef28-b599-4c54-bff3-da9391e83c79
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928813660 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ct
rl_volatile_unlock_smoke.928813660
Directory /workspace/21.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_alert_test.906178583
Short name T514
Test name
Test status
Simulation time 65590557 ps
CPU time 0.92 seconds
Started Jun 07 07:30:55 PM PDT 24
Finished Jun 07 07:30:58 PM PDT 24
Peak memory 209508 kb
Host smart-cc4211a7-896f-400b-aec5-60f03ef7ddaa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906178583 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_alert_test.906178583
Directory /workspace/22.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.lc_ctrl_errors.3488249690
Short name T224
Test name
Test status
Simulation time 1058988672 ps
CPU time 12.13 seconds
Started Jun 07 07:30:46 PM PDT 24
Finished Jun 07 07:31:02 PM PDT 24
Peak memory 218716 kb
Host smart-cea25323-8e2c-4fe7-8206-c1fa9e08d505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488249690 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_errors.3488249690
Directory /workspace/22.lc_ctrl_errors/latest

Test location /workspace/coverage/default/22.lc_ctrl_jtag_access.514093175
Short name T593
Test name
Test status
Simulation time 1249041407 ps
CPU time 8.17 seconds
Started Jun 07 07:30:45 PM PDT 24
Finished Jun 07 07:30:56 PM PDT 24
Peak memory 218096 kb
Host smart-2cf45485-a87b-4f9c-9689-5d07ef07aac5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514093175 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_jtag_access.514093175
Directory /workspace/22.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/22.lc_ctrl_prog_failure.2049715598
Short name T869
Test name
Test status
Simulation time 40360057 ps
CPU time 2.69 seconds
Started Jun 07 07:30:47 PM PDT 24
Finished Jun 07 07:30:52 PM PDT 24
Peak memory 222776 kb
Host smart-fa0c3e12-221c-4fc6-9418-f1ffb14587cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049715598 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_prog_failure.2049715598
Directory /workspace/22.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_mubi.1190729444
Short name T564
Test name
Test status
Simulation time 392487512 ps
CPU time 8.21 seconds
Started Jun 07 07:30:47 PM PDT 24
Finished Jun 07 07:30:59 PM PDT 24
Peak memory 219364 kb
Host smart-3b3a79b3-ddaa-4e35-98c7-e208cdaeef61
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190729444 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_mubi.1190729444
Directory /workspace/22.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_digest.4074817559
Short name T228
Test name
Test status
Simulation time 2124214495 ps
CPU time 12.83 seconds
Started Jun 07 07:30:53 PM PDT 24
Finished Jun 07 07:31:09 PM PDT 24
Peak memory 218684 kb
Host smart-4afc47a8-fa7b-4102-8ac1-36a4cad8d0b7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074817559 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_d
igest.4074817559
Directory /workspace/22.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_mux.357560211
Short name T374
Test name
Test status
Simulation time 1131985742 ps
CPU time 6.13 seconds
Started Jun 07 07:30:56 PM PDT 24
Finished Jun 07 07:31:04 PM PDT 24
Peak memory 218748 kb
Host smart-14439032-933b-48f4-8fd0-6241627b46a8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357560211 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_mux.357560211
Directory /workspace/22.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/22.lc_ctrl_security_escalation.790699437
Short name T490
Test name
Test status
Simulation time 357355764 ps
CPU time 9.02 seconds
Started Jun 07 07:30:47 PM PDT 24
Finished Jun 07 07:30:59 PM PDT 24
Peak memory 218748 kb
Host smart-6e558e98-1fc7-457d-ad31-9d9a1aa9ca67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790699437 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_security_escalation.790699437
Directory /workspace/22.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/22.lc_ctrl_smoke.1004893129
Short name T248
Test name
Test status
Simulation time 20913198 ps
CPU time 1.41 seconds
Started Jun 07 07:30:48 PM PDT 24
Finished Jun 07 07:30:53 PM PDT 24
Peak memory 218192 kb
Host smart-7875bbdc-d504-42ff-9752-33e143f90e69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004893129 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_smoke.1004893129
Directory /workspace/22.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_failure.3808326477
Short name T267
Test name
Test status
Simulation time 895722059 ps
CPU time 23.33 seconds
Started Jun 07 07:30:44 PM PDT 24
Finished Jun 07 07:31:10 PM PDT 24
Peak memory 251420 kb
Host smart-38a6831f-f71e-4bc5-9547-9a611e949c1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808326477 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_failure.3808326477
Directory /workspace/22.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_post_trans.3600363950
Short name T355
Test name
Test status
Simulation time 188446462 ps
CPU time 10.55 seconds
Started Jun 07 07:30:51 PM PDT 24
Finished Jun 07 07:31:04 PM PDT 24
Peak memory 251468 kb
Host smart-6c2f0eab-73db-45aa-8cb6-6563789aaca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600363950 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_post_trans.3600363950
Directory /workspace/22.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/22.lc_ctrl_stress_all.2955946365
Short name T250
Test name
Test status
Simulation time 1243714694 ps
CPU time 40.49 seconds
Started Jun 07 07:30:57 PM PDT 24
Finished Jun 07 07:31:40 PM PDT 24
Peak memory 251476 kb
Host smart-4467810f-6fc2-4603-ae8d-a793e285d65f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955946365 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.lc_ctrl_stress_all.2955946365
Directory /workspace/22.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.lc_ctrl_volatile_unlock_smoke.3423547169
Short name T638
Test name
Test status
Simulation time 33758300 ps
CPU time 0.86 seconds
Started Jun 07 07:30:50 PM PDT 24
Finished Jun 07 07:30:53 PM PDT 24
Peak memory 209596 kb
Host smart-92a6c623-45ee-4533-8c40-1527717b61df
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423547169 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_c
trl_volatile_unlock_smoke.3423547169
Directory /workspace/22.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_alert_test.3662428822
Short name T713
Test name
Test status
Simulation time 43589686 ps
CPU time 0.87 seconds
Started Jun 07 07:31:00 PM PDT 24
Finished Jun 07 07:31:04 PM PDT 24
Peak memory 209172 kb
Host smart-b1598bd9-117b-42cb-a70b-8172b4fb1ce2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662428822 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_alert_test.3662428822
Directory /workspace/23.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.lc_ctrl_errors.1517729973
Short name T793
Test name
Test status
Simulation time 661467062 ps
CPU time 6.79 seconds
Started Jun 07 07:31:02 PM PDT 24
Finished Jun 07 07:31:13 PM PDT 24
Peak memory 218748 kb
Host smart-6cbbff2e-4dd0-4f9c-9fcb-0b4b640ead37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517729973 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_errors.1517729973
Directory /workspace/23.lc_ctrl_errors/latest

Test location /workspace/coverage/default/23.lc_ctrl_jtag_access.147556691
Short name T689
Test name
Test status
Simulation time 1419819278 ps
CPU time 7.88 seconds
Started Jun 07 07:30:55 PM PDT 24
Finished Jun 07 07:31:05 PM PDT 24
Peak memory 217736 kb
Host smart-0722ee3e-9c73-4fff-a66a-48279e52080f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147556691 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_jtag_access.147556691
Directory /workspace/23.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/23.lc_ctrl_prog_failure.2574303716
Short name T10
Test name
Test status
Simulation time 191738290 ps
CPU time 3.28 seconds
Started Jun 07 07:30:53 PM PDT 24
Finished Jun 07 07:30:59 PM PDT 24
Peak memory 218684 kb
Host smart-00a528d1-a186-4ba3-b42d-abc0ad001d38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574303716 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_prog_failure.2574303716
Directory /workspace/23.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_mubi.3453833314
Short name T723
Test name
Test status
Simulation time 1823978167 ps
CPU time 12.91 seconds
Started Jun 07 07:30:57 PM PDT 24
Finished Jun 07 07:31:12 PM PDT 24
Peak memory 219488 kb
Host smart-69bec4e4-a962-4dc0-9785-d5ae540cef09
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453833314 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_mubi.3453833314
Directory /workspace/23.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_digest.757684079
Short name T481
Test name
Test status
Simulation time 163612965 ps
CPU time 8.26 seconds
Started Jun 07 07:30:56 PM PDT 24
Finished Jun 07 07:31:06 PM PDT 24
Peak memory 218756 kb
Host smart-59e4c7a9-afda-4aaf-8d6a-c67a55c9db4b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757684079 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_di
gest.757684079
Directory /workspace/23.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_mux.1629030831
Short name T363
Test name
Test status
Simulation time 862769510 ps
CPU time 16.9 seconds
Started Jun 07 07:30:58 PM PDT 24
Finished Jun 07 07:31:17 PM PDT 24
Peak memory 218712 kb
Host smart-b33c829b-f531-4b05-9d2a-cfe8236677a2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629030831 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_mux.
1629030831
Directory /workspace/23.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/23.lc_ctrl_security_escalation.2518356150
Short name T407
Test name
Test status
Simulation time 403041650 ps
CPU time 8.57 seconds
Started Jun 07 07:30:57 PM PDT 24
Finished Jun 07 07:31:08 PM PDT 24
Peak memory 226536 kb
Host smart-2deeefcb-deac-4c6e-812f-4f42b1ab6e0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2518356150 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_security_escalation.2518356150
Directory /workspace/23.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/23.lc_ctrl_smoke.650288485
Short name T599
Test name
Test status
Simulation time 151702620 ps
CPU time 2.58 seconds
Started Jun 07 07:30:59 PM PDT 24
Finished Jun 07 07:31:04 PM PDT 24
Peak memory 214908 kb
Host smart-7ad48820-8470-4ff8-8b72-1ad36bff0b61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650288485 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_smoke.650288485
Directory /workspace/23.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_failure.3284170938
Short name T765
Test name
Test status
Simulation time 1120121577 ps
CPU time 31.08 seconds
Started Jun 07 07:30:57 PM PDT 24
Finished Jun 07 07:31:31 PM PDT 24
Peak memory 251404 kb
Host smart-c2665b10-343e-45b4-a335-17dc4b3371cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284170938 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_failure.3284170938
Directory /workspace/23.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_post_trans.2428020670
Short name T629
Test name
Test status
Simulation time 270839728 ps
CPU time 9.66 seconds
Started Jun 07 07:31:00 PM PDT 24
Finished Jun 07 07:31:14 PM PDT 24
Peak memory 251380 kb
Host smart-a1481bf1-82a4-4e2d-84d0-3852aa311ded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428020670 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_post_trans.2428020670
Directory /workspace/23.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all.1511497979
Short name T588
Test name
Test status
Simulation time 9079981006 ps
CPU time 51.26 seconds
Started Jun 07 07:30:56 PM PDT 24
Finished Jun 07 07:31:50 PM PDT 24
Peak memory 251352 kb
Host smart-a7573111-e039-4e7a-a989-9469bca38377
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511497979 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.lc_ctrl_stress_all.1511497979
Directory /workspace/23.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.lc_ctrl_volatile_unlock_smoke.3361313821
Short name T813
Test name
Test status
Simulation time 42213121 ps
CPU time 0.91 seconds
Started Jun 07 07:30:57 PM PDT 24
Finished Jun 07 07:31:00 PM PDT 24
Peak memory 212412 kb
Host smart-a5a3b07d-9ad7-4938-bdbe-d34237347bfb
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361313821 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_c
trl_volatile_unlock_smoke.3361313821
Directory /workspace/23.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_alert_test.205579223
Short name T475
Test name
Test status
Simulation time 60920672 ps
CPU time 1 seconds
Started Jun 07 07:31:03 PM PDT 24
Finished Jun 07 07:31:08 PM PDT 24
Peak memory 209348 kb
Host smart-1b0f94c1-9b61-4436-bf24-b656780ab5a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205579223 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_alert_test.205579223
Directory /workspace/24.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.lc_ctrl_errors.1227213547
Short name T223
Test name
Test status
Simulation time 705927417 ps
CPU time 10.13 seconds
Started Jun 07 07:30:57 PM PDT 24
Finished Jun 07 07:31:10 PM PDT 24
Peak memory 218584 kb
Host smart-9406bf79-5a56-4586-986c-76df25e8d79f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227213547 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_errors.1227213547
Directory /workspace/24.lc_ctrl_errors/latest

Test location /workspace/coverage/default/24.lc_ctrl_jtag_access.4244917486
Short name T28
Test name
Test status
Simulation time 632154384 ps
CPU time 10.28 seconds
Started Jun 07 07:31:03 PM PDT 24
Finished Jun 07 07:31:18 PM PDT 24
Peak memory 217664 kb
Host smart-6e8b0c9f-a322-4be7-be6a-c9f44a079c41
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244917486 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_jtag_access.4244917486
Directory /workspace/24.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/24.lc_ctrl_prog_failure.1001936878
Short name T859
Test name
Test status
Simulation time 276811723 ps
CPU time 5.28 seconds
Started Jun 07 07:30:54 PM PDT 24
Finished Jun 07 07:31:02 PM PDT 24
Peak memory 218680 kb
Host smart-6cfaab0d-131f-4cf6-9b82-bb6a05c0f085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001936878 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_prog_failure.1001936878
Directory /workspace/24.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_mubi.716236017
Short name T472
Test name
Test status
Simulation time 1845356528 ps
CPU time 19.3 seconds
Started Jun 07 07:31:01 PM PDT 24
Finished Jun 07 07:31:25 PM PDT 24
Peak memory 219392 kb
Host smart-3bae648b-bae4-434b-9eb3-ec7e8e0b802c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716236017 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_mubi.716236017
Directory /workspace/24.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_digest.3262658305
Short name T225
Test name
Test status
Simulation time 249334792 ps
CPU time 9.93 seconds
Started Jun 07 07:31:02 PM PDT 24
Finished Jun 07 07:31:17 PM PDT 24
Peak memory 218656 kb
Host smart-d0c49d83-fa98-497d-86c8-7d1dd546ac31
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262658305 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_d
igest.3262658305
Directory /workspace/24.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_mux.3623487347
Short name T750
Test name
Test status
Simulation time 1183708496 ps
CPU time 13.89 seconds
Started Jun 07 07:31:04 PM PDT 24
Finished Jun 07 07:31:22 PM PDT 24
Peak memory 218732 kb
Host smart-74f77264-2689-4211-b631-8d3cbbd0d88c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623487347 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_mux.
3623487347
Directory /workspace/24.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/24.lc_ctrl_security_escalation.4201607599
Short name T420
Test name
Test status
Simulation time 381441360 ps
CPU time 14.02 seconds
Started Jun 07 07:30:54 PM PDT 24
Finished Jun 07 07:31:11 PM PDT 24
Peak memory 218828 kb
Host smart-af2a3f33-a601-4846-9a70-7dd2eeac4433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201607599 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_security_escalation.4201607599
Directory /workspace/24.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/24.lc_ctrl_smoke.3438365848
Short name T63
Test name
Test status
Simulation time 57844396 ps
CPU time 1.6 seconds
Started Jun 07 07:30:55 PM PDT 24
Finished Jun 07 07:30:59 PM PDT 24
Peak memory 214300 kb
Host smart-507c09b0-b04a-4fe1-ad19-b50aa1fe3681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438365848 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_smoke.3438365848
Directory /workspace/24.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_failure.2175040011
Short name T255
Test name
Test status
Simulation time 248694901 ps
CPU time 22.96 seconds
Started Jun 07 07:30:59 PM PDT 24
Finished Jun 07 07:31:24 PM PDT 24
Peak memory 251392 kb
Host smart-de46e202-b4bc-4926-8511-567a0431ace7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175040011 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_failure.2175040011
Directory /workspace/24.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_post_trans.1335222497
Short name T507
Test name
Test status
Simulation time 103602759 ps
CPU time 7.24 seconds
Started Jun 07 07:30:58 PM PDT 24
Finished Jun 07 07:31:08 PM PDT 24
Peak memory 250640 kb
Host smart-fa0cfda5-f65e-442a-aaa5-355b9c93e2d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335222497 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_post_trans.1335222497
Directory /workspace/24.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all.2340389083
Short name T498
Test name
Test status
Simulation time 10319591793 ps
CPU time 61.57 seconds
Started Jun 07 07:31:09 PM PDT 24
Finished Jun 07 07:32:14 PM PDT 24
Peak memory 249056 kb
Host smart-99f687ef-2165-4541-8078-b45848fa68c4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340389083 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.lc_ctrl_stress_all.2340389083
Directory /workspace/24.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all_with_rand_reset.3753025507
Short name T57
Test name
Test status
Simulation time 31502137688 ps
CPU time 416.82 seconds
Started Jun 07 07:31:03 PM PDT 24
Finished Jun 07 07:38:04 PM PDT 24
Peak memory 422640 kb
Host smart-c1b64acd-e84e-4cf5-be89-e7d94c43b0fd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3753025507 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_stress_all_with_rand_reset.3753025507
Directory /workspace/24.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.lc_ctrl_volatile_unlock_smoke.4015157880
Short name T471
Test name
Test status
Simulation time 58463935 ps
CPU time 1.03 seconds
Started Jun 07 07:30:56 PM PDT 24
Finished Jun 07 07:31:00 PM PDT 24
Peak memory 218288 kb
Host smart-0824e73d-3b22-4be2-a455-a6b6afe8572a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015157880 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_c
trl_volatile_unlock_smoke.4015157880
Directory /workspace/24.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_alert_test.3802932856
Short name T238
Test name
Test status
Simulation time 15755366 ps
CPU time 0.9 seconds
Started Jun 07 07:31:03 PM PDT 24
Finished Jun 07 07:31:08 PM PDT 24
Peak memory 209328 kb
Host smart-be917517-783b-4548-b835-91ad7acd0def
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802932856 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_alert_test.3802932856
Directory /workspace/25.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.lc_ctrl_errors.3320235493
Short name T320
Test name
Test status
Simulation time 475649683 ps
CPU time 9.91 seconds
Started Jun 07 07:31:04 PM PDT 24
Finished Jun 07 07:31:18 PM PDT 24
Peak memory 218684 kb
Host smart-1e33ba78-7988-4c93-8e85-f54ce184bc6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320235493 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_errors.3320235493
Directory /workspace/25.lc_ctrl_errors/latest

Test location /workspace/coverage/default/25.lc_ctrl_jtag_access.176601130
Short name T541
Test name
Test status
Simulation time 90004757 ps
CPU time 1.83 seconds
Started Jun 07 07:31:06 PM PDT 24
Finished Jun 07 07:31:12 PM PDT 24
Peak memory 217544 kb
Host smart-10ad8061-5868-4f8d-9ec4-ef1c993c220f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176601130 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_jtag_access.176601130
Directory /workspace/25.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/25.lc_ctrl_prog_failure.2280129688
Short name T543
Test name
Test status
Simulation time 70089481 ps
CPU time 2.85 seconds
Started Jun 07 07:31:08 PM PDT 24
Finished Jun 07 07:31:15 PM PDT 24
Peak memory 222872 kb
Host smart-d4b939ac-6d02-46f4-b0a3-7aee0aaf2165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280129688 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_prog_failure.2280129688
Directory /workspace/25.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_mubi.2803421247
Short name T369
Test name
Test status
Simulation time 987700096 ps
CPU time 11.3 seconds
Started Jun 07 07:31:11 PM PDT 24
Finished Jun 07 07:31:26 PM PDT 24
Peak memory 218804 kb
Host smart-b5cbf535-545a-4ac8-bc6d-884d99c5ad08
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803421247 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_mubi.2803421247
Directory /workspace/25.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_digest.1554474949
Short name T775
Test name
Test status
Simulation time 389709619 ps
CPU time 10.05 seconds
Started Jun 07 07:31:02 PM PDT 24
Finished Jun 07 07:31:17 PM PDT 24
Peak memory 218660 kb
Host smart-8960c530-beca-48f0-9dd3-f057aee16307
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554474949 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_d
igest.1554474949
Directory /workspace/25.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_mux.3267522128
Short name T745
Test name
Test status
Simulation time 736256045 ps
CPU time 13.36 seconds
Started Jun 07 07:31:04 PM PDT 24
Finished Jun 07 07:31:21 PM PDT 24
Peak memory 218640 kb
Host smart-bfb0e932-7cb6-4732-92e0-898f0bb27a9e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267522128 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_mux.
3267522128
Directory /workspace/25.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/25.lc_ctrl_security_escalation.4148415180
Short name T430
Test name
Test status
Simulation time 296249907 ps
CPU time 7.34 seconds
Started Jun 07 07:31:05 PM PDT 24
Finished Jun 07 07:31:16 PM PDT 24
Peak memory 226508 kb
Host smart-d25cb031-b12a-4784-9318-5e00a96ed83a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148415180 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_security_escalation.4148415180
Directory /workspace/25.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/25.lc_ctrl_smoke.12837830
Short name T809
Test name
Test status
Simulation time 211060511 ps
CPU time 1.48 seconds
Started Jun 07 07:30:59 PM PDT 24
Finished Jun 07 07:31:03 PM PDT 24
Peak memory 214220 kb
Host smart-2abe6486-8388-4b62-9448-598d813fa06b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12837830 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_smoke.12837830
Directory /workspace/25.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_failure.1692108518
Short name T767
Test name
Test status
Simulation time 821062817 ps
CPU time 20.74 seconds
Started Jun 07 07:31:06 PM PDT 24
Finished Jun 07 07:31:31 PM PDT 24
Peak memory 251540 kb
Host smart-2a9c5b38-9739-4a4f-878b-c4391d3f4abe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692108518 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_failure.1692108518
Directory /workspace/25.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_post_trans.3667579195
Short name T709
Test name
Test status
Simulation time 296012935 ps
CPU time 7.59 seconds
Started Jun 07 07:31:03 PM PDT 24
Finished Jun 07 07:31:15 PM PDT 24
Peak memory 251380 kb
Host smart-55c30002-9f9f-4f4e-a7ae-257414b2c06a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667579195 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_post_trans.3667579195
Directory /workspace/25.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/25.lc_ctrl_stress_all.136552058
Short name T18
Test name
Test status
Simulation time 10934950560 ps
CPU time 167.39 seconds
Started Jun 07 07:31:02 PM PDT 24
Finished Jun 07 07:33:54 PM PDT 24
Peak memory 226560 kb
Host smart-a6e1c7ee-a424-4f89-a022-52c2a31e19b1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136552058 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.lc_ctrl_stress_all.136552058
Directory /workspace/25.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.lc_ctrl_stress_all_with_rand_reset.817740793
Short name T150
Test name
Test status
Simulation time 311753677391 ps
CPU time 368.6 seconds
Started Jun 07 07:31:05 PM PDT 24
Finished Jun 07 07:37:17 PM PDT 24
Peak memory 251564 kb
Host smart-a9911583-7fe7-43dd-a8ae-72ff405cfa48
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=817740793 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_stress_all_with_rand_reset.817740793
Directory /workspace/25.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.lc_ctrl_volatile_unlock_smoke.1752267706
Short name T790
Test name
Test status
Simulation time 20879581 ps
CPU time 0.88 seconds
Started Jun 07 07:31:08 PM PDT 24
Finished Jun 07 07:31:12 PM PDT 24
Peak memory 212364 kb
Host smart-4c214ef1-3a49-42a7-8637-1388e9a7acc3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752267706 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_c
trl_volatile_unlock_smoke.1752267706
Directory /workspace/25.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_alert_test.2423328708
Short name T246
Test name
Test status
Simulation time 63577865 ps
CPU time 0.91 seconds
Started Jun 07 07:31:05 PM PDT 24
Finished Jun 07 07:31:10 PM PDT 24
Peak memory 209444 kb
Host smart-1e364946-8c61-473d-af65-23d156b4be10
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423328708 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_alert_test.2423328708
Directory /workspace/26.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.lc_ctrl_errors.855957495
Short name T422
Test name
Test status
Simulation time 1792529234 ps
CPU time 14.96 seconds
Started Jun 07 07:31:08 PM PDT 24
Finished Jun 07 07:31:27 PM PDT 24
Peak memory 218780 kb
Host smart-bd5b8315-a83c-41f6-85e7-094f29e5b280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855957495 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_errors.855957495
Directory /workspace/26.lc_ctrl_errors/latest

Test location /workspace/coverage/default/26.lc_ctrl_jtag_access.2433064984
Short name T102
Test name
Test status
Simulation time 64242868 ps
CPU time 1.58 seconds
Started Jun 07 07:31:03 PM PDT 24
Finished Jun 07 07:31:09 PM PDT 24
Peak memory 217596 kb
Host smart-6b63cbb1-9dc3-4f2a-8f34-c820d8bdc93d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433064984 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_jtag_access.2433064984
Directory /workspace/26.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/26.lc_ctrl_prog_failure.3787450578
Short name T743
Test name
Test status
Simulation time 144420118 ps
CPU time 3.04 seconds
Started Jun 07 07:31:05 PM PDT 24
Finished Jun 07 07:31:12 PM PDT 24
Peak memory 218692 kb
Host smart-2f57abfe-c27c-4491-86b4-5fa6ea999d75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787450578 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_prog_failure.3787450578
Directory /workspace/26.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_mubi.2474863675
Short name T40
Test name
Test status
Simulation time 1360611139 ps
CPU time 13.43 seconds
Started Jun 07 07:31:01 PM PDT 24
Finished Jun 07 07:31:18 PM PDT 24
Peak memory 226516 kb
Host smart-029ed4f6-2267-430d-b8df-c6a1bb276638
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474863675 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_mubi.2474863675
Directory /workspace/26.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_digest.1867911802
Short name T489
Test name
Test status
Simulation time 436749062 ps
CPU time 18.2 seconds
Started Jun 07 07:31:03 PM PDT 24
Finished Jun 07 07:31:25 PM PDT 24
Peak memory 218688 kb
Host smart-2691e03e-41b2-4bbd-b1b9-58f349145fb1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867911802 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_d
igest.1867911802
Directory /workspace/26.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_mux.2863265876
Short name T399
Test name
Test status
Simulation time 183526002 ps
CPU time 7.73 seconds
Started Jun 07 07:31:02 PM PDT 24
Finished Jun 07 07:31:13 PM PDT 24
Peak memory 218736 kb
Host smart-3d6385b5-d0a6-447f-ae71-108ec2dc79d6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863265876 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_mux.
2863265876
Directory /workspace/26.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/26.lc_ctrl_security_escalation.2636230134
Short name T592
Test name
Test status
Simulation time 540710827 ps
CPU time 8.22 seconds
Started Jun 07 07:31:02 PM PDT 24
Finished Jun 07 07:31:15 PM PDT 24
Peak memory 218780 kb
Host smart-b68676f2-b723-48e5-a8f5-a5034e3c22b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636230134 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_security_escalation.2636230134
Directory /workspace/26.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/26.lc_ctrl_smoke.2697753203
Short name T69
Test name
Test status
Simulation time 180615017 ps
CPU time 2.93 seconds
Started Jun 07 07:31:05 PM PDT 24
Finished Jun 07 07:31:12 PM PDT 24
Peak memory 215344 kb
Host smart-edbfaf1e-2e0c-44f0-872a-059fffdf1c52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697753203 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_smoke.2697753203
Directory /workspace/26.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_failure.3003241678
Short name T462
Test name
Test status
Simulation time 312316272 ps
CPU time 31.3 seconds
Started Jun 07 07:31:05 PM PDT 24
Finished Jun 07 07:31:40 PM PDT 24
Peak memory 251428 kb
Host smart-81a0c9a7-31b0-4b5b-9200-478fbd6dad08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003241678 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_failure.3003241678
Directory /workspace/26.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_post_trans.1852818322
Short name T571
Test name
Test status
Simulation time 46206916 ps
CPU time 6.3 seconds
Started Jun 07 07:31:08 PM PDT 24
Finished Jun 07 07:31:18 PM PDT 24
Peak memory 251304 kb
Host smart-60a157ba-62ce-4daa-ba2d-42a1d73b0802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852818322 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_post_trans.1852818322
Directory /workspace/26.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all.1187893825
Short name T508
Test name
Test status
Simulation time 2418468131 ps
CPU time 86.07 seconds
Started Jun 07 07:31:10 PM PDT 24
Finished Jun 07 07:32:39 PM PDT 24
Peak memory 244408 kb
Host smart-24b750ad-f085-462e-af56-0955e9090cf7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187893825 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.lc_ctrl_stress_all.1187893825
Directory /workspace/26.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.lc_ctrl_volatile_unlock_smoke.2148729123
Short name T174
Test name
Test status
Simulation time 14416606 ps
CPU time 0.87 seconds
Started Jun 07 07:31:05 PM PDT 24
Finished Jun 07 07:31:10 PM PDT 24
Peak memory 209324 kb
Host smart-582c141b-85ec-4af5-87eb-76ba5aa78c42
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148729123 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_c
trl_volatile_unlock_smoke.2148729123
Directory /workspace/26.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_alert_test.3704685685
Short name T271
Test name
Test status
Simulation time 37972179 ps
CPU time 0.79 seconds
Started Jun 07 07:31:09 PM PDT 24
Finished Jun 07 07:31:14 PM PDT 24
Peak memory 209408 kb
Host smart-4a73b9ca-a365-49a6-b13b-4276ec95eac6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704685685 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_alert_test.3704685685
Directory /workspace/27.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.lc_ctrl_errors.1228238330
Short name T614
Test name
Test status
Simulation time 6210124092 ps
CPU time 13.11 seconds
Started Jun 07 07:31:13 PM PDT 24
Finished Jun 07 07:31:29 PM PDT 24
Peak memory 218756 kb
Host smart-89c13e69-c501-4f76-9fc0-3274031fd609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228238330 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_errors.1228238330
Directory /workspace/27.lc_ctrl_errors/latest

Test location /workspace/coverage/default/27.lc_ctrl_jtag_access.2357948394
Short name T435
Test name
Test status
Simulation time 356953138 ps
CPU time 2.64 seconds
Started Jun 07 07:31:10 PM PDT 24
Finished Jun 07 07:31:16 PM PDT 24
Peak memory 217560 kb
Host smart-8c691f67-10e9-4c4b-ad97-a622155fc01e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357948394 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_jtag_access.2357948394
Directory /workspace/27.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/27.lc_ctrl_prog_failure.3192846468
Short name T800
Test name
Test status
Simulation time 157904409 ps
CPU time 2.28 seconds
Started Jun 07 07:31:13 PM PDT 24
Finished Jun 07 07:31:18 PM PDT 24
Peak memory 222728 kb
Host smart-a20352c8-0a06-4d6f-8b5c-a9794d5033ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192846468 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_prog_failure.3192846468
Directory /workspace/27.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_mubi.2944680187
Short name T631
Test name
Test status
Simulation time 8367451315 ps
CPU time 17.11 seconds
Started Jun 07 07:31:07 PM PDT 24
Finished Jun 07 07:31:28 PM PDT 24
Peak memory 226472 kb
Host smart-193cc39a-ae47-4335-a023-0a6b8d63823b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944680187 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_mubi.2944680187
Directory /workspace/27.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_digest.2725110354
Short name T870
Test name
Test status
Simulation time 1467054204 ps
CPU time 7.62 seconds
Started Jun 07 07:31:09 PM PDT 24
Finished Jun 07 07:31:20 PM PDT 24
Peak memory 226532 kb
Host smart-4e095eb9-eff5-42a6-a609-fa5870083761
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725110354 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_d
igest.2725110354
Directory /workspace/27.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_mux.1166112030
Short name T261
Test name
Test status
Simulation time 981561876 ps
CPU time 6.87 seconds
Started Jun 07 07:31:09 PM PDT 24
Finished Jun 07 07:31:19 PM PDT 24
Peak memory 226536 kb
Host smart-71a18041-6b3d-48de-97e3-489f2b4e431a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166112030 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_mux.
1166112030
Directory /workspace/27.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/27.lc_ctrl_security_escalation.2474344489
Short name T181
Test name
Test status
Simulation time 450149131 ps
CPU time 10.9 seconds
Started Jun 07 07:31:09 PM PDT 24
Finished Jun 07 07:31:23 PM PDT 24
Peak memory 225736 kb
Host smart-88372494-9e10-4788-9129-a0b18def29cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474344489 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_security_escalation.2474344489
Directory /workspace/27.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/27.lc_ctrl_smoke.1550722792
Short name T350
Test name
Test status
Simulation time 137376065 ps
CPU time 2.69 seconds
Started Jun 07 07:31:10 PM PDT 24
Finished Jun 07 07:31:17 PM PDT 24
Peak memory 214832 kb
Host smart-35d8b03f-5a55-48f1-83b4-3a4a1e31a856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550722792 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_smoke.1550722792
Directory /workspace/27.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_failure.2531552501
Short name T361
Test name
Test status
Simulation time 285428729 ps
CPU time 30.18 seconds
Started Jun 07 07:31:12 PM PDT 24
Finished Jun 07 07:31:46 PM PDT 24
Peak memory 251344 kb
Host smart-42645d11-040d-436c-9f2c-9702e109e348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531552501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_failure.2531552501
Directory /workspace/27.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_post_trans.3409668160
Short name T264
Test name
Test status
Simulation time 68583575 ps
CPU time 8.24 seconds
Started Jun 07 07:31:13 PM PDT 24
Finished Jun 07 07:31:24 PM PDT 24
Peak memory 251396 kb
Host smart-ce86f64d-798a-45e0-9cfe-ddef1490af74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409668160 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_post_trans.3409668160
Directory /workspace/27.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/27.lc_ctrl_volatile_unlock_smoke.3871674011
Short name T698
Test name
Test status
Simulation time 33927197 ps
CPU time 0.82 seconds
Started Jun 07 07:31:11 PM PDT 24
Finished Jun 07 07:31:15 PM PDT 24
Peak memory 209144 kb
Host smart-91380c6a-efd4-4d40-8e68-d32bee7f479c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871674011 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_c
trl_volatile_unlock_smoke.3871674011
Directory /workspace/27.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_alert_test.2192227864
Short name T408
Test name
Test status
Simulation time 114788705 ps
CPU time 1.04 seconds
Started Jun 07 07:31:15 PM PDT 24
Finished Jun 07 07:31:18 PM PDT 24
Peak memory 209428 kb
Host smart-82da7395-2cc5-4c5b-b689-11f4ebcb705c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192227864 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_alert_test.2192227864
Directory /workspace/28.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.lc_ctrl_errors.2381326961
Short name T832
Test name
Test status
Simulation time 1251871505 ps
CPU time 13.59 seconds
Started Jun 07 07:31:15 PM PDT 24
Finished Jun 07 07:31:31 PM PDT 24
Peak memory 218668 kb
Host smart-4c6592f0-6929-49d1-967f-7521c32b95e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381326961 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_errors.2381326961
Directory /workspace/28.lc_ctrl_errors/latest

Test location /workspace/coverage/default/28.lc_ctrl_jtag_access.3121301422
Short name T641
Test name
Test status
Simulation time 103012123 ps
CPU time 1.07 seconds
Started Jun 07 07:31:16 PM PDT 24
Finished Jun 07 07:31:19 PM PDT 24
Peak memory 217672 kb
Host smart-50daabd5-f40b-460d-a38f-bd9991a83a01
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121301422 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_jtag_access.3121301422
Directory /workspace/28.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/28.lc_ctrl_prog_failure.2353795518
Short name T346
Test name
Test status
Simulation time 31551107 ps
CPU time 1.8 seconds
Started Jun 07 07:31:08 PM PDT 24
Finished Jun 07 07:31:14 PM PDT 24
Peak memory 222520 kb
Host smart-55f2c665-fa13-41b5-bbed-40675ebc350e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353795518 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_prog_failure.2353795518
Directory /workspace/28.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_mubi.3100354822
Short name T306
Test name
Test status
Simulation time 338424936 ps
CPU time 14.94 seconds
Started Jun 07 07:31:11 PM PDT 24
Finished Jun 07 07:31:29 PM PDT 24
Peak memory 220424 kb
Host smart-c351c3d7-9151-4171-a1ab-c749b508c8f3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100354822 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_mubi.3100354822
Directory /workspace/28.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_digest.2131737852
Short name T828
Test name
Test status
Simulation time 974049433 ps
CPU time 11.11 seconds
Started Jun 07 07:31:13 PM PDT 24
Finished Jun 07 07:31:27 PM PDT 24
Peak memory 226528 kb
Host smart-71741115-e5d3-4195-8769-8b7d2697b98d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131737852 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_d
igest.2131737852
Directory /workspace/28.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_mux.2747350603
Short name T351
Test name
Test status
Simulation time 2389672756 ps
CPU time 19.67 seconds
Started Jun 07 07:31:11 PM PDT 24
Finished Jun 07 07:31:34 PM PDT 24
Peak memory 226600 kb
Host smart-a03e59e2-6dce-419c-88ab-159ac8b2bb38
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747350603 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_mux.
2747350603
Directory /workspace/28.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/28.lc_ctrl_security_escalation.3212915413
Short name T215
Test name
Test status
Simulation time 1609457816 ps
CPU time 13.82 seconds
Started Jun 07 07:31:13 PM PDT 24
Finished Jun 07 07:31:30 PM PDT 24
Peak memory 226468 kb
Host smart-f49c3b20-c494-4cb0-9218-13b2301be26c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212915413 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_security_escalation.3212915413
Directory /workspace/28.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/28.lc_ctrl_smoke.3229802098
Short name T66
Test name
Test status
Simulation time 53983714 ps
CPU time 3.88 seconds
Started Jun 07 07:31:09 PM PDT 24
Finished Jun 07 07:31:17 PM PDT 24
Peak memory 215080 kb
Host smart-24eac6b4-69a0-4e26-977d-307b0cdcde91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229802098 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_smoke.3229802098
Directory /workspace/28.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_failure.3008500063
Short name T808
Test name
Test status
Simulation time 7313529143 ps
CPU time 28.14 seconds
Started Jun 07 07:31:11 PM PDT 24
Finished Jun 07 07:31:43 PM PDT 24
Peak memory 251448 kb
Host smart-a9e0d578-14a2-4ee1-95df-9c94df011e5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008500063 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_failure.3008500063
Directory /workspace/28.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_post_trans.2041179740
Short name T524
Test name
Test status
Simulation time 149051960 ps
CPU time 3.04 seconds
Started Jun 07 07:31:09 PM PDT 24
Finished Jun 07 07:31:16 PM PDT 24
Peak memory 222452 kb
Host smart-0188b90b-44fb-4d22-a300-6e6d4e408636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041179740 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_post_trans.2041179740
Directory /workspace/28.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/28.lc_ctrl_stress_all.266850398
Short name T252
Test name
Test status
Simulation time 8488771211 ps
CPU time 314.05 seconds
Started Jun 07 07:31:12 PM PDT 24
Finished Jun 07 07:36:29 PM PDT 24
Peak memory 276052 kb
Host smart-174e3d93-f0f1-4b40-8007-3d9c735ad13c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266850398 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.lc_ctrl_stress_all.266850398
Directory /workspace/28.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.lc_ctrl_stress_all_with_rand_reset.1265026976
Short name T58
Test name
Test status
Simulation time 133882864598 ps
CPU time 330.41 seconds
Started Jun 07 07:31:12 PM PDT 24
Finished Jun 07 07:36:46 PM PDT 24
Peak memory 293932 kb
Host smart-90ca4764-3ec7-46b5-a39e-ae541f448e4d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1265026976 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_stress_all_with_rand_reset.1265026976
Directory /workspace/28.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.lc_ctrl_volatile_unlock_smoke.3934305819
Short name T414
Test name
Test status
Simulation time 13579541 ps
CPU time 0.96 seconds
Started Jun 07 07:31:09 PM PDT 24
Finished Jun 07 07:31:13 PM PDT 24
Peak memory 209624 kb
Host smart-a26626f9-9423-443b-97e0-afc07aff2ea7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934305819 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_c
trl_volatile_unlock_smoke.3934305819
Directory /workspace/28.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_alert_test.2964775782
Short name T751
Test name
Test status
Simulation time 23987282 ps
CPU time 1.24 seconds
Started Jun 07 07:31:14 PM PDT 24
Finished Jun 07 07:31:18 PM PDT 24
Peak memory 209532 kb
Host smart-7277b2ef-e0ce-439e-bc0f-5c79080af395
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964775782 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_alert_test.2964775782
Directory /workspace/29.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.lc_ctrl_errors.3561455876
Short name T630
Test name
Test status
Simulation time 349051651 ps
CPU time 9.8 seconds
Started Jun 07 07:31:10 PM PDT 24
Finished Jun 07 07:31:23 PM PDT 24
Peak memory 218684 kb
Host smart-2f696d99-09ec-4db3-b111-559a4c9c9b5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561455876 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_errors.3561455876
Directory /workspace/29.lc_ctrl_errors/latest

Test location /workspace/coverage/default/29.lc_ctrl_jtag_access.922863512
Short name T528
Test name
Test status
Simulation time 885758879 ps
CPU time 6.09 seconds
Started Jun 07 07:31:14 PM PDT 24
Finished Jun 07 07:31:22 PM PDT 24
Peak memory 217952 kb
Host smart-8a333b67-facf-43fd-98a7-6877e7d32796
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922863512 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_jtag_access.922863512
Directory /workspace/29.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/29.lc_ctrl_prog_failure.380368204
Short name T678
Test name
Test status
Simulation time 17370658 ps
CPU time 1.63 seconds
Started Jun 07 07:31:15 PM PDT 24
Finished Jun 07 07:31:19 PM PDT 24
Peak memory 218736 kb
Host smart-bfd44f84-3b75-460f-82cf-65482174a44c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380368204 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_prog_failure.380368204
Directory /workspace/29.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_mubi.274210255
Short name T532
Test name
Test status
Simulation time 460595004 ps
CPU time 17.55 seconds
Started Jun 07 07:31:17 PM PDT 24
Finished Jun 07 07:31:36 PM PDT 24
Peak memory 219408 kb
Host smart-baab3f70-fed0-463f-bb08-008de9f13518
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274210255 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_mubi.274210255
Directory /workspace/29.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_digest.1734097232
Short name T219
Test name
Test status
Simulation time 2299411857 ps
CPU time 23.51 seconds
Started Jun 07 07:31:19 PM PDT 24
Finished Jun 07 07:31:43 PM PDT 24
Peak memory 218724 kb
Host smart-28087886-f3e5-44cd-b8bb-b94fb89576d0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734097232 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_d
igest.1734097232
Directory /workspace/29.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_mux.1642667537
Short name T816
Test name
Test status
Simulation time 216766082 ps
CPU time 6.79 seconds
Started Jun 07 07:31:14 PM PDT 24
Finished Jun 07 07:31:23 PM PDT 24
Peak memory 218704 kb
Host smart-4a668d8e-d726-45d3-aa76-f34733b3fd39
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642667537 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_mux.
1642667537
Directory /workspace/29.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/29.lc_ctrl_security_escalation.3504023771
Short name T634
Test name
Test status
Simulation time 933573054 ps
CPU time 9.69 seconds
Started Jun 07 07:31:11 PM PDT 24
Finished Jun 07 07:31:24 PM PDT 24
Peak memory 226456 kb
Host smart-9719d83f-a238-4b33-a7bc-d021e786d1c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504023771 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_security_escalation.3504023771
Directory /workspace/29.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/29.lc_ctrl_smoke.2404624289
Short name T82
Test name
Test status
Simulation time 94628127 ps
CPU time 1.71 seconds
Started Jun 07 07:31:12 PM PDT 24
Finished Jun 07 07:31:17 PM PDT 24
Peak memory 214388 kb
Host smart-20fd2b7b-8b7d-44ca-aff1-3f8c203efc7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404624289 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_smoke.2404624289
Directory /workspace/29.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_failure.4085091884
Short name T555
Test name
Test status
Simulation time 220959054 ps
CPU time 24.9 seconds
Started Jun 07 07:31:15 PM PDT 24
Finished Jun 07 07:31:42 PM PDT 24
Peak memory 251480 kb
Host smart-94726f4b-9ca1-4221-9d7b-7bb2ae240d5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085091884 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_failure.4085091884
Directory /workspace/29.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_post_trans.2576244818
Short name T292
Test name
Test status
Simulation time 60813953 ps
CPU time 3.03 seconds
Started Jun 07 07:31:13 PM PDT 24
Finished Jun 07 07:31:19 PM PDT 24
Peak memory 226832 kb
Host smart-fda38ea1-d360-4bb9-a5d2-0e99d78d1b71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576244818 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_post_trans.2576244818
Directory /workspace/29.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/29.lc_ctrl_stress_all.1829355414
Short name T535
Test name
Test status
Simulation time 4804965827 ps
CPU time 103.92 seconds
Started Jun 07 07:31:19 PM PDT 24
Finished Jun 07 07:33:04 PM PDT 24
Peak memory 284284 kb
Host smart-c2ab62f3-48a4-4994-a2ff-41140ed9e5df
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829355414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.lc_ctrl_stress_all.1829355414
Directory /workspace/29.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.lc_ctrl_volatile_unlock_smoke.720147450
Short name T586
Test name
Test status
Simulation time 56822202 ps
CPU time 1 seconds
Started Jun 07 07:31:11 PM PDT 24
Finished Jun 07 07:31:16 PM PDT 24
Peak memory 212300 kb
Host smart-cd45220a-0180-4441-b10f-42f3667d6ad8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720147450 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ct
rl_volatile_unlock_smoke.720147450
Directory /workspace/29.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_alert_test.2469621346
Short name T595
Test name
Test status
Simulation time 19300237 ps
CPU time 0.93 seconds
Started Jun 07 07:29:32 PM PDT 24
Finished Jun 07 07:29:36 PM PDT 24
Peak memory 209356 kb
Host smart-efd632c2-1766-4240-a1c2-b749dd579748
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469621346 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_alert_test.2469621346
Directory /workspace/3.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.lc_ctrl_errors.1770841895
Short name T480
Test name
Test status
Simulation time 581722295 ps
CPU time 10.56 seconds
Started Jun 07 07:29:19 PM PDT 24
Finished Jun 07 07:29:32 PM PDT 24
Peak memory 218656 kb
Host smart-b0c9c4af-0c4e-4c63-ae25-8e2579930152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770841895 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_errors.1770841895
Directory /workspace/3.lc_ctrl_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_access.2083855852
Short name T853
Test name
Test status
Simulation time 997128303 ps
CPU time 3.02 seconds
Started Jun 07 07:29:22 PM PDT 24
Finished Jun 07 07:29:28 PM PDT 24
Peak memory 217656 kb
Host smart-f528e847-9c92-4cc3-a2c7-2811c640807c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083855852 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_access.2083855852
Directory /workspace/3.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_errors.827203391
Short name T824
Test name
Test status
Simulation time 1056264304 ps
CPU time 22.22 seconds
Started Jun 07 07:29:22 PM PDT 24
Finished Jun 07 07:29:47 PM PDT 24
Peak memory 219384 kb
Host smart-08032b00-e287-43d5-8032-75d16d8cc885
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827203391 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_err
ors.827203391
Directory /workspace/3.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_priority.2211052238
Short name T65
Test name
Test status
Simulation time 564620833 ps
CPU time 6.06 seconds
Started Jun 07 07:29:22 PM PDT 24
Finished Jun 07 07:29:31 PM PDT 24
Peak memory 218236 kb
Host smart-25840bcb-db59-4e7c-816b-f57fc745fb49
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211052238 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_priority.2
211052238
Directory /workspace/3.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_prog_failure.681380693
Short name T216
Test name
Test status
Simulation time 697047453 ps
CPU time 5.06 seconds
Started Jun 07 07:29:22 PM PDT 24
Finished Jun 07 07:29:30 PM PDT 24
Peak memory 218736 kb
Host smart-974ca0f0-da58-4a2b-97dc-2a9bbea39cae
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681380693 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_
prog_failure.681380693
Directory /workspace/3.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_regwen_during_op.2476524904
Short name T616
Test name
Test status
Simulation time 2405613688 ps
CPU time 16.79 seconds
Started Jun 07 07:29:23 PM PDT 24
Finished Jun 07 07:29:43 PM PDT 24
Peak memory 218304 kb
Host smart-7cabf215-b884-4944-bcfa-b901dd4d9003
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476524904 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_regwen_during_op.2476524904
Directory /workspace/3.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_smoke.1582442969
Short name T783
Test name
Test status
Simulation time 255518288 ps
CPU time 8.3 seconds
Started Jun 07 07:29:21 PM PDT 24
Finished Jun 07 07:29:32 PM PDT 24
Peak memory 218340 kb
Host smart-bf1c30d0-b763-4b88-b386-a77dae7e58f6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582442969 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_smoke.
1582442969
Directory /workspace/3.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_failure.1157725332
Short name T316
Test name
Test status
Simulation time 3283496458 ps
CPU time 62.46 seconds
Started Jun 07 07:29:22 PM PDT 24
Finished Jun 07 07:30:28 PM PDT 24
Peak memory 283756 kb
Host smart-3cb60522-ffb2-44eb-be69-4f54bdee45a6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157725332 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jta
g_state_failure.1157725332
Directory /workspace/3.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_post_trans.918069064
Short name T655
Test name
Test status
Simulation time 3859358017 ps
CPU time 28.39 seconds
Started Jun 07 07:29:21 PM PDT 24
Finished Jun 07 07:29:52 PM PDT 24
Peak memory 226188 kb
Host smart-ed1ac2a9-6661-4378-a007-df7b8ca58d1c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918069064 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_j
tag_state_post_trans.918069064
Directory /workspace/3.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_prog_failure.149035558
Short name T531
Test name
Test status
Simulation time 154598274 ps
CPU time 3.67 seconds
Started Jun 07 07:29:21 PM PDT 24
Finished Jun 07 07:29:28 PM PDT 24
Peak memory 222792 kb
Host smart-7967a208-f0a3-4eea-8ac5-aab8a5589364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149035558 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_prog_failure.149035558
Directory /workspace/3.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_regwen_during_op.2209873375
Short name T686
Test name
Test status
Simulation time 4015691706 ps
CPU time 10.36 seconds
Started Jun 07 07:29:22 PM PDT 24
Finished Jun 07 07:29:35 PM PDT 24
Peak memory 215948 kb
Host smart-2c080302-b9f5-4140-8abd-0ffa2f79e3d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209873375 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_regwen_during_op.2209873375
Directory /workspace/3.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_cm.682858604
Short name T85
Test name
Test status
Simulation time 252358947 ps
CPU time 25.59 seconds
Started Jun 07 07:29:26 PM PDT 24
Finished Jun 07 07:29:55 PM PDT 24
Peak memory 284884 kb
Host smart-8e674278-d3ff-4196-90dd-bef3d7d8abc1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682858604 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_cm.682858604
Directory /workspace/3.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_mubi.4199788098
Short name T554
Test name
Test status
Simulation time 290634729 ps
CPU time 10.2 seconds
Started Jun 07 07:29:22 PM PDT 24
Finished Jun 07 07:29:35 PM PDT 24
Peak memory 219380 kb
Host smart-da55bc09-4441-4611-b35b-3cb30093df33
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199788098 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_mubi.4199788098
Directory /workspace/3.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_digest.2547489983
Short name T221
Test name
Test status
Simulation time 2269439541 ps
CPU time 12.57 seconds
Started Jun 07 07:29:22 PM PDT 24
Finished Jun 07 07:29:37 PM PDT 24
Peak memory 218812 kb
Host smart-bff57f1b-1052-49f0-8853-8ba420faba14
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547489983 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_di
gest.2547489983
Directory /workspace/3.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_mux.461946531
Short name T572
Test name
Test status
Simulation time 943801405 ps
CPU time 7.42 seconds
Started Jun 07 07:29:20 PM PDT 24
Finished Jun 07 07:29:29 PM PDT 24
Peak memory 226580 kb
Host smart-538c5189-20fc-463e-b885-877880fafe8b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461946531 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_mux.461946531
Directory /workspace/3.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/3.lc_ctrl_security_escalation.4093995613
Short name T769
Test name
Test status
Simulation time 411108776 ps
CPU time 9.47 seconds
Started Jun 07 07:29:20 PM PDT 24
Finished Jun 07 07:29:33 PM PDT 24
Peak memory 225932 kb
Host smart-cbed50af-f2eb-45d7-9bbb-493917f0436d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093995613 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_security_escalation.4093995613
Directory /workspace/3.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/3.lc_ctrl_smoke.3662466050
Short name T677
Test name
Test status
Simulation time 49840983 ps
CPU time 3.51 seconds
Started Jun 07 07:29:22 PM PDT 24
Finished Jun 07 07:29:28 PM PDT 24
Peak memory 218208 kb
Host smart-cea524e8-f956-40f3-8483-b199d2c7f803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662466050 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_smoke.3662466050
Directory /workspace/3.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_failure.3122808474
Short name T308
Test name
Test status
Simulation time 527681312 ps
CPU time 23.19 seconds
Started Jun 07 07:29:17 PM PDT 24
Finished Jun 07 07:29:42 PM PDT 24
Peak memory 251364 kb
Host smart-d346f90a-6317-40c7-8f0f-f6f4655d417c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122808474 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_failure.3122808474
Directory /workspace/3.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_post_trans.1272023526
Short name T60
Test name
Test status
Simulation time 442832692 ps
CPU time 2.88 seconds
Started Jun 07 07:29:19 PM PDT 24
Finished Jun 07 07:29:24 PM PDT 24
Peak memory 222576 kb
Host smart-0e8a6969-1041-42e2-9642-225aab08df41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272023526 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_post_trans.1272023526
Directory /workspace/3.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_stress_all.3175522334
Short name T83
Test name
Test status
Simulation time 5077201993 ps
CPU time 35.08 seconds
Started Jun 07 07:29:23 PM PDT 24
Finished Jun 07 07:30:01 PM PDT 24
Peak memory 251440 kb
Host smart-c9c820e6-8d5a-4809-8e79-c5a6b8a95015
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175522334 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.lc_ctrl_stress_all.3175522334
Directory /workspace/3.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.lc_ctrl_stress_all_with_rand_reset.1205475038
Short name T618
Test name
Test status
Simulation time 37654363743 ps
CPU time 641.67 seconds
Started Jun 07 07:29:24 PM PDT 24
Finished Jun 07 07:40:09 PM PDT 24
Peak memory 284452 kb
Host smart-cb29fd86-7896-43f3-a66b-3ccfef0c36ea
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1205475038 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_stress_all_with_rand_reset.1205475038
Directory /workspace/3.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.lc_ctrl_volatile_unlock_smoke.1998224291
Short name T773
Test name
Test status
Simulation time 15936654 ps
CPU time 1.19 seconds
Started Jun 07 07:29:20 PM PDT 24
Finished Jun 07 07:29:25 PM PDT 24
Peak memory 212380 kb
Host smart-259aa578-276f-4409-a3e3-ac90625a4ef4
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998224291 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ct
rl_volatile_unlock_smoke.1998224291
Directory /workspace/3.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_alert_test.566764578
Short name T777
Test name
Test status
Simulation time 18743407 ps
CPU time 1.18 seconds
Started Jun 07 07:31:21 PM PDT 24
Finished Jun 07 07:31:23 PM PDT 24
Peak memory 209376 kb
Host smart-fd96cc9a-02e1-4b3f-a74f-7f9a4f3f3d13
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566764578 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_alert_test.566764578
Directory /workspace/30.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.lc_ctrl_errors.3996972394
Short name T15
Test name
Test status
Simulation time 1107226049 ps
CPU time 14.19 seconds
Started Jun 07 07:31:14 PM PDT 24
Finished Jun 07 07:31:31 PM PDT 24
Peak memory 218608 kb
Host smart-47aa8570-800a-4baa-83fe-79a893d5ad2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996972394 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_errors.3996972394
Directory /workspace/30.lc_ctrl_errors/latest

Test location /workspace/coverage/default/30.lc_ctrl_jtag_access.3701890267
Short name T26
Test name
Test status
Simulation time 1463392412 ps
CPU time 5.1 seconds
Started Jun 07 07:31:13 PM PDT 24
Finished Jun 07 07:31:21 PM PDT 24
Peak memory 217816 kb
Host smart-7629d5bf-5a93-4a6a-a535-77ba1d8cfab2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701890267 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_jtag_access.3701890267
Directory /workspace/30.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/30.lc_ctrl_prog_failure.3021635728
Short name T667
Test name
Test status
Simulation time 85876962 ps
CPU time 4.25 seconds
Started Jun 07 07:31:20 PM PDT 24
Finished Jun 07 07:31:26 PM PDT 24
Peak memory 223020 kb
Host smart-a6177ca7-fb1b-4689-9c34-4ee3cfe4572e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021635728 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_prog_failure.3021635728
Directory /workspace/30.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_mubi.2170694344
Short name T403
Test name
Test status
Simulation time 1107529165 ps
CPU time 11.42 seconds
Started Jun 07 07:31:21 PM PDT 24
Finished Jun 07 07:31:34 PM PDT 24
Peak memory 218724 kb
Host smart-272be5c0-fcc7-4a44-b9d4-d05c90e1053f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170694344 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_mubi.2170694344
Directory /workspace/30.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_digest.1481347338
Short name T426
Test name
Test status
Simulation time 263921750 ps
CPU time 12.51 seconds
Started Jun 07 07:31:17 PM PDT 24
Finished Jun 07 07:31:31 PM PDT 24
Peak memory 218712 kb
Host smart-74459cad-16d7-4c44-9c87-f4feb0d5f1e0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481347338 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_d
igest.1481347338
Directory /workspace/30.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_mux.1709021323
Short name T545
Test name
Test status
Simulation time 189233756 ps
CPU time 7.43 seconds
Started Jun 07 07:31:16 PM PDT 24
Finished Jun 07 07:31:26 PM PDT 24
Peak memory 225728 kb
Host smart-095597af-0143-4583-8bc9-7d8ca6b5bfd9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709021323 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_mux.
1709021323
Directory /workspace/30.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/30.lc_ctrl_security_escalation.1536829402
Short name T550
Test name
Test status
Simulation time 447184786 ps
CPU time 6.78 seconds
Started Jun 07 07:31:15 PM PDT 24
Finished Jun 07 07:31:24 PM PDT 24
Peak memory 224604 kb
Host smart-51b51535-36ee-4790-b54d-dab0c3f10a66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536829402 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_security_escalation.1536829402
Directory /workspace/30.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/30.lc_ctrl_smoke.3000171521
Short name T156
Test name
Test status
Simulation time 164218044 ps
CPU time 4.57 seconds
Started Jun 07 07:31:15 PM PDT 24
Finished Jun 07 07:31:22 PM PDT 24
Peak memory 218188 kb
Host smart-719a7761-7638-4405-91a5-d86dc0a423ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000171521 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_smoke.3000171521
Directory /workspace/30.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_failure.2289625033
Short name T518
Test name
Test status
Simulation time 219606562 ps
CPU time 30.78 seconds
Started Jun 07 07:31:15 PM PDT 24
Finished Jun 07 07:31:48 PM PDT 24
Peak memory 251428 kb
Host smart-4314f91e-95fd-49a2-9021-b4535fd60d36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289625033 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_failure.2289625033
Directory /workspace/30.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_post_trans.1231127676
Short name T484
Test name
Test status
Simulation time 127625686 ps
CPU time 7.84 seconds
Started Jun 07 07:31:16 PM PDT 24
Finished Jun 07 07:31:26 PM PDT 24
Peak memory 251368 kb
Host smart-4571139c-df1a-467f-8261-2ae9888f6349
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231127676 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_post_trans.1231127676
Directory /workspace/30.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all.1808038466
Short name T598
Test name
Test status
Simulation time 894391364 ps
CPU time 22.73 seconds
Started Jun 07 07:31:14 PM PDT 24
Finished Jun 07 07:31:39 PM PDT 24
Peak memory 218288 kb
Host smart-ca1778ad-33b6-4770-ba98-a89a7c10add0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808038466 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.lc_ctrl_stress_all.1808038466
Directory /workspace/30.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.lc_ctrl_volatile_unlock_smoke.4274403454
Short name T392
Test name
Test status
Simulation time 19983653 ps
CPU time 0.97 seconds
Started Jun 07 07:31:18 PM PDT 24
Finished Jun 07 07:31:20 PM PDT 24
Peak memory 209368 kb
Host smart-63e10dfd-42f5-45fc-983d-f75259e87318
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274403454 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_c
trl_volatile_unlock_smoke.4274403454
Directory /workspace/30.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_alert_test.1191813087
Short name T815
Test name
Test status
Simulation time 229505043 ps
CPU time 1.03 seconds
Started Jun 07 07:31:25 PM PDT 24
Finished Jun 07 07:31:28 PM PDT 24
Peak memory 209372 kb
Host smart-1dda11fe-7531-4e70-893e-e13918be575a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191813087 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_alert_test.1191813087
Directory /workspace/31.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.lc_ctrl_errors.171586348
Short name T394
Test name
Test status
Simulation time 570875036 ps
CPU time 11.56 seconds
Started Jun 07 07:31:17 PM PDT 24
Finished Jun 07 07:31:30 PM PDT 24
Peak memory 218684 kb
Host smart-892129d5-5b51-4c4a-83b5-75e30bf34038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171586348 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_errors.171586348
Directory /workspace/31.lc_ctrl_errors/latest

Test location /workspace/coverage/default/31.lc_ctrl_jtag_access.1953304818
Short name T722
Test name
Test status
Simulation time 4118518108 ps
CPU time 3.96 seconds
Started Jun 07 07:31:26 PM PDT 24
Finished Jun 07 07:31:32 PM PDT 24
Peak memory 218284 kb
Host smart-163cc8b8-f3af-4062-880e-1fcf5b7e3c3d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953304818 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_jtag_access.1953304818
Directory /workspace/31.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/31.lc_ctrl_prog_failure.3092733152
Short name T290
Test name
Test status
Simulation time 93375784 ps
CPU time 2.82 seconds
Started Jun 07 07:31:15 PM PDT 24
Finished Jun 07 07:31:20 PM PDT 24
Peak memory 222920 kb
Host smart-275850a9-9db1-48f0-87c2-5d1ab226aac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092733152 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_prog_failure.3092733152
Directory /workspace/31.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_mubi.1348951687
Short name T311
Test name
Test status
Simulation time 1467047334 ps
CPU time 14.03 seconds
Started Jun 07 07:31:26 PM PDT 24
Finished Jun 07 07:31:41 PM PDT 24
Peak memory 218804 kb
Host smart-a64f9536-7d85-4633-b2dd-f816381b7636
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348951687 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_mubi.1348951687
Directory /workspace/31.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_digest.975383220
Short name T538
Test name
Test status
Simulation time 838333596 ps
CPU time 7.63 seconds
Started Jun 07 07:31:24 PM PDT 24
Finished Jun 07 07:31:33 PM PDT 24
Peak memory 218724 kb
Host smart-70f90a08-c20a-4c2a-80a4-0e33c314af13
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975383220 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_di
gest.975383220
Directory /workspace/31.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_mux.1489697465
Short name T628
Test name
Test status
Simulation time 258141906 ps
CPU time 6.02 seconds
Started Jun 07 07:31:27 PM PDT 24
Finished Jun 07 07:31:35 PM PDT 24
Peak memory 218684 kb
Host smart-084e5fe6-e6fd-4f3b-a3a2-6a3b3a8a3954
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489697465 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_mux.
1489697465
Directory /workspace/31.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/31.lc_ctrl_security_escalation.6492613
Short name T714
Test name
Test status
Simulation time 4526020634 ps
CPU time 19.44 seconds
Started Jun 07 07:31:20 PM PDT 24
Finished Jun 07 07:31:40 PM PDT 24
Peak memory 226592 kb
Host smart-8a028597-b495-416a-9c19-f15eeeff3fa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6492613 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_security_escalation.6492613
Directory /workspace/31.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/31.lc_ctrl_smoke.2578863139
Short name T557
Test name
Test status
Simulation time 135308768 ps
CPU time 3.33 seconds
Started Jun 07 07:31:17 PM PDT 24
Finished Jun 07 07:31:22 PM PDT 24
Peak memory 218276 kb
Host smart-fcb15f68-258f-4bee-ae86-ff51221ac66f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578863139 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_smoke.2578863139
Directory /workspace/31.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_failure.347069818
Short name T317
Test name
Test status
Simulation time 413094459 ps
CPU time 22.06 seconds
Started Jun 07 07:31:17 PM PDT 24
Finished Jun 07 07:31:41 PM PDT 24
Peak memory 251424 kb
Host smart-73da9349-cd25-4ded-91ed-b7cd830a4f0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347069818 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_failure.347069818
Directory /workspace/31.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_post_trans.4072682191
Short name T453
Test name
Test status
Simulation time 136792451 ps
CPU time 7.47 seconds
Started Jun 07 07:31:14 PM PDT 24
Finished Jun 07 07:31:24 PM PDT 24
Peak memory 251424 kb
Host smart-b5172d8b-29f8-4997-bb51-aaf52a68898f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072682191 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_post_trans.4072682191
Directory /workspace/31.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/31.lc_ctrl_stress_all.3446291016
Short name T423
Test name
Test status
Simulation time 5449527097 ps
CPU time 57.47 seconds
Started Jun 07 07:31:26 PM PDT 24
Finished Jun 07 07:32:25 PM PDT 24
Peak memory 267860 kb
Host smart-6fde7891-1a6a-4296-a794-676b23e1594d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446291016 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.lc_ctrl_stress_all.3446291016
Directory /workspace/31.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.lc_ctrl_volatile_unlock_smoke.3207501944
Short name T665
Test name
Test status
Simulation time 12269296 ps
CPU time 0.95 seconds
Started Jun 07 07:31:22 PM PDT 24
Finished Jun 07 07:31:24 PM PDT 24
Peak memory 209608 kb
Host smart-b3f0ca7b-fad5-471b-a0b0-bcf62765f809
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207501944 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_c
trl_volatile_unlock_smoke.3207501944
Directory /workspace/31.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_alert_test.3268427623
Short name T376
Test name
Test status
Simulation time 15694491 ps
CPU time 0.89 seconds
Started Jun 07 07:31:27 PM PDT 24
Finished Jun 07 07:31:30 PM PDT 24
Peak memory 209404 kb
Host smart-7bc28119-2e84-459b-bf71-528675f184a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268427623 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_alert_test.3268427623
Directory /workspace/32.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.lc_ctrl_errors.318227579
Short name T298
Test name
Test status
Simulation time 1278010783 ps
CPU time 10.12 seconds
Started Jun 07 07:31:28 PM PDT 24
Finished Jun 07 07:31:40 PM PDT 24
Peak memory 218624 kb
Host smart-aedda655-3e9f-46f5-be17-69e1a146894e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318227579 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_errors.318227579
Directory /workspace/32.lc_ctrl_errors/latest

Test location /workspace/coverage/default/32.lc_ctrl_jtag_access.949030968
Short name T841
Test name
Test status
Simulation time 175643314 ps
CPU time 4.71 seconds
Started Jun 07 07:31:24 PM PDT 24
Finished Jun 07 07:31:29 PM PDT 24
Peak memory 217540 kb
Host smart-ef93801e-cca0-4c33-a1c8-e9fb1d9acc0f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949030968 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_jtag_access.949030968
Directory /workspace/32.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/32.lc_ctrl_prog_failure.1780955664
Short name T527
Test name
Test status
Simulation time 56860809 ps
CPU time 1.59 seconds
Started Jun 07 07:31:27 PM PDT 24
Finished Jun 07 07:31:31 PM PDT 24
Peak memory 222064 kb
Host smart-90e9c806-e0c3-4d63-8a41-5ef73a4bce1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780955664 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_prog_failure.1780955664
Directory /workspace/32.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_mubi.666341365
Short name T539
Test name
Test status
Simulation time 625889354 ps
CPU time 16.3 seconds
Started Jun 07 07:31:24 PM PDT 24
Finished Jun 07 07:31:42 PM PDT 24
Peak memory 219488 kb
Host smart-c2c60c53-1a19-4809-8c7a-746e90e8e3f3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666341365 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_mubi.666341365
Directory /workspace/32.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_digest.3567463190
Short name T283
Test name
Test status
Simulation time 635775008 ps
CPU time 12.7 seconds
Started Jun 07 07:31:25 PM PDT 24
Finished Jun 07 07:31:39 PM PDT 24
Peak memory 226588 kb
Host smart-64e2ae1a-cfe2-475b-922f-55db9b85cfb7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567463190 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_d
igest.3567463190
Directory /workspace/32.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_mux.2799911758
Short name T864
Test name
Test status
Simulation time 421276595 ps
CPU time 13.92 seconds
Started Jun 07 07:31:27 PM PDT 24
Finished Jun 07 07:31:43 PM PDT 24
Peak memory 218728 kb
Host smart-b92ea932-ef88-4cbe-8180-e36cc74b2543
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799911758 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_mux.
2799911758
Directory /workspace/32.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/32.lc_ctrl_security_escalation.1145518767
Short name T782
Test name
Test status
Simulation time 2249493320 ps
CPU time 7.94 seconds
Started Jun 07 07:31:27 PM PDT 24
Finished Jun 07 07:31:36 PM PDT 24
Peak memory 218808 kb
Host smart-78cc6adc-fa2a-4de4-bfe6-f84479d6e7e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145518767 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_security_escalation.1145518767
Directory /workspace/32.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/32.lc_ctrl_smoke.2184125280
Short name T837
Test name
Test status
Simulation time 87670619 ps
CPU time 1.16 seconds
Started Jun 07 07:31:24 PM PDT 24
Finished Jun 07 07:31:27 PM PDT 24
Peak memory 218236 kb
Host smart-85ac5cc2-590d-48e6-96cb-9bb04c090643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184125280 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_smoke.2184125280
Directory /workspace/32.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_failure.2195355
Short name T106
Test name
Test status
Simulation time 2022650463 ps
CPU time 24.94 seconds
Started Jun 07 07:31:27 PM PDT 24
Finished Jun 07 07:31:54 PM PDT 24
Peak memory 251340 kb
Host smart-2226cd01-1f1e-4170-92ad-6597738252d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195355 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_failure.2195355
Directory /workspace/32.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_post_trans.24327012
Short name T473
Test name
Test status
Simulation time 64887208 ps
CPU time 6.65 seconds
Started Jun 07 07:31:24 PM PDT 24
Finished Jun 07 07:31:32 PM PDT 24
Peak memory 247416 kb
Host smart-109c2ac5-99a5-4522-ace4-a7923828179e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24327012 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_post_trans.24327012
Directory /workspace/32.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all.760445844
Short name T459
Test name
Test status
Simulation time 5907911710 ps
CPU time 119.73 seconds
Started Jun 07 07:31:26 PM PDT 24
Finished Jun 07 07:33:27 PM PDT 24
Peak memory 283472 kb
Host smart-39f1071f-de57-439b-bcdc-c00e51382f24
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760445844 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.lc_ctrl_stress_all.760445844
Directory /workspace/32.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.lc_ctrl_volatile_unlock_smoke.2108657095
Short name T443
Test name
Test status
Simulation time 14982477 ps
CPU time 0.81 seconds
Started Jun 07 07:31:24 PM PDT 24
Finished Jun 07 07:31:26 PM PDT 24
Peak memory 209504 kb
Host smart-865b8ece-fbc2-44c3-8fa4-d50e0e3c43bd
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108657095 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_c
trl_volatile_unlock_smoke.2108657095
Directory /workspace/32.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_alert_test.1901609628
Short name T807
Test name
Test status
Simulation time 15701300 ps
CPU time 1.04 seconds
Started Jun 07 07:31:28 PM PDT 24
Finished Jun 07 07:31:31 PM PDT 24
Peak memory 209548 kb
Host smart-c3e27aff-86a3-4cd3-baba-3634ab747626
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901609628 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_alert_test.1901609628
Directory /workspace/33.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.lc_ctrl_errors.2265308009
Short name T711
Test name
Test status
Simulation time 486167695 ps
CPU time 15.8 seconds
Started Jun 07 07:31:27 PM PDT 24
Finished Jun 07 07:31:44 PM PDT 24
Peak memory 218708 kb
Host smart-53107676-7a3b-4eda-be6b-ef9845364621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265308009 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_errors.2265308009
Directory /workspace/33.lc_ctrl_errors/latest

Test location /workspace/coverage/default/33.lc_ctrl_jtag_access.1046807717
Short name T675
Test name
Test status
Simulation time 1028803765 ps
CPU time 12.79 seconds
Started Jun 07 07:31:26 PM PDT 24
Finished Jun 07 07:31:40 PM PDT 24
Peak memory 217896 kb
Host smart-2ba2677e-c7db-40ef-b717-4fd770e6afa3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046807717 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_jtag_access.1046807717
Directory /workspace/33.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/33.lc_ctrl_prog_failure.2597804583
Short name T819
Test name
Test status
Simulation time 261310208 ps
CPU time 5.53 seconds
Started Jun 07 07:31:28 PM PDT 24
Finished Jun 07 07:31:36 PM PDT 24
Peak memory 218604 kb
Host smart-82ace285-32a7-4caf-a3a0-49dd706b8cb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597804583 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_prog_failure.2597804583
Directory /workspace/33.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_mubi.1460007180
Short name T103
Test name
Test status
Simulation time 1244350392 ps
CPU time 19.5 seconds
Started Jun 07 07:31:26 PM PDT 24
Finished Jun 07 07:31:47 PM PDT 24
Peak memory 226508 kb
Host smart-411975ec-2965-47a1-89a8-84cb7440b1d6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460007180 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_mubi.1460007180
Directory /workspace/33.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_digest.538190300
Short name T359
Test name
Test status
Simulation time 1546374437 ps
CPU time 9.43 seconds
Started Jun 07 07:31:27 PM PDT 24
Finished Jun 07 07:31:39 PM PDT 24
Peak memory 218772 kb
Host smart-c1976cfd-d8e2-4654-acda-4a3a2cc880ef
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538190300 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_di
gest.538190300
Directory /workspace/33.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_mux.343335129
Short name T605
Test name
Test status
Simulation time 287237115 ps
CPU time 9.31 seconds
Started Jun 07 07:31:28 PM PDT 24
Finished Jun 07 07:31:40 PM PDT 24
Peak memory 226460 kb
Host smart-8016b752-6248-4716-9c9b-54df4e1ae383
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343335129 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_mux.343335129
Directory /workspace/33.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/33.lc_ctrl_security_escalation.1661147951
Short name T168
Test name
Test status
Simulation time 321621952 ps
CPU time 9.79 seconds
Started Jun 07 07:31:28 PM PDT 24
Finished Jun 07 07:31:40 PM PDT 24
Peak memory 226468 kb
Host smart-f64ec073-fdf9-4104-b51e-b454cdf38124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661147951 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_security_escalation.1661147951
Directory /workspace/33.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/33.lc_ctrl_smoke.2895116939
Short name T424
Test name
Test status
Simulation time 283239218 ps
CPU time 2.66 seconds
Started Jun 07 07:31:25 PM PDT 24
Finished Jun 07 07:31:30 PM PDT 24
Peak memory 218196 kb
Host smart-2d0b5d96-d45c-4517-ae55-7c684dfd0547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895116939 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_smoke.2895116939
Directory /workspace/33.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_failure.4280279303
Short name T405
Test name
Test status
Simulation time 962980622 ps
CPU time 26.6 seconds
Started Jun 07 07:31:26 PM PDT 24
Finished Jun 07 07:31:54 PM PDT 24
Peak memory 251448 kb
Host smart-9b54858c-8d34-4098-9804-5960827bbb98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280279303 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_failure.4280279303
Directory /workspace/33.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_post_trans.1454006962
Short name T587
Test name
Test status
Simulation time 95479677 ps
CPU time 8.21 seconds
Started Jun 07 07:31:25 PM PDT 24
Finished Jun 07 07:31:34 PM PDT 24
Peak memory 251380 kb
Host smart-0a56e425-9939-44e6-9429-b6a509b17364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454006962 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_post_trans.1454006962
Directory /workspace/33.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all.493420815
Short name T703
Test name
Test status
Simulation time 7196904772 ps
CPU time 228.86 seconds
Started Jun 07 07:31:29 PM PDT 24
Finished Jun 07 07:35:20 PM PDT 24
Peak memory 251556 kb
Host smart-0bdd63dc-b1a7-4a2e-8542-325942796ed8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493420815 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.lc_ctrl_stress_all.493420815
Directory /workspace/33.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.lc_ctrl_volatile_unlock_smoke.791735495
Short name T33
Test name
Test status
Simulation time 45430676 ps
CPU time 0.91 seconds
Started Jun 07 07:31:26 PM PDT 24
Finished Jun 07 07:31:28 PM PDT 24
Peak memory 209584 kb
Host smart-f897213e-cf5f-4fd7-9461-eed83b01dc47
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791735495 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ct
rl_volatile_unlock_smoke.791735495
Directory /workspace/33.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_alert_test.2513273377
Short name T522
Test name
Test status
Simulation time 78915815 ps
CPU time 0.99 seconds
Started Jun 07 07:31:34 PM PDT 24
Finished Jun 07 07:31:36 PM PDT 24
Peak memory 209480 kb
Host smart-fd85f10d-57b0-466e-9a18-70b63440aa20
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513273377 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_alert_test.2513273377
Directory /workspace/34.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.lc_ctrl_errors.2265466140
Short name T716
Test name
Test status
Simulation time 1354049752 ps
CPU time 15.25 seconds
Started Jun 07 07:31:34 PM PDT 24
Finished Jun 07 07:31:51 PM PDT 24
Peak memory 218648 kb
Host smart-9c0011fc-da62-417a-bed1-dab946ed600f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265466140 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_errors.2265466140
Directory /workspace/34.lc_ctrl_errors/latest

Test location /workspace/coverage/default/34.lc_ctrl_jtag_access.805650389
Short name T697
Test name
Test status
Simulation time 72441603 ps
CPU time 2.74 seconds
Started Jun 07 07:31:37 PM PDT 24
Finished Jun 07 07:31:41 PM PDT 24
Peak memory 217568 kb
Host smart-2c7f41ff-16fe-4fc3-9817-5d0e13d43f8e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805650389 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_jtag_access.805650389
Directory /workspace/34.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/34.lc_ctrl_prog_failure.2015067724
Short name T242
Test name
Test status
Simulation time 686304340 ps
CPU time 3.47 seconds
Started Jun 07 07:31:34 PM PDT 24
Finished Jun 07 07:31:39 PM PDT 24
Peak memory 222952 kb
Host smart-91661443-8e9d-4fa3-9e14-b1a916990745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015067724 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_prog_failure.2015067724
Directory /workspace/34.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_mubi.2954077289
Short name T504
Test name
Test status
Simulation time 1816988536 ps
CPU time 14.11 seconds
Started Jun 07 07:31:34 PM PDT 24
Finished Jun 07 07:31:49 PM PDT 24
Peak memory 219388 kb
Host smart-010157fb-0343-4fe0-8983-7b47ae722a00
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954077289 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_mubi.2954077289
Directory /workspace/34.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_digest.879402006
Short name T699
Test name
Test status
Simulation time 2674656899 ps
CPU time 10.54 seconds
Started Jun 07 07:31:35 PM PDT 24
Finished Jun 07 07:31:48 PM PDT 24
Peak memory 218776 kb
Host smart-8e6317ec-b1ff-4c12-af44-0ede56460dc3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879402006 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_di
gest.879402006
Directory /workspace/34.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_mux.204717974
Short name T240
Test name
Test status
Simulation time 3908777277 ps
CPU time 9.24 seconds
Started Jun 07 07:31:36 PM PDT 24
Finished Jun 07 07:31:47 PM PDT 24
Peak memory 218788 kb
Host smart-2be68d86-9a70-4543-a684-fe2b3dbe0765
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204717974 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_mux.204717974
Directory /workspace/34.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/34.lc_ctrl_security_escalation.1652769251
Short name T533
Test name
Test status
Simulation time 1046824736 ps
CPU time 10.01 seconds
Started Jun 07 07:31:35 PM PDT 24
Finished Jun 07 07:31:47 PM PDT 24
Peak memory 226448 kb
Host smart-12ecab29-f21a-42e9-8ed6-d86067d8910f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652769251 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_security_escalation.1652769251
Directory /workspace/34.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/34.lc_ctrl_smoke.2749726263
Short name T568
Test name
Test status
Simulation time 201830764 ps
CPU time 2.81 seconds
Started Jun 07 07:31:27 PM PDT 24
Finished Jun 07 07:31:32 PM PDT 24
Peak memory 218228 kb
Host smart-ea9e19b2-fa32-4809-8464-7468b98e649a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749726263 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_smoke.2749726263
Directory /workspace/34.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_failure.4244232645
Short name T354
Test name
Test status
Simulation time 841802557 ps
CPU time 14.56 seconds
Started Jun 07 07:31:33 PM PDT 24
Finished Jun 07 07:31:49 PM PDT 24
Peak memory 251380 kb
Host smart-943aa564-646d-4795-b220-c3051ee06013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244232645 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_failure.4244232645
Directory /workspace/34.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_post_trans.2318884735
Short name T410
Test name
Test status
Simulation time 498307565 ps
CPU time 3.29 seconds
Started Jun 07 07:31:32 PM PDT 24
Finished Jun 07 07:31:36 PM PDT 24
Peak memory 226800 kb
Host smart-03329ad4-bbaa-40f5-9821-61613b086a14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318884735 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_post_trans.2318884735
Directory /workspace/34.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all.2655174661
Short name T734
Test name
Test status
Simulation time 6563749220 ps
CPU time 81.21 seconds
Started Jun 07 07:31:35 PM PDT 24
Finished Jun 07 07:32:57 PM PDT 24
Peak memory 251396 kb
Host smart-34e1451c-a001-4b65-a4b6-d8eb5d23269e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655174661 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.lc_ctrl_stress_all.2655174661
Directory /workspace/34.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all_with_rand_reset.2225121502
Short name T640
Test name
Test status
Simulation time 11775381610 ps
CPU time 126.19 seconds
Started Jun 07 07:31:35 PM PDT 24
Finished Jun 07 07:33:43 PM PDT 24
Peak memory 259892 kb
Host smart-18e1d6b3-1c4b-48ee-acea-ee3c8e65f896
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2225121502 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_stress_all_with_rand_reset.2225121502
Directory /workspace/34.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.lc_ctrl_volatile_unlock_smoke.115328725
Short name T718
Test name
Test status
Simulation time 14957420 ps
CPU time 1 seconds
Started Jun 07 07:31:26 PM PDT 24
Finished Jun 07 07:31:29 PM PDT 24
Peak memory 209484 kb
Host smart-cc0b0fd1-015d-4c1e-94e4-19dfb0f966a3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115328725 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ct
rl_volatile_unlock_smoke.115328725
Directory /workspace/34.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_alert_test.3905049645
Short name T319
Test name
Test status
Simulation time 79867735 ps
CPU time 1.15 seconds
Started Jun 07 07:31:36 PM PDT 24
Finished Jun 07 07:31:39 PM PDT 24
Peak memory 209512 kb
Host smart-c26ad76f-6ebe-49e8-ad92-24b83980a0a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905049645 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_alert_test.3905049645
Directory /workspace/35.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.lc_ctrl_errors.2030839381
Short name T281
Test name
Test status
Simulation time 2369588652 ps
CPU time 12.51 seconds
Started Jun 07 07:31:34 PM PDT 24
Finished Jun 07 07:31:48 PM PDT 24
Peak memory 219444 kb
Host smart-7e200af8-e683-4b68-b631-6da111027df7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030839381 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_errors.2030839381
Directory /workspace/35.lc_ctrl_errors/latest

Test location /workspace/coverage/default/35.lc_ctrl_jtag_access.4294195048
Short name T810
Test name
Test status
Simulation time 712824531 ps
CPU time 18.71 seconds
Started Jun 07 07:31:34 PM PDT 24
Finished Jun 07 07:31:55 PM PDT 24
Peak memory 217916 kb
Host smart-1f781ace-8afb-42d2-9837-43f163381640
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294195048 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_jtag_access.4294195048
Directory /workspace/35.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/35.lc_ctrl_prog_failure.3405023887
Short name T439
Test name
Test status
Simulation time 97319757 ps
CPU time 3.23 seconds
Started Jun 07 07:31:37 PM PDT 24
Finished Jun 07 07:31:42 PM PDT 24
Peak memory 222960 kb
Host smart-26ba9eb8-2152-46a1-a93d-8d88d1c841af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405023887 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_prog_failure.3405023887
Directory /workspace/35.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_mubi.1691056775
Short name T314
Test name
Test status
Simulation time 4271960694 ps
CPU time 13.61 seconds
Started Jun 07 07:31:37 PM PDT 24
Finished Jun 07 07:31:52 PM PDT 24
Peak memory 226588 kb
Host smart-fcf730dc-f282-4967-918c-84e7d5ce8917
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691056775 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_mubi.1691056775
Directory /workspace/35.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_digest.3915643342
Short name T863
Test name
Test status
Simulation time 1642032273 ps
CPU time 16.04 seconds
Started Jun 07 07:31:33 PM PDT 24
Finished Jun 07 07:31:51 PM PDT 24
Peak memory 218736 kb
Host smart-51135cf6-a7ae-4cf5-b4e5-2733765c8293
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915643342 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_d
igest.3915643342
Directory /workspace/35.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_mux.1773476451
Short name T649
Test name
Test status
Simulation time 487773687 ps
CPU time 11.66 seconds
Started Jun 07 07:31:37 PM PDT 24
Finished Jun 07 07:31:50 PM PDT 24
Peak memory 218724 kb
Host smart-78a375f3-5998-4b28-a4b7-fd0c40dfdb90
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773476451 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_mux.
1773476451
Directory /workspace/35.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/35.lc_ctrl_smoke.4138760048
Short name T589
Test name
Test status
Simulation time 44532997 ps
CPU time 1.75 seconds
Started Jun 07 07:31:33 PM PDT 24
Finished Jun 07 07:31:36 PM PDT 24
Peak memory 223812 kb
Host smart-06a01847-fb2f-4397-baee-018825e8114b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138760048 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_smoke.4138760048
Directory /workspace/35.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_failure.724768383
Short name T485
Test name
Test status
Simulation time 690481219 ps
CPU time 24.75 seconds
Started Jun 07 07:31:33 PM PDT 24
Finished Jun 07 07:31:59 PM PDT 24
Peak memory 251456 kb
Host smart-7a411a3d-323d-46e7-9144-d680d8250682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724768383 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_failure.724768383
Directory /workspace/35.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_post_trans.3695551691
Short name T348
Test name
Test status
Simulation time 73601215 ps
CPU time 7.39 seconds
Started Jun 07 07:31:35 PM PDT 24
Finished Jun 07 07:31:44 PM PDT 24
Peak memory 251464 kb
Host smart-cd31b0c0-0576-4b40-b231-44345f647004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695551691 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_post_trans.3695551691
Directory /workspace/35.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all.1775923140
Short name T377
Test name
Test status
Simulation time 7370183042 ps
CPU time 153.41 seconds
Started Jun 07 07:31:35 PM PDT 24
Finished Jun 07 07:34:10 PM PDT 24
Peak memory 276320 kb
Host smart-1209f19c-573e-45fc-98cc-035becd514ed
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775923140 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.lc_ctrl_stress_all.1775923140
Directory /workspace/35.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all_with_rand_reset.3790376085
Short name T46
Test name
Test status
Simulation time 72047972497 ps
CPU time 497.04 seconds
Started Jun 07 07:31:35 PM PDT 24
Finished Jun 07 07:39:54 PM PDT 24
Peak memory 373588 kb
Host smart-b00d0b32-587e-4cab-825a-7e20edabd991
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3790376085 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_stress_all_with_rand_reset.3790376085
Directory /workspace/35.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.lc_ctrl_volatile_unlock_smoke.545846811
Short name T731
Test name
Test status
Simulation time 12528635 ps
CPU time 0.84 seconds
Started Jun 07 07:31:35 PM PDT 24
Finished Jun 07 07:31:37 PM PDT 24
Peak memory 209316 kb
Host smart-02a0f9bf-5139-425d-b001-5d2f75ceb985
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545846811 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ct
rl_volatile_unlock_smoke.545846811
Directory /workspace/35.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_alert_test.707513507
Short name T760
Test name
Test status
Simulation time 56666444 ps
CPU time 0.87 seconds
Started Jun 07 07:31:41 PM PDT 24
Finished Jun 07 07:31:43 PM PDT 24
Peak memory 209368 kb
Host smart-26766e23-ef42-4da8-881b-dd3337696996
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707513507 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_alert_test.707513507
Directory /workspace/36.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.lc_ctrl_errors.515176660
Short name T517
Test name
Test status
Simulation time 794155738 ps
CPU time 13.65 seconds
Started Jun 07 07:31:39 PM PDT 24
Finished Jun 07 07:31:54 PM PDT 24
Peak memory 218752 kb
Host smart-a9fa4777-de16-4819-8f9f-7e0628bc2d8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515176660 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_errors.515176660
Directory /workspace/36.lc_ctrl_errors/latest

Test location /workspace/coverage/default/36.lc_ctrl_jtag_access.2644695824
Short name T770
Test name
Test status
Simulation time 2432400733 ps
CPU time 15.07 seconds
Started Jun 07 07:31:41 PM PDT 24
Finished Jun 07 07:31:58 PM PDT 24
Peak memory 218276 kb
Host smart-acb16ba5-2c99-4d2e-bc0a-bb2eec95bcd9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644695824 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_jtag_access.2644695824
Directory /workspace/36.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/36.lc_ctrl_prog_failure.571824262
Short name T449
Test name
Test status
Simulation time 868229464 ps
CPU time 3.98 seconds
Started Jun 07 07:31:38 PM PDT 24
Finished Jun 07 07:31:44 PM PDT 24
Peak memory 218684 kb
Host smart-2a3b023b-961a-4191-bbf4-e6a6550de819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571824262 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_prog_failure.571824262
Directory /workspace/36.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_mubi.2534500637
Short name T685
Test name
Test status
Simulation time 1295064553 ps
CPU time 18.42 seconds
Started Jun 07 07:31:40 PM PDT 24
Finished Jun 07 07:32:00 PM PDT 24
Peak memory 226512 kb
Host smart-379ab920-2f6a-493b-ac18-4e32e0a26ba0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534500637 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_mubi.2534500637
Directory /workspace/36.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_digest.3973348555
Short name T3
Test name
Test status
Simulation time 1100304513 ps
CPU time 12.93 seconds
Started Jun 07 07:31:40 PM PDT 24
Finished Jun 07 07:31:55 PM PDT 24
Peak memory 218728 kb
Host smart-620804fb-8a06-4a4f-a507-89b78a19eaee
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973348555 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_d
igest.3973348555
Directory /workspace/36.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_mux.1599146197
Short name T97
Test name
Test status
Simulation time 1047070977 ps
CPU time 8.89 seconds
Started Jun 07 07:31:37 PM PDT 24
Finished Jun 07 07:31:47 PM PDT 24
Peak memory 225252 kb
Host smart-a8ff3919-c6b5-430d-b084-b5c831d3b557
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599146197 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_mux.
1599146197
Directory /workspace/36.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/36.lc_ctrl_security_escalation.252447615
Short name T401
Test name
Test status
Simulation time 1469452906 ps
CPU time 10.09 seconds
Started Jun 07 07:31:39 PM PDT 24
Finished Jun 07 07:31:50 PM PDT 24
Peak memory 226536 kb
Host smart-90b9572f-7075-471c-9dd9-2b0e42351ad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252447615 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_security_escalation.252447615
Directory /workspace/36.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/36.lc_ctrl_smoke.1117288511
Short name T447
Test name
Test status
Simulation time 29561104 ps
CPU time 1.84 seconds
Started Jun 07 07:31:36 PM PDT 24
Finished Jun 07 07:31:40 PM PDT 24
Peak memory 218212 kb
Host smart-95c85d3e-402b-40c9-acef-d420e4d99bb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117288511 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_smoke.1117288511
Directory /workspace/36.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_failure.1078119672
Short name T451
Test name
Test status
Simulation time 558140022 ps
CPU time 28.86 seconds
Started Jun 07 07:31:39 PM PDT 24
Finished Jun 07 07:32:10 PM PDT 24
Peak memory 251396 kb
Host smart-0806e720-df68-49a7-8473-84caa7133161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078119672 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_failure.1078119672
Directory /workspace/36.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_post_trans.2377106138
Short name T324
Test name
Test status
Simulation time 586962879 ps
CPU time 6.77 seconds
Started Jun 07 07:31:40 PM PDT 24
Finished Jun 07 07:31:48 PM PDT 24
Peak memory 247656 kb
Host smart-bfa66bf7-7b2f-4e43-ac1b-d1d74e4bb3aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377106138 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_post_trans.2377106138
Directory /workspace/36.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all.1313049303
Short name T796
Test name
Test status
Simulation time 3048223584 ps
CPU time 86.21 seconds
Started Jun 07 07:31:42 PM PDT 24
Finished Jun 07 07:33:09 PM PDT 24
Peak memory 259672 kb
Host smart-49033c74-7bdf-4c13-b037-045eb94dba0a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313049303 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.lc_ctrl_stress_all.1313049303
Directory /workspace/36.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.lc_ctrl_volatile_unlock_smoke.3487342169
Short name T690
Test name
Test status
Simulation time 39275931 ps
CPU time 0.89 seconds
Started Jun 07 07:31:36 PM PDT 24
Finished Jun 07 07:31:39 PM PDT 24
Peak memory 212384 kb
Host smart-bf0f92ac-a906-46ce-8db4-0aec05b50698
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487342169 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_c
trl_volatile_unlock_smoke.3487342169
Directory /workspace/36.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_alert_test.816328792
Short name T597
Test name
Test status
Simulation time 39881683 ps
CPU time 1.2 seconds
Started Jun 07 07:31:44 PM PDT 24
Finished Jun 07 07:31:46 PM PDT 24
Peak memory 209428 kb
Host smart-91330bef-c0ec-4a0d-8cf9-f13c7097245e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816328792 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_alert_test.816328792
Directory /workspace/37.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.lc_ctrl_errors.1079750502
Short name T391
Test name
Test status
Simulation time 208342295 ps
CPU time 10.93 seconds
Started Jun 07 07:31:40 PM PDT 24
Finished Jun 07 07:31:52 PM PDT 24
Peak memory 218636 kb
Host smart-fd0b7ebd-2903-4fd7-87f2-29598bc55bb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079750502 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_errors.1079750502
Directory /workspace/37.lc_ctrl_errors/latest

Test location /workspace/coverage/default/37.lc_ctrl_jtag_access.881224486
Short name T29
Test name
Test status
Simulation time 1807798830 ps
CPU time 21.85 seconds
Started Jun 07 07:31:39 PM PDT 24
Finished Jun 07 07:32:02 PM PDT 24
Peak memory 217868 kb
Host smart-eec895c2-cfc5-4418-bc05-113fef792981
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881224486 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_jtag_access.881224486
Directory /workspace/37.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/37.lc_ctrl_prog_failure.2275598214
Short name T632
Test name
Test status
Simulation time 77046867 ps
CPU time 3.86 seconds
Started Jun 07 07:31:39 PM PDT 24
Finished Jun 07 07:31:45 PM PDT 24
Peak memory 222952 kb
Host smart-538a3cb6-2093-401f-bebd-3f962a89ad13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275598214 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_prog_failure.2275598214
Directory /workspace/37.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_mubi.3429863876
Short name T663
Test name
Test status
Simulation time 1833890176 ps
CPU time 19.63 seconds
Started Jun 07 07:31:39 PM PDT 24
Finished Jun 07 07:32:00 PM PDT 24
Peak memory 226544 kb
Host smart-1f30232a-ddc8-479f-9df5-075c3bac25df
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429863876 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_mubi.3429863876
Directory /workspace/37.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_digest.565744712
Short name T307
Test name
Test status
Simulation time 1731248328 ps
CPU time 13.82 seconds
Started Jun 07 07:31:41 PM PDT 24
Finished Jun 07 07:31:56 PM PDT 24
Peak memory 218700 kb
Host smart-c5861473-e1a8-47cb-af9f-0dbe5c98670c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565744712 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_di
gest.565744712
Directory /workspace/37.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_mux.660677859
Short name T791
Test name
Test status
Simulation time 209882907 ps
CPU time 6.78 seconds
Started Jun 07 07:31:41 PM PDT 24
Finished Jun 07 07:31:49 PM PDT 24
Peak memory 226568 kb
Host smart-671b0d3f-bd71-4667-9d36-95916c01f522
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660677859 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_mux.660677859
Directory /workspace/37.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/37.lc_ctrl_security_escalation.2462748860
Short name T752
Test name
Test status
Simulation time 911530920 ps
CPU time 9.08 seconds
Started Jun 07 07:31:38 PM PDT 24
Finished Jun 07 07:31:48 PM PDT 24
Peak memory 226512 kb
Host smart-e13e8f02-e41f-4a63-a982-4beedd7af550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462748860 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_security_escalation.2462748860
Directory /workspace/37.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/37.lc_ctrl_smoke.1250876505
Short name T509
Test name
Test status
Simulation time 48144127 ps
CPU time 3.49 seconds
Started Jun 07 07:31:41 PM PDT 24
Finished Jun 07 07:31:46 PM PDT 24
Peak memory 215348 kb
Host smart-fd8615d7-92aa-4d7f-99b4-f4f8e8109032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250876505 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_smoke.1250876505
Directory /workspace/37.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_failure.1652794294
Short name T96
Test name
Test status
Simulation time 956739873 ps
CPU time 18.01 seconds
Started Jun 07 07:31:38 PM PDT 24
Finished Jun 07 07:31:57 PM PDT 24
Peak memory 251416 kb
Host smart-37871c22-4ac1-4de5-8503-6f8d4d8bad3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652794294 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_failure.1652794294
Directory /workspace/37.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_post_trans.3635833547
Short name T266
Test name
Test status
Simulation time 63608487 ps
CPU time 7.14 seconds
Started Jun 07 07:31:37 PM PDT 24
Finished Jun 07 07:31:45 PM PDT 24
Peak memory 250932 kb
Host smart-b8dda6fa-f825-4d82-91e1-8d2e853c538a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635833547 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_post_trans.3635833547
Directory /workspace/37.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all.1526108732
Short name T622
Test name
Test status
Simulation time 2962056187 ps
CPU time 82.09 seconds
Started Jun 07 07:31:38 PM PDT 24
Finished Jun 07 07:33:02 PM PDT 24
Peak memory 269052 kb
Host smart-15d3e1b5-7a55-4522-abc3-9a5be5c3955f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526108732 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.lc_ctrl_stress_all.1526108732
Directory /workspace/37.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all_with_rand_reset.4224753221
Short name T704
Test name
Test status
Simulation time 50457508668 ps
CPU time 220.44 seconds
Started Jun 07 07:31:41 PM PDT 24
Finished Jun 07 07:35:23 PM PDT 24
Peak memory 259496 kb
Host smart-493d5e6f-d7eb-4dd9-b321-464364f5d2ec
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4224753221 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_stress_all_with_rand_reset.4224753221
Directory /workspace/37.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.lc_ctrl_volatile_unlock_smoke.2253688749
Short name T388
Test name
Test status
Simulation time 19588926 ps
CPU time 0.83 seconds
Started Jun 07 07:31:37 PM PDT 24
Finished Jun 07 07:31:39 PM PDT 24
Peak memory 209340 kb
Host smart-8751e4de-f025-4c83-8321-d12f2250e02d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253688749 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_c
trl_volatile_unlock_smoke.2253688749
Directory /workspace/37.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_alert_test.3870022636
Short name T356
Test name
Test status
Simulation time 21612345 ps
CPU time 1.41 seconds
Started Jun 07 07:31:43 PM PDT 24
Finished Jun 07 07:31:46 PM PDT 24
Peak memory 209492 kb
Host smart-a6b4a5cb-b352-4b3f-b6ca-c91e962a42df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870022636 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_alert_test.3870022636
Directory /workspace/38.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.lc_ctrl_errors.265115862
Short name T840
Test name
Test status
Simulation time 432005108 ps
CPU time 10.56 seconds
Started Jun 07 07:31:43 PM PDT 24
Finished Jun 07 07:31:55 PM PDT 24
Peak memory 218656 kb
Host smart-f49e12ab-c7c2-4717-b2be-4a8917a0bb44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265115862 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_errors.265115862
Directory /workspace/38.lc_ctrl_errors/latest

Test location /workspace/coverage/default/38.lc_ctrl_jtag_access.3566344312
Short name T425
Test name
Test status
Simulation time 451067317 ps
CPU time 11.49 seconds
Started Jun 07 07:31:45 PM PDT 24
Finished Jun 07 07:31:58 PM PDT 24
Peak memory 218044 kb
Host smart-1f59eba3-0ec3-4ca6-9a77-88ddc1599ad2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566344312 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_jtag_access.3566344312
Directory /workspace/38.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/38.lc_ctrl_prog_failure.3299373094
Short name T433
Test name
Test status
Simulation time 77432908 ps
CPU time 1.58 seconds
Started Jun 07 07:31:45 PM PDT 24
Finished Jun 07 07:31:48 PM PDT 24
Peak memory 218708 kb
Host smart-feaed0db-76a3-48e3-ac64-fdafdeebccc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299373094 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_prog_failure.3299373094
Directory /workspace/38.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_mubi.3665244727
Short name T534
Test name
Test status
Simulation time 207401089 ps
CPU time 10.7 seconds
Started Jun 07 07:31:42 PM PDT 24
Finished Jun 07 07:31:54 PM PDT 24
Peak memory 219364 kb
Host smart-8d917be9-9fc9-45d6-98c2-4bf8c8cc76e1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665244727 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_mubi.3665244727
Directory /workspace/38.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_digest.4203567630
Short name T380
Test name
Test status
Simulation time 832668873 ps
CPU time 12.13 seconds
Started Jun 07 07:31:46 PM PDT 24
Finished Jun 07 07:32:00 PM PDT 24
Peak memory 226512 kb
Host smart-a0c1e9db-682a-4617-93f3-d17ec3050e8a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203567630 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_d
igest.4203567630
Directory /workspace/38.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_mux.1024883552
Short name T180
Test name
Test status
Simulation time 877086327 ps
CPU time 11.32 seconds
Started Jun 07 07:31:42 PM PDT 24
Finished Jun 07 07:31:55 PM PDT 24
Peak memory 218748 kb
Host smart-217ea29b-a704-4610-8d10-ffc48825bc03
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024883552 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_mux.
1024883552
Directory /workspace/38.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/38.lc_ctrl_smoke.4038308894
Short name T370
Test name
Test status
Simulation time 54503852 ps
CPU time 2.45 seconds
Started Jun 07 07:31:41 PM PDT 24
Finished Jun 07 07:31:45 PM PDT 24
Peak memory 218192 kb
Host smart-7001cba3-ae5c-4cc3-b55c-9f437b3b863e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038308894 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_smoke.4038308894
Directory /workspace/38.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_failure.4214420987
Short name T682
Test name
Test status
Simulation time 3703830114 ps
CPU time 21.16 seconds
Started Jun 07 07:31:42 PM PDT 24
Finished Jun 07 07:32:05 PM PDT 24
Peak memory 251492 kb
Host smart-103ee9a1-10ea-4a61-93d1-18f05ed4e66b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214420987 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_failure.4214420987
Directory /workspace/38.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_post_trans.2083356521
Short name T11
Test name
Test status
Simulation time 155790164 ps
CPU time 3.14 seconds
Started Jun 07 07:31:41 PM PDT 24
Finished Jun 07 07:31:46 PM PDT 24
Peak memory 223028 kb
Host smart-d502ace7-0286-4ceb-ae78-4e00d7b38ffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083356521 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_post_trans.2083356521
Directory /workspace/38.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all.3161006926
Short name T737
Test name
Test status
Simulation time 16422477149 ps
CPU time 64.55 seconds
Started Jun 07 07:31:49 PM PDT 24
Finished Jun 07 07:32:54 PM PDT 24
Peak memory 274940 kb
Host smart-9e0a079b-c6fa-46b2-b222-c80cd5914f7a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161006926 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.lc_ctrl_stress_all.3161006926
Directory /workspace/38.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.lc_ctrl_volatile_unlock_smoke.3153950548
Short name T755
Test name
Test status
Simulation time 12932550 ps
CPU time 0.89 seconds
Started Jun 07 07:31:41 PM PDT 24
Finished Jun 07 07:31:43 PM PDT 24
Peak memory 212280 kb
Host smart-62735147-2c18-42e8-ba36-81d00c6f0021
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153950548 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_c
trl_volatile_unlock_smoke.3153950548
Directory /workspace/38.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_alert_test.1427817840
Short name T784
Test name
Test status
Simulation time 16867120 ps
CPU time 0.9 seconds
Started Jun 07 07:32:08 PM PDT 24
Finished Jun 07 07:32:13 PM PDT 24
Peak memory 209404 kb
Host smart-081783ee-4efa-417d-a574-845440707c2e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427817840 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_alert_test.1427817840
Directory /workspace/39.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.lc_ctrl_errors.3398762238
Short name T325
Test name
Test status
Simulation time 383730564 ps
CPU time 10.59 seconds
Started Jun 07 07:31:47 PM PDT 24
Finished Jun 07 07:31:59 PM PDT 24
Peak memory 218652 kb
Host smart-655bd038-1827-45cd-95b9-2c0722255dc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398762238 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_errors.3398762238
Directory /workspace/39.lc_ctrl_errors/latest

Test location /workspace/coverage/default/39.lc_ctrl_jtag_access.3654146683
Short name T556
Test name
Test status
Simulation time 1121742924 ps
CPU time 3.88 seconds
Started Jun 07 07:32:09 PM PDT 24
Finished Jun 07 07:32:16 PM PDT 24
Peak memory 217644 kb
Host smart-99e5fc97-d87a-44f1-9a0f-62df661443b6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654146683 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_jtag_access.3654146683
Directory /workspace/39.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/39.lc_ctrl_prog_failure.3025713885
Short name T512
Test name
Test status
Simulation time 64840364 ps
CPU time 2.45 seconds
Started Jun 07 07:31:44 PM PDT 24
Finished Jun 07 07:31:48 PM PDT 24
Peak memory 218712 kb
Host smart-4756a14f-37f2-4276-9422-0e8a727131ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025713885 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_prog_failure.3025713885
Directory /workspace/39.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_mubi.1557163303
Short name T175
Test name
Test status
Simulation time 478300255 ps
CPU time 10.07 seconds
Started Jun 07 07:32:08 PM PDT 24
Finished Jun 07 07:32:21 PM PDT 24
Peak memory 219364 kb
Host smart-01c4dcdb-c2fe-41a3-af84-a280673ad6c1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557163303 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_mubi.1557163303
Directory /workspace/39.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_digest.4287300670
Short name T275
Test name
Test status
Simulation time 1153390363 ps
CPU time 8.98 seconds
Started Jun 07 07:32:07 PM PDT 24
Finished Jun 07 07:32:18 PM PDT 24
Peak memory 226524 kb
Host smart-b00c4545-e7e4-438d-9cfd-acd6b6c1c850
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287300670 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_d
igest.4287300670
Directory /workspace/39.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_mux.3142620576
Short name T272
Test name
Test status
Simulation time 10305941242 ps
CPU time 12.54 seconds
Started Jun 07 07:32:07 PM PDT 24
Finished Jun 07 07:32:21 PM PDT 24
Peak memory 226560 kb
Host smart-afe83fae-463e-49e1-af3a-e76987db8a84
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142620576 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_mux.
3142620576
Directory /workspace/39.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/39.lc_ctrl_security_escalation.2261244274
Short name T625
Test name
Test status
Simulation time 761399222 ps
CPU time 6.63 seconds
Started Jun 07 07:32:07 PM PDT 24
Finished Jun 07 07:32:16 PM PDT 24
Peak memory 225028 kb
Host smart-6ec9e020-bcc3-44f7-ac33-b80b6c101769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261244274 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_security_escalation.2261244274
Directory /workspace/39.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/39.lc_ctrl_smoke.3531889952
Short name T553
Test name
Test status
Simulation time 649728762 ps
CPU time 10.67 seconds
Started Jun 07 07:31:45 PM PDT 24
Finished Jun 07 07:31:57 PM PDT 24
Peak memory 218224 kb
Host smart-38a60186-329c-45dc-af98-30bc1aceb1b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531889952 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_smoke.3531889952
Directory /workspace/39.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_failure.2940337933
Short name T684
Test name
Test status
Simulation time 1391137983 ps
CPU time 26.8 seconds
Started Jun 07 07:31:45 PM PDT 24
Finished Jun 07 07:32:13 PM PDT 24
Peak memory 251432 kb
Host smart-7b92bb7c-d178-4453-95e6-a65863f8b5e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940337933 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_failure.2940337933
Directory /workspace/39.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_post_trans.1041911268
Short name T231
Test name
Test status
Simulation time 288793427 ps
CPU time 7.04 seconds
Started Jun 07 07:31:54 PM PDT 24
Finished Jun 07 07:32:02 PM PDT 24
Peak memory 247068 kb
Host smart-c3db8882-b2aa-42ad-bb50-5e5fac8ea7f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041911268 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_post_trans.1041911268
Directory /workspace/39.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all.257474070
Short name T575
Test name
Test status
Simulation time 4489494291 ps
CPU time 85.32 seconds
Started Jun 07 07:32:07 PM PDT 24
Finished Jun 07 07:33:35 PM PDT 24
Peak memory 251440 kb
Host smart-29697d86-8ab5-4976-999b-2c216eb8b2e5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257474070 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.lc_ctrl_stress_all.257474070
Directory /workspace/39.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.lc_ctrl_volatile_unlock_smoke.1996025284
Short name T34
Test name
Test status
Simulation time 42141457 ps
CPU time 0.76 seconds
Started Jun 07 07:31:45 PM PDT 24
Finished Jun 07 07:31:47 PM PDT 24
Peak memory 209368 kb
Host smart-34929844-f551-46e3-862c-4a28da3b627e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996025284 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_c
trl_volatile_unlock_smoke.1996025284
Directory /workspace/39.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_alert_test.1639809477
Short name T478
Test name
Test status
Simulation time 296092977 ps
CPU time 0.89 seconds
Started Jun 07 07:29:25 PM PDT 24
Finished Jun 07 07:29:29 PM PDT 24
Peak memory 209472 kb
Host smart-4f808363-b130-4366-bf9d-a7fa546a3544
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639809477 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_alert_test.1639809477
Directory /workspace/4.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.lc_ctrl_errors.3434876845
Short name T302
Test name
Test status
Simulation time 297578967 ps
CPU time 11.08 seconds
Started Jun 07 07:29:22 PM PDT 24
Finished Jun 07 07:29:36 PM PDT 24
Peak memory 218868 kb
Host smart-ea4f60ae-8019-4727-9c81-bd65d80952b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434876845 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_errors.3434876845
Directory /workspace/4.lc_ctrl_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_errors.1823450453
Short name T163
Test name
Test status
Simulation time 14155011234 ps
CPU time 40.92 seconds
Started Jun 07 07:29:28 PM PDT 24
Finished Jun 07 07:30:13 PM PDT 24
Peak memory 219252 kb
Host smart-9a76bd6d-75e9-4b7e-88b8-028dd17c00dc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823450453 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_er
rors.1823450453
Directory /workspace/4.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_priority.3245832022
Short name T653
Test name
Test status
Simulation time 71498502 ps
CPU time 1.59 seconds
Started Jun 07 07:29:27 PM PDT 24
Finished Jun 07 07:29:32 PM PDT 24
Peak memory 217840 kb
Host smart-cacf9a57-9d24-478e-ab29-799049a05c10
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245832022 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_priority.3
245832022
Directory /workspace/4.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_prog_failure.1351060218
Short name T536
Test name
Test status
Simulation time 546918046 ps
CPU time 2.07 seconds
Started Jun 07 07:29:28 PM PDT 24
Finished Jun 07 07:29:34 PM PDT 24
Peak memory 218752 kb
Host smart-2f844e6c-5f9b-4dcb-bb94-f6efbb0f8f20
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351060218 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag
_prog_failure.1351060218
Directory /workspace/4.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_regwen_during_op.3414199700
Short name T74
Test name
Test status
Simulation time 1010668617 ps
CPU time 14.51 seconds
Started Jun 07 07:29:27 PM PDT 24
Finished Jun 07 07:29:45 PM PDT 24
Peak memory 218148 kb
Host smart-1721ea14-4c4b-464b-b824-88b95664ca7b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414199700 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_regwen_during_op.3414199700
Directory /workspace/4.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_smoke.1584837186
Short name T6
Test name
Test status
Simulation time 437474870 ps
CPU time 3.67 seconds
Started Jun 07 07:29:26 PM PDT 24
Finished Jun 07 07:29:34 PM PDT 24
Peak memory 218244 kb
Host smart-f47d5c14-1baa-4eab-ae51-882426dcca95
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584837186 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_smoke.
1584837186
Directory /workspace/4.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_failure.626735629
Short name T358
Test name
Test status
Simulation time 5184216493 ps
CPU time 55.38 seconds
Started Jun 07 07:29:25 PM PDT 24
Finished Jun 07 07:30:24 PM PDT 24
Peak memory 280020 kb
Host smart-24102228-cad3-42ed-8378-4e357cefec92
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626735629 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag
_state_failure.626735629
Directory /workspace/4.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_post_trans.143460081
Short name T431
Test name
Test status
Simulation time 972476563 ps
CPU time 20.38 seconds
Started Jun 07 07:29:29 PM PDT 24
Finished Jun 07 07:29:53 PM PDT 24
Peak memory 251336 kb
Host smart-01784f03-0488-40df-88e0-2393f1f23309
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143460081 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_j
tag_state_post_trans.143460081
Directory /workspace/4.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_prog_failure.2871247273
Short name T217
Test name
Test status
Simulation time 149595021 ps
CPU time 3.47 seconds
Started Jun 07 07:29:26 PM PDT 24
Finished Jun 07 07:29:33 PM PDT 24
Peak memory 218684 kb
Host smart-fc3661c9-b0a9-4583-a67c-bd4049f67db5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871247273 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_prog_failure.2871247273
Directory /workspace/4.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_regwen_during_op.3104685318
Short name T64
Test name
Test status
Simulation time 815226963 ps
CPU time 10.35 seconds
Started Jun 07 07:29:30 PM PDT 24
Finished Jun 07 07:29:44 PM PDT 24
Peak memory 218208 kb
Host smart-3652ff31-cea9-4301-b374-91bc98962f0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104685318 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_regwen_during_op.3104685318
Directory /workspace/4.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_cm.122019925
Short name T86
Test name
Test status
Simulation time 216017447 ps
CPU time 34.28 seconds
Started Jun 07 07:29:28 PM PDT 24
Finished Jun 07 07:30:06 PM PDT 24
Peak memory 270268 kb
Host smart-11550fd5-99e9-4032-93b1-33a3aa336776
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122019925 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_cm.122019925
Directory /workspace/4.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_digest.1384444935
Short name T169
Test name
Test status
Simulation time 1673392087 ps
CPU time 12.93 seconds
Started Jun 07 07:29:24 PM PDT 24
Finished Jun 07 07:29:39 PM PDT 24
Peak memory 218732 kb
Host smart-addb690f-c301-4862-9d45-4e819e0069c2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384444935 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_di
gest.1384444935
Directory /workspace/4.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_mux.1339958491
Short name T277
Test name
Test status
Simulation time 1353700609 ps
CPU time 6.28 seconds
Started Jun 07 07:29:27 PM PDT 24
Finished Jun 07 07:29:37 PM PDT 24
Peak memory 218720 kb
Host smart-33e3477b-2d03-4fb4-a442-e3885e154107
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339958491 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_mux.1
339958491
Directory /workspace/4.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/4.lc_ctrl_security_escalation.1819905091
Short name T402
Test name
Test status
Simulation time 1189063693 ps
CPU time 8.1 seconds
Started Jun 07 07:29:31 PM PDT 24
Finished Jun 07 07:29:43 PM PDT 24
Peak memory 224976 kb
Host smart-72cc443f-c6cc-4370-ab8e-4395c5634916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819905091 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_security_escalation.1819905091
Directory /workspace/4.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/4.lc_ctrl_smoke.1560739873
Short name T440
Test name
Test status
Simulation time 102102460 ps
CPU time 1.73 seconds
Started Jun 07 07:29:25 PM PDT 24
Finished Jun 07 07:29:29 PM PDT 24
Peak memory 218204 kb
Host smart-0074606c-61d6-4d81-887c-1f19b13c567f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560739873 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_smoke.1560739873
Directory /workspace/4.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_failure.1326867006
Short name T673
Test name
Test status
Simulation time 470661864 ps
CPU time 23.46 seconds
Started Jun 07 07:29:25 PM PDT 24
Finished Jun 07 07:29:51 PM PDT 24
Peak memory 251408 kb
Host smart-6fcca454-d902-497e-8c79-71c6d1fe94a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326867006 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_failure.1326867006
Directory /workspace/4.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_post_trans.2647246993
Short name T768
Test name
Test status
Simulation time 58676693 ps
CPU time 3.52 seconds
Started Jun 07 07:29:24 PM PDT 24
Finished Jun 07 07:29:31 PM PDT 24
Peak memory 218576 kb
Host smart-f37dd780-19c5-4d12-bcab-9fc15eaee706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647246993 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_post_trans.2647246993
Directory /workspace/4.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_stress_all_with_rand_reset.2715504683
Short name T94
Test name
Test status
Simulation time 33700777388 ps
CPU time 1216.42 seconds
Started Jun 07 07:29:25 PM PDT 24
Finished Jun 07 07:49:45 PM PDT 24
Peak memory 448024 kb
Host smart-f81d4aa7-220c-48ca-8f7f-5e2e4663b6b9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2715504683 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_stress_all_with_rand_reset.2715504683
Directory /workspace/4.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.lc_ctrl_volatile_unlock_smoke.787447063
Short name T612
Test name
Test status
Simulation time 46988485 ps
CPU time 1.04 seconds
Started Jun 07 07:29:25 PM PDT 24
Finished Jun 07 07:29:29 PM PDT 24
Peak memory 213304 kb
Host smart-01ee6fa4-4328-4d61-9f7a-e1fd96dc1124
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787447063 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctr
l_volatile_unlock_smoke.787447063
Directory /workspace/4.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_alert_test.761325493
Short name T763
Test name
Test status
Simulation time 18319612 ps
CPU time 1.1 seconds
Started Jun 07 07:32:10 PM PDT 24
Finished Jun 07 07:32:15 PM PDT 24
Peak memory 209400 kb
Host smart-ae9ae577-a2cf-4b6f-83ce-c9e56cde2782
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761325493 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_alert_test.761325493
Directory /workspace/40.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.lc_ctrl_errors.3826997724
Short name T860
Test name
Test status
Simulation time 440687296 ps
CPU time 19.59 seconds
Started Jun 07 07:32:08 PM PDT 24
Finished Jun 07 07:32:30 PM PDT 24
Peak memory 218636 kb
Host smart-4c8884d4-65eb-4325-94fe-d428f5b26d0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826997724 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_errors.3826997724
Directory /workspace/40.lc_ctrl_errors/latest

Test location /workspace/coverage/default/40.lc_ctrl_jtag_access.1593401393
Short name T724
Test name
Test status
Simulation time 1887365842 ps
CPU time 5.12 seconds
Started Jun 07 07:32:12 PM PDT 24
Finished Jun 07 07:32:22 PM PDT 24
Peak memory 217916 kb
Host smart-38e9a154-9dc8-4888-ab66-29db0bfc921c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593401393 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_jtag_access.1593401393
Directory /workspace/40.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/40.lc_ctrl_prog_failure.657303792
Short name T101
Test name
Test status
Simulation time 286210447 ps
CPU time 3.38 seconds
Started Jun 07 07:32:11 PM PDT 24
Finished Jun 07 07:32:19 PM PDT 24
Peak memory 218656 kb
Host smart-69a7bef1-15ca-4aa1-b355-00c9e7790484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657303792 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_prog_failure.657303792
Directory /workspace/40.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_mubi.3620698450
Short name T373
Test name
Test status
Simulation time 1560210760 ps
CPU time 16.46 seconds
Started Jun 07 07:32:08 PM PDT 24
Finished Jun 07 07:32:27 PM PDT 24
Peak memory 218848 kb
Host smart-eca6b2b2-dd1b-4174-ae80-8bc7d23b8fd8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620698450 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_mubi.3620698450
Directory /workspace/40.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_digest.630842781
Short name T436
Test name
Test status
Simulation time 303841533 ps
CPU time 8.68 seconds
Started Jun 07 07:32:14 PM PDT 24
Finished Jun 07 07:32:27 PM PDT 24
Peak memory 226496 kb
Host smart-c24a135e-a97a-4213-bdb7-b4e795db27d2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630842781 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_di
gest.630842781
Directory /workspace/40.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_mux.1071263365
Short name T785
Test name
Test status
Simulation time 457780722 ps
CPU time 7.36 seconds
Started Jun 07 07:32:10 PM PDT 24
Finished Jun 07 07:32:22 PM PDT 24
Peak memory 218764 kb
Host smart-2b92018b-9e9d-4804-b011-c7ee0f5369a9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071263365 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_mux.
1071263365
Directory /workspace/40.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/40.lc_ctrl_security_escalation.500918635
Short name T214
Test name
Test status
Simulation time 349424161 ps
CPU time 8.81 seconds
Started Jun 07 07:32:10 PM PDT 24
Finished Jun 07 07:32:22 PM PDT 24
Peak memory 225208 kb
Host smart-2cedc94c-b70b-48a8-b86e-270dca9815ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500918635 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_security_escalation.500918635
Directory /workspace/40.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/40.lc_ctrl_smoke.2482768497
Short name T627
Test name
Test status
Simulation time 147599026 ps
CPU time 2.09 seconds
Started Jun 07 07:32:08 PM PDT 24
Finished Jun 07 07:32:13 PM PDT 24
Peak memory 214940 kb
Host smart-22a7b7b6-f796-4719-bfc0-2d1c5aae28f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482768497 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_smoke.2482768497
Directory /workspace/40.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_failure.2028692071
Short name T549
Test name
Test status
Simulation time 1396611244 ps
CPU time 23.72 seconds
Started Jun 07 07:32:11 PM PDT 24
Finished Jun 07 07:32:39 PM PDT 24
Peak memory 251368 kb
Host smart-37b9a463-4b6b-4e34-8c23-a68bba7f7789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028692071 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_failure.2028692071
Directory /workspace/40.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_post_trans.1677268414
Short name T104
Test name
Test status
Simulation time 333538442 ps
CPU time 9.9 seconds
Started Jun 07 07:32:11 PM PDT 24
Finished Jun 07 07:32:25 PM PDT 24
Peak memory 251444 kb
Host smart-f98c7475-e5e4-48e8-87bb-9a184f0f76bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677268414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_post_trans.1677268414
Directory /workspace/40.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/40.lc_ctrl_stress_all.4230207940
Short name T91
Test name
Test status
Simulation time 2547850868 ps
CPU time 49.1 seconds
Started Jun 07 07:32:10 PM PDT 24
Finished Jun 07 07:33:02 PM PDT 24
Peak memory 251496 kb
Host smart-e9b2a22a-fa54-4f6c-aa33-a552b5e37381
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230207940 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.lc_ctrl_stress_all.4230207940
Directory /workspace/40.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.lc_ctrl_volatile_unlock_smoke.2416691547
Short name T110
Test name
Test status
Simulation time 22032606 ps
CPU time 0.93 seconds
Started Jun 07 07:32:10 PM PDT 24
Finished Jun 07 07:32:16 PM PDT 24
Peak memory 212260 kb
Host smart-7dc3e2eb-bc25-4a03-8e37-8f124735ac82
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416691547 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_c
trl_volatile_unlock_smoke.2416691547
Directory /workspace/40.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_alert_test.150989179
Short name T708
Test name
Test status
Simulation time 57170199 ps
CPU time 0.97 seconds
Started Jun 07 07:32:11 PM PDT 24
Finished Jun 07 07:32:17 PM PDT 24
Peak memory 209320 kb
Host smart-f9a4668f-6bd8-44d4-878a-1bb10feab0ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150989179 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_alert_test.150989179
Directory /workspace/41.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.lc_ctrl_errors.889226573
Short name T396
Test name
Test status
Simulation time 261048860 ps
CPU time 13.66 seconds
Started Jun 07 07:32:12 PM PDT 24
Finished Jun 07 07:32:30 PM PDT 24
Peak memory 218716 kb
Host smart-045070c4-e74f-4a60-be3d-a07f3cfb8e99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889226573 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_errors.889226573
Directory /workspace/41.lc_ctrl_errors/latest

Test location /workspace/coverage/default/41.lc_ctrl_jtag_access.795617903
Short name T733
Test name
Test status
Simulation time 107713442 ps
CPU time 3.24 seconds
Started Jun 07 07:32:14 PM PDT 24
Finished Jun 07 07:32:22 PM PDT 24
Peak memory 217660 kb
Host smart-2401d024-4de1-4b55-ac3d-9f2e55726085
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795617903 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_jtag_access.795617903
Directory /workspace/41.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/41.lc_ctrl_prog_failure.377777635
Short name T244
Test name
Test status
Simulation time 397187185 ps
CPU time 6.28 seconds
Started Jun 07 07:32:07 PM PDT 24
Finished Jun 07 07:32:16 PM PDT 24
Peak memory 218668 kb
Host smart-d391fbfa-dccc-4884-979e-8cadcc3b3081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377777635 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_prog_failure.377777635
Directory /workspace/41.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_mubi.233063672
Short name T802
Test name
Test status
Simulation time 2086498996 ps
CPU time 11.86 seconds
Started Jun 07 07:32:13 PM PDT 24
Finished Jun 07 07:32:30 PM PDT 24
Peak memory 226544 kb
Host smart-d55abf8c-97f2-4df0-a1ab-79d664e2c193
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233063672 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_mubi.233063672
Directory /workspace/41.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_digest.323548958
Short name T701
Test name
Test status
Simulation time 1551373118 ps
CPU time 15.75 seconds
Started Jun 07 07:32:12 PM PDT 24
Finished Jun 07 07:32:33 PM PDT 24
Peak memory 218692 kb
Host smart-c820255d-82be-47e0-80ad-f6e0fbd1ebda
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323548958 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_di
gest.323548958
Directory /workspace/41.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_mux.2209904957
Short name T239
Test name
Test status
Simulation time 1114817972 ps
CPU time 11.08 seconds
Started Jun 07 07:32:13 PM PDT 24
Finished Jun 07 07:32:29 PM PDT 24
Peak memory 226536 kb
Host smart-ccf7d874-6157-4ce1-ab92-9eef4cc0f377
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209904957 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_mux.
2209904957
Directory /workspace/41.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/41.lc_ctrl_security_escalation.163307873
Short name T338
Test name
Test status
Simulation time 504224496 ps
CPU time 10.74 seconds
Started Jun 07 07:32:11 PM PDT 24
Finished Jun 07 07:32:26 PM PDT 24
Peak memory 226532 kb
Host smart-2fbddae3-c685-423a-9ea9-6cab57fc9cd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163307873 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_security_escalation.163307873
Directory /workspace/41.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/41.lc_ctrl_smoke.2357839545
Short name T279
Test name
Test status
Simulation time 167682878 ps
CPU time 1.84 seconds
Started Jun 07 07:32:15 PM PDT 24
Finished Jun 07 07:32:22 PM PDT 24
Peak memory 214496 kb
Host smart-de23ba83-f2a4-4d13-9720-0f29e7db402a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357839545 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_smoke.2357839545
Directory /workspace/41.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_failure.2620141279
Short name T585
Test name
Test status
Simulation time 1092898978 ps
CPU time 24.67 seconds
Started Jun 07 07:32:11 PM PDT 24
Finished Jun 07 07:32:40 PM PDT 24
Peak memory 251472 kb
Host smart-190d7457-440c-45a8-9017-469ef15550d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620141279 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_failure.2620141279
Directory /workspace/41.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_post_trans.3009186689
Short name T494
Test name
Test status
Simulation time 52885474 ps
CPU time 6.27 seconds
Started Jun 07 07:32:18 PM PDT 24
Finished Jun 07 07:32:29 PM PDT 24
Peak memory 250896 kb
Host smart-966cb755-9fe7-49fa-9671-a7dc04f83400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009186689 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_post_trans.3009186689
Directory /workspace/41.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all.1990787951
Short name T43
Test name
Test status
Simulation time 55970724979 ps
CPU time 884.56 seconds
Started Jun 07 07:32:15 PM PDT 24
Finished Jun 07 07:47:04 PM PDT 24
Peak memory 224116 kb
Host smart-a43d337c-ad6c-4b39-8f3d-a0dc4fb8a031
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990787951 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.lc_ctrl_stress_all.1990787951
Directory /workspace/41.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.lc_ctrl_volatile_unlock_smoke.931292566
Short name T789
Test name
Test status
Simulation time 45358297 ps
CPU time 1.46 seconds
Started Jun 07 07:32:11 PM PDT 24
Finished Jun 07 07:32:17 PM PDT 24
Peak memory 218180 kb
Host smart-6d2e8c14-397f-4d4b-87f0-a3b9bcca261e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931292566 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ct
rl_volatile_unlock_smoke.931292566
Directory /workspace/41.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_alert_test.1664179470
Short name T868
Test name
Test status
Simulation time 36929013 ps
CPU time 0.89 seconds
Started Jun 07 07:32:15 PM PDT 24
Finished Jun 07 07:32:21 PM PDT 24
Peak memory 209516 kb
Host smart-5950a54c-af1b-4100-87b1-d5b299e146a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664179470 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_alert_test.1664179470
Directory /workspace/42.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.lc_ctrl_errors.1669512534
Short name T581
Test name
Test status
Simulation time 257457425 ps
CPU time 13 seconds
Started Jun 07 07:32:11 PM PDT 24
Finished Jun 07 07:32:29 PM PDT 24
Peak memory 218636 kb
Host smart-88c36449-e0fc-45c3-9017-8097f220d265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669512534 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_errors.1669512534
Directory /workspace/42.lc_ctrl_errors/latest

Test location /workspace/coverage/default/42.lc_ctrl_jtag_access.853691964
Short name T867
Test name
Test status
Simulation time 56076421 ps
CPU time 2.16 seconds
Started Jun 07 07:32:11 PM PDT 24
Finished Jun 07 07:32:19 PM PDT 24
Peak memory 217492 kb
Host smart-01a565e2-6402-451c-b282-cbf2ff136c70
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853691964 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_jtag_access.853691964
Directory /workspace/42.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/42.lc_ctrl_prog_failure.1695230162
Short name T669
Test name
Test status
Simulation time 34031569 ps
CPU time 2 seconds
Started Jun 07 07:32:12 PM PDT 24
Finished Jun 07 07:32:19 PM PDT 24
Peak memory 218668 kb
Host smart-ef6a7a8b-5bd4-4b82-b240-7e41a6497dba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695230162 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_prog_failure.1695230162
Directory /workspace/42.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_mubi.1591457637
Short name T829
Test name
Test status
Simulation time 1010193254 ps
CPU time 10.04 seconds
Started Jun 07 07:32:10 PM PDT 24
Finished Jun 07 07:32:24 PM PDT 24
Peak memory 226536 kb
Host smart-52e9a96b-fb52-4263-bc08-830d22701a1a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591457637 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_mubi.1591457637
Directory /workspace/42.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_digest.211531326
Short name T412
Test name
Test status
Simulation time 267628137 ps
CPU time 10.05 seconds
Started Jun 07 07:32:15 PM PDT 24
Finished Jun 07 07:32:29 PM PDT 24
Peak memory 218800 kb
Host smart-a6bde8b0-ed92-4589-96ae-c0359a9c1b4d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211531326 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_di
gest.211531326
Directory /workspace/42.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_mux.2664020659
Short name T683
Test name
Test status
Simulation time 982306051 ps
CPU time 7.27 seconds
Started Jun 07 07:32:14 PM PDT 24
Finished Jun 07 07:32:26 PM PDT 24
Peak memory 218652 kb
Host smart-8631c27b-4712-459c-b4bf-efe09664bdb8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664020659 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_mux.
2664020659
Directory /workspace/42.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/42.lc_ctrl_security_escalation.2957226402
Short name T584
Test name
Test status
Simulation time 237885044 ps
CPU time 8.95 seconds
Started Jun 07 07:32:13 PM PDT 24
Finished Jun 07 07:32:27 PM PDT 24
Peak memory 218752 kb
Host smart-7b16dd7b-8636-4247-8a2c-7fb976190833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957226402 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_security_escalation.2957226402
Directory /workspace/42.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/42.lc_ctrl_smoke.2546001704
Short name T637
Test name
Test status
Simulation time 149658022 ps
CPU time 2.62 seconds
Started Jun 07 07:32:16 PM PDT 24
Finished Jun 07 07:32:23 PM PDT 24
Peak memory 214856 kb
Host smart-b8afa1d7-4553-4981-9bf0-c76776a095da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546001704 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_smoke.2546001704
Directory /workspace/42.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_failure.905345714
Short name T385
Test name
Test status
Simulation time 2550372845 ps
CPU time 23.09 seconds
Started Jun 07 07:32:15 PM PDT 24
Finished Jun 07 07:32:43 PM PDT 24
Peak memory 251476 kb
Host smart-d5917715-6b5e-4d6b-a07c-d7e79136ae85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905345714 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_failure.905345714
Directory /workspace/42.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_post_trans.3078605023
Short name T674
Test name
Test status
Simulation time 174496146 ps
CPU time 7.6 seconds
Started Jun 07 07:32:12 PM PDT 24
Finished Jun 07 07:32:25 PM PDT 24
Peak memory 247068 kb
Host smart-b521a950-8b51-4799-8ef9-86c19e770153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078605023 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_post_trans.3078605023
Directory /workspace/42.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/42.lc_ctrl_stress_all.1998723764
Short name T188
Test name
Test status
Simulation time 36171671259 ps
CPU time 300.35 seconds
Started Jun 07 07:32:16 PM PDT 24
Finished Jun 07 07:37:21 PM PDT 24
Peak memory 251468 kb
Host smart-9a1dccf4-1a80-463a-a19e-4ec578aa237d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998723764 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.lc_ctrl_stress_all.1998723764
Directory /workspace/42.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.lc_ctrl_volatile_unlock_smoke.2375108101
Short name T331
Test name
Test status
Simulation time 38966171 ps
CPU time 0.91 seconds
Started Jun 07 07:32:15 PM PDT 24
Finished Jun 07 07:32:21 PM PDT 24
Peak memory 209412 kb
Host smart-60a72079-772b-4de6-b6d3-36598f604577
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375108101 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_c
trl_volatile_unlock_smoke.2375108101
Directory /workspace/42.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_alert_test.2204917346
Short name T679
Test name
Test status
Simulation time 21195084 ps
CPU time 1.17 seconds
Started Jun 07 07:32:10 PM PDT 24
Finished Jun 07 07:32:14 PM PDT 24
Peak memory 209416 kb
Host smart-ce9e3f0f-8102-4997-a9de-263f71fddfc1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204917346 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_alert_test.2204917346
Directory /workspace/43.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.lc_ctrl_errors.2361042724
Short name T417
Test name
Test status
Simulation time 836894097 ps
CPU time 15.55 seconds
Started Jun 07 07:32:05 PM PDT 24
Finished Jun 07 07:32:22 PM PDT 24
Peak memory 218692 kb
Host smart-beb4dde2-5e2c-4535-8651-5ed6b5d7b147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361042724 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_errors.2361042724
Directory /workspace/43.lc_ctrl_errors/latest

Test location /workspace/coverage/default/43.lc_ctrl_jtag_access.1079175574
Short name T707
Test name
Test status
Simulation time 484743010 ps
CPU time 7.64 seconds
Started Jun 07 07:32:09 PM PDT 24
Finished Jun 07 07:32:20 PM PDT 24
Peak memory 217888 kb
Host smart-0f6f82e5-8811-4b26-8aa8-6b4dd08e5395
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079175574 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_jtag_access.1079175574
Directory /workspace/43.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/43.lc_ctrl_prog_failure.3603179093
Short name T245
Test name
Test status
Simulation time 261704005 ps
CPU time 2.41 seconds
Started Jun 07 07:32:07 PM PDT 24
Finished Jun 07 07:32:12 PM PDT 24
Peak memory 218656 kb
Host smart-7d46d1fd-162d-46fa-8cee-1032f10e5e5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603179093 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_prog_failure.3603179093
Directory /workspace/43.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_mubi.767512315
Short name T520
Test name
Test status
Simulation time 362279874 ps
CPU time 14 seconds
Started Jun 07 07:32:06 PM PDT 24
Finished Jun 07 07:32:21 PM PDT 24
Peak memory 219380 kb
Host smart-924d7542-da12-4861-82bf-7754db6e80b8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767512315 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_mubi.767512315
Directory /workspace/43.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_digest.292991729
Short name T460
Test name
Test status
Simulation time 538135786 ps
CPU time 12.44 seconds
Started Jun 07 07:32:12 PM PDT 24
Finished Jun 07 07:32:29 PM PDT 24
Peak memory 218732 kb
Host smart-f4dcf4cd-b5fb-47ef-a57b-c3af1252e022
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292991729 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_di
gest.292991729
Directory /workspace/43.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_mux.3206528054
Short name T799
Test name
Test status
Simulation time 1444277266 ps
CPU time 8.4 seconds
Started Jun 07 07:32:09 PM PDT 24
Finished Jun 07 07:32:21 PM PDT 24
Peak memory 225684 kb
Host smart-1fbcbe79-7c8b-4d8d-978c-8f69a6453ce4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206528054 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_mux.
3206528054
Directory /workspace/43.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/43.lc_ctrl_security_escalation.4097658432
Short name T551
Test name
Test status
Simulation time 263614116 ps
CPU time 10.38 seconds
Started Jun 07 07:32:09 PM PDT 24
Finished Jun 07 07:32:23 PM PDT 24
Peak memory 225152 kb
Host smart-77ec458f-57d9-4bbd-a4bf-a95c743fa5da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097658432 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_security_escalation.4097658432
Directory /workspace/43.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/43.lc_ctrl_smoke.651891815
Short name T80
Test name
Test status
Simulation time 54632171 ps
CPU time 2.72 seconds
Started Jun 07 07:32:14 PM PDT 24
Finished Jun 07 07:32:21 PM PDT 24
Peak memory 218160 kb
Host smart-73b433b1-786b-4001-88ef-57094f355d41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651891815 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_smoke.651891815
Directory /workspace/43.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_failure.1650519372
Short name T548
Test name
Test status
Simulation time 871491733 ps
CPU time 19.65 seconds
Started Jun 07 07:32:06 PM PDT 24
Finished Jun 07 07:32:28 PM PDT 24
Peak memory 251412 kb
Host smart-49ffece1-ec7a-4aaa-8701-346d3eb9a16e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650519372 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_failure.1650519372
Directory /workspace/43.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_post_trans.382468046
Short name T613
Test name
Test status
Simulation time 852231896 ps
CPU time 4.28 seconds
Started Jun 07 07:32:08 PM PDT 24
Finished Jun 07 07:32:15 PM PDT 24
Peak memory 226840 kb
Host smart-b86e66ee-e995-4aa3-82c2-f891f2b5da3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382468046 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_post_trans.382468046
Directory /workspace/43.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all.1737956277
Short name T668
Test name
Test status
Simulation time 4241357835 ps
CPU time 34.45 seconds
Started Jun 07 07:32:08 PM PDT 24
Finished Jun 07 07:32:45 PM PDT 24
Peak memory 225876 kb
Host smart-f4f93d4a-008e-4970-8ad9-1a25b0fecfff
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737956277 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.lc_ctrl_stress_all.1737956277
Directory /workspace/43.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.lc_ctrl_volatile_unlock_smoke.2872764465
Short name T672
Test name
Test status
Simulation time 38723547 ps
CPU time 0.77 seconds
Started Jun 07 07:32:05 PM PDT 24
Finished Jun 07 07:32:07 PM PDT 24
Peak memory 209156 kb
Host smart-607f63e9-36e3-4fed-83d2-a147582e34a1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872764465 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_c
trl_volatile_unlock_smoke.2872764465
Directory /workspace/43.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_alert_test.2575736237
Short name T700
Test name
Test status
Simulation time 27487846 ps
CPU time 0.86 seconds
Started Jun 07 07:32:15 PM PDT 24
Finished Jun 07 07:32:20 PM PDT 24
Peak memory 209192 kb
Host smart-f25d680f-eb70-48e0-91ce-e1a1aac58ddc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575736237 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_alert_test.2575736237
Directory /workspace/44.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.lc_ctrl_errors.4273938886
Short name T291
Test name
Test status
Simulation time 1178715247 ps
CPU time 14.24 seconds
Started Jun 07 07:32:12 PM PDT 24
Finished Jun 07 07:32:32 PM PDT 24
Peak memory 218692 kb
Host smart-3cbf7fe5-80a8-4483-bf2d-484e53724f2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273938886 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_errors.4273938886
Directory /workspace/44.lc_ctrl_errors/latest

Test location /workspace/coverage/default/44.lc_ctrl_jtag_access.551058804
Short name T607
Test name
Test status
Simulation time 2391597285 ps
CPU time 14.33 seconds
Started Jun 07 07:32:10 PM PDT 24
Finished Jun 07 07:32:29 PM PDT 24
Peak memory 217984 kb
Host smart-0dad59ea-19fd-4d3d-9d63-ce007847666f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551058804 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_jtag_access.551058804
Directory /workspace/44.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/44.lc_ctrl_prog_failure.3876312476
Short name T862
Test name
Test status
Simulation time 81035852 ps
CPU time 1.79 seconds
Started Jun 07 07:32:07 PM PDT 24
Finished Jun 07 07:32:12 PM PDT 24
Peak memory 222636 kb
Host smart-f79b1326-3070-4781-b559-91e88c8d5ed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876312476 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_prog_failure.3876312476
Directory /workspace/44.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_mubi.2757573051
Short name T185
Test name
Test status
Simulation time 170646298 ps
CPU time 9.05 seconds
Started Jun 07 07:32:15 PM PDT 24
Finished Jun 07 07:32:29 PM PDT 24
Peak memory 218776 kb
Host smart-564ea1a2-2e62-4978-bfde-0489590c531c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757573051 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_mubi.2757573051
Directory /workspace/44.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_digest.2817384622
Short name T323
Test name
Test status
Simulation time 2066867822 ps
CPU time 16.81 seconds
Started Jun 07 07:32:13 PM PDT 24
Finished Jun 07 07:32:35 PM PDT 24
Peak memory 226532 kb
Host smart-bc4d8b71-3f1f-4ab0-847d-326dc2884d18
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817384622 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_d
igest.2817384622
Directory /workspace/44.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_mux.2244689520
Short name T13
Test name
Test status
Simulation time 350567566 ps
CPU time 10.01 seconds
Started Jun 07 07:32:12 PM PDT 24
Finished Jun 07 07:32:27 PM PDT 24
Peak memory 218728 kb
Host smart-fea0958c-87e8-4323-8b2f-f8a9a436c4bb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244689520 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_mux.
2244689520
Directory /workspace/44.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/44.lc_ctrl_security_escalation.3824806528
Short name T786
Test name
Test status
Simulation time 242788498 ps
CPU time 9.95 seconds
Started Jun 07 07:32:12 PM PDT 24
Finished Jun 07 07:32:27 PM PDT 24
Peak memory 225364 kb
Host smart-b3f1474a-a5f9-4e8d-8721-d987fbad8097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824806528 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_security_escalation.3824806528
Directory /workspace/44.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/44.lc_ctrl_smoke.750198307
Short name T552
Test name
Test status
Simulation time 27847449 ps
CPU time 1.64 seconds
Started Jun 07 07:32:08 PM PDT 24
Finished Jun 07 07:32:13 PM PDT 24
Peak memory 214376 kb
Host smart-dea1bbcd-8c4e-4740-b5a1-0b4a90a82481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750198307 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_smoke.750198307
Directory /workspace/44.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_failure.2353983878
Short name T795
Test name
Test status
Simulation time 418873395 ps
CPU time 28.7 seconds
Started Jun 07 07:32:09 PM PDT 24
Finished Jun 07 07:32:41 PM PDT 24
Peak memory 251484 kb
Host smart-24d59e41-7cb1-4a31-9b92-5a5375d5398b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353983878 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_failure.2353983878
Directory /workspace/44.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_post_trans.3369678746
Short name T253
Test name
Test status
Simulation time 278942358 ps
CPU time 9.26 seconds
Started Jun 07 07:32:08 PM PDT 24
Finished Jun 07 07:32:21 PM PDT 24
Peak memory 251428 kb
Host smart-ce011a2a-704b-4fd2-b1e0-676f9333cdf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369678746 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_post_trans.3369678746
Directory /workspace/44.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/44.lc_ctrl_stress_all.2977559148
Short name T610
Test name
Test status
Simulation time 175042066661 ps
CPU time 384.75 seconds
Started Jun 07 07:32:11 PM PDT 24
Finished Jun 07 07:38:40 PM PDT 24
Peak memory 271040 kb
Host smart-49c74953-04c0-4615-92d0-6c9d97b562de
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977559148 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.lc_ctrl_stress_all.2977559148
Directory /workspace/44.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.lc_ctrl_stress_all_with_rand_reset.2860002035
Short name T93
Test name
Test status
Simulation time 52659944058 ps
CPU time 285.19 seconds
Started Jun 07 07:32:14 PM PDT 24
Finished Jun 07 07:37:03 PM PDT 24
Peak memory 422696 kb
Host smart-034c5bce-8d2a-4427-bef6-dd276ed7a350
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2860002035 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_stress_all_with_rand_reset.2860002035
Directory /workspace/44.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.lc_ctrl_volatile_unlock_smoke.3999453052
Short name T567
Test name
Test status
Simulation time 13909251 ps
CPU time 0.98 seconds
Started Jun 07 07:32:11 PM PDT 24
Finished Jun 07 07:32:17 PM PDT 24
Peak memory 209432 kb
Host smart-af3c14a9-9ea7-4feb-a4dd-cb0ed25df5ea
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999453052 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_c
trl_volatile_unlock_smoke.3999453052
Directory /workspace/44.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_alert_test.711536300
Short name T247
Test name
Test status
Simulation time 48105510 ps
CPU time 0.98 seconds
Started Jun 07 07:32:03 PM PDT 24
Finished Jun 07 07:32:05 PM PDT 24
Peak memory 209544 kb
Host smart-85c7b73e-ce22-4641-825e-380db50edd4b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711536300 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_alert_test.711536300
Directory /workspace/45.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.lc_ctrl_errors.1349513443
Short name T681
Test name
Test status
Simulation time 190134211 ps
CPU time 7.86 seconds
Started Jun 07 07:32:15 PM PDT 24
Finished Jun 07 07:32:28 PM PDT 24
Peak memory 218680 kb
Host smart-b8797d1c-2fda-4352-b83e-cb7096b5629e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349513443 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_errors.1349513443
Directory /workspace/45.lc_ctrl_errors/latest

Test location /workspace/coverage/default/45.lc_ctrl_jtag_access.3665815811
Short name T25
Test name
Test status
Simulation time 2681843118 ps
CPU time 7.04 seconds
Started Jun 07 07:32:06 PM PDT 24
Finished Jun 07 07:32:14 PM PDT 24
Peak memory 218136 kb
Host smart-54609055-13d5-4ddf-841b-59bcefa10999
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665815811 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_jtag_access.3665815811
Directory /workspace/45.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/45.lc_ctrl_prog_failure.1049854436
Short name T411
Test name
Test status
Simulation time 17636566 ps
CPU time 1.42 seconds
Started Jun 07 07:32:14 PM PDT 24
Finished Jun 07 07:32:20 PM PDT 24
Peak memory 222148 kb
Host smart-e6f17e07-3ff6-4dd9-b386-8c842d106635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049854436 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_prog_failure.1049854436
Directory /workspace/45.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_mubi.1392984022
Short name T165
Test name
Test status
Simulation time 705876543 ps
CPU time 12.34 seconds
Started Jun 07 07:32:05 PM PDT 24
Finished Jun 07 07:32:19 PM PDT 24
Peak memory 226532 kb
Host smart-b2c35257-25b3-47cb-8741-de48ff5f8a97
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392984022 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_mubi.1392984022
Directory /workspace/45.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_digest.1743689810
Short name T620
Test name
Test status
Simulation time 1044318246 ps
CPU time 8.35 seconds
Started Jun 07 07:32:08 PM PDT 24
Finished Jun 07 07:32:19 PM PDT 24
Peak memory 218672 kb
Host smart-64c507a6-5e15-4a5f-b2a7-8530731b6dbc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743689810 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_d
igest.1743689810
Directory /workspace/45.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_mux.2972750590
Short name T237
Test name
Test status
Simulation time 1322951789 ps
CPU time 10.86 seconds
Started Jun 07 07:32:06 PM PDT 24
Finished Jun 07 07:32:18 PM PDT 24
Peak memory 218716 kb
Host smart-a3e48404-ed68-43f9-b36d-cc52914a0dc9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972750590 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_mux.
2972750590
Directory /workspace/45.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/45.lc_ctrl_security_escalation.2125503837
Short name T680
Test name
Test status
Simulation time 764600521 ps
CPU time 6.64 seconds
Started Jun 07 07:32:06 PM PDT 24
Finished Jun 07 07:32:15 PM PDT 24
Peak memory 218720 kb
Host smart-81d1249a-7a39-4719-b55f-1a61fe51f9f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125503837 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_security_escalation.2125503837
Directory /workspace/45.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/45.lc_ctrl_smoke.1870198091
Short name T79
Test name
Test status
Simulation time 40419921 ps
CPU time 1 seconds
Started Jun 07 07:32:12 PM PDT 24
Finished Jun 07 07:32:18 PM PDT 24
Peak memory 218184 kb
Host smart-5f26a5aa-17ca-4e1d-a046-12af8e0beac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870198091 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_smoke.1870198091
Directory /workspace/45.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_failure.2950080634
Short name T36
Test name
Test status
Simulation time 218874530 ps
CPU time 23.32 seconds
Started Jun 07 07:32:12 PM PDT 24
Finished Jun 07 07:32:40 PM PDT 24
Peak memory 251508 kb
Host smart-26ce4963-5bb0-4e29-913a-4af060166123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950080634 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_failure.2950080634
Directory /workspace/45.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_post_trans.3519265167
Short name T269
Test name
Test status
Simulation time 74059252 ps
CPU time 10.79 seconds
Started Jun 07 07:32:12 PM PDT 24
Finished Jun 07 07:32:28 PM PDT 24
Peak memory 251428 kb
Host smart-72e4283f-8693-4639-9b03-d0b45498c252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519265167 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_post_trans.3519265167
Directory /workspace/45.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/45.lc_ctrl_stress_all.2208024706
Short name T757
Test name
Test status
Simulation time 2612924529 ps
CPU time 126.74 seconds
Started Jun 07 07:32:07 PM PDT 24
Finished Jun 07 07:34:16 PM PDT 24
Peak memory 283436 kb
Host smart-e2ef1117-8298-48e6-9a76-633c1be38d01
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208024706 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.lc_ctrl_stress_all.2208024706
Directory /workspace/45.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.lc_ctrl_volatile_unlock_smoke.483728383
Short name T345
Test name
Test status
Simulation time 56247479 ps
CPU time 0.88 seconds
Started Jun 07 07:32:15 PM PDT 24
Finished Jun 07 07:32:21 PM PDT 24
Peak memory 209408 kb
Host smart-935078e4-d1a1-4858-91cb-74bddc72969d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483728383 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ct
rl_volatile_unlock_smoke.483728383
Directory /workspace/45.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_alert_test.3888827028
Short name T72
Test name
Test status
Simulation time 23016159 ps
CPU time 1.02 seconds
Started Jun 07 07:32:10 PM PDT 24
Finished Jun 07 07:32:15 PM PDT 24
Peak memory 209368 kb
Host smart-b0c04b18-0342-4da2-8be7-654ded7e77f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888827028 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_alert_test.3888827028
Directory /workspace/46.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.lc_ctrl_errors.822370156
Short name T781
Test name
Test status
Simulation time 452601991 ps
CPU time 11.45 seconds
Started Jun 07 07:32:07 PM PDT 24
Finished Jun 07 07:32:21 PM PDT 24
Peak memory 218604 kb
Host smart-5283ea44-822c-47cb-a0cc-3ae72c715d74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822370156 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_errors.822370156
Directory /workspace/46.lc_ctrl_errors/latest

Test location /workspace/coverage/default/46.lc_ctrl_jtag_access.1464634787
Short name T694
Test name
Test status
Simulation time 171233872 ps
CPU time 5.29 seconds
Started Jun 07 07:32:07 PM PDT 24
Finished Jun 07 07:32:14 PM PDT 24
Peak memory 217712 kb
Host smart-567b79af-d8cc-4129-8773-3157439c4e2c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464634787 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_jtag_access.1464634787
Directory /workspace/46.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/46.lc_ctrl_prog_failure.2918011203
Short name T753
Test name
Test status
Simulation time 75398065 ps
CPU time 3.67 seconds
Started Jun 07 07:32:09 PM PDT 24
Finished Jun 07 07:32:16 PM PDT 24
Peak memory 222936 kb
Host smart-92861179-a53f-4e2e-a403-9753c8a08ad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918011203 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_prog_failure.2918011203
Directory /workspace/46.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_mubi.3931904314
Short name T835
Test name
Test status
Simulation time 904711001 ps
CPU time 15.54 seconds
Started Jun 07 07:32:08 PM PDT 24
Finished Jun 07 07:32:26 PM PDT 24
Peak memory 219408 kb
Host smart-18a55ea1-8ab4-4e95-aeac-18660449c5d2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931904314 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_mubi.3931904314
Directory /workspace/46.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_digest.1516489067
Short name T479
Test name
Test status
Simulation time 350959623 ps
CPU time 10.91 seconds
Started Jun 07 07:32:09 PM PDT 24
Finished Jun 07 07:32:23 PM PDT 24
Peak memory 218644 kb
Host smart-daac37d6-f9db-463a-ac4a-12c6b89ca2e1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516489067 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_d
igest.1516489067
Directory /workspace/46.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_mux.3333098827
Short name T387
Test name
Test status
Simulation time 2609166048 ps
CPU time 16.65 seconds
Started Jun 07 07:32:11 PM PDT 24
Finished Jun 07 07:32:32 PM PDT 24
Peak memory 218792 kb
Host smart-48f5e988-b39d-4d55-b549-72b4381cd951
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333098827 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_mux.
3333098827
Directory /workspace/46.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/46.lc_ctrl_security_escalation.2221967262
Short name T170
Test name
Test status
Simulation time 1728038163 ps
CPU time 12.45 seconds
Started Jun 07 07:32:07 PM PDT 24
Finished Jun 07 07:32:22 PM PDT 24
Peak memory 226108 kb
Host smart-ca0d3e5e-84f5-4615-86c9-4eae014ff0bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221967262 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_security_escalation.2221967262
Directory /workspace/46.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/46.lc_ctrl_smoke.1697597042
Short name T62
Test name
Test status
Simulation time 55471809 ps
CPU time 2.37 seconds
Started Jun 07 07:32:08 PM PDT 24
Finished Jun 07 07:32:13 PM PDT 24
Peak memory 215072 kb
Host smart-77b875c5-176e-40dc-8717-a42609ccd992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697597042 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_smoke.1697597042
Directory /workspace/46.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_failure.979895302
Short name T600
Test name
Test status
Simulation time 1168299768 ps
CPU time 27.32 seconds
Started Jun 07 07:32:07 PM PDT 24
Finished Jun 07 07:32:37 PM PDT 24
Peak memory 251432 kb
Host smart-f4aef509-c57f-45a7-bcd9-2b4a1ce8b711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979895302 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_failure.979895302
Directory /workspace/46.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_post_trans.4245747335
Short name T48
Test name
Test status
Simulation time 95656043 ps
CPU time 7.06 seconds
Started Jun 07 07:32:08 PM PDT 24
Finished Jun 07 07:32:18 PM PDT 24
Peak memory 250884 kb
Host smart-9344c2ed-106e-40e2-9893-44fe2d5b0f16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245747335 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_post_trans.4245747335
Directory /workspace/46.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all.2403587403
Short name T45
Test name
Test status
Simulation time 31857147594 ps
CPU time 523.87 seconds
Started Jun 07 07:32:07 PM PDT 24
Finished Jun 07 07:40:53 PM PDT 24
Peak memory 270448 kb
Host smart-7c8ef169-54fa-4a79-9c31-45f01d4c554c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403587403 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.lc_ctrl_stress_all.2403587403
Directory /workspace/46.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.lc_ctrl_volatile_unlock_smoke.3975290095
Short name T98
Test name
Test status
Simulation time 20574067 ps
CPU time 0.96 seconds
Started Jun 07 07:32:05 PM PDT 24
Finished Jun 07 07:32:08 PM PDT 24
Peak memory 212356 kb
Host smart-14f0d581-fa1f-48f5-80f5-a6bce1550bfb
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975290095 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_c
trl_volatile_unlock_smoke.3975290095
Directory /workspace/46.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_alert_test.2027743820
Short name T493
Test name
Test status
Simulation time 19771343 ps
CPU time 0.9 seconds
Started Jun 07 07:32:22 PM PDT 24
Finished Jun 07 07:32:29 PM PDT 24
Peak memory 209416 kb
Host smart-29e00e01-3102-4e8f-956b-9b589b9b4f3d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027743820 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_alert_test.2027743820
Directory /workspace/47.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.lc_ctrl_errors.2919814710
Short name T845
Test name
Test status
Simulation time 354122004 ps
CPU time 7.62 seconds
Started Jun 07 07:32:09 PM PDT 24
Finished Jun 07 07:32:21 PM PDT 24
Peak memory 218664 kb
Host smart-84d100c5-5b46-4506-af99-e7efd7c9671f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919814710 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_errors.2919814710
Directory /workspace/47.lc_ctrl_errors/latest

Test location /workspace/coverage/default/47.lc_ctrl_jtag_access.3864501136
Short name T505
Test name
Test status
Simulation time 1470648694 ps
CPU time 9.19 seconds
Started Jun 07 07:32:12 PM PDT 24
Finished Jun 07 07:32:26 PM PDT 24
Peak memory 217676 kb
Host smart-8e9412bb-2c64-4226-b406-aa06f0c5c068
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864501136 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_jtag_access.3864501136
Directory /workspace/47.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/47.lc_ctrl_prog_failure.2763618375
Short name T582
Test name
Test status
Simulation time 25366678 ps
CPU time 1.8 seconds
Started Jun 07 07:32:08 PM PDT 24
Finished Jun 07 07:32:13 PM PDT 24
Peak memory 222708 kb
Host smart-8883fbb1-05fa-4469-87e1-29117f36eef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763618375 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_prog_failure.2763618375
Directory /workspace/47.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_mubi.4058153101
Short name T726
Test name
Test status
Simulation time 1660377146 ps
CPU time 14.65 seconds
Started Jun 07 07:32:08 PM PDT 24
Finished Jun 07 07:32:26 PM PDT 24
Peak memory 220312 kb
Host smart-7a048c8d-8ad3-40ca-b89c-dc1ebf7a12d2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058153101 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_mubi.4058153101
Directory /workspace/47.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_digest.3134578333
Short name T378
Test name
Test status
Simulation time 275644287 ps
CPU time 11.01 seconds
Started Jun 07 07:32:08 PM PDT 24
Finished Jun 07 07:32:23 PM PDT 24
Peak memory 226540 kb
Host smart-51d7d7dc-dc74-43ee-98b2-9f9339b900d9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134578333 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_d
igest.3134578333
Directory /workspace/47.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_mux.1933705723
Short name T771
Test name
Test status
Simulation time 347630350 ps
CPU time 9.83 seconds
Started Jun 07 07:32:13 PM PDT 24
Finished Jun 07 07:32:28 PM PDT 24
Peak memory 218776 kb
Host smart-1ad15dbe-2ff3-4b61-957d-b40164451778
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933705723 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_mux.
1933705723
Directory /workspace/47.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/47.lc_ctrl_security_escalation.1580442055
Short name T846
Test name
Test status
Simulation time 1646153409 ps
CPU time 9.08 seconds
Started Jun 07 07:32:09 PM PDT 24
Finished Jun 07 07:32:21 PM PDT 24
Peak memory 218716 kb
Host smart-726ac06f-e544-4542-b07c-5fc09d77b201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580442055 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_security_escalation.1580442055
Directory /workspace/47.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/47.lc_ctrl_smoke.466230352
Short name T78
Test name
Test status
Simulation time 141031928 ps
CPU time 1.81 seconds
Started Jun 07 07:32:07 PM PDT 24
Finished Jun 07 07:32:11 PM PDT 24
Peak memory 214572 kb
Host smart-c30aeadd-da17-40ef-92f8-d84f61e48806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466230352 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_smoke.466230352
Directory /workspace/47.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_failure.3421085206
Short name T825
Test name
Test status
Simulation time 850372556 ps
CPU time 25.5 seconds
Started Jun 07 07:32:09 PM PDT 24
Finished Jun 07 07:32:38 PM PDT 24
Peak memory 251480 kb
Host smart-e51ee3b8-1200-46c3-821e-bf531625ac0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421085206 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_failure.3421085206
Directory /workspace/47.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_post_trans.3488564858
Short name T758
Test name
Test status
Simulation time 140885485 ps
CPU time 7.4 seconds
Started Jun 07 07:32:09 PM PDT 24
Finished Jun 07 07:32:21 PM PDT 24
Peak memory 250980 kb
Host smart-40f048c7-813b-4cf2-91bb-18d0fe4d1f78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488564858 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_post_trans.3488564858
Directory /workspace/47.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/47.lc_ctrl_stress_all.830651889
Short name T454
Test name
Test status
Simulation time 3406671159 ps
CPU time 123.84 seconds
Started Jun 07 07:32:15 PM PDT 24
Finished Jun 07 07:34:23 PM PDT 24
Peak memory 268660 kb
Host smart-a54dfcb0-0417-45ff-8dde-685f73604d05
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830651889 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.lc_ctrl_stress_all.830651889
Directory /workspace/47.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.lc_ctrl_volatile_unlock_smoke.2424575980
Short name T30
Test name
Test status
Simulation time 12227800 ps
CPU time 0.94 seconds
Started Jun 07 07:32:12 PM PDT 24
Finished Jun 07 07:32:17 PM PDT 24
Peak memory 212504 kb
Host smart-94ae4744-fe42-453d-bd24-eb4490e3f174
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424575980 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_c
trl_volatile_unlock_smoke.2424575980
Directory /workspace/47.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_alert_test.3160784807
Short name T457
Test name
Test status
Simulation time 67879302 ps
CPU time 0.97 seconds
Started Jun 07 07:32:15 PM PDT 24
Finished Jun 07 07:32:21 PM PDT 24
Peak memory 209364 kb
Host smart-806dca05-a21e-4354-bfc6-fc0b76278e70
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160784807 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_alert_test.3160784807
Directory /workspace/48.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.lc_ctrl_errors.3968956988
Short name T705
Test name
Test status
Simulation time 1097444088 ps
CPU time 8.38 seconds
Started Jun 07 07:32:11 PM PDT 24
Finished Jun 07 07:32:25 PM PDT 24
Peak memory 218800 kb
Host smart-723126ef-05b9-45a2-b500-8512e7692cdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968956988 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_errors.3968956988
Directory /workspace/48.lc_ctrl_errors/latest

Test location /workspace/coverage/default/48.lc_ctrl_jtag_access.2078165307
Short name T9
Test name
Test status
Simulation time 6358329964 ps
CPU time 8.49 seconds
Started Jun 07 07:32:15 PM PDT 24
Finished Jun 07 07:32:28 PM PDT 24
Peak memory 218236 kb
Host smart-49f4eead-238c-4cff-9917-6e6b07602a04
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078165307 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_jtag_access.2078165307
Directory /workspace/48.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/48.lc_ctrl_prog_failure.3442452274
Short name T268
Test name
Test status
Simulation time 53621417 ps
CPU time 1.67 seconds
Started Jun 07 07:32:16 PM PDT 24
Finished Jun 07 07:32:23 PM PDT 24
Peak memory 218700 kb
Host smart-38af8c6c-750e-46da-94a9-9dff2bafeaaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442452274 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_prog_failure.3442452274
Directory /workspace/48.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_mubi.837275194
Short name T421
Test name
Test status
Simulation time 584128476 ps
CPU time 11.14 seconds
Started Jun 07 07:32:17 PM PDT 24
Finished Jun 07 07:32:33 PM PDT 24
Peak memory 219404 kb
Host smart-f7a85c79-5b5b-49b6-840a-eb38f38a152e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837275194 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_mubi.837275194
Directory /workspace/48.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_digest.3197628048
Short name T254
Test name
Test status
Simulation time 362895499 ps
CPU time 9.82 seconds
Started Jun 07 07:32:21 PM PDT 24
Finished Jun 07 07:32:36 PM PDT 24
Peak memory 226584 kb
Host smart-bb3f6928-6ebb-4ddd-915f-c8cd20fd4eb6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197628048 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_d
igest.3197628048
Directory /workspace/48.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_mux.815910711
Short name T633
Test name
Test status
Simulation time 794729850 ps
CPU time 9.21 seconds
Started Jun 07 07:32:12 PM PDT 24
Finished Jun 07 07:32:26 PM PDT 24
Peak memory 218712 kb
Host smart-2b478991-9dd8-4d78-a95d-7dbae3cf3bf1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815910711 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_mux.815910711
Directory /workspace/48.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/48.lc_ctrl_security_escalation.1527486769
Short name T458
Test name
Test status
Simulation time 976416917 ps
CPU time 12.95 seconds
Started Jun 07 07:32:17 PM PDT 24
Finished Jun 07 07:32:35 PM PDT 24
Peak memory 225964 kb
Host smart-7ae62bd9-f9da-4b56-b68c-9fd9bba03a74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527486769 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_security_escalation.1527486769
Directory /workspace/48.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/48.lc_ctrl_smoke.1292076047
Short name T646
Test name
Test status
Simulation time 250382257 ps
CPU time 10.51 seconds
Started Jun 07 07:32:15 PM PDT 24
Finished Jun 07 07:32:30 PM PDT 24
Peak memory 218192 kb
Host smart-570e8ba0-4706-4a78-b826-e19ef454ccab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292076047 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_smoke.1292076047
Directory /workspace/48.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_failure.2416698767
Short name T580
Test name
Test status
Simulation time 281689698 ps
CPU time 23.77 seconds
Started Jun 07 07:32:12 PM PDT 24
Finished Jun 07 07:32:41 PM PDT 24
Peak memory 251480 kb
Host smart-7c26a419-dcb5-4bd3-ac3e-4ce0f8cd2b0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2416698767 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_failure.2416698767
Directory /workspace/48.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_post_trans.2161337319
Short name T155
Test name
Test status
Simulation time 170424526 ps
CPU time 10.22 seconds
Started Jun 07 07:32:14 PM PDT 24
Finished Jun 07 07:32:29 PM PDT 24
Peak memory 251544 kb
Host smart-aa6cba8c-cfb1-4f84-9751-17baad1c4778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161337319 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_post_trans.2161337319
Directory /workspace/48.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/48.lc_ctrl_volatile_unlock_smoke.226246923
Short name T657
Test name
Test status
Simulation time 19024360 ps
CPU time 0.76 seconds
Started Jun 07 07:32:14 PM PDT 24
Finished Jun 07 07:32:20 PM PDT 24
Peak memory 209332 kb
Host smart-f6865d36-d9b4-4f19-a003-d9e2950ba8a1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226246923 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ct
rl_volatile_unlock_smoke.226246923
Directory /workspace/48.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_alert_test.137160870
Short name T166
Test name
Test status
Simulation time 38546270 ps
CPU time 1.07 seconds
Started Jun 07 07:32:20 PM PDT 24
Finished Jun 07 07:32:27 PM PDT 24
Peak memory 209412 kb
Host smart-3772d925-331b-4ac3-8c82-5e519039b729
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137160870 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_alert_test.137160870
Directory /workspace/49.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.lc_ctrl_errors.1901858023
Short name T792
Test name
Test status
Simulation time 2203676374 ps
CPU time 10.97 seconds
Started Jun 07 07:32:15 PM PDT 24
Finished Jun 07 07:32:31 PM PDT 24
Peak memory 218708 kb
Host smart-ee726792-eec2-40ef-bd1c-65484392d531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901858023 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_errors.1901858023
Directory /workspace/49.lc_ctrl_errors/latest

Test location /workspace/coverage/default/49.lc_ctrl_jtag_access.3539291834
Short name T573
Test name
Test status
Simulation time 345567364 ps
CPU time 9.51 seconds
Started Jun 07 07:32:21 PM PDT 24
Finished Jun 07 07:32:36 PM PDT 24
Peak memory 217596 kb
Host smart-cb89669e-b03d-4e9e-bb63-9b285a0d54be
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539291834 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_jtag_access.3539291834
Directory /workspace/49.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/49.lc_ctrl_prog_failure.3975474554
Short name T664
Test name
Test status
Simulation time 797731611 ps
CPU time 6.29 seconds
Started Jun 07 07:32:21 PM PDT 24
Finished Jun 07 07:32:33 PM PDT 24
Peak memory 218724 kb
Host smart-0c2a0734-09a7-4ca1-b4c2-4ead6e1cf1d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975474554 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_prog_failure.3975474554
Directory /workspace/49.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_mubi.3266239209
Short name T740
Test name
Test status
Simulation time 904916314 ps
CPU time 11.79 seconds
Started Jun 07 07:32:19 PM PDT 24
Finished Jun 07 07:32:36 PM PDT 24
Peak memory 219284 kb
Host smart-54da8306-e451-4c78-be65-582d32c867ab
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266239209 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_mubi.3266239209
Directory /workspace/49.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_digest.1291190315
Short name T95
Test name
Test status
Simulation time 1021791639 ps
CPU time 20.75 seconds
Started Jun 07 07:32:20 PM PDT 24
Finished Jun 07 07:32:47 PM PDT 24
Peak memory 218704 kb
Host smart-3301ad8a-60ec-4156-baa3-d3d04bc4e637
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291190315 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_d
igest.1291190315
Directory /workspace/49.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_mux.2390913953
Short name T233
Test name
Test status
Simulation time 1540358586 ps
CPU time 10.3 seconds
Started Jun 07 07:32:21 PM PDT 24
Finished Jun 07 07:32:37 PM PDT 24
Peak memory 218700 kb
Host smart-7495bba9-a410-44a8-afd7-fed127f66600
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390913953 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_mux.
2390913953
Directory /workspace/49.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/49.lc_ctrl_security_escalation.2525448496
Short name T432
Test name
Test status
Simulation time 1145914791 ps
CPU time 14.43 seconds
Started Jun 07 07:32:19 PM PDT 24
Finished Jun 07 07:32:39 PM PDT 24
Peak memory 226484 kb
Host smart-d39b890c-a500-40e1-af5f-7dd4714a719c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2525448496 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_security_escalation.2525448496
Directory /workspace/49.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/49.lc_ctrl_smoke.939036288
Short name T865
Test name
Test status
Simulation time 66907614 ps
CPU time 3.35 seconds
Started Jun 07 07:32:22 PM PDT 24
Finished Jun 07 07:32:32 PM PDT 24
Peak memory 218272 kb
Host smart-17d89e1c-f45a-4735-a45c-2aa12eb587c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939036288 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_smoke.939036288
Directory /workspace/49.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_failure.816749971
Short name T477
Test name
Test status
Simulation time 383499403 ps
CPU time 21.52 seconds
Started Jun 07 07:32:21 PM PDT 24
Finished Jun 07 07:32:49 PM PDT 24
Peak memory 251472 kb
Host smart-53dee18d-39de-412f-8755-f89ba1ee33a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816749971 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_failure.816749971
Directory /workspace/49.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_post_trans.3915027709
Short name T623
Test name
Test status
Simulation time 85247929 ps
CPU time 4.59 seconds
Started Jun 07 07:32:19 PM PDT 24
Finished Jun 07 07:32:29 PM PDT 24
Peak memory 222960 kb
Host smart-9adc4e52-cdc2-4cde-ba4d-4426dbc62342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915027709 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_post_trans.3915027709
Directory /workspace/49.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/49.lc_ctrl_stress_all.2460995378
Short name T234
Test name
Test status
Simulation time 3144190610 ps
CPU time 55.47 seconds
Started Jun 07 07:32:20 PM PDT 24
Finished Jun 07 07:33:22 PM PDT 24
Peak memory 251352 kb
Host smart-3356485e-b800-450e-aae3-c09c3fd02c24
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460995378 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.lc_ctrl_stress_all.2460995378
Directory /workspace/49.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.lc_ctrl_volatile_unlock_smoke.1105059844
Short name T395
Test name
Test status
Simulation time 48753819 ps
CPU time 1.05 seconds
Started Jun 07 07:32:21 PM PDT 24
Finished Jun 07 07:32:28 PM PDT 24
Peak memory 213464 kb
Host smart-addd9a3c-b8e5-4ad0-87a9-d63f08fb049e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105059844 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_c
trl_volatile_unlock_smoke.1105059844
Directory /workspace/49.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_alert_test.2314371268
Short name T843
Test name
Test status
Simulation time 26593301 ps
CPU time 0.86 seconds
Started Jun 07 07:29:32 PM PDT 24
Finished Jun 07 07:29:36 PM PDT 24
Peak memory 209284 kb
Host smart-b65d39c6-b4c2-4bfe-9109-f0bc20aee253
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314371268 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_alert_test.2314371268
Directory /workspace/5.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.lc_ctrl_claim_transition_if.1530968714
Short name T559
Test name
Test status
Simulation time 11885208 ps
CPU time 0.85 seconds
Started Jun 07 07:29:28 PM PDT 24
Finished Jun 07 07:29:32 PM PDT 24
Peak memory 209356 kb
Host smart-4d189235-ce53-4dce-9e5b-77e6a0415ec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1530968714 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_claim_transition_if.1530968714
Directory /workspace/5.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/5.lc_ctrl_errors.1165768914
Short name T590
Test name
Test status
Simulation time 945485733 ps
CPU time 11.99 seconds
Started Jun 07 07:29:25 PM PDT 24
Finished Jun 07 07:29:40 PM PDT 24
Peak memory 218676 kb
Host smart-dc488522-9aa0-43c6-a44f-b9b90792d2b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165768914 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_errors.1165768914
Directory /workspace/5.lc_ctrl_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_access.2356434792
Short name T8
Test name
Test status
Simulation time 1516619804 ps
CPU time 17.06 seconds
Started Jun 07 07:29:31 PM PDT 24
Finished Jun 07 07:29:51 PM PDT 24
Peak memory 217852 kb
Host smart-14e1cc07-c83f-4d4c-bcb1-ff13026e27c1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356434792 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_access.2356434792
Directory /workspace/5.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_errors.2643849699
Short name T569
Test name
Test status
Simulation time 6254489880 ps
CPU time 25.05 seconds
Started Jun 07 07:29:27 PM PDT 24
Finished Jun 07 07:29:56 PM PDT 24
Peak memory 219244 kb
Host smart-eed2b0c1-b0f1-4e20-8261-77dbc0d6c45f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643849699 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_er
rors.2643849699
Directory /workspace/5.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_priority.2960078704
Short name T626
Test name
Test status
Simulation time 1240593688 ps
CPU time 7.73 seconds
Started Jun 07 07:29:26 PM PDT 24
Finished Jun 07 07:29:37 PM PDT 24
Peak memory 218248 kb
Host smart-dcd4bd53-7b34-48bf-9250-d5c4bb638a98
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960078704 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_priority.2
960078704
Directory /workspace/5.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_prog_failure.3000594776
Short name T526
Test name
Test status
Simulation time 905734327 ps
CPU time 6.97 seconds
Started Jun 07 07:29:27 PM PDT 24
Finished Jun 07 07:29:38 PM PDT 24
Peak memory 218704 kb
Host smart-a444b3f4-4180-47c5-8136-d77ecec9e982
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000594776 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag
_prog_failure.3000594776
Directory /workspace/5.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_regwen_during_op.1281207010
Short name T227
Test name
Test status
Simulation time 3272909967 ps
CPU time 13.96 seconds
Started Jun 07 07:29:30 PM PDT 24
Finished Jun 07 07:29:47 PM PDT 24
Peak memory 218260 kb
Host smart-8159ef67-9c7b-434c-9735-90f8b226cf48
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281207010 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_regwen_during_op.1281207010
Directory /workspace/5.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_smoke.803335893
Short name T76
Test name
Test status
Simulation time 507814058 ps
CPU time 13.71 seconds
Started Jun 07 07:29:29 PM PDT 24
Finished Jun 07 07:29:46 PM PDT 24
Peak memory 218228 kb
Host smart-3af0a5f2-7c95-48b8-a62a-65e11166648f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803335893 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_smoke.803335893
Directory /workspace/5.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_failure.1848068038
Short name T778
Test name
Test status
Simulation time 2958469584 ps
CPU time 55.92 seconds
Started Jun 07 07:29:27 PM PDT 24
Finished Jun 07 07:30:26 PM PDT 24
Peak memory 268564 kb
Host smart-82ade9a1-576a-4aa6-80af-59fe40cdd9cc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848068038 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jta
g_state_failure.1848068038
Directory /workspace/5.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_post_trans.4087834468
Short name T353
Test name
Test status
Simulation time 2663307356 ps
CPU time 24.51 seconds
Started Jun 07 07:29:25 PM PDT 24
Finished Jun 07 07:29:53 PM PDT 24
Peak memory 246176 kb
Host smart-76350ec8-029e-4edb-800f-040ad798175f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087834468 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_state_post_trans.4087834468
Directory /workspace/5.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_prog_failure.844929572
Short name T303
Test name
Test status
Simulation time 281605377 ps
CPU time 2.87 seconds
Started Jun 07 07:29:30 PM PDT 24
Finished Jun 07 07:29:36 PM PDT 24
Peak memory 222664 kb
Host smart-684e89f8-89f5-4609-ade9-261f5b6bdcdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844929572 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_prog_failure.844929572
Directory /workspace/5.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_regwen_during_op.91928936
Short name T591
Test name
Test status
Simulation time 494354507 ps
CPU time 6.33 seconds
Started Jun 07 07:29:29 PM PDT 24
Finished Jun 07 07:29:39 PM PDT 24
Peak memory 214508 kb
Host smart-39084fd9-5c9d-4021-962f-1cf7c2977037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91928936 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_regwen_during_op.91928936
Directory /workspace/5.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_mubi.4167054975
Short name T812
Test name
Test status
Simulation time 1248923822 ps
CPU time 13.85 seconds
Started Jun 07 07:29:26 PM PDT 24
Finished Jun 07 07:29:43 PM PDT 24
Peak memory 218844 kb
Host smart-904d022c-524f-40fd-9fe8-2ef4b56a262b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167054975 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_mubi.4167054975
Directory /workspace/5.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_digest.2618830043
Short name T333
Test name
Test status
Simulation time 1096175137 ps
CPU time 10.49 seconds
Started Jun 07 07:29:27 PM PDT 24
Finished Jun 07 07:29:41 PM PDT 24
Peak memory 218708 kb
Host smart-b34754a0-ea96-4761-9464-ebe7ae574d12
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618830043 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_di
gest.2618830043
Directory /workspace/5.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_mux.2664842729
Short name T692
Test name
Test status
Simulation time 270953904 ps
CPU time 10.43 seconds
Started Jun 07 07:29:26 PM PDT 24
Finished Jun 07 07:29:40 PM PDT 24
Peak memory 218732 kb
Host smart-04f24ea8-c0e6-4a99-82d6-cbf1f88ba6ee
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664842729 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_mux.2
664842729
Directory /workspace/5.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/5.lc_ctrl_security_escalation.1617038584
Short name T583
Test name
Test status
Simulation time 528044377 ps
CPU time 15.01 seconds
Started Jun 07 07:29:28 PM PDT 24
Finished Jun 07 07:29:46 PM PDT 24
Peak memory 226480 kb
Host smart-526bc8aa-c821-4c53-a257-762d70d4ddeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617038584 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_security_escalation.1617038584
Directory /workspace/5.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/5.lc_ctrl_smoke.3085236260
Short name T467
Test name
Test status
Simulation time 24965634 ps
CPU time 1.47 seconds
Started Jun 07 07:29:26 PM PDT 24
Finished Jun 07 07:29:31 PM PDT 24
Peak memory 223280 kb
Host smart-d4970b3a-44bf-4daf-a01b-b1d7be6435a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085236260 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_smoke.3085236260
Directory /workspace/5.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_failure.2099958584
Short name T309
Test name
Test status
Simulation time 282776235 ps
CPU time 29.55 seconds
Started Jun 07 07:29:25 PM PDT 24
Finished Jun 07 07:29:58 PM PDT 24
Peak memory 251432 kb
Host smart-0463de7e-7483-44e7-8388-d4dbf56bbbf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099958584 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_failure.2099958584
Directory /workspace/5.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_post_trans.1655080231
Short name T84
Test name
Test status
Simulation time 298995329 ps
CPU time 9.84 seconds
Started Jun 07 07:29:28 PM PDT 24
Finished Jun 07 07:29:42 PM PDT 24
Peak memory 251380 kb
Host smart-285dd27a-f3d8-43fd-9960-b23465b9903a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655080231 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_post_trans.1655080231
Directory /workspace/5.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_stress_all.3424086673
Short name T656
Test name
Test status
Simulation time 6398661004 ps
CPU time 214.5 seconds
Started Jun 07 07:29:31 PM PDT 24
Finished Jun 07 07:33:08 PM PDT 24
Peak memory 409656 kb
Host smart-521696e6-68ec-4744-bcbe-7cd1195fb002
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424086673 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.lc_ctrl_stress_all.3424086673
Directory /workspace/5.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.lc_ctrl_volatile_unlock_smoke.1954133150
Short name T476
Test name
Test status
Simulation time 41665217 ps
CPU time 1.49 seconds
Started Jun 07 07:29:30 PM PDT 24
Finished Jun 07 07:29:35 PM PDT 24
Peak memory 218224 kb
Host smart-7170895a-9739-408c-b034-61c347c92acf
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954133150 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ct
rl_volatile_unlock_smoke.1954133150
Directory /workspace/5.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_alert_test.312646895
Short name T501
Test name
Test status
Simulation time 27441612 ps
CPU time 0.87 seconds
Started Jun 07 07:29:35 PM PDT 24
Finished Jun 07 07:29:39 PM PDT 24
Peak memory 209352 kb
Host smart-90037085-c415-4f93-aef3-b331c5c275f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312646895 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_alert_test.312646895
Directory /workspace/6.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.lc_ctrl_claim_transition_if.2465029699
Short name T71
Test name
Test status
Simulation time 39365943 ps
CPU time 0.82 seconds
Started Jun 07 07:29:36 PM PDT 24
Finished Jun 07 07:29:40 PM PDT 24
Peak memory 209240 kb
Host smart-ff311284-6aa2-44d3-a696-65499a35b55e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465029699 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_claim_transition_if.2465029699
Directory /workspace/6.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/6.lc_ctrl_errors.2305900687
Short name T842
Test name
Test status
Simulation time 727718138 ps
CPU time 15.1 seconds
Started Jun 07 07:29:35 PM PDT 24
Finished Jun 07 07:29:54 PM PDT 24
Peak memory 218720 kb
Host smart-9b9dd2de-35f0-4689-bfe4-a3f10311454f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305900687 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_errors.2305900687
Directory /workspace/6.lc_ctrl_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_access.2347664314
Short name T754
Test name
Test status
Simulation time 42645241 ps
CPU time 1.13 seconds
Started Jun 07 07:29:34 PM PDT 24
Finished Jun 07 07:29:39 PM PDT 24
Peak memory 217568 kb
Host smart-dc76cd04-69e3-41dc-a693-f4b307846fec
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347664314 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_access.2347664314
Directory /workspace/6.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_errors.2598797630
Short name T364
Test name
Test status
Simulation time 58617844893 ps
CPU time 75.33 seconds
Started Jun 07 07:29:34 PM PDT 24
Finished Jun 07 07:30:53 PM PDT 24
Peak memory 226580 kb
Host smart-bce645a9-c8c5-4de7-b85f-f0c008f35537
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598797630 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_er
rors.2598797630
Directory /workspace/6.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_priority.1603768076
Short name T521
Test name
Test status
Simulation time 1273730912 ps
CPU time 12.11 seconds
Started Jun 07 07:29:35 PM PDT 24
Finished Jun 07 07:29:51 PM PDT 24
Peak memory 218016 kb
Host smart-f2159655-850c-4024-ab05-e7379e359b43
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603768076 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_priority.1
603768076
Directory /workspace/6.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_prog_failure.1687220617
Short name T519
Test name
Test status
Simulation time 738895441 ps
CPU time 21.16 seconds
Started Jun 07 07:29:33 PM PDT 24
Finished Jun 07 07:29:58 PM PDT 24
Peak memory 225836 kb
Host smart-fbd7af97-6f05-420f-9921-a69a529b2ea3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687220617 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag
_prog_failure.1687220617
Directory /workspace/6.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_regwen_during_op.738141560
Short name T337
Test name
Test status
Simulation time 2183530772 ps
CPU time 16.29 seconds
Started Jun 07 07:29:35 PM PDT 24
Finished Jun 07 07:29:55 PM PDT 24
Peak memory 218244 kb
Host smart-a5de7b19-2c16-476e-8414-73df0707f878
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738141560 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_j
tag_regwen_during_op.738141560
Directory /workspace/6.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_smoke.4264159727
Short name T839
Test name
Test status
Simulation time 114787157 ps
CPU time 3.94 seconds
Started Jun 07 07:29:35 PM PDT 24
Finished Jun 07 07:29:42 PM PDT 24
Peak memory 218248 kb
Host smart-7fc831e1-6539-4340-81b9-c9094975f1e8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264159727 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_smoke.
4264159727
Directory /workspace/6.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_failure.4090527634
Short name T312
Test name
Test status
Simulation time 5371171393 ps
CPU time 51.74 seconds
Started Jun 07 07:29:37 PM PDT 24
Finished Jun 07 07:30:32 PM PDT 24
Peak memory 251488 kb
Host smart-1344a754-a54f-4495-b44e-acfc80d466dd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090527634 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jta
g_state_failure.4090527634
Directory /workspace/6.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_post_trans.141258780
Short name T806
Test name
Test status
Simulation time 4319821219 ps
CPU time 20.8 seconds
Started Jun 07 07:29:33 PM PDT 24
Finished Jun 07 07:29:57 PM PDT 24
Peak memory 251544 kb
Host smart-891e675d-1d0f-4106-bf03-1d25b4cc0a12
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141258780 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_j
tag_state_post_trans.141258780
Directory /workspace/6.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_prog_failure.3941198235
Short name T334
Test name
Test status
Simulation time 75122973 ps
CPU time 2.94 seconds
Started Jun 07 07:29:35 PM PDT 24
Finished Jun 07 07:29:42 PM PDT 24
Peak memory 218784 kb
Host smart-05489f39-c12c-497b-9b20-6de330f0a633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941198235 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_prog_failure.3941198235
Directory /workspace/6.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_regwen_during_op.2699445350
Short name T596
Test name
Test status
Simulation time 375796777 ps
CPU time 16.19 seconds
Started Jun 07 07:29:34 PM PDT 24
Finished Jun 07 07:29:54 PM PDT 24
Peak memory 215068 kb
Host smart-1a62dd89-3c89-4a40-bbfa-a38de0a671ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699445350 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_regwen_during_op.2699445350
Directory /workspace/6.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_mubi.3460667176
Short name T570
Test name
Test status
Simulation time 205386708 ps
CPU time 11.19 seconds
Started Jun 07 07:29:35 PM PDT 24
Finished Jun 07 07:29:50 PM PDT 24
Peak memory 218736 kb
Host smart-7fd8089f-c6a7-43d8-9f38-d9b098a2cedc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460667176 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_mubi.3460667176
Directory /workspace/6.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_digest.3545282484
Short name T437
Test name
Test status
Simulation time 266150343 ps
CPU time 8.35 seconds
Started Jun 07 07:29:35 PM PDT 24
Finished Jun 07 07:29:47 PM PDT 24
Peak memory 218724 kb
Host smart-74620ff9-06ca-4c6e-a861-cacec2900b94
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545282484 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_di
gest.3545282484
Directory /workspace/6.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_mux.4240604426
Short name T852
Test name
Test status
Simulation time 499999296 ps
CPU time 10.04 seconds
Started Jun 07 07:29:34 PM PDT 24
Finished Jun 07 07:29:47 PM PDT 24
Peak memory 218688 kb
Host smart-f46d3a6f-dcfa-424c-b4f8-b9da22f26de5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240604426 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_mux.4
240604426
Directory /workspace/6.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/6.lc_ctrl_security_escalation.310891540
Short name T469
Test name
Test status
Simulation time 707824436 ps
CPU time 15.67 seconds
Started Jun 07 07:29:35 PM PDT 24
Finished Jun 07 07:29:54 PM PDT 24
Peak memory 218636 kb
Host smart-fd8d27e4-744d-47d6-9ba9-d89702f8cfca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310891540 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_security_escalation.310891540
Directory /workspace/6.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/6.lc_ctrl_smoke.2147710482
Short name T604
Test name
Test status
Simulation time 243621767 ps
CPU time 1.76 seconds
Started Jun 07 07:29:28 PM PDT 24
Finished Jun 07 07:29:33 PM PDT 24
Peak memory 218312 kb
Host smart-8cd06d47-5500-4f44-8f38-7bb6a200c79d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147710482 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_smoke.2147710482
Directory /workspace/6.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_failure.4048867521
Short name T352
Test name
Test status
Simulation time 354028124 ps
CPU time 19.57 seconds
Started Jun 07 07:29:30 PM PDT 24
Finished Jun 07 07:29:53 PM PDT 24
Peak memory 251392 kb
Host smart-f77fc8ac-f9f0-41e3-8fbd-c4bc94d7b1c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048867521 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_failure.4048867521
Directory /workspace/6.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_post_trans.813873421
Short name T798
Test name
Test status
Simulation time 64601487 ps
CPU time 6.15 seconds
Started Jun 07 07:29:31 PM PDT 24
Finished Jun 07 07:29:40 PM PDT 24
Peak memory 247092 kb
Host smart-2a5b93b7-fc84-46f5-bd10-2a1f147b650d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813873421 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_post_trans.813873421
Directory /workspace/6.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all.3130144598
Short name T278
Test name
Test status
Simulation time 5096944815 ps
CPU time 108.5 seconds
Started Jun 07 07:29:33 PM PDT 24
Finished Jun 07 07:31:25 PM PDT 24
Peak memory 273280 kb
Host smart-15deeba1-30d4-41fd-afac-0b7f208054df
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130144598 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.lc_ctrl_stress_all.3130144598
Directory /workspace/6.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.lc_ctrl_volatile_unlock_smoke.3155955750
Short name T850
Test name
Test status
Simulation time 24882704 ps
CPU time 0.78 seconds
Started Jun 07 07:29:31 PM PDT 24
Finished Jun 07 07:29:35 PM PDT 24
Peak memory 209108 kb
Host smart-fca8da52-787a-407a-a057-a71a037b5f15
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155955750 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ct
rl_volatile_unlock_smoke.3155955750
Directory /workspace/6.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_alert_test.2620483822
Short name T389
Test name
Test status
Simulation time 16223669 ps
CPU time 1.07 seconds
Started Jun 07 07:29:41 PM PDT 24
Finished Jun 07 07:29:45 PM PDT 24
Peak memory 209408 kb
Host smart-bc257e47-6e4f-41e3-9e1d-92108eaecd97
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620483822 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_alert_test.2620483822
Directory /workspace/7.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.lc_ctrl_errors.1031266927
Short name T647
Test name
Test status
Simulation time 303664577 ps
CPU time 8.42 seconds
Started Jun 07 07:29:36 PM PDT 24
Finished Jun 07 07:29:48 PM PDT 24
Peak memory 218736 kb
Host smart-27d8cb7b-b251-4c7a-824d-ad9839e13b54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031266927 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_errors.1031266927
Directory /workspace/7.lc_ctrl_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_access.3053436769
Short name T851
Test name
Test status
Simulation time 789336354 ps
CPU time 5.89 seconds
Started Jun 07 07:29:41 PM PDT 24
Finished Jun 07 07:29:50 PM PDT 24
Peak memory 217756 kb
Host smart-15acdd42-3477-4f8d-8a60-124b19050336
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053436769 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_access.3053436769
Directory /workspace/7.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_errors.134091783
Short name T561
Test name
Test status
Simulation time 11552804722 ps
CPU time 38.82 seconds
Started Jun 07 07:29:45 PM PDT 24
Finished Jun 07 07:30:27 PM PDT 24
Peak memory 226592 kb
Host smart-8236e98d-8245-4559-a865-7f7209b3ab72
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134091783 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_err
ors.134091783
Directory /workspace/7.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_priority.2935365858
Short name T206
Test name
Test status
Simulation time 218037946 ps
CPU time 3.67 seconds
Started Jun 07 07:29:45 PM PDT 24
Finished Jun 07 07:29:52 PM PDT 24
Peak memory 218256 kb
Host smart-d24137a9-8dca-4c50-8434-2bfb180189bc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935365858 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_priority.2
935365858
Directory /workspace/7.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_prog_failure.547558143
Short name T305
Test name
Test status
Simulation time 794612806 ps
CPU time 6.43 seconds
Started Jun 07 07:29:43 PM PDT 24
Finished Jun 07 07:29:52 PM PDT 24
Peak memory 218844 kb
Host smart-c544cefe-ef2c-42c9-bedb-c2457717b671
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547558143 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_
prog_failure.547558143
Directory /workspace/7.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_regwen_during_op.357422715
Short name T574
Test name
Test status
Simulation time 5914440550 ps
CPU time 17.99 seconds
Started Jun 07 07:29:45 PM PDT 24
Finished Jun 07 07:30:06 PM PDT 24
Peak memory 218276 kb
Host smart-19a9196d-119c-4022-89f8-42f2bc2fe589
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357422715 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_j
tag_regwen_during_op.357422715
Directory /workspace/7.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_smoke.3843677363
Short name T728
Test name
Test status
Simulation time 689141401 ps
CPU time 7.52 seconds
Started Jun 07 07:29:43 PM PDT 24
Finished Jun 07 07:29:53 PM PDT 24
Peak memory 218188 kb
Host smart-bebb18a3-8f5b-423f-8deb-2354bb215825
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843677363 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_smoke.
3843677363
Directory /workspace/7.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_failure.1773318274
Short name T236
Test name
Test status
Simulation time 4500031938 ps
CPU time 79.29 seconds
Started Jun 07 07:29:43 PM PDT 24
Finished Jun 07 07:31:04 PM PDT 24
Peak memory 280868 kb
Host smart-7b0415be-3aff-453a-ba13-d21dc4fd55c7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773318274 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jta
g_state_failure.1773318274
Directory /workspace/7.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_post_trans.2009165414
Short name T164
Test name
Test status
Simulation time 1595858954 ps
CPU time 18.77 seconds
Started Jun 07 07:29:45 PM PDT 24
Finished Jun 07 07:30:07 PM PDT 24
Peak memory 251424 kb
Host smart-18f9820f-64fa-4a8d-a53b-c7e672898366
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009165414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_state_post_trans.2009165414
Directory /workspace/7.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_prog_failure.1459225583
Short name T416
Test name
Test status
Simulation time 903859287 ps
CPU time 4.08 seconds
Started Jun 07 07:29:35 PM PDT 24
Finished Jun 07 07:29:43 PM PDT 24
Peak memory 218684 kb
Host smart-41cde367-e204-437c-804c-93d3b12eaed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459225583 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_prog_failure.1459225583
Directory /workspace/7.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_regwen_during_op.700301777
Short name T386
Test name
Test status
Simulation time 422180893 ps
CPU time 22.85 seconds
Started Jun 07 07:29:37 PM PDT 24
Finished Jun 07 07:30:03 PM PDT 24
Peak memory 218188 kb
Host smart-2f75c29b-30b1-4e71-8a92-7cf0b7816f92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700301777 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_regwen_during_op.700301777
Directory /workspace/7.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_mubi.384384048
Short name T642
Test name
Test status
Simulation time 1064647333 ps
CPU time 17.85 seconds
Started Jun 07 07:29:45 PM PDT 24
Finished Jun 07 07:30:06 PM PDT 24
Peak memory 219400 kb
Host smart-31148025-a771-452e-bffb-ba2f9a8414fc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384384048 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_mubi.384384048
Directory /workspace/7.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_digest.3575663870
Short name T415
Test name
Test status
Simulation time 1783006955 ps
CPU time 13.25 seconds
Started Jun 07 07:29:44 PM PDT 24
Finished Jun 07 07:30:00 PM PDT 24
Peak memory 226572 kb
Host smart-533e19ae-9607-40e6-a224-4e55da7ccf70
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575663870 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_di
gest.3575663870
Directory /workspace/7.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_mux.1891788831
Short name T230
Test name
Test status
Simulation time 1588089369 ps
CPU time 7.58 seconds
Started Jun 07 07:29:43 PM PDT 24
Finished Jun 07 07:29:53 PM PDT 24
Peak memory 218684 kb
Host smart-477f90be-4397-42ae-b393-b03fc4131722
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891788831 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_mux.1
891788831
Directory /workspace/7.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/7.lc_ctrl_security_escalation.2635432440
Short name T51
Test name
Test status
Simulation time 1784641455 ps
CPU time 11.39 seconds
Started Jun 07 07:29:36 PM PDT 24
Finished Jun 07 07:29:51 PM PDT 24
Peak memory 225204 kb
Host smart-60a6cde6-7a5a-4164-bb5a-c634c60b962c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635432440 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_security_escalation.2635432440
Directory /workspace/7.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/7.lc_ctrl_smoke.1558845131
Short name T488
Test name
Test status
Simulation time 49794485 ps
CPU time 2.15 seconds
Started Jun 07 07:29:35 PM PDT 24
Finished Jun 07 07:29:41 PM PDT 24
Peak memory 214720 kb
Host smart-aabd2ff6-21d2-4d22-bd54-cc2fb3380dcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558845131 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_smoke.1558845131
Directory /workspace/7.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_failure.940282527
Short name T578
Test name
Test status
Simulation time 892449892 ps
CPU time 28.28 seconds
Started Jun 07 07:29:37 PM PDT 24
Finished Jun 07 07:30:08 PM PDT 24
Peak memory 251396 kb
Host smart-ed0bb20e-5f8e-422f-afd3-a8054998d270
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940282527 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_failure.940282527
Directory /workspace/7.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_post_trans.2330069212
Short name T344
Test name
Test status
Simulation time 168448936 ps
CPU time 7.57 seconds
Started Jun 07 07:29:32 PM PDT 24
Finished Jun 07 07:29:43 PM PDT 24
Peak memory 251264 kb
Host smart-c6554b27-720c-458c-9fc2-7aa257ad5bcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330069212 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_post_trans.2330069212
Directory /workspace/7.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_stress_all.3892034028
Short name T191
Test name
Test status
Simulation time 5823483727 ps
CPU time 34.18 seconds
Started Jun 07 07:29:42 PM PDT 24
Finished Jun 07 07:30:19 PM PDT 24
Peak memory 227732 kb
Host smart-64549f85-e577-4673-bedc-1ae78a007f6e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892034028 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.lc_ctrl_stress_all.3892034028
Directory /workspace/7.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.lc_ctrl_volatile_unlock_smoke.1139536582
Short name T256
Test name
Test status
Simulation time 52393824 ps
CPU time 0.91 seconds
Started Jun 07 07:29:35 PM PDT 24
Finished Jun 07 07:29:39 PM PDT 24
Peak memory 212316 kb
Host smart-84337965-098c-425c-b79d-58069739b790
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139536582 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ct
rl_volatile_unlock_smoke.1139536582
Directory /workspace/7.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_alert_test.924597235
Short name T398
Test name
Test status
Simulation time 25511592 ps
CPU time 1.36 seconds
Started Jun 07 07:29:50 PM PDT 24
Finished Jun 07 07:29:55 PM PDT 24
Peak memory 209548 kb
Host smart-ce6c4f5c-2365-4088-9120-d11a587c6a58
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924597235 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_alert_test.924597235
Directory /workspace/8.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.lc_ctrl_errors.3925066778
Short name T529
Test name
Test status
Simulation time 208815083 ps
CPU time 10.64 seconds
Started Jun 07 07:29:42 PM PDT 24
Finished Jun 07 07:29:55 PM PDT 24
Peak memory 218632 kb
Host smart-d0c5bcc3-b4b0-4ef2-ae7c-1e9990a0c46c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925066778 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_errors.3925066778
Directory /workspace/8.lc_ctrl_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_access.2300882251
Short name T547
Test name
Test status
Simulation time 1554666209 ps
CPU time 18.5 seconds
Started Jun 07 07:29:52 PM PDT 24
Finished Jun 07 07:30:14 PM PDT 24
Peak memory 217924 kb
Host smart-ac425f83-9baf-4f60-a96e-3f13c1b9e34c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300882251 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_access.2300882251
Directory /workspace/8.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_errors.1388230480
Short name T844
Test name
Test status
Simulation time 9793674016 ps
CPU time 51.21 seconds
Started Jun 07 07:29:48 PM PDT 24
Finished Jun 07 07:30:42 PM PDT 24
Peak memory 226540 kb
Host smart-b0818c5e-3ae5-4b20-b159-6af0fed4dba9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388230480 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_er
rors.1388230480
Directory /workspace/8.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_priority.178358453
Short name T111
Test name
Test status
Simulation time 1070305547 ps
CPU time 10.98 seconds
Started Jun 07 07:29:50 PM PDT 24
Finished Jun 07 07:30:05 PM PDT 24
Peak memory 217964 kb
Host smart-5029540f-4bfe-405e-b9c6-faaf929939f4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178358453 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_priority.178358453
Directory /workspace/8.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_prog_failure.784632809
Short name T404
Test name
Test status
Simulation time 1919384268 ps
CPU time 5.85 seconds
Started Jun 07 07:29:48 PM PDT 24
Finished Jun 07 07:29:56 PM PDT 24
Peak memory 218672 kb
Host smart-3e9f3a0e-9d9e-4091-9460-0c965294ff27
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784632809 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_
prog_failure.784632809
Directory /workspace/8.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_regwen_during_op.1050945257
Short name T644
Test name
Test status
Simulation time 1315164024 ps
CPU time 19.03 seconds
Started Jun 07 07:29:50 PM PDT 24
Finished Jun 07 07:30:12 PM PDT 24
Peak memory 218084 kb
Host smart-b1e533a8-81e9-49f4-a6b2-ce7330975917
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050945257 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_regwen_during_op.1050945257
Directory /workspace/8.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_smoke.2677416086
Short name T500
Test name
Test status
Simulation time 1252023192 ps
CPU time 5.81 seconds
Started Jun 07 07:29:44 PM PDT 24
Finished Jun 07 07:29:53 PM PDT 24
Peak memory 218260 kb
Host smart-af422afb-2a7c-43b9-8368-747ee2d06f20
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677416086 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_smoke.
2677416086
Directory /workspace/8.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_failure.2497091044
Short name T300
Test name
Test status
Simulation time 5099202549 ps
CPU time 49.79 seconds
Started Jun 07 07:29:51 PM PDT 24
Finished Jun 07 07:30:44 PM PDT 24
Peak memory 267844 kb
Host smart-f41bf1d6-1df5-4a6f-9023-08717b22f824
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497091044 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jta
g_state_failure.2497091044
Directory /workspace/8.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_post_trans.481613181
Short name T746
Test name
Test status
Simulation time 1333437129 ps
CPU time 11.36 seconds
Started Jun 07 07:29:52 PM PDT 24
Finished Jun 07 07:30:07 PM PDT 24
Peak memory 251420 kb
Host smart-56135428-4414-4141-93cc-c3061489edf6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481613181 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_j
tag_state_post_trans.481613181
Directory /workspace/8.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_prog_failure.2461069887
Short name T779
Test name
Test status
Simulation time 301758882 ps
CPU time 2.96 seconds
Started Jun 07 07:29:42 PM PDT 24
Finished Jun 07 07:29:48 PM PDT 24
Peak memory 218664 kb
Host smart-31242c6f-6db6-4a96-b2c4-dbbc3efe1645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2461069887 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_prog_failure.2461069887
Directory /workspace/8.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_regwen_during_op.3660975044
Short name T563
Test name
Test status
Simulation time 1319129268 ps
CPU time 18.43 seconds
Started Jun 07 07:29:43 PM PDT 24
Finished Jun 07 07:30:05 PM PDT 24
Peak memory 218244 kb
Host smart-4d6e5d21-aa81-447c-b4bc-7ae920500dec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660975044 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_regwen_during_op.3660975044
Directory /workspace/8.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_mubi.1851465024
Short name T330
Test name
Test status
Simulation time 511616621 ps
CPU time 12.33 seconds
Started Jun 07 07:29:52 PM PDT 24
Finished Jun 07 07:30:07 PM PDT 24
Peak memory 219340 kb
Host smart-32077d94-57e1-433e-9fb1-cd00e30bcaeb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851465024 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_mubi.1851465024
Directory /workspace/8.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_digest.2367898639
Short name T296
Test name
Test status
Simulation time 617548825 ps
CPU time 14.34 seconds
Started Jun 07 07:29:51 PM PDT 24
Finished Jun 07 07:30:09 PM PDT 24
Peak memory 226544 kb
Host smart-c17ebe3c-a0aa-4467-b40f-62dee1810327
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367898639 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_di
gest.2367898639
Directory /workspace/8.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_mux.4270864207
Short name T59
Test name
Test status
Simulation time 2755530835 ps
CPU time 11.31 seconds
Started Jun 07 07:29:50 PM PDT 24
Finished Jun 07 07:30:04 PM PDT 24
Peak memory 218828 kb
Host smart-45085241-0004-4db7-a6c9-70b4a25f4712
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270864207 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_mux.4
270864207
Directory /workspace/8.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/8.lc_ctrl_security_escalation.3661042192
Short name T49
Test name
Test status
Simulation time 263148119 ps
CPU time 9.79 seconds
Started Jun 07 07:29:45 PM PDT 24
Finished Jun 07 07:29:58 PM PDT 24
Peak memory 225572 kb
Host smart-9092dbea-a342-40ba-a6f5-e3c551e41865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661042192 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_security_escalation.3661042192
Directory /workspace/8.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/8.lc_ctrl_smoke.3246408347
Short name T858
Test name
Test status
Simulation time 271421400 ps
CPU time 2.33 seconds
Started Jun 07 07:29:42 PM PDT 24
Finished Jun 07 07:29:47 PM PDT 24
Peak memory 214788 kb
Host smart-021727f7-a287-4a57-92af-bda414db4a0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246408347 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_smoke.3246408347
Directory /workspace/8.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_failure.955187306
Short name T273
Test name
Test status
Simulation time 214427981 ps
CPU time 25.55 seconds
Started Jun 07 07:29:45 PM PDT 24
Finished Jun 07 07:30:14 PM PDT 24
Peak memory 251432 kb
Host smart-53447c79-dadc-4937-b0f8-d1f7607c01a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955187306 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_failure.955187306
Directory /workspace/8.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_post_trans.2295569191
Short name T560
Test name
Test status
Simulation time 78455378 ps
CPU time 6.86 seconds
Started Jun 07 07:29:43 PM PDT 24
Finished Jun 07 07:29:52 PM PDT 24
Peak memory 250960 kb
Host smart-1377dffa-ac1c-416d-b329-a3c0cbde4f45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295569191 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_post_trans.2295569191
Directory /workspace/8.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all.3611296503
Short name T75
Test name
Test status
Simulation time 13039198861 ps
CPU time 170.14 seconds
Started Jun 07 07:29:51 PM PDT 24
Finished Jun 07 07:32:44 PM PDT 24
Peak memory 249012 kb
Host smart-a3e1090b-1ba7-4565-8e03-03021a07e361
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611296503 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.lc_ctrl_stress_all.3611296503
Directory /workspace/8.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all_with_rand_reset.2712022891
Short name T157
Test name
Test status
Simulation time 71689768404 ps
CPU time 474.78 seconds
Started Jun 07 07:29:49 PM PDT 24
Finished Jun 07 07:37:46 PM PDT 24
Peak memory 422520 kb
Host smart-1e0637fa-40fd-438f-a73e-5bec98d3c018
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2712022891 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_stress_all_with_rand_reset.2712022891
Directory /workspace/8.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.lc_ctrl_volatile_unlock_smoke.3359162151
Short name T503
Test name
Test status
Simulation time 13093164 ps
CPU time 0.96 seconds
Started Jun 07 07:29:44 PM PDT 24
Finished Jun 07 07:29:49 PM PDT 24
Peak memory 209464 kb
Host smart-defeccd6-d6c7-4564-884a-79da91e69148
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359162151 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ct
rl_volatile_unlock_smoke.3359162151
Directory /workspace/8.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_claim_transition_if.4245388285
Short name T208
Test name
Test status
Simulation time 30651230 ps
CPU time 0.78 seconds
Started Jun 07 07:29:51 PM PDT 24
Finished Jun 07 07:29:55 PM PDT 24
Peak memory 209436 kb
Host smart-dcc3ab71-ed6c-4dfc-ac45-d478d40d5062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245388285 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_claim_transition_if.4245388285
Directory /workspace/9.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/9.lc_ctrl_errors.2695131909
Short name T413
Test name
Test status
Simulation time 310342079 ps
CPU time 14.57 seconds
Started Jun 07 07:29:50 PM PDT 24
Finished Jun 07 07:30:08 PM PDT 24
Peak memory 218680 kb
Host smart-d1c7a5cf-7e05-4747-9502-7dd8f8292ee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695131909 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_errors.2695131909
Directory /workspace/9.lc_ctrl_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_access.995423245
Short name T695
Test name
Test status
Simulation time 860890179 ps
CPU time 2.84 seconds
Started Jun 07 07:29:49 PM PDT 24
Finished Jun 07 07:29:54 PM PDT 24
Peak memory 217500 kb
Host smart-9c46f6dc-b3f2-4235-8eff-88de2b89ce07
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995423245 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_access.995423245
Directory /workspace/9.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_errors.3795386622
Short name T764
Test name
Test status
Simulation time 1846073692 ps
CPU time 32.05 seconds
Started Jun 07 07:29:51 PM PDT 24
Finished Jun 07 07:30:27 PM PDT 24
Peak memory 226500 kb
Host smart-219a6f2e-951b-49c4-b40f-c538186838e2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795386622 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_er
rors.3795386622
Directory /workspace/9.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_priority.2465304684
Short name T666
Test name
Test status
Simulation time 5179688590 ps
CPU time 9 seconds
Started Jun 07 07:29:50 PM PDT 24
Finished Jun 07 07:30:03 PM PDT 24
Peak memory 218296 kb
Host smart-ff0aa1c8-413a-42a5-8f65-9a61adcf7181
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465304684 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_priority.2
465304684
Directory /workspace/9.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_prog_failure.562696458
Short name T624
Test name
Test status
Simulation time 1341135960 ps
CPU time 7.25 seconds
Started Jun 07 07:29:52 PM PDT 24
Finished Jun 07 07:30:02 PM PDT 24
Peak memory 218640 kb
Host smart-18128360-67f3-4348-9af6-1d5e70151f03
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562696458 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_
prog_failure.562696458
Directory /workspace/9.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_regwen_during_op.3908384979
Short name T229
Test name
Test status
Simulation time 3672075182 ps
CPU time 14.89 seconds
Started Jun 07 07:29:59 PM PDT 24
Finished Jun 07 07:30:17 PM PDT 24
Peak memory 218288 kb
Host smart-3141e2db-7b24-47d6-9b85-f34ac1ed0c18
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908384979 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_regwen_during_op.3908384979
Directory /workspace/9.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_smoke.917209578
Short name T744
Test name
Test status
Simulation time 2082729954 ps
CPU time 5.99 seconds
Started Jun 07 07:29:51 PM PDT 24
Finished Jun 07 07:30:00 PM PDT 24
Peak memory 218260 kb
Host smart-6ec30707-e222-4722-8377-56347bd50a91
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917209578 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_smoke.917209578
Directory /workspace/9.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_failure.1190975371
Short name T259
Test name
Test status
Simulation time 1246893100 ps
CPU time 60.35 seconds
Started Jun 07 07:29:51 PM PDT 24
Finished Jun 07 07:30:54 PM PDT 24
Peak memory 267896 kb
Host smart-c7ef84a7-acec-4f6e-99bc-d814cef56549
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190975371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jta
g_state_failure.1190975371
Directory /workspace/9.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_post_trans.2599452819
Short name T339
Test name
Test status
Simulation time 1012021180 ps
CPU time 17.55 seconds
Started Jun 07 07:29:50 PM PDT 24
Finished Jun 07 07:30:10 PM PDT 24
Peak memory 247920 kb
Host smart-5340a2b7-6261-48de-b6da-17580bd25fec
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599452819 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_state_post_trans.2599452819
Directory /workspace/9.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_prog_failure.504431828
Short name T725
Test name
Test status
Simulation time 57672721 ps
CPU time 3.23 seconds
Started Jun 07 07:29:52 PM PDT 24
Finished Jun 07 07:29:58 PM PDT 24
Peak memory 222860 kb
Host smart-4c2d985a-e101-4567-9eb2-e3ea7e2fec93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504431828 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_prog_failure.504431828
Directory /workspace/9.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_regwen_during_op.51694648
Short name T487
Test name
Test status
Simulation time 339271424 ps
CPU time 22.44 seconds
Started Jun 07 07:29:51 PM PDT 24
Finished Jun 07 07:30:17 PM PDT 24
Peak memory 214640 kb
Host smart-ad9c9e71-d76f-48b6-b49a-0e7c802a9a58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51694648 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_regwen_during_op.51694648
Directory /workspace/9.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_mubi.2685136484
Short name T397
Test name
Test status
Simulation time 1512537130 ps
CPU time 17.35 seconds
Started Jun 07 07:30:00 PM PDT 24
Finished Jun 07 07:30:20 PM PDT 24
Peak memory 219492 kb
Host smart-18aa7bb1-1baa-4541-9f59-ffe79ea16071
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685136484 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_mubi.2685136484
Directory /workspace/9.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_digest.1530525156
Short name T12
Test name
Test status
Simulation time 328911624 ps
CPU time 12.85 seconds
Started Jun 07 07:29:59 PM PDT 24
Finished Jun 07 07:30:15 PM PDT 24
Peak memory 218744 kb
Host smart-7185c4e2-aacd-455c-be98-3304e3852e74
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530525156 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_di
gest.1530525156
Directory /workspace/9.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_mux.421914107
Short name T177
Test name
Test status
Simulation time 366882019 ps
CPU time 9.91 seconds
Started Jun 07 07:30:01 PM PDT 24
Finished Jun 07 07:30:13 PM PDT 24
Peak memory 218740 kb
Host smart-1604a70c-6d8e-4bc2-9e40-98a3f433c48b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421914107 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_mux.421914107
Directory /workspace/9.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/9.lc_ctrl_security_escalation.549169009
Short name T108
Test name
Test status
Simulation time 804691450 ps
CPU time 6.92 seconds
Started Jun 07 07:29:49 PM PDT 24
Finished Jun 07 07:29:58 PM PDT 24
Peak memory 225060 kb
Host smart-ab4eecca-0709-450d-ae60-5e31f8b27fde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549169009 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_security_escalation.549169009
Directory /workspace/9.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/9.lc_ctrl_smoke.4030144509
Short name T328
Test name
Test status
Simulation time 230813825 ps
CPU time 5.58 seconds
Started Jun 07 07:29:50 PM PDT 24
Finished Jun 07 07:29:59 PM PDT 24
Peak memory 218212 kb
Host smart-5b092259-e790-4007-8200-60ee0ce1ea24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030144509 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_smoke.4030144509
Directory /workspace/9.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_failure.311969054
Short name T99
Test name
Test status
Simulation time 465607369 ps
CPU time 26.05 seconds
Started Jun 07 07:29:54 PM PDT 24
Finished Jun 07 07:30:22 PM PDT 24
Peak memory 251344 kb
Host smart-d7344f7b-95d6-441c-82e1-138f2ae6ac69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311969054 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_failure.311969054
Directory /workspace/9.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_post_trans.2166196341
Short name T830
Test name
Test status
Simulation time 62259005 ps
CPU time 8.14 seconds
Started Jun 07 07:29:52 PM PDT 24
Finished Jun 07 07:30:03 PM PDT 24
Peak memory 251412 kb
Host smart-397f7de3-1d3b-4898-b363-d6a642122f27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166196341 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_post_trans.2166196341
Directory /workspace/9.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_stress_all.454509073
Short name T81
Test name
Test status
Simulation time 48648824944 ps
CPU time 299.98 seconds
Started Jun 07 07:30:02 PM PDT 24
Finished Jun 07 07:35:04 PM PDT 24
Peak memory 300640 kb
Host smart-14a07534-6ae7-440c-a95e-218357a9ca23
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454509073 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.lc_ctrl_stress_all.454509073
Directory /workspace/9.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.lc_ctrl_volatile_unlock_smoke.1703547221
Short name T321
Test name
Test status
Simulation time 21851881 ps
CPU time 0.81 seconds
Started Jun 07 07:29:49 PM PDT 24
Finished Jun 07 07:29:52 PM PDT 24
Peak memory 209444 kb
Host smart-166d19b7-7814-4502-bc95-5a5a30819a4f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703547221 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ct
rl_volatile_unlock_smoke.1703547221
Directory /workspace/9.lc_ctrl_volatile_unlock_smoke/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%