Summary for Variable clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
56431 |
1 |
|
|
T1 |
86 |
|
T2 |
4 |
|
T3 |
9 |
auto[1] |
2036 |
1 |
|
|
T12 |
10 |
|
T16 |
10 |
|
T49 |
4 |
Summary for Variable clk_byp_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
57699 |
1 |
|
|
T1 |
86 |
|
T2 |
4 |
|
T3 |
9 |
auto[1] |
768 |
1 |
|
|
T55 |
11 |
|
T56 |
16 |
|
T67 |
14 |
Summary for Variable count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
56352 |
1 |
|
|
T1 |
86 |
|
T2 |
4 |
|
T3 |
9 |
auto[1] |
2115 |
1 |
|
|
T14 |
1 |
|
T18 |
1 |
|
T51 |
20 |
Summary for Variable count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
56334 |
1 |
|
|
T1 |
86 |
|
T2 |
4 |
|
T3 |
9 |
auto[1] |
2133 |
1 |
|
|
T14 |
1 |
|
T18 |
1 |
|
T51 |
8 |
Summary for Variable count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
56403 |
1 |
|
|
T1 |
86 |
|
T2 |
4 |
|
T3 |
9 |
auto[1] |
2064 |
1 |
|
|
T51 |
9 |
|
T60 |
8 |
|
T4 |
84 |
Summary for Variable err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for err_inj_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
err_inj |
53099 |
1 |
|
|
T1 |
86 |
|
T3 |
9 |
|
T11 |
93 |
no_err_inj |
5368 |
1 |
|
|
T2 |
4 |
|
T13 |
6 |
|
T14 |
8 |
Summary for Variable flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
56459 |
1 |
|
|
T1 |
86 |
|
T2 |
4 |
|
T3 |
9 |
auto[1] |
2008 |
1 |
|
|
T12 |
9 |
|
T16 |
10 |
|
T49 |
7 |
Summary for Variable flash_rma_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
57675 |
1 |
|
|
T1 |
86 |
|
T2 |
4 |
|
T3 |
9 |
auto[1] |
792 |
1 |
|
|
T55 |
16 |
|
T56 |
21 |
|
T67 |
16 |
Summary for Variable jtag_csr_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for jtag_csr_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
39081 |
1 |
|
|
T1 |
86 |
|
T2 |
4 |
|
T3 |
9 |
auto[1] |
19386 |
1 |
|
|
T4 |
949 |
|
T5 |
97 |
|
T6 |
81 |
Summary for Variable kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for kmac_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
56385 |
1 |
|
|
T1 |
86 |
|
T2 |
4 |
|
T3 |
9 |
auto[1] |
2082 |
1 |
|
|
T51 |
7 |
|
T60 |
8 |
|
T4 |
75 |
Summary for Variable lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for lc_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
56300 |
1 |
|
|
T1 |
86 |
|
T2 |
4 |
|
T3 |
9 |
auto[1] |
2167 |
1 |
|
|
T51 |
12 |
|
T60 |
12 |
|
T4 |
100 |
Summary for Variable otp_lc_data_i_valid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_lc_data_i_valid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
56359 |
1 |
|
|
T1 |
86 |
|
T2 |
4 |
|
T3 |
9 |
auto[1] |
2108 |
1 |
|
|
T14 |
1 |
|
T18 |
1 |
|
T51 |
10 |
Summary for Variable otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_partition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
56491 |
1 |
|
|
T1 |
86 |
|
T2 |
4 |
|
T3 |
9 |
auto[1] |
1976 |
1 |
|
|
T12 |
14 |
|
T16 |
14 |
|
T49 |
7 |
Summary for Variable otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_prog_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
55621 |
1 |
|
|
T1 |
86 |
|
T2 |
4 |
|
T11 |
93 |
auto[1] |
2846 |
1 |
|
|
T3 |
9 |
|
T4 |
113 |
|
T66 |
6 |
Summary for Variable otp_rma_token_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_rma_token_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
57706 |
1 |
|
|
T1 |
86 |
|
T2 |
4 |
|
T3 |
9 |
auto[1] |
761 |
1 |
|
|
T55 |
18 |
|
T56 |
15 |
|
T67 |
22 |
Summary for Variable otp_secrets_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_secrets_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
57679 |
1 |
|
|
T1 |
86 |
|
T2 |
4 |
|
T3 |
9 |
auto[1] |
788 |
1 |
|
|
T55 |
23 |
|
T56 |
9 |
|
T67 |
18 |
Summary for Variable otp_test_tokens_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_test_tokens_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
57659 |
1 |
|
|
T1 |
86 |
|
T2 |
4 |
|
T3 |
9 |
auto[1] |
808 |
1 |
|
|
T55 |
15 |
|
T56 |
15 |
|
T67 |
28 |
Summary for Variable post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for post_trans_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
55574 |
1 |
|
|
T1 |
86 |
|
T2 |
4 |
|
T3 |
9 |
auto[1] |
2893 |
1 |
|
|
T14 |
12 |
|
T18 |
11 |
|
T4 |
30 |
Summary for Variable security_escalation_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for security_escalation_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54664 |
1 |
|
|
T2 |
4 |
|
T3 |
9 |
|
T12 |
78 |
auto[1] |
3803 |
1 |
|
|
T1 |
86 |
|
T11 |
93 |
|
T39 |
79 |
Summary for Variable state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
56417 |
1 |
|
|
T1 |
86 |
|
T2 |
4 |
|
T3 |
9 |
auto[1] |
2050 |
1 |
|
|
T18 |
2 |
|
T51 |
10 |
|
T60 |
7 |
Summary for Variable state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
56340 |
1 |
|
|
T1 |
86 |
|
T2 |
4 |
|
T3 |
9 |
auto[1] |
2127 |
1 |
|
|
T18 |
2 |
|
T51 |
12 |
|
T60 |
6 |
Summary for Variable state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
56361 |
1 |
|
|
T1 |
86 |
|
T2 |
4 |
|
T3 |
9 |
auto[1] |
2106 |
1 |
|
|
T14 |
1 |
|
T18 |
1 |
|
T51 |
12 |
Summary for Variable token_invalid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_invalid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
56449 |
1 |
|
|
T1 |
86 |
|
T2 |
4 |
|
T3 |
9 |
auto[1] |
2018 |
1 |
|
|
T12 |
7 |
|
T16 |
16 |
|
T49 |
11 |
Summary for Variable token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mismatch_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52706 |
1 |
|
|
T1 |
86 |
|
T2 |
4 |
|
T3 |
9 |
auto[1] |
5761 |
1 |
|
|
T12 |
16 |
|
T16 |
15 |
|
T49 |
11 |
Summary for Variable token_mux_ctrl_redun_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mux_ctrl_redun_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54721 |
1 |
|
|
T1 |
86 |
|
T2 |
4 |
|
T3 |
9 |
auto[1] |
3746 |
1 |
|
|
T15 |
84 |
|
T28 |
66 |
|
T50 |
52 |
Summary for Variable token_mux_digest_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for token_mux_digest_err_cp
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
58467 |
1 |
|
|
T1 |
86 |
|
T2 |
4 |
|
T3 |
9 |
Summary for Variable token_response_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_response_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
56439 |
1 |
|
|
T1 |
86 |
|
T2 |
4 |
|
T3 |
9 |
auto[1] |
2028 |
1 |
|
|
T12 |
6 |
|
T16 |
10 |
|
T49 |
9 |
Summary for Variable transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
56442 |
1 |
|
|
T1 |
86 |
|
T2 |
4 |
|
T3 |
9 |
auto[1] |
2025 |
1 |
|
|
T12 |
6 |
|
T16 |
13 |
|
T49 |
7 |
Summary for Variable transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
56484 |
1 |
|
|
T1 |
86 |
|
T2 |
4 |
|
T3 |
9 |
auto[1] |
1983 |
1 |
|
|
T12 |
10 |
|
T16 |
8 |
|
T49 |
9 |
Summary for Cross post_trans_err_inj_xp
Samples crossed: post_trans_err_cp err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_err_inj_xp
Bins
post_trans_err_cp | err_inj_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
err_inj |
51657 |
1 |
|
|
T1 |
86 |
|
T3 |
9 |
|
T11 |
93 |
auto[0] |
no_err_inj |
3917 |
1 |
|
|
T2 |
4 |
|
T13 |
6 |
|
T65 |
8 |
auto[1] |
err_inj |
1442 |
1 |
|
|
T14 |
4 |
|
T18 |
8 |
|
T4 |
16 |
auto[1] |
no_err_inj |
1451 |
1 |
|
|
T14 |
8 |
|
T18 |
3 |
|
T4 |
14 |
Summary for Cross post_trans_state_err_xp
Samples crossed: post_trans_err_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_err_xp
Bins
post_trans_err_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
53615 |
1 |
|
|
T1 |
86 |
|
T2 |
4 |
|
T3 |
9 |
auto[0] |
auto[1] |
1959 |
1 |
|
|
T51 |
12 |
|
T60 |
6 |
|
T4 |
88 |
auto[1] |
auto[0] |
2725 |
1 |
|
|
T14 |
12 |
|
T18 |
9 |
|
T4 |
27 |
auto[1] |
auto[1] |
168 |
1 |
|
|
T18 |
2 |
|
T4 |
3 |
|
T20 |
4 |
Summary for Cross post_trans_lc_fsm_backdoor_err_xp
Samples crossed: post_trans_err_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_lc_fsm_backdoor_err_xp
Bins
post_trans_err_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
53568 |
1 |
|
|
T1 |
86 |
|
T2 |
4 |
|
T3 |
9 |
auto[0] |
auto[1] |
2006 |
1 |
|
|
T51 |
12 |
|
T60 |
12 |
|
T4 |
98 |
auto[1] |
auto[0] |
2732 |
1 |
|
|
T14 |
12 |
|
T18 |
11 |
|
T4 |
28 |
auto[1] |
auto[1] |
161 |
1 |
|
|
T4 |
2 |
|
T20 |
5 |
|
T23 |
3 |
Summary for Cross post_trans_state_illegal_err_xp
Samples crossed: post_trans_err_cp state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_illegal_err_xp
Bins
post_trans_err_cp | state_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
53632 |
1 |
|
|
T1 |
86 |
|
T2 |
4 |
|
T3 |
9 |
auto[0] |
auto[1] |
1942 |
1 |
|
|
T51 |
12 |
|
T60 |
8 |
|
T4 |
85 |
auto[1] |
auto[0] |
2729 |
1 |
|
|
T14 |
11 |
|
T18 |
10 |
|
T4 |
29 |
auto[1] |
auto[1] |
164 |
1 |
|
|
T14 |
1 |
|
T18 |
1 |
|
T4 |
1 |
Summary for Cross post_trans_count_err_xp
Samples crossed: post_trans_err_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_err_xp
Bins
post_trans_err_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
53605 |
1 |
|
|
T1 |
86 |
|
T2 |
4 |
|
T3 |
9 |
auto[0] |
auto[1] |
1969 |
1 |
|
|
T51 |
8 |
|
T60 |
9 |
|
T4 |
96 |
auto[1] |
auto[0] |
2729 |
1 |
|
|
T14 |
11 |
|
T18 |
10 |
|
T4 |
29 |
auto[1] |
auto[1] |
164 |
1 |
|
|
T14 |
1 |
|
T18 |
1 |
|
T4 |
1 |
Summary for Cross post_trans_count_illegal_err_xp
Samples crossed: post_trans_err_cp count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_illegal_err_xp
Bins
post_trans_err_cp | count_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
53664 |
1 |
|
|
T1 |
86 |
|
T2 |
4 |
|
T3 |
9 |
auto[0] |
auto[1] |
1910 |
1 |
|
|
T51 |
9 |
|
T60 |
8 |
|
T4 |
83 |
auto[1] |
auto[0] |
2739 |
1 |
|
|
T14 |
12 |
|
T18 |
11 |
|
T4 |
29 |
auto[1] |
auto[1] |
154 |
1 |
|
|
T4 |
1 |
|
T20 |
3 |
|
T21 |
1 |
Summary for Cross post_trans_count_backdoor_err_xp
Samples crossed: post_trans_err_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_backdoor_err_xp
Bins
post_trans_err_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
53606 |
1 |
|
|
T1 |
86 |
|
T2 |
4 |
|
T3 |
9 |
auto[0] |
auto[1] |
1968 |
1 |
|
|
T51 |
20 |
|
T60 |
4 |
|
T4 |
102 |
auto[1] |
auto[0] |
2746 |
1 |
|
|
T14 |
11 |
|
T18 |
10 |
|
T4 |
26 |
auto[1] |
auto[1] |
147 |
1 |
|
|
T14 |
1 |
|
T18 |
1 |
|
T4 |
4 |
Summary for Cross jtag_clk_byp_error_rsp_xp
Samples crossed: jtag_csr_cp clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_clk_byp_error_rsp_xp
Bins
jtag_csr_cp | clk_byp_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37972 |
1 |
|
|
T1 |
86 |
|
T2 |
4 |
|
T3 |
9 |
auto[0] |
auto[1] |
1109 |
1 |
|
|
T12 |
10 |
|
T16 |
10 |
|
T49 |
4 |
auto[1] |
auto[0] |
18459 |
1 |
|
|
T4 |
916 |
|
T5 |
97 |
|
T6 |
72 |
auto[1] |
auto[1] |
927 |
1 |
|
|
T4 |
33 |
|
T6 |
9 |
|
T20 |
19 |
Summary for Cross jtag_flash_rma_error_rsp_xp
Samples crossed: jtag_csr_cp flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_flash_rma_error_rsp_xp
Bins
jtag_csr_cp | flash_rma_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38000 |
1 |
|
|
T1 |
86 |
|
T2 |
4 |
|
T3 |
9 |
auto[0] |
auto[1] |
1081 |
1 |
|
|
T12 |
9 |
|
T16 |
10 |
|
T49 |
7 |
auto[1] |
auto[0] |
18459 |
1 |
|
|
T4 |
899 |
|
T5 |
97 |
|
T6 |
66 |
auto[1] |
auto[1] |
927 |
1 |
|
|
T4 |
50 |
|
T6 |
15 |
|
T20 |
18 |
Summary for Cross jtag_otp_prog_err_xp
Samples crossed: jtag_csr_cp otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_prog_err_xp
Bins
jtag_csr_cp | otp_prog_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37451 |
1 |
|
|
T1 |
86 |
|
T2 |
4 |
|
T11 |
93 |
auto[0] |
auto[1] |
1630 |
1 |
|
|
T3 |
9 |
|
T4 |
28 |
|
T66 |
6 |
auto[1] |
auto[0] |
18170 |
1 |
|
|
T4 |
864 |
|
T5 |
97 |
|
T6 |
81 |
auto[1] |
auto[1] |
1216 |
1 |
|
|
T4 |
85 |
|
T45 |
56 |
|
T212 |
19 |
Summary for Cross jtag_otp_partition_err_xp
Samples crossed: jtag_csr_cp otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_partition_err_xp
Bins
jtag_csr_cp | otp_partition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38010 |
1 |
|
|
T1 |
86 |
|
T2 |
4 |
|
T3 |
9 |
auto[0] |
auto[1] |
1071 |
1 |
|
|
T12 |
14 |
|
T16 |
14 |
|
T49 |
7 |
auto[1] |
auto[0] |
18481 |
1 |
|
|
T4 |
914 |
|
T5 |
97 |
|
T6 |
72 |
auto[1] |
auto[1] |
905 |
1 |
|
|
T4 |
35 |
|
T6 |
9 |
|
T20 |
19 |
Summary for Cross jtag_token_mismatch_err_xp
Samples crossed: jtag_csr_cp token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_token_mismatch_err_xp
Bins
jtag_csr_cp | token_mismatch_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
34175 |
1 |
|
|
T1 |
86 |
|
T2 |
4 |
|
T3 |
9 |
auto[0] |
auto[1] |
4906 |
1 |
|
|
T12 |
16 |
|
T16 |
15 |
|
T49 |
11 |
auto[1] |
auto[0] |
18531 |
1 |
|
|
T4 |
908 |
|
T5 |
97 |
|
T6 |
69 |
auto[1] |
auto[1] |
855 |
1 |
|
|
T4 |
41 |
|
T6 |
12 |
|
T20 |
18 |
Summary for Cross jtag_state_err_xp
Samples crossed: jtag_csr_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_err_xp
Bins
jtag_csr_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37930 |
1 |
|
|
T1 |
86 |
|
T2 |
4 |
|
T3 |
9 |
auto[0] |
auto[1] |
1151 |
1 |
|
|
T18 |
2 |
|
T51 |
12 |
|
T60 |
6 |
auto[1] |
auto[0] |
18410 |
1 |
|
|
T4 |
892 |
|
T5 |
82 |
|
T6 |
81 |
auto[1] |
auto[1] |
976 |
1 |
|
|
T4 |
57 |
|
T5 |
15 |
|
T20 |
16 |
Summary for Cross jtag_state_backdoor_err_xp
Samples crossed: jtag_csr_cp state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_backdoor_err_xp
Bins
jtag_csr_cp | state_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37944 |
1 |
|
|
T1 |
86 |
|
T2 |
4 |
|
T3 |
9 |
auto[0] |
auto[1] |
1137 |
1 |
|
|
T18 |
2 |
|
T51 |
10 |
|
T60 |
7 |
auto[1] |
auto[0] |
18473 |
1 |
|
|
T4 |
900 |
|
T5 |
90 |
|
T6 |
81 |
auto[1] |
auto[1] |
913 |
1 |
|
|
T4 |
49 |
|
T5 |
7 |
|
T20 |
10 |
Summary for Cross jtag_lc_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_lc_fsm_backdoor_err_xp
Bins
jtag_csr_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37886 |
1 |
|
|
T1 |
86 |
|
T2 |
4 |
|
T3 |
9 |
auto[0] |
auto[1] |
1195 |
1 |
|
|
T51 |
12 |
|
T60 |
12 |
|
T4 |
38 |
auto[1] |
auto[0] |
18414 |
1 |
|
|
T4 |
887 |
|
T5 |
82 |
|
T6 |
81 |
auto[1] |
auto[1] |
972 |
1 |
|
|
T4 |
62 |
|
T5 |
15 |
|
T20 |
20 |
Summary for Cross jtag_kmac_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_kmac_fsm_backdoor_err_xp
Bins
jtag_csr_cp | kmac_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37864 |
1 |
|
|
T1 |
86 |
|
T2 |
4 |
|
T3 |
9 |
auto[0] |
auto[1] |
1217 |
1 |
|
|
T51 |
7 |
|
T60 |
8 |
|
T4 |
37 |
auto[1] |
auto[0] |
18521 |
1 |
|
|
T4 |
911 |
|
T5 |
86 |
|
T6 |
81 |
auto[1] |
auto[1] |
865 |
1 |
|
|
T4 |
38 |
|
T5 |
11 |
|
T20 |
11 |
Summary for Cross jtag_count_err_xp
Samples crossed: jtag_csr_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_err_xp
Bins
jtag_csr_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37843 |
1 |
|
|
T1 |
86 |
|
T2 |
4 |
|
T3 |
9 |
auto[0] |
auto[1] |
1238 |
1 |
|
|
T14 |
1 |
|
T18 |
1 |
|
T51 |
8 |
auto[1] |
auto[0] |
18491 |
1 |
|
|
T4 |
898 |
|
T5 |
88 |
|
T6 |
81 |
auto[1] |
auto[1] |
895 |
1 |
|
|
T4 |
51 |
|
T5 |
9 |
|
T20 |
8 |
Summary for Cross jtag_count_backdoor_err_xp
Samples crossed: jtag_csr_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_backdoor_err_xp
Bins
jtag_csr_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37938 |
1 |
|
|
T1 |
86 |
|
T2 |
4 |
|
T3 |
9 |
auto[0] |
auto[1] |
1143 |
1 |
|
|
T14 |
1 |
|
T18 |
1 |
|
T51 |
20 |
auto[1] |
auto[0] |
18414 |
1 |
|
|
T4 |
883 |
|
T5 |
91 |
|
T6 |
81 |
auto[1] |
auto[1] |
972 |
1 |
|
|
T4 |
66 |
|
T5 |
6 |
|
T20 |
17 |
Summary for Cross jtag_transition_err_xp
Samples crossed: jtag_csr_cp transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_err_xp
Bins
jtag_csr_cp | transition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38022 |
1 |
|
|
T1 |
86 |
|
T2 |
4 |
|
T3 |
9 |
auto[0] |
auto[1] |
1059 |
1 |
|
|
T12 |
10 |
|
T16 |
8 |
|
T49 |
9 |
auto[1] |
auto[0] |
18462 |
1 |
|
|
T4 |
909 |
|
T5 |
97 |
|
T6 |
67 |
auto[1] |
auto[1] |
924 |
1 |
|
|
T4 |
40 |
|
T6 |
14 |
|
T20 |
16 |
Summary for Cross jtag_transition_count_err_xp
Samples crossed: jtag_csr_cp transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_count_err_xp
Bins
jtag_csr_cp | transition_count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37976 |
1 |
|
|
T1 |
86 |
|
T2 |
4 |
|
T3 |
9 |
auto[0] |
auto[1] |
1105 |
1 |
|
|
T12 |
6 |
|
T16 |
13 |
|
T49 |
7 |
auto[1] |
auto[0] |
18466 |
1 |
|
|
T4 |
910 |
|
T5 |
97 |
|
T6 |
74 |
auto[1] |
auto[1] |
920 |
1 |
|
|
T4 |
39 |
|
T6 |
7 |
|
T20 |
16 |
Summary for Cross jtag_post_trans_err_xp
Samples crossed: jtag_csr_cp post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_post_trans_err_xp
Bins
jtag_csr_cp | post_trans_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37626 |
1 |
|
|
T1 |
86 |
|
T2 |
4 |
|
T3 |
9 |
auto[0] |
auto[1] |
1455 |
1 |
|
|
T14 |
12 |
|
T18 |
11 |
|
T4 |
14 |
auto[1] |
auto[0] |
17948 |
1 |
|
|
T4 |
933 |
|
T5 |
97 |
|
T6 |
81 |
auto[1] |
auto[1] |
1438 |
1 |
|
|
T4 |
16 |
|
T20 |
36 |
|
T21 |
11 |