Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

114922659

1

T1

35407

T2

2353

T3

3915

auto[1]

1506700

1

T1

10328

T3

297

T11

10620

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

114925122

1

T1

34166

T2

2353

T3

3618

auto[1]

1504237

1

T1

11569

T3

594

T11

10686

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	8060367	1			T1	8305		T2	385		T3	929
auto[IdleSt]	25266455	1			T1	6872		T2	665		T3	1292
auto[ClkMuxSt]	38332	1			T1	75		T2	4		T3	9
auto[CntIncrSt]	38096	1			T1	74		T2	4		T3	9
auto[CntProgSt]	1974547	1			T1	795		T2	8		T3	18
auto[TransCheckSt]	29262	1			T1	35		T2	4		T11	38
auto[TokenHashSt]	42470776	1			T1	12919		T2	401		T11	361
auto[FlashRmaSt]	31353	1			T1	28		T2	17		T11	61
auto[TokenCheck0St]	13655	1			T1	21		T2	4		T11	29
auto[TokenCheck1St]	10166	1			T1	20		T2	4		T11	28
auto[TransProgSt]	557619	1			T1	58		T2	8		T11	90
auto[PostTransSt]	15348092	1			T1	6		T2	849		T3	727
auto[ScrapSt]	111467	1			T1	6		T11	9		T13	24
auto[EscalateSt]	8049216	1			T1	16521		T3	1228		T11	14769
auto[InvalidSt]	14427708	1			T14	153		T18	429		T51	5659

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	2248	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	14427708	1			T14	153		T18	429		T51	5659
EscalateSt	8049216	1			T1	16521		T3	1228		T11	14769
ScrapSt	111467	1			T1	6		T11	9		T13	24
PostTransSt	15348092	1			T1	6		T2	849		T3	727
TransProgSt	557619	1			T1	58		T2	8		T11	90
TokenCheck1St	10166	1			T1	20		T2	4		T11	28
TokenCheck0St	13655	1			T1	21		T2	4		T11	29
FlashRmaSt	31353	1			T1	28		T2	17		T11	61
TokenHashSt	42470776	1			T1	12919		T2	401		T11	361
TransCheckSt	29262	1			T1	35		T2	4		T11	38
CntProgSt	1974547	1			T1	795		T2	8		T3	18
CntIncrSt	38096	1			T1	74		T2	4		T3	9
ClkMuxSt	38332	1			T1	75		T2	4		T3	9
IdleSt	25266455	1			T1	6872		T2	665		T3	1292
ResetSt	8060367	1			T1	8305		T2	385		T3	929
arcs[ResetSt=>IdleSt]	58684	1			T1	84		T2	4		T3	10
arcs[IdleSt=>ScrapSt]	292	1			T1	2		T11	3		T13	1
arcs[IdleSt=>ClkMuxSt]	38155	1			T1	75		T2	4		T3	9
arcs[ClkMuxSt=>CntIncrSt]	38096	1			T1	74		T2	4		T3	9
arcs[CntIncrSt=>PostTransSt]	2030	1			T12	6		T16	13		T49	7
arcs[CntIncrSt=>CntProgSt]	35989	1			T1	72		T2	4		T3	9
arcs[CntProgSt=>PostTransSt]	5623	1			T3	9		T12	10		T16	9
arcs[CntProgSt=>TransCheckSt]	29262	1			T1	35		T2	4		T11	38
arcs[TransCheckSt=>PostTransSt]	3838	1			T12	10		T15	34		T16	8
arcs[TransCheckSt=>TokenHashSt]	25295	1			T1	34		T2	4		T11	37
arcs[TokenHashSt=>PostTransSt]	10837	1			T12	29		T15	10		T16	41
arcs[TokenHashSt=>FlashRmaSt]	13757	1			T1	26		T2	4		T11	30
arcs[FlashRmaSt=>TokenCheck0St]	13655	1			T1	21		T2	4		T11	29
arcs[TokenCheck0St=>PostTransSt]	3456	1			T12	4		T15	23		T16	9
arcs[TokenCheck0St=>TokenCheck1St]	10166	1			T1	20		T2	4		T11	28
arcs[TokenCheck1St=>PostTransSt]	664	1			T12	2		T15	17		T16	1
arcs[TransProgSt=>PostTransSt]	8601	1			T1	2		T2	4		T11	2
arcs[IdleSt=>EscalateSt]	163	1			T1	6		T39	9		T61	4
arcs[ClkMuxSt=>EscalateSt]	59	1			T1	1		T11	2		T41	1
arcs[CntIncrSt=>EscalateSt]	77	1			T1	2		T11	2		T39	4
arcs[CntProgSt=>EscalateSt]	1104	1			T1	37		T11	41		T39	32
arcs[TransCheckSt=>EscalateSt]	129	1			T1	1		T11	1		T39	2
arcs[TokenHashSt=>EscalateSt]	700	1			T1	8		T11	7		T4	3
arcs[FlashRmaSt=>EscalateSt]	102	1			T1	5		T11	1		T39	1
arcs[TokenCheck0St=>EscalateSt]	33	1			T1	1		T11	1		T41	1
arcs[TokenCheck1St=>EscalateSt]	139	1			T1	2		T11	2		T39	1
arcs[TransProgSt=>EscalateSt]	762	1			T1	16		T11	24		T39	14
arcs[PostTransSt=>EscalateSt]	5876	1			T1	2		T3	9		T11	2
arcs[InvalidSt=>EscalateSt]	15541	1			T14	2		T18	6		T51	78

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	8060196	1			T1	8304		T2	385		T3	929
auto[0]	auto[IdleSt]	25266346	1			T1	6867		T2	665		T3	1292
auto[0]	auto[ClkMuxSt]	38290	1			T1	75		T2	4		T3	9
auto[0]	auto[CntIncrSt]	38051	1			T1	72		T2	4		T3	9
auto[0]	auto[CntProgSt]	1973785	1			T1	776		T2	8		T3	18
auto[0]	auto[TransCheckSt]	29172	1			T1	34		T2	4		T11	38
auto[0]	auto[TokenHashSt]	42470312	1			T1	12912		T2	401		T11	356
auto[0]	auto[FlashRmaSt]	31283	1			T1	23		T2	17		T11	61
auto[0]	auto[TokenCheck0St]	13637	1			T1	21		T2	4		T11	28
auto[0]	auto[TokenCheck1St]	10067	1			T1	19		T2	4		T11	26
auto[0]	auto[TransProgSt]	557095	1			T1	48		T2	8		T11	74
auto[0]	auto[PostTransSt]	15345164	1			T1	4		T2	849		T3	724
auto[0]	auto[ScrapSt]	111426	1			T1	6		T11	7		T13	24
auto[0]	auto[EscalateSt]	6555639	1			T1	6246		T3	934		T11	4215
auto[0]	auto[InvalidSt]	14419948	1			T14	151		T18	426		T51	5620
auto[1]	auto[ResetSt]	171	1			T1	1		T11	6		T39	4
auto[1]	auto[IdleSt]	109	1			T1	5		T39	5		T61	3
auto[1]	auto[ClkMuxSt]	42	1			T11	2		T162	1		T209	1
auto[1]	auto[CntIncrSt]	45	1			T1	2		T11	2		T39	2
auto[1]	auto[CntProgSt]	762	1			T1	19		T11	29		T39	21
auto[1]	auto[TransCheckSt]	90	1			T1	1		T41	2		T210	1
auto[1]	auto[TokenHashSt]	464	1			T1	7		T11	5		T4	2
auto[1]	auto[FlashRmaSt]	70	1			T1	5		T39	1		T41	1
auto[1]	auto[TokenCheck0St]	18	1			T11	1		T61	2		T211	1
auto[1]	auto[TokenCheck1St]	99	1			T1	1		T11	2		T39	1
auto[1]	auto[TransProgSt]	524	1			T1	10		T11	16		T39	9
auto[1]	auto[PostTransSt]	2928	1			T1	2		T3	3		T11	1
auto[1]	auto[ScrapSt]	41	1			T11	2		T39	1		T41	2
auto[1]	auto[EscalateSt]	1493577	1			T1	10275		T3	294		T11	10554
auto[1]	auto[InvalidSt]	7760	1			T14	2		T18	3		T51	39

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	8060194	1			T1	8303		T2	385		T3	929
auto[0]	auto[IdleSt]	25266344	1			T1	6866		T2	665		T3	1292
auto[0]	auto[ClkMuxSt]	38294	1			T1	74		T2	4		T3	9
auto[0]	auto[CntIncrSt]	38042	1			T1	74		T2	4		T3	9
auto[0]	auto[CntProgSt]	1973843	1			T1	767		T2	8		T3	18
auto[0]	auto[TransCheckSt]	29179	1			T1	35		T2	4		T11	37
auto[0]	auto[TokenHashSt]	42470315	1			T1	12915		T2	401		T11	355
auto[0]	auto[FlashRmaSt]	31289	1			T1	26		T2	17		T11	60
auto[0]	auto[TokenCheck0St]	13630	1			T1	20		T2	4		T11	28
auto[0]	auto[TokenCheck1St]	10067	1			T1	18		T2	4		T11	26
auto[0]	auto[TransProgSt]	557121	1			T1	47		T2	8		T11	74
auto[0]	auto[PostTransSt]	15345071	1			T1	4		T2	849		T3	721
auto[0]	auto[ScrapSt]	111424	1			T1	4		T11	8		T13	24
auto[0]	auto[EscalateSt]	6558134	1			T1	5013		T3	640		T11	4148
auto[0]	auto[InvalidSt]	14419927	1			T14	153		T18	426		T51	5620
auto[1]	auto[ResetSt]	173	1			T1	2		T11	6		T39	5
auto[1]	auto[IdleSt]	111	1			T1	6		T39	7		T61	1
auto[1]	auto[ClkMuxSt]	38	1			T1	1		T11	1		T41	1
auto[1]	auto[CntIncrSt]	54	1			T11	1		T39	3		T41	1
auto[1]	auto[CntProgSt]	704	1			T1	28		T11	27		T39	21
auto[1]	auto[TransCheckSt]	83	1			T11	1		T39	2		T210	2
auto[1]	auto[TokenHashSt]	461	1			T1	4		T11	6		T4	1
auto[1]	auto[FlashRmaSt]	64	1			T1	2		T11	1		T41	1
auto[1]	auto[TokenCheck0St]	25	1			T1	1		T11	1		T41	1
auto[1]	auto[TokenCheck1St]	99	1			T1	2		T11	2		T39	1
auto[1]	auto[TransProgSt]	498	1			T1	11		T11	16		T39	8
auto[1]	auto[PostTransSt]	3021	1			T1	2		T3	6		T11	2
auto[1]	auto[ScrapSt]	43	1			T1	2		T11	1		T39	1
auto[1]	auto[EscalateSt]	1491082	1			T1	11508		T3	588		T11	10621
auto[1]	auto[InvalidSt]	7781	1			T18	3		T51	39		T60	21