Unified Coverage Report :: Tests

Tests

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Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.22	97.89	95.68	93.34	100.00	98.55	99.00	96.11

Total test records in report: 1004

tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html

T1001	/workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.3160116852			Jun 09 12:28:42 PM PDT 24	Jun 09 12:28:44 PM PDT 24	362141237 ps
T1002	/workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.867856543			Jun 09 12:28:35 PM PDT 24	Jun 09 12:28:39 PM PDT 24	467000604 ps
T1003	/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.208729898			Jun 09 12:29:42 PM PDT 24	Jun 09 12:29:45 PM PDT 24	94472308 ps
T1004	/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.1329920882			Jun 09 12:28:33 PM PDT 24	Jun 09 12:28:36 PM PDT 24	188664275 ps

Test location	/workspace/coverage/default/12.lc_ctrl_security_escalation.3173783364
Short name	T11
Test name
Test status
Simulation time	594795473 ps
CPU time	11.54 seconds
Started	Jun 09 02:24:53 PM PDT 24
Finished	Jun 09 02:25:05 PM PDT 24
Peak memory	218888 kb
Host	smart-dafb67ad-33c6-4f56-adf2-cac7520ae418
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3173783364 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_security_escalation.3173783364
Directory	/workspace/12.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/4.lc_ctrl_stress_all_with_rand_reset.2562209137
Short name	T4
Test name
Test status
Simulation time	134295862277 ps
CPU time	1271.53 seconds
Started	Jun 09 02:24:41 PM PDT 24
Finished	Jun 09 02:45:53 PM PDT 24
Peak memory	464572 kb
Host	smart-20c4a77c-ae43-40e0-a746-8394cecd3cf5
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=2562209137 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_stress_all_with_rand_reset.2562209137
Directory	/workspace/4.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/17.lc_ctrl_sec_mubi.3383864191
Short name	T55
Test name
Test status
Simulation time	946204203 ps
CPU time	19.55 seconds
Started	Jun 09 02:25:15 PM PDT 24
Finished	Jun 09 02:25:35 PM PDT 24
Peak memory	219516 kb
Host	smart-2c705a0f-56c6-45d3-ad38-163849a67750
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383864191 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_mubi.3383864191
Directory	/workspace/17.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/4.lc_ctrl_sec_token_mux.4035868147
Short name	T15
Test name
Test status
Simulation time	4977239591 ps
CPU time	10.89 seconds
Started	Jun 09 02:24:30 PM PDT 24
Finished	Jun 09 02:24:41 PM PDT 24
Peak memory	226580 kb
Host	smart-b42cee91-ef69-4049-a4ef-06a7cf55afd2
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035868147 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_mux.4 035868147
Directory	/workspace/4.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/27.lc_ctrl_volatile_unlock_smoke.3876313815
Short name	T52
Test name
Test status
Simulation time	26976191 ps
CPU time	1.01 seconds
Started	Jun 09 02:25:33 PM PDT 24
Finished	Jun 09 02:25:34 PM PDT 24
Peak memory	208216 kb
Host	smart-9278b653-dbe3-491c-9c11-22cdda663126
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876313815 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_c trl_volatile_unlock_smoke.3876313815
Directory	/workspace/27.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.1097657485
Short name	T116
Test name
Test status
Simulation time	75092961 ps
CPU time	2.72 seconds
Started	Jun 09 12:30:22 PM PDT 24
Finished	Jun 09 12:30:25 PM PDT 24
Peak memory	223024 kb
Host	smart-e25d23e4-9cab-4df8-a42a-dda67f1e3517
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097657485 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_intg _err.1097657485
Directory	/workspace/18.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/default/1.lc_ctrl_sec_cm.3439189739
Short name	T64
Test name
Test status
Simulation time	874628187 ps
CPU time	38.06 seconds
Started	Jun 09 02:24:27 PM PDT 24
Finished	Jun 09 02:25:05 PM PDT 24
Peak memory	271732 kb
Host	smart-8b4316b4-28ff-4872-8459-369fcbb0230c
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439189739 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_cm.3439189739
Directory	/workspace/1.lc_ctrl_sec_cm/latest

Test location	/workspace/coverage/default/40.lc_ctrl_security_escalation.813737767
Short name	T1
Test name
Test status
Simulation time	457365523 ps
CPU time	10.96 seconds
Started	Jun 09 02:26:15 PM PDT 24
Finished	Jun 09 02:26:26 PM PDT 24
Peak memory	225920 kb
Host	smart-e83afe22-6318-4ea5-abee-d6c5c0409d46
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=813737767 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_security_escalation.813737767
Directory	/workspace/40.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2598073228
Short name	T145
Test name
Test status
Simulation time	315661302 ps
CPU time	2.69 seconds
Started	Jun 09 12:28:39 PM PDT 24
Finished	Jun 09 12:28:42 PM PDT 24
Peak memory	218200 kb
Host	smart-346a6b2c-0870-4fed-b441-4e2789c69c55
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259807 3228 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2598073228
Directory	/workspace/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/default/16.lc_ctrl_jtag_access.3772064501
Short name	T8
Test name
Test status
Simulation time	2576059989 ps
CPU time	12.78 seconds
Started	Jun 09 02:25:23 PM PDT 24
Finished	Jun 09 02:25:36 PM PDT 24
Peak memory	218180 kb
Host	smart-4decaed8-1de3-4d5f-92b7-9e9741ddd027
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772064501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_access.3772064501
Directory	/workspace/16.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/15.lc_ctrl_alert_test.3449034670
Short name	T68
Test name
Test status
Simulation time	52761078 ps
CPU time	1.02 seconds
Started	Jun 09 02:25:25 PM PDT 24
Finished	Jun 09 02:25:27 PM PDT 24
Peak memory	209464 kb
Host	smart-0d00fb35-30ba-424c-adb2-379e7c60427b
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449034670 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_alert_test.3449034670
Directory	/workspace/15.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/32.lc_ctrl_errors.3489211052
Short name	T163
Test name
Test status
Simulation time	362288588 ps
CPU time	10.08 seconds
Started	Jun 09 02:25:47 PM PDT 24
Finished	Jun 09 02:25:57 PM PDT 24
Peak memory	218708 kb
Host	smart-8af84dfa-5b88-494e-9deb-a962d74b3b66
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3489211052 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_errors.3489211052
Directory	/workspace/32.lc_ctrl_errors/latest

Test location	/workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.4213034191
Short name	T185
Test name
Test status
Simulation time	17606702 ps
CPU time	0.83 seconds
Started	Jun 09 12:28:55 PM PDT 24
Finished	Jun 09 12:28:56 PM PDT 24
Peak memory	209632 kb
Host	smart-3cdfb93f-0ef2-4e7a-b3e0-8556a22b455c
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213034191 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_csr_rw.4213034191
Directory	/workspace/10.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.3945260831
Short name	T123
Test name
Test status
Simulation time	30955997 ps
CPU time	2.14 seconds
Started	Jun 09 12:28:45 PM PDT 24
Finished	Jun 09 12:28:48 PM PDT 24
Peak memory	218100 kb
Host	smart-758ed3fe-7ab0-4370-8e2c-b76e693821af
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945260831 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_errors.3945260831
Directory	/workspace/8.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/default/28.lc_ctrl_errors.236526244
Short name	T16
Test name
Test status
Simulation time	309307618 ps
CPU time	14.57 seconds
Started	Jun 09 02:25:38 PM PDT 24
Finished	Jun 09 02:25:53 PM PDT 24
Peak memory	218680 kb
Host	smart-21428b29-491e-43ae-a24d-347062e67b17
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=236526244 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_errors.236526244
Directory	/workspace/28.lc_ctrl_errors/latest

Test location	/workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.4042630537
Short name	T130
Test name
Test status
Simulation time	619690069 ps
CPU time	2.79 seconds
Started	Jun 09 12:28:43 PM PDT 24
Finished	Jun 09 12:28:46 PM PDT 24
Peak memory	222564 kb
Host	smart-45232384-f5ed-4eba-a828-65ee2eec5b2a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042630537 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_intg_ err.4042630537
Directory	/workspace/4.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/default/12.lc_ctrl_stress_all_with_rand_reset.3863076639
Short name	T88
Test name
Test status
Simulation time	43592508574 ps
CPU time	720 seconds
Started	Jun 09 02:25:10 PM PDT 24
Finished	Jun 09 02:37:11 PM PDT 24
Peak memory	497308 kb
Host	smart-2d1eb45f-50d1-48dd-a8ca-cd63a59186f6
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=3863076639 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_stress_all_with_rand_reset.3863076639
Directory	/workspace/12.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/39.lc_ctrl_volatile_unlock_smoke.1198244576
Short name	T17
Test name
Test status
Simulation time	13430402 ps
CPU time	0.96 seconds
Started	Jun 09 02:26:04 PM PDT 24
Finished	Jun 09 02:26:05 PM PDT 24
Peak memory	209676 kb
Host	smart-ae906676-e130-4a54-8764-c2d4f26d19f5
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198244576 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_c trl_volatile_unlock_smoke.1198244576
Directory	/workspace/39.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.3601358720
Short name	T125
Test name
Test status
Simulation time	623161789 ps
CPU time	2.85 seconds
Started	Jun 09 12:28:48 PM PDT 24
Finished	Jun 09 12:28:51 PM PDT 24
Peak memory	222916 kb
Host	smart-db3c99e1-3920-4992-b347-d763cfe50aaa
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601358720 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_intg _err.3601358720
Directory	/workspace/12.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.2749467384
Short name	T135
Test name
Test status
Simulation time	134696760 ps
CPU time	3.27 seconds
Started	Jun 09 12:29:00 PM PDT 24
Finished	Jun 09 12:29:05 PM PDT 24
Peak memory	218068 kb
Host	smart-644d137b-dece-46fc-9fc7-fb03c7c13e34
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749467384 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_errors.2749467384
Directory	/workspace/12.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.2049332222
Short name	T131
Test name
Test status
Simulation time	42179988 ps
CPU time	2.12 seconds
Started	Jun 09 12:28:49 PM PDT 24
Finished	Jun 09 12:28:52 PM PDT 24
Peak memory	218008 kb
Host	smart-3f8f957c-7059-46a7-a457-5c3e4947dcf3
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049332222 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_intg _err.2049332222
Directory	/workspace/13.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.1921462462
Short name	T129
Test name
Test status
Simulation time	475538145 ps
CPU time	2.88 seconds
Started	Jun 09 12:28:48 PM PDT 24
Finished	Jun 09 12:28:51 PM PDT 24
Peak memory	222572 kb
Host	smart-d10ae353-92cc-4a06-8bbc-cfd1e6425a3f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921462462 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_intg_ err.1921462462
Directory	/workspace/9.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.3131205979
Short name	T195
Test name
Test status
Simulation time	117216326 ps
CPU time	1.37 seconds
Started	Jun 09 12:28:52 PM PDT 24
Finished	Jun 09 12:28:54 PM PDT 24
Peak memory	209860 kb
Host	smart-04f3fea5-fef5-4880-b2d4-e8156fa5dc90
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131205979 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctr l_same_csr_outstanding.3131205979
Directory	/workspace/10.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/default/19.lc_ctrl_errors.654784897
Short name	T12
Test name
Test status
Simulation time	1355981106 ps
CPU time	16.47 seconds
Started	Jun 09 02:25:36 PM PDT 24
Finished	Jun 09 02:25:53 PM PDT 24
Peak memory	218692 kb
Host	smart-108e0308-755c-43ed-a174-c983b4ecab7d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=654784897 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_errors.654784897
Directory	/workspace/19.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/11.lc_ctrl_security_escalation.3262243605
Short name	T318
Test name
Test status
Simulation time	1550203046 ps
CPU time	14.39 seconds
Started	Jun 09 02:24:48 PM PDT 24
Finished	Jun 09 02:25:03 PM PDT 24
Peak memory	226532 kb
Host	smart-d8c7a779-deaf-4ef8-8c6a-1738773ec2d0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3262243605 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_security_escalation.3262243605
Directory	/workspace/11.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/0.lc_ctrl_claim_transition_if.4260528157
Short name	T205
Test name
Test status
Simulation time	38250564 ps
CPU time	0.94 seconds
Started	Jun 09 02:24:17 PM PDT 24
Finished	Jun 09 02:24:18 PM PDT 24
Peak memory	209392 kb
Host	smart-d2888d4d-9f5e-4638-8fb7-e85827757337
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4260528157 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_claim_transition_if.4260528157
Directory	/workspace/0.lc_ctrl_claim_transition_if/latest

Test location	/workspace/coverage/default/2.lc_ctrl_claim_transition_if.4245461749
Short name	T206
Test name
Test status
Simulation time	11474343 ps
CPU time	1.01 seconds
Started	Jun 09 02:24:27 PM PDT 24
Finished	Jun 09 02:24:28 PM PDT 24
Peak memory	209496 kb
Host	smart-89673d8f-a4d6-4e42-9130-4eaba060542c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4245461749 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_claim_transition_if.4245461749
Directory	/workspace/2.lc_ctrl_claim_transition_if/latest

Test location	/workspace/coverage/default/3.lc_ctrl_claim_transition_if.1311139648
Short name	T204
Test name
Test status
Simulation time	36752998 ps
CPU time	0.81 seconds
Started	Jun 09 02:24:31 PM PDT 24
Finished	Jun 09 02:24:32 PM PDT 24
Peak memory	209420 kb
Host	smart-5a653e49-501b-4c3a-af26-59a6b90b8936
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1311139648 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_claim_transition_if.1311139648
Directory	/workspace/3.lc_ctrl_claim_transition_if/latest

Test location	/workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.138412525
Short name	T112
Test name
Test status
Simulation time	59846649 ps
CPU time	1.96 seconds
Started	Jun 09 12:28:35 PM PDT 24
Finished	Jun 09 12:28:38 PM PDT 24
Peak memory	222548 kb
Host	smart-ebcf6e15-0ebc-41f7-b1ae-75e090ed053d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138412525 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_intg_e rr.138412525
Directory	/workspace/1.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.3264978088
Short name	T136
Test name
Test status
Simulation time	117082969 ps
CPU time	2.73 seconds
Started	Jun 09 12:28:52 PM PDT 24
Finished	Jun 09 12:28:55 PM PDT 24
Peak memory	218036 kb
Host	smart-a52d0031-a4a9-44c8-9483-93935b735567
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264978088 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_intg _err.3264978088
Directory	/workspace/10.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.366558529
Short name	T138
Test name
Test status
Simulation time	211457287 ps
CPU time	1.89 seconds
Started	Jun 09 12:29:00 PM PDT 24
Finished	Jun 09 12:29:03 PM PDT 24
Peak memory	222492 kb
Host	smart-4538f497-316d-459c-b926-e34b22f9b8f1
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366558529 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_intg_ err.366558529
Directory	/workspace/16.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.311098111
Short name	T137
Test name
Test status
Simulation time	126766052 ps
CPU time	2.51 seconds
Started	Jun 09 12:28:53 PM PDT 24
Finished	Jun 09 12:28:56 PM PDT 24
Peak memory	218060 kb
Host	smart-9bc1cf95-3bb8-4d4b-88a0-baf08b317923
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311098111 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_intg_ err.311098111
Directory	/workspace/19.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.518567653
Short name	T945
Test name
Test status
Simulation time	282821925 ps
CPU time	2.73 seconds
Started	Jun 09 12:28:33 PM PDT 24
Finished	Jun 09 12:28:37 PM PDT 24
Peak memory	219276 kb
Host	smart-76d77cd2-99d9-480d-b7bc-01311ddc3b58
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518567 653 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.518567653
Directory	/workspace/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.2221451892
Short name	T139
Test name
Test status
Simulation time	131093637 ps
CPU time	3.31 seconds
Started	Jun 09 12:28:41 PM PDT 24
Finished	Jun 09 12:28:45 PM PDT 24
Peak memory	223048 kb
Host	smart-1f3b0710-13d3-4775-966d-2215d7e32d82
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221451892 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_intg_ err.2221451892
Directory	/workspace/2.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.73475502
Short name	T124
Test name
Test status
Simulation time	122389390 ps
CPU time	3.21 seconds
Started	Jun 09 12:28:36 PM PDT 24
Finished	Jun 09 12:28:41 PM PDT 24
Peak memory	222288 kb
Host	smart-8a54470b-b9be-4fb1-86d9-a1c56d1da249
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73475502 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_intg_er r.73475502
Directory	/workspace/3.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.63808379
Short name	T140
Test name
Test status
Simulation time	293813872 ps
CPU time	3.47 seconds
Started	Jun 09 12:29:42 PM PDT 24
Finished	Jun 09 12:29:46 PM PDT 24
Peak memory	222536 kb
Host	smart-304b67d7-060b-45f4-b0eb-63bb8f11edc8
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63808379 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_intg_er r.63808379
Directory	/workspace/7.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/default/15.lc_ctrl_stress_all.2373134287
Short name	T59
Test name
Test status
Simulation time	4597616492 ps
CPU time	101.44 seconds
Started	Jun 09 02:25:30 PM PDT 24
Finished	Jun 09 02:27:12 PM PDT 24
Peak memory	277732 kb
Host	smart-d85cbbc6-f461-47d7-85d1-6dd9a93fd31f
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373134287 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_stress_all.2373134287
Directory	/workspace/15.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/26.lc_ctrl_stress_all_with_rand_reset.1805262890
Short name	T58
Test name
Test status
Simulation time	22616279156 ps
CPU time	780.82 seconds
Started	Jun 09 02:25:36 PM PDT 24
Finished	Jun 09 02:38:37 PM PDT 24
Peak memory	268208 kb
Host	smart-3843eb05-4e23-494a-b3b6-fcc4344ea959
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=1805262890 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_stress_all_with_rand_reset.1805262890
Directory	/workspace/26.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/6.lc_ctrl_regwen_during_op.1577803106
Short name	T27
Test name
Test status
Simulation time	225816475 ps
CPU time	5.51 seconds
Started	Jun 09 02:24:40 PM PDT 24
Finished	Jun 09 02:24:46 PM PDT 24
Peak memory	214968 kb
Host	smart-f904c6ce-9b0a-4557-944b-191eb79f0710
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1577803106 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_regwen_during_op.1577803106
Directory	/workspace/6.lc_ctrl_regwen_during_op/latest

Test location	/workspace/coverage/default/11.lc_ctrl_jtag_state_post_trans.279223551
Short name	T21
Test name
Test status
Simulation time	1360075622 ps
CPU time	15.76 seconds
Started	Jun 09 02:25:08 PM PDT 24
Finished	Jun 09 02:25:24 PM PDT 24
Peak memory	251392 kb
Host	smart-9bbdba94-0b4e-4a46-ae54-59e0337bae38
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279223551 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_ jtag_state_post_trans.279223551
Directory	/workspace/11.lc_ctrl_jtag_state_post_trans/latest

Test location	/workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.354233896
Short name	T183
Test name
Test status
Simulation time	44886964 ps
CPU time	1.09 seconds
Started	Jun 09 12:28:30 PM PDT 24
Finished	Jun 09 12:28:32 PM PDT 24
Peak memory	209804 kb
Host	smart-88a747a9-74f5-4e62-94d2-ed0f31714f67
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354233896 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_aliasing .354233896
Directory	/workspace/0.lc_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.3683264748
Short name	T884
Test name
Test status
Simulation time	60474750 ps
CPU time	1.3 seconds
Started	Jun 09 12:28:33 PM PDT 24
Finished	Jun 09 12:28:35 PM PDT 24
Peak memory	209464 kb
Host	smart-d4075801-bf79-4790-bdab-130653dd4a6e
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683264748 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_bit_bas h.3683264748
Directory	/workspace/0.lc_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.404837218
Short name	T959
Test name
Test status
Simulation time	153595191 ps
CPU time	1.06 seconds
Started	Jun 09 12:28:32 PM PDT 24
Finished	Jun 09 12:28:34 PM PDT 24
Peak memory	210336 kb
Host	smart-ce63d338-30ef-4035-a7bd-34f03619d8e1
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404837218 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_hw_reset .404837218
Directory	/workspace/0.lc_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.360876804
Short name	T115
Test name
Test status
Simulation time	222193529 ps
CPU time	1.43 seconds
Started	Jun 09 12:28:24 PM PDT 24
Finished	Jun 09 12:28:25 PM PDT 24
Peak memory	218636 kb
Host	smart-d5dd3dba-1380-4431-b54b-71c2527b303f
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360876804 -assert nopostproc +UVM_TESTNAME= lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 0.lc_ctrl_csr_mem_rw_with_rand_reset.360876804
Directory	/workspace/0.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.3382453125
Short name	T192
Test name
Test status
Simulation time	46420334 ps
CPU time	0.98 seconds
Started	Jun 09 12:28:23 PM PDT 24
Finished	Jun 09 12:28:24 PM PDT 24
Peak memory	209784 kb
Host	smart-fb8f81e5-7ade-4f1f-bb71-7140a6153bf0
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382453125 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_rw.3382453125
Directory	/workspace/0.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.1971726617
Short name	T956
Test name
Test status
Simulation time	31257058 ps
CPU time	1.42 seconds
Started	Jun 09 12:28:12 PM PDT 24
Finished	Jun 09 12:28:14 PM PDT 24
Peak memory	209240 kb
Host	smart-56e9fa05-db41-4e38-b8f2-fedcd06723a3
User	root
Command	/workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971726617 -assert nopostproc +UVM_TESTNAME=lc_ctrl _base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 0.lc_ctrl_jtag_alert_test.1971726617
Directory	/workspace/0.lc_ctrl_jtag_alert_test/latest

Test location	/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.2952861646
Short name	T885
Test name
Test status
Simulation time	2160975434 ps
CPU time	6.74 seconds
Started	Jun 09 12:28:30 PM PDT 24
Finished	Jun 09 12:28:37 PM PDT 24
Peak memory	209500 kb
Host	smart-516225e2-94bd-43e2-848a-78e566d41f66
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952861646 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 0.lc_ctrl_jtag_csr_aliasing.2952861646
Directory	/workspace/0.lc_ctrl_jtag_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.2190926697
Short name	T898
Test name
Test status
Simulation time	1383277749 ps
CPU time	12.47 seconds
Started	Jun 09 12:28:21 PM PDT 24
Finished	Jun 09 12:28:34 PM PDT 24
Peak memory	209332 kb
Host	smart-993c3886-682c-4fbf-bf96-8dcc66f3385f
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190926697 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 0.lc_ctrl_jtag_csr_bit_bash.2190926697
Directory	/workspace/0.lc_ctrl_jtag_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.2129478697
Short name	T907
Test name
Test status
Simulation time	260125107 ps
CPU time	2.57 seconds
Started	Jun 09 12:28:18 PM PDT 24
Finished	Jun 09 12:28:21 PM PDT 24
Peak memory	211544 kb
Host	smart-4fd123ad-b798-46ff-9bb2-3dfc7826e580
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129478697 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 0.lc_ctrl_jtag_csr_hw_reset.2129478697
Directory	/workspace/0.lc_ctrl_jtag_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2719308530
Short name	T988
Test name
Test status
Simulation time	512539959 ps
CPU time	2.37 seconds
Started	Jun 09 12:28:31 PM PDT 24
Finished	Jun 09 12:28:34 PM PDT 24
Peak memory	219140 kb
Host	smart-0519ed02-3670-4634-a25d-f9636f64d293
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271930 8530 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2719308530
Directory	/workspace/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.824055106
Short name	T887
Test name
Test status
Simulation time	126856786 ps
CPU time	2.18 seconds
Started	Jun 09 12:28:29 PM PDT 24
Finished	Jun 09 12:28:32 PM PDT 24
Peak memory	209708 kb
Host	smart-936f961d-dbbb-4fc9-9b76-ff843c125240
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824055106 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_csr_rw.824055106
Directory	/workspace/0.lc_ctrl_jtag_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.3833859291
Short name	T918
Test name
Test status
Simulation time	24220140 ps
CPU time	1.21 seconds
Started	Jun 09 12:28:29 PM PDT 24
Finished	Jun 09 12:28:31 PM PDT 24
Peak memory	211896 kb
Host	smart-244346e8-60a0-4054-aa20-66fcc456a37d
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833859291 -assert nopostproc +UVM_TESTNA ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_same_csr_outstanding.3833859291
Directory	/workspace/0.lc_ctrl_jtag_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.4212619635
Short name	T911
Test name
Test status
Simulation time	165362337 ps
CPU time	1.78 seconds
Started	Jun 09 12:28:31 PM PDT 24
Finished	Jun 09 12:28:33 PM PDT 24
Peak memory	217752 kb
Host	smart-99253b73-f939-4155-a48b-03a972d213ed
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212619635 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl _same_csr_outstanding.4212619635
Directory	/workspace/0.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.1181544689
Short name	T924
Test name
Test status
Simulation time	88919164 ps
CPU time	2.88 seconds
Started	Jun 09 12:28:29 PM PDT 24
Finished	Jun 09 12:28:32 PM PDT 24
Peak memory	218740 kb
Host	smart-37cb7193-62d3-462a-9fbc-5205fe781833
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181544689 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_errors.1181544689
Directory	/workspace/0.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.3852324951
Short name	T987
Test name
Test status
Simulation time	169756477 ps
CPU time	2.21 seconds
Started	Jun 09 12:28:35 PM PDT 24
Finished	Jun 09 12:28:38 PM PDT 24
Peak memory	218112 kb
Host	smart-64130fde-622c-48bb-abba-f99e13eafb30
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852324951 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_intg_ err.3852324951
Directory	/workspace/0.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.3847859682
Short name	T899
Test name
Test status
Simulation time	43130635 ps
CPU time	1.07 seconds
Started	Jun 09 12:28:43 PM PDT 24
Finished	Jun 09 12:28:45 PM PDT 24
Peak memory	217600 kb
Host	smart-ec9bcc9f-1e1b-4bca-802e-65dfe491b545
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847859682 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_aliasin g.3847859682
Directory	/workspace/1.lc_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.2911901554
Short name	T983
Test name
Test status
Simulation time	137767313 ps
CPU time	1.29 seconds
Started	Jun 09 12:28:40 PM PDT 24
Finished	Jun 09 12:28:43 PM PDT 24
Peak memory	209952 kb
Host	smart-f70cfc84-a086-498f-9e1c-36b397d15aac
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911901554 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_bit_bas h.2911901554
Directory	/workspace/1.lc_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.3190646971
Short name	T180
Test name
Test status
Simulation time	17785049 ps
CPU time	1.19 seconds
Started	Jun 09 12:28:35 PM PDT 24
Finished	Jun 09 12:28:37 PM PDT 24
Peak memory	211912 kb
Host	smart-a331bc03-cbbe-4cc4-8ef6-2768f26f3b8f
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190646971 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_hw_rese t.3190646971
Directory	/workspace/1.lc_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.2108886605
Short name	T897
Test name
Test status
Simulation time	59381139 ps
CPU time	0.97 seconds
Started	Jun 09 12:28:39 PM PDT 24
Finished	Jun 09 12:28:41 PM PDT 24
Peak memory	218184 kb
Host	smart-a79153e2-9a8f-4105-85c6-5fef0b62a685
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108886605 -assert nopostproc +UVM_TESTNAME =lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 1.lc_ctrl_csr_mem_rw_with_rand_reset.2108886605
Directory	/workspace/1.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.2684052387
Short name	T878
Test name
Test status
Simulation time	25336422 ps
CPU time	0.86 seconds
Started	Jun 09 12:28:30 PM PDT 24
Finished	Jun 09 12:28:32 PM PDT 24
Peak memory	209780 kb
Host	smart-a129793a-4514-4912-bd7c-5c16c7566614
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684052387 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_rw.2684052387
Directory	/workspace/1.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.3747492227
Short name	T906
Test name
Test status
Simulation time	31897981 ps
CPU time	1.08 seconds
Started	Jun 09 12:28:34 PM PDT 24
Finished	Jun 09 12:28:37 PM PDT 24
Peak memory	209684 kb
Host	smart-ba50acdd-17d6-4c83-83a5-78b3204ffa48
User	root
Command	/workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747492227 -assert nopostproc +UVM_TESTNAME=lc_ctrl _base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 1.lc_ctrl_jtag_alert_test.3747492227
Directory	/workspace/1.lc_ctrl_jtag_alert_test/latest

Test location	/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.701608181
Short name	T973
Test name
Test status
Simulation time	1752878606 ps
CPU time	6.91 seconds
Started	Jun 09 12:28:40 PM PDT 24
Finished	Jun 09 12:28:48 PM PDT 24
Peak memory	209856 kb
Host	smart-a96d7abb-fecd-47d0-93de-76b5351f7cd0
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701608181 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 1.lc_ctrl_jtag_csr_aliasing.701608181
Directory	/workspace/1.lc_ctrl_jtag_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.2409032656
Short name	T953
Test name
Test status
Simulation time	1507601406 ps
CPU time	19.88 seconds
Started	Jun 09 12:28:30 PM PDT 24
Finished	Jun 09 12:28:50 PM PDT 24
Peak memory	209716 kb
Host	smart-39ca9417-c3ea-4a17-bb44-cf7db4f452ee
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409032656 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 1.lc_ctrl_jtag_csr_bit_bash.2409032656
Directory	/workspace/1.lc_ctrl_jtag_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.3031470895
Short name	T894
Test name
Test status
Simulation time	325065901 ps
CPU time	3.24 seconds
Started	Jun 09 12:28:33 PM PDT 24
Finished	Jun 09 12:28:37 PM PDT 24
Peak memory	211144 kb
Host	smart-a97adeaf-852d-41b1-bed3-6383f7c0ff83
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031470895 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 1.lc_ctrl_jtag_csr_hw_reset.3031470895
Directory	/workspace/1.lc_ctrl_jtag_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1750220761
Short name	T905
Test name
Test status
Simulation time	892058590 ps
CPU time	3.45 seconds
Started	Jun 09 12:28:34 PM PDT 24
Finished	Jun 09 12:28:39 PM PDT 24
Peak memory	219140 kb
Host	smart-b1dc3fea-6d01-4ac5-a0ac-5d1ecf8c1753
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175022 0761 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1750220761
Directory	/workspace/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.3706582371
Short name	T917
Test name
Test status
Simulation time	286365247 ps
CPU time	1.51 seconds
Started	Jun 09 12:28:29 PM PDT 24
Finished	Jun 09 12:28:31 PM PDT 24
Peak memory	217740 kb
Host	smart-066bc7d5-519c-476a-85bd-3815a8fe47d7
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706582371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_csr_rw.3706582371
Directory	/workspace/1.lc_ctrl_jtag_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.2885016366
Short name	T962
Test name
Test status
Simulation time	26125967 ps
CPU time	1.23 seconds
Started	Jun 09 12:28:32 PM PDT 24
Finished	Jun 09 12:28:34 PM PDT 24
Peak memory	218152 kb
Host	smart-53d48329-ca07-467f-9852-c3b3d608deba
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885016366 -assert nopostproc +UVM_TESTNA ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_same_csr_outstanding.2885016366
Directory	/workspace/1.lc_ctrl_jtag_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.1937974976
Short name	T958
Test name
Test status
Simulation time	40701705 ps
CPU time	1.38 seconds
Started	Jun 09 12:28:39 PM PDT 24
Finished	Jun 09 12:28:41 PM PDT 24
Peak memory	211840 kb
Host	smart-cb5bcf9b-8938-4ce1-ae69-a2582b2d7732
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937974976 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl _same_csr_outstanding.1937974976
Directory	/workspace/1.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.1714214474
Short name	T933
Test name
Test status
Simulation time	442293270 ps
CPU time	2.72 seconds
Started	Jun 09 12:28:30 PM PDT 24
Finished	Jun 09 12:28:33 PM PDT 24
Peak memory	218944 kb
Host	smart-f0db34a7-8e69-4928-8080-6fd9462df74d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714214474 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_errors.1714214474
Directory	/workspace/1.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.2213009752
Short name	T935
Test name
Test status
Simulation time	26996101 ps
CPU time	1.27 seconds
Started	Jun 09 12:28:53 PM PDT 24
Finished	Jun 09 12:28:54 PM PDT 24
Peak memory	218260 kb
Host	smart-4a27a9b3-485e-4060-baef-d719461bc04f
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213009752 -assert nopostproc +UVM_TESTNAME =lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 10.lc_ctrl_csr_mem_rw_with_rand_reset.2213009752
Directory	/workspace/10.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.2298369167
Short name	T934
Test name
Test status
Simulation time	260667387 ps
CPU time	2.07 seconds
Started	Jun 09 12:30:14 PM PDT 24
Finished	Jun 09 12:30:17 PM PDT 24
Peak memory	218520 kb
Host	smart-533f1ac3-d834-4ffe-91f5-e31a9df4b4dc
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298369167 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_errors.2298369167
Directory	/workspace/10.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.1583316392
Short name	T903
Test name
Test status
Simulation time	23698443 ps
CPU time	1.32 seconds
Started	Jun 09 12:30:02 PM PDT 24
Finished	Jun 09 12:30:03 PM PDT 24
Peak memory	218104 kb
Host	smart-addcd8fe-ef43-4546-8de4-fa532ab6f3cd
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583316392 -assert nopostproc +UVM_TESTNAME =lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 11.lc_ctrl_csr_mem_rw_with_rand_reset.1583316392
Directory	/workspace/11.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.2398974581
Short name	T890
Test name
Test status
Simulation time	29151609 ps
CPU time	0.88 seconds
Started	Jun 09 12:29:57 PM PDT 24
Finished	Jun 09 12:29:58 PM PDT 24
Peak memory	209420 kb
Host	smart-c664ee45-2197-4345-beae-4e7fb5218e47
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398974581 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_csr_rw.2398974581
Directory	/workspace/11.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.3411409031
Short name	T922
Test name
Test status
Simulation time	75166020 ps
CPU time	1.22 seconds
Started	Jun 09 12:30:02 PM PDT 24
Finished	Jun 09 12:30:04 PM PDT 24
Peak memory	209780 kb
Host	smart-060f193a-d47f-4a4b-b9ff-e6f56d488bd6
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411409031 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctr l_same_csr_outstanding.3411409031
Directory	/workspace/11.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.1360653217
Short name	T972
Test name
Test status
Simulation time	499295420 ps
CPU time	3.36 seconds
Started	Jun 09 12:28:47 PM PDT 24
Finished	Jun 09 12:28:50 PM PDT 24
Peak memory	218108 kb
Host	smart-62f9ed43-1a69-4bae-a771-0e93e8d58ad3
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360653217 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_errors.1360653217
Directory	/workspace/11.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.1675069387
Short name	T128
Test name
Test status
Simulation time	277189505 ps
CPU time	2.05 seconds
Started	Jun 09 12:28:48 PM PDT 24
Finished	Jun 09 12:28:51 PM PDT 24
Peak memory	222528 kb
Host	smart-637975c0-5ea0-409f-9e3c-980fbdea6be8
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675069387 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_intg _err.1675069387
Directory	/workspace/11.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.1688988067
Short name	T999
Test name
Test status
Simulation time	109329805 ps
CPU time	1.23 seconds
Started	Jun 09 12:28:53 PM PDT 24
Finished	Jun 09 12:28:54 PM PDT 24
Peak memory	219304 kb
Host	smart-acfe9450-bc14-4c40-bc9d-c94ed71141ce
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688988067 -assert nopostproc +UVM_TESTNAME =lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 12.lc_ctrl_csr_mem_rw_with_rand_reset.1688988067
Directory	/workspace/12.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.1856770162
Short name	T194
Test name
Test status
Simulation time	28628937 ps
CPU time	1.01 seconds
Started	Jun 09 12:28:46 PM PDT 24
Finished	Jun 09 12:28:48 PM PDT 24
Peak memory	210096 kb
Host	smart-8fa1159e-d043-4a1a-901d-bbca87e60aca
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856770162 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_csr_rw.1856770162
Directory	/workspace/12.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.3494430920
Short name	T991
Test name
Test status
Simulation time	50869214 ps
CPU time	1.52 seconds
Started	Jun 09 12:28:53 PM PDT 24
Finished	Jun 09 12:28:55 PM PDT 24
Peak memory	209888 kb
Host	smart-6037abe3-b8f3-4db2-bba6-207b1b3948e3
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494430920 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctr l_same_csr_outstanding.3494430920
Directory	/workspace/12.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.2941473846
Short name	T955
Test name
Test status
Simulation time	51201277 ps
CPU time	1 seconds
Started	Jun 09 12:29:00 PM PDT 24
Finished	Jun 09 12:29:03 PM PDT 24
Peak memory	218132 kb
Host	smart-c1cfb932-9ad9-4c0a-b4bf-e7fcdc29df0a
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941473846 -assert nopostproc +UVM_TESTNAME =lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 13.lc_ctrl_csr_mem_rw_with_rand_reset.2941473846
Directory	/workspace/13.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.530037589
Short name	T190
Test name
Test status
Simulation time	17896322 ps
CPU time	1.02 seconds
Started	Jun 09 12:29:53 PM PDT 24
Finished	Jun 09 12:29:54 PM PDT 24
Peak memory	208948 kb
Host	smart-1e89b2aa-5313-4a58-9847-9f8c81827a35
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530037589 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_csr_rw.530037589
Directory	/workspace/13.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.1745581635
Short name	T912
Test name
Test status
Simulation time	106727266 ps
CPU time	1.27 seconds
Started	Jun 09 12:29:56 PM PDT 24
Finished	Jun 09 12:29:58 PM PDT 24
Peak memory	209776 kb
Host	smart-8fd9dc54-3dc4-49e9-b66a-ca95b0bb2ae6
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745581635 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctr l_same_csr_outstanding.1745581635
Directory	/workspace/13.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.2274030191
Short name	T132
Test name
Test status
Simulation time	432678818 ps
CPU time	3.04 seconds
Started	Jun 09 12:29:00 PM PDT 24
Finished	Jun 09 12:29:05 PM PDT 24
Peak memory	218160 kb
Host	smart-f69ab2ad-e111-47c8-9ff4-dcfbee4d7062
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274030191 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_errors.2274030191
Directory	/workspace/13.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.1359155259
Short name	T992
Test name
Test status
Simulation time	211167067 ps
CPU time	1.4 seconds
Started	Jun 09 12:28:53 PM PDT 24
Finished	Jun 09 12:28:54 PM PDT 24
Peak memory	218140 kb
Host	smart-0c4b3d38-5335-4463-af24-97d2acef1100
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359155259 -assert nopostproc +UVM_TESTNAME =lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 14.lc_ctrl_csr_mem_rw_with_rand_reset.1359155259
Directory	/workspace/14.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.1196887507
Short name	T189
Test name
Test status
Simulation time	49854251 ps
CPU time	0.88 seconds
Started	Jun 09 12:28:51 PM PDT 24
Finished	Jun 09 12:28:53 PM PDT 24
Peak memory	209424 kb
Host	smart-580da119-9fa2-45d0-8154-738ab913963b
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196887507 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_csr_rw.1196887507
Directory	/workspace/14.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.472359204
Short name	T121
Test name
Test status
Simulation time	208604285 ps
CPU time	1.32 seconds
Started	Jun 09 12:28:45 PM PDT 24
Finished	Jun 09 12:28:47 PM PDT 24
Peak memory	209856 kb
Host	smart-da6f6fd1-2dfc-4401-82de-0537cead06d5
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472359204 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl _same_csr_outstanding.472359204
Directory	/workspace/14.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.619300802
Short name	T893
Test name
Test status
Simulation time	478223476 ps
CPU time	2.18 seconds
Started	Jun 09 12:29:00 PM PDT 24
Finished	Jun 09 12:29:08 PM PDT 24
Peak memory	218072 kb
Host	smart-7009884e-9b3e-4276-97a9-f54b997e457f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619300802 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_errors.619300802
Directory	/workspace/14.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.980307094
Short name	T968
Test name
Test status
Simulation time	73946421 ps
CPU time	2.51 seconds
Started	Jun 09 12:29:57 PM PDT 24
Finished	Jun 09 12:30:00 PM PDT 24
Peak memory	222752 kb
Host	smart-9ef8d280-430e-45df-99d1-78516f70bd19
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980307094 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_intg_ err.980307094
Directory	/workspace/14.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.3841785379
Short name	T941
Test name
Test status
Simulation time	40968514 ps
CPU time	1.45 seconds
Started	Jun 09 12:28:48 PM PDT 24
Finished	Jun 09 12:28:50 PM PDT 24
Peak memory	218328 kb
Host	smart-f46f3a50-81c9-4ebf-82a3-7e9c28f7817d
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841785379 -assert nopostproc +UVM_TESTNAME =lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 15.lc_ctrl_csr_mem_rw_with_rand_reset.3841785379
Directory	/workspace/15.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.1243694377
Short name	T936
Test name
Test status
Simulation time	23141586 ps
CPU time	0.85 seconds
Started	Jun 09 12:28:52 PM PDT 24
Finished	Jun 09 12:28:54 PM PDT 24
Peak memory	209628 kb
Host	smart-65b0d27f-f742-4351-8f85-61dffbb66b16
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243694377 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_csr_rw.1243694377
Directory	/workspace/15.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.2739413755
Short name	T995
Test name
Test status
Simulation time	126658622 ps
CPU time	1.47 seconds
Started	Jun 09 12:28:50 PM PDT 24
Finished	Jun 09 12:28:52 PM PDT 24
Peak memory	217868 kb
Host	smart-5f8e9a61-ec79-450e-ae20-1dd9212f3a26
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739413755 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctr l_same_csr_outstanding.2739413755
Directory	/workspace/15.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.2504336729
Short name	T119
Test name
Test status
Simulation time	379911358 ps
CPU time	2.78 seconds
Started	Jun 09 12:28:52 PM PDT 24
Finished	Jun 09 12:28:55 PM PDT 24
Peak memory	218408 kb
Host	smart-883f92c0-e4b4-4c0b-ac9f-ca9047f3ff36
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504336729 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_errors.2504336729
Directory	/workspace/15.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.2146225389
Short name	T114
Test name
Test status
Simulation time	453500779 ps
CPU time	2.63 seconds
Started	Jun 09 12:28:44 PM PDT 24
Finished	Jun 09 12:28:48 PM PDT 24
Peak memory	218116 kb
Host	smart-fb1bd52c-9a3d-4a1f-b40d-9d4438544c65
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146225389 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_intg _err.2146225389
Directory	/workspace/15.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.3204560189
Short name	T888
Test name
Test status
Simulation time	15079217 ps
CPU time	1.01 seconds
Started	Jun 09 12:30:11 PM PDT 24
Finished	Jun 09 12:30:13 PM PDT 24
Peak memory	219612 kb
Host	smart-60a303aa-ddda-4a51-ab88-cf0cf0e2c16f
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204560189 -assert nopostproc +UVM_TESTNAME =lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 16.lc_ctrl_csr_mem_rw_with_rand_reset.3204560189
Directory	/workspace/16.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.60817257
Short name	T976
Test name
Test status
Simulation time	38720396 ps
CPU time	0.9 seconds
Started	Jun 09 12:29:57 PM PDT 24
Finished	Jun 09 12:29:58 PM PDT 24
Peak memory	209304 kb
Host	smart-e40f5b9e-70ff-48bb-a092-4073cccdd99d
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60817257 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_csr_rw.60817257
Directory	/workspace/16.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.2897399611
Short name	T929
Test name
Test status
Simulation time	52368530 ps
CPU time	1.6 seconds
Started	Jun 09 12:28:56 PM PDT 24
Finished	Jun 09 12:28:59 PM PDT 24
Peak memory	211976 kb
Host	smart-7f11aafe-16ae-45c3-b380-718de71ffe07
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897399611 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctr l_same_csr_outstanding.2897399611
Directory	/workspace/16.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.659241519
Short name	T961
Test name
Test status
Simulation time	164680823 ps
CPU time	2.91 seconds
Started	Jun 09 12:28:46 PM PDT 24
Finished	Jun 09 12:28:50 PM PDT 24
Peak memory	219168 kb
Host	smart-9a552f8a-ba06-41fd-a71b-16bfc9d9f37b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659241519 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_errors.659241519
Directory	/workspace/16.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.930377739
Short name	T895
Test name
Test status
Simulation time	19759275 ps
CPU time	1.39 seconds
Started	Jun 09 12:28:53 PM PDT 24
Finished	Jun 09 12:28:55 PM PDT 24
Peak memory	223436 kb
Host	smart-eecfc97b-41cd-4d52-b91f-eb9095d620d5
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930377739 -assert nopostproc +UVM_TESTNAME= lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 17.lc_ctrl_csr_mem_rw_with_rand_reset.930377739
Directory	/workspace/17.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.3137493406
Short name	T977
Test name
Test status
Simulation time	13966427 ps
CPU time	0.84 seconds
Started	Jun 09 12:29:02 PM PDT 24
Finished	Jun 09 12:29:04 PM PDT 24
Peak memory	209136 kb
Host	smart-12a3b859-b5fb-474c-951c-f58cb5c99b3b
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137493406 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_csr_rw.3137493406
Directory	/workspace/17.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.3140437903
Short name	T969
Test name
Test status
Simulation time	61310454 ps
CPU time	1.15 seconds
Started	Jun 09 12:28:54 PM PDT 24
Finished	Jun 09 12:28:55 PM PDT 24
Peak memory	209856 kb
Host	smart-80afbf2d-0ddb-4821-823b-86b2e461917f
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140437903 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctr l_same_csr_outstanding.3140437903
Directory	/workspace/17.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.2002515255
Short name	T921
Test name
Test status
Simulation time	142718496 ps
CPU time	2.4 seconds
Started	Jun 09 12:29:00 PM PDT 24
Finished	Jun 09 12:29:04 PM PDT 24
Peak memory	219184 kb
Host	smart-3cd48865-6b2b-4ed2-9a45-4ae874b057e1
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002515255 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_errors.2002515255
Directory	/workspace/17.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.1834035519
Short name	T133
Test name
Test status
Simulation time	73982001 ps
CPU time	2.74 seconds
Started	Jun 09 12:28:52 PM PDT 24
Finished	Jun 09 12:28:55 PM PDT 24
Peak memory	223128 kb
Host	smart-e0e701f7-5f08-4b94-9888-1050967b699c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834035519 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_intg _err.1834035519
Directory	/workspace/17.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.3361415919
Short name	T904
Test name
Test status
Simulation time	35957405 ps
CPU time	1.41 seconds
Started	Jun 09 12:28:51 PM PDT 24
Finished	Jun 09 12:28:53 PM PDT 24
Peak memory	219200 kb
Host	smart-c491b6ea-f2e3-4efe-8d16-41e652799b72
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361415919 -assert nopostproc +UVM_TESTNAME =lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 18.lc_ctrl_csr_mem_rw_with_rand_reset.3361415919
Directory	/workspace/18.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.2520678999
Short name	T187
Test name
Test status
Simulation time	38174938 ps
CPU time	0.82 seconds
Started	Jun 09 12:30:11 PM PDT 24
Finished	Jun 09 12:30:12 PM PDT 24
Peak memory	209764 kb
Host	smart-78aab931-69fd-4edd-8511-2527dee76219
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520678999 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_csr_rw.2520678999
Directory	/workspace/18.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.3883207858
Short name	T928
Test name
Test status
Simulation time	92275494 ps
CPU time	1.54 seconds
Started	Jun 09 12:30:14 PM PDT 24
Finished	Jun 09 12:30:16 PM PDT 24
Peak memory	211976 kb
Host	smart-5d26499f-e23a-4e32-ab26-a78758aceda0
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883207858 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctr l_same_csr_outstanding.3883207858
Directory	/workspace/18.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.326265365
Short name	T923
Test name
Test status
Simulation time	53846144 ps
CPU time	1.7 seconds
Started	Jun 09 12:28:55 PM PDT 24
Finished	Jun 09 12:28:57 PM PDT 24
Peak memory	218028 kb
Host	smart-5e676046-b76c-475d-b4cf-6b30f282e910
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326265365 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_errors.326265365
Directory	/workspace/18.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.531708272
Short name	T113
Test name
Test status
Simulation time	51608293 ps
CPU time	1.61 seconds
Started	Jun 09 12:30:17 PM PDT 24
Finished	Jun 09 12:30:20 PM PDT 24
Peak memory	219800 kb
Host	smart-d938779b-afcb-4223-957e-a52acc41344d
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531708272 -assert nopostproc +UVM_TESTNAME= lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 19.lc_ctrl_csr_mem_rw_with_rand_reset.531708272
Directory	/workspace/19.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.85481490
Short name	T191
Test name
Test status
Simulation time	11914061 ps
CPU time	0.84 seconds
Started	Jun 09 12:28:53 PM PDT 24
Finished	Jun 09 12:28:55 PM PDT 24
Peak memory	209628 kb
Host	smart-f3f15685-9d84-4242-a511-13a30dc1230d
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85481490 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_csr_rw.85481490
Directory	/workspace/19.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.1272084851
Short name	T943
Test name
Test status
Simulation time	107960308 ps
CPU time	1.05 seconds
Started	Jun 09 12:28:52 PM PDT 24
Finished	Jun 09 12:29:04 PM PDT 24
Peak memory	209800 kb
Host	smart-fb5066e4-0ae2-4f30-8bf5-1ece6d5266d4
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272084851 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctr l_same_csr_outstanding.1272084851
Directory	/workspace/19.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.4131055320
Short name	T963
Test name
Test status
Simulation time	138056226 ps
CPU time	3.49 seconds
Started	Jun 09 12:28:55 PM PDT 24
Finished	Jun 09 12:28:59 PM PDT 24
Peak memory	218024 kb
Host	smart-ec19b495-0185-4571-9e91-e6a8a95c922f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131055320 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_errors.4131055320
Directory	/workspace/19.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.2074287658
Short name	T186
Test name
Test status
Simulation time	33869157 ps
CPU time	1.4 seconds
Started	Jun 09 12:28:34 PM PDT 24
Finished	Jun 09 12:28:41 PM PDT 24
Peak memory	217812 kb
Host	smart-a09dc517-962a-4cac-8603-675bbd031610
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074287658 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_aliasin g.2074287658
Directory	/workspace/2.lc_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.1153120436
Short name	T879
Test name
Test status
Simulation time	185799180 ps
CPU time	3.15 seconds
Started	Jun 09 12:28:37 PM PDT 24
Finished	Jun 09 12:28:41 PM PDT 24
Peak memory	209752 kb
Host	smart-15606921-569f-4dea-87ee-2ad9a660edd3
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153120436 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_bit_bas h.1153120436
Directory	/workspace/2.lc_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.2394196716
Short name	T182
Test name
Test status
Simulation time	21284382 ps
CPU time	1.13 seconds
Started	Jun 09 12:28:38 PM PDT 24
Finished	Jun 09 12:28:40 PM PDT 24
Peak memory	211884 kb
Host	smart-9747271d-321a-45b7-b8db-d122a9425ea6
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394196716 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_hw_rese t.2394196716
Directory	/workspace/2.lc_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.3372642154
Short name	T118
Test name
Test status
Simulation time	24591196 ps
CPU time	1.86 seconds
Started	Jun 09 12:28:36 PM PDT 24
Finished	Jun 09 12:28:39 PM PDT 24
Peak memory	225644 kb
Host	smart-7d67e4f4-ea73-4e16-855d-c297008f7388
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372642154 -assert nopostproc +UVM_TESTNAME =lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 2.lc_ctrl_csr_mem_rw_with_rand_reset.3372642154
Directory	/workspace/2.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.2099094101
Short name	T947
Test name
Test status
Simulation time	15955625 ps
CPU time	0.86 seconds
Started	Jun 09 12:28:38 PM PDT 24
Finished	Jun 09 12:28:39 PM PDT 24
Peak memory	209928 kb
Host	smart-f182c12b-5800-4c59-827a-7a568a19988a
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099094101 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_rw.2099094101
Directory	/workspace/2.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.4278244411
Short name	T881
Test name
Test status
Simulation time	236778937 ps
CPU time	0.94 seconds
Started	Jun 09 12:28:35 PM PDT 24
Finished	Jun 09 12:28:37 PM PDT 24
Peak memory	209100 kb
Host	smart-3b4bb2be-87ce-4e88-9591-06afe268a1ca
User	root
Command	/workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278244411 -assert nopostproc +UVM_TESTNAME=lc_ctrl _base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 2.lc_ctrl_jtag_alert_test.4278244411
Directory	/workspace/2.lc_ctrl_jtag_alert_test/latest

Test location	/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.2595721772
Short name	T949
Test name
Test status
Simulation time	455320980 ps
CPU time	11.06 seconds
Started	Jun 09 12:28:32 PM PDT 24
Finished	Jun 09 12:28:44 PM PDT 24
Peak memory	209688 kb
Host	smart-9b77c5bf-2c42-4300-9154-aac457cd2757
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595721772 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 2.lc_ctrl_jtag_csr_aliasing.2595721772
Directory	/workspace/2.lc_ctrl_jtag_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.2028526888
Short name	T882
Test name
Test status
Simulation time	2363178805 ps
CPU time	5.58 seconds
Started	Jun 09 12:28:31 PM PDT 24
Finished	Jun 09 12:28:38 PM PDT 24
Peak memory	209684 kb
Host	smart-683d3768-cf65-49fb-9c97-1ed149bfff5a
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028526888 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 2.lc_ctrl_jtag_csr_bit_bash.2028526888
Directory	/workspace/2.lc_ctrl_jtag_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.1329920882
Short name	T1004
Test name
Test status
Simulation time	188664275 ps
CPU time	2.31 seconds
Started	Jun 09 12:28:33 PM PDT 24
Finished	Jun 09 12:28:36 PM PDT 24
Peak memory	211268 kb
Host	smart-fe5db2f4-3102-4446-a98b-fc63cae74da4
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329920882 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 2.lc_ctrl_jtag_csr_hw_reset.1329920882
Directory	/workspace/2.lc_ctrl_jtag_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.793660041
Short name	T916
Test name
Test status
Simulation time	189309266 ps
CPU time	1.63 seconds
Started	Jun 09 12:28:32 PM PDT 24
Finished	Jun 09 12:28:35 PM PDT 24
Peak memory	209732 kb
Host	smart-fdb25bc0-83db-4275-bc2c-0161c28c4065
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793660041 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_csr_rw.793660041
Directory	/workspace/2.lc_ctrl_jtag_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.4240348111
Short name	T908
Test name
Test status
Simulation time	53505659 ps
CPU time	1.09 seconds
Started	Jun 09 12:28:38 PM PDT 24
Finished	Jun 09 12:28:39 PM PDT 24
Peak memory	209904 kb
Host	smart-0a2df78d-c633-44e5-8dab-cfcd6767fe42
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240348111 -assert nopostproc +UVM_TESTNA ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_same_csr_outstanding.4240348111
Directory	/workspace/2.lc_ctrl_jtag_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.1579131665
Short name	T979
Test name
Test status
Simulation time	157018482 ps
CPU time	1.12 seconds
Started	Jun 09 12:28:34 PM PDT 24
Finished	Jun 09 12:28:37 PM PDT 24
Peak memory	209932 kb
Host	smart-34bb1ee9-bde2-4d95-ac24-062356c816b6
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579131665 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl _same_csr_outstanding.1579131665
Directory	/workspace/2.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.3832288618
Short name	T989
Test name
Test status
Simulation time	177797491 ps
CPU time	3.18 seconds
Started	Jun 09 12:28:37 PM PDT 24
Finished	Jun 09 12:28:41 PM PDT 24
Peak memory	218072 kb
Host	smart-a75a2205-fb2c-47ed-b26e-ff3a08b9640a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832288618 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_errors.3832288618
Directory	/workspace/2.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.3706245030
Short name	T184
Test name
Test status
Simulation time	27937630 ps
CPU time	0.97 seconds
Started	Jun 09 12:28:37 PM PDT 24
Finished	Jun 09 12:28:39 PM PDT 24
Peak memory	209860 kb
Host	smart-7c3dfc0f-7bb0-418b-977c-9001580cab60
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706245030 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_aliasin g.3706245030
Directory	/workspace/3.lc_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.2624400717
Short name	T954
Test name
Test status
Simulation time	56494120 ps
CPU time	1.48 seconds
Started	Jun 09 12:28:36 PM PDT 24
Finished	Jun 09 12:28:39 PM PDT 24
Peak memory	209800 kb
Host	smart-93d09273-dbbc-44c3-b5fb-7eb1584baf88
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624400717 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_bit_bas h.2624400717
Directory	/workspace/3.lc_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.2150032229
Short name	T942
Test name
Test status
Simulation time	70803202 ps
CPU time	1.26 seconds
Started	Jun 09 12:28:39 PM PDT 24
Finished	Jun 09 12:28:42 PM PDT 24
Peak memory	212128 kb
Host	smart-22d5ba1f-24b5-492a-bde2-02f7254eee14
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150032229 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_hw_rese t.2150032229
Directory	/workspace/3.lc_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.3763692004
Short name	T134
Test name
Test status
Simulation time	27064865 ps
CPU time	1.79 seconds
Started	Jun 09 12:28:36 PM PDT 24
Finished	Jun 09 12:28:39 PM PDT 24
Peak memory	218208 kb
Host	smart-64e077b6-5fd8-4834-b40b-8e558af1c00c
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763692004 -assert nopostproc +UVM_TESTNAME =lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 3.lc_ctrl_csr_mem_rw_with_rand_reset.3763692004
Directory	/workspace/3.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.4060846686
Short name	T883
Test name
Test status
Simulation time	12397785 ps
CPU time	0.9 seconds
Started	Jun 09 12:28:34 PM PDT 24
Finished	Jun 09 12:28:36 PM PDT 24
Peak memory	209792 kb
Host	smart-4187e60e-fadc-481a-97d5-9efceb4fdc24
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060846686 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_rw.4060846686
Directory	/workspace/3.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.3594618174
Short name	T146
Test name
Test status
Simulation time	115139712 ps
CPU time	0.99 seconds
Started	Jun 09 12:28:34 PM PDT 24
Finished	Jun 09 12:28:36 PM PDT 24
Peak memory	209680 kb
Host	smart-4a66400f-8e76-4962-a01d-ebd88443ecbc
User	root
Command	/workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594618174 -assert nopostproc +UVM_TESTNAME=lc_ctrl _base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 3.lc_ctrl_jtag_alert_test.3594618174
Directory	/workspace/3.lc_ctrl_jtag_alert_test/latest

Test location	/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.4017570391
Short name	T915
Test name
Test status
Simulation time	587467665 ps
CPU time	5.19 seconds
Started	Jun 09 12:28:31 PM PDT 24
Finished	Jun 09 12:28:37 PM PDT 24
Peak memory	209424 kb
Host	smart-d58a7a9a-f214-4369-b4b5-1ba7a584efc9
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017570391 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 3.lc_ctrl_jtag_csr_aliasing.4017570391
Directory	/workspace/3.lc_ctrl_jtag_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.3268755119
Short name	T913
Test name
Test status
Simulation time	2394092911 ps
CPU time	9.81 seconds
Started	Jun 09 12:28:37 PM PDT 24
Finished	Jun 09 12:28:48 PM PDT 24
Peak memory	209804 kb
Host	smart-30ce05bd-c67f-4b73-af6f-765def4483cd
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268755119 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 3.lc_ctrl_jtag_csr_bit_bash.3268755119
Directory	/workspace/3.lc_ctrl_jtag_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.157074578
Short name	T889
Test name
Test status
Simulation time	93771971 ps
CPU time	1.8 seconds
Started	Jun 09 12:28:33 PM PDT 24
Finished	Jun 09 12:28:36 PM PDT 24
Peak memory	217908 kb
Host	smart-bf3171ae-09f1-4120-bf2c-1833e62603dc
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157074578 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 3.lc_ctrl_jtag_csr_hw_reset.157074578
Directory	/workspace/3.lc_ctrl_jtag_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1491280788
Short name	T1000
Test name
Test status
Simulation time	1982193778 ps
CPU time	3.67 seconds
Started	Jun 09 12:28:39 PM PDT 24
Finished	Jun 09 12:28:43 PM PDT 24
Peak memory	218188 kb
Host	smart-8ab7b059-244b-4f83-b918-f2ab2dd90159
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149128 0788 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1491280788
Directory	/workspace/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.2552348585
Short name	T944
Test name
Test status
Simulation time	68421570 ps
CPU time	2.15 seconds
Started	Jun 09 12:28:36 PM PDT 24
Finished	Jun 09 12:28:39 PM PDT 24
Peak memory	209724 kb
Host	smart-815f3806-8bf5-45f2-b521-e1178cbc1415
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552348585 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_csr_rw.2552348585
Directory	/workspace/3.lc_ctrl_jtag_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.2677523665
Short name	T193
Test name
Test status
Simulation time	73345239 ps
CPU time	0.97 seconds
Started	Jun 09 12:28:39 PM PDT 24
Finished	Jun 09 12:28:41 PM PDT 24
Peak memory	209844 kb
Host	smart-ff7e1c5a-3686-43b9-a9cc-8bc456d6dc3e
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677523665 -assert nopostproc +UVM_TESTNA ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_same_csr_outstanding.2677523665
Directory	/workspace/3.lc_ctrl_jtag_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.3160116852
Short name	T1001
Test name
Test status
Simulation time	362141237 ps
CPU time	1.1 seconds
Started	Jun 09 12:28:42 PM PDT 24
Finished	Jun 09 12:28:44 PM PDT 24
Peak memory	209856 kb
Host	smart-fcce2a80-74d6-4b01-84ad-4875ce73bd21
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160116852 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl _same_csr_outstanding.3160116852
Directory	/workspace/3.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.4024024284
Short name	T122
Test name
Test status
Simulation time	30123072 ps
CPU time	1.89 seconds
Started	Jun 09 12:28:33 PM PDT 24
Finished	Jun 09 12:28:36 PM PDT 24
Peak memory	219220 kb
Host	smart-59baf177-fc07-428d-90a3-f71abd8f5207
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024024284 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_errors.4024024284
Directory	/workspace/3.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.4188540842
Short name	T964
Test name
Test status
Simulation time	92165141 ps
CPU time	1.07 seconds
Started	Jun 09 12:28:39 PM PDT 24
Finished	Jun 09 12:28:41 PM PDT 24
Peak memory	209804 kb
Host	smart-f96807a2-22cb-487e-bd9a-0bf4e663d462
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188540842 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_aliasin g.4188540842
Directory	/workspace/4.lc_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.2488998460
Short name	T940
Test name
Test status
Simulation time	76107260 ps
CPU time	1.83 seconds
Started	Jun 09 12:28:44 PM PDT 24
Finished	Jun 09 12:28:47 PM PDT 24
Peak memory	209804 kb
Host	smart-6a7159c3-d85c-43b8-9a9c-1546bcf48274
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488998460 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_bit_bas h.2488998460
Directory	/workspace/4.lc_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.2867722737
Short name	T181
Test name
Test status
Simulation time	57704344 ps
CPU time	0.88 seconds
Started	Jun 09 12:28:40 PM PDT 24
Finished	Jun 09 12:28:41 PM PDT 24
Peak memory	210152 kb
Host	smart-ed4817d9-8d6f-4b68-afe6-c34b2723dde8
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867722737 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_hw_rese t.2867722737
Directory	/workspace/4.lc_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.3524867976
Short name	T117
Test name
Test status
Simulation time	199180706 ps
CPU time	1.18 seconds
Started	Jun 09 12:28:46 PM PDT 24
Finished	Jun 09 12:28:48 PM PDT 24
Peak memory	221924 kb
Host	smart-bcd06722-5a9c-438d-aa5d-550beb16397c
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524867976 -assert nopostproc +UVM_TESTNAME =lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 4.lc_ctrl_csr_mem_rw_with_rand_reset.3524867976
Directory	/workspace/4.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.4635852
Short name	T970
Test name
Test status
Simulation time	54563553 ps
CPU time	0.83 seconds
Started	Jun 09 12:28:36 PM PDT 24
Finished	Jun 09 12:28:38 PM PDT 24
Peak memory	209056 kb
Host	smart-93ebe738-8635-4f7d-a0e8-f8fc2641a56e
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4635852 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_rw.4635852
Directory	/workspace/4.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.208729898
Short name	T1003
Test name
Test status
Simulation time	94472308 ps
CPU time	1.9 seconds
Started	Jun 09 12:29:42 PM PDT 24
Finished	Jun 09 12:29:45 PM PDT 24
Peak memory	208852 kb
Host	smart-eda69914-1391-47e4-8af7-9935398bd840
User	root
Command	/workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208729898 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 4.lc_ctrl_jtag_alert_test.208729898
Directory	/workspace/4.lc_ctrl_jtag_alert_test/latest

Test location	/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.423378663
Short name	T950
Test name
Test status
Simulation time	373690765 ps
CPU time	8.11 seconds
Started	Jun 09 12:28:34 PM PDT 24
Finished	Jun 09 12:28:43 PM PDT 24
Peak memory	209644 kb
Host	smart-17b81113-fb74-4932-9689-0a186d4e9917
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423378663 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 4.lc_ctrl_jtag_csr_aliasing.423378663
Directory	/workspace/4.lc_ctrl_jtag_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.2916901120
Short name	T886
Test name
Test status
Simulation time	355689482 ps
CPU time	5.07 seconds
Started	Jun 09 12:28:38 PM PDT 24
Finished	Jun 09 12:28:44 PM PDT 24
Peak memory	217440 kb
Host	smart-ff3bc210-7a83-4048-87bb-dd80c2260ee8
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916901120 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 4.lc_ctrl_jtag_csr_bit_bash.2916901120
Directory	/workspace/4.lc_ctrl_jtag_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.3382038119
Short name	T966
Test name
Test status
Simulation time	122033197 ps
CPU time	1.42 seconds
Started	Jun 09 12:28:35 PM PDT 24
Finished	Jun 09 12:28:37 PM PDT 24
Peak memory	211112 kb
Host	smart-cf55ec86-6dc2-4ad7-b2a8-722067955dae
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382038119 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 4.lc_ctrl_jtag_csr_hw_reset.3382038119
Directory	/workspace/4.lc_ctrl_jtag_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.139292887
Short name	T926
Test name
Test status
Simulation time	369805958 ps
CPU time	2.16 seconds
Started	Jun 09 12:28:49 PM PDT 24
Finished	Jun 09 12:28:51 PM PDT 24
Peak memory	218208 kb
Host	smart-1927d93b-faee-42d8-b8b5-ff394fc96311
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139292 887 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.139292887
Directory	/workspace/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.2019315017
Short name	T984
Test name
Test status
Simulation time	311547989 ps
CPU time	1.96 seconds
Started	Jun 09 12:28:32 PM PDT 24
Finished	Jun 09 12:28:35 PM PDT 24
Peak memory	217564 kb
Host	smart-577feeee-6c92-498b-a1c1-1e118898ff6e
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019315017 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_csr_rw.2019315017
Directory	/workspace/4.lc_ctrl_jtag_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.3658323635
Short name	T937
Test name
Test status
Simulation time	27289972 ps
CPU time	1.39 seconds
Started	Jun 09 12:28:40 PM PDT 24
Finished	Jun 09 12:28:42 PM PDT 24
Peak memory	209872 kb
Host	smart-abc760a6-95f0-4903-960b-5fd3ddc3c261
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658323635 -assert nopostproc +UVM_TESTNA ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_same_csr_outstanding.3658323635
Directory	/workspace/4.lc_ctrl_jtag_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.3083616141
Short name	T957
Test name
Test status
Simulation time	131834821 ps
CPU time	2.03 seconds
Started	Jun 09 12:28:33 PM PDT 24
Finished	Jun 09 12:28:36 PM PDT 24
Peak memory	209980 kb
Host	smart-1300eb53-65cb-48e8-95e3-46d95aaf03c6
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083616141 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl _same_csr_outstanding.3083616141
Directory	/workspace/4.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.1455136926
Short name	T952
Test name
Test status
Simulation time	41051131 ps
CPU time	2.64 seconds
Started	Jun 09 12:28:38 PM PDT 24
Finished	Jun 09 12:28:42 PM PDT 24
Peak memory	218100 kb
Host	smart-c05b3955-6ec6-436d-bdee-75c1090f4611
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455136926 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_errors.1455136926
Directory	/workspace/4.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.2149287818
Short name	T914
Test name
Test status
Simulation time	73949752 ps
CPU time	1.16 seconds
Started	Jun 09 12:28:33 PM PDT 24
Finished	Jun 09 12:28:36 PM PDT 24
Peak memory	220560 kb
Host	smart-8a9b98e1-ddb6-4bf1-b4d6-1e89570a25b2
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149287818 -assert nopostproc +UVM_TESTNAME =lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 5.lc_ctrl_csr_mem_rw_with_rand_reset.2149287818
Directory	/workspace/5.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.797240636
Short name	T932
Test name
Test status
Simulation time	11735208 ps
CPU time	0.95 seconds
Started	Jun 09 12:28:43 PM PDT 24
Finished	Jun 09 12:28:45 PM PDT 24
Peak memory	209800 kb
Host	smart-d537a7ca-c2f1-4fc0-abd7-75ff548c6176
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797240636 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_csr_rw.797240636
Directory	/workspace/5.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.2277489719
Short name	T974
Test name
Test status
Simulation time	75072552 ps
CPU time	2.21 seconds
Started	Jun 09 12:28:34 PM PDT 24
Finished	Jun 09 12:28:38 PM PDT 24
Peak memory	209184 kb
Host	smart-67f1e1de-af98-475b-a052-84ac9242e21d
User	root
Command	/workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277489719 -assert nopostproc +UVM_TESTNAME=lc_ctrl _base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 5.lc_ctrl_jtag_alert_test.2277489719
Directory	/workspace/5.lc_ctrl_jtag_alert_test/latest

Test location	/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.2395045820
Short name	T951
Test name
Test status
Simulation time	2628498117 ps
CPU time	15.84 seconds
Started	Jun 09 12:28:40 PM PDT 24
Finished	Jun 09 12:28:57 PM PDT 24
Peak memory	209884 kb
Host	smart-97483021-434a-4948-a73e-d5d54731ad00
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395045820 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 5.lc_ctrl_jtag_csr_aliasing.2395045820
Directory	/workspace/5.lc_ctrl_jtag_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.3343832761
Short name	T202
Test name
Test status
Simulation time	970781580 ps
CPU time	9.49 seconds
Started	Jun 09 12:28:43 PM PDT 24
Finished	Jun 09 12:28:53 PM PDT 24
Peak memory	217428 kb
Host	smart-7e53e5e6-5271-453d-b8c5-348f068ce472
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343832761 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 5.lc_ctrl_jtag_csr_bit_bash.3343832761
Directory	/workspace/5.lc_ctrl_jtag_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.2670836600
Short name	T141
Test name
Test status
Simulation time	131685183 ps
CPU time	3.89 seconds
Started	Jun 09 12:28:37 PM PDT 24
Finished	Jun 09 12:28:42 PM PDT 24
Peak memory	211192 kb
Host	smart-490f6ac1-715d-44e6-84f5-da9d524de6d4
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670836600 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 5.lc_ctrl_jtag_csr_hw_reset.2670836600
Directory	/workspace/5.lc_ctrl_jtag_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2326453589
Short name	T901
Test name
Test status
Simulation time	102745335 ps
CPU time	3.45 seconds
Started	Jun 09 12:28:36 PM PDT 24
Finished	Jun 09 12:28:41 PM PDT 24
Peak memory	218336 kb
Host	smart-c19b9b1b-ae6f-48df-9d87-031e5f864c63
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232645 3589 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2326453589
Directory	/workspace/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.445007195
Short name	T994
Test name
Test status
Simulation time	254129250 ps
CPU time	1.52 seconds
Started	Jun 09 12:29:24 PM PDT 24
Finished	Jun 09 12:29:27 PM PDT 24
Peak memory	208860 kb
Host	smart-a269f105-e48d-4f0d-9d77-b27f6688b42a
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445007195 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_csr_rw.445007195
Directory	/workspace/5.lc_ctrl_jtag_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.1895463596
Short name	T996
Test name
Test status
Simulation time	266977059 ps
CPU time	1.65 seconds
Started	Jun 09 12:28:32 PM PDT 24
Finished	Jun 09 12:28:35 PM PDT 24
Peak memory	209844 kb
Host	smart-b2c7fa1c-a19b-468c-a5c0-e176a2948efd
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895463596 -assert nopostproc +UVM_TESTNA ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_same_csr_outstanding.1895463596
Directory	/workspace/5.lc_ctrl_jtag_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.3111606297
Short name	T930
Test name
Test status
Simulation time	67173113 ps
CPU time	0.92 seconds
Started	Jun 09 12:28:45 PM PDT 24
Finished	Jun 09 12:28:46 PM PDT 24
Peak memory	209876 kb
Host	smart-321c35b4-6fdb-4b6e-99cd-042a619f3423
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111606297 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl _same_csr_outstanding.3111606297
Directory	/workspace/5.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.671824773
Short name	T126
Test name
Test status
Simulation time	269232069 ps
CPU time	3.27 seconds
Started	Jun 09 12:28:36 PM PDT 24
Finished	Jun 09 12:28:40 PM PDT 24
Peak memory	219264 kb
Host	smart-21f6f795-eea1-4971-b8ba-cee6beec53e9
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671824773 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_errors.671824773
Directory	/workspace/5.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.867856543
Short name	T1002
Test name
Test status
Simulation time	467000604 ps
CPU time	2.18 seconds
Started	Jun 09 12:28:35 PM PDT 24
Finished	Jun 09 12:28:39 PM PDT 24
Peak memory	218112 kb
Host	smart-c647ed5c-6c39-4202-8589-ac7a0db895e8
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867856543 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_intg_e rr.867856543
Directory	/workspace/5.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.606168531
Short name	T166
Test name
Test status
Simulation time	33936672 ps
CPU time	1.05 seconds
Started	Jun 09 12:28:49 PM PDT 24
Finished	Jun 09 12:28:50 PM PDT 24
Peak memory	218120 kb
Host	smart-d11b459c-ea34-47d4-8ed4-671a90f2d921
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606168531 -assert nopostproc +UVM_TESTNAME= lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 6.lc_ctrl_csr_mem_rw_with_rand_reset.606168531
Directory	/workspace/6.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.3773845660
Short name	T927
Test name
Test status
Simulation time	29277478 ps
CPU time	1.15 seconds
Started	Jun 09 12:29:42 PM PDT 24
Finished	Jun 09 12:29:44 PM PDT 24
Peak memory	209708 kb
Host	smart-22eb847c-0548-44fd-b3d8-665baa89c57a
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773845660 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_csr_rw.3773845660
Directory	/workspace/6.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.1253973003
Short name	T990
Test name
Test status
Simulation time	238885913 ps
CPU time	2.19 seconds
Started	Jun 09 12:28:40 PM PDT 24
Finished	Jun 09 12:28:44 PM PDT 24
Peak memory	209640 kb
Host	smart-ef65795e-254a-4e8a-9317-13ae1f9e256e
User	root
Command	/workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253973003 -assert nopostproc +UVM_TESTNAME=lc_ctrl _base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 6.lc_ctrl_jtag_alert_test.1253973003
Directory	/workspace/6.lc_ctrl_jtag_alert_test/latest

Test location	/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.2808310652
Short name	T144
Test name
Test status
Simulation time	1015634274 ps
CPU time	9.27 seconds
Started	Jun 09 12:28:38 PM PDT 24
Finished	Jun 09 12:28:48 PM PDT 24
Peak memory	217400 kb
Host	smart-e0a730fe-2cfc-4678-98eb-fb30476605c0
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808310652 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 6.lc_ctrl_jtag_csr_aliasing.2808310652
Directory	/workspace/6.lc_ctrl_jtag_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.1185937049
Short name	T993
Test name
Test status
Simulation time	1379282965 ps
CPU time	18.24 seconds
Started	Jun 09 12:28:40 PM PDT 24
Finished	Jun 09 12:28:59 PM PDT 24
Peak memory	209448 kb
Host	smart-2ff3be7a-cdda-4b32-9144-748d64860ba3
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185937049 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 6.lc_ctrl_jtag_csr_bit_bash.1185937049
Directory	/workspace/6.lc_ctrl_jtag_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.1423710211
Short name	T920
Test name
Test status
Simulation time	256249517 ps
CPU time	2.18 seconds
Started	Jun 09 12:28:47 PM PDT 24
Finished	Jun 09 12:28:50 PM PDT 24
Peak memory	217928 kb
Host	smart-4eb1e41a-3aed-4dca-bea0-1ff39449ac7b
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423710211 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 6.lc_ctrl_jtag_csr_hw_reset.1423710211
Directory	/workspace/6.lc_ctrl_jtag_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4276559844
Short name	T982
Test name
Test status
Simulation time	583665348 ps
CPU time	1.83 seconds
Started	Jun 09 12:28:48 PM PDT 24
Finished	Jun 09 12:28:50 PM PDT 24
Peak memory	220952 kb
Host	smart-0339dc40-894a-4f8b-9521-ceab47136e2d
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427655 9844 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4276559844
Directory	/workspace/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.3059761502
Short name	T948
Test name
Test status
Simulation time	113591990 ps
CPU time	2.17 seconds
Started	Jun 09 12:28:34 PM PDT 24
Finished	Jun 09 12:28:37 PM PDT 24
Peak memory	210004 kb
Host	smart-cd03f5b1-7a61-47cf-a774-2cc4bd2f542a
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059761502 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_csr_rw.3059761502
Directory	/workspace/6.lc_ctrl_jtag_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.1242738230
Short name	T925
Test name
Test status
Simulation time	377885611 ps
CPU time	1.03 seconds
Started	Jun 09 12:28:36 PM PDT 24
Finished	Jun 09 12:28:38 PM PDT 24
Peak memory	218056 kb
Host	smart-b42f5607-958c-447e-946b-647967ed0fb2
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242738230 -assert nopostproc +UVM_TESTNA ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_same_csr_outstanding.1242738230
Directory	/workspace/6.lc_ctrl_jtag_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.1485706608
Short name	T960
Test name
Test status
Simulation time	88700611 ps
CPU time	1.32 seconds
Started	Jun 09 12:28:42 PM PDT 24
Finished	Jun 09 12:28:44 PM PDT 24
Peak memory	209832 kb
Host	smart-88ffe317-ff08-4f69-8cad-b55b4212e961
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485706608 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl _same_csr_outstanding.1485706608
Directory	/workspace/6.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.2036308245
Short name	T896
Test name
Test status
Simulation time	226653403 ps
CPU time	1.81 seconds
Started	Jun 09 12:28:45 PM PDT 24
Finished	Jun 09 12:28:47 PM PDT 24
Peak memory	218036 kb
Host	smart-6caf0204-f554-4497-bb9e-a7fc8355a0e5
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036308245 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_errors.2036308245
Directory	/workspace/6.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.968801281
Short name	T981
Test name
Test status
Simulation time	80109964 ps
CPU time	1.85 seconds
Started	Jun 09 12:28:33 PM PDT 24
Finished	Jun 09 12:28:36 PM PDT 24
Peak memory	222452 kb
Host	smart-4d764c5c-acaf-48a1-87dd-d458fcc202fe
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968801281 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_intg_e rr.968801281
Directory	/workspace/6.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.2945863781
Short name	T910
Test name
Test status
Simulation time	211999556 ps
CPU time	1.49 seconds
Started	Jun 09 12:28:40 PM PDT 24
Finished	Jun 09 12:28:42 PM PDT 24
Peak memory	219216 kb
Host	smart-6ee3a524-4eb4-4456-a0b7-52358c26b29e
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945863781 -assert nopostproc +UVM_TESTNAME =lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 7.lc_ctrl_csr_mem_rw_with_rand_reset.2945863781
Directory	/workspace/7.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.3560528833
Short name	T892
Test name
Test status
Simulation time	173970409 ps
CPU time	0.9 seconds
Started	Jun 09 12:28:41 PM PDT 24
Finished	Jun 09 12:28:43 PM PDT 24
Peak memory	209796 kb
Host	smart-fde740db-d890-4700-84cb-c13f22662111
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560528833 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_csr_rw.3560528833
Directory	/workspace/7.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.2769128628
Short name	T880
Test name
Test status
Simulation time	34643856 ps
CPU time	1.1 seconds
Started	Jun 09 12:29:40 PM PDT 24
Finished	Jun 09 12:29:42 PM PDT 24
Peak memory	209584 kb
Host	smart-0fe2ac61-9991-499d-bc43-c6bbe4ee4616
User	root
Command	/workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769128628 -assert nopostproc +UVM_TESTNAME=lc_ctrl _base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 7.lc_ctrl_jtag_alert_test.2769128628
Directory	/workspace/7.lc_ctrl_jtag_alert_test/latest

Test location	/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.1691273411
Short name	T891
Test name
Test status
Simulation time	550144334 ps
CPU time	4.19 seconds
Started	Jun 09 12:28:47 PM PDT 24
Finished	Jun 09 12:28:52 PM PDT 24
Peak memory	209396 kb
Host	smart-94b74102-dfd8-4de2-8990-d1a4f25ad38c
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691273411 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 7.lc_ctrl_jtag_csr_aliasing.1691273411
Directory	/workspace/7.lc_ctrl_jtag_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.2831966418
Short name	T939
Test name
Test status
Simulation time	3306910607 ps
CPU time	13.02 seconds
Started	Jun 09 12:28:51 PM PDT 24
Finished	Jun 09 12:29:04 PM PDT 24
Peak memory	209776 kb
Host	smart-d79d320b-2548-4bdd-b658-b9d0264470f3
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831966418 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 7.lc_ctrl_jtag_csr_bit_bash.2831966418
Directory	/workspace/7.lc_ctrl_jtag_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.687695736
Short name	T980
Test name
Test status
Simulation time	283238075 ps
CPU time	1.28 seconds
Started	Jun 09 12:28:40 PM PDT 24
Finished	Jun 09 12:28:42 PM PDT 24
Peak memory	211124 kb
Host	smart-405d9ca2-76f4-4ee2-8c5d-8c8aedc9a42e
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687695736 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 7.lc_ctrl_jtag_csr_hw_reset.687695736
Directory	/workspace/7.lc_ctrl_jtag_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.2559066231
Short name	T971
Test name
Test status
Simulation time	185748833 ps
CPU time	1.64 seconds
Started	Jun 09 12:28:47 PM PDT 24
Finished	Jun 09 12:28:49 PM PDT 24
Peak memory	217740 kb
Host	smart-36ec687b-7e2c-4181-9e64-3e3652bca7ff
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559066231 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_csr_rw.2559066231
Directory	/workspace/7.lc_ctrl_jtag_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.1166555389
Short name	T197
Test name
Test status
Simulation time	28403586 ps
CPU time	1.2 seconds
Started	Jun 09 12:28:44 PM PDT 24
Finished	Jun 09 12:28:46 PM PDT 24
Peak memory	218064 kb
Host	smart-330f6181-298c-4490-9b9f-9f36800dfa05
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166555389 -assert nopostproc +UVM_TESTNA ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_same_csr_outstanding.1166555389
Directory	/workspace/7.lc_ctrl_jtag_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.3890872321
Short name	T985
Test name
Test status
Simulation time	52519484 ps
CPU time	1.45 seconds
Started	Jun 09 12:28:42 PM PDT 24
Finished	Jun 09 12:28:44 PM PDT 24
Peak memory	218120 kb
Host	smart-03fd480f-fe7d-4cd7-b070-c115f106bfac
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890872321 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl _same_csr_outstanding.3890872321
Directory	/workspace/7.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.3632629339
Short name	T998
Test name
Test status
Simulation time	41609064 ps
CPU time	2.67 seconds
Started	Jun 09 12:28:49 PM PDT 24
Finished	Jun 09 12:28:52 PM PDT 24
Peak memory	218140 kb
Host	smart-8b30d713-5d69-482c-a7b8-9a4b7920c518
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632629339 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_errors.3632629339
Directory	/workspace/7.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.4275995102
Short name	T997
Test name
Test status
Simulation time	124117007 ps
CPU time	1.34 seconds
Started	Jun 09 12:28:50 PM PDT 24
Finished	Jun 09 12:28:52 PM PDT 24
Peak memory	218704 kb
Host	smart-bdd34f3c-702d-400c-886d-e459bb605496
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275995102 -assert nopostproc +UVM_TESTNAME =lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 8.lc_ctrl_csr_mem_rw_with_rand_reset.4275995102
Directory	/workspace/8.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.3376106030
Short name	T120
Test name
Test status
Simulation time	17061709 ps
CPU time	1.15 seconds
Started	Jun 09 12:28:51 PM PDT 24
Finished	Jun 09 12:28:52 PM PDT 24
Peak memory	209792 kb
Host	smart-24ee9d3f-596f-41f9-aef5-d5676036a826
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376106030 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_csr_rw.3376106030
Directory	/workspace/8.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.1481111763
Short name	T931
Test name
Test status
Simulation time	56273800 ps
CPU time	2.13 seconds
Started	Jun 09 12:28:51 PM PDT 24
Finished	Jun 09 12:28:53 PM PDT 24
Peak memory	209704 kb
Host	smart-24c97510-0faf-457e-b850-daf4875be89c
User	root
Command	/workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481111763 -assert nopostproc +UVM_TESTNAME=lc_ctrl _base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 8.lc_ctrl_jtag_alert_test.1481111763
Directory	/workspace/8.lc_ctrl_jtag_alert_test/latest

Test location	/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.1125278750
Short name	T902
Test name
Test status
Simulation time	749262370 ps
CPU time	8.91 seconds
Started	Jun 09 12:28:50 PM PDT 24
Finished	Jun 09 12:28:59 PM PDT 24
Peak memory	209696 kb
Host	smart-bec66de6-bcf5-472d-8d1b-06389625da38
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125278750 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 8.lc_ctrl_jtag_csr_aliasing.1125278750
Directory	/workspace/8.lc_ctrl_jtag_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.2611661391
Short name	T967
Test name
Test status
Simulation time	1540296990 ps
CPU time	17.39 seconds
Started	Jun 09 12:28:50 PM PDT 24
Finished	Jun 09 12:29:08 PM PDT 24
Peak memory	209476 kb
Host	smart-b7759284-c1e7-4a62-b90e-c96330d6b8ac
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611661391 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 8.lc_ctrl_jtag_csr_bit_bash.2611661391
Directory	/workspace/8.lc_ctrl_jtag_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.341386183
Short name	T143
Test name
Test status
Simulation time	247138659 ps
CPU time	2.09 seconds
Started	Jun 09 12:28:45 PM PDT 24
Finished	Jun 09 12:28:48 PM PDT 24
Peak memory	211132 kb
Host	smart-4ac9503c-15ae-493d-9855-d08cbd1143d1
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341386183 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 8.lc_ctrl_jtag_csr_hw_reset.341386183
Directory	/workspace/8.lc_ctrl_jtag_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.740926589
Short name	T919
Test name
Test status
Simulation time	105733108 ps
CPU time	2.1 seconds
Started	Jun 09 12:28:52 PM PDT 24
Finished	Jun 09 12:28:54 PM PDT 24
Peak memory	218116 kb
Host	smart-07b7fddb-3ba1-4740-b9a9-3582d103c5f5
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740926 589 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.740926589
Directory	/workspace/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.1284327124
Short name	T142
Test name
Test status
Simulation time	865344318 ps
CPU time	1.19 seconds
Started	Jun 09 12:28:46 PM PDT 24
Finished	Jun 09 12:28:48 PM PDT 24
Peak memory	209760 kb
Host	smart-e84fbaad-99c9-4c7c-ada8-d7efdff4c60c
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284327124 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_csr_rw.1284327124
Directory	/workspace/8.lc_ctrl_jtag_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.3405763737
Short name	T196
Test name
Test status
Simulation time	79240664 ps
CPU time	1.44 seconds
Started	Jun 09 12:28:44 PM PDT 24
Finished	Jun 09 12:28:46 PM PDT 24
Peak memory	212040 kb
Host	smart-18c4a559-968c-4949-93a6-7765ce7d58f0
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405763737 -assert nopostproc +UVM_TESTNA ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_same_csr_outstanding.3405763737
Directory	/workspace/8.lc_ctrl_jtag_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.3169346495
Short name	T198
Test name
Test status
Simulation time	21375537 ps
CPU time	1.27 seconds
Started	Jun 09 12:28:45 PM PDT 24
Finished	Jun 09 12:28:46 PM PDT 24
Peak memory	218084 kb
Host	smart-b8aa8566-50fc-4755-ac3a-c687d5d825ef
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169346495 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl _same_csr_outstanding.3169346495
Directory	/workspace/8.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.2946280760
Short name	T127
Test name
Test status
Simulation time	649287515 ps
CPU time	4.02 seconds
Started	Jun 09 12:28:50 PM PDT 24
Finished	Jun 09 12:28:55 PM PDT 24
Peak memory	218236 kb
Host	smart-1c822c12-b067-4f8a-907a-473885e20f0d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946280760 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_intg_ err.2946280760
Directory	/workspace/8.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.2116824591
Short name	T900
Test name
Test status
Simulation time	13807426 ps
CPU time	0.99 seconds
Started	Jun 09 12:28:51 PM PDT 24
Finished	Jun 09 12:28:52 PM PDT 24
Peak memory	218100 kb
Host	smart-2dec13fe-e037-417b-b991-5911bb1e4178
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116824591 -assert nopostproc +UVM_TESTNAME =lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 9.lc_ctrl_csr_mem_rw_with_rand_reset.2116824591
Directory	/workspace/9.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.423129603
Short name	T188
Test name
Test status
Simulation time	144997272 ps
CPU time	0.96 seconds
Started	Jun 09 12:28:45 PM PDT 24
Finished	Jun 09 12:28:47 PM PDT 24
Peak memory	209872 kb
Host	smart-0dd81a50-61bd-4511-945f-1a90317ff3b9
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423129603 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_csr_rw.423129603
Directory	/workspace/9.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.4231067857
Short name	T975
Test name
Test status
Simulation time	15925153 ps
CPU time	1.06 seconds
Started	Jun 09 12:28:51 PM PDT 24
Finished	Jun 09 12:28:53 PM PDT 24
Peak memory	209684 kb
Host	smart-5eae96fc-a37c-4f75-84c2-2fcc2405c65d
User	root
Command	/workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231067857 -assert nopostproc +UVM_TESTNAME=lc_ctrl _base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 9.lc_ctrl_jtag_alert_test.4231067857
Directory	/workspace/9.lc_ctrl_jtag_alert_test/latest

Test location	/workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.3357688116
Short name	T938
Test name
Test status
Simulation time	1291602075 ps
CPU time	3.54 seconds
Started	Jun 09 12:28:49 PM PDT 24
Finished	Jun 09 12:28:53 PM PDT 24
Peak memory	209468 kb
Host	smart-aa14f164-4487-48a1-8a48-497ca5d22c9e
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357688116 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 9.lc_ctrl_jtag_csr_aliasing.3357688116
Directory	/workspace/9.lc_ctrl_jtag_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.2935364335
Short name	T986
Test name
Test status
Simulation time	699521742 ps
CPU time	9.05 seconds
Started	Jun 09 12:28:48 PM PDT 24
Finished	Jun 09 12:28:57 PM PDT 24
Peak memory	209664 kb
Host	smart-b7b22169-d250-48ef-88c8-aa4c248a77d3
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935364335 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 9.lc_ctrl_jtag_csr_bit_bash.2935364335
Directory	/workspace/9.lc_ctrl_jtag_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.892995290
Short name	T909
Test name
Test status
Simulation time	133335963 ps
CPU time	2.22 seconds
Started	Jun 09 12:28:50 PM PDT 24
Finished	Jun 09 12:28:52 PM PDT 24
Peak memory	217928 kb
Host	smart-79e4e092-81c2-4266-9308-3124a4837a50
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892995290 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 9.lc_ctrl_jtag_csr_hw_reset.892995290
Directory	/workspace/9.lc_ctrl_jtag_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.859175928
Short name	T978
Test name
Test status
Simulation time	204885314 ps
CPU time	2.62 seconds
Started	Jun 09 12:28:50 PM PDT 24
Finished	Jun 09 12:28:53 PM PDT 24
Peak memory	218204 kb
Host	smart-b8e0989c-8c7e-4dc4-993f-e3d7b14ebcdd
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859175 928 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.859175928
Directory	/workspace/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.2349991264
Short name	T946
Test name
Test status
Simulation time	693216973 ps
CPU time	2.1 seconds
Started	Jun 09 12:28:47 PM PDT 24
Finished	Jun 09 12:28:50 PM PDT 24
Peak memory	209688 kb
Host	smart-8349a99c-a616-45f9-afa8-3d65994810b1
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349991264 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_csr_rw.2349991264
Directory	/workspace/9.lc_ctrl_jtag_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.2799618205
Short name	T199
Test name
Test status
Simulation time	48412004 ps
CPU time	1.34 seconds
Started	Jun 09 12:28:49 PM PDT 24
Finished	Jun 09 12:28:51 PM PDT 24
Peak memory	209956 kb
Host	smart-e084d5b3-6744-403f-8455-45319ccf8994
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799618205 -assert nopostproc +UVM_TESTNA ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_same_csr_outstanding.2799618205
Directory	/workspace/9.lc_ctrl_jtag_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.3409280085
Short name	T200
Test name
Test status
Simulation time	20259706 ps
CPU time	1.2 seconds
Started	Jun 09 12:29:00 PM PDT 24
Finished	Jun 09 12:29:03 PM PDT 24
Peak memory	209880 kb
Host	smart-a0a9b99d-ce47-4389-b99f-04e8bf05b370
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409280085 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl _same_csr_outstanding.3409280085
Directory	/workspace/9.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.500334641
Short name	T965
Test name
Test status
Simulation time	73048220 ps
CPU time	2.03 seconds
Started	Jun 09 12:28:56 PM PDT 24
Finished	Jun 09 12:28:58 PM PDT 24
Peak memory	218048 kb
Host	smart-6895580f-0982-4fe9-8d04-dd2aaa37e343
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500334641 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_errors.500334641
Directory	/workspace/9.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/default/0.lc_ctrl_alert_test.3846263316
Short name	T624
Test name
Test status
Simulation time	79990330 ps
CPU time	1 seconds
Started	Jun 09 02:24:30 PM PDT 24
Finished	Jun 09 02:24:32 PM PDT 24
Peak memory	209464 kb
Host	smart-2a7f36b5-6790-4d7c-bec2-69c97d4e0033
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846263316 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_alert_test.3846263316
Directory	/workspace/0.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/0.lc_ctrl_errors.1701864150
Short name	T626
Test name
Test status
Simulation time	925181193 ps
CPU time	11.36 seconds
Started	Jun 09 02:24:22 PM PDT 24
Finished	Jun 09 02:24:34 PM PDT 24
Peak memory	218752 kb
Host	smart-eb6269ad-a4f6-48d5-9cad-804273337054
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1701864150 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_errors.1701864150
Directory	/workspace/0.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/0.lc_ctrl_jtag_access.1031125312
Short name	T869
Test name
Test status
Simulation time	527191521 ps
CPU time	5.58 seconds
Started	Jun 09 02:24:24 PM PDT 24
Finished	Jun 09 02:24:30 PM PDT 24
Peak memory	217732 kb
Host	smart-a976d330-5443-49da-a189-d1da3a579b1e
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031125312 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_access.1031125312
Directory	/workspace/0.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/0.lc_ctrl_jtag_errors.2270926300
Short name	T811
Test name
Test status
Simulation time	5478917727 ps
CPU time	78.23 seconds
Started	Jun 09 02:24:38 PM PDT 24
Finished	Jun 09 02:25:56 PM PDT 24
Peak memory	219616 kb
Host	smart-726eb2e4-9631-4840-9280-667f26b3918b
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270926300 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_er rors.2270926300
Directory	/workspace/0.lc_ctrl_jtag_errors/latest

Test location	/workspace/coverage/default/0.lc_ctrl_jtag_priority.1730544980
Short name	T451
Test name
Test status
Simulation time	413128127 ps
CPU time	9.17 seconds
Started	Jun 09 02:24:30 PM PDT 24
Finished	Jun 09 02:24:39 PM PDT 24
Peak memory	217796 kb
Host	smart-81392d1f-dd4f-4020-9f9a-dc65b976082f
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730544980 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_priority.1 730544980
Directory	/workspace/0.lc_ctrl_jtag_priority/latest

Test location	/workspace/coverage/default/0.lc_ctrl_jtag_prog_failure.91968629
Short name	T613
Test name
Test status
Simulation time	278473758 ps
CPU time	8.26 seconds
Started	Jun 09 02:24:22 PM PDT 24
Finished	Jun 09 02:24:30 PM PDT 24
Peak memory	218904 kb
Host	smart-574c056f-8fad-40d9-a311-2a96dc6471b7
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91968629 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_p rog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_p rog_failure.91968629
Directory	/workspace/0.lc_ctrl_jtag_prog_failure/latest

Test location	/workspace/coverage/default/0.lc_ctrl_jtag_regwen_during_op.85765281
Short name	T713
Test name
Test status
Simulation time	4865553896 ps
CPU time	31.8 seconds
Started	Jun 09 02:24:22 PM PDT 24
Finished	Jun 09 02:24:55 PM PDT 24
Peak memory	218276 kb
Host	smart-d6650d49-b1a1-40a0-9ce9-495110517d84
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85765281 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_r egwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jt ag_regwen_during_op.85765281
Directory	/workspace/0.lc_ctrl_jtag_regwen_during_op/latest

Test location	/workspace/coverage/default/0.lc_ctrl_jtag_smoke.3709134958
Short name	T379
Test name
Test status
Simulation time	2517395882 ps
CPU time	16.19 seconds
Started	Jun 09 02:24:12 PM PDT 24
Finished	Jun 09 02:24:29 PM PDT 24
Peak memory	218304 kb
Host	smart-d7fca920-163c-485b-b858-113ba3c1a410
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709134958 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_smoke. 3709134958
Directory	/workspace/0.lc_ctrl_jtag_smoke/latest

Test location	/workspace/coverage/default/0.lc_ctrl_jtag_state_failure.2031173623
Short name	T340
Test name
Test status
Simulation time	1160402360 ps
CPU time	31.05 seconds
Started	Jun 09 02:24:26 PM PDT 24
Finished	Jun 09 02:24:58 PM PDT 24
Peak memory	251420 kb
Host	smart-cfa2db03-4a06-4fdf-9ff9-a3a123eb0f32
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031173623 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jta g_state_failure.2031173623
Directory	/workspace/0.lc_ctrl_jtag_state_failure/latest

Test location	/workspace/coverage/default/0.lc_ctrl_jtag_state_post_trans.3355369961
Short name	T826
Test name
Test status
Simulation time	1954602056 ps
CPU time	21.03 seconds
Started	Jun 09 02:24:27 PM PDT 24
Finished	Jun 09 02:24:48 PM PDT 24
Peak memory	251412 kb
Host	smart-af5f42e8-c8e3-47eb-8be6-719e6a543158
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355369961 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_ jtag_state_post_trans.3355369961
Directory	/workspace/0.lc_ctrl_jtag_state_post_trans/latest

Test location	/workspace/coverage/default/0.lc_ctrl_prog_failure.2332552141
Short name	T239
Test name
Test status
Simulation time	46414824 ps
CPU time	1.75 seconds
Started	Jun 09 02:24:21 PM PDT 24
Finished	Jun 09 02:24:23 PM PDT 24
Peak memory	218692 kb
Host	smart-0adac6c5-6902-45ce-a203-9e767ea243b1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2332552141 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_prog_failure.2332552141
Directory	/workspace/0.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/0.lc_ctrl_regwen_during_op.1685941043
Short name	T673
Test name
Test status
Simulation time	1298908801 ps
CPU time	22.48 seconds
Started	Jun 09 02:24:30 PM PDT 24
Finished	Jun 09 02:24:52 PM PDT 24
Peak memory	218236 kb
Host	smart-00b47000-f98c-4347-b208-ab4c141eb8a7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1685941043 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_regwen_during_op.1685941043
Directory	/workspace/0.lc_ctrl_regwen_during_op/latest

Test location	/workspace/coverage/default/0.lc_ctrl_sec_cm.2959719736
Short name	T98
Test name
Test status
Simulation time	250624957 ps
CPU time	25.57 seconds
Started	Jun 09 02:24:20 PM PDT 24
Finished	Jun 09 02:24:46 PM PDT 24
Peak memory	283044 kb
Host	smart-a8351385-7e28-4b5a-b30d-31a1ff33cf14
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959719736 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_cm.2959719736
Directory	/workspace/0.lc_ctrl_sec_cm/latest

Test location	/workspace/coverage/default/0.lc_ctrl_sec_mubi.1903475686
Short name	T849
Test name
Test status
Simulation time	1403572520 ps
CPU time	11.86 seconds
Started	Jun 09 02:24:33 PM PDT 24
Finished	Jun 09 02:24:45 PM PDT 24
Peak memory	218728 kb
Host	smart-f0299b79-ede3-452e-b349-4fabfa11a5b0
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903475686 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_mubi.1903475686
Directory	/workspace/0.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/0.lc_ctrl_sec_token_digest.3880292140
Short name	T167
Test name
Test status
Simulation time	682942937 ps
CPU time	16.19 seconds
Started	Jun 09 02:24:21 PM PDT 24
Finished	Jun 09 02:24:37 PM PDT 24
Peak memory	218724 kb
Host	smart-f6456aab-785e-4401-ba5d-49d19bfc7190
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880292140 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_di gest.3880292140
Directory	/workspace/0.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/0.lc_ctrl_sec_token_mux.1915325388
Short name	T307
Test name
Test status
Simulation time	1824896243 ps
CPU time	7.42 seconds
Started	Jun 09 02:24:28 PM PDT 24
Finished	Jun 09 02:24:36 PM PDT 24
Peak memory	225828 kb
Host	smart-ccde30fd-9b06-4467-abfb-99b2d3b80d78
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915325388 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_mux.1 915325388
Directory	/workspace/0.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/0.lc_ctrl_security_escalation.2373311634
Short name	T427
Test name
Test status
Simulation time	304652201 ps
CPU time	7.73 seconds
Started	Jun 09 02:24:22 PM PDT 24
Finished	Jun 09 02:24:30 PM PDT 24
Peak memory	218744 kb
Host	smart-2cf658cd-f74c-43cd-932c-4cb6fa00b0ce
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2373311634 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_security_escalation.2373311634
Directory	/workspace/0.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/0.lc_ctrl_smoke.755897428
Short name	T664
Test name
Test status
Simulation time	78538915 ps
CPU time	2.4 seconds
Started	Jun 09 02:24:21 PM PDT 24
Finished	Jun 09 02:24:23 PM PDT 24
Peak memory	215108 kb
Host	smart-1b5b8c4d-c04b-455c-b76d-de02067fbf10
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=755897428 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_smoke.755897428
Directory	/workspace/0.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/0.lc_ctrl_state_failure.3371823229
Short name	T591
Test name
Test status
Simulation time	1736600191 ps
CPU time	35.68 seconds
Started	Jun 09 02:24:26 PM PDT 24
Finished	Jun 09 02:25:03 PM PDT 24
Peak memory	251420 kb
Host	smart-12f76a6c-d37e-445d-8cde-8324c8774216
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3371823229 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_failure.3371823229
Directory	/workspace/0.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/0.lc_ctrl_state_post_trans.1676177935
Short name	T759
Test name
Test status
Simulation time	46885493 ps
CPU time	7.73 seconds
Started	Jun 09 02:24:10 PM PDT 24
Finished	Jun 09 02:24:18 PM PDT 24
Peak memory	251384 kb
Host	smart-6559f2d6-c307-4ce4-af0c-938e69262ffb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1676177935 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_post_trans.1676177935
Directory	/workspace/0.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/0.lc_ctrl_stress_all.747050247
Short name	T86
Test name
Test status
Simulation time	8237505699 ps
CPU time	296.65 seconds
Started	Jun 09 02:24:20 PM PDT 24
Finished	Jun 09 02:29:17 PM PDT 24
Peak memory	272512 kb
Host	smart-a7b5d15b-6043-47a3-b1d4-af36fc8fb050
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747050247 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_ TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_stress_all.747050247
Directory	/workspace/0.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/0.lc_ctrl_volatile_unlock_smoke.2759738883
Short name	T784
Test name
Test status
Simulation time	30182682 ps
CPU time	0.85 seconds
Started	Jun 09 02:24:16 PM PDT 24
Finished	Jun 09 02:24:17 PM PDT 24
Peak memory	209356 kb
Host	smart-df345372-012a-400e-a594-be16827d48b0
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759738883 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ct rl_volatile_unlock_smoke.2759738883
Directory	/workspace/0.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/1.lc_ctrl_alert_test.96903706
Short name	T71
Test name
Test status
Simulation time	96374532 ps
CPU time	0.95 seconds
Started	Jun 09 02:24:30 PM PDT 24
Finished	Jun 09 02:24:31 PM PDT 24
Peak memory	209344 kb
Host	smart-a2d8daf3-f106-4473-acf7-d90859de17a1
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96903706 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_alert_test.96903706
Directory	/workspace/1.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/1.lc_ctrl_claim_transition_if.73937528
Short name	T270
Test name
Test status
Simulation time	37318792 ps
CPU time	0.9 seconds
Started	Jun 09 02:24:17 PM PDT 24
Finished	Jun 09 02:24:18 PM PDT 24
Peak memory	209484 kb
Host	smart-c32cdbe3-55f2-4b53-a6c5-e56ce1a92f15
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=73937528 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_claim_transition_if.73937528
Directory	/workspace/1.lc_ctrl_claim_transition_if/latest

Test location	/workspace/coverage/default/1.lc_ctrl_errors.2821769774
Short name	T233
Test name
Test status
Simulation time	375412405 ps
CPU time	7.62 seconds
Started	Jun 09 02:24:33 PM PDT 24
Finished	Jun 09 02:24:41 PM PDT 24
Peak memory	218904 kb
Host	smart-01a5e454-85f0-46b2-b755-ff89311ca322
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2821769774 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_errors.2821769774
Directory	/workspace/1.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/1.lc_ctrl_jtag_access.3590286299
Short name	T630
Test name
Test status
Simulation time	371110240 ps
CPU time	5.36 seconds
Started	Jun 09 02:24:21 PM PDT 24
Finished	Jun 09 02:24:27 PM PDT 24
Peak memory	217708 kb
Host	smart-a7eac64f-250e-4258-9777-f0ffb522022a
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590286299 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_access.3590286299
Directory	/workspace/1.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/1.lc_ctrl_jtag_errors.3858711011
Short name	T715
Test name
Test status
Simulation time	10930483867 ps
CPU time	39.57 seconds
Started	Jun 09 02:24:32 PM PDT 24
Finished	Jun 09 02:25:12 PM PDT 24
Peak memory	226612 kb
Host	smart-4cf2ace6-efb0-45a8-bc5c-9e04236ea258
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858711011 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_er rors.3858711011
Directory	/workspace/1.lc_ctrl_jtag_errors/latest

Test location	/workspace/coverage/default/1.lc_ctrl_jtag_priority.2352061459
Short name	T649
Test name
Test status
Simulation time	742700938 ps
CPU time	9.98 seconds
Started	Jun 09 02:24:32 PM PDT 24
Finished	Jun 09 02:24:43 PM PDT 24
Peak memory	218092 kb
Host	smart-a2547620-1818-42dc-a90f-26afc9051e44
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352061459 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_priority.2 352061459
Directory	/workspace/1.lc_ctrl_jtag_priority/latest

Test location	/workspace/coverage/default/1.lc_ctrl_jtag_prog_failure.1096859351
Short name	T710
Test name
Test status
Simulation time	351513200 ps
CPU time	5.53 seconds
Started	Jun 09 02:24:20 PM PDT 24
Finished	Jun 09 02:24:25 PM PDT 24
Peak memory	218636 kb
Host	smart-7c9f2f12-b82d-4363-ad83-bd91522b8768
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096859351 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag _prog_failure.1096859351
Directory	/workspace/1.lc_ctrl_jtag_prog_failure/latest

Test location	/workspace/coverage/default/1.lc_ctrl_jtag_regwen_during_op.3352474648
Short name	T226
Test name
Test status
Simulation time	8202887511 ps
CPU time	11.92 seconds
Started	Jun 09 02:24:32 PM PDT 24
Finished	Jun 09 02:24:44 PM PDT 24
Peak memory	218272 kb
Host	smart-aa3e09cd-cf0b-42f3-bb63-1224d9d4e2a4
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352474648 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_ jtag_regwen_during_op.3352474648
Directory	/workspace/1.lc_ctrl_jtag_regwen_during_op/latest

Test location	/workspace/coverage/default/1.lc_ctrl_jtag_smoke.2098547133
Short name	T299
Test name
Test status
Simulation time	3347175851 ps
CPU time	7.85 seconds
Started	Jun 09 02:24:25 PM PDT 24
Finished	Jun 09 02:24:34 PM PDT 24
Peak memory	218256 kb
Host	smart-001f1604-44a9-4e92-94ce-83d23c0a3763
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098547133 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_smoke. 2098547133
Directory	/workspace/1.lc_ctrl_jtag_smoke/latest

Test location	/workspace/coverage/default/1.lc_ctrl_jtag_state_failure.2907829403
Short name	T5
Test name
Test status
Simulation time	11253594306 ps
CPU time	77.76 seconds
Started	Jun 09 02:24:32 PM PDT 24
Finished	Jun 09 02:25:51 PM PDT 24
Peak memory	276176 kb
Host	smart-250358a0-d6d3-47b2-a54f-500add21d0c7
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907829403 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jta g_state_failure.2907829403
Directory	/workspace/1.lc_ctrl_jtag_state_failure/latest

Test location	/workspace/coverage/default/1.lc_ctrl_jtag_state_post_trans.3561577731
Short name	T96
Test name
Test status
Simulation time	3256496928 ps
CPU time	18.1 seconds
Started	Jun 09 02:24:22 PM PDT 24
Finished	Jun 09 02:24:41 PM PDT 24
Peak memory	251412 kb
Host	smart-b4cccfa2-9ad4-4b69-b496-8c299a09c3e7
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561577731 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_ jtag_state_post_trans.3561577731
Directory	/workspace/1.lc_ctrl_jtag_state_post_trans/latest

Test location	/workspace/coverage/default/1.lc_ctrl_prog_failure.3477857945
Short name	T650
Test name
Test status
Simulation time	83598650 ps
CPU time	3.97 seconds
Started	Jun 09 02:24:32 PM PDT 24
Finished	Jun 09 02:24:36 PM PDT 24
Peak memory	223132 kb
Host	smart-a700b678-a79f-4a02-b519-082eddfe0fce
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3477857945 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_prog_failure.3477857945
Directory	/workspace/1.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/1.lc_ctrl_regwen_during_op.1127529088
Short name	T503
Test name
Test status
Simulation time	312971453 ps
CPU time	11.54 seconds
Started	Jun 09 02:24:34 PM PDT 24
Finished	Jun 09 02:24:46 PM PDT 24
Peak memory	215164 kb
Host	smart-1f8846b8-d0e5-4b21-946a-3e27aa856c00
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1127529088 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_regwen_during_op.1127529088
Directory	/workspace/1.lc_ctrl_regwen_during_op/latest

Test location	/workspace/coverage/default/1.lc_ctrl_sec_mubi.4256683326
Short name	T615
Test name
Test status
Simulation time	1016553658 ps
CPU time	11.19 seconds
Started	Jun 09 02:24:33 PM PDT 24
Finished	Jun 09 02:24:44 PM PDT 24
Peak memory	226568 kb
Host	smart-bcb21461-6762-4bb4-abbd-f305c06ffa7e
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256683326 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_mubi.4256683326
Directory	/workspace/1.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/1.lc_ctrl_sec_token_digest.3724614684
Short name	T438
Test name
Test status
Simulation time	2383615813 ps
CPU time	26.56 seconds
Started	Jun 09 02:24:35 PM PDT 24
Finished	Jun 09 02:25:02 PM PDT 24
Peak memory	218780 kb
Host	smart-ed82071a-9055-4f2e-be95-e40310fcf3c1
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724614684 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_di gest.3724614684
Directory	/workspace/1.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/1.lc_ctrl_sec_token_mux.2891890711
Short name	T383
Test name
Test status
Simulation time	316518825 ps
CPU time	9.73 seconds
Started	Jun 09 02:24:32 PM PDT 24
Finished	Jun 09 02:24:42 PM PDT 24
Peak memory	225928 kb
Host	smart-e85129f8-1893-4a1a-a33e-2f87d87d9676
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891890711 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_mux.2 891890711
Directory	/workspace/1.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/1.lc_ctrl_security_escalation.2692408652
Short name	T601
Test name
Test status
Simulation time	325930270 ps
CPU time	11.08 seconds
Started	Jun 09 02:24:22 PM PDT 24
Finished	Jun 09 02:24:33 PM PDT 24
Peak memory	218748 kb
Host	smart-409dd54e-34da-44cc-9e7e-8cee01d479ed
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2692408652 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_security_escalation.2692408652
Directory	/workspace/1.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/1.lc_ctrl_smoke.1408892557
Short name	T75
Test name
Test status
Simulation time	28588398 ps
CPU time	2.09 seconds
Started	Jun 09 02:24:35 PM PDT 24
Finished	Jun 09 02:24:37 PM PDT 24
Peak memory	218288 kb
Host	smart-5c7546e1-4572-4206-90ce-2d5bc0e1955f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1408892557 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_smoke.1408892557
Directory	/workspace/1.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/1.lc_ctrl_state_failure.2201327642
Short name	T771
Test name
Test status
Simulation time	150484513 ps
CPU time	19.94 seconds
Started	Jun 09 02:24:28 PM PDT 24
Finished	Jun 09 02:24:48 PM PDT 24
Peak memory	251432 kb
Host	smart-39150d24-06dc-4cc1-9f5c-c1f1e187bf2d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2201327642 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_failure.2201327642
Directory	/workspace/1.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/1.lc_ctrl_state_post_trans.3097403954
Short name	T686
Test name
Test status
Simulation time	194431098 ps
CPU time	7.41 seconds
Started	Jun 09 02:24:33 PM PDT 24
Finished	Jun 09 02:24:41 PM PDT 24
Peak memory	247664 kb
Host	smart-123b6381-16e5-4481-8054-cc338d510b9c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3097403954 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_post_trans.3097403954
Directory	/workspace/1.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/1.lc_ctrl_stress_all.1162504822
Short name	T495
Test name
Test status
Simulation time	36397140431 ps
CPU time	252.92 seconds
Started	Jun 09 02:24:27 PM PDT 24
Finished	Jun 09 02:28:40 PM PDT 24
Peak memory	251480 kb
Host	smart-722be8f3-01da-4d41-9e17-aaf195621700
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162504822 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_stress_all.1162504822
Directory	/workspace/1.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/1.lc_ctrl_volatile_unlock_smoke.1647587957
Short name	T785
Test name
Test status
Simulation time	15942501 ps
CPU time	1.01 seconds
Started	Jun 09 02:24:22 PM PDT 24
Finished	Jun 09 02:24:23 PM PDT 24
Peak memory	218316 kb
Host	smart-08f19995-184b-4704-8b1e-e6e954db2e4a
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647587957 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ct rl_volatile_unlock_smoke.1647587957
Directory	/workspace/1.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/10.lc_ctrl_alert_test.2820389141
Short name	T779
Test name
Test status
Simulation time	69589377 ps
CPU time	1.12 seconds
Started	Jun 09 02:24:52 PM PDT 24
Finished	Jun 09 02:24:53 PM PDT 24
Peak memory	209476 kb
Host	smart-06a4c078-0fda-4392-897f-9865023691e1
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820389141 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_alert_test.2820389141
Directory	/workspace/10.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/10.lc_ctrl_errors.3271972820
Short name	T300
Test name
Test status
Simulation time	381178452 ps
CPU time	11.7 seconds
Started	Jun 09 02:24:53 PM PDT 24
Finished	Jun 09 02:25:05 PM PDT 24
Peak memory	218700 kb
Host	smart-a5c0ba3d-188a-46e1-8623-049f7cce62bf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3271972820 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_errors.3271972820
Directory	/workspace/10.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/10.lc_ctrl_jtag_access.2522249150
Short name	T35
Test name
Test status
Simulation time	585588436 ps
CPU time	2.34 seconds
Started	Jun 09 02:24:50 PM PDT 24
Finished	Jun 09 02:24:53 PM PDT 24
Peak memory	217620 kb
Host	smart-d3918b1e-142c-4271-9cc8-27d7bd31ec0f
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522249150 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_access.2522249150
Directory	/workspace/10.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/10.lc_ctrl_jtag_errors.2255128847
Short name	T569
Test name
Test status
Simulation time	5874555361 ps
CPU time	23.31 seconds
Started	Jun 09 02:25:06 PM PDT 24
Finished	Jun 09 02:25:30 PM PDT 24
Peak memory	219032 kb
Host	smart-2103394f-f055-4d86-a46c-ad8bf090cfe9
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255128847 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_e rrors.2255128847
Directory	/workspace/10.lc_ctrl_jtag_errors/latest

Test location	/workspace/coverage/default/10.lc_ctrl_jtag_prog_failure.4035701692
Short name	T724
Test name
Test status
Simulation time	1518014416 ps
CPU time	19.87 seconds
Started	Jun 09 02:24:59 PM PDT 24
Finished	Jun 09 02:25:19 PM PDT 24
Peak memory	218700 kb
Host	smart-c8584305-d03c-4434-bff2-b6b52aa7eb49
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035701692 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jta g_prog_failure.4035701692
Directory	/workspace/10.lc_ctrl_jtag_prog_failure/latest

Test location	/workspace/coverage/default/10.lc_ctrl_jtag_smoke.14690551
Short name	T160
Test name
Test status
Simulation time	261599325 ps
CPU time	3.52 seconds
Started	Jun 09 02:24:58 PM PDT 24
Finished	Jun 09 02:25:02 PM PDT 24
Peak memory	218232 kb
Host	smart-137c0724-ab7e-4950-a99e-217dc1083493
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14690551 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_smoke.14690551
Directory	/workspace/10.lc_ctrl_jtag_smoke/latest

Test location	/workspace/coverage/default/10.lc_ctrl_jtag_state_failure.2870628078
Short name	T865
Test name
Test status
Simulation time	2886554426 ps
CPU time	30.44 seconds
Started	Jun 09 02:24:46 PM PDT 24
Finished	Jun 09 02:25:17 PM PDT 24
Peak memory	267896 kb
Host	smart-b0b988b0-63f5-4a8f-88f3-b6f14ebede90
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870628078 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jt ag_state_failure.2870628078
Directory	/workspace/10.lc_ctrl_jtag_state_failure/latest

Test location	/workspace/coverage/default/10.lc_ctrl_jtag_state_post_trans.4182292300
Short name	T608
Test name
Test status
Simulation time	1819733832 ps
CPU time	8.47 seconds
Started	Jun 09 02:24:50 PM PDT 24
Finished	Jun 09 02:24:59 PM PDT 24
Peak memory	226832 kb
Host	smart-81dde37a-18bc-436d-ad56-289c6e3bbc47
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182292300 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl _jtag_state_post_trans.4182292300
Directory	/workspace/10.lc_ctrl_jtag_state_post_trans/latest

Test location	/workspace/coverage/default/10.lc_ctrl_prog_failure.1003784873
Short name	T830
Test name
Test status
Simulation time	29650770 ps
CPU time	2.02 seconds
Started	Jun 09 02:25:08 PM PDT 24
Finished	Jun 09 02:25:10 PM PDT 24
Peak memory	222560 kb
Host	smart-9d8d3e29-cb4d-48bc-9fe1-52912d7e791d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1003784873 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_prog_failure.1003784873
Directory	/workspace/10.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/10.lc_ctrl_sec_mubi.718226970
Short name	T625
Test name
Test status
Simulation time	771351368 ps
CPU time	8.96 seconds
Started	Jun 09 02:24:46 PM PDT 24
Finished	Jun 09 02:24:55 PM PDT 24
Peak memory	218676 kb
Host	smart-6f303cfd-f2de-4f43-be9d-28c6d3a44d31
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718226970 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_mubi.718226970
Directory	/workspace/10.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/10.lc_ctrl_sec_token_digest.2286977595
Short name	T703
Test name
Test status
Simulation time	1995277446 ps
CPU time	15.03 seconds
Started	Jun 09 02:24:51 PM PDT 24
Finished	Jun 09 02:25:06 PM PDT 24
Peak memory	226512 kb
Host	smart-3a135fc4-fa7c-43cf-8f11-d54ed4abc02d
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286977595 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_d igest.2286977595
Directory	/workspace/10.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/10.lc_ctrl_sec_token_mux.2852785367
Short name	T487
Test name
Test status
Simulation time	1324382915 ps
CPU time	9.7 seconds
Started	Jun 09 02:25:27 PM PDT 24
Finished	Jun 09 02:25:37 PM PDT 24
Peak memory	218728 kb
Host	smart-edb5be97-b2c2-4bb5-9a11-c4fa4c6f2dc6
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852785367 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_mux. 2852785367
Directory	/workspace/10.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/10.lc_ctrl_security_escalation.24003389
Short name	T774
Test name
Test status
Simulation time	469204407 ps
CPU time	14.62 seconds
Started	Jun 09 02:24:49 PM PDT 24
Finished	Jun 09 02:25:04 PM PDT 24
Peak memory	226556 kb
Host	smart-d65736b9-051d-4ec9-aeaf-2d0398135697
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=24003389 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_security_escalation.24003389
Directory	/workspace/10.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/10.lc_ctrl_smoke.2782755014
Short name	T722
Test name
Test status
Simulation time	49201031 ps
CPU time	2.63 seconds
Started	Jun 09 02:24:56 PM PDT 24
Finished	Jun 09 02:24:59 PM PDT 24
Peak memory	218224 kb
Host	smart-7b174142-e7d4-4c6b-9c60-dad8efdf5dd3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2782755014 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_smoke.2782755014
Directory	/workspace/10.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/10.lc_ctrl_state_failure.3960311074
Short name	T677
Test name
Test status
Simulation time	166652153 ps
CPU time	23.23 seconds
Started	Jun 09 02:25:07 PM PDT 24
Finished	Jun 09 02:25:30 PM PDT 24
Peak memory	251400 kb
Host	smart-a6e24704-3aed-446d-81d9-40eb095c9885
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3960311074 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_failure.3960311074
Directory	/workspace/10.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/10.lc_ctrl_state_post_trans.4095668674
Short name	T636
Test name
Test status
Simulation time	99071204 ps
CPU time	6.47 seconds
Started	Jun 09 02:24:49 PM PDT 24
Finished	Jun 09 02:24:55 PM PDT 24
Peak memory	251304 kb
Host	smart-74845638-3371-49ae-a76f-bcf04c19c465
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4095668674 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_post_trans.4095668674
Directory	/workspace/10.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/10.lc_ctrl_stress_all.4220865127
Short name	T756
Test name
Test status
Simulation time	46293898136 ps
CPU time	258.77 seconds
Started	Jun 09 02:25:04 PM PDT 24
Finished	Jun 09 02:29:23 PM PDT 24
Peak memory	275884 kb
Host	smart-cd6bd650-dfc3-4309-9ff3-e4833d8897db
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220865127 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_stress_all.4220865127
Directory	/workspace/10.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/10.lc_ctrl_stress_all_with_rand_reset.1451471422
Short name	T214
Test name
Test status
Simulation time	70762134118 ps
CPU time	626.58 seconds
Started	Jun 09 02:24:50 PM PDT 24
Finished	Jun 09 02:35:17 PM PDT 24
Peak memory	286148 kb
Host	smart-5ceab9ba-f34c-4628-91dc-83bd67f02f56
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=1451471422 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_stress_all_with_rand_reset.1451471422
Directory	/workspace/10.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/10.lc_ctrl_volatile_unlock_smoke.996567717
Short name	T806
Test name
Test status
Simulation time	13341199 ps
CPU time	0.85 seconds
Started	Jun 09 02:24:47 PM PDT 24
Finished	Jun 09 02:24:49 PM PDT 24
Peak memory	209568 kb
Host	smart-cc7daceb-3aa4-4483-96b2-9f983bc5f522
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996567717 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ct rl_volatile_unlock_smoke.996567717
Directory	/workspace/10.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/11.lc_ctrl_alert_test.2618862826
Short name	T448
Test name
Test status
Simulation time	32507655 ps
CPU time	1.03 seconds
Started	Jun 09 02:24:58 PM PDT 24
Finished	Jun 09 02:25:00 PM PDT 24
Peak memory	209432 kb
Host	smart-6539db4d-ad48-4e07-bb6e-20355c3aea64
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618862826 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_alert_test.2618862826
Directory	/workspace/11.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/11.lc_ctrl_errors.380626857
Short name	T364
Test name
Test status
Simulation time	818083921 ps
CPU time	12.09 seconds
Started	Jun 09 02:24:55 PM PDT 24
Finished	Jun 09 02:25:07 PM PDT 24
Peak memory	218676 kb
Host	smart-e79f10b0-3449-4187-9412-f3d71cc4daf1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=380626857 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_errors.380626857
Directory	/workspace/11.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/11.lc_ctrl_jtag_access.1681352947
Short name	T773
Test name
Test status
Simulation time	1401163445 ps
CPU time	27.82 seconds
Started	Jun 09 02:25:02 PM PDT 24
Finished	Jun 09 02:25:30 PM PDT 24
Peak memory	217856 kb
Host	smart-79909f15-af56-47fa-beef-a923cc98e39f
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681352947 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_access.1681352947
Directory	/workspace/11.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/11.lc_ctrl_jtag_errors.3172349487
Short name	T288
Test name
Test status
Simulation time	3892669247 ps
CPU time	46.69 seconds
Started	Jun 09 02:24:49 PM PDT 24
Finished	Jun 09 02:25:36 PM PDT 24
Peak memory	220520 kb
Host	smart-2361cfa1-1ec4-4de0-ba50-3c2fe09e76c1
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172349487 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_e rrors.3172349487
Directory	/workspace/11.lc_ctrl_jtag_errors/latest

Test location	/workspace/coverage/default/11.lc_ctrl_jtag_prog_failure.1889930285
Short name	T547
Test name
Test status
Simulation time	597903031 ps
CPU time	5.77 seconds
Started	Jun 09 02:25:28 PM PDT 24
Finished	Jun 09 02:25:34 PM PDT 24
Peak memory	218704 kb
Host	smart-10781aad-ad79-4e61-8651-01c1d7243938
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889930285 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jta g_prog_failure.1889930285
Directory	/workspace/11.lc_ctrl_jtag_prog_failure/latest

Test location	/workspace/coverage/default/11.lc_ctrl_jtag_smoke.78026844
Short name	T832
Test name
Test status
Simulation time	400082408 ps
CPU time	11.06 seconds
Started	Jun 09 02:24:49 PM PDT 24
Finished	Jun 09 02:25:00 PM PDT 24
Peak memory	218212 kb
Host	smart-ad54b2af-2f5d-4d1f-9543-869d27211950
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78026844 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_smoke.78026844
Directory	/workspace/11.lc_ctrl_jtag_smoke/latest

Test location	/workspace/coverage/default/11.lc_ctrl_jtag_state_failure.2447755915
Short name	T738
Test name
Test status
Simulation time	1343545402 ps
CPU time	58.03 seconds
Started	Jun 09 02:24:58 PM PDT 24
Finished	Jun 09 02:25:57 PM PDT 24
Peak memory	284132 kb
Host	smart-6d7ffcbf-ccfc-48bd-8d0a-38ab63652c5d
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447755915 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jt ag_state_failure.2447755915
Directory	/workspace/11.lc_ctrl_jtag_state_failure/latest

Test location	/workspace/coverage/default/11.lc_ctrl_prog_failure.1904706851
Short name	T709
Test name
Test status
Simulation time	135873651 ps
CPU time	2.96 seconds
Started	Jun 09 02:25:05 PM PDT 24
Finished	Jun 09 02:25:08 PM PDT 24
Peak memory	218656 kb
Host	smart-6fd343a4-5a89-4b0f-a113-59ed338bd9a3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1904706851 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_prog_failure.1904706851
Directory	/workspace/11.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/11.lc_ctrl_sec_mubi.497455869
Short name	T527
Test name
Test status
Simulation time	239577124 ps
CPU time	12.13 seconds
Started	Jun 09 02:24:56 PM PDT 24
Finished	Jun 09 02:25:09 PM PDT 24
Peak memory	218800 kb
Host	smart-532d2760-9e93-4636-a28d-f204c86e5bb8
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497455869 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_mubi.497455869
Directory	/workspace/11.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/11.lc_ctrl_sec_token_digest.660120671
Short name	T814
Test name
Test status
Simulation time	294556382 ps
CPU time	13.51 seconds
Started	Jun 09 02:24:51 PM PDT 24
Finished	Jun 09 02:25:05 PM PDT 24
Peak memory	226428 kb
Host	smart-0018c260-2d46-4e79-a6be-2e2a9a8141eb
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660120671 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_di gest.660120671
Directory	/workspace/11.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/11.lc_ctrl_sec_token_mux.708999405
Short name	T857
Test name
Test status
Simulation time	589804631 ps
CPU time	7.11 seconds
Started	Jun 09 02:24:52 PM PDT 24
Finished	Jun 09 02:24:59 PM PDT 24
Peak memory	218716 kb
Host	smart-97f0a62c-7beb-460d-b028-91a0f0f08a4f
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708999405 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_mux.708999405
Directory	/workspace/11.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/11.lc_ctrl_smoke.3291746665
Short name	T440
Test name
Test status
Simulation time	216493375 ps
CPU time	2.2 seconds
Started	Jun 09 02:24:49 PM PDT 24
Finished	Jun 09 02:24:57 PM PDT 24
Peak memory	214700 kb
Host	smart-021675ef-0a66-485f-aac8-bef1a5b7b800
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3291746665 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_smoke.3291746665
Directory	/workspace/11.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/11.lc_ctrl_state_failure.2396109779
Short name	T672
Test name
Test status
Simulation time	1103845251 ps
CPU time	22.52 seconds
Started	Jun 09 02:24:51 PM PDT 24
Finished	Jun 09 02:25:13 PM PDT 24
Peak memory	251448 kb
Host	smart-c702e713-6cba-4c19-b2a8-f4478a83a642
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2396109779 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_failure.2396109779
Directory	/workspace/11.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/11.lc_ctrl_state_post_trans.437544690
Short name	T105
Test name
Test status
Simulation time	84399503 ps
CPU time	6.35 seconds
Started	Jun 09 02:25:03 PM PDT 24
Finished	Jun 09 02:25:09 PM PDT 24
Peak memory	247580 kb
Host	smart-adc18158-6e91-42e8-86d7-62e498a501e1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=437544690 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_post_trans.437544690
Directory	/workspace/11.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/11.lc_ctrl_stress_all.3516909209
Short name	T175
Test name
Test status
Simulation time	609078106 ps
CPU time	30.34 seconds
Started	Jun 09 02:25:01 PM PDT 24
Finished	Jun 09 02:25:31 PM PDT 24
Peak memory	251416 kb
Host	smart-064407d3-0117-43de-97e7-6590d46cf357
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516909209 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_stress_all.3516909209
Directory	/workspace/11.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/11.lc_ctrl_stress_all_with_rand_reset.4182604197
Short name	T151
Test name
Test status
Simulation time	220878720808 ps
CPU time	311.95 seconds
Started	Jun 09 02:25:03 PM PDT 24
Finished	Jun 09 02:30:15 PM PDT 24
Peak memory	281720 kb
Host	smart-4d332bfa-4354-43ca-9c4f-e245677750f0
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=4182604197 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_stress_all_with_rand_reset.4182604197
Directory	/workspace/11.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/11.lc_ctrl_volatile_unlock_smoke.413382957
Short name	T384
Test name
Test status
Simulation time	11840818 ps
CPU time	0.93 seconds
Started	Jun 09 02:24:55 PM PDT 24
Finished	Jun 09 02:24:57 PM PDT 24
Peak memory	212360 kb
Host	smart-4fdaf99b-3dc5-4090-8227-4bca1d5e9c61
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413382957 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ct rl_volatile_unlock_smoke.413382957
Directory	/workspace/11.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/12.lc_ctrl_alert_test.1296997774
Short name	T698
Test name
Test status
Simulation time	57177893 ps
CPU time	1.06 seconds
Started	Jun 09 02:24:58 PM PDT 24
Finished	Jun 09 02:24:59 PM PDT 24
Peak memory	209444 kb
Host	smart-1a371d88-8b5c-4656-95e2-dd39a8160049
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296997774 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_alert_test.1296997774
Directory	/workspace/12.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/12.lc_ctrl_errors.3714327630
Short name	T824
Test name
Test status
Simulation time	485623897 ps
CPU time	11.99 seconds
Started	Jun 09 02:25:02 PM PDT 24
Finished	Jun 09 02:25:15 PM PDT 24
Peak memory	218628 kb
Host	smart-07476b1d-55ad-4eb7-be68-5185aabe3a1d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3714327630 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_errors.3714327630
Directory	/workspace/12.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/12.lc_ctrl_jtag_access.1064523358
Short name	T870
Test name
Test status
Simulation time	1308610881 ps
CPU time	8.62 seconds
Started	Jun 09 02:25:00 PM PDT 24
Finished	Jun 09 02:25:09 PM PDT 24
Peak memory	217572 kb
Host	smart-5c33e032-75fb-47e5-98aa-04bb8897aa20
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064523358 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_access.1064523358
Directory	/workspace/12.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/12.lc_ctrl_jtag_errors.3877132610
Short name	T311
Test name
Test status
Simulation time	2607281448 ps
CPU time	38.84 seconds
Started	Jun 09 02:25:03 PM PDT 24
Finished	Jun 09 02:25:42 PM PDT 24
Peak memory	219496 kb
Host	smart-fb5ef56e-2b7d-4ddf-a0bf-cd85bc031050
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877132610 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_e rrors.3877132610
Directory	/workspace/12.lc_ctrl_jtag_errors/latest

Test location	/workspace/coverage/default/12.lc_ctrl_jtag_prog_failure.1844240746
Short name	T600
Test name
Test status
Simulation time	373992064 ps
CPU time	12.19 seconds
Started	Jun 09 02:24:52 PM PDT 24
Finished	Jun 09 02:25:09 PM PDT 24
Peak memory	218724 kb
Host	smart-ae9873fb-38d2-40e2-880a-865128dc14e2
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844240746 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jta g_prog_failure.1844240746
Directory	/workspace/12.lc_ctrl_jtag_prog_failure/latest

Test location	/workspace/coverage/default/12.lc_ctrl_jtag_smoke.2959554512
Short name	T807
Test name
Test status
Simulation time	63582784 ps
CPU time	2.5 seconds
Started	Jun 09 02:25:03 PM PDT 24
Finished	Jun 09 02:25:05 PM PDT 24
Peak memory	218176 kb
Host	smart-45120352-f22c-4c25-a16d-350af554bbc7
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959554512 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_smoke .2959554512
Directory	/workspace/12.lc_ctrl_jtag_smoke/latest

Test location	/workspace/coverage/default/12.lc_ctrl_jtag_state_failure.1081389595
Short name	T346
Test name
Test status
Simulation time	4072230438 ps
CPU time	43.5 seconds
Started	Jun 09 02:25:13 PM PDT 24
Finished	Jun 09 02:25:56 PM PDT 24
Peak memory	273196 kb
Host	smart-d39ea95b-e786-43da-bfb7-5a79a8134be8
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081389595 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jt ag_state_failure.1081389595
Directory	/workspace/12.lc_ctrl_jtag_state_failure/latest

Test location	/workspace/coverage/default/12.lc_ctrl_jtag_state_post_trans.3992081736
Short name	T862
Test name
Test status
Simulation time	1232755942 ps
CPU time	21.11 seconds
Started	Jun 09 02:24:53 PM PDT 24
Finished	Jun 09 02:25:15 PM PDT 24
Peak memory	251416 kb
Host	smart-a5a49c4c-5805-4763-bc2d-1ab35be955d4
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992081736 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl _jtag_state_post_trans.3992081736
Directory	/workspace/12.lc_ctrl_jtag_state_post_trans/latest

Test location	/workspace/coverage/default/12.lc_ctrl_prog_failure.4129121536
Short name	T331
Test name
Test status
Simulation time	76380660 ps
CPU time	3.88 seconds
Started	Jun 09 02:24:51 PM PDT 24
Finished	Jun 09 02:24:57 PM PDT 24
Peak memory	223224 kb
Host	smart-e330520d-715d-4e01-be73-6ff3df34fb4e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4129121536 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_prog_failure.4129121536
Directory	/workspace/12.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/12.lc_ctrl_sec_mubi.1049423532
Short name	T343
Test name
Test status
Simulation time	426072564 ps
CPU time	10.97 seconds
Started	Jun 09 02:25:01 PM PDT 24
Finished	Jun 09 02:25:13 PM PDT 24
Peak memory	218804 kb
Host	smart-fa4be7c2-5ec9-4e10-a56a-0b8361d09cde
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049423532 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_mubi.1049423532
Directory	/workspace/12.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/12.lc_ctrl_sec_token_digest.508467929
Short name	T705
Test name
Test status
Simulation time	811473728 ps
CPU time	14 seconds
Started	Jun 09 02:25:02 PM PDT 24
Finished	Jun 09 02:25:16 PM PDT 24
Peak memory	218704 kb
Host	smart-555c7a0f-2ef9-4c1b-8d9f-22c3fabe7327
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508467929 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_di gest.508467929
Directory	/workspace/12.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/12.lc_ctrl_sec_token_mux.1033926830
Short name	T352
Test name
Test status
Simulation time	2719916062 ps
CPU time	9.72 seconds
Started	Jun 09 02:25:00 PM PDT 24
Finished	Jun 09 02:25:09 PM PDT 24
Peak memory	226608 kb
Host	smart-2aa87f89-b1b6-41ef-bc76-acd5c7d3a1f7
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033926830 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_mux. 1033926830
Directory	/workspace/12.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/12.lc_ctrl_smoke.1639547229
Short name	T388
Test name
Test status
Simulation time	137627740 ps
CPU time	2.56 seconds
Started	Jun 09 02:24:52 PM PDT 24
Finished	Jun 09 02:24:55 PM PDT 24
Peak memory	218224 kb
Host	smart-61942f28-bec6-4ae0-9b8d-6667d1880a90
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1639547229 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_smoke.1639547229
Directory	/workspace/12.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/12.lc_ctrl_state_failure.409686027
Short name	T426
Test name
Test status
Simulation time	871772830 ps
CPU time	24.28 seconds
Started	Jun 09 02:24:59 PM PDT 24
Finished	Jun 09 02:25:23 PM PDT 24
Peak memory	251472 kb
Host	smart-6e4a4c33-c135-45eb-ac2e-d5897a7ca35d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=409686027 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_failure.409686027
Directory	/workspace/12.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/12.lc_ctrl_state_post_trans.3487946501
Short name	T232
Test name
Test status
Simulation time	137112852 ps
CPU time	9.18 seconds
Started	Jun 09 02:24:52 PM PDT 24
Finished	Jun 09 02:25:01 PM PDT 24
Peak memory	251524 kb
Host	smart-9daf93b9-515d-47ee-9157-b492a26c77ab
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3487946501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_post_trans.3487946501
Directory	/workspace/12.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/12.lc_ctrl_stress_all.2180966664
Short name	T297
Test name
Test status
Simulation time	6951690939 ps
CPU time	47.58 seconds
Started	Jun 09 02:25:11 PM PDT 24
Finished	Jun 09 02:25:59 PM PDT 24
Peak memory	248736 kb
Host	smart-a640f29a-09f4-4345-9dbd-d1744e0bbb75
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180966664 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_stress_all.2180966664
Directory	/workspace/12.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/12.lc_ctrl_volatile_unlock_smoke.2919061592
Short name	T506
Test name
Test status
Simulation time	13666049 ps
CPU time	0.75 seconds
Started	Jun 09 02:25:01 PM PDT 24
Finished	Jun 09 02:25:02 PM PDT 24
Peak memory	208612 kb
Host	smart-6debd215-b7fd-41c8-8ddb-93a4c17efbe5
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919061592 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_c trl_volatile_unlock_smoke.2919061592
Directory	/workspace/12.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/13.lc_ctrl_alert_test.1240487913
Short name	T377
Test name
Test status
Simulation time	34094645 ps
CPU time	0.83 seconds
Started	Jun 09 02:24:59 PM PDT 24
Finished	Jun 09 02:25:00 PM PDT 24
Peak memory	209448 kb
Host	smart-cada76ab-2774-412d-93b1-fea566977816
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240487913 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_alert_test.1240487913
Directory	/workspace/13.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/13.lc_ctrl_errors.2524077866
Short name	T26
Test name
Test status
Simulation time	1452558088 ps
CPU time	15.9 seconds
Started	Jun 09 02:25:05 PM PDT 24
Finished	Jun 09 02:25:21 PM PDT 24
Peak memory	218704 kb
Host	smart-5ca710f5-39fc-46f5-9d64-3d1a3689e62d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2524077866 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_errors.2524077866
Directory	/workspace/13.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/13.lc_ctrl_jtag_access.4201030149
Short name	T19
Test name
Test status
Simulation time	326157924 ps
CPU time	1.68 seconds
Started	Jun 09 02:24:52 PM PDT 24
Finished	Jun 09 02:24:54 PM PDT 24
Peak memory	217580 kb
Host	smart-f92abe1e-81ea-4dd9-b0c5-ba9e3aabc0b2
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201030149 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_access.4201030149
Directory	/workspace/13.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/13.lc_ctrl_jtag_errors.2433787405
Short name	T248
Test name
Test status
Simulation time	1546354640 ps
CPU time	25.47 seconds
Started	Jun 09 02:24:53 PM PDT 24
Finished	Jun 09 02:25:19 PM PDT 24
Peak memory	218720 kb
Host	smart-d10eb344-a0f3-42d0-ad56-6bf7090d15dd
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433787405 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_e rrors.2433787405
Directory	/workspace/13.lc_ctrl_jtag_errors/latest

Test location	/workspace/coverage/default/13.lc_ctrl_jtag_prog_failure.898199677
Short name	T301
Test name
Test status
Simulation time	3219399093 ps
CPU time	20.45 seconds
Started	Jun 09 02:25:28 PM PDT 24
Finished	Jun 09 02:25:49 PM PDT 24
Peak memory	226240 kb
Host	smart-f26339df-4745-4f0d-bb42-6a11eaf31c1d
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898199677 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag _prog_failure.898199677
Directory	/workspace/13.lc_ctrl_jtag_prog_failure/latest

Test location	/workspace/coverage/default/13.lc_ctrl_jtag_smoke.1275408687
Short name	T457
Test name
Test status
Simulation time	442126908 ps
CPU time	2.28 seconds
Started	Jun 09 02:25:05 PM PDT 24
Finished	Jun 09 02:25:08 PM PDT 24
Peak memory	218200 kb
Host	smart-3252d21d-3d63-447d-bea1-127261193d32
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275408687 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_smoke .1275408687
Directory	/workspace/13.lc_ctrl_jtag_smoke/latest

Test location	/workspace/coverage/default/13.lc_ctrl_jtag_state_failure.3240587256
Short name	T551
Test name
Test status
Simulation time	2996142233 ps
CPU time	33.81 seconds
Started	Jun 09 02:24:52 PM PDT 24
Finished	Jun 09 02:25:26 PM PDT 24
Peak memory	251524 kb
Host	smart-394a44f3-07dc-4c64-b122-adcd3acb7ae9
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240587256 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jt ag_state_failure.3240587256
Directory	/workspace/13.lc_ctrl_jtag_state_failure/latest

Test location	/workspace/coverage/default/13.lc_ctrl_jtag_state_post_trans.115845399
Short name	T173
Test name
Test status
Simulation time	2374110605 ps
CPU time	14.6 seconds
Started	Jun 09 02:25:10 PM PDT 24
Finished	Jun 09 02:25:25 PM PDT 24
Peak memory	251292 kb
Host	smart-0d84a43a-3a0e-4724-b798-bf34690b2d78
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115845399 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_ jtag_state_post_trans.115845399
Directory	/workspace/13.lc_ctrl_jtag_state_post_trans/latest

Test location	/workspace/coverage/default/13.lc_ctrl_prog_failure.3929701285
Short name	T622
Test name
Test status
Simulation time	86750909 ps
CPU time	1.96 seconds
Started	Jun 09 02:24:59 PM PDT 24
Finished	Jun 09 02:25:01 PM PDT 24
Peak memory	218868 kb
Host	smart-abc167cb-c081-4ca4-a0d4-7a4ef678bcc4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3929701285 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_prog_failure.3929701285
Directory	/workspace/13.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/13.lc_ctrl_sec_mubi.3457635435
Short name	T67
Test name
Test status
Simulation time	377083932 ps
CPU time	15.45 seconds
Started	Jun 09 02:25:03 PM PDT 24
Finished	Jun 09 02:25:19 PM PDT 24
Peak memory	219376 kb
Host	smart-ac4d92a2-c3db-4435-a88f-5ff9e8f80dd5
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457635435 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_mubi.3457635435
Directory	/workspace/13.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/13.lc_ctrl_sec_token_digest.1381235237
Short name	T531
Test name
Test status
Simulation time	250660580 ps
CPU time	8.42 seconds
Started	Jun 09 02:25:01 PM PDT 24
Finished	Jun 09 02:25:09 PM PDT 24
Peak memory	218740 kb
Host	smart-f4f55c6b-fd1b-4134-b1ff-ff8e3bbb2c68
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381235237 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_d igest.1381235237
Directory	/workspace/13.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/13.lc_ctrl_sec_token_mux.417153934
Short name	T266
Test name
Test status
Simulation time	480748190 ps
CPU time	7.36 seconds
Started	Jun 09 02:25:01 PM PDT 24
Finished	Jun 09 02:25:09 PM PDT 24
Peak memory	225500 kb
Host	smart-7936ae83-ab40-48a8-9ded-6c04eecc7622
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417153934 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_mux.417153934
Directory	/workspace/13.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/13.lc_ctrl_security_escalation.3624018523
Short name	T403
Test name
Test status
Simulation time	497825170 ps
CPU time	8.09 seconds
Started	Jun 09 02:25:03 PM PDT 24
Finished	Jun 09 02:25:11 PM PDT 24
Peak memory	218792 kb
Host	smart-50e0bc98-bfd8-42e0-87f3-f280a2094540
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3624018523 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_security_escalation.3624018523
Directory	/workspace/13.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/13.lc_ctrl_smoke.3733948150
Short name	T44
Test name
Test status
Simulation time	87960792 ps
CPU time	2.13 seconds
Started	Jun 09 02:25:03 PM PDT 24
Finished	Jun 09 02:25:06 PM PDT 24
Peak memory	214656 kb
Host	smart-48774a04-21ad-4957-81b4-0aaa4796b9e0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3733948150 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_smoke.3733948150
Directory	/workspace/13.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/13.lc_ctrl_state_failure.1297295189
Short name	T567
Test name
Test status
Simulation time	1357885400 ps
CPU time	35.87 seconds
Started	Jun 09 02:24:51 PM PDT 24
Finished	Jun 09 02:25:27 PM PDT 24
Peak memory	251424 kb
Host	smart-4d5a94a9-6dab-4858-94c8-94afb912a051
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1297295189 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_failure.1297295189
Directory	/workspace/13.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/13.lc_ctrl_state_post_trans.596300014
Short name	T760
Test name
Test status
Simulation time	249731531 ps
CPU time	2.95 seconds
Started	Jun 09 02:25:08 PM PDT 24
Finished	Jun 09 02:25:12 PM PDT 24
Peak memory	224576 kb
Host	smart-40aaf7d1-2336-4a18-bb00-5d09127f2d31
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=596300014 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_post_trans.596300014
Directory	/workspace/13.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/13.lc_ctrl_stress_all.1169789039
Short name	T201
Test name
Test status
Simulation time	2415978085 ps
CPU time	97.72 seconds
Started	Jun 09 02:24:57 PM PDT 24
Finished	Jun 09 02:26:35 PM PDT 24
Peak memory	269012 kb
Host	smart-930b5c28-cf61-4b44-b8da-b40179039fe2
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169789039 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_stress_all.1169789039
Directory	/workspace/13.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/13.lc_ctrl_stress_all_with_rand_reset.3146942846
Short name	T149
Test name
Test status
Simulation time	98877262388 ps
CPU time	839.21 seconds
Started	Jun 09 02:24:55 PM PDT 24
Finished	Jun 09 02:38:55 PM PDT 24
Peak memory	422584 kb
Host	smart-2ff422bf-4bb4-48cf-b721-d3693d0b15a6
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=3146942846 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_stress_all_with_rand_reset.3146942846
Directory	/workspace/13.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/13.lc_ctrl_volatile_unlock_smoke.1925874011
Short name	T454
Test name
Test status
Simulation time	131963908 ps
CPU time	1.01 seconds
Started	Jun 09 02:24:50 PM PDT 24
Finished	Jun 09 02:24:51 PM PDT 24
Peak memory	212356 kb
Host	smart-2098d35b-9127-4d47-b90d-80ae5c69b4b5
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925874011 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_c trl_volatile_unlock_smoke.1925874011
Directory	/workspace/13.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/14.lc_ctrl_alert_test.1379868793
Short name	T528
Test name
Test status
Simulation time	38615218 ps
CPU time	1.2 seconds
Started	Jun 09 02:25:11 PM PDT 24
Finished	Jun 09 02:25:12 PM PDT 24
Peak memory	209392 kb
Host	smart-35bbd630-aea0-4c84-9e85-4e927b767dca
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379868793 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_alert_test.1379868793
Directory	/workspace/14.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/14.lc_ctrl_errors.2197597942
Short name	T847
Test name
Test status
Simulation time	498257310 ps
CPU time	14.4 seconds
Started	Jun 09 02:24:55 PM PDT 24
Finished	Jun 09 02:25:09 PM PDT 24
Peak memory	218688 kb
Host	smart-742803ac-5b2c-42dc-9bdf-46e7f94b7ad8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2197597942 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_errors.2197597942
Directory	/workspace/14.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/14.lc_ctrl_jtag_access.4106382589
Short name	T827
Test name
Test status
Simulation time	3799570544 ps
CPU time	22.34 seconds
Started	Jun 09 02:25:07 PM PDT 24
Finished	Jun 09 02:25:29 PM PDT 24
Peak memory	218256 kb
Host	smart-5c469b78-1264-4141-83bc-4405513f16ce
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106382589 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_access.4106382589
Directory	/workspace/14.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/14.lc_ctrl_jtag_errors.2274239474
Short name	T764
Test name
Test status
Simulation time	8353538998 ps
CPU time	32.83 seconds
Started	Jun 09 02:25:01 PM PDT 24
Finished	Jun 09 02:25:35 PM PDT 24
Peak memory	219452 kb
Host	smart-ba70c965-6e15-4609-bc5d-4af239d17673
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274239474 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_e rrors.2274239474
Directory	/workspace/14.lc_ctrl_jtag_errors/latest

Test location	/workspace/coverage/default/14.lc_ctrl_jtag_prog_failure.2502631628
Short name	T356
Test name
Test status
Simulation time	1762572828 ps
CPU time	9.72 seconds
Started	Jun 09 02:25:10 PM PDT 24
Finished	Jun 09 02:25:20 PM PDT 24
Peak memory	218708 kb
Host	smart-5a955741-5094-4504-9946-3ba7c34ae4b9
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502631628 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jta g_prog_failure.2502631628
Directory	/workspace/14.lc_ctrl_jtag_prog_failure/latest

Test location	/workspace/coverage/default/14.lc_ctrl_jtag_smoke.2906993790
Short name	T72
Test name
Test status
Simulation time	3563894252 ps
CPU time	3.71 seconds
Started	Jun 09 02:25:04 PM PDT 24
Finished	Jun 09 02:25:08 PM PDT 24
Peak memory	218272 kb
Host	smart-89c048be-6cf4-47ef-b845-d33055be620c
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906993790 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_smoke .2906993790
Directory	/workspace/14.lc_ctrl_jtag_smoke/latest

Test location	/workspace/coverage/default/14.lc_ctrl_jtag_state_failure.3807772458
Short name	T515
Test name
Test status
Simulation time	11969029884 ps
CPU time	60.04 seconds
Started	Jun 09 02:24:56 PM PDT 24
Finished	Jun 09 02:25:56 PM PDT 24
Peak memory	251444 kb
Host	smart-1d132813-e8ff-4af9-b3a5-0bfd0596eda5
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807772458 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jt ag_state_failure.3807772458
Directory	/workspace/14.lc_ctrl_jtag_state_failure/latest

Test location	/workspace/coverage/default/14.lc_ctrl_jtag_state_post_trans.1380624651
Short name	T587
Test name
Test status
Simulation time	2000048716 ps
CPU time	17.88 seconds
Started	Jun 09 02:25:02 PM PDT 24
Finished	Jun 09 02:25:20 PM PDT 24
Peak memory	251372 kb
Host	smart-feb92ac1-b540-47e5-a795-fa802215bbf0
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380624651 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl _jtag_state_post_trans.1380624651
Directory	/workspace/14.lc_ctrl_jtag_state_post_trans/latest

Test location	/workspace/coverage/default/14.lc_ctrl_prog_failure.3702151899
Short name	T236
Test name
Test status
Simulation time	56924400 ps
CPU time	3.38 seconds
Started	Jun 09 02:25:10 PM PDT 24
Finished	Jun 09 02:25:14 PM PDT 24
Peak memory	218676 kb
Host	smart-30138e3f-b901-4d1e-b949-cf6508de1fc5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3702151899 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_prog_failure.3702151899
Directory	/workspace/14.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/14.lc_ctrl_sec_mubi.3356016261
Short name	T817
Test name
Test status
Simulation time	247473438 ps
CPU time	11.51 seconds
Started	Jun 09 02:25:03 PM PDT 24
Finished	Jun 09 02:25:15 PM PDT 24
Peak memory	218724 kb
Host	smart-05476a94-6e41-4b9a-b00e-1e16891f76db
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356016261 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_mubi.3356016261
Directory	/workspace/14.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/14.lc_ctrl_sec_token_digest.2661724564
Short name	T229
Test name
Test status
Simulation time	3642740520 ps
CPU time	22.8 seconds
Started	Jun 09 02:25:06 PM PDT 24
Finished	Jun 09 02:25:29 PM PDT 24
Peak memory	226608 kb
Host	smart-413983af-80f6-4222-9051-b5b5a6816c69
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661724564 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_d igest.2661724564
Directory	/workspace/14.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/14.lc_ctrl_sec_token_mux.4217736790
Short name	T542
Test name
Test status
Simulation time	308688302 ps
CPU time	11.57 seconds
Started	Jun 09 02:25:09 PM PDT 24
Finished	Jun 09 02:25:21 PM PDT 24
Peak memory	218724 kb
Host	smart-6de4bad4-d696-4720-af68-0f7d07a4f044
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217736790 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_mux. 4217736790
Directory	/workspace/14.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/14.lc_ctrl_security_escalation.89384255
Short name	T588
Test name
Test status
Simulation time	719584229 ps
CPU time	9.83 seconds
Started	Jun 09 02:25:05 PM PDT 24
Finished	Jun 09 02:25:15 PM PDT 24
Peak memory	226544 kb
Host	smart-b09bbdd3-7dff-4541-a1d5-b03c027ce80f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=89384255 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_security_escalation.89384255
Directory	/workspace/14.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/14.lc_ctrl_smoke.4216425358
Short name	T281
Test name
Test status
Simulation time	106554463 ps
CPU time	3.49 seconds
Started	Jun 09 02:25:06 PM PDT 24
Finished	Jun 09 02:25:10 PM PDT 24
Peak memory	215568 kb
Host	smart-df525341-01da-4165-98e8-6d90f4dd0942
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4216425358 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_smoke.4216425358
Directory	/workspace/14.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/14.lc_ctrl_state_failure.3839192194
Short name	T51
Test name
Test status
Simulation time	275950113 ps
CPU time	35.47 seconds
Started	Jun 09 02:25:06 PM PDT 24
Finished	Jun 09 02:25:42 PM PDT 24
Peak memory	251420 kb
Host	smart-38985f12-1469-497e-8069-b4e33de16a63
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3839192194 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_failure.3839192194
Directory	/workspace/14.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/14.lc_ctrl_state_post_trans.3319492515
Short name	T845
Test name
Test status
Simulation time	89572745 ps
CPU time	6.6 seconds
Started	Jun 09 02:25:05 PM PDT 24
Finished	Jun 09 02:25:11 PM PDT 24
Peak memory	250844 kb
Host	smart-5696dc9f-597f-4b08-a1a6-47279b9283fa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3319492515 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_post_trans.3319492515
Directory	/workspace/14.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/14.lc_ctrl_stress_all.3254084966
Short name	T731
Test name
Test status
Simulation time	15538480738 ps
CPU time	53.67 seconds
Started	Jun 09 02:25:17 PM PDT 24
Finished	Jun 09 02:26:11 PM PDT 24
Peak memory	251420 kb
Host	smart-597dc46a-39b3-47af-820f-f0a69824ebe3
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254084966 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_stress_all.3254084966
Directory	/workspace/14.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/14.lc_ctrl_volatile_unlock_smoke.3663307231
Short name	T78
Test name
Test status
Simulation time	14095288 ps
CPU time	0.91 seconds
Started	Jun 09 02:25:10 PM PDT 24
Finished	Jun 09 02:25:11 PM PDT 24
Peak memory	212332 kb
Host	smart-7c13e33f-08b5-49c3-929a-5309ff64826a
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663307231 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_c trl_volatile_unlock_smoke.3663307231
Directory	/workspace/14.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/15.lc_ctrl_errors.3479841699
Short name	T537
Test name
Test status
Simulation time	1259964790 ps
CPU time	13.75 seconds
Started	Jun 09 02:25:06 PM PDT 24
Finished	Jun 09 02:25:20 PM PDT 24
Peak memory	218704 kb
Host	smart-a8b34453-8880-42cf-a440-c8cef9d9c012
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3479841699 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_errors.3479841699
Directory	/workspace/15.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/15.lc_ctrl_jtag_access.1776451345
Short name	T480
Test name
Test status
Simulation time	760369533 ps
CPU time	10.4 seconds
Started	Jun 09 02:25:16 PM PDT 24
Finished	Jun 09 02:25:27 PM PDT 24
Peak memory	217792 kb
Host	smart-5e9f174a-5e4a-4e32-a6b7-6e6b693f0987
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776451345 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_access.1776451345
Directory	/workspace/15.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/15.lc_ctrl_jtag_errors.3603779939
Short name	T355
Test name
Test status
Simulation time	12468327778 ps
CPU time	40.93 seconds
Started	Jun 09 02:25:20 PM PDT 24
Finished	Jun 09 02:26:01 PM PDT 24
Peak memory	226592 kb
Host	smart-0db35e71-946d-4867-a787-b5e549492283
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603779939 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_e rrors.3603779939
Directory	/workspace/15.lc_ctrl_jtag_errors/latest

Test location	/workspace/coverage/default/15.lc_ctrl_jtag_prog_failure.1522654145
Short name	T508
Test name
Test status
Simulation time	1446888349 ps
CPU time	10.58 seconds
Started	Jun 09 02:25:06 PM PDT 24
Finished	Jun 09 02:25:17 PM PDT 24
Peak memory	218708 kb
Host	smart-b1ae9368-bacb-4122-a8f7-41091a013c77
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522654145 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jta g_prog_failure.1522654145
Directory	/workspace/15.lc_ctrl_jtag_prog_failure/latest

Test location	/workspace/coverage/default/15.lc_ctrl_jtag_smoke.4285084082
Short name	T425
Test name
Test status
Simulation time	1230648477 ps
CPU time	5.17 seconds
Started	Jun 09 02:25:10 PM PDT 24
Finished	Jun 09 02:25:16 PM PDT 24
Peak memory	218196 kb
Host	smart-59d36c25-bb3a-4d9c-aaa8-84bc16df7ce8
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285084082 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_smoke .4285084082
Directory	/workspace/15.lc_ctrl_jtag_smoke/latest

Test location	/workspace/coverage/default/15.lc_ctrl_jtag_state_failure.2050578100
Short name	T831
Test name
Test status
Simulation time	4797250065 ps
CPU time	84.02 seconds
Started	Jun 09 02:25:15 PM PDT 24
Finished	Jun 09 02:26:39 PM PDT 24
Peak memory	284196 kb
Host	smart-01de3875-cedf-427d-acca-48b8f74dbead
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050578100 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jt ag_state_failure.2050578100
Directory	/workspace/15.lc_ctrl_jtag_state_failure/latest

Test location	/workspace/coverage/default/15.lc_ctrl_jtag_state_post_trans.3321328011
Short name	T610
Test name
Test status
Simulation time	582708058 ps
CPU time	24.05 seconds
Started	Jun 09 02:25:08 PM PDT 24
Finished	Jun 09 02:25:32 PM PDT 24
Peak memory	251420 kb
Host	smart-92317bf4-3db3-46be-b157-354588d9f372
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321328011 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl _jtag_state_post_trans.3321328011
Directory	/workspace/15.lc_ctrl_jtag_state_post_trans/latest

Test location	/workspace/coverage/default/15.lc_ctrl_prog_failure.1997271431
Short name	T250
Test name
Test status
Simulation time	21463944 ps
CPU time	1.76 seconds
Started	Jun 09 02:25:10 PM PDT 24
Finished	Jun 09 02:25:12 PM PDT 24
Peak memory	222612 kb
Host	smart-291ddb1c-5d10-48aa-a539-f3f41e415697
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1997271431 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_prog_failure.1997271431
Directory	/workspace/15.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/15.lc_ctrl_sec_mubi.2996121120
Short name	T449
Test name
Test status
Simulation time	1780273796 ps
CPU time	15.28 seconds
Started	Jun 09 02:25:13 PM PDT 24
Finished	Jun 09 02:25:29 PM PDT 24
Peak memory	219376 kb
Host	smart-aff9312a-6a1f-4948-acd5-1e9efa82aa59
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996121120 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_mubi.2996121120
Directory	/workspace/15.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/15.lc_ctrl_sec_token_digest.1773201235
Short name	T748
Test name
Test status
Simulation time	1974998849 ps
CPU time	11.94 seconds
Started	Jun 09 02:25:12 PM PDT 24
Finished	Jun 09 02:25:24 PM PDT 24
Peak memory	218720 kb
Host	smart-ea1a19eb-a755-4986-b1d3-7a74c48bfa59
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773201235 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_d igest.1773201235
Directory	/workspace/15.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/15.lc_ctrl_sec_token_mux.2290536712
Short name	T538
Test name
Test status
Simulation time	1422658498 ps
CPU time	12.14 seconds
Started	Jun 09 02:25:23 PM PDT 24
Finished	Jun 09 02:25:36 PM PDT 24
Peak memory	218708 kb
Host	smart-b723dfc1-aeab-44e3-827c-7ddb94b038ec
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290536712 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_mux. 2290536712
Directory	/workspace/15.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/15.lc_ctrl_security_escalation.3883565692
Short name	T41
Test name
Test status
Simulation time	1208645911 ps
CPU time	10.69 seconds
Started	Jun 09 02:25:05 PM PDT 24
Finished	Jun 09 02:25:16 PM PDT 24
Peak memory	226508 kb
Host	smart-6c267ef9-0523-405b-9eef-96b271a69136
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3883565692 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_security_escalation.3883565692
Directory	/workspace/15.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/15.lc_ctrl_smoke.2056692072
Short name	T833
Test name
Test status
Simulation time	96051617 ps
CPU time	3.23 seconds
Started	Jun 09 02:25:05 PM PDT 24
Finished	Jun 09 02:25:08 PM PDT 24
Peak memory	218176 kb
Host	smart-8a34d6ee-0b55-47cd-ad40-bb76531f7d59
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2056692072 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_smoke.2056692072
Directory	/workspace/15.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/15.lc_ctrl_state_failure.2367169787
Short name	T60
Test name
Test status
Simulation time	1500958862 ps
CPU time	20.53 seconds
Started	Jun 09 02:25:15 PM PDT 24
Finished	Jun 09 02:25:36 PM PDT 24
Peak memory	251416 kb
Host	smart-3abf8d25-02bd-4141-882d-24e823d447a1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2367169787 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_failure.2367169787
Directory	/workspace/15.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/15.lc_ctrl_state_post_trans.2644027274
Short name	T611
Test name
Test status
Simulation time	79666668 ps
CPU time	6.79 seconds
Started	Jun 09 02:25:09 PM PDT 24
Finished	Jun 09 02:25:16 PM PDT 24
Peak memory	249004 kb
Host	smart-e298350a-6d24-42d4-b3d6-46fd7c425422
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2644027274 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_post_trans.2644027274
Directory	/workspace/15.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/15.lc_ctrl_volatile_unlock_smoke.832370933
Short name	T344
Test name
Test status
Simulation time	50677505 ps
CPU time	0.94 seconds
Started	Jun 09 02:25:00 PM PDT 24
Finished	Jun 09 02:25:01 PM PDT 24
Peak memory	212420 kb
Host	smart-a35ccf6c-b5e5-4d8c-a117-93205b9f9e3b
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832370933 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ct rl_volatile_unlock_smoke.832370933
Directory	/workspace/15.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/16.lc_ctrl_alert_test.3302170635
Short name	T432
Test name
Test status
Simulation time	23791477 ps
CPU time	1.24 seconds
Started	Jun 09 02:25:17 PM PDT 24
Finished	Jun 09 02:25:19 PM PDT 24
Peak memory	209576 kb
Host	smart-98eb95d7-5bd8-4f34-a4d6-a8d215d75dd9
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302170635 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_alert_test.3302170635
Directory	/workspace/16.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/16.lc_ctrl_errors.1870186189
Short name	T767
Test name
Test status
Simulation time	2190489301 ps
CPU time	13.17 seconds
Started	Jun 09 02:25:07 PM PDT 24
Finished	Jun 09 02:25:20 PM PDT 24
Peak memory	218700 kb
Host	smart-9bea793d-e94e-40f2-be27-ac09f3dc8846
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1870186189 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_errors.1870186189
Directory	/workspace/16.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/16.lc_ctrl_jtag_errors.426995261
Short name	T795
Test name
Test status
Simulation time	5836070746 ps
CPU time	75.77 seconds
Started	Jun 09 02:25:12 PM PDT 24
Finished	Jun 09 02:26:28 PM PDT 24
Peak memory	226584 kb
Host	smart-315b4a76-95fc-4632-ac1c-d6e78c95126a
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426995261 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_er rors.426995261
Directory	/workspace/16.lc_ctrl_jtag_errors/latest

Test location	/workspace/coverage/default/16.lc_ctrl_jtag_prog_failure.3178317540
Short name	T496
Test name
Test status
Simulation time	1309887502 ps
CPU time	13.14 seconds
Started	Jun 09 02:25:29 PM PDT 24
Finished	Jun 09 02:25:43 PM PDT 24
Peak memory	218688 kb
Host	smart-4f61a6fb-e43d-497b-9d65-82e9625580d5
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178317540 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jta g_prog_failure.3178317540
Directory	/workspace/16.lc_ctrl_jtag_prog_failure/latest

Test location	/workspace/coverage/default/16.lc_ctrl_jtag_smoke.1996130309
Short name	T259
Test name
Test status
Simulation time	167484586 ps
CPU time	1.67 seconds
Started	Jun 09 02:25:17 PM PDT 24
Finished	Jun 09 02:25:19 PM PDT 24
Peak memory	218196 kb
Host	smart-f7c12937-04ff-4073-9667-d66e334d5f0e
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996130309 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_smoke .1996130309
Directory	/workspace/16.lc_ctrl_jtag_smoke/latest

Test location	/workspace/coverage/default/16.lc_ctrl_jtag_state_failure.2237405984
Short name	T279
Test name
Test status
Simulation time	6778113151 ps
CPU time	43.4 seconds
Started	Jun 09 02:25:19 PM PDT 24
Finished	Jun 09 02:26:03 PM PDT 24
Peak memory	267884 kb
Host	smart-4b306813-22a8-486b-925b-18e59008d286
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237405984 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jt ag_state_failure.2237405984
Directory	/workspace/16.lc_ctrl_jtag_state_failure/latest

Test location	/workspace/coverage/default/16.lc_ctrl_jtag_state_post_trans.2239773069
Short name	T385
Test name
Test status
Simulation time	1848886260 ps
CPU time	15.82 seconds
Started	Jun 09 02:25:29 PM PDT 24
Finished	Jun 09 02:25:45 PM PDT 24
Peak memory	251420 kb
Host	smart-bae7e6fc-9ee1-434a-89aa-b667f5276247
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239773069 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl _jtag_state_post_trans.2239773069
Directory	/workspace/16.lc_ctrl_jtag_state_post_trans/latest

Test location	/workspace/coverage/default/16.lc_ctrl_prog_failure.1988068180
Short name	T369
Test name
Test status
Simulation time	50589067 ps
CPU time	2.86 seconds
Started	Jun 09 02:25:18 PM PDT 24
Finished	Jun 09 02:25:21 PM PDT 24
Peak memory	218660 kb
Host	smart-e3959d03-fb92-43bb-b78f-b2f76f311d0a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1988068180 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_prog_failure.1988068180
Directory	/workspace/16.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/16.lc_ctrl_sec_mubi.482512202
Short name	T277
Test name
Test status
Simulation time	715059988 ps
CPU time	11.94 seconds
Started	Jun 09 02:25:18 PM PDT 24
Finished	Jun 09 02:25:30 PM PDT 24
Peak memory	218780 kb
Host	smart-780a132d-053f-49d4-aed6-d03277b9e176
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482512202 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_mubi.482512202
Directory	/workspace/16.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/16.lc_ctrl_sec_token_digest.864907447
Short name	T246
Test name
Test status
Simulation time	375929903 ps
CPU time	15.24 seconds
Started	Jun 09 02:25:08 PM PDT 24
Finished	Jun 09 02:25:24 PM PDT 24
Peak memory	226540 kb
Host	smart-0609efde-e24e-4eb2-9333-5600572bbaa3
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864907447 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_di gest.864907447
Directory	/workspace/16.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/16.lc_ctrl_sec_token_mux.284112875
Short name	T578
Test name
Test status
Simulation time	1530710993 ps
CPU time	6.88 seconds
Started	Jun 09 02:25:14 PM PDT 24
Finished	Jun 09 02:25:21 PM PDT 24
Peak memory	218760 kb
Host	smart-cb2ccf5b-9dda-402b-a3c7-1b9fcb0043d4
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284112875 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_mux.284112875
Directory	/workspace/16.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/16.lc_ctrl_security_escalation.1116024162
Short name	T210
Test name
Test status
Simulation time	1114760383 ps
CPU time	8.37 seconds
Started	Jun 09 02:25:29 PM PDT 24
Finished	Jun 09 02:25:38 PM PDT 24
Peak memory	225720 kb
Host	smart-0e5a89d5-9d79-4f2e-8006-a42003f3687b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1116024162 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_security_escalation.1116024162
Directory	/workspace/16.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/16.lc_ctrl_smoke.2228678214
Short name	T654
Test name
Test status
Simulation time	81154526 ps
CPU time	2.72 seconds
Started	Jun 09 02:25:09 PM PDT 24
Finished	Jun 09 02:25:12 PM PDT 24
Peak memory	218200 kb
Host	smart-8a6f3e96-b33e-4b39-ad73-b8567e2c395e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2228678214 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_smoke.2228678214
Directory	/workspace/16.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/16.lc_ctrl_state_failure.3069120040
Short name	T662
Test name
Test status
Simulation time	809569270 ps
CPU time	13.69 seconds
Started	Jun 09 02:25:15 PM PDT 24
Finished	Jun 09 02:25:29 PM PDT 24
Peak memory	251476 kb
Host	smart-08477416-0aba-4558-b1c4-a421c5a9f486
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3069120040 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_failure.3069120040
Directory	/workspace/16.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/16.lc_ctrl_state_post_trans.835989425
Short name	T43
Test name
Test status
Simulation time	217827205 ps
CPU time	3.06 seconds
Started	Jun 09 02:25:11 PM PDT 24
Finished	Jun 09 02:25:15 PM PDT 24
Peak memory	223176 kb
Host	smart-68aa6901-d357-40ee-ae1b-ae90981e0de5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=835989425 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_post_trans.835989425
Directory	/workspace/16.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/16.lc_ctrl_stress_all.1401798109
Short name	T395
Test name
Test status
Simulation time	46581105050 ps
CPU time	166.19 seconds
Started	Jun 09 02:25:13 PM PDT 24
Finished	Jun 09 02:28:00 PM PDT 24
Peak memory	250692 kb
Host	smart-5d4b88f7-c5bf-4431-8225-f6864fd6aa6c
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401798109 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_stress_all.1401798109
Directory	/workspace/16.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/16.lc_ctrl_stress_all_with_rand_reset.3553041895
Short name	T57
Test name
Test status
Simulation time	76992112831 ps
CPU time	355.9 seconds
Started	Jun 09 02:25:14 PM PDT 24
Finished	Jun 09 02:31:10 PM PDT 24
Peak memory	513724 kb
Host	smart-f88bb715-7c05-4dcf-9175-fd5d28ed9c28
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=3553041895 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_stress_all_with_rand_reset.3553041895
Directory	/workspace/16.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/16.lc_ctrl_volatile_unlock_smoke.2694532485
Short name	T339
Test name
Test status
Simulation time	167133009 ps
CPU time	0.88 seconds
Started	Jun 09 02:25:12 PM PDT 24
Finished	Jun 09 02:25:13 PM PDT 24
Peak memory	209588 kb
Host	smart-c328273e-1cc9-493a-8188-14f80036d492
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694532485 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_c trl_volatile_unlock_smoke.2694532485
Directory	/workspace/16.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/17.lc_ctrl_alert_test.4111070315
Short name	T375
Test name
Test status
Simulation time	26434743 ps
CPU time	1.32 seconds
Started	Jun 09 02:25:17 PM PDT 24
Finished	Jun 09 02:25:19 PM PDT 24
Peak memory	209460 kb
Host	smart-d1a7e274-e0ce-4f41-b362-3fcf9cc13afa
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111070315 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_alert_test.4111070315
Directory	/workspace/17.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/17.lc_ctrl_errors.1225268749
Short name	T564
Test name
Test status
Simulation time	1072410679 ps
CPU time	16.88 seconds
Started	Jun 09 02:25:20 PM PDT 24
Finished	Jun 09 02:25:37 PM PDT 24
Peak memory	218980 kb
Host	smart-1ad9565d-7e3c-4755-9eff-a9f99370e730
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1225268749 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_errors.1225268749
Directory	/workspace/17.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/17.lc_ctrl_jtag_access.1897130024
Short name	T31
Test name
Test status
Simulation time	226391334 ps
CPU time	3.34 seconds
Started	Jun 09 02:25:16 PM PDT 24
Finished	Jun 09 02:25:19 PM PDT 24
Peak memory	217628 kb
Host	smart-3e03a0eb-1c48-4557-a5cf-0c740b1f295d
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897130024 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_access.1897130024
Directory	/workspace/17.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/17.lc_ctrl_jtag_errors.2475748104
Short name	T380
Test name
Test status
Simulation time	27508351267 ps
CPU time	43.44 seconds
Started	Jun 09 02:25:13 PM PDT 24
Finished	Jun 09 02:25:57 PM PDT 24
Peak memory	219200 kb
Host	smart-02811ec1-70bd-464c-958c-871b5b64239c
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475748104 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_e rrors.2475748104
Directory	/workspace/17.lc_ctrl_jtag_errors/latest

Test location	/workspace/coverage/default/17.lc_ctrl_jtag_prog_failure.3366480465
Short name	T647
Test name
Test status
Simulation time	251187252 ps
CPU time	1.99 seconds
Started	Jun 09 02:25:17 PM PDT 24
Finished	Jun 09 02:25:19 PM PDT 24
Peak memory	218680 kb
Host	smart-7cdec3b9-8ad5-4dbc-9662-1693bd0a12b8
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366480465 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jta g_prog_failure.3366480465
Directory	/workspace/17.lc_ctrl_jtag_prog_failure/latest

Test location	/workspace/coverage/default/17.lc_ctrl_jtag_smoke.347703430
Short name	T292
Test name
Test status
Simulation time	711969775 ps
CPU time	2.12 seconds
Started	Jun 09 02:25:11 PM PDT 24
Finished	Jun 09 02:25:13 PM PDT 24
Peak memory	218212 kb
Host	smart-040afaee-a5d2-446a-a70f-b51dbcdc2f86
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347703430 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_smoke. 347703430
Directory	/workspace/17.lc_ctrl_jtag_smoke/latest

Test location	/workspace/coverage/default/17.lc_ctrl_jtag_state_failure.3487030951
Short name	T532
Test name
Test status
Simulation time	2602849319 ps
CPU time	53.91 seconds
Started	Jun 09 02:25:16 PM PDT 24
Finished	Jun 09 02:26:10 PM PDT 24
Peak memory	268120 kb
Host	smart-a58909cd-f17d-4c7d-8b75-7860a075d557
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487030951 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jt ag_state_failure.3487030951
Directory	/workspace/17.lc_ctrl_jtag_state_failure/latest

Test location	/workspace/coverage/default/17.lc_ctrl_jtag_state_post_trans.4123163727
Short name	T263
Test name
Test status
Simulation time	1834433544 ps
CPU time	13.88 seconds
Started	Jun 09 02:25:15 PM PDT 24
Finished	Jun 09 02:25:29 PM PDT 24
Peak memory	251248 kb
Host	smart-34915c7f-07ca-4fb5-8178-9516bf99e47c
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123163727 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl _jtag_state_post_trans.4123163727
Directory	/workspace/17.lc_ctrl_jtag_state_post_trans/latest

Test location	/workspace/coverage/default/17.lc_ctrl_prog_failure.1675676720
Short name	T800
Test name
Test status
Simulation time	208259093 ps
CPU time	3.03 seconds
Started	Jun 09 02:25:24 PM PDT 24
Finished	Jun 09 02:25:27 PM PDT 24
Peak memory	222784 kb
Host	smart-47a7fbab-fe6e-4a1a-b508-8b0157a759dd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1675676720 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_prog_failure.1675676720
Directory	/workspace/17.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/17.lc_ctrl_sec_token_digest.3643968352
Short name	T484
Test name
Test status
Simulation time	223597014 ps
CPU time	8.45 seconds
Started	Jun 09 02:25:14 PM PDT 24
Finished	Jun 09 02:25:23 PM PDT 24
Peak memory	218728 kb
Host	smart-77d97faf-27fb-4b76-b733-8f2fe7d073b9
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643968352 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_d igest.3643968352
Directory	/workspace/17.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/17.lc_ctrl_sec_token_mux.2328556749
Short name	T592
Test name
Test status
Simulation time	1753562618 ps
CPU time	13.28 seconds
Started	Jun 09 02:25:26 PM PDT 24
Finished	Jun 09 02:25:40 PM PDT 24
Peak memory	218720 kb
Host	smart-2a2a7b57-6a02-4802-a5b4-783b96816d1c
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328556749 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_mux. 2328556749
Directory	/workspace/17.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/17.lc_ctrl_security_escalation.829600052
Short name	T655
Test name
Test status
Simulation time	393713601 ps
CPU time	5.81 seconds
Started	Jun 09 02:25:13 PM PDT 24
Finished	Jun 09 02:25:19 PM PDT 24
Peak memory	225040 kb
Host	smart-e6993229-ac2d-4d01-aeea-b4b9a9d513f2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=829600052 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_security_escalation.829600052
Directory	/workspace/17.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/17.lc_ctrl_smoke.2706179133
Short name	T861
Test name
Test status
Simulation time	77234298 ps
CPU time	2.6 seconds
Started	Jun 09 02:25:25 PM PDT 24
Finished	Jun 09 02:25:28 PM PDT 24
Peak memory	214704 kb
Host	smart-bcbb3686-7f34-46c9-b281-6f729782e9c7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2706179133 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_smoke.2706179133
Directory	/workspace/17.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/17.lc_ctrl_state_failure.1475005766
Short name	T761
Test name
Test status
Simulation time	314384957 ps
CPU time	26.89 seconds
Started	Jun 09 02:25:17 PM PDT 24
Finished	Jun 09 02:25:44 PM PDT 24
Peak memory	251404 kb
Host	smart-beedf7a1-81bf-4fb1-8829-244f9787160c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1475005766 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_failure.1475005766
Directory	/workspace/17.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/17.lc_ctrl_state_post_trans.3408470353
Short name	T794
Test name
Test status
Simulation time	74263060 ps
CPU time	6.3 seconds
Started	Jun 09 02:25:14 PM PDT 24
Finished	Jun 09 02:25:21 PM PDT 24
Peak memory	247396 kb
Host	smart-3d5b5386-d7b1-4aa7-83b7-e45bed09ecc7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3408470353 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_post_trans.3408470353
Directory	/workspace/17.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/17.lc_ctrl_stress_all.88827367
Short name	T523
Test name
Test status
Simulation time	1711294486 ps
CPU time	66.59 seconds
Started	Jun 09 02:25:16 PM PDT 24
Finished	Jun 09 02:26:23 PM PDT 24
Peak memory	271920 kb
Host	smart-1b7c70c7-d9f9-4549-b6c9-0183603e09df
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88827367 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_T EST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 7.lc_ctrl_stress_all.88827367
Directory	/workspace/17.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/17.lc_ctrl_stress_all_with_rand_reset.1321931000
Short name	T746
Test name
Test status
Simulation time	143091622904 ps
CPU time	1097.38 seconds
Started	Jun 09 02:25:14 PM PDT 24
Finished	Jun 09 02:43:32 PM PDT 24
Peak memory	300752 kb
Host	smart-05faf73f-4f42-468c-b1b6-b6970a50d21a
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=1321931000 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_stress_all_with_rand_reset.1321931000
Directory	/workspace/17.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/17.lc_ctrl_volatile_unlock_smoke.881171188
Short name	T552
Test name
Test status
Simulation time	147814926 ps
CPU time	0.91 seconds
Started	Jun 09 02:25:10 PM PDT 24
Finished	Jun 09 02:25:11 PM PDT 24
Peak memory	212448 kb
Host	smart-74debbba-a10e-4af7-8166-bba791408b3b
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881171188 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ct rl_volatile_unlock_smoke.881171188
Directory	/workspace/17.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/18.lc_ctrl_alert_test.769504522
Short name	T471
Test name
Test status
Simulation time	92464143 ps
CPU time	0.94 seconds
Started	Jun 09 02:25:23 PM PDT 24
Finished	Jun 09 02:25:24 PM PDT 24
Peak memory	209516 kb
Host	smart-401da2cd-467f-4c49-a654-fccca278e980
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769504522 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_alert_test.769504522
Directory	/workspace/18.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/18.lc_ctrl_errors.2679515190
Short name	T867
Test name
Test status
Simulation time	1078690770 ps
CPU time	22.43 seconds
Started	Jun 09 02:25:28 PM PDT 24
Finished	Jun 09 02:25:51 PM PDT 24
Peak memory	218756 kb
Host	smart-09490268-9091-414f-97b9-bd80c3a125d1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2679515190 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_errors.2679515190
Directory	/workspace/18.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/18.lc_ctrl_jtag_access.3332812926
Short name	T874
Test name
Test status
Simulation time	1142029575 ps
CPU time	2.56 seconds
Started	Jun 09 02:25:34 PM PDT 24
Finished	Jun 09 02:25:36 PM PDT 24
Peak memory	217672 kb
Host	smart-9c3f35ae-7896-4ca9-8729-77f4ef392f6e
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332812926 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_access.3332812926
Directory	/workspace/18.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/18.lc_ctrl_jtag_errors.2174917159
Short name	T6
Test name
Test status
Simulation time	11500089959 ps
CPU time	28.92 seconds
Started	Jun 09 02:25:14 PM PDT 24
Finished	Jun 09 02:25:43 PM PDT 24
Peak memory	219452 kb
Host	smart-ec139e8f-5964-4bfe-be09-f1299f1da3c6
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174917159 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_e rrors.2174917159
Directory	/workspace/18.lc_ctrl_jtag_errors/latest

Test location	/workspace/coverage/default/18.lc_ctrl_jtag_prog_failure.1028329982
Short name	T267
Test name
Test status
Simulation time	323150705 ps
CPU time	5.92 seconds
Started	Jun 09 02:25:20 PM PDT 24
Finished	Jun 09 02:25:26 PM PDT 24
Peak memory	222268 kb
Host	smart-53f2d95b-d98c-4afd-b492-20d675701535
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028329982 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jta g_prog_failure.1028329982
Directory	/workspace/18.lc_ctrl_jtag_prog_failure/latest

Test location	/workspace/coverage/default/18.lc_ctrl_jtag_smoke.1630973134
Short name	T546
Test name
Test status
Simulation time	217556796 ps
CPU time	2.09 seconds
Started	Jun 09 02:25:14 PM PDT 24
Finished	Jun 09 02:25:16 PM PDT 24
Peak memory	218228 kb
Host	smart-ffdfebd8-137e-4435-a558-45379298a386
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630973134 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_smoke .1630973134
Directory	/workspace/18.lc_ctrl_jtag_smoke/latest

Test location	/workspace/coverage/default/18.lc_ctrl_jtag_state_failure.1245671570
Short name	T555
Test name
Test status
Simulation time	1539759299 ps
CPU time	70.19 seconds
Started	Jun 09 02:25:17 PM PDT 24
Finished	Jun 09 02:26:28 PM PDT 24
Peak memory	267792 kb
Host	smart-bf5b8bc1-47b2-4558-b059-9e113b2ddc28
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245671570 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jt ag_state_failure.1245671570
Directory	/workspace/18.lc_ctrl_jtag_state_failure/latest

Test location	/workspace/coverage/default/18.lc_ctrl_jtag_state_post_trans.2360150993
Short name	T390
Test name
Test status
Simulation time	14151070677 ps
CPU time	18.91 seconds
Started	Jun 09 02:25:24 PM PDT 24
Finished	Jun 09 02:25:44 PM PDT 24
Peak memory	251448 kb
Host	smart-5eb98a17-bfe7-4b73-a99e-0f9dad194a92
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360150993 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl _jtag_state_post_trans.2360150993
Directory	/workspace/18.lc_ctrl_jtag_state_post_trans/latest

Test location	/workspace/coverage/default/18.lc_ctrl_prog_failure.1287609391
Short name	T470
Test name
Test status
Simulation time	1312287781 ps
CPU time	3.96 seconds
Started	Jun 09 02:25:15 PM PDT 24
Finished	Jun 09 02:25:20 PM PDT 24
Peak memory	218692 kb
Host	smart-7dd5f712-8eb3-461d-8640-8cac5ef97978
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1287609391 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_prog_failure.1287609391
Directory	/workspace/18.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/18.lc_ctrl_sec_mubi.2874721536
Short name	T399
Test name
Test status
Simulation time	1616236397 ps
CPU time	28.99 seconds
Started	Jun 09 02:25:22 PM PDT 24
Finished	Jun 09 02:25:51 PM PDT 24
Peak memory	220636 kb
Host	smart-73dcf82c-62ee-4126-b29f-24bb694860cc
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874721536 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_mubi.2874721536
Directory	/workspace/18.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/18.lc_ctrl_sec_token_digest.4021087497
Short name	T519
Test name
Test status
Simulation time	585739714 ps
CPU time	14.16 seconds
Started	Jun 09 02:25:32 PM PDT 24
Finished	Jun 09 02:25:47 PM PDT 24
Peak memory	218696 kb
Host	smart-bc79d15d-5d4d-439c-8440-fd939f9d5b86
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021087497 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_d igest.4021087497
Directory	/workspace/18.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/18.lc_ctrl_sec_token_mux.931576451
Short name	T745
Test name
Test status
Simulation time	875470765 ps
CPU time	8.45 seconds
Started	Jun 09 02:25:26 PM PDT 24
Finished	Jun 09 02:25:35 PM PDT 24
Peak memory	218700 kb
Host	smart-07200fd9-d83d-487e-baec-079c84312006
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931576451 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_mux.931576451
Directory	/workspace/18.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/18.lc_ctrl_security_escalation.1531080365
Short name	T602
Test name
Test status
Simulation time	419146649 ps
CPU time	9.75 seconds
Started	Jun 09 02:25:28 PM PDT 24
Finished	Jun 09 02:25:38 PM PDT 24
Peak memory	226524 kb
Host	smart-63fe4570-3dba-47ce-bc86-f4bdf5b91508
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1531080365 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_security_escalation.1531080365
Directory	/workspace/18.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/18.lc_ctrl_smoke.2482823912
Short name	T524
Test name
Test status
Simulation time	129031790 ps
CPU time	2.92 seconds
Started	Jun 09 02:25:29 PM PDT 24
Finished	Jun 09 02:25:33 PM PDT 24
Peak memory	215200 kb
Host	smart-4f84ba32-56ed-4631-b163-74e50b4d05a7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2482823912 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_smoke.2482823912
Directory	/workspace/18.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/18.lc_ctrl_state_failure.247479604
Short name	T809
Test name
Test status
Simulation time	1188624542 ps
CPU time	27.69 seconds
Started	Jun 09 02:25:14 PM PDT 24
Finished	Jun 09 02:25:42 PM PDT 24
Peak memory	251392 kb
Host	smart-7930aaec-e44e-4bd7-aeaf-2a284a0fc5f8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=247479604 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_failure.247479604
Directory	/workspace/18.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/18.lc_ctrl_state_post_trans.1459043552
Short name	T726
Test name
Test status
Simulation time	195110688 ps
CPU time	7.86 seconds
Started	Jun 09 02:25:19 PM PDT 24
Finished	Jun 09 02:25:27 PM PDT 24
Peak memory	251460 kb
Host	smart-e145ba1b-f9d6-4e6c-a755-c7cd91363972
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1459043552 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_post_trans.1459043552
Directory	/workspace/18.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/18.lc_ctrl_stress_all.3388262510
Short name	T218
Test name
Test status
Simulation time	39026569512 ps
CPU time	142.55 seconds
Started	Jun 09 02:25:18 PM PDT 24
Finished	Jun 09 02:27:41 PM PDT 24
Peak memory	284208 kb
Host	smart-b5425ae4-d11c-428c-85e2-a3021457b390
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388262510 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_stress_all.3388262510
Directory	/workspace/18.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/18.lc_ctrl_stress_all_with_rand_reset.1753825411
Short name	T169
Test name
Test status
Simulation time	59688559067 ps
CPU time	331.57 seconds
Started	Jun 09 02:25:28 PM PDT 24
Finished	Jun 09 02:31:00 PM PDT 24
Peak memory	357076 kb
Host	smart-044e89da-03d0-49b1-bac1-e7b147adaae4
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=1753825411 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_stress_all_with_rand_reset.1753825411
Directory	/workspace/18.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/18.lc_ctrl_volatile_unlock_smoke.2386804784
Short name	T393
Test name
Test status
Simulation time	24603784 ps
CPU time	0.82 seconds
Started	Jun 09 02:25:27 PM PDT 24
Finished	Jun 09 02:25:28 PM PDT 24
Peak memory	209332 kb
Host	smart-57caf8a1-d453-4d06-8b5b-e09e5ed52c39
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386804784 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_c trl_volatile_unlock_smoke.2386804784
Directory	/workspace/18.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/19.lc_ctrl_alert_test.3100198470
Short name	T708
Test name
Test status
Simulation time	64894297 ps
CPU time	0.93 seconds
Started	Jun 09 02:25:20 PM PDT 24
Finished	Jun 09 02:25:21 PM PDT 24
Peak memory	209496 kb
Host	smart-8f530edc-876d-41e3-8660-54d8927d6b0b
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100198470 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_alert_test.3100198470
Directory	/workspace/19.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/19.lc_ctrl_jtag_access.1838410597
Short name	T723
Test name
Test status
Simulation time	1120333182 ps
CPU time	7.28 seconds
Started	Jun 09 02:25:23 PM PDT 24
Finished	Jun 09 02:25:31 PM PDT 24
Peak memory	217652 kb
Host	smart-e057ca76-5975-417d-a38d-01da9821d646
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838410597 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_access.1838410597
Directory	/workspace/19.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/19.lc_ctrl_jtag_errors.1809973777
Short name	T737
Test name
Test status
Simulation time	11348127385 ps
CPU time	73.46 seconds
Started	Jun 09 02:25:29 PM PDT 24
Finished	Jun 09 02:26:43 PM PDT 24
Peak memory	219344 kb
Host	smart-1dfad4cd-9597-4893-8b11-64f60f09438c
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809973777 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_e rrors.1809973777
Directory	/workspace/19.lc_ctrl_jtag_errors/latest

Test location	/workspace/coverage/default/19.lc_ctrl_jtag_prog_failure.1917680967
Short name	T251
Test name
Test status
Simulation time	220578137 ps
CPU time	1.87 seconds
Started	Jun 09 02:25:22 PM PDT 24
Finished	Jun 09 02:25:24 PM PDT 24
Peak memory	218704 kb
Host	smart-abfe375b-f7ab-4a3f-9390-512e9c5ad1a7
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917680967 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jta g_prog_failure.1917680967
Directory	/workspace/19.lc_ctrl_jtag_prog_failure/latest

Test location	/workspace/coverage/default/19.lc_ctrl_jtag_smoke.1980776419
Short name	T176
Test name
Test status
Simulation time	2514319437 ps
CPU time	2.38 seconds
Started	Jun 09 02:25:23 PM PDT 24
Finished	Jun 09 02:25:26 PM PDT 24
Peak memory	218248 kb
Host	smart-6ca16f79-5703-4df3-a4aa-d66eddf3ba7c
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980776419 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_smoke .1980776419
Directory	/workspace/19.lc_ctrl_jtag_smoke/latest

Test location	/workspace/coverage/default/19.lc_ctrl_jtag_state_failure.2552220132
Short name	T855
Test name
Test status
Simulation time	18234266692 ps
CPU time	85.06 seconds
Started	Jun 09 02:25:29 PM PDT 24
Finished	Jun 09 02:26:55 PM PDT 24
Peak memory	281636 kb
Host	smart-b71f7b5c-49a5-44e4-8a7d-69306ccf5a74
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552220132 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jt ag_state_failure.2552220132
Directory	/workspace/19.lc_ctrl_jtag_state_failure/latest

Test location	/workspace/coverage/default/19.lc_ctrl_jtag_state_post_trans.1466120332
Short name	T877
Test name
Test status
Simulation time	1104102016 ps
CPU time	14.38 seconds
Started	Jun 09 02:25:24 PM PDT 24
Finished	Jun 09 02:25:38 PM PDT 24
Peak memory	251432 kb
Host	smart-6da02779-7136-4df5-903a-32ff12bdec7c
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466120332 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl _jtag_state_post_trans.1466120332
Directory	/workspace/19.lc_ctrl_jtag_state_post_trans/latest

Test location	/workspace/coverage/default/19.lc_ctrl_prog_failure.3371755838
Short name	T694
Test name
Test status
Simulation time	464795366 ps
CPU time	3.73 seconds
Started	Jun 09 02:25:22 PM PDT 24
Finished	Jun 09 02:25:26 PM PDT 24
Peak memory	218664 kb
Host	smart-73e5df14-d711-47ca-bfac-35ed22fa0411
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3371755838 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_prog_failure.3371755838
Directory	/workspace/19.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/19.lc_ctrl_sec_mubi.4075288730
Short name	T609
Test name
Test status
Simulation time	5522974861 ps
CPU time	21.71 seconds
Started	Jun 09 02:25:23 PM PDT 24
Finished	Jun 09 02:25:45 PM PDT 24
Peak memory	220840 kb
Host	smart-89309c84-2486-490a-bbb8-b8810c5d8f15
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075288730 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_mubi.4075288730
Directory	/workspace/19.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/19.lc_ctrl_sec_token_digest.1842947943
Short name	T510
Test name
Test status
Simulation time	985915438 ps
CPU time	11.74 seconds
Started	Jun 09 02:25:24 PM PDT 24
Finished	Jun 09 02:25:37 PM PDT 24
Peak memory	226540 kb
Host	smart-6977f147-4d5f-4b55-8d52-47af86cc7b30
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842947943 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_d igest.1842947943
Directory	/workspace/19.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/19.lc_ctrl_sec_token_mux.4066583576
Short name	T323
Test name
Test status
Simulation time	298972635 ps
CPU time	11.09 seconds
Started	Jun 09 02:25:21 PM PDT 24
Finished	Jun 09 02:25:33 PM PDT 24
Peak memory	218704 kb
Host	smart-63d9e68c-bdd7-43b1-b3ff-55883a6305ca
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066583576 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_mux. 4066583576
Directory	/workspace/19.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/19.lc_ctrl_security_escalation.3672933892
Short name	T696
Test name
Test status
Simulation time	925752229 ps
CPU time	7.53 seconds
Started	Jun 09 02:25:23 PM PDT 24
Finished	Jun 09 02:25:31 PM PDT 24
Peak memory	226524 kb
Host	smart-4ce2cf8f-bdd8-4953-a62f-ccc9654487de
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3672933892 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_security_escalation.3672933892
Directory	/workspace/19.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/19.lc_ctrl_smoke.687693260
Short name	T606
Test name
Test status
Simulation time	269860769 ps
CPU time	9.84 seconds
Started	Jun 09 02:25:20 PM PDT 24
Finished	Jun 09 02:25:30 PM PDT 24
Peak memory	218320 kb
Host	smart-6f8a55e1-b93d-4b74-98b0-4e8dee866ffc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=687693260 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_smoke.687693260
Directory	/workspace/19.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/19.lc_ctrl_state_failure.2758628514
Short name	T466
Test name
Test status
Simulation time	1483220375 ps
CPU time	27.11 seconds
Started	Jun 09 02:25:17 PM PDT 24
Finished	Jun 09 02:25:44 PM PDT 24
Peak memory	251512 kb
Host	smart-ddd4449f-2a25-4206-a9b3-21a0307f42c4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2758628514 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_failure.2758628514
Directory	/workspace/19.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/19.lc_ctrl_state_post_trans.452869650
Short name	T641
Test name
Test status
Simulation time	95969299 ps
CPU time	9.36 seconds
Started	Jun 09 02:25:23 PM PDT 24
Finished	Jun 09 02:25:33 PM PDT 24
Peak memory	251424 kb
Host	smart-e0b8c44a-7a48-4bf1-8948-c94a1476d734
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=452869650 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_post_trans.452869650
Directory	/workspace/19.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/19.lc_ctrl_stress_all.2640151274
Short name	T659
Test name
Test status
Simulation time	15824135352 ps
CPU time	57.91 seconds
Started	Jun 09 02:25:28 PM PDT 24
Finished	Jun 09 02:26:27 PM PDT 24
Peak memory	276064 kb
Host	smart-20117477-e5a2-4d25-9da4-c9112bfd7bf6
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640151274 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_stress_all.2640151274
Directory	/workspace/19.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/19.lc_ctrl_stress_all_with_rand_reset.3146565769
Short name	T633
Test name
Test status
Simulation time	200671243825 ps
CPU time	1326.59 seconds
Started	Jun 09 02:25:24 PM PDT 24
Finished	Jun 09 02:47:31 PM PDT 24
Peak memory	439012 kb
Host	smart-12207c2c-e9b5-4325-9c5f-338fee29c079
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=3146565769 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_stress_all_with_rand_reset.3146565769
Directory	/workspace/19.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/19.lc_ctrl_volatile_unlock_smoke.2560915740
Short name	T728
Test name
Test status
Simulation time	18408169 ps
CPU time	1.17 seconds
Started	Jun 09 02:25:19 PM PDT 24
Finished	Jun 09 02:25:21 PM PDT 24
Peak memory	218308 kb
Host	smart-e046ebdc-99cf-4489-9a9e-7e6176c60c5d
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560915740 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_c trl_volatile_unlock_smoke.2560915740
Directory	/workspace/19.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/2.lc_ctrl_alert_test.1858657637
Short name	T85
Test name
Test status
Simulation time	109244177 ps
CPU time	1.27 seconds
Started	Jun 09 02:24:38 PM PDT 24
Finished	Jun 09 02:24:39 PM PDT 24
Peak memory	209444 kb
Host	smart-75416095-3910-4779-a42b-45ea4ff6939a
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858657637 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_alert_test.1858657637
Directory	/workspace/2.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/2.lc_ctrl_errors.2582263788
Short name	T787
Test name
Test status
Simulation time	280596976 ps
CPU time	11.28 seconds
Started	Jun 09 02:24:33 PM PDT 24
Finished	Jun 09 02:24:45 PM PDT 24
Peak memory	218756 kb
Host	smart-fda3efb6-3d52-4a67-a4ff-3e4cf671c1f9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2582263788 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_errors.2582263788
Directory	/workspace/2.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/2.lc_ctrl_jtag_access.2519168625
Short name	T513
Test name
Test status
Simulation time	509323810 ps
CPU time	3.27 seconds
Started	Jun 09 02:24:24 PM PDT 24
Finished	Jun 09 02:24:28 PM PDT 24
Peak memory	217548 kb
Host	smart-2fedaf0d-f920-401a-960f-83e44367c151
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519168625 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_access.2519168625
Directory	/workspace/2.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/2.lc_ctrl_jtag_errors.2677957535
Short name	T215
Test name
Test status
Simulation time	5627089788 ps
CPU time	80.66 seconds
Started	Jun 09 02:24:32 PM PDT 24
Finished	Jun 09 02:25:53 PM PDT 24
Peak memory	219440 kb
Host	smart-21b5bd48-291c-427b-9f00-1bdc03f413a1
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677957535 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_er rors.2677957535
Directory	/workspace/2.lc_ctrl_jtag_errors/latest

Test location	/workspace/coverage/default/2.lc_ctrl_jtag_priority.2582399867
Short name	T521
Test name
Test status
Simulation time	1121703392 ps
CPU time	4.02 seconds
Started	Jun 09 02:24:33 PM PDT 24
Finished	Jun 09 02:24:38 PM PDT 24
Peak memory	218052 kb
Host	smart-7c014328-d431-49eb-b416-20c1e6ffe83a
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582399867 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_priority.2 582399867
Directory	/workspace/2.lc_ctrl_jtag_priority/latest

Test location	/workspace/coverage/default/2.lc_ctrl_jtag_prog_failure.2270078454
Short name	T405
Test name
Test status
Simulation time	925431425 ps
CPU time	13.09 seconds
Started	Jun 09 02:24:31 PM PDT 24
Finished	Jun 09 02:24:44 PM PDT 24
Peak memory	218668 kb
Host	smart-b2e70ab8-294d-44cd-9597-cf31e6445049
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270078454 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag _prog_failure.2270078454
Directory	/workspace/2.lc_ctrl_jtag_prog_failure/latest

Test location	/workspace/coverage/default/2.lc_ctrl_jtag_regwen_during_op.3231396574
Short name	T575
Test name
Test status
Simulation time	1794300625 ps
CPU time	21.44 seconds
Started	Jun 09 02:24:27 PM PDT 24
Finished	Jun 09 02:24:48 PM PDT 24
Peak memory	218196 kb
Host	smart-c38eb2d8-6867-46f2-9f95-2b2e5f52ac52
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231396574 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_ jtag_regwen_during_op.3231396574
Directory	/workspace/2.lc_ctrl_jtag_regwen_during_op/latest

Test location	/workspace/coverage/default/2.lc_ctrl_jtag_smoke.1390191544
Short name	T368
Test name
Test status
Simulation time	1112069810 ps
CPU time	13.24 seconds
Started	Jun 09 02:24:24 PM PDT 24
Finished	Jun 09 02:24:38 PM PDT 24
Peak memory	218212 kb
Host	smart-dcfb2c36-ebd6-48eb-aace-5a40a18e6692
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390191544 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_smoke. 1390191544
Directory	/workspace/2.lc_ctrl_jtag_smoke/latest

Test location	/workspace/coverage/default/2.lc_ctrl_jtag_state_failure.3675984839
Short name	T680
Test name
Test status
Simulation time	3247522460 ps
CPU time	57.98 seconds
Started	Jun 09 02:24:31 PM PDT 24
Finished	Jun 09 02:25:29 PM PDT 24
Peak memory	281752 kb
Host	smart-573211ef-478c-40e7-8f0b-358dabb74400
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675984839 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jta g_state_failure.3675984839
Directory	/workspace/2.lc_ctrl_jtag_state_failure/latest

Test location	/workspace/coverage/default/2.lc_ctrl_jtag_state_post_trans.2106412882
Short name	T518
Test name
Test status
Simulation time	407193231 ps
CPU time	14.44 seconds
Started	Jun 09 02:24:26 PM PDT 24
Finished	Jun 09 02:24:41 PM PDT 24
Peak memory	251428 kb
Host	smart-a6c8ebbb-21e1-4319-aac2-b64768f98c7b
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106412882 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_ jtag_state_post_trans.2106412882
Directory	/workspace/2.lc_ctrl_jtag_state_post_trans/latest

Test location	/workspace/coverage/default/2.lc_ctrl_prog_failure.1004800688
Short name	T103
Test name
Test status
Simulation time	187907156 ps
CPU time	2.99 seconds
Started	Jun 09 02:24:22 PM PDT 24
Finished	Jun 09 02:24:25 PM PDT 24
Peak memory	223176 kb
Host	smart-2fccb929-608a-4931-a421-687f31368769
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1004800688 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_prog_failure.1004800688
Directory	/workspace/2.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/2.lc_ctrl_regwen_during_op.693782625
Short name	T706
Test name
Test status
Simulation time	275467113 ps
CPU time	17.9 seconds
Started	Jun 09 02:24:33 PM PDT 24
Finished	Jun 09 02:24:52 PM PDT 24
Peak memory	218180 kb
Host	smart-fbae1416-df8d-4d76-accb-d4c7959a6b39
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=693782625 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_regwen_during_op.693782625
Directory	/workspace/2.lc_ctrl_regwen_during_op/latest

Test location	/workspace/coverage/default/2.lc_ctrl_sec_cm.4005240921
Short name	T63
Test name
Test status
Simulation time	988324022 ps
CPU time	35.16 seconds
Started	Jun 09 02:24:26 PM PDT 24
Finished	Jun 09 02:25:01 PM PDT 24
Peak memory	282724 kb
Host	smart-d3fb1065-6753-45ec-8551-81eed15b2e14
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005240921 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_cm.4005240921
Directory	/workspace/2.lc_ctrl_sec_cm/latest

Test location	/workspace/coverage/default/2.lc_ctrl_sec_mubi.434263043
Short name	T860
Test name
Test status
Simulation time	1251289344 ps
CPU time	9.53 seconds
Started	Jun 09 02:24:25 PM PDT 24
Finished	Jun 09 02:24:35 PM PDT 24
Peak memory	219392 kb
Host	smart-a4685631-71ae-44e4-b55e-ce28c3dc9684
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434263043 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_mubi.434263043
Directory	/workspace/2.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/2.lc_ctrl_sec_token_digest.3488204632
Short name	T871
Test name
Test status
Simulation time	795447271 ps
CPU time	16.76 seconds
Started	Jun 09 02:24:22 PM PDT 24
Finished	Jun 09 02:24:39 PM PDT 24
Peak memory	226540 kb
Host	smart-b41b94a2-cfc4-4126-984d-2b8d5b17ff95
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488204632 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_di gest.3488204632
Directory	/workspace/2.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/2.lc_ctrl_sec_token_mux.730539874
Short name	T349
Test name
Test status
Simulation time	1445470669 ps
CPU time	8.32 seconds
Started	Jun 09 02:24:22 PM PDT 24
Finished	Jun 09 02:24:31 PM PDT 24
Peak memory	218728 kb
Host	smart-d4087641-14c8-44b6-a6b7-161ac25cc614
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730539874 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_mux.730539874
Directory	/workspace/2.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/2.lc_ctrl_security_escalation.24827237
Short name	T162
Test name
Test status
Simulation time	400622342 ps
CPU time	11.08 seconds
Started	Jun 09 02:24:27 PM PDT 24
Finished	Jun 09 02:24:39 PM PDT 24
Peak memory	218752 kb
Host	smart-52435409-1721-442e-9aab-e59bdf6e2703
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=24827237 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_security_escalation.24827237
Directory	/workspace/2.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/2.lc_ctrl_smoke.4190395030
Short name	T486
Test name
Test status
Simulation time	125806387 ps
CPU time	5.22 seconds
Started	Jun 09 02:24:34 PM PDT 24
Finished	Jun 09 02:24:40 PM PDT 24
Peak memory	218168 kb
Host	smart-3ae1e075-84c9-432b-a79b-918fa98fbc16
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4190395030 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_smoke.4190395030
Directory	/workspace/2.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/2.lc_ctrl_state_failure.155506806
Short name	T725
Test name
Test status
Simulation time	421815005 ps
CPU time	21.1 seconds
Started	Jun 09 02:24:33 PM PDT 24
Finished	Jun 09 02:24:54 PM PDT 24
Peak memory	251428 kb
Host	smart-38c1d050-196a-4dc2-a96c-7c99060f101f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=155506806 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_failure.155506806
Directory	/workspace/2.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/2.lc_ctrl_state_post_trans.1830302488
Short name	T217
Test name
Test status
Simulation time	233949072 ps
CPU time	4.04 seconds
Started	Jun 09 02:24:24 PM PDT 24
Finished	Jun 09 02:24:28 PM PDT 24
Peak memory	223440 kb
Host	smart-5d185cf0-2bbf-4ec8-b515-13c093728789
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1830302488 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_post_trans.1830302488
Directory	/workspace/2.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/2.lc_ctrl_stress_all.600972686
Short name	T543
Test name
Test status
Simulation time	24804005021 ps
CPU time	58.48 seconds
Started	Jun 09 02:24:25 PM PDT 24
Finished	Jun 09 02:25:24 PM PDT 24
Peak memory	232652 kb
Host	smart-7e93e0ec-e521-4149-be90-a3d049d37594
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600972686 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_ TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_stress_all.600972686
Directory	/workspace/2.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/2.lc_ctrl_volatile_unlock_smoke.3233825789
Short name	T498
Test name
Test status
Simulation time	14135738 ps
CPU time	1.1 seconds
Started	Jun 09 02:24:32 PM PDT 24
Finished	Jun 09 02:24:34 PM PDT 24
Peak memory	212384 kb
Host	smart-ef255fa1-1ffd-4181-84a9-976f4788966e
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233825789 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ct rl_volatile_unlock_smoke.3233825789
Directory	/workspace/2.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/20.lc_ctrl_alert_test.1690012118
Short name	T829
Test name
Test status
Simulation time	21338288 ps
CPU time	1 seconds
Started	Jun 09 02:25:21 PM PDT 24
Finished	Jun 09 02:25:23 PM PDT 24
Peak memory	209496 kb
Host	smart-90345f4f-2750-45c7-a719-64144f1c12df
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690012118 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_alert_test.1690012118
Directory	/workspace/20.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/20.lc_ctrl_errors.3197060225
Short name	T25
Test name
Test status
Simulation time	2261049798 ps
CPU time	14.6 seconds
Started	Jun 09 02:25:23 PM PDT 24
Finished	Jun 09 02:25:38 PM PDT 24
Peak memory	218748 kb
Host	smart-816f9e8f-b24c-4b74-a1ff-ed19ad8b0baa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3197060225 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_errors.3197060225
Directory	/workspace/20.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/20.lc_ctrl_jtag_access.3491764395
Short name	T607
Test name
Test status
Simulation time	1878414446 ps
CPU time	13.08 seconds
Started	Jun 09 02:25:22 PM PDT 24
Finished	Jun 09 02:25:35 PM PDT 24
Peak memory	218004 kb
Host	smart-d7f61e28-65dc-4883-8b68-a49a02dafcc1
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491764395 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_jtag_access.3491764395
Directory	/workspace/20.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/20.lc_ctrl_prog_failure.2468599837
Short name	T450
Test name
Test status
Simulation time	67590299 ps
CPU time	3.54 seconds
Started	Jun 09 02:25:30 PM PDT 24
Finished	Jun 09 02:25:34 PM PDT 24
Peak memory	222704 kb
Host	smart-854a4870-5251-40fc-b8f0-89cd1bf4f5eb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2468599837 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_prog_failure.2468599837
Directory	/workspace/20.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/20.lc_ctrl_sec_mubi.1279945580
Short name	T781
Test name
Test status
Simulation time	1576061319 ps
CPU time	11.92 seconds
Started	Jun 09 02:25:28 PM PDT 24
Finished	Jun 09 02:25:40 PM PDT 24
Peak memory	219396 kb
Host	smart-48b670c2-b9d9-4e0e-aeca-f1e4e528241a
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279945580 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_mubi.1279945580
Directory	/workspace/20.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/20.lc_ctrl_sec_token_digest.2366678539
Short name	T38
Test name
Test status
Simulation time	248630273 ps
CPU time	11.15 seconds
Started	Jun 09 02:25:26 PM PDT 24
Finished	Jun 09 02:25:38 PM PDT 24
Peak memory	218724 kb
Host	smart-e18a3fc3-a50f-4dc8-9ab3-023044e62880
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366678539 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_d igest.2366678539
Directory	/workspace/20.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/20.lc_ctrl_sec_token_mux.2794680148
Short name	T689
Test name
Test status
Simulation time	1211182664 ps
CPU time	8.76 seconds
Started	Jun 09 02:25:22 PM PDT 24
Finished	Jun 09 02:25:31 PM PDT 24
Peak memory	218720 kb
Host	smart-9a2ebf2c-5bea-4720-b6d5-a71c9b4714d4
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794680148 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_mux. 2794680148
Directory	/workspace/20.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/20.lc_ctrl_security_escalation.1815995535
Short name	T678
Test name
Test status
Simulation time	301327786 ps
CPU time	12.41 seconds
Started	Jun 09 02:25:22 PM PDT 24
Finished	Jun 09 02:25:35 PM PDT 24
Peak memory	226512 kb
Host	smart-13aaec84-a257-40a1-934b-e4bd0490a8f1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1815995535 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_security_escalation.1815995535
Directory	/workspace/20.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/20.lc_ctrl_smoke.839446755
Short name	T70
Test name
Test status
Simulation time	117073022 ps
CPU time	1.84 seconds
Started	Jun 09 02:25:28 PM PDT 24
Finished	Jun 09 02:25:30 PM PDT 24
Peak memory	222640 kb
Host	smart-b3313eda-5ead-4209-835f-47555105c102
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=839446755 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_smoke.839446755
Directory	/workspace/20.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/20.lc_ctrl_state_failure.2530908932
Short name	T378
Test name
Test status
Simulation time	201007891 ps
CPU time	23.56 seconds
Started	Jun 09 02:25:24 PM PDT 24
Finished	Jun 09 02:25:48 PM PDT 24
Peak memory	251416 kb
Host	smart-8b164a39-d4ae-47ef-a2d0-8022c1bc186a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2530908932 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_failure.2530908932
Directory	/workspace/20.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/20.lc_ctrl_state_post_trans.3490993947
Short name	T159
Test name
Test status
Simulation time	65191810 ps
CPU time	7.59 seconds
Started	Jun 09 02:25:25 PM PDT 24
Finished	Jun 09 02:25:33 PM PDT 24
Peak memory	251448 kb
Host	smart-f2ffcbac-729d-4515-a21b-171f70a2c379
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3490993947 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_post_trans.3490993947
Directory	/workspace/20.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/20.lc_ctrl_stress_all.1361900458
Short name	T322
Test name
Test status
Simulation time	44435500896 ps
CPU time	298.87 seconds
Started	Jun 09 02:25:19 PM PDT 24
Finished	Jun 09 02:30:18 PM PDT 24
Peak memory	284216 kb
Host	smart-ceee6744-a76d-4f33-8c12-32ca80575d4e
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361900458 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_stress_all.1361900458
Directory	/workspace/20.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/20.lc_ctrl_stress_all_with_rand_reset.2848120111
Short name	T111
Test name
Test status
Simulation time	86212977978 ps
CPU time	368.17 seconds
Started	Jun 09 02:25:24 PM PDT 24
Finished	Jun 09 02:31:32 PM PDT 24
Peak memory	284468 kb
Host	smart-42844907-2305-4d3b-9b20-8cf59d497343
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=2848120111 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_stress_all_with_rand_reset.2848120111
Directory	/workspace/20.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/20.lc_ctrl_volatile_unlock_smoke.743042506
Short name	T456
Test name
Test status
Simulation time	26579751 ps
CPU time	0.9 seconds
Started	Jun 09 02:25:28 PM PDT 24
Finished	Jun 09 02:25:30 PM PDT 24
Peak memory	212356 kb
Host	smart-883a5108-9c42-453d-8d56-cafe4309ec05
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743042506 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ct rl_volatile_unlock_smoke.743042506
Directory	/workspace/20.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/21.lc_ctrl_alert_test.1252749791
Short name	T254
Test name
Test status
Simulation time	60158961 ps
CPU time	1.28 seconds
Started	Jun 09 02:25:41 PM PDT 24
Finished	Jun 09 02:25:43 PM PDT 24
Peak memory	209516 kb
Host	smart-8181a03b-ed16-4e76-ab46-e18ea7d48aa0
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252749791 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_alert_test.1252749791
Directory	/workspace/21.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/21.lc_ctrl_errors.3853577365
Short name	T458
Test name
Test status
Simulation time	633256952 ps
CPU time	8.39 seconds
Started	Jun 09 02:25:25 PM PDT 24
Finished	Jun 09 02:25:34 PM PDT 24
Peak memory	218736 kb
Host	smart-32d0e2a7-6802-4f21-a5c0-193b065dc4aa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3853577365 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_errors.3853577365
Directory	/workspace/21.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/21.lc_ctrl_jtag_access.2630822683
Short name	T415
Test name
Test status
Simulation time	276341093 ps
CPU time	1.94 seconds
Started	Jun 09 02:25:29 PM PDT 24
Finished	Jun 09 02:25:32 PM PDT 24
Peak memory	217440 kb
Host	smart-c6ef2134-bc3d-44e0-8c64-16bca845ff68
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630822683 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_jtag_access.2630822683
Directory	/workspace/21.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/21.lc_ctrl_prog_failure.1276479512
Short name	T834
Test name
Test status
Simulation time	60862953 ps
CPU time	1.73 seconds
Started	Jun 09 02:25:29 PM PDT 24
Finished	Jun 09 02:25:31 PM PDT 24
Peak memory	222396 kb
Host	smart-c8e68440-6c22-4808-ab78-b345144a5c05
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1276479512 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_prog_failure.1276479512
Directory	/workspace/21.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/21.lc_ctrl_sec_mubi.1997148309
Short name	T228
Test name
Test status
Simulation time	528826712 ps
CPU time	15.72 seconds
Started	Jun 09 02:25:42 PM PDT 24
Finished	Jun 09 02:25:58 PM PDT 24
Peak memory	226564 kb
Host	smart-0def82dc-5d11-406b-9a01-e8f36649becd
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997148309 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_mubi.1997148309
Directory	/workspace/21.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/21.lc_ctrl_sec_token_digest.3741828490
Short name	T813
Test name
Test status
Simulation time	369782212 ps
CPU time	12.07 seconds
Started	Jun 09 02:25:25 PM PDT 24
Finished	Jun 09 02:25:37 PM PDT 24
Peak memory	218712 kb
Host	smart-c4f3874e-91d4-4928-941a-0299552ff421
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741828490 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_d igest.3741828490
Directory	/workspace/21.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/21.lc_ctrl_sec_token_mux.2663048422
Short name	T382
Test name
Test status
Simulation time	402771911 ps
CPU time	8.16 seconds
Started	Jun 09 02:25:23 PM PDT 24
Finished	Jun 09 02:25:32 PM PDT 24
Peak memory	218716 kb
Host	smart-730a6a18-7d5d-4ef7-92e3-659fc6ef143d
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663048422 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_mux. 2663048422
Directory	/workspace/21.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/21.lc_ctrl_security_escalation.1233081388
Short name	T61
Test name
Test status
Simulation time	949826201 ps
CPU time	6.48 seconds
Started	Jun 09 02:25:24 PM PDT 24
Finished	Jun 09 02:25:31 PM PDT 24
Peak memory	225092 kb
Host	smart-24216613-3e27-467d-a98c-fda0be5149ac
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1233081388 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_security_escalation.1233081388
Directory	/workspace/21.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/21.lc_ctrl_smoke.1886414354
Short name	T468
Test name
Test status
Simulation time	128647721 ps
CPU time	2.31 seconds
Started	Jun 09 02:25:21 PM PDT 24
Finished	Jun 09 02:25:24 PM PDT 24
Peak memory	218292 kb
Host	smart-3bcac4c8-f4b4-49f2-a523-ddc0378c1f94
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1886414354 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_smoke.1886414354
Directory	/workspace/21.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/21.lc_ctrl_state_failure.92553300
Short name	T276
Test name
Test status
Simulation time	362841755 ps
CPU time	24.22 seconds
Started	Jun 09 02:25:28 PM PDT 24
Finished	Jun 09 02:25:53 PM PDT 24
Peak memory	251504 kb
Host	smart-d34431a7-9e6f-4c72-9b9e-ba3f9e5df358
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=92553300 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_failure.92553300
Directory	/workspace/21.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/21.lc_ctrl_state_post_trans.2161144773
Short name	T247
Test name
Test status
Simulation time	64368847 ps
CPU time	6.3 seconds
Started	Jun 09 02:25:26 PM PDT 24
Finished	Jun 09 02:25:33 PM PDT 24
Peak memory	251020 kb
Host	smart-42d1e4a5-f9b7-44c8-8155-161256005d2a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2161144773 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_post_trans.2161144773
Directory	/workspace/21.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/21.lc_ctrl_stress_all.3702647182
Short name	T837
Test name
Test status
Simulation time	57440258211 ps
CPU time	76.57 seconds
Started	Jun 09 02:25:25 PM PDT 24
Finished	Jun 09 02:26:42 PM PDT 24
Peak memory	259456 kb
Host	smart-74e28281-c18d-4793-b1fb-6e0cf6da1fd1
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702647182 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_stress_all.3702647182
Directory	/workspace/21.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/21.lc_ctrl_volatile_unlock_smoke.411454128
Short name	T46
Test name
Test status
Simulation time	14053742 ps
CPU time	1.13 seconds
Started	Jun 09 02:25:21 PM PDT 24
Finished	Jun 09 02:25:23 PM PDT 24
Peak memory	212436 kb
Host	smart-df408f9a-037f-4003-a5e8-cd779a2e87e6
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411454128 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ct rl_volatile_unlock_smoke.411454128
Directory	/workspace/21.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/22.lc_ctrl_alert_test.3100556075
Short name	T387
Test name
Test status
Simulation time	22726632 ps
CPU time	0.92 seconds
Started	Jun 09 02:25:24 PM PDT 24
Finished	Jun 09 02:25:25 PM PDT 24
Peak memory	209512 kb
Host	smart-e906edb6-a510-4403-8247-2115e921037b
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100556075 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_alert_test.3100556075
Directory	/workspace/22.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/22.lc_ctrl_errors.980235175
Short name	T262
Test name
Test status
Simulation time	263542713 ps
CPU time	11.28 seconds
Started	Jun 09 02:25:42 PM PDT 24
Finished	Jun 09 02:25:53 PM PDT 24
Peak memory	218688 kb
Host	smart-ffe509fe-a069-4934-a0cf-ecc4af5551cf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=980235175 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_errors.980235175
Directory	/workspace/22.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/22.lc_ctrl_jtag_access.884593529
Short name	T721
Test name
Test status
Simulation time	399116284 ps
CPU time	5.74 seconds
Started	Jun 09 02:25:39 PM PDT 24
Finished	Jun 09 02:25:45 PM PDT 24
Peak memory	217568 kb
Host	smart-7256fcf6-9ae7-4643-b95d-b9251978660b
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884593529 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_jtag_access.884593529
Directory	/workspace/22.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/22.lc_ctrl_prog_failure.586083768
Short name	T358
Test name
Test status
Simulation time	40480064 ps
CPU time	2.13 seconds
Started	Jun 09 02:25:23 PM PDT 24
Finished	Jun 09 02:25:26 PM PDT 24
Peak memory	222728 kb
Host	smart-7b0659a9-3064-4dc5-9843-7fd624b236c7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=586083768 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_prog_failure.586083768
Directory	/workspace/22.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/22.lc_ctrl_sec_mubi.2402184093
Short name	T637
Test name
Test status
Simulation time	1390290791 ps
CPU time	12.99 seconds
Started	Jun 09 02:25:43 PM PDT 24
Finished	Jun 09 02:25:56 PM PDT 24
Peak memory	219392 kb
Host	smart-fce2b19c-ac1c-4a72-a610-978a24f7049f
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402184093 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_mubi.2402184093
Directory	/workspace/22.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/22.lc_ctrl_sec_token_digest.947659599
Short name	T769
Test name
Test status
Simulation time	518038363 ps
CPU time	14.71 seconds
Started	Jun 09 02:25:23 PM PDT 24
Finished	Jun 09 02:25:38 PM PDT 24
Peak memory	218744 kb
Host	smart-b37553c1-d98a-48d2-948a-a5156dd773b2
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947659599 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_di gest.947659599
Directory	/workspace/22.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/22.lc_ctrl_sec_token_mux.328046552
Short name	T467
Test name
Test status
Simulation time	1186304448 ps
CPU time	7.43 seconds
Started	Jun 09 02:25:25 PM PDT 24
Finished	Jun 09 02:25:33 PM PDT 24
Peak memory	226532 kb
Host	smart-ce0f8c48-3ee2-47bd-bee9-f01c9f969c87
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328046552 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_mux.328046552
Directory	/workspace/22.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/22.lc_ctrl_security_escalation.193938143
Short name	T868
Test name
Test status
Simulation time	621453394 ps
CPU time	8.84 seconds
Started	Jun 09 02:25:40 PM PDT 24
Finished	Jun 09 02:25:49 PM PDT 24
Peak memory	218752 kb
Host	smart-2a7af7ba-1c0c-4235-8c46-443a8175a971
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=193938143 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_security_escalation.193938143
Directory	/workspace/22.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/22.lc_ctrl_smoke.1618818625
Short name	T719
Test name
Test status
Simulation time	49487373 ps
CPU time	2.87 seconds
Started	Jun 09 02:25:29 PM PDT 24
Finished	Jun 09 02:25:32 PM PDT 24
Peak memory	215020 kb
Host	smart-d256098f-c1cb-461a-be6d-85ca194703e9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1618818625 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_smoke.1618818625
Directory	/workspace/22.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/22.lc_ctrl_state_failure.2137682416
Short name	T90
Test name
Test status
Simulation time	1119884469 ps
CPU time	27.79 seconds
Started	Jun 09 02:25:26 PM PDT 24
Finished	Jun 09 02:25:54 PM PDT 24
Peak memory	251424 kb
Host	smart-eb8fa958-e875-460b-a41c-dc474586c832
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2137682416 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_failure.2137682416
Directory	/workspace/22.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/22.lc_ctrl_state_post_trans.1776897850
Short name	T359
Test name
Test status
Simulation time	246062408 ps
CPU time	6.32 seconds
Started	Jun 09 02:25:28 PM PDT 24
Finished	Jun 09 02:25:35 PM PDT 24
Peak memory	247656 kb
Host	smart-34ea2a13-ed76-40bd-bf73-46a52d2b077d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1776897850 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_post_trans.1776897850
Directory	/workspace/22.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/22.lc_ctrl_stress_all.2789413786
Short name	T23
Test name
Test status
Simulation time	986680025 ps
CPU time	45.82 seconds
Started	Jun 09 02:25:26 PM PDT 24
Finished	Jun 09 02:26:12 PM PDT 24
Peak memory	267128 kb
Host	smart-d274e989-aa79-4ba9-af9e-d239895b4915
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789413786 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_stress_all.2789413786
Directory	/workspace/22.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/22.lc_ctrl_stress_all_with_rand_reset.3071724315
Short name	T20
Test name
Test status
Simulation time	173956427582 ps
CPU time	346.43 seconds
Started	Jun 09 02:25:34 PM PDT 24
Finished	Jun 09 02:31:21 PM PDT 24
Peak memory	284364 kb
Host	smart-2267d0a5-00b3-4f53-9aec-e32d0b26f4ea
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=3071724315 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_stress_all_with_rand_reset.3071724315
Directory	/workspace/22.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/22.lc_ctrl_volatile_unlock_smoke.1143824474
Short name	T792
Test name
Test status
Simulation time	13894156 ps
CPU time	0.8 seconds
Started	Jun 09 02:25:25 PM PDT 24
Finished	Jun 09 02:25:26 PM PDT 24
Peak memory	209332 kb
Host	smart-6087125b-9ce4-4a32-8244-c21a3f032a18
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143824474 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_c trl_volatile_unlock_smoke.1143824474
Directory	/workspace/22.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/23.lc_ctrl_alert_test.318855084
Short name	T493
Test name
Test status
Simulation time	39508825 ps
CPU time	1.16 seconds
Started	Jun 09 02:25:37 PM PDT 24
Finished	Jun 09 02:25:39 PM PDT 24
Peak memory	209376 kb
Host	smart-5c6f58e8-ee67-497e-a779-3275f1a8da57
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318855084 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_alert_test.318855084
Directory	/workspace/23.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/23.lc_ctrl_errors.3570528018
Short name	T489
Test name
Test status
Simulation time	1644953869 ps
CPU time	11.97 seconds
Started	Jun 09 02:25:43 PM PDT 24
Finished	Jun 09 02:25:56 PM PDT 24
Peak memory	218680 kb
Host	smart-f0a68cd2-09c4-4426-b506-1c9673a0a159
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3570528018 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_errors.3570528018
Directory	/workspace/23.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/23.lc_ctrl_jtag_access.2446928670
Short name	T9
Test name
Test status
Simulation time	1395118426 ps
CPU time	8.5 seconds
Started	Jun 09 02:25:36 PM PDT 24
Finished	Jun 09 02:25:45 PM PDT 24
Peak memory	217568 kb
Host	smart-7d6f63e2-2a64-49dd-8ccd-7c0ee302d1ea
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446928670 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_jtag_access.2446928670
Directory	/workspace/23.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/23.lc_ctrl_prog_failure.3641035946
Short name	T3
Test name
Test status
Simulation time	175572808 ps
CPU time	2.11 seconds
Started	Jun 09 02:25:44 PM PDT 24
Finished	Jun 09 02:25:46 PM PDT 24
Peak memory	218676 kb
Host	smart-98c7d602-3e4b-41a2-ae93-522591768e5a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3641035946 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_prog_failure.3641035946
Directory	/workspace/23.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/23.lc_ctrl_sec_mubi.2669626857
Short name	T842
Test name
Test status
Simulation time	430174457 ps
CPU time	17.51 seconds
Started	Jun 09 02:25:39 PM PDT 24
Finished	Jun 09 02:25:57 PM PDT 24
Peak memory	219484 kb
Host	smart-48668555-60eb-4caf-b062-ba45adef7104
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669626857 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_mubi.2669626857
Directory	/workspace/23.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/23.lc_ctrl_sec_token_digest.1467759588
Short name	T397
Test name
Test status
Simulation time	1672216515 ps
CPU time	7.76 seconds
Started	Jun 09 02:25:30 PM PDT 24
Finished	Jun 09 02:25:38 PM PDT 24
Peak memory	218720 kb
Host	smart-f89f3bb2-fbde-4ab6-b7bf-0f10fcf4b1e8
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467759588 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_d igest.1467759588
Directory	/workspace/23.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/23.lc_ctrl_sec_token_mux.626167365
Short name	T50
Test name
Test status
Simulation time	317916921 ps
CPU time	7.62 seconds
Started	Jun 09 02:25:28 PM PDT 24
Finished	Jun 09 02:25:36 PM PDT 24
Peak memory	218716 kb
Host	smart-e09842c9-8d6e-4131-9397-16da8352bc69
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626167365 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_mux.626167365
Directory	/workspace/23.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/23.lc_ctrl_security_escalation.622118494
Short name	T562
Test name
Test status
Simulation time	409933767 ps
CPU time	7.11 seconds
Started	Jun 09 02:25:41 PM PDT 24
Finished	Jun 09 02:25:49 PM PDT 24
Peak memory	225188 kb
Host	smart-d6416db9-f7f5-4990-b05d-765bf6140459
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=622118494 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_security_escalation.622118494
Directory	/workspace/23.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/23.lc_ctrl_smoke.1456474834
Short name	T156
Test name
Test status
Simulation time	158497618 ps
CPU time	1.71 seconds
Started	Jun 09 02:25:24 PM PDT 24
Finished	Jun 09 02:25:27 PM PDT 24
Peak memory	214580 kb
Host	smart-0f5152d1-8e4e-4887-8347-f83c3c174b97
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1456474834 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_smoke.1456474834
Directory	/workspace/23.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/23.lc_ctrl_state_failure.3768432275
Short name	T687
Test name
Test status
Simulation time	1889431668 ps
CPU time	31.33 seconds
Started	Jun 09 02:25:27 PM PDT 24
Finished	Jun 09 02:25:58 PM PDT 24
Peak memory	251432 kb
Host	smart-94e54bfa-d62b-4e19-8236-c3d0fda68942
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3768432275 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_failure.3768432275
Directory	/workspace/23.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/23.lc_ctrl_state_post_trans.1772284475
Short name	T820
Test name
Test status
Simulation time	112010960 ps
CPU time	2.66 seconds
Started	Jun 09 02:25:24 PM PDT 24
Finished	Jun 09 02:25:28 PM PDT 24
Peak memory	218664 kb
Host	smart-a6398992-9c97-4917-89be-c608b32b7364
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1772284475 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_post_trans.1772284475
Directory	/workspace/23.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/23.lc_ctrl_stress_all.494260348
Short name	T661
Test name
Test status
Simulation time	10434960111 ps
CPU time	75.52 seconds
Started	Jun 09 02:25:30 PM PDT 24
Finished	Jun 09 02:26:46 PM PDT 24
Peak memory	235420 kb
Host	smart-bf9859fb-fae7-40df-b92d-9c551f8285f9
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494260348 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_ TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_stress_all.494260348
Directory	/workspace/23.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/23.lc_ctrl_volatile_unlock_smoke.3682502216
Short name	T269
Test name
Test status
Simulation time	75955019 ps
CPU time	0.82 seconds
Started	Jun 09 02:25:41 PM PDT 24
Finished	Jun 09 02:25:43 PM PDT 24
Peak memory	208748 kb
Host	smart-459b1ced-ef64-4df5-9d70-8f2536cfecdb
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682502216 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_c trl_volatile_unlock_smoke.3682502216
Directory	/workspace/23.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/24.lc_ctrl_alert_test.4154828799
Short name	T341
Test name
Test status
Simulation time	45467178 ps
CPU time	0.94 seconds
Started	Jun 09 02:25:28 PM PDT 24
Finished	Jun 09 02:25:30 PM PDT 24
Peak memory	209504 kb
Host	smart-78229e4f-8b49-4e4a-87d0-40f9310b8dac
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154828799 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_alert_test.4154828799
Directory	/workspace/24.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/24.lc_ctrl_errors.2428039642
Short name	T320
Test name
Test status
Simulation time	362904977 ps
CPU time	10.35 seconds
Started	Jun 09 02:25:31 PM PDT 24
Finished	Jun 09 02:25:41 PM PDT 24
Peak memory	218744 kb
Host	smart-9cc0f222-8300-4e06-ae01-bc457c2638e6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2428039642 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_errors.2428039642
Directory	/workspace/24.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/24.lc_ctrl_jtag_access.2634127318
Short name	T394
Test name
Test status
Simulation time	721791278 ps
CPU time	3.44 seconds
Started	Jun 09 02:25:29 PM PDT 24
Finished	Jun 09 02:25:33 PM PDT 24
Peak memory	217540 kb
Host	smart-8f1adbb0-9bf7-4116-8159-654854a47436
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634127318 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_jtag_access.2634127318
Directory	/workspace/24.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/24.lc_ctrl_prog_failure.1081270542
Short name	T823
Test name
Test status
Simulation time	209528757 ps
CPU time	2.57 seconds
Started	Jun 09 02:25:27 PM PDT 24
Finished	Jun 09 02:25:30 PM PDT 24
Peak memory	218636 kb
Host	smart-a35cc6cd-cff5-46ea-9171-879f4403ded0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1081270542 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_prog_failure.1081270542
Directory	/workspace/24.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/24.lc_ctrl_sec_mubi.1173343853
Short name	T441
Test name
Test status
Simulation time	809666289 ps
CPU time	17.49 seconds
Started	Jun 09 02:25:30 PM PDT 24
Finished	Jun 09 02:25:48 PM PDT 24
Peak memory	219468 kb
Host	smart-c874ce38-3cb2-42bd-a868-7b25f203dc3d
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173343853 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_mubi.1173343853
Directory	/workspace/24.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/24.lc_ctrl_sec_token_digest.3008586540
Short name	T460
Test name
Test status
Simulation time	375984160 ps
CPU time	12.94 seconds
Started	Jun 09 02:25:29 PM PDT 24
Finished	Jun 09 02:25:42 PM PDT 24
Peak memory	218732 kb
Host	smart-f2f996af-0d71-485e-944e-96933ad8e207
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008586540 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_d igest.3008586540
Directory	/workspace/24.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/24.lc_ctrl_sec_token_mux.677357644
Short name	T733
Test name
Test status
Simulation time	1145910470 ps
CPU time	19.45 seconds
Started	Jun 09 02:25:28 PM PDT 24
Finished	Jun 09 02:25:48 PM PDT 24
Peak memory	226528 kb
Host	smart-e0116295-5644-4517-9f31-8fea667f61b2
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677357644 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_mux.677357644
Directory	/workspace/24.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/24.lc_ctrl_security_escalation.3792394462
Short name	T668
Test name
Test status
Simulation time	1368151568 ps
CPU time	8.59 seconds
Started	Jun 09 02:25:31 PM PDT 24
Finished	Jun 09 02:25:40 PM PDT 24
Peak memory	225424 kb
Host	smart-f6795b8f-3836-4b34-9175-27884f5a6aac
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3792394462 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_security_escalation.3792394462
Directory	/workspace/24.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/24.lc_ctrl_smoke.73302217
Short name	T347
Test name
Test status
Simulation time	29435376 ps
CPU time	1.84 seconds
Started	Jun 09 02:25:34 PM PDT 24
Finished	Jun 09 02:25:36 PM PDT 24
Peak memory	218252 kb
Host	smart-854f5503-ed50-4a5c-87d7-c5ff2419e44b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=73302217 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_smoke.73302217
Directory	/workspace/24.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/24.lc_ctrl_state_failure.3426711821
Short name	T314
Test name
Test status
Simulation time	1082513661 ps
CPU time	33.39 seconds
Started	Jun 09 02:25:44 PM PDT 24
Finished	Jun 09 02:26:18 PM PDT 24
Peak memory	251424 kb
Host	smart-b6370605-e6a8-456b-b846-fddfe439aa4f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3426711821 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_failure.3426711821
Directory	/workspace/24.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/24.lc_ctrl_state_post_trans.4079379315
Short name	T319
Test name
Test status
Simulation time	77926373 ps
CPU time	7.39 seconds
Started	Jun 09 02:25:27 PM PDT 24
Finished	Jun 09 02:25:35 PM PDT 24
Peak memory	251424 kb
Host	smart-a2a91e20-d567-4756-95ff-41ec7d1ee4fc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4079379315 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_post_trans.4079379315
Directory	/workspace/24.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/24.lc_ctrl_stress_all.228799178
Short name	T212
Test name
Test status
Simulation time	9694640497 ps
CPU time	64.86 seconds
Started	Jun 09 02:25:30 PM PDT 24
Finished	Jun 09 02:26:35 PM PDT 24
Peak memory	235380 kb
Host	smart-50c4cddd-6391-4427-b0fa-a0d454324467
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228799178 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_ TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_stress_all.228799178
Directory	/workspace/24.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/24.lc_ctrl_volatile_unlock_smoke.4074984081
Short name	T679
Test name
Test status
Simulation time	14437753 ps
CPU time	1.02 seconds
Started	Jun 09 02:25:35 PM PDT 24
Finished	Jun 09 02:25:37 PM PDT 24
Peak memory	209640 kb
Host	smart-20cf6e64-3678-478a-b9ca-b3db052c618c
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074984081 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_c trl_volatile_unlock_smoke.4074984081
Directory	/workspace/24.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/25.lc_ctrl_alert_test.3551707433
Short name	T367
Test name
Test status
Simulation time	79639039 ps
CPU time	1.16 seconds
Started	Jun 09 02:25:43 PM PDT 24
Finished	Jun 09 02:25:44 PM PDT 24
Peak memory	209432 kb
Host	smart-1b68b57a-6a3d-4e97-9769-e301bdedb9d4
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551707433 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_alert_test.3551707433
Directory	/workspace/25.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/25.lc_ctrl_errors.1659918878
Short name	T261
Test name
Test status
Simulation time	924772594 ps
CPU time	21.98 seconds
Started	Jun 09 02:25:34 PM PDT 24
Finished	Jun 09 02:25:56 PM PDT 24
Peak memory	218464 kb
Host	smart-53c50b42-a674-4ddd-a921-b6303c943710
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1659918878 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_errors.1659918878
Directory	/workspace/25.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/25.lc_ctrl_jtag_access.892060336
Short name	T338
Test name
Test status
Simulation time	126665561 ps
CPU time	1.31 seconds
Started	Jun 09 02:25:37 PM PDT 24
Finished	Jun 09 02:25:39 PM PDT 24
Peak memory	217452 kb
Host	smart-2fb5695b-30ed-45bb-ba20-ef6888ff54d3
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892060336 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_jtag_access.892060336
Directory	/workspace/25.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/25.lc_ctrl_prog_failure.2990424738
Short name	T704
Test name
Test status
Simulation time	398265591 ps
CPU time	4.11 seconds
Started	Jun 09 02:25:33 PM PDT 24
Finished	Jun 09 02:25:37 PM PDT 24
Peak memory	218680 kb
Host	smart-2d6a9d33-a2d7-416a-8d06-387d25b3efcc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2990424738 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_prog_failure.2990424738
Directory	/workspace/25.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/25.lc_ctrl_sec_mubi.3797596604
Short name	T479
Test name
Test status
Simulation time	1435691104 ps
CPU time	16.53 seconds
Started	Jun 09 02:25:36 PM PDT 24
Finished	Jun 09 02:25:54 PM PDT 24
Peak memory	219392 kb
Host	smart-b51cf778-3db4-4b93-82f0-81815d1e8516
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797596604 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_mubi.3797596604
Directory	/workspace/25.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/25.lc_ctrl_sec_token_digest.4085675529
Short name	T581
Test name
Test status
Simulation time	579104131 ps
CPU time	11.09 seconds
Started	Jun 09 02:25:33 PM PDT 24
Finished	Jun 09 02:25:44 PM PDT 24
Peak memory	226348 kb
Host	smart-12bfdea5-9e89-4e52-a40e-dc4b9b0afbcd
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085675529 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_d igest.4085675529
Directory	/workspace/25.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/25.lc_ctrl_sec_token_mux.157303347
Short name	T729
Test name
Test status
Simulation time	284472398 ps
CPU time	11.31 seconds
Started	Jun 09 02:25:32 PM PDT 24
Finished	Jun 09 02:25:43 PM PDT 24
Peak memory	218736 kb
Host	smart-554a6cf8-2952-4d06-a49f-e08fa219da6e
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157303347 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_mux.157303347
Directory	/workspace/25.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/25.lc_ctrl_security_escalation.2529708239
Short name	T730
Test name
Test status
Simulation time	420076995 ps
CPU time	7.96 seconds
Started	Jun 09 02:25:33 PM PDT 24
Finished	Jun 09 02:25:41 PM PDT 24
Peak memory	226552 kb
Host	smart-ba959f37-8756-4ff8-9a32-feb85fc9b939
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2529708239 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_security_escalation.2529708239
Directory	/workspace/25.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/25.lc_ctrl_smoke.1659882176
Short name	T81
Test name
Test status
Simulation time	23745323 ps
CPU time	1.69 seconds
Started	Jun 09 02:25:28 PM PDT 24
Finished	Jun 09 02:25:31 PM PDT 24
Peak memory	222568 kb
Host	smart-704213d1-9a9d-4fb6-8d2f-2b0ff89225a0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1659882176 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_smoke.1659882176
Directory	/workspace/25.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/25.lc_ctrl_state_failure.2430211678
Short name	T565
Test name
Test status
Simulation time	3196002609 ps
CPU time	17.64 seconds
Started	Jun 09 02:25:27 PM PDT 24
Finished	Jun 09 02:25:45 PM PDT 24
Peak memory	251484 kb
Host	smart-7db30fb6-da0d-4e01-93da-cb3200974e88
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2430211678 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_failure.2430211678
Directory	/workspace/25.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/25.lc_ctrl_state_post_trans.2915883034
Short name	T221
Test name
Test status
Simulation time	47315699 ps
CPU time	9.79 seconds
Started	Jun 09 02:25:27 PM PDT 24
Finished	Jun 09 02:25:37 PM PDT 24
Peak memory	251416 kb
Host	smart-ee14857b-6c38-411a-b543-63a4d35ee850
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2915883034 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_post_trans.2915883034
Directory	/workspace/25.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/25.lc_ctrl_stress_all.4075956839
Short name	T109
Test name
Test status
Simulation time	11024504780 ps
CPU time	185.26 seconds
Started	Jun 09 02:25:41 PM PDT 24
Finished	Jun 09 02:28:47 PM PDT 24
Peak memory	280096 kb
Host	smart-65f00243-89a9-49d2-becb-9ecd44276e56
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075956839 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_stress_all.4075956839
Directory	/workspace/25.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/25.lc_ctrl_volatile_unlock_smoke.4033638828
Short name	T335
Test name
Test status
Simulation time	16523375 ps
CPU time	1.12 seconds
Started	Jun 09 02:25:28 PM PDT 24
Finished	Jun 09 02:25:29 PM PDT 24
Peak memory	212352 kb
Host	smart-5ea4790d-47ca-4c07-9bc1-8159d2a1b991
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033638828 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_c trl_volatile_unlock_smoke.4033638828
Directory	/workspace/25.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/26.lc_ctrl_alert_test.17245792
Short name	T102
Test name
Test status
Simulation time	22997932 ps
CPU time	0.96 seconds
Started	Jun 09 02:25:34 PM PDT 24
Finished	Jun 09 02:25:35 PM PDT 24
Peak memory	209248 kb
Host	smart-4f6b7f49-add4-4f3c-863b-7e527869e3df
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17245792 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_alert_test.17245792
Directory	/workspace/26.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/26.lc_ctrl_errors.724778741
Short name	T429
Test name
Test status
Simulation time	527635123 ps
CPU time	12.99 seconds
Started	Jun 09 02:25:32 PM PDT 24
Finished	Jun 09 02:25:46 PM PDT 24
Peak memory	218744 kb
Host	smart-0884b865-42c6-4fed-bd26-c03383b99a33
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=724778741 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_errors.724778741
Directory	/workspace/26.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/26.lc_ctrl_jtag_access.2704487547
Short name	T720
Test name
Test status
Simulation time	1024996346 ps
CPU time	6.36 seconds
Started	Jun 09 02:25:31 PM PDT 24
Finished	Jun 09 02:25:38 PM PDT 24
Peak memory	217852 kb
Host	smart-23068f19-1677-4852-af43-eada368144d1
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704487547 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_jtag_access.2704487547
Directory	/workspace/26.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/26.lc_ctrl_prog_failure.1046427703
Short name	T66
Test name
Test status
Simulation time	144975175 ps
CPU time	2.07 seconds
Started	Jun 09 02:25:34 PM PDT 24
Finished	Jun 09 02:25:37 PM PDT 24
Peak memory	218676 kb
Host	smart-ae57c226-f084-4c87-a2c9-a3cc4b30aa2a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1046427703 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_prog_failure.1046427703
Directory	/workspace/26.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/26.lc_ctrl_sec_mubi.1254734162
Short name	T89
Test name
Test status
Simulation time	649622049 ps
CPU time	13.22 seconds
Started	Jun 09 02:25:41 PM PDT 24
Finished	Jun 09 02:25:54 PM PDT 24
Peak memory	226556 kb
Host	smart-8823d862-6983-4be4-bae9-44243494075a
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254734162 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_mubi.1254734162
Directory	/workspace/26.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/26.lc_ctrl_sec_token_digest.384635215
Short name	T778
Test name
Test status
Simulation time	5565300804 ps
CPU time	12.3 seconds
Started	Jun 09 02:25:32 PM PDT 24
Finished	Jun 09 02:25:44 PM PDT 24
Peak memory	226596 kb
Host	smart-9ac29970-772a-4d1b-80cd-d0ad46701b08
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384635215 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_di gest.384635215
Directory	/workspace/26.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/26.lc_ctrl_sec_token_mux.219966903
Short name	T252
Test name
Test status
Simulation time	681946481 ps
CPU time	12.26 seconds
Started	Jun 09 02:25:31 PM PDT 24
Finished	Jun 09 02:25:44 PM PDT 24
Peak memory	218652 kb
Host	smart-3dd4538e-1f3a-4b5e-8a46-d8e311ab593b
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219966903 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_mux.219966903
Directory	/workspace/26.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/26.lc_ctrl_security_escalation.1704833216
Short name	T681
Test name
Test status
Simulation time	342416136 ps
CPU time	8.45 seconds
Started	Jun 09 02:25:43 PM PDT 24
Finished	Jun 09 02:25:52 PM PDT 24
Peak memory	226532 kb
Host	smart-eb867240-7956-469a-95d2-43808a86ea89
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1704833216 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_security_escalation.1704833216
Directory	/workspace/26.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/26.lc_ctrl_smoke.1640712405
Short name	T620
Test name
Test status
Simulation time	153173011 ps
CPU time	2.27 seconds
Started	Jun 09 02:25:36 PM PDT 24
Finished	Jun 09 02:25:38 PM PDT 24
Peak memory	214656 kb
Host	smart-02abfc6f-fd21-46d6-9da7-f478e05d60f2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1640712405 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_smoke.1640712405
Directory	/workspace/26.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/26.lc_ctrl_state_failure.3404973162
Short name	T692
Test name
Test status
Simulation time	401055761 ps
CPU time	19.58 seconds
Started	Jun 09 02:25:32 PM PDT 24
Finished	Jun 09 02:25:52 PM PDT 24
Peak memory	251380 kb
Host	smart-7018b334-43bb-4b31-802a-1a5fc589eeba
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3404973162 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_failure.3404973162
Directory	/workspace/26.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/26.lc_ctrl_state_post_trans.4147558704
Short name	T497
Test name
Test status
Simulation time	87014971 ps
CPU time	3.13 seconds
Started	Jun 09 02:25:43 PM PDT 24
Finished	Jun 09 02:25:47 PM PDT 24
Peak memory	222968 kb
Host	smart-4cc28ffb-c005-413a-aed1-96f307b5cb40
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4147558704 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_post_trans.4147558704
Directory	/workspace/26.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/26.lc_ctrl_stress_all.1479868329
Short name	T330
Test name
Test status
Simulation time	21190177214 ps
CPU time	170.33 seconds
Started	Jun 09 02:25:34 PM PDT 24
Finished	Jun 09 02:28:25 PM PDT 24
Peak memory	252840 kb
Host	smart-97617ac1-017d-4425-850c-32856593779c
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479868329 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_stress_all.1479868329
Directory	/workspace/26.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/26.lc_ctrl_volatile_unlock_smoke.3289845872
Short name	T296
Test name
Test status
Simulation time	49453678 ps
CPU time	1.07 seconds
Started	Jun 09 02:25:33 PM PDT 24
Finished	Jun 09 02:25:34 PM PDT 24
Peak memory	212468 kb
Host	smart-4310b65c-ad10-45b1-9ec9-d3b308ec4de0
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289845872 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_c trl_volatile_unlock_smoke.3289845872
Directory	/workspace/26.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/27.lc_ctrl_alert_test.1243677770
Short name	T434
Test name
Test status
Simulation time	47711411 ps
CPU time	0.81 seconds
Started	Jun 09 02:25:45 PM PDT 24
Finished	Jun 09 02:25:47 PM PDT 24
Peak memory	209272 kb
Host	smart-63bc83a0-122d-4b00-bb70-b8233d604631
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243677770 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_alert_test.1243677770
Directory	/workspace/27.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/27.lc_ctrl_errors.1936275313
Short name	T507
Test name
Test status
Simulation time	1109397544 ps
CPU time	13.04 seconds
Started	Jun 09 02:25:33 PM PDT 24
Finished	Jun 09 02:25:46 PM PDT 24
Peak memory	218696 kb
Host	smart-cf46cf0f-4cb2-48f2-824b-77cfb3457a11
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1936275313 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_errors.1936275313
Directory	/workspace/27.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/27.lc_ctrl_jtag_access.2184159250
Short name	T656
Test name
Test status
Simulation time	285788381 ps
CPU time	4.19 seconds
Started	Jun 09 02:25:34 PM PDT 24
Finished	Jun 09 02:25:39 PM PDT 24
Peak memory	217580 kb
Host	smart-e6758ce1-03a6-4449-9882-b3b0e62d0593
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184159250 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_jtag_access.2184159250
Directory	/workspace/27.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/27.lc_ctrl_prog_failure.3438576178
Short name	T836
Test name
Test status
Simulation time	196890257 ps
CPU time	3.28 seconds
Started	Jun 09 02:25:45 PM PDT 24
Finished	Jun 09 02:25:49 PM PDT 24
Peak memory	218680 kb
Host	smart-202b5a91-3084-44fa-8d16-01afb305310e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3438576178 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_prog_failure.3438576178
Directory	/workspace/27.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/27.lc_ctrl_sec_mubi.2979661999
Short name	T789
Test name
Test status
Simulation time	872098009 ps
CPU time	15.56 seconds
Started	Jun 09 02:25:31 PM PDT 24
Finished	Jun 09 02:25:47 PM PDT 24
Peak memory	219416 kb
Host	smart-1ff16e31-907b-492f-aaff-3a8931e93445
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979661999 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_mubi.2979661999
Directory	/workspace/27.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/27.lc_ctrl_sec_token_digest.2238588767
Short name	T815
Test name
Test status
Simulation time	211690143 ps
CPU time	7.69 seconds
Started	Jun 09 02:25:39 PM PDT 24
Finished	Jun 09 02:25:47 PM PDT 24
Peak memory	226556 kb
Host	smart-dcba03af-9390-4def-8a04-fc0b95db03b0
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238588767 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_d igest.2238588767
Directory	/workspace/27.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/27.lc_ctrl_sec_token_mux.3347584208
Short name	T635
Test name
Test status
Simulation time	290221695 ps
CPU time	8.88 seconds
Started	Jun 09 02:25:35 PM PDT 24
Finished	Jun 09 02:25:44 PM PDT 24
Peak memory	218720 kb
Host	smart-5ec223f6-5a3b-4df0-9b84-c1a7b7711b93
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347584208 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_mux. 3347584208
Directory	/workspace/27.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/27.lc_ctrl_security_escalation.1230875050
Short name	T422
Test name
Test status
Simulation time	264313507 ps
CPU time	8.75 seconds
Started	Jun 09 02:25:45 PM PDT 24
Finished	Jun 09 02:25:54 PM PDT 24
Peak memory	226152 kb
Host	smart-d4cabc8a-18b0-43d6-b6f7-400fd54b1029
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1230875050 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_security_escalation.1230875050
Directory	/workspace/27.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/27.lc_ctrl_smoke.2683914826
Short name	T556
Test name
Test status
Simulation time	108530297 ps
CPU time	2.47 seconds
Started	Jun 09 02:25:39 PM PDT 24
Finished	Jun 09 02:25:42 PM PDT 24
Peak memory	214904 kb
Host	smart-4b8d7114-8ada-4266-8ba8-f60b2d93d96d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2683914826 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_smoke.2683914826
Directory	/workspace/27.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/27.lc_ctrl_state_failure.3594634231
Short name	T739
Test name
Test status
Simulation time	228794239 ps
CPU time	25.91 seconds
Started	Jun 09 02:25:32 PM PDT 24
Finished	Jun 09 02:25:58 PM PDT 24
Peak memory	251416 kb
Host	smart-a87ab6af-85cc-46a5-8de4-b15727ea4489
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3594634231 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_failure.3594634231
Directory	/workspace/27.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/27.lc_ctrl_state_post_trans.493934936
Short name	T648
Test name
Test status
Simulation time	246050161 ps
CPU time	6.26 seconds
Started	Jun 09 02:25:36 PM PDT 24
Finished	Jun 09 02:25:43 PM PDT 24
Peak memory	250956 kb
Host	smart-05b08bf4-b1c3-40a1-881e-b3fd4375d32a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=493934936 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_post_trans.493934936
Directory	/workspace/27.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/27.lc_ctrl_stress_all.2163251555
Short name	T316
Test name
Test status
Simulation time	4916502600 ps
CPU time	31.79 seconds
Started	Jun 09 02:25:34 PM PDT 24
Finished	Jun 09 02:26:06 PM PDT 24
Peak memory	226592 kb
Host	smart-de180224-24b8-45eb-a628-cbd3f50eb937
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163251555 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_stress_all.2163251555
Directory	/workspace/27.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/28.lc_ctrl_alert_test.3122710958
Short name	T583
Test name
Test status
Simulation time	105932364 ps
CPU time	0.87 seconds
Started	Jun 09 02:25:37 PM PDT 24
Finished	Jun 09 02:25:38 PM PDT 24
Peak memory	209452 kb
Host	smart-cbca59bf-efec-4dc5-a3f9-7c87407f12cd
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122710958 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_alert_test.3122710958
Directory	/workspace/28.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/28.lc_ctrl_jtag_access.725635804
Short name	T743
Test name
Test status
Simulation time	150576845 ps
CPU time	2.36 seconds
Started	Jun 09 02:25:38 PM PDT 24
Finished	Jun 09 02:25:41 PM PDT 24
Peak memory	217672 kb
Host	smart-fb5ab29d-8f2d-41de-bdb3-07ba54beefae
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725635804 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_jtag_access.725635804
Directory	/workspace/28.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/28.lc_ctrl_prog_failure.2548426801
Short name	T544
Test name
Test status
Simulation time	142113971 ps
CPU time	2.61 seconds
Started	Jun 09 02:25:36 PM PDT 24
Finished	Jun 09 02:25:39 PM PDT 24
Peak memory	218676 kb
Host	smart-fc78101c-817b-47cb-8f2d-6df787e79725
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2548426801 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_prog_failure.2548426801
Directory	/workspace/28.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/28.lc_ctrl_sec_mubi.2092928493
Short name	T642
Test name
Test status
Simulation time	638213076 ps
CPU time	13.24 seconds
Started	Jun 09 02:25:34 PM PDT 24
Finished	Jun 09 02:25:48 PM PDT 24
Peak memory	226536 kb
Host	smart-03019253-8f06-4c9b-8a49-5ba36e6755de
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092928493 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_mubi.2092928493
Directory	/workspace/28.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/28.lc_ctrl_sec_token_digest.1903927238
Short name	T700
Test name
Test status
Simulation time	1198624234 ps
CPU time	10.89 seconds
Started	Jun 09 02:25:37 PM PDT 24
Finished	Jun 09 02:25:49 PM PDT 24
Peak memory	218724 kb
Host	smart-bfe946b6-bc92-4535-b2a6-748e8baa9038
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903927238 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_d igest.1903927238
Directory	/workspace/28.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/28.lc_ctrl_sec_token_mux.4012273823
Short name	T540
Test name
Test status
Simulation time	1388334787 ps
CPU time	14.9 seconds
Started	Jun 09 02:25:39 PM PDT 24
Finished	Jun 09 02:25:55 PM PDT 24
Peak memory	218460 kb
Host	smart-31ef8bb7-b27e-42ca-82aa-f69f155b2fe9
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012273823 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_mux. 4012273823
Directory	/workspace/28.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/28.lc_ctrl_security_escalation.2335639419
Short name	T688
Test name
Test status
Simulation time	3200454727 ps
CPU time	11.43 seconds
Started	Jun 09 02:25:37 PM PDT 24
Finished	Jun 09 02:25:49 PM PDT 24
Peak memory	226584 kb
Host	smart-62214aee-6cc2-4095-8353-0784ef5fea02
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2335639419 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_security_escalation.2335639419
Directory	/workspace/28.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/28.lc_ctrl_smoke.3576295506
Short name	T623
Test name
Test status
Simulation time	68017720 ps
CPU time	1.68 seconds
Started	Jun 09 02:25:34 PM PDT 24
Finished	Jun 09 02:25:36 PM PDT 24
Peak memory	218200 kb
Host	smart-d967b824-56ac-4eb6-81ea-e00443c6da45
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3576295506 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_smoke.3576295506
Directory	/workspace/28.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/28.lc_ctrl_state_failure.3151569890
Short name	T553
Test name
Test status
Simulation time	263879220 ps
CPU time	31.79 seconds
Started	Jun 09 02:25:39 PM PDT 24
Finished	Jun 09 02:26:11 PM PDT 24
Peak memory	251440 kb
Host	smart-86c3075b-6bdd-4329-8819-c03eab5bde5b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3151569890 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_failure.3151569890
Directory	/workspace/28.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/28.lc_ctrl_state_post_trans.3989312973
Short name	T796
Test name
Test status
Simulation time	103603422 ps
CPU time	8.42 seconds
Started	Jun 09 02:25:37 PM PDT 24
Finished	Jun 09 02:25:46 PM PDT 24
Peak memory	251412 kb
Host	smart-d21d1929-d0e8-4952-a049-df31627b4afe
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3989312973 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_post_trans.3989312973
Directory	/workspace/28.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/28.lc_ctrl_stress_all.255198634
Short name	T455
Test name
Test status
Simulation time	4293530382 ps
CPU time	163.15 seconds
Started	Jun 09 02:25:41 PM PDT 24
Finished	Jun 09 02:28:25 PM PDT 24
Peak memory	267852 kb
Host	smart-8bc1a384-1b07-473c-a0d7-35bf214ddfe8
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255198634 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_ TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_stress_all.255198634
Directory	/workspace/28.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/28.lc_ctrl_stress_all_with_rand_reset.2558082279
Short name	T147
Test name
Test status
Simulation time	189382150145 ps
CPU time	801.78 seconds
Started	Jun 09 02:25:37 PM PDT 24
Finished	Jun 09 02:39:00 PM PDT 24
Peak memory	497328 kb
Host	smart-f9f6609d-5fd2-4e30-bd64-be8cb613e527
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=2558082279 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_stress_all_with_rand_reset.2558082279
Directory	/workspace/28.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/28.lc_ctrl_volatile_unlock_smoke.2254440241
Short name	T290
Test name
Test status
Simulation time	30911371 ps
CPU time	0.85 seconds
Started	Jun 09 02:25:40 PM PDT 24
Finished	Jun 09 02:25:41 PM PDT 24
Peak memory	209320 kb
Host	smart-5be675e7-c59c-4a0a-ae60-5438a3bc9949
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254440241 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_c trl_volatile_unlock_smoke.2254440241
Directory	/workspace/28.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/29.lc_ctrl_alert_test.724079729
Short name	T570
Test name
Test status
Simulation time	55248408 ps
CPU time	0.93 seconds
Started	Jun 09 02:25:36 PM PDT 24
Finished	Jun 09 02:25:38 PM PDT 24
Peak memory	209532 kb
Host	smart-2126c454-4d86-40d4-8439-c76427823e45
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724079729 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_alert_test.724079729
Directory	/workspace/29.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/29.lc_ctrl_errors.2206750832
Short name	T563
Test name
Test status
Simulation time	264403774 ps
CPU time	9.06 seconds
Started	Jun 09 02:25:34 PM PDT 24
Finished	Jun 09 02:25:44 PM PDT 24
Peak memory	218680 kb
Host	smart-cc281650-ccd1-423d-a87f-651b8f768ed9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2206750832 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_errors.2206750832
Directory	/workspace/29.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/29.lc_ctrl_jtag_access.1050861530
Short name	T36
Test name
Test status
Simulation time	4621783568 ps
CPU time	7.14 seconds
Started	Jun 09 02:25:36 PM PDT 24
Finished	Jun 09 02:25:44 PM PDT 24
Peak memory	218264 kb
Host	smart-0c8038ca-edcd-46af-87a5-3646c0b53b40
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050861530 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_jtag_access.1050861530
Directory	/workspace/29.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/29.lc_ctrl_prog_failure.361268893
Short name	T663
Test name
Test status
Simulation time	71411195 ps
CPU time	1.48 seconds
Started	Jun 09 02:25:38 PM PDT 24
Finished	Jun 09 02:25:40 PM PDT 24
Peak memory	218696 kb
Host	smart-fb836c19-7a41-4d9e-bf6a-280d1ea43e31
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=361268893 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_prog_failure.361268893
Directory	/workspace/29.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/29.lc_ctrl_sec_mubi.312853097
Short name	T566
Test name
Test status
Simulation time	378426685 ps
CPU time	11.17 seconds
Started	Jun 09 02:25:45 PM PDT 24
Finished	Jun 09 02:25:57 PM PDT 24
Peak memory	218732 kb
Host	smart-b2f95235-7050-4c19-893f-eaaf5978b581
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312853097 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_mubi.312853097
Directory	/workspace/29.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/29.lc_ctrl_sec_token_digest.1227346665
Short name	T550
Test name
Test status
Simulation time	355416798 ps
CPU time	10.57 seconds
Started	Jun 09 02:25:45 PM PDT 24
Finished	Jun 09 02:25:56 PM PDT 24
Peak memory	218724 kb
Host	smart-055f2ad9-c57b-486d-a222-2be91a39034d
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227346665 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_d igest.1227346665
Directory	/workspace/29.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/29.lc_ctrl_sec_token_mux.3309383351
Short name	T812
Test name
Test status
Simulation time	253353622 ps
CPU time	10.78 seconds
Started	Jun 09 02:25:36 PM PDT 24
Finished	Jun 09 02:25:47 PM PDT 24
Peak memory	218752 kb
Host	smart-e4dad7f9-f8d0-477c-9b5d-afeea7d76e12
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309383351 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_mux. 3309383351
Directory	/workspace/29.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/29.lc_ctrl_security_escalation.419918277
Short name	T549
Test name
Test status
Simulation time	857186574 ps
CPU time	12.53 seconds
Started	Jun 09 02:25:35 PM PDT 24
Finished	Jun 09 02:25:48 PM PDT 24
Peak memory	226560 kb
Host	smart-bbd44190-7bfd-4d96-b295-e0a16b9b28de
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=419918277 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_security_escalation.419918277
Directory	/workspace/29.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/29.lc_ctrl_smoke.1742274534
Short name	T431
Test name
Test status
Simulation time	43249770 ps
CPU time	1.8 seconds
Started	Jun 09 02:25:41 PM PDT 24
Finished	Jun 09 02:25:43 PM PDT 24
Peak memory	218276 kb
Host	smart-7fbcdf23-7c1e-4a28-a43a-70ee2cc40cbb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1742274534 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_smoke.1742274534
Directory	/workspace/29.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/29.lc_ctrl_state_failure.3127702438
Short name	T691
Test name
Test status
Simulation time	541368639 ps
CPU time	30.52 seconds
Started	Jun 09 02:25:37 PM PDT 24
Finished	Jun 09 02:26:08 PM PDT 24
Peak memory	251416 kb
Host	smart-d81e2489-3a7f-4b25-8a73-3eb19424d14e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3127702438 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_failure.3127702438
Directory	/workspace/29.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/29.lc_ctrl_state_post_trans.3729300780
Short name	T225
Test name
Test status
Simulation time	73124120 ps
CPU time	8.44 seconds
Started	Jun 09 02:25:39 PM PDT 24
Finished	Jun 09 02:25:48 PM PDT 24
Peak memory	251412 kb
Host	smart-12ea20ef-f191-4305-816f-abd890ffdcd5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3729300780 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_post_trans.3729300780
Directory	/workspace/29.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/29.lc_ctrl_stress_all.3058958223
Short name	T490
Test name
Test status
Simulation time	61450746832 ps
CPU time	423.37 seconds
Started	Jun 09 02:25:39 PM PDT 24
Finished	Jun 09 02:32:43 PM PDT 24
Peak memory	221448 kb
Host	smart-67656ece-eacc-464e-9af8-3411fdeea6a9
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058958223 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_stress_all.3058958223
Directory	/workspace/29.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/29.lc_ctrl_stress_all_with_rand_reset.1131648197
Short name	T45
Test name
Test status
Simulation time	122229858616 ps
CPU time	4918.18 seconds
Started	Jun 09 02:25:38 PM PDT 24
Finished	Jun 09 03:47:38 PM PDT 24
Peak memory	956092 kb
Host	smart-70be5293-21ef-4542-a8db-a5bb22f2c364
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=1131648197 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_stress_all_with_rand_reset.1131648197
Directory	/workspace/29.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/29.lc_ctrl_volatile_unlock_smoke.3983892791
Short name	T303
Test name
Test status
Simulation time	14193055 ps
CPU time	1.03 seconds
Started	Jun 09 02:25:34 PM PDT 24
Finished	Jun 09 02:25:36 PM PDT 24
Peak memory	212368 kb
Host	smart-0f39441f-e7a4-4170-874b-2752af820054
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983892791 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_c trl_volatile_unlock_smoke.3983892791
Directory	/workspace/29.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/3.lc_ctrl_alert_test.4291250447
Short name	T306
Test name
Test status
Simulation time	90791628 ps
CPU time	0.99 seconds
Started	Jun 09 02:24:36 PM PDT 24
Finished	Jun 09 02:24:37 PM PDT 24
Peak memory	209540 kb
Host	smart-c90d9d09-2f34-4592-b66c-777dca34c6fe
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291250447 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_alert_test.4291250447
Directory	/workspace/3.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/3.lc_ctrl_errors.3223501626
Short name	T223
Test name
Test status
Simulation time	2790761488 ps
CPU time	10.51 seconds
Started	Jun 09 02:24:32 PM PDT 24
Finished	Jun 09 02:24:43 PM PDT 24
Peak memory	218724 kb
Host	smart-1c64c091-6181-424a-b9e2-34a58ff28b2a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3223501626 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_errors.3223501626
Directory	/workspace/3.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/3.lc_ctrl_jtag_access.1992223970
Short name	T514
Test name
Test status
Simulation time	852970832 ps
CPU time	5.51 seconds
Started	Jun 09 02:24:35 PM PDT 24
Finished	Jun 09 02:24:41 PM PDT 24
Peak memory	217856 kb
Host	smart-831cd7d0-5404-48d2-a9ac-bd4381d3ab88
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992223970 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_access.1992223970
Directory	/workspace/3.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/3.lc_ctrl_jtag_errors.4167621797
Short name	T260
Test name
Test status
Simulation time	1367708270 ps
CPU time	26.75 seconds
Started	Jun 09 02:24:24 PM PDT 24
Finished	Jun 09 02:24:51 PM PDT 24
Peak memory	226564 kb
Host	smart-4927346a-f2d5-4981-be54-31d4bd6fc0a6
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167621797 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_er rors.4167621797
Directory	/workspace/3.lc_ctrl_jtag_errors/latest

Test location	/workspace/coverage/default/3.lc_ctrl_jtag_priority.3727983630
Short name	T271
Test name
Test status
Simulation time	1988205903 ps
CPU time	18.78 seconds
Started	Jun 09 02:24:31 PM PDT 24
Finished	Jun 09 02:24:50 PM PDT 24
Peak memory	218144 kb
Host	smart-ae7a657e-ca9e-41de-b8e0-1018545e0102
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727983630 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_priority.3 727983630
Directory	/workspace/3.lc_ctrl_jtag_priority/latest

Test location	/workspace/coverage/default/3.lc_ctrl_jtag_prog_failure.2349644282
Short name	T599
Test name
Test status
Simulation time	1388061746 ps
CPU time	4.79 seconds
Started	Jun 09 02:24:28 PM PDT 24
Finished	Jun 09 02:24:33 PM PDT 24
Peak memory	223292 kb
Host	smart-120f02df-fb93-455e-9736-ddeb5f635560
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349644282 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag _prog_failure.2349644282
Directory	/workspace/3.lc_ctrl_jtag_prog_failure/latest

Test location	/workspace/coverage/default/3.lc_ctrl_jtag_regwen_during_op.2872457876
Short name	T73
Test name
Test status
Simulation time	3616360888 ps
CPU time	11.58 seconds
Started	Jun 09 02:24:34 PM PDT 24
Finished	Jun 09 02:24:46 PM PDT 24
Peak memory	218268 kb
Host	smart-fdfc4b0e-52d1-4a77-95de-d2607615d59e
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872457876 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_ jtag_regwen_during_op.2872457876
Directory	/workspace/3.lc_ctrl_jtag_regwen_during_op/latest

Test location	/workspace/coverage/default/3.lc_ctrl_jtag_smoke.1094150659
Short name	T554
Test name
Test status
Simulation time	290097236 ps
CPU time	8.29 seconds
Started	Jun 09 02:24:37 PM PDT 24
Finished	Jun 09 02:24:46 PM PDT 24
Peak memory	218212 kb
Host	smart-47ce2d79-3ccb-4360-8659-0b85222e913c
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094150659 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_smoke. 1094150659
Directory	/workspace/3.lc_ctrl_jtag_smoke/latest

Test location	/workspace/coverage/default/3.lc_ctrl_jtag_state_failure.3500112616
Short name	T825
Test name
Test status
Simulation time	1923841088 ps
CPU time	77.52 seconds
Started	Jun 09 02:24:32 PM PDT 24
Finished	Jun 09 02:25:50 PM PDT 24
Peak memory	267876 kb
Host	smart-51287efb-7d12-46a2-8db7-9110a14aa186
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500112616 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jta g_state_failure.3500112616
Directory	/workspace/3.lc_ctrl_jtag_state_failure/latest

Test location	/workspace/coverage/default/3.lc_ctrl_jtag_state_post_trans.1651114272
Short name	T407
Test name
Test status
Simulation time	4588092320 ps
CPU time	24.84 seconds
Started	Jun 09 02:24:36 PM PDT 24
Finished	Jun 09 02:25:01 PM PDT 24
Peak memory	251536 kb
Host	smart-790a2d63-afea-4cfe-980c-5de2ea8073ad
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651114272 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_ jtag_state_post_trans.1651114272
Directory	/workspace/3.lc_ctrl_jtag_state_post_trans/latest

Test location	/workspace/coverage/default/3.lc_ctrl_prog_failure.3633952077
Short name	T658
Test name
Test status
Simulation time	242565432 ps
CPU time	3.16 seconds
Started	Jun 09 02:24:36 PM PDT 24
Finished	Jun 09 02:24:40 PM PDT 24
Peak memory	218708 kb
Host	smart-ca506670-aa36-47ec-ab3b-9d9f3d40493d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3633952077 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_prog_failure.3633952077
Directory	/workspace/3.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/3.lc_ctrl_regwen_during_op.366531796
Short name	T501
Test name
Test status
Simulation time	389569384 ps
CPU time	11.74 seconds
Started	Jun 09 02:24:27 PM PDT 24
Finished	Jun 09 02:24:39 PM PDT 24
Peak memory	215228 kb
Host	smart-e8555443-e664-4200-9a48-ad8c3a5276ef
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=366531796 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_regwen_during_op.366531796
Directory	/workspace/3.lc_ctrl_regwen_during_op/latest

Test location	/workspace/coverage/default/3.lc_ctrl_sec_cm.2337440181
Short name	T83
Test name
Test status
Simulation time	642903351 ps
CPU time	22.53 seconds
Started	Jun 09 02:24:37 PM PDT 24
Finished	Jun 09 02:25:00 PM PDT 24
Peak memory	284772 kb
Host	smart-136cb0da-d1d7-4bb8-b54a-b21e71630f9c
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337440181 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_cm.2337440181
Directory	/workspace/3.lc_ctrl_sec_cm/latest

Test location	/workspace/coverage/default/3.lc_ctrl_sec_mubi.2054589878
Short name	T873
Test name
Test status
Simulation time	975807187 ps
CPU time	15.04 seconds
Started	Jun 09 02:24:39 PM PDT 24
Finished	Jun 09 02:24:55 PM PDT 24
Peak memory	226656 kb
Host	smart-9aad3ca2-db4f-4f56-a3ac-69da1841cebf
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054589878 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_mubi.2054589878
Directory	/workspace/3.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/3.lc_ctrl_sec_token_digest.2983488604
Short name	T753
Test name
Test status
Simulation time	303392496 ps
CPU time	9.55 seconds
Started	Jun 09 02:24:41 PM PDT 24
Finished	Jun 09 02:24:51 PM PDT 24
Peak memory	218688 kb
Host	smart-06e88f2b-8fa9-40c9-bd0f-8aeb5924bbd0
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983488604 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_di gest.2983488604
Directory	/workspace/3.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/3.lc_ctrl_sec_token_mux.534638217
Short name	T573
Test name
Test status
Simulation time	518915872 ps
CPU time	6.9 seconds
Started	Jun 09 02:24:37 PM PDT 24
Finished	Jun 09 02:24:44 PM PDT 24
Peak memory	218724 kb
Host	smart-53c5f55c-2da0-4357-a3a6-fbe7ad15a10c
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534638217 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_mux.534638217
Directory	/workspace/3.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/3.lc_ctrl_security_escalation.834211679
Short name	T491
Test name
Test status
Simulation time	561368333 ps
CPU time	12.01 seconds
Started	Jun 09 02:24:29 PM PDT 24
Finished	Jun 09 02:24:42 PM PDT 24
Peak memory	218856 kb
Host	smart-5689dd5e-e41d-4ec4-a061-37945c3d0510
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=834211679 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_security_escalation.834211679
Directory	/workspace/3.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/3.lc_ctrl_smoke.1615913348
Short name	T2
Test name
Test status
Simulation time	46168170 ps
CPU time	1.35 seconds
Started	Jun 09 02:24:33 PM PDT 24
Finished	Jun 09 02:24:35 PM PDT 24
Peak memory	218304 kb
Host	smart-9d954d48-2972-4679-b0b5-e32ed0dc5695
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1615913348 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_smoke.1615913348
Directory	/workspace/3.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/3.lc_ctrl_state_failure.3898289781
Short name	T249
Test name
Test status
Simulation time	338166610 ps
CPU time	36.79 seconds
Started	Jun 09 02:24:36 PM PDT 24
Finished	Jun 09 02:25:13 PM PDT 24
Peak memory	251424 kb
Host	smart-9b4c510f-d591-49a7-83c1-794170c90d6d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3898289781 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_failure.3898289781
Directory	/workspace/3.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/3.lc_ctrl_state_post_trans.847556146
Short name	T437
Test name
Test status
Simulation time	151806891 ps
CPU time	10.38 seconds
Started	Jun 09 02:24:24 PM PDT 24
Finished	Jun 09 02:24:35 PM PDT 24
Peak memory	251420 kb
Host	smart-4404de79-989d-4c6f-bbff-2c418cb3cf3e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=847556146 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_post_trans.847556146
Directory	/workspace/3.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/3.lc_ctrl_stress_all.3049296217
Short name	T77
Test name
Test status
Simulation time	5393034878 ps
CPU time	201.42 seconds
Started	Jun 09 02:24:38 PM PDT 24
Finished	Jun 09 02:28:00 PM PDT 24
Peak memory	276060 kb
Host	smart-aa1de8ad-daa9-48ec-b14f-64759cb54f31
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049296217 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_stress_all.3049296217
Directory	/workspace/3.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/3.lc_ctrl_stress_all_with_rand_reset.704298223
Short name	T148
Test name
Test status
Simulation time	98034270023 ps
CPU time	1060.1 seconds
Started	Jun 09 02:24:36 PM PDT 24
Finished	Jun 09 02:42:16 PM PDT 24
Peak memory	497340 kb
Host	smart-e101d952-379d-4bac-87a4-f1557f31e8aa
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=704298223 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_stress_all_with_rand_reset.704298223
Directory	/workspace/3.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/3.lc_ctrl_volatile_unlock_smoke.3318039309
Short name	T376
Test name
Test status
Simulation time	13321109 ps
CPU time	1.12 seconds
Started	Jun 09 02:24:35 PM PDT 24
Finished	Jun 09 02:24:37 PM PDT 24
Peak memory	212392 kb
Host	smart-5a59e3cb-a62e-481d-b7b6-29e4a9787bf0
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318039309 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ct rl_volatile_unlock_smoke.3318039309
Directory	/workspace/3.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/30.lc_ctrl_alert_test.1965884448
Short name	T772
Test name
Test status
Simulation time	35138175 ps
CPU time	1.07 seconds
Started	Jun 09 02:25:43 PM PDT 24
Finished	Jun 09 02:25:45 PM PDT 24
Peak memory	209376 kb
Host	smart-f7664d54-02e5-436c-b974-415176e80d4f
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965884448 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_alert_test.1965884448
Directory	/workspace/30.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/30.lc_ctrl_errors.3614243376
Short name	T492
Test name
Test status
Simulation time	1164431488 ps
CPU time	22.74 seconds
Started	Jun 09 02:25:40 PM PDT 24
Finished	Jun 09 02:26:03 PM PDT 24
Peak memory	218684 kb
Host	smart-7b393dd2-9fc9-4ef0-9350-94c783443238
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3614243376 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_errors.3614243376
Directory	/workspace/30.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/30.lc_ctrl_jtag_access.4213433673
Short name	T783
Test name
Test status
Simulation time	940174493 ps
CPU time	7.32 seconds
Started	Jun 09 02:25:41 PM PDT 24
Finished	Jun 09 02:25:49 PM PDT 24
Peak memory	217860 kb
Host	smart-d9225eae-784c-4a8b-896f-d222517d5e0a
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213433673 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_jtag_access.4213433673
Directory	/workspace/30.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/30.lc_ctrl_prog_failure.552567361
Short name	T646
Test name
Test status
Simulation time	320123834 ps
CPU time	2.22 seconds
Started	Jun 09 02:25:41 PM PDT 24
Finished	Jun 09 02:25:44 PM PDT 24
Peak memory	218676 kb
Host	smart-d60ed273-f8d4-49dd-9d90-4f8c8f832f17
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=552567361 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_prog_failure.552567361
Directory	/workspace/30.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/30.lc_ctrl_sec_mubi.2261735928
Short name	T716
Test name
Test status
Simulation time	994464602 ps
CPU time	12.64 seconds
Started	Jun 09 02:25:41 PM PDT 24
Finished	Jun 09 02:25:54 PM PDT 24
Peak memory	219392 kb
Host	smart-e998d7ca-c4fa-450a-ac28-0d98125dac13
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261735928 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_mubi.2261735928
Directory	/workspace/30.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/30.lc_ctrl_sec_token_digest.2164568790
Short name	T463
Test name
Test status
Simulation time	197254985 ps
CPU time	8.58 seconds
Started	Jun 09 02:25:41 PM PDT 24
Finished	Jun 09 02:25:50 PM PDT 24
Peak memory	226516 kb
Host	smart-c387db0a-71d7-4512-893e-6cdee6f8b76e
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164568790 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_d igest.2164568790
Directory	/workspace/30.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/30.lc_ctrl_sec_token_mux.3756689468
Short name	T374
Test name
Test status
Simulation time	404530556 ps
CPU time	10.11 seconds
Started	Jun 09 02:25:42 PM PDT 24
Finished	Jun 09 02:25:53 PM PDT 24
Peak memory	218676 kb
Host	smart-e36e7312-b5aa-4fc1-8a2f-4f27af74757c
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756689468 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_mux. 3756689468
Directory	/workspace/30.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/30.lc_ctrl_security_escalation.2113903628
Short name	T209
Test name
Test status
Simulation time	1046518418 ps
CPU time	10.56 seconds
Started	Jun 09 02:25:41 PM PDT 24
Finished	Jun 09 02:25:52 PM PDT 24
Peak memory	226536 kb
Host	smart-d826485b-d2f8-4ea1-8377-c80205a2aa35
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2113903628 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_security_escalation.2113903628
Directory	/workspace/30.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/30.lc_ctrl_smoke.1721087599
Short name	T216
Test name
Test status
Simulation time	108972331 ps
CPU time	2.12 seconds
Started	Jun 09 02:25:39 PM PDT 24
Finished	Jun 09 02:25:42 PM PDT 24
Peak memory	218240 kb
Host	smart-b31ef23c-a7b8-409d-9509-6fd8566667a9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1721087599 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_smoke.1721087599
Directory	/workspace/30.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/30.lc_ctrl_state_failure.746993710
Short name	T82
Test name
Test status
Simulation time	1016695469 ps
CPU time	22.19 seconds
Started	Jun 09 02:25:45 PM PDT 24
Finished	Jun 09 02:26:08 PM PDT 24
Peak memory	251428 kb
Host	smart-df45e00d-f4e1-4d08-af22-43507dda6524
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=746993710 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_failure.746993710
Directory	/workspace/30.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/30.lc_ctrl_state_post_trans.16599613
Short name	T765
Test name
Test status
Simulation time	135474001 ps
CPU time	9.4 seconds
Started	Jun 09 02:25:39 PM PDT 24
Finished	Jun 09 02:25:49 PM PDT 24
Peak memory	251444 kb
Host	smart-3b73c05c-3112-4f2e-b391-0aa734cc761a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=16599613 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_post_trans.16599613
Directory	/workspace/30.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/30.lc_ctrl_stress_all.2677447633
Short name	T178
Test name
Test status
Simulation time	3299184781 ps
CPU time	71.6 seconds
Started	Jun 09 02:25:43 PM PDT 24
Finished	Jun 09 02:26:55 PM PDT 24
Peak memory	228016 kb
Host	smart-c6ed45f5-8fbd-4b62-b789-729d42733a2d
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677447633 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_stress_all.2677447633
Directory	/workspace/30.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/30.lc_ctrl_stress_all_with_rand_reset.2389524097
Short name	T525
Test name
Test status
Simulation time	55643555401 ps
CPU time	502.61 seconds
Started	Jun 09 02:25:41 PM PDT 24
Finished	Jun 09 02:34:04 PM PDT 24
Peak memory	284376 kb
Host	smart-d51346b1-7a9f-47af-977e-6bb78f2ca522
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=2389524097 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_stress_all_with_rand_reset.2389524097
Directory	/workspace/30.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/30.lc_ctrl_volatile_unlock_smoke.2400019969
Short name	T54
Test name
Test status
Simulation time	103878809 ps
CPU time	0.78 seconds
Started	Jun 09 02:25:41 PM PDT 24
Finished	Jun 09 02:25:43 PM PDT 24
Peak memory	209360 kb
Host	smart-304ee25a-930f-4441-9ea6-dfcebfb9fdca
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400019969 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_c trl_volatile_unlock_smoke.2400019969
Directory	/workspace/30.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/31.lc_ctrl_alert_test.23153888
Short name	T568
Test name
Test status
Simulation time	52701678 ps
CPU time	0.97 seconds
Started	Jun 09 02:25:44 PM PDT 24
Finished	Jun 09 02:25:46 PM PDT 24
Peak memory	209536 kb
Host	smart-c198cef8-d808-4848-a445-a292c4f55e5c
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23153888 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_alert_test.23153888
Directory	/workspace/31.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/31.lc_ctrl_errors.987995240
Short name	T255
Test name
Test status
Simulation time	684743156 ps
CPU time	9.25 seconds
Started	Jun 09 02:25:48 PM PDT 24
Finished	Jun 09 02:25:58 PM PDT 24
Peak memory	218736 kb
Host	smart-d47f7973-e485-487a-b886-5e5c315189fd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=987995240 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_errors.987995240
Directory	/workspace/31.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/31.lc_ctrl_jtag_access.211413406
Short name	T172
Test name
Test status
Simulation time	106843573 ps
CPU time	1.39 seconds
Started	Jun 09 02:25:43 PM PDT 24
Finished	Jun 09 02:25:45 PM PDT 24
Peak memory	217484 kb
Host	smart-9049ffb9-dc19-482a-a5f9-140770b0fec9
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211413406 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_jtag_access.211413406
Directory	/workspace/31.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/31.lc_ctrl_prog_failure.2874285127
Short name	T404
Test name
Test status
Simulation time	151683113 ps
CPU time	3.79 seconds
Started	Jun 09 02:25:48 PM PDT 24
Finished	Jun 09 02:25:52 PM PDT 24
Peak memory	222928 kb
Host	smart-9167d382-4dae-46b4-ba8b-a357e8c0a2d1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2874285127 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_prog_failure.2874285127
Directory	/workspace/31.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/31.lc_ctrl_sec_mubi.1408513297
Short name	T669
Test name
Test status
Simulation time	1883564110 ps
CPU time	13.33 seconds
Started	Jun 09 02:25:48 PM PDT 24
Finished	Jun 09 02:26:01 PM PDT 24
Peak memory	218748 kb
Host	smart-3c17b463-1de7-40e7-ad53-5800becd6d10
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408513297 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_mubi.1408513297
Directory	/workspace/31.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/31.lc_ctrl_sec_token_digest.3410056649
Short name	T863
Test name
Test status
Simulation time	646945565 ps
CPU time	15.21 seconds
Started	Jun 09 02:25:45 PM PDT 24
Finished	Jun 09 02:26:01 PM PDT 24
Peak memory	218940 kb
Host	smart-1d2322d9-dae1-4947-bf55-ac8b126c2075
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410056649 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_d igest.3410056649
Directory	/workspace/31.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/31.lc_ctrl_sec_token_mux.1699786673
Short name	T665
Test name
Test status
Simulation time	785396768 ps
CPU time	10.02 seconds
Started	Jun 09 02:25:47 PM PDT 24
Finished	Jun 09 02:25:57 PM PDT 24
Peak memory	218768 kb
Host	smart-e7f1b3cc-6a16-4b29-af88-4343eb3979bb
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699786673 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_mux. 1699786673
Directory	/workspace/31.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/31.lc_ctrl_security_escalation.3225533018
Short name	T621
Test name
Test status
Simulation time	386353770 ps
CPU time	9.47 seconds
Started	Jun 09 02:25:54 PM PDT 24
Finished	Jun 09 02:26:04 PM PDT 24
Peak memory	225396 kb
Host	smart-aaedb62d-ebb1-4349-9126-d347adcde3c5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3225533018 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_security_escalation.3225533018
Directory	/workspace/31.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/31.lc_ctrl_smoke.336792339
Short name	T224
Test name
Test status
Simulation time	198218588 ps
CPU time	3.46 seconds
Started	Jun 09 02:25:42 PM PDT 24
Finished	Jun 09 02:25:46 PM PDT 24
Peak memory	215680 kb
Host	smart-869eceef-e4f0-41df-ba63-464db70a2fda
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=336792339 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_smoke.336792339
Directory	/workspace/31.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/31.lc_ctrl_state_failure.1212373295
Short name	T100
Test name
Test status
Simulation time	397085747 ps
CPU time	33.53 seconds
Started	Jun 09 02:25:40 PM PDT 24
Finished	Jun 09 02:26:14 PM PDT 24
Peak memory	251424 kb
Host	smart-597d6682-a1a3-4ff8-a33b-176196b38659
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1212373295 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_failure.1212373295
Directory	/workspace/31.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/31.lc_ctrl_state_post_trans.91684307
Short name	T362
Test name
Test status
Simulation time	104446197 ps
CPU time	7.63 seconds
Started	Jun 09 02:25:40 PM PDT 24
Finished	Jun 09 02:25:48 PM PDT 24
Peak memory	251364 kb
Host	smart-bfcab70b-2510-4dfa-bbb3-48efb1d5a3e6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=91684307 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_post_trans.91684307
Directory	/workspace/31.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/31.lc_ctrl_stress_all.3752649885
Short name	T110
Test name
Test status
Simulation time	3542978206 ps
CPU time	152.29 seconds
Started	Jun 09 02:25:46 PM PDT 24
Finished	Jun 09 02:28:19 PM PDT 24
Peak memory	267836 kb
Host	smart-e7c6e3ed-b01f-440e-b878-d100a2450e68
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752649885 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_stress_all.3752649885
Directory	/workspace/31.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/31.lc_ctrl_volatile_unlock_smoke.1239817487
Short name	T334
Test name
Test status
Simulation time	42461921 ps
CPU time	0.78 seconds
Started	Jun 09 02:25:40 PM PDT 24
Finished	Jun 09 02:25:41 PM PDT 24
Peak memory	209184 kb
Host	smart-5f8ed6aa-b2c9-47c1-b5ef-c799518dbc50
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239817487 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_c trl_volatile_unlock_smoke.1239817487
Directory	/workspace/31.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/32.lc_ctrl_alert_test.241526353
Short name	T770
Test name
Test status
Simulation time	58907751 ps
CPU time	0.93 seconds
Started	Jun 09 02:25:54 PM PDT 24
Finished	Jun 09 02:25:55 PM PDT 24
Peak memory	209500 kb
Host	smart-16ce126e-5145-4247-99be-6d460bca028a
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241526353 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_alert_test.241526353
Directory	/workspace/32.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/32.lc_ctrl_jtag_access.3101014878
Short name	T618
Test name
Test status
Simulation time	136512946 ps
CPU time	1.86 seconds
Started	Jun 09 02:25:54 PM PDT 24
Finished	Jun 09 02:25:56 PM PDT 24
Peak memory	217540 kb
Host	smart-e4b7e7f5-92ef-4b57-8e07-0829628f4d4c
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101014878 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_jtag_access.3101014878
Directory	/workspace/32.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/32.lc_ctrl_prog_failure.850904127
Short name	T174
Test name
Test status
Simulation time	197887927 ps
CPU time	2.22 seconds
Started	Jun 09 02:25:46 PM PDT 24
Finished	Jun 09 02:25:49 PM PDT 24
Peak memory	218748 kb
Host	smart-16bec79e-826d-4cb7-bf7c-883d8544ad9b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=850904127 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_prog_failure.850904127
Directory	/workspace/32.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/32.lc_ctrl_sec_mubi.672720209
Short name	T801
Test name
Test status
Simulation time	558090798 ps
CPU time	14.79 seconds
Started	Jun 09 02:25:45 PM PDT 24
Finished	Jun 09 02:26:01 PM PDT 24
Peak memory	218800 kb
Host	smart-08a338e7-c133-46c5-9059-f5a33a8ab109
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672720209 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_mubi.672720209
Directory	/workspace/32.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/32.lc_ctrl_sec_token_digest.3786676397
Short name	T294
Test name
Test status
Simulation time	1911519691 ps
CPU time	13.28 seconds
Started	Jun 09 02:25:44 PM PDT 24
Finished	Jun 09 02:25:58 PM PDT 24
Peak memory	226532 kb
Host	smart-4f490501-ade2-4766-928f-7a1583d77ad6
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786676397 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_d igest.3786676397
Directory	/workspace/32.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/32.lc_ctrl_sec_token_mux.3594037471
Short name	T502
Test name
Test status
Simulation time	437077323 ps
CPU time	7.86 seconds
Started	Jun 09 02:25:47 PM PDT 24
Finished	Jun 09 02:25:55 PM PDT 24
Peak memory	226548 kb
Host	smart-1d693bf9-0a68-40f5-ac9d-819c8777359a
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594037471 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_mux. 3594037471
Directory	/workspace/32.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/32.lc_ctrl_security_escalation.313609280
Short name	T363
Test name
Test status
Simulation time	2263783530 ps
CPU time	7.88 seconds
Started	Jun 09 02:25:43 PM PDT 24
Finished	Jun 09 02:25:51 PM PDT 24
Peak memory	226592 kb
Host	smart-0249a0b3-8243-44f6-88c7-6f39d9e567b9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=313609280 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_security_escalation.313609280
Directory	/workspace/32.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/32.lc_ctrl_smoke.2064556663
Short name	T69
Test name
Test status
Simulation time	196075015 ps
CPU time	2.88 seconds
Started	Jun 09 02:25:47 PM PDT 24
Finished	Jun 09 02:25:50 PM PDT 24
Peak memory	218192 kb
Host	smart-7aea28b3-ea5b-4627-b757-d65de656c20b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2064556663 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_smoke.2064556663
Directory	/workspace/32.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/32.lc_ctrl_state_failure.2065706584
Short name	T257
Test name
Test status
Simulation time	1528840151 ps
CPU time	28.12 seconds
Started	Jun 09 02:25:54 PM PDT 24
Finished	Jun 09 02:26:22 PM PDT 24
Peak memory	251416 kb
Host	smart-b53293d8-5495-4f4c-8396-24dee39d9070
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2065706584 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_failure.2065706584
Directory	/workspace/32.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/32.lc_ctrl_state_post_trans.1837224905
Short name	T337
Test name
Test status
Simulation time	350788300 ps
CPU time	4.18 seconds
Started	Jun 09 02:25:45 PM PDT 24
Finished	Jun 09 02:25:50 PM PDT 24
Peak memory	226832 kb
Host	smart-0f049250-1a5c-481d-b0bb-2ca20d366648
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1837224905 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_post_trans.1837224905
Directory	/workspace/32.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/32.lc_ctrl_stress_all.4241146943
Short name	T577
Test name
Test status
Simulation time	9636827779 ps
CPU time	46.78 seconds
Started	Jun 09 02:25:48 PM PDT 24
Finished	Jun 09 02:26:35 PM PDT 24
Peak memory	251492 kb
Host	smart-f76ac66d-2bd5-4c73-95e0-4356765f83a0
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241146943 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_stress_all.4241146943
Directory	/workspace/32.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/32.lc_ctrl_stress_all_with_rand_reset.3281190013
Short name	T853
Test name
Test status
Simulation time	38333592409 ps
CPU time	638.26 seconds
Started	Jun 09 02:25:54 PM PDT 24
Finished	Jun 09 02:36:32 PM PDT 24
Peak memory	412204 kb
Host	smart-6bbf01f2-b3a3-4f85-a357-51cbea186dcb
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=3281190013 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_stress_all_with_rand_reset.3281190013
Directory	/workspace/32.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/32.lc_ctrl_volatile_unlock_smoke.832131119
Short name	T797
Test name
Test status
Simulation time	13442175 ps
CPU time	1.1 seconds
Started	Jun 09 02:25:47 PM PDT 24
Finished	Jun 09 02:25:48 PM PDT 24
Peak memory	212356 kb
Host	smart-5246c5bc-3939-496e-b8af-4a8f19b0cc53
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832131119 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ct rl_volatile_unlock_smoke.832131119
Directory	/workspace/32.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/33.lc_ctrl_alert_test.970226288
Short name	T365
Test name
Test status
Simulation time	86165414 ps
CPU time	0.98 seconds
Started	Jun 09 02:25:50 PM PDT 24
Finished	Jun 09 02:25:51 PM PDT 24
Peak memory	209556 kb
Host	smart-480f6dd5-af79-410a-9a53-0b188df4d058
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970226288 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_alert_test.970226288
Directory	/workspace/33.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/33.lc_ctrl_errors.1747821902
Short name	T264
Test name
Test status
Simulation time	622050214 ps
CPU time	14.11 seconds
Started	Jun 09 02:25:50 PM PDT 24
Finished	Jun 09 02:26:05 PM PDT 24
Peak memory	218604 kb
Host	smart-3f76d2a4-5384-4e53-838f-8cf42c30a020
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1747821902 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_errors.1747821902
Directory	/workspace/33.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/33.lc_ctrl_jtag_access.1416483772
Short name	T643
Test name
Test status
Simulation time	222438108 ps
CPU time	6.31 seconds
Started	Jun 09 02:25:50 PM PDT 24
Finished	Jun 09 02:25:57 PM PDT 24
Peak memory	217872 kb
Host	smart-0d3516eb-8a4b-4ecf-9b98-86ddc8d73984
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416483772 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_jtag_access.1416483772
Directory	/workspace/33.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/33.lc_ctrl_prog_failure.3035928998
Short name	T408
Test name
Test status
Simulation time	67617164 ps
CPU time	3.31 seconds
Started	Jun 09 02:26:00 PM PDT 24
Finished	Jun 09 02:26:03 PM PDT 24
Peak memory	218696 kb
Host	smart-2ac420a2-e4f0-4755-af11-9be8c68f3857
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3035928998 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_prog_failure.3035928998
Directory	/workspace/33.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/33.lc_ctrl_sec_mubi.3560218201
Short name	T213
Test name
Test status
Simulation time	2737569691 ps
CPU time	14.49 seconds
Started	Jun 09 02:25:48 PM PDT 24
Finished	Jun 09 02:26:03 PM PDT 24
Peak memory	219728 kb
Host	smart-6441c61b-63e4-4769-95eb-9fc5bdaba00a
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560218201 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_mubi.3560218201
Directory	/workspace/33.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/33.lc_ctrl_sec_token_digest.3021312052
Short name	T788
Test name
Test status
Simulation time	644797325 ps
CPU time	9.92 seconds
Started	Jun 09 02:25:54 PM PDT 24
Finished	Jun 09 02:26:04 PM PDT 24
Peak memory	218720 kb
Host	smart-c45125a1-3a0c-4491-96aa-5ef63f7715c5
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021312052 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_d igest.3021312052
Directory	/workspace/33.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/33.lc_ctrl_sec_token_mux.388927397
Short name	T28
Test name
Test status
Simulation time	279993125 ps
CPU time	9.76 seconds
Started	Jun 09 02:25:49 PM PDT 24
Finished	Jun 09 02:25:59 PM PDT 24
Peak memory	218736 kb
Host	smart-46df6c1a-5eca-4ccd-a20e-0c0d951bd18d
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388927397 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_mux.388927397
Directory	/workspace/33.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/33.lc_ctrl_security_escalation.1218473677
Short name	T590
Test name
Test status
Simulation time	1036178703 ps
CPU time	10.58 seconds
Started	Jun 09 02:25:50 PM PDT 24
Finished	Jun 09 02:26:01 PM PDT 24
Peak memory	226508 kb
Host	smart-6e0b8c52-8fc1-406b-afce-cc5d883b22af
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1218473677 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_security_escalation.1218473677
Directory	/workspace/33.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/33.lc_ctrl_smoke.975199179
Short name	T401
Test name
Test status
Simulation time	62018630 ps
CPU time	3.13 seconds
Started	Jun 09 02:25:53 PM PDT 24
Finished	Jun 09 02:25:56 PM PDT 24
Peak memory	218220 kb
Host	smart-af4b4a71-1ed4-47d1-bb18-ca4142261644
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=975199179 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_smoke.975199179
Directory	/workspace/33.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/33.lc_ctrl_state_failure.2615743877
Short name	T596
Test name
Test status
Simulation time	4177092092 ps
CPU time	32.95 seconds
Started	Jun 09 02:25:46 PM PDT 24
Finished	Jun 09 02:26:19 PM PDT 24
Peak memory	251504 kb
Host	smart-a5cdfcd5-8db3-4c35-810c-edbf8d737932
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2615743877 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_failure.2615743877
Directory	/workspace/33.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/33.lc_ctrl_state_post_trans.515672034
Short name	T864
Test name
Test status
Simulation time	65876289 ps
CPU time	6.57 seconds
Started	Jun 09 02:25:49 PM PDT 24
Finished	Jun 09 02:25:56 PM PDT 24
Peak memory	247500 kb
Host	smart-c611c633-6512-4711-970f-5fe93dfdf934
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=515672034 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_post_trans.515672034
Directory	/workspace/33.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/33.lc_ctrl_stress_all.3620701341
Short name	T589
Test name
Test status
Simulation time	6859934853 ps
CPU time	209.53 seconds
Started	Jun 09 02:25:49 PM PDT 24
Finished	Jun 09 02:29:19 PM PDT 24
Peak memory	224508 kb
Host	smart-38b23f1f-a144-4287-bbce-cee2a588f7dc
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620701341 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_stress_all.3620701341
Directory	/workspace/33.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/33.lc_ctrl_stress_all_with_rand_reset.3736625672
Short name	T87
Test name
Test status
Simulation time	41442333347 ps
CPU time	966.65 seconds
Started	Jun 09 02:25:50 PM PDT 24
Finished	Jun 09 02:41:57 PM PDT 24
Peak memory	497368 kb
Host	smart-76a9cb70-7477-4b34-a715-f34630d0cdcf
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=3736625672 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_stress_all_with_rand_reset.3736625672
Directory	/workspace/33.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/33.lc_ctrl_volatile_unlock_smoke.2123480959
Short name	T53
Test name
Test status
Simulation time	35123530 ps
CPU time	1.01 seconds
Started	Jun 09 02:25:49 PM PDT 24
Finished	Jun 09 02:25:51 PM PDT 24
Peak memory	218400 kb
Host	smart-b5ee8301-3c6f-4537-911b-cfbf7efa0010
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123480959 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_c trl_volatile_unlock_smoke.2123480959
Directory	/workspace/33.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/34.lc_ctrl_alert_test.3801487365
Short name	T293
Test name
Test status
Simulation time	16563048 ps
CPU time	1.08 seconds
Started	Jun 09 02:25:57 PM PDT 24
Finished	Jun 09 02:25:58 PM PDT 24
Peak memory	209432 kb
Host	smart-a9a69d31-280b-4790-89c7-7cd187603e6c
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801487365 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_alert_test.3801487365
Directory	/workspace/34.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/34.lc_ctrl_errors.3409649345
Short name	T274
Test name
Test status
Simulation time	367023562 ps
CPU time	15.71 seconds
Started	Jun 09 02:25:48 PM PDT 24
Finished	Jun 09 02:26:04 PM PDT 24
Peak memory	218756 kb
Host	smart-cc1cdba7-8ef5-46f0-b351-4030e807ccd4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3409649345 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_errors.3409649345
Directory	/workspace/34.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/34.lc_ctrl_jtag_access.1985536307
Short name	T854
Test name
Test status
Simulation time	2453617682 ps
CPU time	6.5 seconds
Started	Jun 09 02:25:49 PM PDT 24
Finished	Jun 09 02:25:56 PM PDT 24
Peak memory	218072 kb
Host	smart-c8c28709-fd52-4641-ae09-8c5ee1a9a837
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985536307 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_jtag_access.1985536307
Directory	/workspace/34.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/34.lc_ctrl_prog_failure.1963422160
Short name	T775
Test name
Test status
Simulation time	74776554 ps
CPU time	3.02 seconds
Started	Jun 09 02:25:48 PM PDT 24
Finished	Jun 09 02:25:51 PM PDT 24
Peak memory	218892 kb
Host	smart-9a266731-f490-46fc-a3b5-9bc5af4af2df
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1963422160 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_prog_failure.1963422160
Directory	/workspace/34.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/34.lc_ctrl_sec_mubi.1416911960
Short name	T604
Test name
Test status
Simulation time	423220175 ps
CPU time	13.56 seconds
Started	Jun 09 02:25:49 PM PDT 24
Finished	Jun 09 02:26:03 PM PDT 24
Peak memory	219392 kb
Host	smart-0054d886-75b4-4fe6-9e12-ec256c854a42
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416911960 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_mubi.1416911960
Directory	/workspace/34.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/34.lc_ctrl_sec_token_digest.556021093
Short name	T632
Test name
Test status
Simulation time	435167554 ps
CPU time	10.58 seconds
Started	Jun 09 02:25:52 PM PDT 24
Finished	Jun 09 02:26:02 PM PDT 24
Peak memory	226544 kb
Host	smart-dab05e96-163b-4e7a-9b63-6ef0787a1119
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556021093 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_di gest.556021093
Directory	/workspace/34.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/34.lc_ctrl_sec_token_mux.1908962482
Short name	T253
Test name
Test status
Simulation time	268178037 ps
CPU time	7.56 seconds
Started	Jun 09 02:25:50 PM PDT 24
Finished	Jun 09 02:25:58 PM PDT 24
Peak memory	218708 kb
Host	smart-176ff2bf-34f2-4b0b-a71c-b21d4b375919
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908962482 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_mux. 1908962482
Directory	/workspace/34.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/34.lc_ctrl_security_escalation.2480499298
Short name	T329
Test name
Test status
Simulation time	238168210 ps
CPU time	9.05 seconds
Started	Jun 09 02:25:48 PM PDT 24
Finished	Jun 09 02:25:57 PM PDT 24
Peak memory	218772 kb
Host	smart-ab074684-c9ef-4553-b342-1c5aa5af6057
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2480499298 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_security_escalation.2480499298
Directory	/workspace/34.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/34.lc_ctrl_smoke.1039933094
Short name	T411
Test name
Test status
Simulation time	590792045 ps
CPU time	2.15 seconds
Started	Jun 09 02:25:49 PM PDT 24
Finished	Jun 09 02:25:51 PM PDT 24
Peak memory	218304 kb
Host	smart-1a3348c3-1182-467d-b30a-8d269614a05f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1039933094 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_smoke.1039933094
Directory	/workspace/34.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/34.lc_ctrl_state_failure.2113584346
Short name	T324
Test name
Test status
Simulation time	326222408 ps
CPU time	32.13 seconds
Started	Jun 09 02:25:48 PM PDT 24
Finished	Jun 09 02:26:20 PM PDT 24
Peak memory	251396 kb
Host	smart-e9ba25bd-acd8-4b45-a78d-905d08ae77aa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2113584346 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_failure.2113584346
Directory	/workspace/34.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/34.lc_ctrl_state_post_trans.1919799632
Short name	T371
Test name
Test status
Simulation time	76670894 ps
CPU time	6.54 seconds
Started	Jun 09 02:25:57 PM PDT 24
Finished	Jun 09 02:26:04 PM PDT 24
Peak memory	250988 kb
Host	smart-3be7138f-b839-4c1e-8b4d-1792a9eff7e9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1919799632 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_post_trans.1919799632
Directory	/workspace/34.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/34.lc_ctrl_stress_all.1264159831
Short name	T304
Test name
Test status
Simulation time	10492496906 ps
CPU time	202.45 seconds
Started	Jun 09 02:25:56 PM PDT 24
Finished	Jun 09 02:29:18 PM PDT 24
Peak memory	271272 kb
Host	smart-79a7bf06-cb51-46d3-af51-6a9208bbd772
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264159831 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_stress_all.1264159831
Directory	/workspace/34.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/34.lc_ctrl_volatile_unlock_smoke.1685138163
Short name	T439
Test name
Test status
Simulation time	58503432 ps
CPU time	1.02 seconds
Started	Jun 09 02:25:51 PM PDT 24
Finished	Jun 09 02:25:57 PM PDT 24
Peak memory	212368 kb
Host	smart-4137c863-b9ad-4dad-b5f3-3822d8d1bda7
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685138163 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_c trl_volatile_unlock_smoke.1685138163
Directory	/workspace/34.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/35.lc_ctrl_alert_test.2409924772
Short name	T464
Test name
Test status
Simulation time	20854543 ps
CPU time	0.95 seconds
Started	Jun 09 02:25:59 PM PDT 24
Finished	Jun 09 02:26:01 PM PDT 24
Peak memory	209324 kb
Host	smart-fbe06ac8-2bbe-46c7-a413-196c2f6c4cf7
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409924772 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_alert_test.2409924772
Directory	/workspace/35.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/35.lc_ctrl_errors.2904539390
Short name	T752
Test name
Test status
Simulation time	1680378573 ps
CPU time	12.62 seconds
Started	Jun 09 02:25:52 PM PDT 24
Finished	Jun 09 02:26:09 PM PDT 24
Peak memory	218684 kb
Host	smart-cb2c6a50-8878-4a54-9ffb-6287505e10c8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2904539390 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_errors.2904539390
Directory	/workspace/35.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/35.lc_ctrl_jtag_access.4089229228
Short name	T30
Test name
Test status
Simulation time	576346481 ps
CPU time	6.67 seconds
Started	Jun 09 02:25:56 PM PDT 24
Finished	Jun 09 02:26:03 PM PDT 24
Peak memory	217788 kb
Host	smart-a4eec7da-2be2-4526-b8f5-d03f74ebe52c
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089229228 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_jtag_access.4089229228
Directory	/workspace/35.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/35.lc_ctrl_prog_failure.1166640793
Short name	T465
Test name
Test status
Simulation time	41192027 ps
CPU time	1.95 seconds
Started	Jun 09 02:25:53 PM PDT 24
Finished	Jun 09 02:25:55 PM PDT 24
Peak memory	218676 kb
Host	smart-6b8ba4ef-d3de-41b5-a25d-0e52078d70e2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1166640793 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_prog_failure.1166640793
Directory	/workspace/35.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/35.lc_ctrl_sec_mubi.2979310699
Short name	T289
Test name
Test status
Simulation time	1511036578 ps
CPU time	16.1 seconds
Started	Jun 09 02:25:52 PM PDT 24
Finished	Jun 09 02:26:08 PM PDT 24
Peak memory	220460 kb
Host	smart-30868a69-ae0c-44fd-b830-4eaa626e8ae2
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979310699 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_mubi.2979310699
Directory	/workspace/35.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/35.lc_ctrl_sec_token_digest.780362396
Short name	T762
Test name
Test status
Simulation time	1069049213 ps
CPU time	20.69 seconds
Started	Jun 09 02:26:09 PM PDT 24
Finished	Jun 09 02:26:30 PM PDT 24
Peak memory	226540 kb
Host	smart-8a603c07-508e-4b80-9aac-13e0ca02fc9e
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780362396 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_di gest.780362396
Directory	/workspace/35.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/35.lc_ctrl_sec_token_mux.2150244015
Short name	T258
Test name
Test status
Simulation time	1633636185 ps
CPU time	9.17 seconds
Started	Jun 09 02:26:08 PM PDT 24
Finished	Jun 09 02:26:18 PM PDT 24
Peak memory	218716 kb
Host	smart-63f43a1c-e3a7-4709-a2ad-87ce4bdcc2a0
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150244015 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_mux. 2150244015
Directory	/workspace/35.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/35.lc_ctrl_security_escalation.2353328185
Short name	T639
Test name
Test status
Simulation time	158221820 ps
CPU time	7.68 seconds
Started	Jun 09 02:25:56 PM PDT 24
Finished	Jun 09 02:26:04 PM PDT 24
Peak memory	225728 kb
Host	smart-d4065ae4-1fdd-4468-a58d-2d8d51757547
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2353328185 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_security_escalation.2353328185
Directory	/workspace/35.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/35.lc_ctrl_smoke.3027069812
Short name	T29
Test name
Test status
Simulation time	407110892 ps
CPU time	11.46 seconds
Started	Jun 09 02:26:03 PM PDT 24
Finished	Jun 09 02:26:14 PM PDT 24
Peak memory	218220 kb
Host	smart-40cf22af-bcef-4af9-9134-409b023cc539
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3027069812 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_smoke.3027069812
Directory	/workspace/35.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/35.lc_ctrl_state_failure.452765641
Short name	T695
Test name
Test status
Simulation time	3878034388 ps
CPU time	23.16 seconds
Started	Jun 09 02:25:58 PM PDT 24
Finished	Jun 09 02:26:22 PM PDT 24
Peak memory	251452 kb
Host	smart-fe895d59-f5ef-40ec-8d9e-12a507ab0ba8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=452765641 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_failure.452765641
Directory	/workspace/35.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/35.lc_ctrl_state_post_trans.1395048401
Short name	T617
Test name
Test status
Simulation time	439715867 ps
CPU time	7.13 seconds
Started	Jun 09 02:25:53 PM PDT 24
Finished	Jun 09 02:26:00 PM PDT 24
Peak memory	250880 kb
Host	smart-b32f531e-7ed3-43f4-96e5-38817b2a069b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1395048401 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_post_trans.1395048401
Directory	/workspace/35.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/35.lc_ctrl_stress_all.2263017697
Short name	T653
Test name
Test status
Simulation time	9049711161 ps
CPU time	103.96 seconds
Started	Jun 09 02:25:56 PM PDT 24
Finished	Jun 09 02:27:41 PM PDT 24
Peak memory	267860 kb
Host	smart-dd6e7b72-9e98-4817-8289-3acae446d3f6
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263017697 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_stress_all.2263017697
Directory	/workspace/35.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/35.lc_ctrl_volatile_unlock_smoke.4191952867
Short name	T107
Test name
Test status
Simulation time	14685865 ps
CPU time	0.8 seconds
Started	Jun 09 02:25:59 PM PDT 24
Finished	Jun 09 02:26:00 PM PDT 24
Peak memory	209268 kb
Host	smart-35af01d7-cd65-49bd-8831-416e39e18617
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191952867 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_c trl_volatile_unlock_smoke.4191952867
Directory	/workspace/35.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/36.lc_ctrl_alert_test.148913229
Short name	T838
Test name
Test status
Simulation time	134125536 ps
CPU time	0.92 seconds
Started	Jun 09 02:26:12 PM PDT 24
Finished	Jun 09 02:26:13 PM PDT 24
Peak memory	209364 kb
Host	smart-76f4fe8d-f809-4db7-81ee-06aa6008602b
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148913229 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_alert_test.148913229
Directory	/workspace/36.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/36.lc_ctrl_errors.2936618802
Short name	T593
Test name
Test status
Simulation time	436998068 ps
CPU time	18.52 seconds
Started	Jun 09 02:25:54 PM PDT 24
Finished	Jun 09 02:26:13 PM PDT 24
Peak memory	218700 kb
Host	smart-2dc5341d-48ae-445c-8767-8b5d4f0a70c5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2936618802 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_errors.2936618802
Directory	/workspace/36.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/36.lc_ctrl_jtag_access.450866885
Short name	T822
Test name
Test status
Simulation time	438622149 ps
CPU time	3.93 seconds
Started	Jun 09 02:25:53 PM PDT 24
Finished	Jun 09 02:25:57 PM PDT 24
Peak memory	217708 kb
Host	smart-d830dc1b-9814-40e3-adc4-25541f327de2
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450866885 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_jtag_access.450866885
Directory	/workspace/36.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/36.lc_ctrl_prog_failure.409548558
Short name	T97
Test name
Test status
Simulation time	64400490 ps
CPU time	2.74 seconds
Started	Jun 09 02:25:57 PM PDT 24
Finished	Jun 09 02:26:00 PM PDT 24
Peak memory	222836 kb
Host	smart-aae554f5-f40a-47c6-bb11-f3a3021fc2ba
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=409548558 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_prog_failure.409548558
Directory	/workspace/36.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/36.lc_ctrl_sec_mubi.1394417974
Short name	T802
Test name
Test status
Simulation time	523935397 ps
CPU time	11.79 seconds
Started	Jun 09 02:26:02 PM PDT 24
Finished	Jun 09 02:26:14 PM PDT 24
Peak memory	226560 kb
Host	smart-79b94a71-dcb2-4bf4-8b6f-47439b7f01cb
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394417974 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_mubi.1394417974
Directory	/workspace/36.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/36.lc_ctrl_sec_token_digest.529591325
Short name	T101
Test name
Test status
Simulation time	287156492 ps
CPU time	8.76 seconds
Started	Jun 09 02:26:02 PM PDT 24
Finished	Jun 09 02:26:11 PM PDT 24
Peak memory	226556 kb
Host	smart-1e8dd19a-8cb9-4aa3-98d0-ec1efac261b4
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529591325 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_di gest.529591325
Directory	/workspace/36.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/36.lc_ctrl_sec_token_mux.3538259594
Short name	T574
Test name
Test status
Simulation time	1194640675 ps
CPU time	13.55 seconds
Started	Jun 09 02:26:09 PM PDT 24
Finished	Jun 09 02:26:23 PM PDT 24
Peak memory	226520 kb
Host	smart-288cfc1d-cf43-4a2d-ae09-340711c139c6
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538259594 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_mux. 3538259594
Directory	/workspace/36.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/36.lc_ctrl_security_escalation.1785791282
Short name	T697
Test name
Test status
Simulation time	1232494615 ps
CPU time	8.77 seconds
Started	Jun 09 02:25:57 PM PDT 24
Finished	Jun 09 02:26:06 PM PDT 24
Peak memory	225592 kb
Host	smart-42847518-917a-4f66-a5fd-276636d8c7e9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1785791282 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_security_escalation.1785791282
Directory	/workspace/36.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/36.lc_ctrl_smoke.219071118
Short name	T37
Test name
Test status
Simulation time	25062523 ps
CPU time	1.69 seconds
Started	Jun 09 02:26:08 PM PDT 24
Finished	Jun 09 02:26:10 PM PDT 24
Peak memory	218220 kb
Host	smart-b3f63bd8-d016-4612-a05a-e9b9ee7d75d5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=219071118 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_smoke.219071118
Directory	/workspace/36.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/36.lc_ctrl_state_failure.3764396692
Short name	T629
Test name
Test status
Simulation time	377383586 ps
CPU time	23.65 seconds
Started	Jun 09 02:25:56 PM PDT 24
Finished	Jun 09 02:26:20 PM PDT 24
Peak memory	251428 kb
Host	smart-85190c37-a107-4351-aa8c-63977c7f4c84
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3764396692 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_failure.3764396692
Directory	/workspace/36.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/36.lc_ctrl_state_post_trans.4194421565
Short name	T816
Test name
Test status
Simulation time	199480192 ps
CPU time	6.52 seconds
Started	Jun 09 02:25:55 PM PDT 24
Finished	Jun 09 02:26:02 PM PDT 24
Peak memory	247444 kb
Host	smart-e88efaf3-b10e-4767-a7aa-ae074129ff34
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4194421565 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_post_trans.4194421565
Directory	/workspace/36.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/36.lc_ctrl_stress_all.209225665
Short name	T744
Test name
Test status
Simulation time	440743819 ps
CPU time	10.04 seconds
Started	Jun 09 02:25:58 PM PDT 24
Finished	Jun 09 02:26:09 PM PDT 24
Peak memory	218364 kb
Host	smart-20b43284-33bc-4f6d-903c-fa0e0355cae3
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209225665 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_ TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_stress_all.209225665
Directory	/workspace/36.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/36.lc_ctrl_volatile_unlock_smoke.3855180414
Short name	T597
Test name
Test status
Simulation time	20600682 ps
CPU time	1 seconds
Started	Jun 09 02:26:05 PM PDT 24
Finished	Jun 09 02:26:06 PM PDT 24
Peak memory	212368 kb
Host	smart-e6f4c942-d3dd-47ee-b0a6-2e7c586d2997
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855180414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_c trl_volatile_unlock_smoke.3855180414
Directory	/workspace/36.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/37.lc_ctrl_alert_test.2404608384
Short name	T839
Test name
Test status
Simulation time	79665590 ps
CPU time	0.95 seconds
Started	Jun 09 02:26:10 PM PDT 24
Finished	Jun 09 02:26:11 PM PDT 24
Peak memory	209492 kb
Host	smart-35f9cdab-37a1-4d48-b20b-c012245291d4
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404608384 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_alert_test.2404608384
Directory	/workspace/37.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/37.lc_ctrl_errors.4115926979
Short name	T278
Test name
Test status
Simulation time	231492702 ps
CPU time	8.61 seconds
Started	Jun 09 02:26:08 PM PDT 24
Finished	Jun 09 02:26:17 PM PDT 24
Peak memory	218664 kb
Host	smart-d7b4c0c5-9ed5-44f2-aa99-2d9b20dac910
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4115926979 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_errors.4115926979
Directory	/workspace/37.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/37.lc_ctrl_jtag_access.179215593
Short name	T684
Test name
Test status
Simulation time	1187519791 ps
CPU time	14.48 seconds
Started	Jun 09 02:25:57 PM PDT 24
Finished	Jun 09 02:26:12 PM PDT 24
Peak memory	217884 kb
Host	smart-88cdd02a-9f56-4685-9836-397eceaa402d
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179215593 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_jtag_access.179215593
Directory	/workspace/37.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/37.lc_ctrl_prog_failure.241158909
Short name	T420
Test name
Test status
Simulation time	108374126 ps
CPU time	4.91 seconds
Started	Jun 09 02:26:13 PM PDT 24
Finished	Jun 09 02:26:18 PM PDT 24
Peak memory	218656 kb
Host	smart-87dd41bb-f267-46bf-a0b7-ea96424772d4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=241158909 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_prog_failure.241158909
Directory	/workspace/37.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/37.lc_ctrl_sec_mubi.633136251
Short name	T674
Test name
Test status
Simulation time	1513087486 ps
CPU time	17.04 seconds
Started	Jun 09 02:26:09 PM PDT 24
Finished	Jun 09 02:26:26 PM PDT 24
Peak memory	219344 kb
Host	smart-286dd61b-c25d-4742-aaee-57cdb74f030a
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633136251 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_mubi.633136251
Directory	/workspace/37.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/37.lc_ctrl_sec_token_digest.2975183390
Short name	T499
Test name
Test status
Simulation time	1155092985 ps
CPU time	9.24 seconds
Started	Jun 09 02:25:58 PM PDT 24
Finished	Jun 09 02:26:08 PM PDT 24
Peak memory	218676 kb
Host	smart-00e4aefc-0615-492d-b456-13189068ab1b
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975183390 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_d igest.2975183390
Directory	/workspace/37.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/37.lc_ctrl_sec_token_mux.2282409078
Short name	T535
Test name
Test status
Simulation time	944206103 ps
CPU time	8.38 seconds
Started	Jun 09 02:26:00 PM PDT 24
Finished	Jun 09 02:26:09 PM PDT 24
Peak memory	226532 kb
Host	smart-3c52e779-432c-4f54-b6dc-c05b6f4d8ec9
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282409078 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_mux. 2282409078
Directory	/workspace/37.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/37.lc_ctrl_security_escalation.1770464099
Short name	T850
Test name
Test status
Simulation time	1638707565 ps
CPU time	14.25 seconds
Started	Jun 09 02:25:59 PM PDT 24
Finished	Jun 09 02:26:13 PM PDT 24
Peak memory	225988 kb
Host	smart-d99440a2-dbbe-48ed-a12b-f709a5851002
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1770464099 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_security_escalation.1770464099
Directory	/workspace/37.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/37.lc_ctrl_smoke.838779386
Short name	T325
Test name
Test status
Simulation time	29575511 ps
CPU time	1.57 seconds
Started	Jun 09 02:26:10 PM PDT 24
Finished	Jun 09 02:26:12 PM PDT 24
Peak memory	214312 kb
Host	smart-ad11117c-db38-4159-b669-7c69271a4a9c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=838779386 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_smoke.838779386
Directory	/workspace/37.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/37.lc_ctrl_state_failure.1414075739
Short name	T683
Test name
Test status
Simulation time	466382737 ps
CPU time	22.25 seconds
Started	Jun 09 02:26:08 PM PDT 24
Finished	Jun 09 02:26:31 PM PDT 24
Peak memory	251416 kb
Host	smart-80053baf-070b-4fc8-b7aa-aea6dc8035c3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1414075739 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_failure.1414075739
Directory	/workspace/37.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/37.lc_ctrl_state_post_trans.699406661
Short name	T651
Test name
Test status
Simulation time	184883654 ps
CPU time	10.03 seconds
Started	Jun 09 02:25:59 PM PDT 24
Finished	Jun 09 02:26:09 PM PDT 24
Peak memory	251436 kb
Host	smart-dd1accf1-a1d9-41a8-8214-90a484791f74
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=699406661 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_post_trans.699406661
Directory	/workspace/37.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/37.lc_ctrl_stress_all.2501287834
Short name	T545
Test name
Test status
Simulation time	39485908757 ps
CPU time	301.47 seconds
Started	Jun 09 02:26:02 PM PDT 24
Finished	Jun 09 02:31:03 PM PDT 24
Peak memory	251484 kb
Host	smart-7b7f5e41-fbee-49a5-82b5-79e49cad36c1
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501287834 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_stress_all.2501287834
Directory	/workspace/37.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/37.lc_ctrl_stress_all_with_rand_reset.1694129388
Short name	T462
Test name
Test status
Simulation time	28004037918 ps
CPU time	266.71 seconds
Started	Jun 09 02:26:01 PM PDT 24
Finished	Jun 09 02:30:29 PM PDT 24
Peak memory	333520 kb
Host	smart-dec60569-8954-4c24-9087-0792a994a79d
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=1694129388 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_stress_all_with_rand_reset.1694129388
Directory	/workspace/37.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/37.lc_ctrl_volatile_unlock_smoke.1552801894
Short name	T790
Test name
Test status
Simulation time	19581280 ps
CPU time	0.79 seconds
Started	Jun 09 02:26:07 PM PDT 24
Finished	Jun 09 02:26:08 PM PDT 24
Peak memory	209164 kb
Host	smart-62cfd641-8fd3-4a5d-84b5-0765c823454e
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552801894 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_c trl_volatile_unlock_smoke.1552801894
Directory	/workspace/37.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/38.lc_ctrl_alert_test.1679077121
Short name	T701
Test name
Test status
Simulation time	24583319 ps
CPU time	0.96 seconds
Started	Jun 09 02:26:07 PM PDT 24
Finished	Jun 09 02:26:08 PM PDT 24
Peak memory	209444 kb
Host	smart-21ab1bad-39d7-4aca-a690-7b641fd7a5a5
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679077121 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_alert_test.1679077121
Directory	/workspace/38.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/38.lc_ctrl_errors.4026293744
Short name	T230
Test name
Test status
Simulation time	438016205 ps
CPU time	9.72 seconds
Started	Jun 09 02:26:12 PM PDT 24
Finished	Jun 09 02:26:23 PM PDT 24
Peak memory	218684 kb
Host	smart-00de207e-053a-4021-a50f-d991d25741c9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4026293744 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_errors.4026293744
Directory	/workspace/38.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/38.lc_ctrl_jtag_access.4256517574
Short name	T461
Test name
Test status
Simulation time	1186717742 ps
CPU time	5.02 seconds
Started	Jun 09 02:26:05 PM PDT 24
Finished	Jun 09 02:26:10 PM PDT 24
Peak memory	217560 kb
Host	smart-000b6477-d78b-45db-875a-9a4313c7e094
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256517574 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_jtag_access.4256517574
Directory	/workspace/38.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/38.lc_ctrl_prog_failure.2604142589
Short name	T227
Test name
Test status
Simulation time	62620668 ps
CPU time	3.38 seconds
Started	Jun 09 02:25:59 PM PDT 24
Finished	Jun 09 02:26:03 PM PDT 24
Peak memory	218656 kb
Host	smart-8678f439-4b05-4a85-b12b-5afc1b410ed4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2604142589 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_prog_failure.2604142589
Directory	/workspace/38.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/38.lc_ctrl_sec_mubi.1880841199
Short name	T241
Test name
Test status
Simulation time	308208823 ps
CPU time	13.79 seconds
Started	Jun 09 02:26:12 PM PDT 24
Finished	Jun 09 02:26:26 PM PDT 24
Peak memory	220456 kb
Host	smart-3864fdc8-b157-4e23-8a1e-b5da7a152bb1
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880841199 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_mubi.1880841199
Directory	/workspace/38.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/38.lc_ctrl_sec_token_digest.437140916
Short name	T586
Test name
Test status
Simulation time	948929145 ps
CPU time	8.51 seconds
Started	Jun 09 02:26:13 PM PDT 24
Finished	Jun 09 02:26:22 PM PDT 24
Peak memory	218724 kb
Host	smart-dda660a9-bf3e-42a0-903b-817676ba4fd6
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437140916 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_di gest.437140916
Directory	/workspace/38.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/38.lc_ctrl_sec_token_mux.4093508370
Short name	T702
Test name
Test status
Simulation time	225657047 ps
CPU time	8.87 seconds
Started	Jun 09 02:26:09 PM PDT 24
Finished	Jun 09 02:26:18 PM PDT 24
Peak memory	218732 kb
Host	smart-c778e1cf-f3f7-49d0-818a-78a8c31c04d9
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093508370 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_mux. 4093508370
Directory	/workspace/38.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/38.lc_ctrl_security_escalation.2464711421
Short name	T561
Test name
Test status
Simulation time	3094617553 ps
CPU time	12.99 seconds
Started	Jun 09 02:26:05 PM PDT 24
Finished	Jun 09 02:26:19 PM PDT 24
Peak memory	226552 kb
Host	smart-c4fab97e-de3b-4538-8e78-28def58149d0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2464711421 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_security_escalation.2464711421
Directory	/workspace/38.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/38.lc_ctrl_smoke.866938534
Short name	T13
Test name
Test status
Simulation time	27031091 ps
CPU time	1.49 seconds
Started	Jun 09 02:26:13 PM PDT 24
Finished	Jun 09 02:26:15 PM PDT 24
Peak memory	214280 kb
Host	smart-710eb7d3-0069-4f60-8ddc-81da67387f12
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=866938534 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_smoke.866938534
Directory	/workspace/38.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/38.lc_ctrl_state_failure.1537890233
Short name	T682
Test name
Test status
Simulation time	295306423 ps
CPU time	27.92 seconds
Started	Jun 09 02:25:59 PM PDT 24
Finished	Jun 09 02:26:27 PM PDT 24
Peak memory	251420 kb
Host	smart-1eaf760d-9a34-45f5-867e-f7dd267fa9e7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1537890233 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_failure.1537890233
Directory	/workspace/38.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/38.lc_ctrl_state_post_trans.4131376502
Short name	T473
Test name
Test status
Simulation time	249341922 ps
CPU time	7.2 seconds
Started	Jun 09 02:26:00 PM PDT 24
Finished	Jun 09 02:26:08 PM PDT 24
Peak memory	251244 kb
Host	smart-63171794-16d1-4f44-9ad3-c637a8148917
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4131376502 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_post_trans.4131376502
Directory	/workspace/38.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/38.lc_ctrl_stress_all.1521970309
Short name	T846
Test name
Test status
Simulation time	9718213050 ps
CPU time	162.69 seconds
Started	Jun 09 02:26:10 PM PDT 24
Finished	Jun 09 02:28:53 PM PDT 24
Peak memory	251472 kb
Host	smart-25d3b74d-0671-4789-b89f-43b9fdfe1e78
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521970309 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_stress_all.1521970309
Directory	/workspace/38.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/38.lc_ctrl_volatile_unlock_smoke.967048810
Short name	T481
Test name
Test status
Simulation time	91726353 ps
CPU time	0.92 seconds
Started	Jun 09 02:25:57 PM PDT 24
Finished	Jun 09 02:25:59 PM PDT 24
Peak memory	212364 kb
Host	smart-4c34ad9c-e241-4b53-a2c4-857e7e7670ac
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967048810 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ct rl_volatile_unlock_smoke.967048810
Directory	/workspace/38.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/39.lc_ctrl_alert_test.1569087382
Short name	T876
Test name
Test status
Simulation time	47629300 ps
CPU time	1.31 seconds
Started	Jun 09 02:26:05 PM PDT 24
Finished	Jun 09 02:26:06 PM PDT 24
Peak memory	209520 kb
Host	smart-0e2b8a71-44fa-4244-ac24-7689ec0cd4de
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569087382 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_alert_test.1569087382
Directory	/workspace/39.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/39.lc_ctrl_errors.513169966
Short name	T244
Test name
Test status
Simulation time	1750097439 ps
CPU time	13.96 seconds
Started	Jun 09 02:26:12 PM PDT 24
Finished	Jun 09 02:26:26 PM PDT 24
Peak memory	218560 kb
Host	smart-d2343c09-b6c7-4d05-aecb-8c7eec5628b5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=513169966 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_errors.513169966
Directory	/workspace/39.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/39.lc_ctrl_jtag_access.2728978161
Short name	T598
Test name
Test status
Simulation time	1850544788 ps
CPU time	12.12 seconds
Started	Jun 09 02:26:12 PM PDT 24
Finished	Jun 09 02:26:25 PM PDT 24
Peak memory	218044 kb
Host	smart-c44ff6a9-feab-4011-91f8-a2dfdbac81a7
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728978161 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_jtag_access.2728978161
Directory	/workspace/39.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/39.lc_ctrl_prog_failure.4134974288
Short name	T295
Test name
Test status
Simulation time	31031829 ps
CPU time	1.93 seconds
Started	Jun 09 02:26:11 PM PDT 24
Finished	Jun 09 02:26:13 PM PDT 24
Peak memory	218700 kb
Host	smart-e96e7ed0-cccb-4f6b-a43e-fcb5c83c12fa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4134974288 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_prog_failure.4134974288
Directory	/workspace/39.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/39.lc_ctrl_sec_mubi.3222674598
Short name	T558
Test name
Test status
Simulation time	460095139 ps
CPU time	19.09 seconds
Started	Jun 09 02:26:07 PM PDT 24
Finished	Jun 09 02:26:26 PM PDT 24
Peak memory	226528 kb
Host	smart-206bd8f2-65e6-488a-81b5-a1e2869c6cef
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222674598 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_mubi.3222674598
Directory	/workspace/39.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/39.lc_ctrl_sec_token_digest.2956435168
Short name	T447
Test name
Test status
Simulation time	1634440516 ps
CPU time	11.86 seconds
Started	Jun 09 02:26:03 PM PDT 24
Finished	Jun 09 02:26:16 PM PDT 24
Peak memory	218656 kb
Host	smart-19f77fbb-11d1-467c-89b5-25c5605d663d
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956435168 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_d igest.2956435168
Directory	/workspace/39.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/39.lc_ctrl_sec_token_mux.1624932933
Short name	T571
Test name
Test status
Simulation time	1031550680 ps
CPU time	9.6 seconds
Started	Jun 09 02:26:05 PM PDT 24
Finished	Jun 09 02:26:15 PM PDT 24
Peak memory	226516 kb
Host	smart-5fba9c33-096e-4ce3-accb-a9f9dd7a1934
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624932933 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_mux. 1624932933
Directory	/workspace/39.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/39.lc_ctrl_security_escalation.2205578659
Short name	T576
Test name
Test status
Simulation time	2792488017 ps
CPU time	6.66 seconds
Started	Jun 09 02:26:07 PM PDT 24
Finished	Jun 09 02:26:14 PM PDT 24
Peak memory	226584 kb
Host	smart-a04228c8-f05c-4d1b-8966-583dcbd325b4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2205578659 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_security_escalation.2205578659
Directory	/workspace/39.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/39.lc_ctrl_smoke.144200315
Short name	T768
Test name
Test status
Simulation time	300214627 ps
CPU time	4.64 seconds
Started	Jun 09 02:26:01 PM PDT 24
Finished	Jun 09 02:26:07 PM PDT 24
Peak memory	218208 kb
Host	smart-64060b6a-6032-478f-8ab4-ed4e13edec3b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=144200315 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_smoke.144200315
Directory	/workspace/39.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/39.lc_ctrl_state_failure.1423680374
Short name	T285
Test name
Test status
Simulation time	335909098 ps
CPU time	30.33 seconds
Started	Jun 09 02:26:12 PM PDT 24
Finished	Jun 09 02:26:43 PM PDT 24
Peak memory	251432 kb
Host	smart-31e51845-cc46-4fde-9093-e47b73752add
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1423680374 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_failure.1423680374
Directory	/workspace/39.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/39.lc_ctrl_state_post_trans.3443405529
Short name	T158
Test name
Test status
Simulation time	111640725 ps
CPU time	3.21 seconds
Started	Jun 09 02:26:02 PM PDT 24
Finished	Jun 09 02:26:05 PM PDT 24
Peak memory	222944 kb
Host	smart-91453a17-43b3-4fe7-b29a-80922535162f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3443405529 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_post_trans.3443405529
Directory	/workspace/39.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/39.lc_ctrl_stress_all.1431378182
Short name	T42
Test name
Test status
Simulation time	28555115029 ps
CPU time	149.7 seconds
Started	Jun 09 02:26:12 PM PDT 24
Finished	Jun 09 02:28:42 PM PDT 24
Peak memory	283108 kb
Host	smart-40479afa-fd7a-4b51-9c96-40073f63dc62
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431378182 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_stress_all.1431378182
Directory	/workspace/39.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/4.lc_ctrl_alert_test.2254546587
Short name	T512
Test name
Test status
Simulation time	52516953 ps
CPU time	0.85 seconds
Started	Jun 09 02:24:41 PM PDT 24
Finished	Jun 09 02:24:42 PM PDT 24
Peak memory	209432 kb
Host	smart-d173ee12-ebd5-4b06-b378-b1d3417ab185
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254546587 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_alert_test.2254546587
Directory	/workspace/4.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/4.lc_ctrl_claim_transition_if.3395387031
Short name	T208
Test name
Test status
Simulation time	10941307 ps
CPU time	0.91 seconds
Started	Jun 09 02:24:43 PM PDT 24
Finished	Jun 09 02:24:44 PM PDT 24
Peak memory	209436 kb
Host	smart-3db90fbd-e4eb-4cd8-b7ed-79866571a676
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3395387031 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_claim_transition_if.3395387031
Directory	/workspace/4.lc_ctrl_claim_transition_if/latest

Test location	/workspace/coverage/default/4.lc_ctrl_errors.1494968745
Short name	T302
Test name
Test status
Simulation time	214077911 ps
CPU time	9.89 seconds
Started	Jun 09 02:24:31 PM PDT 24
Finished	Jun 09 02:24:42 PM PDT 24
Peak memory	218720 kb
Host	smart-01404c2d-37e3-43af-97bc-77d09d22f39a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1494968745 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_errors.1494968745
Directory	/workspace/4.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/4.lc_ctrl_jtag_access.3241455974
Short name	T32
Test name
Test status
Simulation time	1105989168 ps
CPU time	3.21 seconds
Started	Jun 09 02:24:36 PM PDT 24
Finished	Jun 09 02:24:40 PM PDT 24
Peak memory	217632 kb
Host	smart-fe394ef6-7aea-4b0a-99df-66840c2bf141
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241455974 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_access.3241455974
Directory	/workspace/4.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/4.lc_ctrl_jtag_errors.3561417355
Short name	T534
Test name
Test status
Simulation time	6267471739 ps
CPU time	53.38 seconds
Started	Jun 09 02:24:38 PM PDT 24
Finished	Jun 09 02:25:31 PM PDT 24
Peak memory	219412 kb
Host	smart-421c9bfc-6cb9-4034-812c-7773adfc6150
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561417355 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_er rors.3561417355
Directory	/workspace/4.lc_ctrl_jtag_errors/latest

Test location	/workspace/coverage/default/4.lc_ctrl_jtag_priority.1337529931
Short name	T245
Test name
Test status
Simulation time	694867097 ps
CPU time	17.49 seconds
Started	Jun 09 02:24:39 PM PDT 24
Finished	Jun 09 02:24:57 PM PDT 24
Peak memory	218304 kb
Host	smart-5cbb5a62-4ca0-4a0b-87c5-79cc9c495e07
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337529931 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_priority.1 337529931
Directory	/workspace/4.lc_ctrl_jtag_priority/latest

Test location	/workspace/coverage/default/4.lc_ctrl_jtag_prog_failure.2575169003
Short name	T536
Test name
Test status
Simulation time	322288152 ps
CPU time	10.47 seconds
Started	Jun 09 02:24:34 PM PDT 24
Finished	Jun 09 02:24:44 PM PDT 24
Peak memory	218704 kb
Host	smart-0b5f0aeb-79b3-4fdc-90f5-b7531e9b2ff1
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575169003 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag _prog_failure.2575169003
Directory	/workspace/4.lc_ctrl_jtag_prog_failure/latest

Test location	/workspace/coverage/default/4.lc_ctrl_jtag_regwen_during_op.1997609426
Short name	T381
Test name
Test status
Simulation time	12821022035 ps
CPU time	18.5 seconds
Started	Jun 09 02:24:38 PM PDT 24
Finished	Jun 09 02:24:56 PM PDT 24
Peak memory	218244 kb
Host	smart-133577cc-b1d1-4c6d-a182-d7b55d956228
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997609426 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_ jtag_regwen_during_op.1997609426
Directory	/workspace/4.lc_ctrl_jtag_regwen_during_op/latest

Test location	/workspace/coverage/default/4.lc_ctrl_jtag_smoke.4270807426
Short name	T435
Test name
Test status
Simulation time	344625464 ps
CPU time	5.83 seconds
Started	Jun 09 02:24:35 PM PDT 24
Finished	Jun 09 02:24:42 PM PDT 24
Peak memory	218232 kb
Host	smart-4ca7120d-f289-4acb-b3a8-a3c669d34223
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270807426 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_smoke. 4270807426
Directory	/workspace/4.lc_ctrl_jtag_smoke/latest

Test location	/workspace/coverage/default/4.lc_ctrl_jtag_state_failure.4256468155
Short name	T231
Test name
Test status
Simulation time	2404642566 ps
CPU time	37.42 seconds
Started	Jun 09 02:24:39 PM PDT 24
Finished	Jun 09 02:25:17 PM PDT 24
Peak memory	276284 kb
Host	smart-660aa1df-d6f8-41f7-bf79-75df29c61a16
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256468155 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jta g_state_failure.4256468155
Directory	/workspace/4.lc_ctrl_jtag_state_failure/latest

Test location	/workspace/coverage/default/4.lc_ctrl_jtag_state_post_trans.3147732278
Short name	T416
Test name
Test status
Simulation time	478279124 ps
CPU time	14.14 seconds
Started	Jun 09 02:24:38 PM PDT 24
Finished	Jun 09 02:24:53 PM PDT 24
Peak memory	251440 kb
Host	smart-97d60170-e84e-4454-88b5-43153d5a0697
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147732278 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_ jtag_state_post_trans.3147732278
Directory	/workspace/4.lc_ctrl_jtag_state_post_trans/latest

Test location	/workspace/coverage/default/4.lc_ctrl_prog_failure.3329270819
Short name	T332
Test name
Test status
Simulation time	50376226 ps
CPU time	2.87 seconds
Started	Jun 09 02:24:31 PM PDT 24
Finished	Jun 09 02:24:34 PM PDT 24
Peak memory	218680 kb
Host	smart-0a8a59b6-4a98-430c-bf24-5db24efb2186
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3329270819 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_prog_failure.3329270819
Directory	/workspace/4.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/4.lc_ctrl_regwen_during_op.2330026666
Short name	T65
Test name
Test status
Simulation time	330375458 ps
CPU time	8.53 seconds
Started	Jun 09 02:24:34 PM PDT 24
Finished	Jun 09 02:24:42 PM PDT 24
Peak memory	218192 kb
Host	smart-617f499e-eb5b-4469-be3c-b7cfbe9967fe
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2330026666 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_regwen_during_op.2330026666
Directory	/workspace/4.lc_ctrl_regwen_during_op/latest

Test location	/workspace/coverage/default/4.lc_ctrl_sec_cm.2780238007
Short name	T62
Test name
Test status
Simulation time	270943170 ps
CPU time	42.1 seconds
Started	Jun 09 02:24:36 PM PDT 24
Finished	Jun 09 02:25:18 PM PDT 24
Peak memory	282744 kb
Host	smart-5ae49e6b-c89d-4c9b-9c1a-40e86e73b42e
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780238007 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_cm.2780238007
Directory	/workspace/4.lc_ctrl_sec_cm/latest

Test location	/workspace/coverage/default/4.lc_ctrl_sec_mubi.3326153505
Short name	T517
Test name
Test status
Simulation time	2000771764 ps
CPU time	16.45 seconds
Started	Jun 09 02:24:40 PM PDT 24
Finished	Jun 09 02:24:57 PM PDT 24
Peak memory	218728 kb
Host	smart-630d4222-c1e4-4aa3-ba8c-7562bdd7cc60
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326153505 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_mubi.3326153505
Directory	/workspace/4.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/4.lc_ctrl_sec_token_digest.3398783098
Short name	T433
Test name
Test status
Simulation time	258134070 ps
CPU time	9.93 seconds
Started	Jun 09 02:24:43 PM PDT 24
Finished	Jun 09 02:24:53 PM PDT 24
Peak memory	226520 kb
Host	smart-fc7cd4fd-d115-4d65-a213-4e650af388bf
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398783098 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_di gest.3398783098
Directory	/workspace/4.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/4.lc_ctrl_security_escalation.562455374
Short name	T835
Test name
Test status
Simulation time	273144379 ps
CPU time	6.39 seconds
Started	Jun 09 02:24:37 PM PDT 24
Finished	Jun 09 02:24:44 PM PDT 24
Peak memory	218748 kb
Host	smart-443ae966-627b-4268-90c4-dae37d96afd3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=562455374 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_security_escalation.562455374
Directory	/workspace/4.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/4.lc_ctrl_smoke.595552397
Short name	T79
Test name
Test status
Simulation time	60471725 ps
CPU time	3.48 seconds
Started	Jun 09 02:24:33 PM PDT 24
Finished	Jun 09 02:24:37 PM PDT 24
Peak memory	218220 kb
Host	smart-23b1818b-4d56-4769-8cfb-89ecd29917b5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=595552397 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_smoke.595552397
Directory	/workspace/4.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/4.lc_ctrl_state_failure.142339136
Short name	T92
Test name
Test status
Simulation time	498977037 ps
CPU time	24.45 seconds
Started	Jun 09 02:24:43 PM PDT 24
Finished	Jun 09 02:25:08 PM PDT 24
Peak memory	251424 kb
Host	smart-50099eb9-432e-48f0-ab8a-fbe6e00a2d36
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=142339136 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_failure.142339136
Directory	/workspace/4.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/4.lc_ctrl_state_post_trans.1386519529
Short name	T18
Test name
Test status
Simulation time	49043222 ps
CPU time	8.04 seconds
Started	Jun 09 02:24:29 PM PDT 24
Finished	Jun 09 02:24:37 PM PDT 24
Peak memory	251420 kb
Host	smart-1997ee6a-26a1-42c2-ba6e-e6e247d9464f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1386519529 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_post_trans.1386519529
Directory	/workspace/4.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/4.lc_ctrl_stress_all.818972299
Short name	T179
Test name
Test status
Simulation time	87224642980 ps
CPU time	451.06 seconds
Started	Jun 09 02:24:30 PM PDT 24
Finished	Jun 09 02:32:01 PM PDT 24
Peak memory	284240 kb
Host	smart-a0f974e9-954c-4745-ade0-c3be514daa26
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818972299 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_ TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_stress_all.818972299
Directory	/workspace/4.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/4.lc_ctrl_volatile_unlock_smoke.1869682145
Short name	T93
Test name
Test status
Simulation time	27590276 ps
CPU time	0.86 seconds
Started	Jun 09 02:24:25 PM PDT 24
Finished	Jun 09 02:24:27 PM PDT 24
Peak memory	212324 kb
Host	smart-1cbaaeaf-d141-4104-9aa6-2fb2eabd518b
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869682145 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ct rl_volatile_unlock_smoke.1869682145
Directory	/workspace/4.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/40.lc_ctrl_alert_test.507441376
Short name	T707
Test name
Test status
Simulation time	64155523 ps
CPU time	1.08 seconds
Started	Jun 09 02:26:17 PM PDT 24
Finished	Jun 09 02:26:18 PM PDT 24
Peak memory	209260 kb
Host	smart-68da0b29-1227-447d-9d92-2308cb05b81f
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507441376 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_alert_test.507441376
Directory	/workspace/40.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/40.lc_ctrl_errors.1657502001
Short name	T472
Test name
Test status
Simulation time	482155625 ps
CPU time	18.01 seconds
Started	Jun 09 02:26:15 PM PDT 24
Finished	Jun 09 02:26:33 PM PDT 24
Peak memory	218656 kb
Host	smart-92e843f2-0f82-47dc-b214-5fb3f67c24ab
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1657502001 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_errors.1657502001
Directory	/workspace/40.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/40.lc_ctrl_jtag_access.3614274001
Short name	T799
Test name
Test status
Simulation time	464556103 ps
CPU time	3.03 seconds
Started	Jun 09 02:26:13 PM PDT 24
Finished	Jun 09 02:26:16 PM PDT 24
Peak memory	217624 kb
Host	smart-9b1512ac-e040-4a82-8fd2-044ba4958b8d
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614274001 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_jtag_access.3614274001
Directory	/workspace/40.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/40.lc_ctrl_prog_failure.2704105227
Short name	T652
Test name
Test status
Simulation time	40343466 ps
CPU time	2.72 seconds
Started	Jun 09 02:26:13 PM PDT 24
Finished	Jun 09 02:26:16 PM PDT 24
Peak memory	222640 kb
Host	smart-8017e004-5764-4ea0-9ca8-7b6454bdf3f7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2704105227 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_prog_failure.2704105227
Directory	/workspace/40.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/40.lc_ctrl_sec_mubi.644368932
Short name	T56
Test name
Test status
Simulation time	509448370 ps
CPU time	13.17 seconds
Started	Jun 09 02:26:22 PM PDT 24
Finished	Jun 09 02:26:35 PM PDT 24
Peak memory	218700 kb
Host	smart-51776542-a960-42bf-b591-10682962925d
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644368932 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_mubi.644368932
Directory	/workspace/40.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/40.lc_ctrl_sec_token_digest.3148168949
Short name	T736
Test name
Test status
Simulation time	736760716 ps
CPU time	15.92 seconds
Started	Jun 09 02:26:25 PM PDT 24
Finished	Jun 09 02:26:41 PM PDT 24
Peak memory	226536 kb
Host	smart-2c5310e2-1c07-46bd-b326-9569d1cebcff
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148168949 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_d igest.3148168949
Directory	/workspace/40.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/40.lc_ctrl_sec_token_mux.3320994282
Short name	T526
Test name
Test status
Simulation time	2988446144 ps
CPU time	7.13 seconds
Started	Jun 09 02:26:13 PM PDT 24
Finished	Jun 09 02:26:20 PM PDT 24
Peak memory	218760 kb
Host	smart-89640b28-7765-447c-97ac-51f3e1471e76
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320994282 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_mux. 3320994282
Directory	/workspace/40.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/40.lc_ctrl_smoke.1336015666
Short name	T94
Test name
Test status
Simulation time	35043158 ps
CPU time	2.85 seconds
Started	Jun 09 02:26:14 PM PDT 24
Finished	Jun 09 02:26:17 PM PDT 24
Peak memory	218292 kb
Host	smart-83dd0b20-53a0-4653-bbeb-f95af33a3008
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1336015666 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_smoke.1336015666
Directory	/workspace/40.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/40.lc_ctrl_state_failure.486120218
Short name	T238
Test name
Test status
Simulation time	2239677097 ps
CPU time	30.68 seconds
Started	Jun 09 02:26:19 PM PDT 24
Finished	Jun 09 02:26:50 PM PDT 24
Peak memory	251484 kb
Host	smart-b33782d3-9f53-42c6-9c8a-d39221e87652
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=486120218 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_failure.486120218
Directory	/workspace/40.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/40.lc_ctrl_state_post_trans.3055405730
Short name	T243
Test name
Test status
Simulation time	391280721 ps
CPU time	9.01 seconds
Started	Jun 09 02:26:11 PM PDT 24
Finished	Jun 09 02:26:20 PM PDT 24
Peak memory	251536 kb
Host	smart-383651cd-73e1-4d71-b924-9561ca9d13f9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3055405730 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_post_trans.3055405730
Directory	/workspace/40.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/40.lc_ctrl_stress_all.1171754421
Short name	T442
Test name
Test status
Simulation time	21494387053 ps
CPU time	163.31 seconds
Started	Jun 09 02:26:15 PM PDT 24
Finished	Jun 09 02:28:58 PM PDT 24
Peak memory	284312 kb
Host	smart-2246327e-716c-41b2-b658-69c10712f2fe
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171754421 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_stress_all.1171754421
Directory	/workspace/40.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/40.lc_ctrl_stress_all_with_rand_reset.602621000
Short name	T165
Test name
Test status
Simulation time	14093995935 ps
CPU time	374.66 seconds
Started	Jun 09 02:26:12 PM PDT 24
Finished	Jun 09 02:32:27 PM PDT 24
Peak memory	497300 kb
Host	smart-7bab7109-b61d-4d45-968d-4a9010e32139
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=602621000 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_stress_all_with_rand_reset.602621000
Directory	/workspace/40.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/40.lc_ctrl_volatile_unlock_smoke.3269655266
Short name	T372
Test name
Test status
Simulation time	36880226 ps
CPU time	1.02 seconds
Started	Jun 09 02:26:15 PM PDT 24
Finished	Jun 09 02:26:17 PM PDT 24
Peak memory	212424 kb
Host	smart-5224a772-18e4-4207-857e-6ac4e3f44471
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269655266 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_c trl_volatile_unlock_smoke.3269655266
Directory	/workspace/40.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/41.lc_ctrl_alert_test.4053132839
Short name	T763
Test name
Test status
Simulation time	25030393 ps
CPU time	0.99 seconds
Started	Jun 09 02:26:20 PM PDT 24
Finished	Jun 09 02:26:22 PM PDT 24
Peak memory	209348 kb
Host	smart-34e1ebac-4990-4013-990d-6e0f82aa6651
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053132839 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_alert_test.4053132839
Directory	/workspace/41.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/41.lc_ctrl_errors.419483082
Short name	T353
Test name
Test status
Simulation time	552215581 ps
CPU time	10.4 seconds
Started	Jun 09 02:26:10 PM PDT 24
Finished	Jun 09 02:26:20 PM PDT 24
Peak memory	218752 kb
Host	smart-b26936cc-9d03-413b-b784-8f0d936ff257
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=419483082 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_errors.419483082
Directory	/workspace/41.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/41.lc_ctrl_jtag_access.2608015271
Short name	T483
Test name
Test status
Simulation time	283085996 ps
CPU time	2.72 seconds
Started	Jun 09 02:26:14 PM PDT 24
Finished	Jun 09 02:26:16 PM PDT 24
Peak memory	217552 kb
Host	smart-258fb379-646c-4e73-bee0-f20125053aab
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608015271 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_jtag_access.2608015271
Directory	/workspace/41.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/41.lc_ctrl_prog_failure.35452778
Short name	T235
Test name
Test status
Simulation time	144267718 ps
CPU time	2.33 seconds
Started	Jun 09 02:26:12 PM PDT 24
Finished	Jun 09 02:26:15 PM PDT 24
Peak memory	222592 kb
Host	smart-623f2aed-d3ba-42da-942a-b6dc6a897584
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=35452778 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_prog_failure.35452778
Directory	/workspace/41.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/41.lc_ctrl_sec_mubi.2339720201
Short name	T645
Test name
Test status
Simulation time	1609255016 ps
CPU time	12.92 seconds
Started	Jun 09 02:26:14 PM PDT 24
Finished	Jun 09 02:26:27 PM PDT 24
Peak memory	218788 kb
Host	smart-87741294-a22a-417e-8b29-5e34313c6edd
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339720201 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_mubi.2339720201
Directory	/workspace/41.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/41.lc_ctrl_sec_token_digest.1985435760
Short name	T560
Test name
Test status
Simulation time	601897624 ps
CPU time	14.34 seconds
Started	Jun 09 02:26:12 PM PDT 24
Finished	Jun 09 02:26:26 PM PDT 24
Peak memory	218724 kb
Host	smart-2bc6d075-9853-4bf4-a5f4-7099b79155e7
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985435760 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_d igest.1985435760
Directory	/workspace/41.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/41.lc_ctrl_sec_token_mux.3384696865
Short name	T443
Test name
Test status
Simulation time	399240584 ps
CPU time	13.22 seconds
Started	Jun 09 02:26:19 PM PDT 24
Finished	Jun 09 02:26:32 PM PDT 24
Peak memory	218732 kb
Host	smart-5e87f978-736d-4bd1-be26-0bd4cab20b7e
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384696865 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_mux. 3384696865
Directory	/workspace/41.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/41.lc_ctrl_security_escalation.1647885969
Short name	T509
Test name
Test status
Simulation time	921728585 ps
CPU time	6.77 seconds
Started	Jun 09 02:26:12 PM PDT 24
Finished	Jun 09 02:26:20 PM PDT 24
Peak memory	226592 kb
Host	smart-f509ccd4-8f5f-4b84-925d-9380f9465385
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1647885969 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_security_escalation.1647885969
Directory	/workspace/41.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/41.lc_ctrl_smoke.494244391
Short name	T95
Test name
Test status
Simulation time	143730735 ps
CPU time	2.93 seconds
Started	Jun 09 02:26:18 PM PDT 24
Finished	Jun 09 02:26:21 PM PDT 24
Peak memory	215656 kb
Host	smart-25bac134-bfbe-4955-b613-f4e6e94bfcba
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=494244391 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_smoke.494244391
Directory	/workspace/41.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/41.lc_ctrl_state_failure.1191695881
Short name	T539
Test name
Test status
Simulation time	360959319 ps
CPU time	20.06 seconds
Started	Jun 09 02:26:21 PM PDT 24
Finished	Jun 09 02:26:41 PM PDT 24
Peak memory	251432 kb
Host	smart-6e0a38ad-3e36-43a9-a0cd-2c2dc59b0eeb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1191695881 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_failure.1191695881
Directory	/workspace/41.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/41.lc_ctrl_state_post_trans.3768312645
Short name	T755
Test name
Test status
Simulation time	218896673 ps
CPU time	7.75 seconds
Started	Jun 09 02:26:20 PM PDT 24
Finished	Jun 09 02:26:28 PM PDT 24
Peak memory	251416 kb
Host	smart-14b08f69-1225-4171-832d-b2400005f0e7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3768312645 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_post_trans.3768312645
Directory	/workspace/41.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/41.lc_ctrl_stress_all.2987666600
Short name	T803
Test name
Test status
Simulation time	4270328966 ps
CPU time	91.64 seconds
Started	Jun 09 02:26:15 PM PDT 24
Finished	Jun 09 02:27:47 PM PDT 24
Peak memory	267888 kb
Host	smart-daaf1f4c-50a6-4766-82fa-3a34c5e97e4a
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987666600 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_stress_all.2987666600
Directory	/workspace/41.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/41.lc_ctrl_stress_all_with_rand_reset.668143476
Short name	T150
Test name
Test status
Simulation time	364987337330 ps
CPU time	1176.75 seconds
Started	Jun 09 02:26:20 PM PDT 24
Finished	Jun 09 02:45:58 PM PDT 24
Peak memory	677612 kb
Host	smart-c30a63f5-d41f-4271-b11e-e145ccaf4775
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=668143476 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_stress_all_with_rand_reset.668143476
Directory	/workspace/41.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/41.lc_ctrl_volatile_unlock_smoke.4229652005
Short name	T671
Test name
Test status
Simulation time	42232989 ps
CPU time	0.91 seconds
Started	Jun 09 02:26:11 PM PDT 24
Finished	Jun 09 02:26:12 PM PDT 24
Peak memory	209444 kb
Host	smart-04dd2136-406c-453b-81b6-a9d3b8521a96
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229652005 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_c trl_volatile_unlock_smoke.4229652005
Directory	/workspace/41.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/42.lc_ctrl_alert_test.3141682147
Short name	T84
Test name
Test status
Simulation time	64629226 ps
CPU time	0.89 seconds
Started	Jun 09 02:26:14 PM PDT 24
Finished	Jun 09 02:26:15 PM PDT 24
Peak memory	209268 kb
Host	smart-aa88381d-a2ab-4a87-aad3-09625c06a1e6
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141682147 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_alert_test.3141682147
Directory	/workspace/42.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/42.lc_ctrl_errors.487499365
Short name	T732
Test name
Test status
Simulation time	961591291 ps
CPU time	16.22 seconds
Started	Jun 09 02:26:17 PM PDT 24
Finished	Jun 09 02:26:34 PM PDT 24
Peak memory	218748 kb
Host	smart-d9d89b31-507b-413a-be1e-d9504d0f79b8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=487499365 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_errors.487499365
Directory	/workspace/42.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/42.lc_ctrl_jtag_access.804293048
Short name	T676
Test name
Test status
Simulation time	87759040 ps
CPU time	2.99 seconds
Started	Jun 09 02:26:24 PM PDT 24
Finished	Jun 09 02:26:28 PM PDT 24
Peak memory	217612 kb
Host	smart-909a168b-9e3b-4d1c-955f-2cef67024697
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804293048 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_jtag_access.804293048
Directory	/workspace/42.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/42.lc_ctrl_prog_failure.980355278
Short name	T171
Test name
Test status
Simulation time	183148759 ps
CPU time	2.74 seconds
Started	Jun 09 02:26:13 PM PDT 24
Finished	Jun 09 02:26:16 PM PDT 24
Peak memory	222756 kb
Host	smart-70b0af95-b86e-4a40-89c6-39edff2f8d52
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=980355278 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_prog_failure.980355278
Directory	/workspace/42.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/42.lc_ctrl_sec_mubi.2820579227
Short name	T351
Test name
Test status
Simulation time	295596477 ps
CPU time	11.44 seconds
Started	Jun 09 02:26:15 PM PDT 24
Finished	Jun 09 02:26:27 PM PDT 24
Peak memory	219392 kb
Host	smart-0fdf30fb-21fd-41d4-b156-87d98030ac42
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820579227 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_mubi.2820579227
Directory	/workspace/42.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/42.lc_ctrl_sec_token_digest.1489113769
Short name	T603
Test name
Test status
Simulation time	1261440159 ps
CPU time	13.05 seconds
Started	Jun 09 02:26:15 PM PDT 24
Finished	Jun 09 02:26:29 PM PDT 24
Peak memory	218732 kb
Host	smart-3443e301-75b5-4720-a414-ef15c0732e8c
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489113769 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_d igest.1489113769
Directory	/workspace/42.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/42.lc_ctrl_sec_token_mux.2189249703
Short name	T758
Test name
Test status
Simulation time	295695929 ps
CPU time	8.19 seconds
Started	Jun 09 02:26:13 PM PDT 24
Finished	Jun 09 02:26:22 PM PDT 24
Peak memory	218692 kb
Host	smart-d4139ab3-37d1-43d6-aa0b-1b888f1792bc
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189249703 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_mux. 2189249703
Directory	/workspace/42.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/42.lc_ctrl_security_escalation.1802858813
Short name	T657
Test name
Test status
Simulation time	1890430773 ps
CPU time	10.47 seconds
Started	Jun 09 02:26:23 PM PDT 24
Finished	Jun 09 02:26:34 PM PDT 24
Peak memory	225124 kb
Host	smart-0c05d2ce-460b-4e28-b5b7-eca5229f1760
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1802858813 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_security_escalation.1802858813
Directory	/workspace/42.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/42.lc_ctrl_smoke.877033043
Short name	T104
Test name
Test status
Simulation time	28245011 ps
CPU time	2.2 seconds
Started	Jun 09 02:26:21 PM PDT 24
Finished	Jun 09 02:26:23 PM PDT 24
Peak memory	214688 kb
Host	smart-3c081d26-ab02-4e17-b01a-760c5a40a259
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=877033043 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_smoke.877033043
Directory	/workspace/42.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/42.lc_ctrl_state_failure.151550512
Short name	T410
Test name
Test status
Simulation time	782619807 ps
CPU time	29.05 seconds
Started	Jun 09 02:26:18 PM PDT 24
Finished	Jun 09 02:26:47 PM PDT 24
Peak memory	251380 kb
Host	smart-2fbacaee-9d55-4981-ad5d-216422133856
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=151550512 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_failure.151550512
Directory	/workspace/42.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/42.lc_ctrl_state_post_trans.2612150949
Short name	T391
Test name
Test status
Simulation time	136992639 ps
CPU time	6.39 seconds
Started	Jun 09 02:26:12 PM PDT 24
Finished	Jun 09 02:26:19 PM PDT 24
Peak memory	247792 kb
Host	smart-c667a2a1-2fa5-4f9d-9bc9-309a3a7e6090
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2612150949 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_post_trans.2612150949
Directory	/workspace/42.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/42.lc_ctrl_stress_all.663057360
Short name	T866
Test name
Test status
Simulation time	4962365393 ps
CPU time	48.58 seconds
Started	Jun 09 02:26:12 PM PDT 24
Finished	Jun 09 02:27:01 PM PDT 24
Peak memory	272520 kb
Host	smart-23bb899a-75cc-4eb6-a1ce-bcf55bc7d148
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663057360 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_ TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_stress_all.663057360
Directory	/workspace/42.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/42.lc_ctrl_stress_all_with_rand_reset.2725490960
Short name	T152
Test name
Test status
Simulation time	6799799486 ps
CPU time	163.63 seconds
Started	Jun 09 02:26:17 PM PDT 24
Finished	Jun 09 02:29:01 PM PDT 24
Peak memory	333520 kb
Host	smart-ac14458c-a7c0-47a7-9a1e-d8d4ae8e8af4
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=2725490960 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_stress_all_with_rand_reset.2725490960
Directory	/workspace/42.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/42.lc_ctrl_volatile_unlock_smoke.4132531607
Short name	T74
Test name
Test status
Simulation time	12765337 ps
CPU time	1.13 seconds
Started	Jun 09 02:26:23 PM PDT 24
Finished	Jun 09 02:26:25 PM PDT 24
Peak memory	212392 kb
Host	smart-26b21f9f-9121-4872-b069-6c96723aa9f4
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132531607 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_c trl_volatile_unlock_smoke.4132531607
Directory	/workspace/42.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/43.lc_ctrl_alert_test.1712971763
Short name	T350
Test name
Test status
Simulation time	30303977 ps
CPU time	1.11 seconds
Started	Jun 09 02:26:17 PM PDT 24
Finished	Jun 09 02:26:18 PM PDT 24
Peak memory	209384 kb
Host	smart-f228e1d4-005e-44ea-a9d5-dfb53c5c7a8d
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712971763 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_alert_test.1712971763
Directory	/workspace/43.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/43.lc_ctrl_errors.2778685423
Short name	T453
Test name
Test status
Simulation time	1194781288 ps
CPU time	16.88 seconds
Started	Jun 09 02:26:20 PM PDT 24
Finished	Jun 09 02:26:37 PM PDT 24
Peak memory	218588 kb
Host	smart-6eda32d3-dd27-45d3-a8d8-6055f199e8ff
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2778685423 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_errors.2778685423
Directory	/workspace/43.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/43.lc_ctrl_jtag_access.1474832808
Short name	T844
Test name
Test status
Simulation time	891393292 ps
CPU time	9 seconds
Started	Jun 09 02:26:22 PM PDT 24
Finished	Jun 09 02:26:32 PM PDT 24
Peak memory	217872 kb
Host	smart-91b10ac8-ca66-4567-b4e1-c13f72fee38c
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474832808 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_jtag_access.1474832808
Directory	/workspace/43.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/43.lc_ctrl_prog_failure.165565009
Short name	T557
Test name
Test status
Simulation time	113927332 ps
CPU time	3.57 seconds
Started	Jun 09 02:26:16 PM PDT 24
Finished	Jun 09 02:26:20 PM PDT 24
Peak memory	218692 kb
Host	smart-759d4abf-6dcd-4500-9a25-85c2bd0e304f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=165565009 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_prog_failure.165565009
Directory	/workspace/43.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/43.lc_ctrl_sec_mubi.3929388937
Short name	T614
Test name
Test status
Simulation time	3306809065 ps
CPU time	18.52 seconds
Started	Jun 09 02:26:10 PM PDT 24
Finished	Jun 09 02:26:28 PM PDT 24
Peak memory	226644 kb
Host	smart-e2fe845e-e590-42ca-8560-15e8f24eddde
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929388937 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_mubi.3929388937
Directory	/workspace/43.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/43.lc_ctrl_sec_token_digest.3847533823
Short name	T445
Test name
Test status
Simulation time	229823299 ps
CPU time	10.56 seconds
Started	Jun 09 02:26:25 PM PDT 24
Finished	Jun 09 02:26:36 PM PDT 24
Peak memory	218720 kb
Host	smart-8dfc0840-c299-4428-a60e-d4eda92c73c4
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847533823 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_d igest.3847533823
Directory	/workspace/43.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/43.lc_ctrl_sec_token_mux.20534196
Short name	T234
Test name
Test status
Simulation time	955644744 ps
CPU time	9.92 seconds
Started	Jun 09 02:26:18 PM PDT 24
Finished	Jun 09 02:26:29 PM PDT 24
Peak memory	218704 kb
Host	smart-df5fe1bb-bc69-4185-b665-92df4f9fb380
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20534196 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_mux.20534196
Directory	/workspace/43.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/43.lc_ctrl_security_escalation.2914364123
Short name	T91
Test name
Test status
Simulation time	543381077 ps
CPU time	7.69 seconds
Started	Jun 09 02:26:16 PM PDT 24
Finished	Jun 09 02:26:24 PM PDT 24
Peak memory	226508 kb
Host	smart-49fc98fa-32de-4ec0-a336-ecded2a60332
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2914364123 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_security_escalation.2914364123
Directory	/workspace/43.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/43.lc_ctrl_smoke.4240740854
Short name	T333
Test name
Test status
Simulation time	190618320 ps
CPU time	3.41 seconds
Started	Jun 09 02:26:15 PM PDT 24
Finished	Jun 09 02:26:19 PM PDT 24
Peak memory	218200 kb
Host	smart-f9618d5f-baa8-4da3-a7a0-e3e8a8336503
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4240740854 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_smoke.4240740854
Directory	/workspace/43.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/43.lc_ctrl_state_failure.412087150
Short name	T327
Test name
Test status
Simulation time	1178229474 ps
CPU time	21.25 seconds
Started	Jun 09 02:26:13 PM PDT 24
Finished	Jun 09 02:26:34 PM PDT 24
Peak memory	251484 kb
Host	smart-f548fb13-c64b-47d8-8493-f41d2c725f4d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=412087150 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_failure.412087150
Directory	/workspace/43.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/43.lc_ctrl_state_post_trans.180949286
Short name	T237
Test name
Test status
Simulation time	277037002 ps
CPU time	3.1 seconds
Started	Jun 09 02:26:14 PM PDT 24
Finished	Jun 09 02:26:18 PM PDT 24
Peak memory	226832 kb
Host	smart-973d37cf-cadf-4eb4-b4f1-0bf9da9a47f8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=180949286 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_post_trans.180949286
Directory	/workspace/43.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/43.lc_ctrl_stress_all.319947348
Short name	T667
Test name
Test status
Simulation time	3728369482 ps
CPU time	56.51 seconds
Started	Jun 09 02:26:16 PM PDT 24
Finished	Jun 09 02:27:13 PM PDT 24
Peak memory	249668 kb
Host	smart-40dffd06-7fe4-4819-b2fa-560f7e3ce512
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319947348 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_ TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_stress_all.319947348
Directory	/workspace/43.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/43.lc_ctrl_volatile_unlock_smoke.3656117481
Short name	T735
Test name
Test status
Simulation time	29484848 ps
CPU time	1.03 seconds
Started	Jun 09 02:26:15 PM PDT 24
Finished	Jun 09 02:26:17 PM PDT 24
Peak memory	212384 kb
Host	smart-9d643d6a-f4de-492d-a11e-36139b4f2f98
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656117481 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_c trl_volatile_unlock_smoke.3656117481
Directory	/workspace/43.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/44.lc_ctrl_alert_test.60267949
Short name	T488
Test name
Test status
Simulation time	21769130 ps
CPU time	0.98 seconds
Started	Jun 09 02:26:22 PM PDT 24
Finished	Jun 09 02:26:23 PM PDT 24
Peak memory	209432 kb
Host	smart-1440bc62-1243-4c6b-bb16-8f0b007e0607
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60267949 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_alert_test.60267949
Directory	/workspace/44.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/44.lc_ctrl_errors.2936315477
Short name	T49
Test name
Test status
Simulation time	765267233 ps
CPU time	9.19 seconds
Started	Jun 09 02:26:14 PM PDT 24
Finished	Jun 09 02:26:24 PM PDT 24
Peak memory	218824 kb
Host	smart-8cbcdcc8-9fb6-445d-a18e-24a4f34329fa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2936315477 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_errors.2936315477
Directory	/workspace/44.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/44.lc_ctrl_jtag_access.3283404134
Short name	T584
Test name
Test status
Simulation time	482021948 ps
CPU time	11.92 seconds
Started	Jun 09 02:26:16 PM PDT 24
Finished	Jun 09 02:26:28 PM PDT 24
Peak memory	217748 kb
Host	smart-c193d5ce-c3fd-4d30-96fc-9df890cab1dd
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283404134 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_jtag_access.3283404134
Directory	/workspace/44.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/44.lc_ctrl_prog_failure.3536731334
Short name	T580
Test name
Test status
Simulation time	395591735 ps
CPU time	4.53 seconds
Started	Jun 09 02:26:25 PM PDT 24
Finished	Jun 09 02:26:30 PM PDT 24
Peak memory	222664 kb
Host	smart-2ca75bd1-fbfc-4d65-b4bf-173763f6326f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3536731334 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_prog_failure.3536731334
Directory	/workspace/44.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/44.lc_ctrl_sec_mubi.1148695205
Short name	T313
Test name
Test status
Simulation time	2281946308 ps
CPU time	17.5 seconds
Started	Jun 09 02:26:14 PM PDT 24
Finished	Jun 09 02:26:32 PM PDT 24
Peak memory	219460 kb
Host	smart-87e3bbbd-065e-483b-8614-017506acc520
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148695205 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_mubi.1148695205
Directory	/workspace/44.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/44.lc_ctrl_sec_token_digest.284850139
Short name	T240
Test name
Test status
Simulation time	200401985 ps
CPU time	10.05 seconds
Started	Jun 09 02:26:15 PM PDT 24
Finished	Jun 09 02:26:26 PM PDT 24
Peak memory	226528 kb
Host	smart-5acc2d4d-60f1-431d-921c-6885589a01c1
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284850139 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_di gest.284850139
Directory	/workspace/44.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/44.lc_ctrl_sec_token_mux.1178285773
Short name	T500
Test name
Test status
Simulation time	5025102853 ps
CPU time	12.55 seconds
Started	Jun 09 02:26:15 PM PDT 24
Finished	Jun 09 02:26:28 PM PDT 24
Peak memory	218768 kb
Host	smart-77424a38-bc7d-41ac-9f4c-36b22c3b7380
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178285773 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_mux. 1178285773
Directory	/workspace/44.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/44.lc_ctrl_security_escalation.937418681
Short name	T858
Test name
Test status
Simulation time	884946183 ps
CPU time	9.61 seconds
Started	Jun 09 02:26:15 PM PDT 24
Finished	Jun 09 02:26:24 PM PDT 24
Peak memory	218772 kb
Host	smart-3d8149c9-c9cc-4f5b-8267-259af364b040
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=937418681 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_security_escalation.937418681
Directory	/workspace/44.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/44.lc_ctrl_smoke.2817111445
Short name	T326
Test name
Test status
Simulation time	157594360 ps
CPU time	3.15 seconds
Started	Jun 09 02:26:15 PM PDT 24
Finished	Jun 09 02:26:19 PM PDT 24
Peak memory	215228 kb
Host	smart-a3f1e47b-0327-476a-af77-7afbb85bae99
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2817111445 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_smoke.2817111445
Directory	/workspace/44.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/44.lc_ctrl_state_failure.185817807
Short name	T529
Test name
Test status
Simulation time	502705365 ps
CPU time	29.12 seconds
Started	Jun 09 02:26:16 PM PDT 24
Finished	Jun 09 02:26:45 PM PDT 24
Peak memory	251420 kb
Host	smart-ce33273a-bdd0-40be-a781-5fac9081ccbc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=185817807 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_failure.185817807
Directory	/workspace/44.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/44.lc_ctrl_state_post_trans.3842693767
Short name	T754
Test name
Test status
Simulation time	98978045 ps
CPU time	3 seconds
Started	Jun 09 02:26:16 PM PDT 24
Finished	Jun 09 02:26:19 PM PDT 24
Peak memory	224484 kb
Host	smart-7b2a9fa6-98d9-4c7a-bd33-f8112545c4f9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3842693767 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_post_trans.3842693767
Directory	/workspace/44.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/44.lc_ctrl_stress_all.2853649721
Short name	T749
Test name
Test status
Simulation time	16134389849 ps
CPU time	204.01 seconds
Started	Jun 09 02:26:21 PM PDT 24
Finished	Jun 09 02:29:45 PM PDT 24
Peak memory	496712 kb
Host	smart-62bea04d-f9d5-433a-9065-e56eab675880
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853649721 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_stress_all.2853649721
Directory	/workspace/44.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/44.lc_ctrl_volatile_unlock_smoke.3890039473
Short name	T444
Test name
Test status
Simulation time	34249211 ps
CPU time	0.91 seconds
Started	Jun 09 02:26:24 PM PDT 24
Finished	Jun 09 02:26:25 PM PDT 24
Peak memory	212592 kb
Host	smart-9eda3599-67d9-455f-8238-09d0c92be2a3
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890039473 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_c trl_volatile_unlock_smoke.3890039473
Directory	/workspace/44.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/45.lc_ctrl_alert_test.1429419576
Short name	T808
Test name
Test status
Simulation time	16786072 ps
CPU time	0.9 seconds
Started	Jun 09 02:26:21 PM PDT 24
Finished	Jun 09 02:26:22 PM PDT 24
Peak memory	209432 kb
Host	smart-82446ff0-e90a-4904-9f19-69daf337042f
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429419576 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_alert_test.1429419576
Directory	/workspace/45.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/45.lc_ctrl_errors.2511778005
Short name	T638
Test name
Test status
Simulation time	1951415424 ps
CPU time	11.31 seconds
Started	Jun 09 02:26:24 PM PDT 24
Finished	Jun 09 02:26:36 PM PDT 24
Peak memory	218684 kb
Host	smart-699b9ffa-8a7b-4771-aa9b-1adfc55b28f1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2511778005 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_errors.2511778005
Directory	/workspace/45.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/45.lc_ctrl_jtag_access.1689273581
Short name	T34
Test name
Test status
Simulation time	371591390 ps
CPU time	4.88 seconds
Started	Jun 09 02:26:16 PM PDT 24
Finished	Jun 09 02:26:22 PM PDT 24
Peak memory	218024 kb
Host	smart-13ed3e91-693c-4130-8407-6069b399404f
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689273581 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_jtag_access.1689273581
Directory	/workspace/45.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/45.lc_ctrl_prog_failure.94368343
Short name	T392
Test name
Test status
Simulation time	38675740 ps
CPU time	1.92 seconds
Started	Jun 09 02:26:14 PM PDT 24
Finished	Jun 09 02:26:16 PM PDT 24
Peak memory	222420 kb
Host	smart-f1366ab5-075c-43e1-b7a9-dda7dd76780d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=94368343 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_prog_failure.94368343
Directory	/workspace/45.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/45.lc_ctrl_sec_mubi.520848247
Short name	T366
Test name
Test status
Simulation time	1013048589 ps
CPU time	11.75 seconds
Started	Jun 09 02:26:20 PM PDT 24
Finished	Jun 09 02:26:32 PM PDT 24
Peak memory	226540 kb
Host	smart-1e3454d2-f1d7-42cd-8b44-06fb6e9f5ad3
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520848247 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_mubi.520848247
Directory	/workspace/45.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/45.lc_ctrl_sec_token_digest.1952593501
Short name	T741
Test name
Test status
Simulation time	246867260 ps
CPU time	11.05 seconds
Started	Jun 09 02:26:16 PM PDT 24
Finished	Jun 09 02:26:28 PM PDT 24
Peak memory	218716 kb
Host	smart-95c33d69-c39b-4640-9286-59a8000bb385
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952593501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_d igest.1952593501
Directory	/workspace/45.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/45.lc_ctrl_sec_token_mux.4077215372
Short name	T786
Test name
Test status
Simulation time	478784425 ps
CPU time	8.97 seconds
Started	Jun 09 02:26:26 PM PDT 24
Finished	Jun 09 02:26:35 PM PDT 24
Peak memory	218716 kb
Host	smart-9b5f6a78-b90c-4932-badd-32329c205018
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077215372 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_mux. 4077215372
Directory	/workspace/45.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/45.lc_ctrl_security_escalation.1089178442
Short name	T39
Test name
Test status
Simulation time	352923549 ps
CPU time	12.69 seconds
Started	Jun 09 02:26:22 PM PDT 24
Finished	Jun 09 02:26:35 PM PDT 24
Peak memory	225652 kb
Host	smart-dfe4f04e-66bb-4809-bfcf-87485986f454
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1089178442 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_security_escalation.1089178442
Directory	/workspace/45.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/45.lc_ctrl_smoke.2961821565
Short name	T675
Test name
Test status
Simulation time	440442435 ps
CPU time	3.07 seconds
Started	Jun 09 02:26:16 PM PDT 24
Finished	Jun 09 02:26:19 PM PDT 24
Peak memory	215288 kb
Host	smart-ca3e0f82-e860-4e44-9598-ac7bc3dc95fd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2961821565 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_smoke.2961821565
Directory	/workspace/45.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/45.lc_ctrl_state_failure.3941155563
Short name	T459
Test name
Test status
Simulation time	2157798826 ps
CPU time	29.45 seconds
Started	Jun 09 02:26:30 PM PDT 24
Finished	Jun 09 02:27:00 PM PDT 24
Peak memory	251504 kb
Host	smart-78d6deca-1568-4bd4-ab63-57a0e350014d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3941155563 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_failure.3941155563
Directory	/workspace/45.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/45.lc_ctrl_state_post_trans.1633393770
Short name	T594
Test name
Test status
Simulation time	86839471 ps
CPU time	7.3 seconds
Started	Jun 09 02:26:17 PM PDT 24
Finished	Jun 09 02:26:24 PM PDT 24
Peak memory	251432 kb
Host	smart-f190d1d4-07c8-49e0-80a9-a782a3ea7928
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1633393770 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_post_trans.1633393770
Directory	/workspace/45.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/45.lc_ctrl_stress_all.1167613769
Short name	T605
Test name
Test status
Simulation time	4150139207 ps
CPU time	53.38 seconds
Started	Jun 09 02:26:18 PM PDT 24
Finished	Jun 09 02:27:11 PM PDT 24
Peak memory	273104 kb
Host	smart-b964a3e8-9b73-4a19-a861-e2466cf6e5ce
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167613769 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_stress_all.1167613769
Directory	/workspace/45.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/45.lc_ctrl_volatile_unlock_smoke.2014348946
Short name	T631
Test name
Test status
Simulation time	21797690 ps
CPU time	0.89 seconds
Started	Jun 09 02:26:12 PM PDT 24
Finished	Jun 09 02:26:13 PM PDT 24
Peak memory	209444 kb
Host	smart-756b167e-c898-4ac2-8b37-f9653bbceb57
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014348946 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_c trl_volatile_unlock_smoke.2014348946
Directory	/workspace/45.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/46.lc_ctrl_alert_test.2720767991
Short name	T818
Test name
Test status
Simulation time	65502605 ps
CPU time	0.97 seconds
Started	Jun 09 02:26:22 PM PDT 24
Finished	Jun 09 02:26:23 PM PDT 24
Peak memory	209544 kb
Host	smart-f3f710b2-b9b5-4df5-b259-b8c9be8e1e2f
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720767991 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_alert_test.2720767991
Directory	/workspace/46.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/46.lc_ctrl_errors.3921465315
Short name	T841
Test name
Test status
Simulation time	372289749 ps
CPU time	16.43 seconds
Started	Jun 09 02:26:25 PM PDT 24
Finished	Jun 09 02:26:42 PM PDT 24
Peak memory	218684 kb
Host	smart-d1a01fbd-908c-427f-8afd-ce543f357734
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3921465315 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_errors.3921465315
Directory	/workspace/46.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/46.lc_ctrl_jtag_access.2779833076
Short name	T33
Test name
Test status
Simulation time	128238465 ps
CPU time	3.41 seconds
Started	Jun 09 02:26:16 PM PDT 24
Finished	Jun 09 02:26:20 PM PDT 24
Peak memory	217508 kb
Host	smart-9fe5c30e-637b-454b-b3c3-e8d727897f43
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779833076 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_jtag_access.2779833076
Directory	/workspace/46.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/46.lc_ctrl_prog_failure.3033873558
Short name	T220
Test name
Test status
Simulation time	340366058 ps
CPU time	2.93 seconds
Started	Jun 09 02:26:20 PM PDT 24
Finished	Jun 09 02:26:23 PM PDT 24
Peak memory	218760 kb
Host	smart-bc1ae4cb-b7cc-4937-a7f2-6fd97d49436a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3033873558 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_prog_failure.3033873558
Directory	/workspace/46.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/46.lc_ctrl_sec_mubi.441445373
Short name	T821
Test name
Test status
Simulation time	1013979528 ps
CPU time	14.32 seconds
Started	Jun 09 02:26:16 PM PDT 24
Finished	Jun 09 02:26:30 PM PDT 24
Peak memory	226528 kb
Host	smart-0d59bad2-75f2-4c23-ad28-857c9d035190
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441445373 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_mubi.441445373
Directory	/workspace/46.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/46.lc_ctrl_sec_token_digest.1394792286
Short name	T805
Test name
Test status
Simulation time	174197957 ps
CPU time	8.46 seconds
Started	Jun 09 02:26:24 PM PDT 24
Finished	Jun 09 02:26:32 PM PDT 24
Peak memory	218740 kb
Host	smart-93b5d18e-ceff-45f5-8cd8-f9279d24e9b3
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394792286 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_d igest.1394792286
Directory	/workspace/46.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/46.lc_ctrl_sec_token_mux.4149285295
Short name	T485
Test name
Test status
Simulation time	2695137478 ps
CPU time	7.8 seconds
Started	Jun 09 02:26:21 PM PDT 24
Finished	Jun 09 02:26:30 PM PDT 24
Peak memory	218776 kb
Host	smart-e082585b-d3a9-4223-b781-070ae026b209
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149285295 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_mux. 4149285295
Directory	/workspace/46.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/46.lc_ctrl_security_escalation.1986984446
Short name	T298
Test name
Test status
Simulation time	1348407151 ps
CPU time	8.54 seconds
Started	Jun 09 02:26:18 PM PDT 24
Finished	Jun 09 02:26:27 PM PDT 24
Peak memory	226536 kb
Host	smart-a5632f76-8437-4bca-997a-72dedd62a7b6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1986984446 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_security_escalation.1986984446
Directory	/workspace/46.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/46.lc_ctrl_smoke.1156632611
Short name	T644
Test name
Test status
Simulation time	94909206 ps
CPU time	1.72 seconds
Started	Jun 09 02:26:22 PM PDT 24
Finished	Jun 09 02:26:24 PM PDT 24
Peak memory	218220 kb
Host	smart-d82a602f-3e59-498d-be1b-7373195e2c4e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1156632611 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_smoke.1156632611
Directory	/workspace/46.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/46.lc_ctrl_state_failure.1297955628
Short name	T559
Test name
Test status
Simulation time	647572334 ps
CPU time	33.29 seconds
Started	Jun 09 02:26:24 PM PDT 24
Finished	Jun 09 02:26:57 PM PDT 24
Peak memory	251424 kb
Host	smart-c7be8d19-3e40-4b4f-ab1c-5d1060031ed4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1297955628 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_failure.1297955628
Directory	/workspace/46.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/46.lc_ctrl_state_post_trans.923041797
Short name	T265
Test name
Test status
Simulation time	85582318 ps
CPU time	7.54 seconds
Started	Jun 09 02:26:18 PM PDT 24
Finished	Jun 09 02:26:26 PM PDT 24
Peak memory	251376 kb
Host	smart-6e584902-f9ff-403b-91c4-c3796f16cd55
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=923041797 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_post_trans.923041797
Directory	/workspace/46.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/46.lc_ctrl_stress_all.3809022002
Short name	T177
Test name
Test status
Simulation time	43633788136 ps
CPU time	210.08 seconds
Started	Jun 09 02:26:32 PM PDT 24
Finished	Jun 09 02:30:02 PM PDT 24
Peak memory	284160 kb
Host	smart-93ffa701-1c69-4ed5-a372-35315d3308ce
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809022002 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_stress_all.3809022002
Directory	/workspace/46.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/46.lc_ctrl_volatile_unlock_smoke.1768882735
Short name	T409
Test name
Test status
Simulation time	13983175 ps
CPU time	0.79 seconds
Started	Jun 09 02:26:21 PM PDT 24
Finished	Jun 09 02:26:22 PM PDT 24
Peak memory	209324 kb
Host	smart-8b9edaca-bce7-4f61-b2c8-b204d5cbd91c
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768882735 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_c trl_volatile_unlock_smoke.1768882735
Directory	/workspace/46.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/47.lc_ctrl_alert_test.3932382862
Short name	T520
Test name
Test status
Simulation time	110011837 ps
CPU time	1.08 seconds
Started	Jun 09 02:26:33 PM PDT 24
Finished	Jun 09 02:26:34 PM PDT 24
Peak memory	209436 kb
Host	smart-690432da-8c9d-4482-848d-3261d1794926
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932382862 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_alert_test.3932382862
Directory	/workspace/47.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/47.lc_ctrl_errors.4226518486
Short name	T828
Test name
Test status
Simulation time	431563700 ps
CPU time	12.98 seconds
Started	Jun 09 02:26:19 PM PDT 24
Finished	Jun 09 02:26:33 PM PDT 24
Peak memory	218704 kb
Host	smart-8c1d27db-08b7-49b1-83fb-15a0ad4cf1fe
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4226518486 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_errors.4226518486
Directory	/workspace/47.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/47.lc_ctrl_jtag_access.985558203
Short name	T548
Test name
Test status
Simulation time	894796208 ps
CPU time	3.74 seconds
Started	Jun 09 02:26:32 PM PDT 24
Finished	Jun 09 02:26:36 PM PDT 24
Peak memory	217764 kb
Host	smart-887692ca-ff25-4646-aa83-0a10f6b1cbc6
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985558203 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_jtag_access.985558203
Directory	/workspace/47.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/47.lc_ctrl_prog_failure.2003868403
Short name	T400
Test name
Test status
Simulation time	99598895 ps
CPU time	4.29 seconds
Started	Jun 09 02:26:23 PM PDT 24
Finished	Jun 09 02:26:27 PM PDT 24
Peak memory	218696 kb
Host	smart-0c1d0889-2903-47d3-b572-d1204b734d68
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2003868403 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_prog_failure.2003868403
Directory	/workspace/47.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/47.lc_ctrl_sec_mubi.3935918045
Short name	T856
Test name
Test status
Simulation time	498653360 ps
CPU time	15.33 seconds
Started	Jun 09 02:26:24 PM PDT 24
Finished	Jun 09 02:26:40 PM PDT 24
Peak memory	218960 kb
Host	smart-77438228-52a6-4d9c-887c-a7f042a9ad16
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935918045 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_mubi.3935918045
Directory	/workspace/47.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/47.lc_ctrl_sec_token_digest.4147715015
Short name	T511
Test name
Test status
Simulation time	262842248 ps
CPU time	9.25 seconds
Started	Jun 09 02:26:20 PM PDT 24
Finished	Jun 09 02:26:30 PM PDT 24
Peak memory	226536 kb
Host	smart-f9dc3678-d148-41ec-abc7-0e04dc44e938
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147715015 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_d igest.4147715015
Directory	/workspace/47.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/47.lc_ctrl_sec_token_mux.1490543864
Short name	T798
Test name
Test status
Simulation time	1342490902 ps
CPU time	10.36 seconds
Started	Jun 09 02:26:25 PM PDT 24
Finished	Jun 09 02:26:36 PM PDT 24
Peak memory	218748 kb
Host	smart-86a2c72f-3d70-4594-95ea-15d00a5bc4e3
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490543864 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_mux. 1490543864
Directory	/workspace/47.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/47.lc_ctrl_security_escalation.3068323881
Short name	T452
Test name
Test status
Simulation time	269773714 ps
CPU time	8.8 seconds
Started	Jun 09 02:26:22 PM PDT 24
Finished	Jun 09 02:26:31 PM PDT 24
Peak memory	224960 kb
Host	smart-a8496025-6126-42c0-b55d-fdfa416259c4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3068323881 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_security_escalation.3068323881
Directory	/workspace/47.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/47.lc_ctrl_smoke.3303149926
Short name	T309
Test name
Test status
Simulation time	23518139 ps
CPU time	1.25 seconds
Started	Jun 09 02:26:32 PM PDT 24
Finished	Jun 09 02:26:34 PM PDT 24
Peak memory	218240 kb
Host	smart-e899abf5-163f-4c17-80b7-69ab53d9505e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3303149926 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_smoke.3303149926
Directory	/workspace/47.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/47.lc_ctrl_state_failure.3176179926
Short name	T413
Test name
Test status
Simulation time	1426304821 ps
CPU time	30.11 seconds
Started	Jun 09 02:26:19 PM PDT 24
Finished	Jun 09 02:26:50 PM PDT 24
Peak memory	251404 kb
Host	smart-5683c8cb-bd07-47d1-902c-0eef9498e86d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3176179926 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_failure.3176179926
Directory	/workspace/47.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/47.lc_ctrl_state_post_trans.393080047
Short name	T810
Test name
Test status
Simulation time	141924890 ps
CPU time	7.5 seconds
Started	Jun 09 02:26:22 PM PDT 24
Finished	Jun 09 02:26:30 PM PDT 24
Peak memory	251428 kb
Host	smart-3cbb49ee-8206-4284-a5c1-8e634e149f63
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=393080047 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_post_trans.393080047
Directory	/workspace/47.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/47.lc_ctrl_stress_all.1940121935
Short name	T406
Test name
Test status
Simulation time	7006506864 ps
CPU time	222.76 seconds
Started	Jun 09 02:26:32 PM PDT 24
Finished	Jun 09 02:30:15 PM PDT 24
Peak memory	311716 kb
Host	smart-44acbb80-698a-40b1-a35a-abcc29522a30
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940121935 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_stress_all.1940121935
Directory	/workspace/47.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/47.lc_ctrl_volatile_unlock_smoke.3808479452
Short name	T161
Test name
Test status
Simulation time	11754967 ps
CPU time	0.93 seconds
Started	Jun 09 02:26:18 PM PDT 24
Finished	Jun 09 02:26:19 PM PDT 24
Peak memory	209432 kb
Host	smart-49149ad0-c108-4db6-9b24-a6b517c08a99
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808479452 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_c trl_volatile_unlock_smoke.3808479452
Directory	/workspace/47.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/48.lc_ctrl_alert_test.876450320
Short name	T634
Test name
Test status
Simulation time	109374447 ps
CPU time	0.97 seconds
Started	Jun 09 02:26:31 PM PDT 24
Finished	Jun 09 02:26:32 PM PDT 24
Peak memory	209340 kb
Host	smart-f145ee7e-0e8d-4851-8b5e-501d92e3d67a
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876450320 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_alert_test.876450320
Directory	/workspace/48.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/48.lc_ctrl_errors.346846590
Short name	T370
Test name
Test status
Simulation time	285768017 ps
CPU time	8.29 seconds
Started	Jun 09 02:26:32 PM PDT 24
Finished	Jun 09 02:26:40 PM PDT 24
Peak memory	218732 kb
Host	smart-74a61924-3dec-4eca-877a-47fa74d02ce0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=346846590 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_errors.346846590
Directory	/workspace/48.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/48.lc_ctrl_jtag_access.276642649
Short name	T475
Test name
Test status
Simulation time	6084748021 ps
CPU time	4.22 seconds
Started	Jun 09 02:26:22 PM PDT 24
Finished	Jun 09 02:26:27 PM PDT 24
Peak memory	218120 kb
Host	smart-f43221be-a426-485e-81ef-c518c4994e8b
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276642649 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_jtag_access.276642649
Directory	/workspace/48.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/48.lc_ctrl_prog_failure.632429450
Short name	T627
Test name
Test status
Simulation time	26673986 ps
CPU time	1.59 seconds
Started	Jun 09 02:26:25 PM PDT 24
Finished	Jun 09 02:26:27 PM PDT 24
Peak memory	218692 kb
Host	smart-0c83bc19-1edc-4e6c-a241-fd7c28eb35b8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=632429450 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_prog_failure.632429450
Directory	/workspace/48.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/48.lc_ctrl_sec_mubi.3628960156
Short name	T585
Test name
Test status
Simulation time	846195098 ps
CPU time	10.39 seconds
Started	Jun 09 02:26:22 PM PDT 24
Finished	Jun 09 02:26:33 PM PDT 24
Peak memory	218896 kb
Host	smart-a32f7efb-ca47-4123-a9d9-b90cc99af963
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628960156 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_mubi.3628960156
Directory	/workspace/48.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/48.lc_ctrl_sec_token_digest.1498526691
Short name	T504
Test name
Test status
Simulation time	309271414 ps
CPU time	9.87 seconds
Started	Jun 09 02:26:38 PM PDT 24
Finished	Jun 09 02:26:48 PM PDT 24
Peak memory	218720 kb
Host	smart-c7f0c012-0eea-4f48-956c-b03f75b49a15
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498526691 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_d igest.1498526691
Directory	/workspace/48.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/48.lc_ctrl_sec_token_mux.3701545844
Short name	T494
Test name
Test status
Simulation time	335450138 ps
CPU time	10.95 seconds
Started	Jun 09 02:26:39 PM PDT 24
Finished	Jun 09 02:26:51 PM PDT 24
Peak memory	226536 kb
Host	smart-a7e4dd5c-259f-4eb3-8848-618e6d5ed3d0
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701545844 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_mux. 3701545844
Directory	/workspace/48.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/48.lc_ctrl_security_escalation.3487043459
Short name	T211
Test name
Test status
Simulation time	1717306768 ps
CPU time	14.72 seconds
Started	Jun 09 02:26:22 PM PDT 24
Finished	Jun 09 02:26:37 PM PDT 24
Peak memory	226508 kb
Host	smart-877fe837-5fb8-4940-8158-2caeff96e0d1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3487043459 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_security_escalation.3487043459
Directory	/workspace/48.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/48.lc_ctrl_smoke.3543390355
Short name	T80
Test name
Test status
Simulation time	28910266 ps
CPU time	2.23 seconds
Started	Jun 09 02:26:19 PM PDT 24
Finished	Jun 09 02:26:21 PM PDT 24
Peak memory	214744 kb
Host	smart-38253cb1-4c8c-4fdf-9848-132af8752978
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3543390355 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_smoke.3543390355
Directory	/workspace/48.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/48.lc_ctrl_state_failure.1397688354
Short name	T396
Test name
Test status
Simulation time	1012636653 ps
CPU time	30.89 seconds
Started	Jun 09 02:26:30 PM PDT 24
Finished	Jun 09 02:27:01 PM PDT 24
Peak memory	251428 kb
Host	smart-1118621a-f81e-4cf1-b01f-175d3721be64
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1397688354 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_failure.1397688354
Directory	/workspace/48.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/48.lc_ctrl_state_post_trans.50549026
Short name	T782
Test name
Test status
Simulation time	140274766 ps
CPU time	3.14 seconds
Started	Jun 09 02:26:30 PM PDT 24
Finished	Jun 09 02:26:34 PM PDT 24
Peak memory	223120 kb
Host	smart-e1780e0b-2dd0-4b84-955e-b22e3e218f21
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=50549026 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_post_trans.50549026
Directory	/workspace/48.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/48.lc_ctrl_stress_all.1243249109
Short name	T660
Test name
Test status
Simulation time	26204606371 ps
CPU time	176.87 seconds
Started	Jun 09 02:26:22 PM PDT 24
Finished	Jun 09 02:29:20 PM PDT 24
Peak memory	276204 kb
Host	smart-a953bc2c-a866-44a8-9fcb-064ff5c2af57
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243249109 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_stress_all.1243249109
Directory	/workspace/48.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/48.lc_ctrl_volatile_unlock_smoke.2699421171
Short name	T157
Test name
Test status
Simulation time	26276510 ps
CPU time	0.84 seconds
Started	Jun 09 02:26:22 PM PDT 24
Finished	Jun 09 02:26:24 PM PDT 24
Peak memory	209576 kb
Host	smart-37fbc3d8-9e83-4ca9-a175-92482337b802
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699421171 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_c trl_volatile_unlock_smoke.2699421171
Directory	/workspace/48.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/49.lc_ctrl_alert_test.3588039129
Short name	T305
Test name
Test status
Simulation time	38059581 ps
CPU time	0.98 seconds
Started	Jun 09 02:26:26 PM PDT 24
Finished	Jun 09 02:26:27 PM PDT 24
Peak memory	209376 kb
Host	smart-536ec1a1-53c9-4378-9b73-e127304b9041
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588039129 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_alert_test.3588039129
Directory	/workspace/49.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/49.lc_ctrl_errors.3885642328
Short name	T478
Test name
Test status
Simulation time	466812975 ps
CPU time	14.13 seconds
Started	Jun 09 02:26:41 PM PDT 24
Finished	Jun 09 02:27:00 PM PDT 24
Peak memory	218772 kb
Host	smart-08468e2c-19b1-45b6-9dab-5a9b68926c9b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3885642328 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_errors.3885642328
Directory	/workspace/49.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/49.lc_ctrl_jtag_access.679046644
Short name	T712
Test name
Test status
Simulation time	590264829 ps
CPU time	13.87 seconds
Started	Jun 09 02:26:20 PM PDT 24
Finished	Jun 09 02:26:35 PM PDT 24
Peak memory	217900 kb
Host	smart-dece0718-f68c-41c9-9478-416e25fc3cc4
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679046644 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_jtag_access.679046644
Directory	/workspace/49.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/49.lc_ctrl_prog_failure.3797375924
Short name	T747
Test name
Test status
Simulation time	96373026 ps
CPU time	4.47 seconds
Started	Jun 09 02:26:22 PM PDT 24
Finished	Jun 09 02:26:27 PM PDT 24
Peak memory	218676 kb
Host	smart-d1fe4a0d-5739-4e3c-9e7f-a0207f5da0bc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3797375924 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_prog_failure.3797375924
Directory	/workspace/49.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/49.lc_ctrl_sec_mubi.4256627483
Short name	T714
Test name
Test status
Simulation time	1289022018 ps
CPU time	13.56 seconds
Started	Jun 09 02:26:24 PM PDT 24
Finished	Jun 09 02:26:39 PM PDT 24
Peak memory	219412 kb
Host	smart-9d917b00-8828-4045-8ee0-53ee415ba18b
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256627483 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_mubi.4256627483
Directory	/workspace/49.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/49.lc_ctrl_sec_token_digest.4113966528
Short name	T469
Test name
Test status
Simulation time	1857057578 ps
CPU time	17.31 seconds
Started	Jun 09 02:26:26 PM PDT 24
Finished	Jun 09 02:26:43 PM PDT 24
Peak memory	218720 kb
Host	smart-6a17a7ce-3675-46ef-be85-78ddcaaed219
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113966528 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_d igest.4113966528
Directory	/workspace/49.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/49.lc_ctrl_sec_token_mux.2497636968
Short name	T776
Test name
Test status
Simulation time	244438857 ps
CPU time	8.25 seconds
Started	Jun 09 02:26:23 PM PDT 24
Finished	Jun 09 02:26:31 PM PDT 24
Peak memory	218712 kb
Host	smart-a9779304-e439-4b73-8120-a215048353be
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497636968 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_mux. 2497636968
Directory	/workspace/49.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/49.lc_ctrl_security_escalation.834414250
Short name	T522
Test name
Test status
Simulation time	591169191 ps
CPU time	12.1 seconds
Started	Jun 09 02:26:29 PM PDT 24
Finished	Jun 09 02:26:41 PM PDT 24
Peak memory	226232 kb
Host	smart-43208920-a33e-4959-830d-0f1836b3fdeb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=834414250 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_security_escalation.834414250
Directory	/workspace/49.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/49.lc_ctrl_smoke.2056526207
Short name	T430
Test name
Test status
Simulation time	26874078 ps
CPU time	1.32 seconds
Started	Jun 09 02:26:21 PM PDT 24
Finished	Jun 09 02:26:23 PM PDT 24
Peak memory	214224 kb
Host	smart-2adbd8b2-73d9-4e4a-a9ff-0ad28b327e67
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2056526207 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_smoke.2056526207
Directory	/workspace/49.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/49.lc_ctrl_state_failure.3451043686
Short name	T282
Test name
Test status
Simulation time	381180935 ps
CPU time	37.95 seconds
Started	Jun 09 02:26:20 PM PDT 24
Finished	Jun 09 02:26:59 PM PDT 24
Peak memory	251412 kb
Host	smart-62886287-63a9-408f-9a4e-196cce382ab5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3451043686 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_failure.3451043686
Directory	/workspace/49.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/49.lc_ctrl_state_post_trans.1106897422
Short name	T357
Test name
Test status
Simulation time	80716158 ps
CPU time	8.81 seconds
Started	Jun 09 02:26:31 PM PDT 24
Finished	Jun 09 02:26:40 PM PDT 24
Peak memory	251352 kb
Host	smart-70c49bbb-2d89-4342-b758-93a3cf695be6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1106897422 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_post_trans.1106897422
Directory	/workspace/49.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/49.lc_ctrl_stress_all.223401121
Short name	T693
Test name
Test status
Simulation time	20992029928 ps
CPU time	105.03 seconds
Started	Jun 09 02:26:23 PM PDT 24
Finished	Jun 09 02:28:08 PM PDT 24
Peak memory	251488 kb
Host	smart-1be36911-45e8-42e6-8f40-9a6eed0dfcf5
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223401121 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_ TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_stress_all.223401121
Directory	/workspace/49.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/49.lc_ctrl_stress_all_with_rand_reset.3442958154
Short name	T153
Test name
Test status
Simulation time	25407172294 ps
CPU time	392.31 seconds
Started	Jun 09 02:26:23 PM PDT 24
Finished	Jun 09 02:32:56 PM PDT 24
Peak memory	333520 kb
Host	smart-9d0c2160-063d-498a-b72d-09d9a6b6875d
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=3442958154 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_stress_all_with_rand_reset.3442958154
Directory	/workspace/49.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/49.lc_ctrl_volatile_unlock_smoke.1659731690
Short name	T48
Test name
Test status
Simulation time	120659250 ps
CPU time	0.77 seconds
Started	Jun 09 02:26:32 PM PDT 24
Finished	Jun 09 02:26:33 PM PDT 24
Peak memory	209220 kb
Host	smart-c7728c6d-6ccb-4190-966b-28800e596a8b
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659731690 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_c trl_volatile_unlock_smoke.1659731690
Directory	/workspace/49.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/5.lc_ctrl_alert_test.1671165343
Short name	T284
Test name
Test status
Simulation time	47643751 ps
CPU time	0.97 seconds
Started	Jun 09 02:24:45 PM PDT 24
Finished	Jun 09 02:24:46 PM PDT 24
Peak memory	209432 kb
Host	smart-88a70f67-62a6-414b-877c-448cc8a97c01
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671165343 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_alert_test.1671165343
Directory	/workspace/5.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/5.lc_ctrl_claim_transition_if.2708874666
Short name	T203
Test name
Test status
Simulation time	20225573 ps
CPU time	0.78 seconds
Started	Jun 09 02:24:35 PM PDT 24
Finished	Jun 09 02:24:36 PM PDT 24
Peak memory	209452 kb
Host	smart-cfabb683-1f12-4f4f-b5cd-b931097cb51b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2708874666 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_claim_transition_if.2708874666
Directory	/workspace/5.lc_ctrl_claim_transition_if/latest

Test location	/workspace/coverage/default/5.lc_ctrl_errors.1043029511
Short name	T840
Test name
Test status
Simulation time	3940154630 ps
CPU time	10.24 seconds
Started	Jun 09 02:24:36 PM PDT 24
Finished	Jun 09 02:24:47 PM PDT 24
Peak memory	218680 kb
Host	smart-61352aa8-a25e-40cd-bb07-a9f53dc8df1a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1043029511 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_errors.1043029511
Directory	/workspace/5.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/5.lc_ctrl_jtag_access.2606776028
Short name	T848
Test name
Test status
Simulation time	3104443637 ps
CPU time	6.14 seconds
Started	Jun 09 02:24:40 PM PDT 24
Finished	Jun 09 02:24:47 PM PDT 24
Peak memory	218268 kb
Host	smart-15287d00-6657-4acb-9b84-db5b5353a64d
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606776028 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_access.2606776028
Directory	/workspace/5.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/5.lc_ctrl_jtag_errors.2942727087
Short name	T242
Test name
Test status
Simulation time	15571649322 ps
CPU time	29.47 seconds
Started	Jun 09 02:24:45 PM PDT 24
Finished	Jun 09 02:25:15 PM PDT 24
Peak memory	226480 kb
Host	smart-8b717123-8618-4514-8555-9f88855be644
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942727087 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_er rors.2942727087
Directory	/workspace/5.lc_ctrl_jtag_errors/latest

Test location	/workspace/coverage/default/5.lc_ctrl_jtag_priority.2565253
Short name	T99
Test name
Test status
Simulation time	673482945 ps
CPU time	2.26 seconds
Started	Jun 09 02:24:38 PM PDT 24
Finished	Jun 09 02:24:41 PM PDT 24
Peak memory	217912 kb
Host	smart-fdaac789-7041-43e9-a0a6-bcd681e64646
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565253 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priority_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_priority.2565253
Directory	/workspace/5.lc_ctrl_jtag_priority/latest

Test location	/workspace/coverage/default/5.lc_ctrl_jtag_prog_failure.1255250451
Short name	T414
Test name
Test status
Simulation time	275063520 ps
CPU time	3.33 seconds
Started	Jun 09 02:24:31 PM PDT 24
Finished	Jun 09 02:24:35 PM PDT 24
Peak memory	218708 kb
Host	smart-56646f75-ce53-45c2-9b59-d2d9b3cfd60d
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255250451 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag _prog_failure.1255250451
Directory	/workspace/5.lc_ctrl_jtag_prog_failure/latest

Test location	/workspace/coverage/default/5.lc_ctrl_jtag_regwen_during_op.111319528
Short name	T354
Test name
Test status
Simulation time	2228801913 ps
CPU time	15.39 seconds
Started	Jun 09 02:24:37 PM PDT 24
Finished	Jun 09 02:24:53 PM PDT 24
Peak memory	218288 kb
Host	smart-42316f6f-24bf-41e2-9900-4a5bf0fb1e63
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111319528 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_j tag_regwen_during_op.111319528
Directory	/workspace/5.lc_ctrl_jtag_regwen_during_op/latest

Test location	/workspace/coverage/default/5.lc_ctrl_jtag_smoke.1200195228
Short name	T22
Test name
Test status
Simulation time	1522890355 ps
CPU time	7.03 seconds
Started	Jun 09 02:24:45 PM PDT 24
Finished	Jun 09 02:24:52 PM PDT 24
Peak memory	218212 kb
Host	smart-8d662987-3f34-4a35-95f0-706bae371d20
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200195228 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_smoke. 1200195228
Directory	/workspace/5.lc_ctrl_jtag_smoke/latest

Test location	/workspace/coverage/default/5.lc_ctrl_jtag_state_failure.1518782643
Short name	T24
Test name
Test status
Simulation time	2405946799 ps
CPU time	49.71 seconds
Started	Jun 09 02:24:45 PM PDT 24
Finished	Jun 09 02:25:35 PM PDT 24
Peak memory	277396 kb
Host	smart-b02ad841-1463-4b7f-8ed0-29cf54948020
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518782643 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jta g_state_failure.1518782643
Directory	/workspace/5.lc_ctrl_jtag_state_failure/latest

Test location	/workspace/coverage/default/5.lc_ctrl_jtag_state_post_trans.3540289329
Short name	T106
Test name
Test status
Simulation time	4904178457 ps
CPU time	17.33 seconds
Started	Jun 09 02:24:30 PM PDT 24
Finished	Jun 09 02:24:47 PM PDT 24
Peak memory	251472 kb
Host	smart-ba1ed105-73b1-4ad0-adb6-7fce7c40c924
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540289329 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_ jtag_state_post_trans.3540289329
Directory	/workspace/5.lc_ctrl_jtag_state_post_trans/latest

Test location	/workspace/coverage/default/5.lc_ctrl_prog_failure.2943210681
Short name	T436
Test name
Test status
Simulation time	107496006 ps
CPU time	4.87 seconds
Started	Jun 09 02:24:30 PM PDT 24
Finished	Jun 09 02:24:35 PM PDT 24
Peak memory	223160 kb
Host	smart-5df23101-4ba9-4ed2-a664-9dab30123f8d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2943210681 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_prog_failure.2943210681
Directory	/workspace/5.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/5.lc_ctrl_regwen_during_op.567593683
Short name	T476
Test name
Test status
Simulation time	1932638458 ps
CPU time	17.1 seconds
Started	Jun 09 02:24:35 PM PDT 24
Finished	Jun 09 02:24:52 PM PDT 24
Peak memory	215084 kb
Host	smart-6a4a138a-f2a3-49b4-907c-c820367d4fc3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=567593683 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_regwen_during_op.567593683
Directory	/workspace/5.lc_ctrl_regwen_during_op/latest

Test location	/workspace/coverage/default/5.lc_ctrl_sec_mubi.2714715408
Short name	T541
Test name
Test status
Simulation time	1670488951 ps
CPU time	19.3 seconds
Started	Jun 09 02:24:41 PM PDT 24
Finished	Jun 09 02:25:00 PM PDT 24
Peak memory	220468 kb
Host	smart-a26e23a2-2a01-49fb-a0de-474750b6b0d6
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714715408 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_mubi.2714715408
Directory	/workspace/5.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/5.lc_ctrl_sec_token_digest.3955892194
Short name	T310
Test name
Test status
Simulation time	1152371171 ps
CPU time	22.86 seconds
Started	Jun 09 02:24:43 PM PDT 24
Finished	Jun 09 02:25:06 PM PDT 24
Peak memory	218728 kb
Host	smart-1fc53242-23a7-4fdb-92fc-9eb1e6ecf884
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955892194 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_di gest.3955892194
Directory	/workspace/5.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/5.lc_ctrl_sec_token_mux.4088983393
Short name	T342
Test name
Test status
Simulation time	557329685 ps
CPU time	7.48 seconds
Started	Jun 09 02:24:36 PM PDT 24
Finished	Jun 09 02:24:44 PM PDT 24
Peak memory	225296 kb
Host	smart-859b2d13-354f-44ef-b508-a80389dfadb4
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088983393 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_mux.4 088983393
Directory	/workspace/5.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/5.lc_ctrl_security_escalation.1946591383
Short name	T328
Test name
Test status
Simulation time	1234835778 ps
CPU time	7.65 seconds
Started	Jun 09 02:24:38 PM PDT 24
Finished	Jun 09 02:24:46 PM PDT 24
Peak memory	225512 kb
Host	smart-bbc4bcce-0e82-408a-b47f-409fe6df947b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1946591383 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_security_escalation.1946591383
Directory	/workspace/5.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/5.lc_ctrl_smoke.41382068
Short name	T412
Test name
Test status
Simulation time	254941021 ps
CPU time	2.41 seconds
Started	Jun 09 02:24:37 PM PDT 24
Finished	Jun 09 02:24:40 PM PDT 24
Peak memory	218224 kb
Host	smart-dd56079a-8e3c-49b5-aa0a-1d6fcb5e93e0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=41382068 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_smoke.41382068
Directory	/workspace/5.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/5.lc_ctrl_state_failure.2562467065
Short name	T219
Test name
Test status
Simulation time	187128609 ps
CPU time	23.13 seconds
Started	Jun 09 02:24:28 PM PDT 24
Finished	Jun 09 02:24:52 PM PDT 24
Peak memory	251572 kb
Host	smart-14a8cb71-4d6f-4979-aed0-1aa824943c35
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2562467065 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_failure.2562467065
Directory	/workspace/5.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/5.lc_ctrl_state_post_trans.1540736925
Short name	T423
Test name
Test status
Simulation time	80455245 ps
CPU time	3.98 seconds
Started	Jun 09 02:24:38 PM PDT 24
Finished	Jun 09 02:24:43 PM PDT 24
Peak memory	222564 kb
Host	smart-f7f7bc68-7a48-4443-8300-9e881ad6fbc0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1540736925 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_post_trans.1540736925
Directory	/workspace/5.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/5.lc_ctrl_stress_all.1985867953
Short name	T272
Test name
Test status
Simulation time	4968737816 ps
CPU time	179.93 seconds
Started	Jun 09 02:24:37 PM PDT 24
Finished	Jun 09 02:27:37 PM PDT 24
Peak memory	250524 kb
Host	smart-07562c0c-1c64-4530-9d47-14df0ecde144
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985867953 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_stress_all.1985867953
Directory	/workspace/5.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/5.lc_ctrl_volatile_unlock_smoke.4229730132
Short name	T717
Test name
Test status
Simulation time	49888385 ps
CPU time	0.82 seconds
Started	Jun 09 02:24:41 PM PDT 24
Finished	Jun 09 02:24:42 PM PDT 24
Peak memory	209356 kb
Host	smart-9eb672d3-a7e6-4257-9d0c-c2f22179a43b
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229730132 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ct rl_volatile_unlock_smoke.4229730132
Directory	/workspace/5.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/6.lc_ctrl_alert_test.2732546482
Short name	T727
Test name
Test status
Simulation time	26702348 ps
CPU time	1.04 seconds
Started	Jun 09 02:24:42 PM PDT 24
Finished	Jun 09 02:24:43 PM PDT 24
Peak memory	209460 kb
Host	smart-e5e16f2a-63a2-478c-a62f-5059707b635c
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732546482 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_alert_test.2732546482
Directory	/workspace/6.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/6.lc_ctrl_claim_transition_if.2969344792
Short name	T612
Test name
Test status
Simulation time	30591537 ps
CPU time	0.86 seconds
Started	Jun 09 02:24:35 PM PDT 24
Finished	Jun 09 02:24:36 PM PDT 24
Peak memory	209504 kb
Host	smart-0da33489-5f22-4750-a882-93729a2ab5cc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2969344792 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_claim_transition_if.2969344792
Directory	/workspace/6.lc_ctrl_claim_transition_if/latest

Test location	/workspace/coverage/default/6.lc_ctrl_errors.4134239301
Short name	T751
Test name
Test status
Simulation time	330724193 ps
CPU time	12.65 seconds
Started	Jun 09 02:24:44 PM PDT 24
Finished	Jun 09 02:24:57 PM PDT 24
Peak memory	218704 kb
Host	smart-453c3342-3abd-4119-b790-ab24df18312b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4134239301 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_errors.4134239301
Directory	/workspace/6.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/6.lc_ctrl_jtag_access.2819963020
Short name	T533
Test name
Test status
Simulation time	198726123 ps
CPU time	5.53 seconds
Started	Jun 09 02:24:45 PM PDT 24
Finished	Jun 09 02:24:51 PM PDT 24
Peak memory	217668 kb
Host	smart-04c981ef-34db-4557-bb77-0966bace127f
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819963020 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_access.2819963020
Directory	/workspace/6.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/6.lc_ctrl_jtag_errors.1708278021
Short name	T711
Test name
Test status
Simulation time	2960747579 ps
CPU time	26.61 seconds
Started	Jun 09 02:24:40 PM PDT 24
Finished	Jun 09 02:25:07 PM PDT 24
Peak memory	226624 kb
Host	smart-78550ee0-4998-499a-bc42-8019e0b4995d
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708278021 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_er rors.1708278021
Directory	/workspace/6.lc_ctrl_jtag_errors/latest

Test location	/workspace/coverage/default/6.lc_ctrl_jtag_priority.4124762518
Short name	T505
Test name
Test status
Simulation time	602858658 ps
CPU time	4.29 seconds
Started	Jun 09 02:24:43 PM PDT 24
Finished	Jun 09 02:24:48 PM PDT 24
Peak memory	217824 kb
Host	smart-69f3df9e-e668-408f-abe7-0425cefaf6c0
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124762518 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_priority.4 124762518
Directory	/workspace/6.lc_ctrl_jtag_priority/latest

Test location	/workspace/coverage/default/6.lc_ctrl_jtag_prog_failure.4186427571
Short name	T780
Test name
Test status
Simulation time	325049922 ps
CPU time	5.64 seconds
Started	Jun 09 02:24:43 PM PDT 24
Finished	Jun 09 02:24:49 PM PDT 24
Peak memory	218664 kb
Host	smart-7c674ad3-685e-4ea9-88b8-353d3c03a312
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186427571 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag _prog_failure.4186427571
Directory	/workspace/6.lc_ctrl_jtag_prog_failure/latest

Test location	/workspace/coverage/default/6.lc_ctrl_jtag_regwen_during_op.2806727330
Short name	T482
Test name
Test status
Simulation time	4866712066 ps
CPU time	37.86 seconds
Started	Jun 09 02:24:37 PM PDT 24
Finished	Jun 09 02:25:15 PM PDT 24
Peak memory	218264 kb
Host	smart-a65db378-16c6-461f-96a9-695cbcd31b58
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806727330 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_ jtag_regwen_during_op.2806727330
Directory	/workspace/6.lc_ctrl_jtag_regwen_during_op/latest

Test location	/workspace/coverage/default/6.lc_ctrl_jtag_smoke.1155240474
Short name	T361
Test name
Test status
Simulation time	2967549561 ps
CPU time	5.91 seconds
Started	Jun 09 02:24:40 PM PDT 24
Finished	Jun 09 02:24:46 PM PDT 24
Peak memory	218288 kb
Host	smart-0f1b7b06-ad79-4bb5-b5bb-08247c885500
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155240474 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_smoke. 1155240474
Directory	/workspace/6.lc_ctrl_jtag_smoke/latest

Test location	/workspace/coverage/default/6.lc_ctrl_jtag_state_failure.3776541313
Short name	T791
Test name
Test status
Simulation time	1001401712 ps
CPU time	38.23 seconds
Started	Jun 09 02:24:41 PM PDT 24
Finished	Jun 09 02:25:19 PM PDT 24
Peak memory	251416 kb
Host	smart-e44f42ac-55ff-420b-8cdb-79d67f2a49fd
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776541313 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jta g_state_failure.3776541313
Directory	/workspace/6.lc_ctrl_jtag_state_failure/latest

Test location	/workspace/coverage/default/6.lc_ctrl_jtag_state_post_trans.1167693767
Short name	T291
Test name
Test status
Simulation time	474836091 ps
CPU time	15.31 seconds
Started	Jun 09 02:24:44 PM PDT 24
Finished	Jun 09 02:25:00 PM PDT 24
Peak memory	251376 kb
Host	smart-ae4d9ee5-a38b-4c2f-bccf-761817b17648
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167693767 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_ jtag_state_post_trans.1167693767
Directory	/workspace/6.lc_ctrl_jtag_state_post_trans/latest

Test location	/workspace/coverage/default/6.lc_ctrl_prog_failure.2796536973
Short name	T766
Test name
Test status
Simulation time	228135138 ps
CPU time	2.78 seconds
Started	Jun 09 02:24:43 PM PDT 24
Finished	Jun 09 02:24:46 PM PDT 24
Peak memory	222924 kb
Host	smart-5090b8dc-0cb2-4254-9d99-c0317e0b5aa1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2796536973 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_prog_failure.2796536973
Directory	/workspace/6.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/6.lc_ctrl_sec_mubi.787471188
Short name	T872
Test name
Test status
Simulation time	2048814694 ps
CPU time	13.42 seconds
Started	Jun 09 02:24:41 PM PDT 24
Finished	Jun 09 02:24:55 PM PDT 24
Peak memory	226556 kb
Host	smart-89e7013b-e919-4df6-89ae-85e56b391bbb
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787471188 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_mubi.787471188
Directory	/workspace/6.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/6.lc_ctrl_sec_token_digest.3943897717
Short name	T418
Test name
Test status
Simulation time	1312907584 ps
CPU time	9.38 seconds
Started	Jun 09 02:24:41 PM PDT 24
Finished	Jun 09 02:24:51 PM PDT 24
Peak memory	218716 kb
Host	smart-5d2740f1-68db-47f2-a478-9ad0004f7648
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943897717 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_di gest.3943897717
Directory	/workspace/6.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/6.lc_ctrl_sec_token_mux.1689201958
Short name	T360
Test name
Test status
Simulation time	199833735 ps
CPU time	8.4 seconds
Started	Jun 09 02:24:45 PM PDT 24
Finished	Jun 09 02:24:53 PM PDT 24
Peak memory	218696 kb
Host	smart-abd617b7-546b-4cb7-8727-ae0de09a5f2b
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689201958 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_mux.1 689201958
Directory	/workspace/6.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/6.lc_ctrl_security_escalation.2147185565
Short name	T108
Test name
Test status
Simulation time	2867605573 ps
CPU time	15.35 seconds
Started	Jun 09 02:24:43 PM PDT 24
Finished	Jun 09 02:24:59 PM PDT 24
Peak memory	218824 kb
Host	smart-32d4eef0-845e-4326-af4a-52e40997f143
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2147185565 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_security_escalation.2147185565
Directory	/workspace/6.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/6.lc_ctrl_smoke.3846080766
Short name	T699
Test name
Test status
Simulation time	396095241 ps
CPU time	2.29 seconds
Started	Jun 09 02:24:41 PM PDT 24
Finished	Jun 09 02:24:44 PM PDT 24
Peak memory	218240 kb
Host	smart-051543f1-a43d-4000-9563-a2c3390b3778
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3846080766 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_smoke.3846080766
Directory	/workspace/6.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/6.lc_ctrl_state_failure.901149451
Short name	T154
Test name
Test status
Simulation time	232765325 ps
CPU time	26.47 seconds
Started	Jun 09 02:24:40 PM PDT 24
Finished	Jun 09 02:25:06 PM PDT 24
Peak memory	251416 kb
Host	smart-8c401eae-a4ce-4b5d-853a-901e33f3f9e6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=901149451 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_failure.901149451
Directory	/workspace/6.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/6.lc_ctrl_state_post_trans.1026787430
Short name	T14
Test name
Test status
Simulation time	113326987 ps
CPU time	6.27 seconds
Started	Jun 09 02:24:42 PM PDT 24
Finished	Jun 09 02:24:49 PM PDT 24
Peak memory	250888 kb
Host	smart-c3070984-4961-40f0-8660-808c6f22d55e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1026787430 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_post_trans.1026787430
Directory	/workspace/6.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/6.lc_ctrl_stress_all.2955769165
Short name	T164
Test name
Test status
Simulation time	28843547330 ps
CPU time	207.35 seconds
Started	Jun 09 02:24:43 PM PDT 24
Finished	Jun 09 02:28:11 PM PDT 24
Peak memory	251468 kb
Host	smart-e297f485-d9d2-4725-9225-48868e71bcf3
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955769165 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_stress_all.2955769165
Directory	/workspace/6.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/6.lc_ctrl_stress_all_with_rand_reset.395352217
Short name	T530
Test name
Test status
Simulation time	44525164668 ps
CPU time	222.36 seconds
Started	Jun 09 02:24:41 PM PDT 24
Finished	Jun 09 02:28:24 PM PDT 24
Peak memory	268888 kb
Host	smart-318c00ce-017a-4aaa-aaa3-318878633349
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=395352217 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_stress_all_with_rand_reset.395352217
Directory	/workspace/6.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/6.lc_ctrl_volatile_unlock_smoke.848066996
Short name	T477
Test name
Test status
Simulation time	107528044 ps
CPU time	0.84 seconds
Started	Jun 09 02:24:40 PM PDT 24
Finished	Jun 09 02:24:41 PM PDT 24
Peak memory	212620 kb
Host	smart-9ae94a1a-2d0d-4ddb-bc29-9c7cb278dff3
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848066996 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctr l_volatile_unlock_smoke.848066996
Directory	/workspace/6.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/7.lc_ctrl_alert_test.1189080295
Short name	T336
Test name
Test status
Simulation time	81894415 ps
CPU time	0.96 seconds
Started	Jun 09 02:24:57 PM PDT 24
Finished	Jun 09 02:24:58 PM PDT 24
Peak memory	209516 kb
Host	smart-814beb4e-4a59-4654-b79f-aff9730c1869
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189080295 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_alert_test.1189080295
Directory	/workspace/7.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/7.lc_ctrl_claim_transition_if.3068968699
Short name	T207
Test name
Test status
Simulation time	12913649 ps
CPU time	0.82 seconds
Started	Jun 09 02:24:44 PM PDT 24
Finished	Jun 09 02:24:46 PM PDT 24
Peak memory	209252 kb
Host	smart-7a0edf4a-225a-41cc-9ee8-97e371742220
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3068968699 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_claim_transition_if.3068968699
Directory	/workspace/7.lc_ctrl_claim_transition_if/latest

Test location	/workspace/coverage/default/7.lc_ctrl_errors.2028633548
Short name	T286
Test name
Test status
Simulation time	2754063585 ps
CPU time	15.98 seconds
Started	Jun 09 02:24:43 PM PDT 24
Finished	Jun 09 02:25:00 PM PDT 24
Peak memory	218700 kb
Host	smart-89bbc1bc-634a-45f6-bf2f-7307122693d8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2028633548 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_errors.2028633548
Directory	/workspace/7.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/7.lc_ctrl_jtag_access.2884333016
Short name	T734
Test name
Test status
Simulation time	6575056588 ps
CPU time	7.93 seconds
Started	Jun 09 02:24:43 PM PDT 24
Finished	Jun 09 02:24:51 PM PDT 24
Peak memory	218224 kb
Host	smart-d64b2046-b857-4fbe-96ca-d259b71e8f98
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884333016 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_access.2884333016
Directory	/workspace/7.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/7.lc_ctrl_jtag_errors.2574563865
Short name	T222
Test name
Test status
Simulation time	6581531425 ps
CPU time	54.36 seconds
Started	Jun 09 02:24:41 PM PDT 24
Finished	Jun 09 02:25:36 PM PDT 24
Peak memory	226612 kb
Host	smart-15de00e9-394a-481d-b211-651471bb94e0
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574563865 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_er rors.2574563865
Directory	/workspace/7.lc_ctrl_jtag_errors/latest

Test location	/workspace/coverage/default/7.lc_ctrl_jtag_priority.4046120778
Short name	T690
Test name
Test status
Simulation time	435780592 ps
CPU time	10.66 seconds
Started	Jun 09 02:24:49 PM PDT 24
Finished	Jun 09 02:24:59 PM PDT 24
Peak memory	218296 kb
Host	smart-c9077bab-c8a8-4e6f-bcc3-6969a8d7782d
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046120778 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_priority.4 046120778
Directory	/workspace/7.lc_ctrl_jtag_priority/latest

Test location	/workspace/coverage/default/7.lc_ctrl_jtag_prog_failure.2811692758
Short name	T348
Test name
Test status
Simulation time	546997611 ps
CPU time	8.67 seconds
Started	Jun 09 02:24:43 PM PDT 24
Finished	Jun 09 02:24:52 PM PDT 24
Peak memory	218720 kb
Host	smart-3543ffd5-2a28-4fff-9d50-b644bb733522
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811692758 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag _prog_failure.2811692758
Directory	/workspace/7.lc_ctrl_jtag_prog_failure/latest

Test location	/workspace/coverage/default/7.lc_ctrl_jtag_regwen_during_op.4178794457
Short name	T76
Test name
Test status
Simulation time	1036501811 ps
CPU time	29.74 seconds
Started	Jun 09 02:24:44 PM PDT 24
Finished	Jun 09 02:25:14 PM PDT 24
Peak memory	218192 kb
Host	smart-01a93abc-3561-4542-86c2-d4a8dc917cc3
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178794457 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_ jtag_regwen_during_op.4178794457
Directory	/workspace/7.lc_ctrl_jtag_regwen_during_op/latest

Test location	/workspace/coverage/default/7.lc_ctrl_jtag_smoke.4257897642
Short name	T516
Test name
Test status
Simulation time	742539609 ps
CPU time	7.95 seconds
Started	Jun 09 02:24:43 PM PDT 24
Finished	Jun 09 02:24:52 PM PDT 24
Peak memory	218216 kb
Host	smart-cbd55b8c-7a3b-4622-b9bb-0c6221912ea1
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257897642 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_smoke. 4257897642
Directory	/workspace/7.lc_ctrl_jtag_smoke/latest

Test location	/workspace/coverage/default/7.lc_ctrl_jtag_state_failure.4158765259
Short name	T312
Test name
Test status
Simulation time	1463176597 ps
CPU time	40.21 seconds
Started	Jun 09 02:24:40 PM PDT 24
Finished	Jun 09 02:25:21 PM PDT 24
Peak memory	284196 kb
Host	smart-ffeee8de-762f-412a-8074-c201ec49c102
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158765259 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jta g_state_failure.4158765259
Directory	/workspace/7.lc_ctrl_jtag_state_failure/latest

Test location	/workspace/coverage/default/7.lc_ctrl_jtag_state_post_trans.1763762033
Short name	T417
Test name
Test status
Simulation time	2824343164 ps
CPU time	19.74 seconds
Started	Jun 09 02:24:42 PM PDT 24
Finished	Jun 09 02:25:02 PM PDT 24
Peak memory	251456 kb
Host	smart-65d15d27-ed7e-41b2-b971-ea822a3ec39c
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763762033 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_ jtag_state_post_trans.1763762033
Directory	/workspace/7.lc_ctrl_jtag_state_post_trans/latest

Test location	/workspace/coverage/default/7.lc_ctrl_prog_failure.836692707
Short name	T804
Test name
Test status
Simulation time	254762197 ps
CPU time	2.42 seconds
Started	Jun 09 02:24:42 PM PDT 24
Finished	Jun 09 02:24:44 PM PDT 24
Peak memory	223048 kb
Host	smart-b782dd74-e050-49be-a65b-f35781add3fd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=836692707 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_prog_failure.836692707
Directory	/workspace/7.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/7.lc_ctrl_regwen_during_op.3639246912
Short name	T619
Test name
Test status
Simulation time	633805282 ps
CPU time	6.77 seconds
Started	Jun 09 02:24:49 PM PDT 24
Finished	Jun 09 02:24:56 PM PDT 24
Peak memory	218232 kb
Host	smart-b44d6f48-72c3-4d60-bfe8-21a7c7677061
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3639246912 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_regwen_during_op.3639246912
Directory	/workspace/7.lc_ctrl_regwen_during_op/latest

Test location	/workspace/coverage/default/7.lc_ctrl_sec_mubi.3072942932
Short name	T670
Test name
Test status
Simulation time	699215430 ps
CPU time	22.05 seconds
Started	Jun 09 02:24:40 PM PDT 24
Finished	Jun 09 02:25:03 PM PDT 24
Peak memory	219464 kb
Host	smart-d5f591eb-3b10-46b2-8a04-652273ad7b0e
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072942932 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_mubi.3072942932
Directory	/workspace/7.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/7.lc_ctrl_sec_token_digest.2675330596
Short name	T419
Test name
Test status
Simulation time	219840252 ps
CPU time	10.18 seconds
Started	Jun 09 02:24:45 PM PDT 24
Finished	Jun 09 02:24:56 PM PDT 24
Peak memory	218712 kb
Host	smart-529d4307-d5d0-4800-b27b-66352c2d9db0
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675330596 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_di gest.2675330596
Directory	/workspace/7.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/7.lc_ctrl_sec_token_mux.3633218803
Short name	T843
Test name
Test status
Simulation time	3894109980 ps
CPU time	18.6 seconds
Started	Jun 09 02:24:48 PM PDT 24
Finished	Jun 09 02:25:07 PM PDT 24
Peak memory	219420 kb
Host	smart-89eb5f84-cf92-45ab-94d3-7ad17ffbf83e
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633218803 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_mux.3 633218803
Directory	/workspace/7.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/7.lc_ctrl_security_escalation.2025753171
Short name	T170
Test name
Test status
Simulation time	189452803 ps
CPU time	6.73 seconds
Started	Jun 09 02:24:41 PM PDT 24
Finished	Jun 09 02:24:48 PM PDT 24
Peak memory	218756 kb
Host	smart-7dfa03b2-2db3-42ac-9eff-71f3f521ba95
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2025753171 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_security_escalation.2025753171
Directory	/workspace/7.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/7.lc_ctrl_smoke.1577599427
Short name	T389
Test name
Test status
Simulation time	84614180 ps
CPU time	3.37 seconds
Started	Jun 09 02:24:50 PM PDT 24
Finished	Jun 09 02:24:54 PM PDT 24
Peak memory	218220 kb
Host	smart-c2fd79bf-4869-4736-b944-4eb5d5cadb3a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1577599427 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_smoke.1577599427
Directory	/workspace/7.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/7.lc_ctrl_state_failure.3779698364
Short name	T742
Test name
Test status
Simulation time	1112499823 ps
CPU time	27.27 seconds
Started	Jun 09 02:24:40 PM PDT 24
Finished	Jun 09 02:25:08 PM PDT 24
Peak memory	251400 kb
Host	smart-8414b471-2674-43cd-9443-3eff1bf1fa0c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3779698364 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_failure.3779698364
Directory	/workspace/7.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/7.lc_ctrl_state_post_trans.44311474
Short name	T287
Test name
Test status
Simulation time	68529962 ps
CPU time	3.56 seconds
Started	Jun 09 02:24:43 PM PDT 24
Finished	Jun 09 02:24:47 PM PDT 24
Peak memory	222828 kb
Host	smart-b71009a9-a40c-447e-8a39-12a781899cac
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=44311474 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_post_trans.44311474
Directory	/workspace/7.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/7.lc_ctrl_stress_all.3409062895
Short name	T308
Test name
Test status
Simulation time	3710584857 ps
CPU time	33.99 seconds
Started	Jun 09 02:24:50 PM PDT 24
Finished	Jun 09 02:25:24 PM PDT 24
Peak memory	251484 kb
Host	smart-babdc44c-352b-4093-99e8-f341fc92741f
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409062895 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_stress_all.3409062895
Directory	/workspace/7.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/7.lc_ctrl_volatile_unlock_smoke.1712046515
Short name	T572
Test name
Test status
Simulation time	17648606 ps
CPU time	0.98 seconds
Started	Jun 09 02:24:46 PM PDT 24
Finished	Jun 09 02:24:47 PM PDT 24
Peak memory	218212 kb
Host	smart-0e48601e-29f8-4319-9340-085cf8d4b892
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712046515 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ct rl_volatile_unlock_smoke.1712046515
Directory	/workspace/7.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/8.lc_ctrl_alert_test.2721002311
Short name	T446
Test name
Test status
Simulation time	22126816 ps
CPU time	1.04 seconds
Started	Jun 09 02:24:45 PM PDT 24
Finished	Jun 09 02:24:47 PM PDT 24
Peak memory	209452 kb
Host	smart-b52be710-4dcb-4818-a801-c70b25a37351
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721002311 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_alert_test.2721002311
Directory	/workspace/8.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/8.lc_ctrl_claim_transition_if.4087896925
Short name	T616
Test name
Test status
Simulation time	10447747 ps
CPU time	0.81 seconds
Started	Jun 09 02:24:48 PM PDT 24
Finished	Jun 09 02:24:49 PM PDT 24
Peak memory	209484 kb
Host	smart-d3cdd1b3-bf88-41cc-a7f4-01da4beaa12e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4087896925 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_claim_transition_if.4087896925
Directory	/workspace/8.lc_ctrl_claim_transition_if/latest

Test location	/workspace/coverage/default/8.lc_ctrl_errors.690656308
Short name	T875
Test name
Test status
Simulation time	228886766 ps
CPU time	8.45 seconds
Started	Jun 09 02:24:47 PM PDT 24
Finished	Jun 09 02:24:56 PM PDT 24
Peak memory	218712 kb
Host	smart-86dcded8-5ef7-4086-8bf6-ca318877c1e0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=690656308 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_errors.690656308
Directory	/workspace/8.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/8.lc_ctrl_jtag_access.3275557660
Short name	T474
Test name
Test status
Simulation time	932208922 ps
CPU time	5.88 seconds
Started	Jun 09 02:24:43 PM PDT 24
Finished	Jun 09 02:24:54 PM PDT 24
Peak memory	217968 kb
Host	smart-344ebcb9-b57f-4e2f-b690-53268ad71315
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275557660 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_access.3275557660
Directory	/workspace/8.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/8.lc_ctrl_jtag_errors.1572176035
Short name	T315
Test name
Test status
Simulation time	2135846949 ps
CPU time	33.37 seconds
Started	Jun 09 02:24:48 PM PDT 24
Finished	Jun 09 02:25:22 PM PDT 24
Peak memory	218712 kb
Host	smart-211c1937-a138-474a-8d4b-c9c55873e453
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572176035 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_er rors.1572176035
Directory	/workspace/8.lc_ctrl_jtag_errors/latest

Test location	/workspace/coverage/default/8.lc_ctrl_jtag_priority.3762431496
Short name	T750
Test name
Test status
Simulation time	784988338 ps
CPU time	3.09 seconds
Started	Jun 09 02:24:59 PM PDT 24
Finished	Jun 09 02:25:03 PM PDT 24
Peak memory	218060 kb
Host	smart-c2906ddc-599c-4c78-b74e-575cd8453ca2
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762431496 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_priority.3 762431496
Directory	/workspace/8.lc_ctrl_jtag_priority/latest

Test location	/workspace/coverage/default/8.lc_ctrl_jtag_prog_failure.1319214518
Short name	T428
Test name
Test status
Simulation time	111725310 ps
CPU time	2.6 seconds
Started	Jun 09 02:24:53 PM PDT 24
Finished	Jun 09 02:24:56 PM PDT 24
Peak memory	221932 kb
Host	smart-b9cad68c-811b-47da-aa03-5b37744344d1
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319214518 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag _prog_failure.1319214518
Directory	/workspace/8.lc_ctrl_jtag_prog_failure/latest

Test location	/workspace/coverage/default/8.lc_ctrl_jtag_regwen_during_op.3063668624
Short name	T386
Test name
Test status
Simulation time	1230590118 ps
CPU time	17.91 seconds
Started	Jun 09 02:24:51 PM PDT 24
Finished	Jun 09 02:25:09 PM PDT 24
Peak memory	218208 kb
Host	smart-07d66623-38e8-4a05-9ebe-9bb3737828b6
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063668624 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_ jtag_regwen_during_op.3063668624
Directory	/workspace/8.lc_ctrl_jtag_regwen_during_op/latest

Test location	/workspace/coverage/default/8.lc_ctrl_jtag_smoke.1677694323
Short name	T851
Test name
Test status
Simulation time	292655118 ps
CPU time	8.35 seconds
Started	Jun 09 02:24:50 PM PDT 24
Finished	Jun 09 02:24:58 PM PDT 24
Peak memory	218232 kb
Host	smart-478e4457-46a8-43f1-b62c-0667ac6e1e8c
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677694323 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_smoke. 1677694323
Directory	/workspace/8.lc_ctrl_jtag_smoke/latest

Test location	/workspace/coverage/default/8.lc_ctrl_jtag_state_failure.180783424
Short name	T582
Test name
Test status
Simulation time	4372582875 ps
CPU time	47.61 seconds
Started	Jun 09 02:24:50 PM PDT 24
Finished	Jun 09 02:25:38 PM PDT 24
Peak memory	251488 kb
Host	smart-a4a05209-f430-4c67-aa71-f73be61ad49c
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180783424 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag _state_failure.180783424
Directory	/workspace/8.lc_ctrl_jtag_state_failure/latest

Test location	/workspace/coverage/default/8.lc_ctrl_jtag_state_post_trans.3481454240
Short name	T685
Test name
Test status
Simulation time	279519178 ps
CPU time	10.33 seconds
Started	Jun 09 02:24:43 PM PDT 24
Finished	Jun 09 02:24:54 PM PDT 24
Peak memory	251404 kb
Host	smart-95f89de5-b4bd-43f4-8812-16cc27108bfb
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481454240 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_ jtag_state_post_trans.3481454240
Directory	/workspace/8.lc_ctrl_jtag_state_post_trans/latest

Test location	/workspace/coverage/default/8.lc_ctrl_prog_failure.2801092649
Short name	T268
Test name
Test status
Simulation time	244061611 ps
CPU time	3.25 seconds
Started	Jun 09 02:24:50 PM PDT 24
Finished	Jun 09 02:24:53 PM PDT 24
Peak memory	218696 kb
Host	smart-0f86a69c-8ef9-45bd-a092-c705ac1dde7e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2801092649 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_prog_failure.2801092649
Directory	/workspace/8.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/8.lc_ctrl_regwen_during_op.380904080
Short name	T595
Test name
Test status
Simulation time	5772578916 ps
CPU time	10.75 seconds
Started	Jun 09 02:24:47 PM PDT 24
Finished	Jun 09 02:24:58 PM PDT 24
Peak memory	216104 kb
Host	smart-4b59af80-29e5-43bb-8e95-f62261014163
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=380904080 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_regwen_during_op.380904080
Directory	/workspace/8.lc_ctrl_regwen_during_op/latest

Test location	/workspace/coverage/default/8.lc_ctrl_sec_mubi.1435371456
Short name	T777
Test name
Test status
Simulation time	1514206604 ps
CPU time	10.33 seconds
Started	Jun 09 02:24:49 PM PDT 24
Finished	Jun 09 02:25:00 PM PDT 24
Peak memory	218728 kb
Host	smart-63c0734e-dddc-46d6-87b2-4c9288f26e5d
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435371456 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_mubi.1435371456
Directory	/workspace/8.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/8.lc_ctrl_sec_token_digest.2528325257
Short name	T280
Test name
Test status
Simulation time	767522413 ps
CPU time	16.24 seconds
Started	Jun 09 02:24:43 PM PDT 24
Finished	Jun 09 02:24:59 PM PDT 24
Peak memory	218704 kb
Host	smart-559e3825-b45e-4718-bdea-c9dc64feff66
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528325257 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_di gest.2528325257
Directory	/workspace/8.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/8.lc_ctrl_sec_token_mux.400027649
Short name	T819
Test name
Test status
Simulation time	806913743 ps
CPU time	10.79 seconds
Started	Jun 09 02:24:44 PM PDT 24
Finished	Jun 09 02:24:55 PM PDT 24
Peak memory	218716 kb
Host	smart-99b443e4-b1b2-4feb-8fe6-e6bc4f2cfca4
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400027649 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_mux.400027649
Directory	/workspace/8.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/8.lc_ctrl_security_escalation.1706538658
Short name	T421
Test name
Test status
Simulation time	2783839482 ps
CPU time	10.04 seconds
Started	Jun 09 02:24:47 PM PDT 24
Finished	Jun 09 02:24:57 PM PDT 24
Peak memory	226588 kb
Host	smart-ae2b2ae3-54f2-450e-8b13-74cb7ae84c9b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1706538658 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_security_escalation.1706538658
Directory	/workspace/8.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/8.lc_ctrl_smoke.3321439204
Short name	T155
Test name
Test status
Simulation time	24292366 ps
CPU time	1.17 seconds
Started	Jun 09 02:24:41 PM PDT 24
Finished	Jun 09 02:24:42 PM PDT 24
Peak memory	212644 kb
Host	smart-77f7ee92-f6cd-4ab4-9e5b-b1d20714389f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3321439204 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_smoke.3321439204
Directory	/workspace/8.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/8.lc_ctrl_state_failure.3122903204
Short name	T718
Test name
Test status
Simulation time	2445008436 ps
CPU time	34.07 seconds
Started	Jun 09 02:24:45 PM PDT 24
Finished	Jun 09 02:25:19 PM PDT 24
Peak memory	251460 kb
Host	smart-c411355b-cbc6-4e2e-b3d1-845e55b55cd8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3122903204 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_failure.3122903204
Directory	/workspace/8.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/8.lc_ctrl_state_post_trans.1750641157
Short name	T283
Test name
Test status
Simulation time	157597053 ps
CPU time	9.22 seconds
Started	Jun 09 02:24:45 PM PDT 24
Finished	Jun 09 02:24:55 PM PDT 24
Peak memory	251396 kb
Host	smart-d35941f5-d76a-4e2b-9724-86dbb33d5e8c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1750641157 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_post_trans.1750641157
Directory	/workspace/8.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/8.lc_ctrl_stress_all.614192444
Short name	T852
Test name
Test status
Simulation time	7062239478 ps
CPU time	173.12 seconds
Started	Jun 09 02:25:01 PM PDT 24
Finished	Jun 09 02:27:55 PM PDT 24
Peak memory	284240 kb
Host	smart-c221684a-654a-484b-a4a5-845ba5f92c17
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614192444 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_ TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_stress_all.614192444
Directory	/workspace/8.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/8.lc_ctrl_volatile_unlock_smoke.1073936297
Short name	T793
Test name
Test status
Simulation time	15282665 ps
CPU time	0.82 seconds
Started	Jun 09 02:24:41 PM PDT 24
Finished	Jun 09 02:24:42 PM PDT 24
Peak memory	209344 kb
Host	smart-49b1a3cd-5175-432b-8787-b8b60abca5b0
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073936297 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ct rl_volatile_unlock_smoke.1073936297
Directory	/workspace/8.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/9.lc_ctrl_alert_test.39525173
Short name	T373
Test name
Test status
Simulation time	47209571 ps
CPU time	1.02 seconds
Started	Jun 09 02:24:47 PM PDT 24
Finished	Jun 09 02:24:48 PM PDT 24
Peak memory	209528 kb
Host	smart-19372a9b-9413-4709-8b51-cf845532cc01
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39525173 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_alert_test.39525173
Directory	/workspace/9.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/9.lc_ctrl_claim_transition_if.1426201212
Short name	T402
Test name
Test status
Simulation time	40810359 ps
CPU time	0.82 seconds
Started	Jun 09 02:24:57 PM PDT 24
Finished	Jun 09 02:24:58 PM PDT 24
Peak memory	209336 kb
Host	smart-694d23da-cc59-4770-83fd-36894a0d8a56
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1426201212 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_claim_transition_if.1426201212
Directory	/workspace/9.lc_ctrl_claim_transition_if/latest

Test location	/workspace/coverage/default/9.lc_ctrl_errors.1705882734
Short name	T859
Test name
Test status
Simulation time	641570986 ps
CPU time	17.02 seconds
Started	Jun 09 02:24:43 PM PDT 24
Finished	Jun 09 02:25:01 PM PDT 24
Peak memory	218688 kb
Host	smart-c3e47fa8-bea3-4a3c-9fae-b4238b0cb250
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1705882734 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_errors.1705882734
Directory	/workspace/9.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/9.lc_ctrl_jtag_access.2719865495
Short name	T10
Test name
Test status
Simulation time	589311914 ps
CPU time	9.51 seconds
Started	Jun 09 02:24:48 PM PDT 24
Finished	Jun 09 02:24:58 PM PDT 24
Peak memory	217980 kb
Host	smart-e0d95fb0-5250-4f33-b037-b436dac06e41
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719865495 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_access.2719865495
Directory	/workspace/9.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/9.lc_ctrl_jtag_errors.2584134240
Short name	T273
Test name
Test status
Simulation time	1781446407 ps
CPU time	21.64 seconds
Started	Jun 09 02:24:42 PM PDT 24
Finished	Jun 09 02:25:04 PM PDT 24
Peak memory	219044 kb
Host	smart-4a2bbbe0-60c9-45e0-962a-e4438b87ab95
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584134240 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_er rors.2584134240
Directory	/workspace/9.lc_ctrl_jtag_errors/latest

Test location	/workspace/coverage/default/9.lc_ctrl_jtag_priority.1979683734
Short name	T7
Test name
Test status
Simulation time	389610687 ps
CPU time	6.08 seconds
Started	Jun 09 02:24:48 PM PDT 24
Finished	Jun 09 02:24:54 PM PDT 24
Peak memory	217836 kb
Host	smart-adf11b41-0cbb-47a1-91bd-0a50f4b87d10
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979683734 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_priority.1 979683734
Directory	/workspace/9.lc_ctrl_jtag_priority/latest

Test location	/workspace/coverage/default/9.lc_ctrl_jtag_prog_failure.199732548
Short name	T321
Test name
Test status
Simulation time	178196150 ps
CPU time	3.3 seconds
Started	Jun 09 02:24:55 PM PDT 24
Finished	Jun 09 02:24:58 PM PDT 24
Peak memory	218680 kb
Host	smart-aba4ce11-850a-467a-9c63-4fe664e8f77f
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199732548 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_ prog_failure.199732548
Directory	/workspace/9.lc_ctrl_jtag_prog_failure/latest

Test location	/workspace/coverage/default/9.lc_ctrl_jtag_regwen_during_op.550669980
Short name	T666
Test name
Test status
Simulation time	885610811 ps
CPU time	16 seconds
Started	Jun 09 02:24:53 PM PDT 24
Finished	Jun 09 02:25:10 PM PDT 24
Peak memory	218300 kb
Host	smart-dab97cc7-475f-4b00-b2f3-8fba615b280e
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550669980 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_j tag_regwen_during_op.550669980
Directory	/workspace/9.lc_ctrl_jtag_regwen_during_op/latest

Test location	/workspace/coverage/default/9.lc_ctrl_jtag_smoke.3949948744
Short name	T628
Test name
Test status
Simulation time	1046288849 ps
CPU time	8.63 seconds
Started	Jun 09 02:24:44 PM PDT 24
Finished	Jun 09 02:24:53 PM PDT 24
Peak memory	218232 kb
Host	smart-f1c5f806-1517-4b85-8659-82527056e5d2
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949948744 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_smoke. 3949948744
Directory	/workspace/9.lc_ctrl_jtag_smoke/latest

Test location	/workspace/coverage/default/9.lc_ctrl_jtag_state_failure.4033620554
Short name	T740
Test name
Test status
Simulation time	957207249 ps
CPU time	34.99 seconds
Started	Jun 09 02:24:46 PM PDT 24
Finished	Jun 09 02:25:21 PM PDT 24
Peak memory	251432 kb
Host	smart-822dd0f3-6e84-4a28-9cfe-f22e91df2249
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033620554 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jta g_state_failure.4033620554
Directory	/workspace/9.lc_ctrl_jtag_state_failure/latest

Test location	/workspace/coverage/default/9.lc_ctrl_jtag_state_post_trans.2573877702
Short name	T398
Test name
Test status
Simulation time	1976463412 ps
CPU time	10.13 seconds
Started	Jun 09 02:24:57 PM PDT 24
Finished	Jun 09 02:25:07 PM PDT 24
Peak memory	225980 kb
Host	smart-7329d1cf-458f-45b6-a4ac-ab316332638b
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573877702 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_ jtag_state_post_trans.2573877702
Directory	/workspace/9.lc_ctrl_jtag_state_post_trans/latest

Test location	/workspace/coverage/default/9.lc_ctrl_prog_failure.57201383
Short name	T40
Test name
Test status
Simulation time	74066205 ps
CPU time	3.69 seconds
Started	Jun 09 02:24:43 PM PDT 24
Finished	Jun 09 02:24:47 PM PDT 24
Peak memory	223088 kb
Host	smart-aff80bb8-bc5e-4c86-88a1-2f8a1f2c13d4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=57201383 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_prog_failure.57201383
Directory	/workspace/9.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/9.lc_ctrl_regwen_during_op.2444401185
Short name	T345
Test name
Test status
Simulation time	1793509806 ps
CPU time	18.45 seconds
Started	Jun 09 02:24:47 PM PDT 24
Finished	Jun 09 02:25:06 PM PDT 24
Peak memory	218428 kb
Host	smart-f6755dac-4e6f-445b-9fac-97b9db47a15b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2444401185 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_regwen_during_op.2444401185
Directory	/workspace/9.lc_ctrl_regwen_during_op/latest

Test location	/workspace/coverage/default/9.lc_ctrl_sec_mubi.3779303338
Short name	T579
Test name
Test status
Simulation time	415463087 ps
CPU time	12.61 seconds
Started	Jun 09 02:24:55 PM PDT 24
Finished	Jun 09 02:25:08 PM PDT 24
Peak memory	218780 kb
Host	smart-6c6e568e-e9bd-4f22-acb2-fa2841035594
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779303338 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_mubi.3779303338
Directory	/workspace/9.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/9.lc_ctrl_sec_token_digest.3982057353
Short name	T168
Test name
Test status
Simulation time	236598102 ps
CPU time	10.88 seconds
Started	Jun 09 02:24:57 PM PDT 24
Finished	Jun 09 02:25:08 PM PDT 24
Peak memory	218716 kb
Host	smart-f05250a3-9299-4dbf-b357-dbc864c2d1f4
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982057353 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_di gest.3982057353
Directory	/workspace/9.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/9.lc_ctrl_sec_token_mux.1479084973
Short name	T640
Test name
Test status
Simulation time	277938801 ps
CPU time	11.33 seconds
Started	Jun 09 02:24:49 PM PDT 24
Finished	Jun 09 02:25:05 PM PDT 24
Peak memory	218740 kb
Host	smart-5dad745e-2f27-4c6b-be1a-4d131765fa36
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479084973 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_mux.1 479084973
Directory	/workspace/9.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/9.lc_ctrl_security_escalation.3791504619
Short name	T757
Test name
Test status
Simulation time	414916737 ps
CPU time	10.21 seconds
Started	Jun 09 02:25:07 PM PDT 24
Finished	Jun 09 02:25:18 PM PDT 24
Peak memory	226528 kb
Host	smart-fa90088d-7953-4651-8208-7cc92457b481
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3791504619 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_security_escalation.3791504619
Directory	/workspace/9.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/9.lc_ctrl_smoke.2652495780
Short name	T275
Test name
Test status
Simulation time	79965476 ps
CPU time	2.73 seconds
Started	Jun 09 02:24:44 PM PDT 24
Finished	Jun 09 02:24:47 PM PDT 24
Peak memory	215384 kb
Host	smart-980103d4-4e50-4c39-aad0-a7b4d8076323
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2652495780 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_smoke.2652495780
Directory	/workspace/9.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/9.lc_ctrl_state_failure.2303346753
Short name	T424
Test name
Test status
Simulation time	532957133 ps
CPU time	31.46 seconds
Started	Jun 09 02:25:05 PM PDT 24
Finished	Jun 09 02:25:36 PM PDT 24
Peak memory	251420 kb
Host	smart-38e18c55-5f0a-4569-bfbb-85f6517a8b9e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2303346753 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_failure.2303346753
Directory	/workspace/9.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/9.lc_ctrl_state_post_trans.2206808643
Short name	T317
Test name
Test status
Simulation time	136852043 ps
CPU time	7.26 seconds
Started	Jun 09 02:24:41 PM PDT 24
Finished	Jun 09 02:24:49 PM PDT 24
Peak memory	251420 kb
Host	smart-9cb65404-00b5-43f6-84f0-fa41da7640c7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2206808643 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_post_trans.2206808643
Directory	/workspace/9.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/9.lc_ctrl_stress_all.975648285
Short name	T256
Test name
Test status
Simulation time	1026909658 ps
CPU time	33.47 seconds
Started	Jun 09 02:24:45 PM PDT 24
Finished	Jun 09 02:25:18 PM PDT 24
Peak memory	267760 kb
Host	smart-0cf4fbae-d2ce-40df-af97-6197ebb1d646
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975648285 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_ TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_stress_all.975648285
Directory	/workspace/9.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/9.lc_ctrl_volatile_unlock_smoke.1843529213
Short name	T47
Test name
Test status
Simulation time	12148331 ps
CPU time	0.81 seconds
Started	Jun 09 02:24:48 PM PDT 24
Finished	Jun 09 02:24:49 PM PDT 24
Peak memory	209332 kb
Host	smart-3179c513-6f78-4773-b293-6a4608873822
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843529213 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ct rl_volatile_unlock_smoke.1843529213
Directory	/workspace/9.lc_ctrl_volatile_unlock_smoke/latest

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