Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

94462306

1

T1

38001

T2

16804

T3

25007

auto[1]

1295057

1

T1

9029

T3

1287

T4

693

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

94451861

1

T1

35611

T2

16804

T3

24215

auto[1]

1305502

1

T1

11419

T3

2079

T4

396

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	6879987	1			T1	7460		T2	5323		T3	7451
auto[IdleSt]	22491380	1			T1	6203		T2	2120		T3	2215
auto[ClkMuxSt]	34606	1			T1	68		T2	54		T3	61
auto[CntIncrSt]	34314	1			T1	66		T2	54		T3	61
auto[CntProgSt]	1521023	1			T1	126		T2	108		T3	1654
auto[TransCheckSt]	26718	1			T1	52		T2	54		T3	43
auto[TokenHashSt]	33988012	1			T1	17173		T2	1068		T3	478
auto[FlashRmaSt]	27126	1			T1	55		T3	83		T4	27
auto[TokenCheck0St]	12279	1			T1	29		T3	35		T4	16
auto[TokenCheck1St]	9053	1			T1	29		T3	27		T4	6
auto[TransProgSt]	383389	1			T1	53		T3	942		T4	192
auto[PostTransSt]	13745902	1			T1	30		T2	8023		T3	7541
auto[ScrapSt]	415302	1			T13	6		T6	454		T16	203
auto[EscalateSt]	6247754	1			T1	15686		T3	4460		T4	6094
auto[InvalidSt]	9938760	1			T3	1243		T5	93602		T14	6413

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1758	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	9938760	1			T3	1243		T5	93602		T14	6413
EscalateSt	6247754	1			T1	15686		T3	4460		T4	6094
ScrapSt	415302	1			T13	6		T6	454		T16	203
PostTransSt	13745902	1			T1	30		T2	8023		T3	7541
TransProgSt	383389	1			T1	53		T3	942		T4	192
TokenCheck1St	9053	1			T1	29		T3	27		T4	6
TokenCheck0St	12279	1			T1	29		T3	35		T4	16
FlashRmaSt	27126	1			T1	55		T3	83		T4	27
TokenHashSt	33988012	1			T1	17173		T2	1068		T3	478
TransCheckSt	26718	1			T1	52		T2	54		T3	43
CntProgSt	1521023	1			T1	126		T2	108		T3	1654
CntIncrSt	34314	1			T1	66		T2	54		T3	61
ClkMuxSt	34606	1			T1	68		T2	54		T3	61
IdleSt	22491380	1			T1	6203		T2	2120		T3	2215
ResetSt	6879987	1			T1	7460		T2	5323		T3	7451
arcs[ResetSt=>IdleSt]	51036	1			T1	76		T2	55		T3	78
arcs[IdleSt=>ScrapSt]	280	1			T13	2		T6	1		T16	1
arcs[IdleSt=>ClkMuxSt]	34389	1			T1	68		T2	54		T3	61
arcs[ClkMuxSt=>CntIncrSt]	34314	1			T1	66		T2	54		T3	61
arcs[CntIncrSt=>PostTransSt]	1773	1			T4	13		T16	10		T17	15
arcs[CntIncrSt=>CntProgSt]	32476	1			T1	65		T2	54		T3	61
arcs[CntProgSt=>PostTransSt]	4611	1			T3	18		T4	11		T12	10
arcs[CntProgSt=>TransCheckSt]	26718	1			T1	52		T2	54		T3	43
arcs[TransCheckSt=>PostTransSt]	3635	1			T4	8		T16	10		T40	32
arcs[TransCheckSt=>TokenHashSt]	22973	1			T1	47		T2	54		T3	43
arcs[TokenHashSt=>PostTransSt]	9892	1			T2	54		T3	8		T4	22
arcs[TokenHashSt=>FlashRmaSt]	12377	1			T1	31		T3	35		T4	16
arcs[FlashRmaSt=>TokenCheck0St]	12279	1			T1	29		T3	35		T4	16
arcs[TokenCheck0St=>PostTransSt]	3205	1			T3	8		T4	10		T19	9
arcs[TokenCheck0St=>TokenCheck1St]	9053	1			T1	29		T3	27		T4	6
arcs[TokenCheck1St=>PostTransSt]	649	1			T3	1		T16	1		T40	9
arcs[TransProgSt=>PostTransSt]	7499	1			T1	15		T3	26		T4	6
arcs[IdleSt=>EscalateSt]	145	1			T1	7		T13	10		T56	2
arcs[ClkMuxSt=>EscalateSt]	75	1			T1	2		T13	2		T54	1
arcs[CntIncrSt=>EscalateSt]	65	1			T1	1		T13	2		T55	3
arcs[CntProgSt=>EscalateSt]	1147	1			T1	13		T13	28		T54	7
arcs[TransCheckSt=>EscalateSt]	110	1			T1	5		T54	5		T58	3
arcs[TokenHashSt=>EscalateSt]	704	1			T1	16		T13	10		T16	1
arcs[FlashRmaSt=>EscalateSt]	98	1			T1	2		T13	2		T55	1
arcs[TokenCheck0St=>EscalateSt]	21	1			T54	1		T55	1		T58	1
arcs[TokenCheck1St=>EscalateSt]	145	1			T13	2		T54	6		T55	5
arcs[TransProgSt=>EscalateSt]	760	1			T1	14		T13	19		T54	5
arcs[PostTransSt=>EscalateSt]	4841	1			T1	15		T3	18		T4	11
arcs[InvalidSt=>EscalateSt]	12218	1			T3	16		T5	54		T14	45

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	6879789	1			T1	7458		T2	5323		T3	7451
auto[0]	auto[IdleSt]	22491277	1			T1	6198		T2	2120		T3	2215
auto[0]	auto[ClkMuxSt]	34557	1			T1	68		T2	54		T3	61
auto[0]	auto[CntIncrSt]	34271	1			T1	66		T2	54		T3	61
auto[0]	auto[CntProgSt]	1520266	1			T1	117		T2	108		T3	1654
auto[0]	auto[TransCheckSt]	26642	1			T1	49		T2	54		T3	43
auto[0]	auto[TokenHashSt]	33987537	1			T1	17161		T2	1068		T3	478
auto[0]	auto[FlashRmaSt]	27067	1			T1	54		T3	83		T4	27
auto[0]	auto[TokenCheck0St]	12263	1			T1	29		T3	35		T4	16
auto[0]	auto[TokenCheck1St]	8950	1			T1	29		T3	27		T4	6
auto[0]	auto[TransProgSt]	382874	1			T1	47		T3	942		T4	192
auto[0]	auto[PostTransSt]	13743434	1			T1	21		T2	8023		T3	7531
auto[0]	auto[ScrapSt]	415263	1			T13	4		T6	454		T16	203
auto[0]	auto[EscalateSt]	4963658	1			T1	6704		T3	3186		T4	5408
auto[0]	auto[InvalidSt]	9932700	1			T3	1240		T5	93571		T14	6384
auto[1]	auto[ResetSt]	198	1			T1	2		T13	9		T54	3
auto[1]	auto[IdleSt]	103	1			T1	5		T13	7		T56	1
auto[1]	auto[ClkMuxSt]	49	1			T13	1		T55	2		T165	1
auto[1]	auto[CntIncrSt]	43	1			T13	2		T55	2		T58	1
auto[1]	auto[CntProgSt]	757	1			T1	9		T13	18		T54	3
auto[1]	auto[TransCheckSt]	76	1			T1	3		T54	4		T58	2
auto[1]	auto[TokenHashSt]	475	1			T1	12		T13	6		T17	1
auto[1]	auto[FlashRmaSt]	59	1			T1	1		T55	1		T58	1
auto[1]	auto[TokenCheck0St]	16	1			T54	1		T212	1		T213	2
auto[1]	auto[TokenCheck1St]	103	1			T13	1		T54	5		T55	2
auto[1]	auto[TransProgSt]	515	1			T1	6		T13	8		T54	4
auto[1]	auto[PostTransSt]	2468	1			T1	9		T3	10		T4	7
auto[1]	auto[ScrapSt]	39	1			T13	2		T55	1		T58	1
auto[1]	auto[EscalateSt]	1284096	1			T1	8982		T3	1274		T4	686
auto[1]	auto[InvalidSt]	6060	1			T3	3		T5	31		T14	29

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	6879796	1			T1	7454		T2	5323		T3	7451
auto[0]	auto[IdleSt]	22491289	1			T1	6200		T2	2120		T3	2215
auto[0]	auto[ClkMuxSt]	34558	1			T1	66		T2	54		T3	61
auto[0]	auto[CntIncrSt]	34269	1			T1	65		T2	54		T3	61
auto[0]	auto[CntProgSt]	1520239	1			T1	116		T2	108		T3	1654
auto[0]	auto[TransCheckSt]	26648	1			T1	49		T2	54		T3	43
auto[0]	auto[TokenHashSt]	33987538	1			T1	17162		T2	1068		T3	478
auto[0]	auto[FlashRmaSt]	27059	1			T1	53		T3	83		T4	27
auto[0]	auto[TokenCheck0St]	12266	1			T1	29		T3	35		T4	16
auto[0]	auto[TokenCheck1St]	8955	1			T1	29		T3	27		T4	6
auto[0]	auto[TransProgSt]	382876	1			T1	45		T3	942		T4	192
auto[0]	auto[PostTransSt]	13743458	1			T1	18		T2	8023		T3	7533
auto[0]	auto[ScrapSt]	415259	1			T13	5		T6	454		T16	203
auto[0]	auto[EscalateSt]	4953291	1			T1	4325		T3	2402		T4	5702
auto[0]	auto[InvalidSt]	9932602	1			T3	1230		T5	93579		T14	6397
auto[1]	auto[ResetSt]	191	1			T1	6		T13	8		T54	2
auto[1]	auto[IdleSt]	91	1			T1	3		T13	8		T56	1
auto[1]	auto[ClkMuxSt]	48	1			T1	2		T13	2		T54	1
auto[1]	auto[CntIncrSt]	45	1			T1	1		T13	1		T55	2
auto[1]	auto[CntProgSt]	784	1			T1	10		T13	19		T54	7
auto[1]	auto[TransCheckSt]	70	1			T1	3		T54	2		T58	1
auto[1]	auto[TokenHashSt]	474	1			T1	11		T13	7		T16	1
auto[1]	auto[FlashRmaSt]	67	1			T1	2		T13	2		T165	3
auto[1]	auto[TokenCheck0St]	13	1			T54	1		T55	1		T58	1
auto[1]	auto[TokenCheck1St]	98	1			T13	2		T54	4		T55	3
auto[1]	auto[TransProgSt]	513	1			T1	8		T13	15		T54	5
auto[1]	auto[PostTransSt]	2444	1			T1	12		T3	8		T4	4
auto[1]	auto[ScrapSt]	43	1			T13	1		T54	1		T55	1
auto[1]	auto[EscalateSt]	1294463	1			T1	11361		T3	2058		T4	392
auto[1]	auto[InvalidSt]	6158	1			T3	13		T5	23		T14	16