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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.23 97.89 95.77 93.34 100.00 98.55 98.76 96.29


Total test records in report: 999
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T812 /workspace/coverage/default/12.lc_ctrl_sec_mubi.974856733 Jun 10 05:47:42 PM PDT 24 Jun 10 05:48:11 PM PDT 24 1671144512 ps
T813 /workspace/coverage/default/0.lc_ctrl_jtag_smoke.3314926768 Jun 10 05:46:30 PM PDT 24 Jun 10 05:46:33 PM PDT 24 105557280 ps
T814 /workspace/coverage/default/26.lc_ctrl_sec_token_digest.2086001432 Jun 10 05:48:40 PM PDT 24 Jun 10 05:48:55 PM PDT 24 326095741 ps
T815 /workspace/coverage/default/24.lc_ctrl_prog_failure.3178967438 Jun 10 05:48:29 PM PDT 24 Jun 10 05:48:32 PM PDT 24 47607520 ps
T816 /workspace/coverage/default/5.lc_ctrl_smoke.720471773 Jun 10 05:46:56 PM PDT 24 Jun 10 05:47:01 PM PDT 24 190278091 ps
T44 /workspace/coverage/default/45.lc_ctrl_volatile_unlock_smoke.1859976494 Jun 10 05:49:44 PM PDT 24 Jun 10 05:49:45 PM PDT 24 42818837 ps
T817 /workspace/coverage/default/32.lc_ctrl_state_post_trans.4271596015 Jun 10 05:48:59 PM PDT 24 Jun 10 05:49:08 PM PDT 24 1149118009 ps
T818 /workspace/coverage/default/18.lc_ctrl_jtag_state_failure.4005137501 Jun 10 05:48:08 PM PDT 24 Jun 10 05:48:50 PM PDT 24 1871517832 ps
T819 /workspace/coverage/default/19.lc_ctrl_errors.2500251373 Jun 10 05:48:19 PM PDT 24 Jun 10 05:48:28 PM PDT 24 171056085 ps
T820 /workspace/coverage/default/5.lc_ctrl_sec_mubi.359594486 Jun 10 05:46:59 PM PDT 24 Jun 10 05:47:14 PM PDT 24 276785995 ps
T821 /workspace/coverage/default/4.lc_ctrl_alert_test.2376286408 Jun 10 05:46:58 PM PDT 24 Jun 10 05:46:59 PM PDT 24 197579429 ps
T822 /workspace/coverage/default/37.lc_ctrl_sec_mubi.2964445545 Jun 10 05:49:20 PM PDT 24 Jun 10 05:49:36 PM PDT 24 313219107 ps
T823 /workspace/coverage/default/34.lc_ctrl_jtag_access.3569187357 Jun 10 05:49:07 PM PDT 24 Jun 10 05:49:11 PM PDT 24 466808816 ps
T824 /workspace/coverage/default/9.lc_ctrl_alert_test.1778378577 Jun 10 05:47:27 PM PDT 24 Jun 10 05:47:28 PM PDT 24 73330978 ps
T825 /workspace/coverage/default/16.lc_ctrl_state_failure.1881593620 Jun 10 05:48:01 PM PDT 24 Jun 10 05:48:27 PM PDT 24 328163124 ps
T826 /workspace/coverage/default/0.lc_ctrl_jtag_errors.667032147 Jun 10 05:46:33 PM PDT 24 Jun 10 05:47:24 PM PDT 24 26581187096 ps
T827 /workspace/coverage/default/23.lc_ctrl_state_post_trans.499153433 Jun 10 05:48:35 PM PDT 24 Jun 10 05:48:42 PM PDT 24 218633200 ps
T828 /workspace/coverage/default/4.lc_ctrl_claim_transition_if.3104505188 Jun 10 05:46:49 PM PDT 24 Jun 10 05:46:50 PM PDT 24 42226922 ps
T829 /workspace/coverage/default/41.lc_ctrl_prog_failure.4169434892 Jun 10 05:49:30 PM PDT 24 Jun 10 05:49:33 PM PDT 24 226881230 ps
T830 /workspace/coverage/default/48.lc_ctrl_sec_mubi.859333742 Jun 10 05:49:49 PM PDT 24 Jun 10 05:50:00 PM PDT 24 1343022782 ps
T831 /workspace/coverage/default/0.lc_ctrl_jtag_prog_failure.1956359100 Jun 10 05:46:32 PM PDT 24 Jun 10 05:46:41 PM PDT 24 3151660623 ps
T832 /workspace/coverage/default/12.lc_ctrl_sec_token_mux.1424641061 Jun 10 05:47:42 PM PDT 24 Jun 10 05:48:10 PM PDT 24 9526331777 ps
T833 /workspace/coverage/default/6.lc_ctrl_prog_failure.1073232874 Jun 10 05:47:00 PM PDT 24 Jun 10 05:47:03 PM PDT 24 452501965 ps
T834 /workspace/coverage/default/20.lc_ctrl_state_post_trans.92621674 Jun 10 05:48:19 PM PDT 24 Jun 10 05:48:29 PM PDT 24 55609326 ps
T835 /workspace/coverage/default/39.lc_ctrl_security_escalation.449118150 Jun 10 05:49:24 PM PDT 24 Jun 10 05:49:33 PM PDT 24 1327817963 ps
T836 /workspace/coverage/default/29.lc_ctrl_state_failure.2012813948 Jun 10 05:48:46 PM PDT 24 Jun 10 05:49:18 PM PDT 24 324180944 ps
T96 /workspace/coverage/default/1.lc_ctrl_stress_all_with_rand_reset.1650508797 Jun 10 05:46:40 PM PDT 24 Jun 10 06:04:27 PM PDT 24 80163074118 ps
T837 /workspace/coverage/default/15.lc_ctrl_jtag_errors.1688957609 Jun 10 05:47:57 PM PDT 24 Jun 10 05:48:50 PM PDT 24 1702972864 ps
T838 /workspace/coverage/default/35.lc_ctrl_alert_test.2216266601 Jun 10 05:49:11 PM PDT 24 Jun 10 05:49:12 PM PDT 24 22669427 ps
T839 /workspace/coverage/default/3.lc_ctrl_jtag_state_post_trans.3483205354 Jun 10 05:46:49 PM PDT 24 Jun 10 05:47:09 PM PDT 24 928093803 ps
T840 /workspace/coverage/default/35.lc_ctrl_volatile_unlock_smoke.38091964 Jun 10 05:49:08 PM PDT 24 Jun 10 05:49:09 PM PDT 24 15460263 ps
T841 /workspace/coverage/default/36.lc_ctrl_sec_token_digest.3727790951 Jun 10 05:49:17 PM PDT 24 Jun 10 05:49:24 PM PDT 24 3118144805 ps
T842 /workspace/coverage/default/38.lc_ctrl_sec_token_mux.872241352 Jun 10 05:49:20 PM PDT 24 Jun 10 05:49:31 PM PDT 24 534977637 ps
T843 /workspace/coverage/default/40.lc_ctrl_jtag_access.2511572280 Jun 10 05:49:32 PM PDT 24 Jun 10 05:49:38 PM PDT 24 325437908 ps
T844 /workspace/coverage/default/14.lc_ctrl_volatile_unlock_smoke.3976733900 Jun 10 05:47:51 PM PDT 24 Jun 10 05:47:52 PM PDT 24 22519567 ps
T845 /workspace/coverage/default/13.lc_ctrl_state_failure.212817944 Jun 10 05:47:41 PM PDT 24 Jun 10 05:48:01 PM PDT 24 258855585 ps
T846 /workspace/coverage/default/41.lc_ctrl_alert_test.2496540120 Jun 10 05:49:30 PM PDT 24 Jun 10 05:49:32 PM PDT 24 16919067 ps
T847 /workspace/coverage/default/10.lc_ctrl_jtag_state_post_trans.4215068828 Jun 10 05:47:30 PM PDT 24 Jun 10 05:47:56 PM PDT 24 728113702 ps
T848 /workspace/coverage/default/43.lc_ctrl_errors.2752940091 Jun 10 05:49:31 PM PDT 24 Jun 10 05:49:45 PM PDT 24 1115823539 ps
T849 /workspace/coverage/default/6.lc_ctrl_sec_token_mux.1451372427 Jun 10 05:47:11 PM PDT 24 Jun 10 05:47:22 PM PDT 24 508125043 ps
T850 /workspace/coverage/default/40.lc_ctrl_stress_all.3683896528 Jun 10 05:49:33 PM PDT 24 Jun 10 05:51:23 PM PDT 24 11289138894 ps
T851 /workspace/coverage/default/40.lc_ctrl_smoke.501461080 Jun 10 05:49:23 PM PDT 24 Jun 10 05:49:30 PM PDT 24 906472776 ps
T852 /workspace/coverage/default/33.lc_ctrl_sec_token_digest.436021862 Jun 10 05:49:02 PM PDT 24 Jun 10 05:49:14 PM PDT 24 3409152272 ps
T853 /workspace/coverage/default/45.lc_ctrl_stress_all.4057608059 Jun 10 05:49:41 PM PDT 24 Jun 10 05:50:46 PM PDT 24 8992867592 ps
T854 /workspace/coverage/default/27.lc_ctrl_sec_token_digest.2526934227 Jun 10 05:48:43 PM PDT 24 Jun 10 05:48:56 PM PDT 24 435956027 ps
T855 /workspace/coverage/default/22.lc_ctrl_security_escalation.1273968380 Jun 10 05:48:27 PM PDT 24 Jun 10 05:48:37 PM PDT 24 912814750 ps
T856 /workspace/coverage/default/4.lc_ctrl_state_post_trans.913229077 Jun 10 05:46:51 PM PDT 24 Jun 10 05:46:55 PM PDT 24 170036108 ps
T857 /workspace/coverage/default/33.lc_ctrl_prog_failure.4260180341 Jun 10 05:49:01 PM PDT 24 Jun 10 05:49:03 PM PDT 24 141417214 ps
T858 /workspace/coverage/default/27.lc_ctrl_sec_token_mux.1346710850 Jun 10 05:48:43 PM PDT 24 Jun 10 05:48:54 PM PDT 24 216374469 ps
T859 /workspace/coverage/default/25.lc_ctrl_security_escalation.720426826 Jun 10 05:48:35 PM PDT 24 Jun 10 05:48:44 PM PDT 24 1455806726 ps
T860 /workspace/coverage/default/10.lc_ctrl_security_escalation.3211853699 Jun 10 05:47:28 PM PDT 24 Jun 10 05:47:40 PM PDT 24 354797043 ps
T861 /workspace/coverage/default/40.lc_ctrl_volatile_unlock_smoke.3225226691 Jun 10 05:49:26 PM PDT 24 Jun 10 05:49:28 PM PDT 24 19078769 ps
T862 /workspace/coverage/default/7.lc_ctrl_security_escalation.22393030 Jun 10 05:47:12 PM PDT 24 Jun 10 05:47:19 PM PDT 24 172202235 ps
T863 /workspace/coverage/default/18.lc_ctrl_sec_token_mux.2884923637 Jun 10 05:48:10 PM PDT 24 Jun 10 05:48:22 PM PDT 24 629722204 ps
T864 /workspace/coverage/default/10.lc_ctrl_sec_token_digest.3827517751 Jun 10 05:47:31 PM PDT 24 Jun 10 05:47:39 PM PDT 24 654633262 ps
T52 /workspace/coverage/default/44.lc_ctrl_stress_all_with_rand_reset.759075405 Jun 10 05:49:38 PM PDT 24 Jun 10 05:52:38 PM PDT 24 8816704217 ps
T865 /workspace/coverage/default/1.lc_ctrl_prog_failure.3695855667 Jun 10 05:46:36 PM PDT 24 Jun 10 05:46:39 PM PDT 24 73409775 ps
T866 /workspace/coverage/default/39.lc_ctrl_state_post_trans.3776647643 Jun 10 05:49:27 PM PDT 24 Jun 10 05:49:36 PM PDT 24 237164224 ps
T867 /workspace/coverage/default/45.lc_ctrl_errors.2423300218 Jun 10 05:49:42 PM PDT 24 Jun 10 05:49:55 PM PDT 24 1245067762 ps
T868 /workspace/coverage/default/34.lc_ctrl_errors.2882247857 Jun 10 05:49:09 PM PDT 24 Jun 10 05:49:27 PM PDT 24 1439691902 ps
T869 /workspace/coverage/default/12.lc_ctrl_jtag_state_failure.4105826091 Jun 10 05:47:35 PM PDT 24 Jun 10 05:48:26 PM PDT 24 2502482926 ps
T870 /workspace/coverage/default/49.lc_ctrl_smoke.4083754612 Jun 10 05:49:51 PM PDT 24 Jun 10 05:49:55 PM PDT 24 228455546 ps
T871 /workspace/coverage/default/5.lc_ctrl_prog_failure.3275305739 Jun 10 05:46:56 PM PDT 24 Jun 10 05:46:59 PM PDT 24 33763909 ps
T872 /workspace/coverage/default/20.lc_ctrl_smoke.3644467732 Jun 10 05:48:18 PM PDT 24 Jun 10 05:48:20 PM PDT 24 106623068 ps
T119 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.2459583897 Jun 10 05:45:16 PM PDT 24 Jun 10 05:45:17 PM PDT 24 77218784 ps
T120 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.4235761455 Jun 10 05:44:59 PM PDT 24 Jun 10 05:45:01 PM PDT 24 99548922 ps
T125 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.2894255830 Jun 10 05:44:56 PM PDT 24 Jun 10 05:44:57 PM PDT 24 106623892 ps
T112 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.3956166288 Jun 10 05:44:47 PM PDT 24 Jun 10 05:44:52 PM PDT 24 163044975 ps
T160 /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.470423539 Jun 10 05:45:15 PM PDT 24 Jun 10 05:45:17 PM PDT 24 150418027 ps
T148 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.1852195352 Jun 10 05:44:56 PM PDT 24 Jun 10 05:45:11 PM PDT 24 3698616809 ps
T144 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.1872876696 Jun 10 05:44:36 PM PDT 24 Jun 10 05:44:40 PM PDT 24 303466522 ps
T873 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.3024593586 Jun 10 05:44:50 PM PDT 24 Jun 10 05:44:51 PM PDT 24 23292493 ps
T149 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.692714006 Jun 10 05:45:16 PM PDT 24 Jun 10 05:45:17 PM PDT 24 41117809 ps
T189 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.2024416827 Jun 10 05:45:30 PM PDT 24 Jun 10 05:45:32 PM PDT 24 67085582 ps
T113 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.1664249376 Jun 10 05:44:48 PM PDT 24 Jun 10 05:44:50 PM PDT 24 126434454 ps
T145 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.1574470054 Jun 10 05:45:24 PM PDT 24 Jun 10 05:45:26 PM PDT 24 641675309 ps
T874 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.2342627887 Jun 10 05:45:11 PM PDT 24 Jun 10 05:45:12 PM PDT 24 29225116 ps
T146 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.3818600708 Jun 10 05:44:53 PM PDT 24 Jun 10 05:44:59 PM PDT 24 445185480 ps
T875 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.3589748418 Jun 10 05:44:49 PM PDT 24 Jun 10 05:44:51 PM PDT 24 43899353 ps
T876 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.1854292809 Jun 10 05:45:06 PM PDT 24 Jun 10 05:45:17 PM PDT 24 772168860 ps
T161 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.3041125758 Jun 10 05:45:06 PM PDT 24 Jun 10 05:45:07 PM PDT 24 65567503 ps
T877 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.4266947199 Jun 10 05:45:15 PM PDT 24 Jun 10 05:45:17 PM PDT 24 71325712 ps
T114 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.2095690665 Jun 10 05:45:30 PM PDT 24 Jun 10 05:45:32 PM PDT 24 104562722 ps
T118 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.2839752843 Jun 10 05:45:34 PM PDT 24 Jun 10 05:45:36 PM PDT 24 25255520 ps
T190 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.2048276758 Jun 10 05:45:22 PM PDT 24 Jun 10 05:45:23 PM PDT 24 32144748 ps
T191 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.3076764224 Jun 10 05:44:46 PM PDT 24 Jun 10 05:44:48 PM PDT 24 33895110 ps
T134 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.3189844997 Jun 10 05:44:57 PM PDT 24 Jun 10 05:44:59 PM PDT 24 25850917 ps
T878 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.3574165946 Jun 10 05:45:08 PM PDT 24 Jun 10 05:45:10 PM PDT 24 250212231 ps
T115 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.2957421406 Jun 10 05:45:17 PM PDT 24 Jun 10 05:45:21 PM PDT 24 336175785 ps
T879 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.359743634 Jun 10 05:45:19 PM PDT 24 Jun 10 05:45:47 PM PDT 24 7567532356 ps
T880 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.1859886285 Jun 10 05:45:09 PM PDT 24 Jun 10 05:45:20 PM PDT 24 3460968487 ps
T881 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.3011575567 Jun 10 05:45:01 PM PDT 24 Jun 10 05:45:02 PM PDT 24 14362344 ps
T202 /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.2308310792 Jun 10 05:45:25 PM PDT 24 Jun 10 05:45:26 PM PDT 24 44215510 ps
T882 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.3496901883 Jun 10 05:44:40 PM PDT 24 Jun 10 05:44:44 PM PDT 24 1628703466 ps
T192 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.2721995334 Jun 10 05:45:11 PM PDT 24 Jun 10 05:45:12 PM PDT 24 13879234 ps
T203 /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.2198075758 Jun 10 05:44:54 PM PDT 24 Jun 10 05:44:56 PM PDT 24 175809920 ps
T204 /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.324130788 Jun 10 05:45:38 PM PDT 24 Jun 10 05:45:39 PM PDT 24 27572459 ps
T205 /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.2163911859 Jun 10 05:45:41 PM PDT 24 Jun 10 05:45:42 PM PDT 24 47988777 ps
T193 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.3160316637 Jun 10 05:45:37 PM PDT 24 Jun 10 05:45:38 PM PDT 24 26727587 ps
T883 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.3330912006 Jun 10 05:45:15 PM PDT 24 Jun 10 05:45:18 PM PDT 24 223382131 ps
T884 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.4227393710 Jun 10 05:44:37 PM PDT 24 Jun 10 05:44:43 PM PDT 24 2225423275 ps
T173 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2742480271 Jun 10 05:45:19 PM PDT 24 Jun 10 05:45:22 PM PDT 24 399548625 ps
T885 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.163300664 Jun 10 05:45:20 PM PDT 24 Jun 10 05:45:23 PM PDT 24 230122554 ps
T182 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.3501852239 Jun 10 05:45:10 PM PDT 24 Jun 10 05:45:11 PM PDT 24 132131556 ps
T886 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.2540339326 Jun 10 05:44:33 PM PDT 24 Jun 10 05:44:34 PM PDT 24 75891407 ps
T121 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.2610631241 Jun 10 05:45:26 PM PDT 24 Jun 10 05:45:30 PM PDT 24 133157609 ps
T887 /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.3118706256 Jun 10 05:45:27 PM PDT 24 Jun 10 05:45:29 PM PDT 24 39570835 ps
T888 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.1430658321 Jun 10 05:45:47 PM PDT 24 Jun 10 05:45:48 PM PDT 24 242403347 ps
T889 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.1594478757 Jun 10 05:45:27 PM PDT 24 Jun 10 05:45:28 PM PDT 24 15435820 ps
T890 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.903823789 Jun 10 05:45:20 PM PDT 24 Jun 10 05:45:22 PM PDT 24 199689787 ps
T891 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.1065695066 Jun 10 05:44:46 PM PDT 24 Jun 10 05:44:57 PM PDT 24 441492389 ps
T128 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.1245043479 Jun 10 05:45:03 PM PDT 24 Jun 10 05:45:05 PM PDT 24 215119011 ps
T892 /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.2644671230 Jun 10 05:45:34 PM PDT 24 Jun 10 05:45:35 PM PDT 24 51130384 ps
T893 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.195811112 Jun 10 05:45:27 PM PDT 24 Jun 10 05:45:29 PM PDT 24 97951109 ps
T894 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.1712816790 Jun 10 05:45:30 PM PDT 24 Jun 10 05:45:34 PM PDT 24 129408271 ps
T895 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.1100253528 Jun 10 05:44:42 PM PDT 24 Jun 10 05:44:44 PM PDT 24 40193880 ps
T123 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.343821880 Jun 10 05:45:42 PM PDT 24 Jun 10 05:45:45 PM PDT 24 81042261 ps
T896 /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.3202881565 Jun 10 05:45:32 PM PDT 24 Jun 10 05:45:34 PM PDT 24 50925284 ps
T124 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.754386294 Jun 10 05:44:45 PM PDT 24 Jun 10 05:44:49 PM PDT 24 118799572 ps
T897 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.3952743318 Jun 10 05:45:35 PM PDT 24 Jun 10 05:45:36 PM PDT 24 14790308 ps
T136 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.1712968687 Jun 10 05:45:32 PM PDT 24 Jun 10 05:45:35 PM PDT 24 52910330 ps
T898 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.2636477116 Jun 10 05:45:13 PM PDT 24 Jun 10 05:45:14 PM PDT 24 121017910 ps
T116 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.4268138172 Jun 10 05:45:21 PM PDT 24 Jun 10 05:45:26 PM PDT 24 109556664 ps
T899 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.281448729 Jun 10 05:44:32 PM PDT 24 Jun 10 05:44:34 PM PDT 24 41244382 ps
T127 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.6639534 Jun 10 05:45:36 PM PDT 24 Jun 10 05:45:41 PM PDT 24 104531477 ps
T900 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.3340511664 Jun 10 05:45:04 PM PDT 24 Jun 10 05:45:05 PM PDT 24 93362676 ps
T901 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.3611462576 Jun 10 05:45:06 PM PDT 24 Jun 10 05:45:08 PM PDT 24 111281333 ps
T902 /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.2221728648 Jun 10 05:44:59 PM PDT 24 Jun 10 05:45:01 PM PDT 24 261816933 ps
T903 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.1915611588 Jun 10 05:45:40 PM PDT 24 Jun 10 05:45:42 PM PDT 24 45143042 ps
T904 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.2976771382 Jun 10 05:44:46 PM PDT 24 Jun 10 05:44:47 PM PDT 24 31137602 ps
T905 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.4047451878 Jun 10 05:44:56 PM PDT 24 Jun 10 05:45:03 PM PDT 24 5866389915 ps
T906 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.3093411144 Jun 10 05:44:47 PM PDT 24 Jun 10 05:44:48 PM PDT 24 29657767 ps
T907 /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.1438067245 Jun 10 05:45:08 PM PDT 24 Jun 10 05:45:09 PM PDT 24 53651929 ps
T908 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.657417766 Jun 10 05:44:52 PM PDT 24 Jun 10 05:44:53 PM PDT 24 105884041 ps
T909 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.3921411318 Jun 10 05:45:38 PM PDT 24 Jun 10 05:45:39 PM PDT 24 37457537 ps
T910 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2105853778 Jun 10 05:45:10 PM PDT 24 Jun 10 05:45:12 PM PDT 24 102511726 ps
T911 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.451683232 Jun 10 05:45:12 PM PDT 24 Jun 10 05:45:15 PM PDT 24 451176475 ps
T912 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.2150077455 Jun 10 05:44:33 PM PDT 24 Jun 10 05:45:04 PM PDT 24 10448609642 ps
T913 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.3790950122 Jun 10 05:45:42 PM PDT 24 Jun 10 05:45:43 PM PDT 24 18527241 ps
T914 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.526661756 Jun 10 05:44:56 PM PDT 24 Jun 10 05:44:58 PM PDT 24 35955913 ps
T915 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.4019877025 Jun 10 05:44:46 PM PDT 24 Jun 10 05:44:48 PM PDT 24 46275406 ps
T916 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.2476251344 Jun 10 05:44:36 PM PDT 24 Jun 10 05:44:38 PM PDT 24 102518963 ps
T917 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.428097153 Jun 10 05:45:08 PM PDT 24 Jun 10 05:45:10 PM PDT 24 56731742 ps
T918 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.635570626 Jun 10 05:44:34 PM PDT 24 Jun 10 05:44:38 PM PDT 24 864692793 ps
T919 /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.3744453775 Jun 10 05:45:28 PM PDT 24 Jun 10 05:45:30 PM PDT 24 87749638 ps
T920 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.576918789 Jun 10 05:44:54 PM PDT 24 Jun 10 05:44:56 PM PDT 24 57636443 ps
T117 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.3805112132 Jun 10 05:45:32 PM PDT 24 Jun 10 05:45:36 PM PDT 24 119824285 ps
T921 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.3152580159 Jun 10 05:44:46 PM PDT 24 Jun 10 05:44:48 PM PDT 24 45897109 ps
T922 /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.3641891153 Jun 10 05:45:37 PM PDT 24 Jun 10 05:45:39 PM PDT 24 151092290 ps
T923 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.3416269954 Jun 10 05:45:22 PM PDT 24 Jun 10 05:45:23 PM PDT 24 76933441 ps
T139 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.2331655576 Jun 10 05:44:46 PM PDT 24 Jun 10 05:44:48 PM PDT 24 212777074 ps
T924 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.862268230 Jun 10 05:44:32 PM PDT 24 Jun 10 05:44:34 PM PDT 24 101750736 ps
T925 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1154838971 Jun 10 05:44:59 PM PDT 24 Jun 10 05:45:02 PM PDT 24 664148039 ps
T129 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.3718283500 Jun 10 05:44:33 PM PDT 24 Jun 10 05:44:36 PM PDT 24 121262593 ps
T926 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.1428810125 Jun 10 05:45:29 PM PDT 24 Jun 10 05:45:32 PM PDT 24 139027364 ps
T927 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.2716072398 Jun 10 05:45:24 PM PDT 24 Jun 10 05:45:25 PM PDT 24 38667697 ps
T126 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.358565913 Jun 10 05:45:22 PM PDT 24 Jun 10 05:45:24 PM PDT 24 59296185 ps
T928 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.4198504904 Jun 10 05:44:43 PM PDT 24 Jun 10 05:44:44 PM PDT 24 81527819 ps
T137 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.461517928 Jun 10 05:45:02 PM PDT 24 Jun 10 05:45:06 PM PDT 24 138844025 ps
T929 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.136216659 Jun 10 05:45:29 PM PDT 24 Jun 10 05:45:30 PM PDT 24 83941431 ps
T930 /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.2063432829 Jun 10 05:45:39 PM PDT 24 Jun 10 05:45:40 PM PDT 24 25513066 ps
T194 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.1454623315 Jun 10 05:45:09 PM PDT 24 Jun 10 05:45:11 PM PDT 24 98434016 ps
T931 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.1265048343 Jun 10 05:44:47 PM PDT 24 Jun 10 05:44:49 PM PDT 24 39477851 ps
T932 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.1355079318 Jun 10 05:45:14 PM PDT 24 Jun 10 05:45:17 PM PDT 24 1258829487 ps
T142 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.4006229544 Jun 10 05:45:15 PM PDT 24 Jun 10 05:45:19 PM PDT 24 420751002 ps
T933 /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.180772749 Jun 10 05:45:34 PM PDT 24 Jun 10 05:45:36 PM PDT 24 86250916 ps
T934 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.489631882 Jun 10 05:44:44 PM PDT 24 Jun 10 05:44:46 PM PDT 24 183679474 ps
T935 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.218772747 Jun 10 05:45:11 PM PDT 24 Jun 10 05:45:13 PM PDT 24 16858596 ps
T936 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.1760128329 Jun 10 05:45:01 PM PDT 24 Jun 10 05:45:03 PM PDT 24 79521578 ps
T195 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.2118001189 Jun 10 05:45:01 PM PDT 24 Jun 10 05:45:02 PM PDT 24 168721358 ps
T937 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2355423620 Jun 10 05:45:11 PM PDT 24 Jun 10 05:45:14 PM PDT 24 247180717 ps
T938 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.37754440 Jun 10 05:45:41 PM PDT 24 Jun 10 05:45:42 PM PDT 24 47790598 ps
T939 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.1902160202 Jun 10 05:45:20 PM PDT 24 Jun 10 05:45:22 PM PDT 24 207318730 ps
T940 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.3716062978 Jun 10 05:45:18 PM PDT 24 Jun 10 05:45:20 PM PDT 24 90381610 ps
T941 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.4198734653 Jun 10 05:44:49 PM PDT 24 Jun 10 05:44:51 PM PDT 24 79051156 ps
T196 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.3546875437 Jun 10 05:45:28 PM PDT 24 Jun 10 05:45:29 PM PDT 24 40465555 ps
T942 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.1877085599 Jun 10 05:44:56 PM PDT 24 Jun 10 05:44:58 PM PDT 24 78753751 ps
T141 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.1546835687 Jun 10 05:45:32 PM PDT 24 Jun 10 05:45:36 PM PDT 24 387476419 ps
T943 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.2092815494 Jun 10 05:45:20 PM PDT 24 Jun 10 05:45:24 PM PDT 24 151702519 ps
T197 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.2303572208 Jun 10 05:44:54 PM PDT 24 Jun 10 05:44:55 PM PDT 24 43603249 ps
T944 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.1502408068 Jun 10 05:45:31 PM PDT 24 Jun 10 05:45:33 PM PDT 24 29346253 ps
T945 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.3370912072 Jun 10 05:44:54 PM PDT 24 Jun 10 05:45:10 PM PDT 24 2210970168 ps
T946 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.3882841344 Jun 10 05:45:33 PM PDT 24 Jun 10 05:45:39 PM PDT 24 146304768 ps
T138 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.850230881 Jun 10 05:45:20 PM PDT 24 Jun 10 05:45:22 PM PDT 24 199531785 ps
T947 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.1641492194 Jun 10 05:45:33 PM PDT 24 Jun 10 05:45:36 PM PDT 24 230337156 ps
T948 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.383853061 Jun 10 05:45:16 PM PDT 24 Jun 10 05:45:18 PM PDT 24 100943488 ps
T949 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.3758823531 Jun 10 05:44:36 PM PDT 24 Jun 10 05:44:38 PM PDT 24 73563093 ps
T130 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.3734093059 Jun 10 05:45:26 PM PDT 24 Jun 10 05:45:31 PM PDT 24 409346254 ps
T950 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.119173960 Jun 10 05:44:47 PM PDT 24 Jun 10 05:44:49 PM PDT 24 51325739 ps
T951 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.2647510095 Jun 10 05:45:38 PM PDT 24 Jun 10 05:45:40 PM PDT 24 169154080 ps
T952 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.2513972726 Jun 10 05:45:35 PM PDT 24 Jun 10 05:45:39 PM PDT 24 71921457 ps
T131 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.1794707039 Jun 10 05:45:34 PM PDT 24 Jun 10 05:45:37 PM PDT 24 187199461 ps
T953 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.2056469818 Jun 10 05:44:34 PM PDT 24 Jun 10 05:44:41 PM PDT 24 1688662536 ps
T143 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.265381017 Jun 10 05:45:17 PM PDT 24 Jun 10 05:45:19 PM PDT 24 65399575 ps
T954 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.2321255631 Jun 10 05:45:27 PM PDT 24 Jun 10 05:45:29 PM PDT 24 206006945 ps
T140 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.381032073 Jun 10 05:45:36 PM PDT 24 Jun 10 05:45:38 PM PDT 24 374278989 ps
T955 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.1307282879 Jun 10 05:45:08 PM PDT 24 Jun 10 05:45:13 PM PDT 24 189658870 ps
T956 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.1354434831 Jun 10 05:44:33 PM PDT 24 Jun 10 05:44:34 PM PDT 24 87462923 ps
T957 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.148003562 Jun 10 05:45:36 PM PDT 24 Jun 10 05:45:41 PM PDT 24 223898746 ps
T958 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.180774654 Jun 10 05:45:14 PM PDT 24 Jun 10 05:45:16 PM PDT 24 75211155 ps
T959 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.1516760063 Jun 10 05:45:16 PM PDT 24 Jun 10 05:45:22 PM PDT 24 366430715 ps
T960 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.2671996107 Jun 10 05:45:15 PM PDT 24 Jun 10 05:45:22 PM PDT 24 1098669711 ps
T961 /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.239998227 Jun 10 05:45:16 PM PDT 24 Jun 10 05:45:17 PM PDT 24 24368359 ps
T198 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.2758362209 Jun 10 05:45:34 PM PDT 24 Jun 10 05:45:35 PM PDT 24 29418857 ps
T962 /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.278098816 Jun 10 05:45:27 PM PDT 24 Jun 10 05:45:29 PM PDT 24 67871680 ps
T963 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.2364593709 Jun 10 05:44:34 PM PDT 24 Jun 10 05:44:35 PM PDT 24 136560898 ps
T964 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.4023161245 Jun 10 05:45:26 PM PDT 24 Jun 10 05:45:32 PM PDT 24 757724583 ps
T965 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.1458753277 Jun 10 05:45:38 PM PDT 24 Jun 10 05:45:41 PM PDT 24 51852271 ps
T966 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.3480087699 Jun 10 05:45:20 PM PDT 24 Jun 10 05:45:22 PM PDT 24 31770381 ps
T967 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.3003679453 Jun 10 05:45:01 PM PDT 24 Jun 10 05:45:07 PM PDT 24 2849693095 ps
T968 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.2019503417 Jun 10 05:44:54 PM PDT 24 Jun 10 05:44:56 PM PDT 24 67035335 ps
T969 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.956486639 Jun 10 05:45:12 PM PDT 24 Jun 10 05:45:15 PM PDT 24 37844389 ps
T970 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1161428605 Jun 10 05:45:25 PM PDT 24 Jun 10 05:45:27 PM PDT 24 60907054 ps
T132 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.1927596767 Jun 10 05:45:31 PM PDT 24 Jun 10 05:45:35 PM PDT 24 397987674 ps
T971 /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.2059209711 Jun 10 05:45:25 PM PDT 24 Jun 10 05:45:26 PM PDT 24 19302934 ps
T972 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3095604247 Jun 10 05:44:57 PM PDT 24 Jun 10 05:44:59 PM PDT 24 64081348 ps
T973 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.1075272502 Jun 10 05:45:20 PM PDT 24 Jun 10 05:45:22 PM PDT 24 86788837 ps
T974 /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.1490505752 Jun 10 05:44:43 PM PDT 24 Jun 10 05:44:44 PM PDT 24 135508144 ps
T975 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.3939848210 Jun 10 05:45:25 PM PDT 24 Jun 10 05:45:38 PM PDT 24 547858152 ps
T976 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.1202609175 Jun 10 05:44:34 PM PDT 24 Jun 10 05:44:36 PM PDT 24 22409231 ps
T977 /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.2797777471 Jun 10 05:44:35 PM PDT 24 Jun 10 05:44:37 PM PDT 24 514151319 ps
T122 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.1788609342 Jun 10 05:45:40 PM PDT 24 Jun 10 05:45:43 PM PDT 24 630331042 ps
T978 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.3069321596 Jun 10 05:45:12 PM PDT 24 Jun 10 05:45:15 PM PDT 24 41930761 ps
T979 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.3307405539 Jun 10 05:45:20 PM PDT 24 Jun 10 05:45:22 PM PDT 24 244918970 ps
T980 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.3536632279 Jun 10 05:45:07 PM PDT 24 Jun 10 05:45:10 PM PDT 24 384300959 ps
T199 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.339640046 Jun 10 05:45:29 PM PDT 24 Jun 10 05:45:30 PM PDT 24 22824034 ps
T981 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.3652385234 Jun 10 05:44:45 PM PDT 24 Jun 10 05:44:47 PM PDT 24 160794231 ps
T982 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.3183220283 Jun 10 05:45:28 PM PDT 24 Jun 10 05:45:30 PM PDT 24 20339943 ps
T983 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.697331437 Jun 10 05:44:49 PM PDT 24 Jun 10 05:44:53 PM PDT 24 122251300 ps
T984 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.2221812738 Jun 10 05:44:37 PM PDT 24 Jun 10 05:44:38 PM PDT 24 65550224 ps
T985 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.3418219868 Jun 10 05:44:45 PM PDT 24 Jun 10 05:45:09 PM PDT 24 4265325302 ps
T986 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.2673026913 Jun 10 05:44:54 PM PDT 24 Jun 10 05:44:55 PM PDT 24 57187220 ps
T987 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.3447103613 Jun 10 05:44:47 PM PDT 24 Jun 10 05:44:49 PM PDT 24 17835786 ps
T988 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.954174630 Jun 10 05:44:32 PM PDT 24 Jun 10 05:44:35 PM PDT 24 79864964 ps
T133 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.2736866601 Jun 10 05:44:56 PM PDT 24 Jun 10 05:45:00 PM PDT 24 627394365 ps
T135 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.3552854548 Jun 10 05:45:42 PM PDT 24 Jun 10 05:45:45 PM PDT 24 44093180 ps
T200 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.994826341 Jun 10 05:44:31 PM PDT 24 Jun 10 05:44:32 PM PDT 24 15959126 ps
T201 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.314354543 Jun 10 05:45:12 PM PDT 24 Jun 10 05:45:13 PM PDT 24 33958441 ps
T989 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.3388793135 Jun 10 05:45:31 PM PDT 24 Jun 10 05:45:34 PM PDT 24 168616661 ps
T990 /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.3182577608 Jun 10 05:45:15 PM PDT 24 Jun 10 05:45:17 PM PDT 24 76610780 ps
T991 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.324279333 Jun 10 05:44:46 PM PDT 24 Jun 10 05:44:49 PM PDT 24 396198248 ps
T992 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.2273671459 Jun 10 05:44:54 PM PDT 24 Jun 10 05:44:56 PM PDT 24 39601486 ps
T993 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.2282120507 Jun 10 05:45:34 PM PDT 24 Jun 10 05:45:36 PM PDT 24 135352810 ps
T994 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.2390433483 Jun 10 05:45:14 PM PDT 24 Jun 10 05:45:21 PM PDT 24 425159493 ps
T995 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.731078447 Jun 10 05:45:00 PM PDT 24 Jun 10 05:45:02 PM PDT 24 86407300 ps
T996 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.276459060 Jun 10 05:45:24 PM PDT 24 Jun 10 05:45:26 PM PDT 24 61291233 ps
T997 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.1277663285 Jun 10 05:45:34 PM PDT 24 Jun 10 05:45:36 PM PDT 24 21518088 ps
T998 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3026792198 Jun 10 05:45:08 PM PDT 24 Jun 10 05:45:10 PM PDT 24 82590529 ps
T999 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.4094244343 Jun 10 05:45:27 PM PDT 24 Jun 10 05:45:47 PM PDT 24 2922676236 ps

Test location /workspace/coverage/default/6.lc_ctrl_sec_mubi.3043774602
Short name T3
Test name
Test status
Simulation time 1095673375 ps
CPU time 14.01 seconds
Started Jun 10 05:47:09 PM PDT 24
Finished Jun 10 05:47:23 PM PDT 24
Peak memory 218784 kb
Host smart-e5b55a88-fe3c-4665-acb1-ec9270f6858a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043774602 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_mubi.3043774602
Directory /workspace/6.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all.1506198843
Short name T17
Test name
Test status
Simulation time 80792238574 ps
CPU time 268.22 seconds
Started Jun 10 05:49:17 PM PDT 24
Finished Jun 10 05:53:45 PM PDT 24
Peak memory 284268 kb
Host smart-28648a1f-1dee-478c-af07-8ae99d337e38
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506198843 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.lc_ctrl_stress_all.1506198843
Directory /workspace/36.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.lc_ctrl_security_escalation.1946976489
Short name T13
Test name
Test status
Simulation time 2172116107 ps
CPU time 13.24 seconds
Started Jun 10 05:48:04 PM PDT 24
Finished Jun 10 05:48:18 PM PDT 24
Peak memory 226600 kb
Host smart-65e26c04-1edc-4f85-bc65-136ac1293b9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946976489 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_security_escalation.1946976489
Directory /workspace/17.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.2095690665
Short name T114
Test name
Test status
Simulation time 104562722 ps
CPU time 2.2 seconds
Started Jun 10 05:45:30 PM PDT 24
Finished Jun 10 05:45:32 PM PDT 24
Peak memory 219852 kb
Host smart-1ded4fde-e86c-4bd9-9785-911dbd6eacac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095690665 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 15.lc_ctrl_csr_mem_rw_with_rand_reset.2095690665
Directory /workspace/15.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all_with_rand_reset.1931094321
Short name T49
Test name
Test status
Simulation time 14598515913 ps
CPU time 304.91 seconds
Started Jun 10 05:48:44 PM PDT 24
Finished Jun 10 05:53:49 PM PDT 24
Peak memory 286932 kb
Host smart-093169be-6af0-450a-ab0f-4d6baad48a0b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1931094321 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_stress_all_with_rand_reset.1931094321
Directory /workspace/27.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_cm.2309488071
Short name T67
Test name
Test status
Simulation time 823049908 ps
CPU time 38.33 seconds
Started Jun 10 05:46:46 PM PDT 24
Finished Jun 10 05:47:25 PM PDT 24
Peak memory 271636 kb
Host smart-25e813d3-8a89-4ff7-81a7-9a80552a35a5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309488071 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_cm.2309488071
Directory /workspace/2.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.lc_ctrl_security_escalation.2457669853
Short name T54
Test name
Test status
Simulation time 172301455 ps
CPU time 6.36 seconds
Started Jun 10 05:46:52 PM PDT 24
Finished Jun 10 05:46:59 PM PDT 24
Peak memory 218844 kb
Host smart-36d4eb30-4a28-4dfe-bb8c-6ea7a9186fcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457669853 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_security_escalation.2457669853
Directory /workspace/3.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/12.lc_ctrl_volatile_unlock_smoke.333501455
Short name T39
Test name
Test status
Simulation time 14624625 ps
CPU time 0.98 seconds
Started Jun 10 05:47:37 PM PDT 24
Finished Jun 10 05:47:39 PM PDT 24
Peak memory 209648 kb
Host smart-09bf9b47-3bb1-45bd-951c-076df965df7e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333501455 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ct
rl_volatile_unlock_smoke.333501455
Directory /workspace/12.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_mux.3378077297
Short name T53
Test name
Test status
Simulation time 4062272944 ps
CPU time 9.4 seconds
Started Jun 10 05:47:14 PM PDT 24
Finished Jun 10 05:47:24 PM PDT 24
Peak memory 226524 kb
Host smart-46979ce1-2a51-44b5-9124-dbf3781da4b6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378077297 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_mux.3
378077297
Directory /workspace/7.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_cm.3307818210
Short name T57
Test name
Test status
Simulation time 1387436272 ps
CPU time 37.5 seconds
Started Jun 10 05:46:50 PM PDT 24
Finished Jun 10 05:47:28 PM PDT 24
Peak memory 282412 kb
Host smart-572c7469-a5eb-4b46-b68f-37be772fc785
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307818210 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_cm.3307818210
Directory /workspace/3.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/33.lc_ctrl_jtag_access.84844341
Short name T9
Test name
Test status
Simulation time 931170475 ps
CPU time 6.14 seconds
Started Jun 10 05:49:03 PM PDT 24
Finished Jun 10 05:49:09 PM PDT 24
Peak memory 217808 kb
Host smart-88b6ff37-67fe-4981-b028-c9983c8d2878
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84844341 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_jtag_access.84844341
Directory /workspace/33.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all_with_rand_reset.628685539
Short name T78
Test name
Test status
Simulation time 39872606673 ps
CPU time 658.95 seconds
Started Jun 10 05:47:07 PM PDT 24
Finished Jun 10 05:58:07 PM PDT 24
Peak memory 373492 kb
Host smart-955bdc04-dede-4ed1-96d5-0e202546d0c2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=628685539 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_stress_all_with_rand_reset.628685539
Directory /workspace/6.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all_with_rand_reset.1525004462
Short name T62
Test name
Test status
Simulation time 3560321453 ps
CPU time 194.13 seconds
Started Jun 10 05:49:50 PM PDT 24
Finished Jun 10 05:53:05 PM PDT 24
Peak memory 277572 kb
Host smart-d5134329-8742-4d39-b2e4-1afcfa31f937
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1525004462 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_stress_all_with_rand_reset.1525004462
Directory /workspace/48.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.3805112132
Short name T117
Test name
Test status
Simulation time 119824285 ps
CPU time 4.28 seconds
Started Jun 10 05:45:32 PM PDT 24
Finished Jun 10 05:45:36 PM PDT 24
Peak memory 218148 kb
Host smart-109de289-4a1a-4831-af78-4098888738b6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805112132 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_intg
_err.3805112132
Directory /workspace/16.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.1872876696
Short name T144
Test name
Test status
Simulation time 303466522 ps
CPU time 4.17 seconds
Started Jun 10 05:44:36 PM PDT 24
Finished Jun 10 05:44:40 PM PDT 24
Peak memory 211400 kb
Host smart-daa57a19-6cc5-4051-a6e4-71c794e383a0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872876696 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_hw_reset.1872876696
Directory /workspace/1.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.2303572208
Short name T197
Test name
Test status
Simulation time 43603249 ps
CPU time 0.99 seconds
Started Jun 10 05:44:54 PM PDT 24
Finished Jun 10 05:44:55 PM PDT 24
Peak memory 209644 kb
Host smart-45cdfa9b-6456-4551-a34b-44df948c81f0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303572208 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_rw.2303572208
Directory /workspace/2.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/default/13.lc_ctrl_alert_test.3392867928
Short name T90
Test name
Test status
Simulation time 12946844 ps
CPU time 1.01 seconds
Started Jun 10 05:47:52 PM PDT 24
Finished Jun 10 05:47:53 PM PDT 24
Peak memory 209396 kb
Host smart-fff28b73-9bba-4a64-8fb1-8d21282e9513
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392867928 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_alert_test.3392867928
Directory /workspace/13.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all.332609254
Short name T215
Test name
Test status
Simulation time 6945750602 ps
CPU time 227.91 seconds
Started Jun 10 05:48:15 PM PDT 24
Finished Jun 10 05:52:03 PM PDT 24
Peak memory 292444 kb
Host smart-1859a7e9-c3dd-4499-b6c6-ba0a31bf17a2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332609254 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.lc_ctrl_stress_all.332609254
Directory /workspace/19.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all.3910663378
Short name T16
Test name
Test status
Simulation time 26806503240 ps
CPU time 199.53 seconds
Started Jun 10 05:48:52 PM PDT 24
Finished Jun 10 05:52:12 PM PDT 24
Peak memory 221700 kb
Host smart-a2fe6ee7-8483-4f08-851a-6cdb4b530790
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910663378 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.lc_ctrl_stress_all.3910663378
Directory /workspace/30.lc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.2736866601
Short name T133
Test name
Test status
Simulation time 627394365 ps
CPU time 3.96 seconds
Started Jun 10 05:44:56 PM PDT 24
Finished Jun 10 05:45:00 PM PDT 24
Peak memory 218256 kb
Host smart-c089a5a0-63eb-4af7-9c95-3cf5d2befd25
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736866601 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_intg_
err.2736866601
Directory /workspace/3.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.1794707039
Short name T131
Test name
Test status
Simulation time 187199461 ps
CPU time 2.85 seconds
Started Jun 10 05:45:34 PM PDT 24
Finished Jun 10 05:45:37 PM PDT 24
Peak memory 222616 kb
Host smart-1e420fd2-3b37-4e2a-83ba-2c6d736707be
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794707039 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_intg
_err.1794707039
Directory /workspace/15.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all_with_rand_reset.1146281242
Short name T93
Test name
Test status
Simulation time 87220229404 ps
CPU time 329.48 seconds
Started Jun 10 05:49:37 PM PDT 24
Finished Jun 10 05:55:07 PM PDT 24
Peak memory 454572 kb
Host smart-cbbb0a43-c6de-4f31-858b-59f8cb7628f0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1146281242 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_stress_all_with_rand_reset.1146281242
Directory /workspace/43.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.6639534
Short name T127
Test name
Test status
Simulation time 104531477 ps
CPU time 4.36 seconds
Started Jun 10 05:45:36 PM PDT 24
Finished Jun 10 05:45:41 PM PDT 24
Peak memory 218212 kb
Host smart-4c901100-7206-4e22-8309-94edbb9b0577
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6639534 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_errors.6639534
Directory /workspace/18.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.324130788
Short name T204
Test name
Test status
Simulation time 27572459 ps
CPU time 1.34 seconds
Started Jun 10 05:45:38 PM PDT 24
Finished Jun 10 05:45:39 PM PDT 24
Peak memory 210028 kb
Host smart-c939baf1-34f1-4ad9-bb26-c9672a526ce3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324130788 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl
_same_csr_outstanding.324130788
Directory /workspace/17.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all_with_rand_reset.4169562690
Short name T109
Test name
Test status
Simulation time 41439272624 ps
CPU time 836.89 seconds
Started Jun 10 05:47:58 PM PDT 24
Finished Jun 10 06:01:55 PM PDT 24
Peak memory 317104 kb
Host smart-5461ca01-7f8a-4798-b02f-131ce268ae14
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4169562690 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_stress_all_with_rand_reset.4169562690
Directory /workspace/15.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.lc_ctrl_stress_all_with_rand_reset.1650508797
Short name T96
Test name
Test status
Simulation time 80163074118 ps
CPU time 1067.01 seconds
Started Jun 10 05:46:40 PM PDT 24
Finished Jun 10 06:04:27 PM PDT 24
Peak memory 333516 kb
Host smart-7313457b-a02d-47c1-9c1d-f15a50c8af4b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1650508797 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_stress_all_with_rand_reset.1650508797
Directory /workspace/1.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.lc_ctrl_security_escalation.2403648113
Short name T1
Test name
Test status
Simulation time 1881260806 ps
CPU time 11.68 seconds
Started Jun 10 05:47:54 PM PDT 24
Finished Jun 10 05:48:06 PM PDT 24
Peak memory 225888 kb
Host smart-5f533749-ee72-4260-ba66-0ccfe28700ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403648113 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_security_escalation.2403648113
Directory /workspace/15.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.3718283500
Short name T129
Test name
Test status
Simulation time 121262593 ps
CPU time 2.8 seconds
Started Jun 10 05:44:33 PM PDT 24
Finished Jun 10 05:44:36 PM PDT 24
Peak memory 222432 kb
Host smart-ce9ca029-fb13-4f84-b410-26be0b562a63
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718283500 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_intg_
err.3718283500
Directory /workspace/0.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.3734093059
Short name T130
Test name
Test status
Simulation time 409346254 ps
CPU time 3.83 seconds
Started Jun 10 05:45:26 PM PDT 24
Finished Jun 10 05:45:31 PM PDT 24
Peak memory 218244 kb
Host smart-a1096e20-6872-4fca-a81c-50a72b434dba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734093059 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_intg
_err.3734093059
Directory /workspace/11.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.1788609342
Short name T122
Test name
Test status
Simulation time 630331042 ps
CPU time 3.32 seconds
Started Jun 10 05:45:40 PM PDT 24
Finished Jun 10 05:45:43 PM PDT 24
Peak memory 222824 kb
Host smart-2297986f-0710-4617-872c-2f93fc9d6b87
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788609342 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_intg
_err.1788609342
Directory /workspace/17.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.3956166288
Short name T112
Test name
Test status
Simulation time 163044975 ps
CPU time 3.86 seconds
Started Jun 10 05:44:47 PM PDT 24
Finished Jun 10 05:44:52 PM PDT 24
Peak memory 222844 kb
Host smart-719324e3-d1a4-42a7-8b40-6c3d195a95f1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956166288 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_intg_
err.3956166288
Directory /workspace/2.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_claim_transition_if.838666549
Short name T206
Test name
Test status
Simulation time 32633807 ps
CPU time 0.8 seconds
Started Jun 10 05:46:35 PM PDT 24
Finished Jun 10 05:46:36 PM PDT 24
Peak memory 209488 kb
Host smart-9246bc36-98c0-485a-b914-a2016840ab7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838666549 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_claim_transition_if.838666549
Directory /workspace/0.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/1.lc_ctrl_claim_transition_if.951878794
Short name T210
Test name
Test status
Simulation time 13706012 ps
CPU time 1.03 seconds
Started Jun 10 05:46:36 PM PDT 24
Finished Jun 10 05:46:37 PM PDT 24
Peak memory 209472 kb
Host smart-1e71fea6-617a-41a8-a450-63b9393d4c06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951878794 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_claim_transition_if.951878794
Directory /workspace/1.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/3.lc_ctrl_claim_transition_if.827690262
Short name T207
Test name
Test status
Simulation time 42073786 ps
CPU time 0.79 seconds
Started Jun 10 05:46:46 PM PDT 24
Finished Jun 10 05:46:47 PM PDT 24
Peak memory 209400 kb
Host smart-271fdf8a-7ad8-4637-9abc-ef5ec3eef4e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827690262 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_claim_transition_if.827690262
Directory /workspace/3.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/5.lc_ctrl_claim_transition_if.2591036765
Short name T211
Test name
Test status
Simulation time 21464520 ps
CPU time 0.81 seconds
Started Jun 10 05:46:58 PM PDT 24
Finished Jun 10 05:46:59 PM PDT 24
Peak memory 209336 kb
Host smart-0a8af0b9-2929-4c47-874e-a416c5b648a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591036765 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_claim_transition_if.2591036765
Directory /workspace/5.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_mubi.1985599226
Short name T19
Test name
Test status
Simulation time 234209710 ps
CPU time 8.09 seconds
Started Jun 10 05:48:54 PM PDT 24
Finished Jun 10 05:49:03 PM PDT 24
Peak memory 218816 kb
Host smart-65c09cf3-479d-444a-8e01-c57e82c20054
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985599226 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_mubi.1985599226
Directory /workspace/30.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.358565913
Short name T126
Test name
Test status
Simulation time 59296185 ps
CPU time 2.4 seconds
Started Jun 10 05:45:22 PM PDT 24
Finished Jun 10 05:45:24 PM PDT 24
Peak memory 218248 kb
Host smart-a40274b3-ca4d-49ba-b704-814733baba2c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358565913 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_intg_
err.358565913
Directory /workspace/10.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.1546835687
Short name T141
Test name
Test status
Simulation time 387476419 ps
CPU time 3.35 seconds
Started Jun 10 05:45:32 PM PDT 24
Finished Jun 10 05:45:36 PM PDT 24
Peak memory 218160 kb
Host smart-0a80fbd9-bed7-4c9a-93d5-8b00501e8196
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546835687 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_intg
_err.1546835687
Directory /workspace/13.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all.1951760935
Short name T51
Test name
Test status
Simulation time 7213477356 ps
CPU time 123.72 seconds
Started Jun 10 05:49:46 PM PDT 24
Finished Jun 10 05:51:50 PM PDT 24
Peak memory 267952 kb
Host smart-75f6e22b-34a5-429d-a498-83dbd4086fff
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951760935 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.lc_ctrl_stress_all.1951760935
Directory /workspace/46.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all.1253200389
Short name T66
Test name
Test status
Simulation time 2287537720 ps
CPU time 67.21 seconds
Started Jun 10 05:47:46 PM PDT 24
Finished Jun 10 05:48:54 PM PDT 24
Peak memory 251456 kb
Host smart-6f4143f0-f5f4-4833-8753-d4338b2eded9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253200389 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.lc_ctrl_stress_all.1253200389
Directory /workspace/13.lc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.2221812738
Short name T984
Test name
Test status
Simulation time 65550224 ps
CPU time 1.31 seconds
Started Jun 10 05:44:37 PM PDT 24
Finished Jun 10 05:44:38 PM PDT 24
Peak memory 209972 kb
Host smart-2da59947-b1fe-4cb9-8e37-d6f189c2420e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221812738 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_aliasin
g.2221812738
Directory /workspace/0.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.2476251344
Short name T916
Test name
Test status
Simulation time 102518963 ps
CPU time 1.58 seconds
Started Jun 10 05:44:36 PM PDT 24
Finished Jun 10 05:44:38 PM PDT 24
Peak memory 209976 kb
Host smart-f73815bb-89ce-49fd-b0c4-8b5f69acdbf4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476251344 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_bit_bas
h.2476251344
Directory /workspace/0.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.1202609175
Short name T976
Test name
Test status
Simulation time 22409231 ps
CPU time 1.11 seconds
Started Jun 10 05:44:34 PM PDT 24
Finished Jun 10 05:44:36 PM PDT 24
Peak memory 212152 kb
Host smart-7e8d9592-f5bc-49da-8173-9204610a73dc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202609175 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_hw_rese
t.1202609175
Directory /workspace/0.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.2540339326
Short name T886
Test name
Test status
Simulation time 75891407 ps
CPU time 1.22 seconds
Started Jun 10 05:44:33 PM PDT 24
Finished Jun 10 05:44:34 PM PDT 24
Peak memory 218140 kb
Host smart-a9719ba7-fb20-4325-82fe-df91ca7400a6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540339326 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 0.lc_ctrl_csr_mem_rw_with_rand_reset.2540339326
Directory /workspace/0.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.994826341
Short name T200
Test name
Test status
Simulation time 15959126 ps
CPU time 1.03 seconds
Started Jun 10 05:44:31 PM PDT 24
Finished Jun 10 05:44:32 PM PDT 24
Peak memory 209484 kb
Host smart-51785fed-cfb3-4ae9-b41c-6d393b3205e1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994826341 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_rw.994826341
Directory /workspace/0.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.862268230
Short name T924
Test name
Test status
Simulation time 101750736 ps
CPU time 1.27 seconds
Started Jun 10 05:44:32 PM PDT 24
Finished Jun 10 05:44:34 PM PDT 24
Peak memory 209212 kb
Host smart-489a227f-307f-4c69-b725-da2e1f01f1b7
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862268230 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 0.lc_ctrl_jtag_alert_test.862268230
Directory /workspace/0.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.4227393710
Short name T884
Test name
Test status
Simulation time 2225423275 ps
CPU time 5.38 seconds
Started Jun 10 05:44:37 PM PDT 24
Finished Jun 10 05:44:43 PM PDT 24
Peak memory 209560 kb
Host smart-eb6ea777-5a8c-42d9-b94d-af3801e81172
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227393710 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_aliasing.4227393710
Directory /workspace/0.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.2150077455
Short name T912
Test name
Test status
Simulation time 10448609642 ps
CPU time 30.71 seconds
Started Jun 10 05:44:33 PM PDT 24
Finished Jun 10 05:45:04 PM PDT 24
Peak memory 217916 kb
Host smart-77d3110a-30e3-400b-9088-6f4df61d4d07
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150077455 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_bit_bash.2150077455
Directory /workspace/0.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.954174630
Short name T988
Test name
Test status
Simulation time 79864964 ps
CPU time 2.73 seconds
Started Jun 10 05:44:32 PM PDT 24
Finished Jun 10 05:44:35 PM PDT 24
Peak memory 211444 kb
Host smart-0525f2b2-72a0-416d-a02c-5bcb46c01665
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954174630 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 0.lc_ctrl_jtag_csr_hw_reset.954174630
Directory /workspace/0.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.635570626
Short name T918
Test name
Test status
Simulation time 864692793 ps
CPU time 4.01 seconds
Started Jun 10 05:44:34 PM PDT 24
Finished Jun 10 05:44:38 PM PDT 24
Peak memory 220988 kb
Host smart-51a00eba-4abf-48bc-9f20-51f087dd9690
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635570
626 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.635570626
Directory /workspace/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.2364593709
Short name T963
Test name
Test status
Simulation time 136560898 ps
CPU time 1.37 seconds
Started Jun 10 05:44:34 PM PDT 24
Finished Jun 10 05:44:35 PM PDT 24
Peak memory 209764 kb
Host smart-a45a494c-d90a-4b1f-9e1b-45d64b1a46d0
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364593709 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.lc_ctrl_jtag_csr_rw.2364593709
Directory /workspace/0.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.281448729
Short name T899
Test name
Test status
Simulation time 41244382 ps
CPU time 1.64 seconds
Started Jun 10 05:44:32 PM PDT 24
Finished Jun 10 05:44:34 PM PDT 24
Peak memory 209984 kb
Host smart-a086e88e-40ed-4a1f-86cb-8ca88872c2e7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281448729 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.lc_ctrl_jtag_same_csr_outstanding.281448729
Directory /workspace/0.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.2797777471
Short name T977
Test name
Test status
Simulation time 514151319 ps
CPU time 1.96 seconds
Started Jun 10 05:44:35 PM PDT 24
Finished Jun 10 05:44:37 PM PDT 24
Peak memory 218156 kb
Host smart-587696b1-25e0-4331-8009-159f4ea9a50a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797777471 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl
_same_csr_outstanding.2797777471
Directory /workspace/0.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.1354434831
Short name T956
Test name
Test status
Simulation time 87462923 ps
CPU time 1.44 seconds
Started Jun 10 05:44:33 PM PDT 24
Finished Jun 10 05:44:34 PM PDT 24
Peak memory 219288 kb
Host smart-91b8610e-420c-424f-af46-70b0f46cbcd1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354434831 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_errors.1354434831
Directory /workspace/0.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.3076764224
Short name T191
Test name
Test status
Simulation time 33895110 ps
CPU time 1.3 seconds
Started Jun 10 05:44:46 PM PDT 24
Finished Jun 10 05:44:48 PM PDT 24
Peak memory 217700 kb
Host smart-9a148637-da66-4307-8bb2-ffe65c87fc61
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076764224 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_aliasin
g.3076764224
Directory /workspace/1.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.2976771382
Short name T904
Test name
Test status
Simulation time 31137602 ps
CPU time 1.25 seconds
Started Jun 10 05:44:46 PM PDT 24
Finished Jun 10 05:44:47 PM PDT 24
Peak memory 209868 kb
Host smart-4d1d63c5-36f9-4f0d-ac99-7da17ff8d21f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976771382 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_bit_bas
h.2976771382
Directory /workspace/1.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.4019877025
Short name T915
Test name
Test status
Simulation time 46275406 ps
CPU time 1 seconds
Started Jun 10 05:44:46 PM PDT 24
Finished Jun 10 05:44:48 PM PDT 24
Peak memory 210388 kb
Host smart-c21a5332-6eef-45bb-8be1-f4aa7eb16439
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019877025 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_hw_rese
t.4019877025
Directory /workspace/1.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.1100253528
Short name T895
Test name
Test status
Simulation time 40193880 ps
CPU time 1.23 seconds
Started Jun 10 05:44:42 PM PDT 24
Finished Jun 10 05:44:44 PM PDT 24
Peak memory 218324 kb
Host smart-f3d0fd76-472b-4dfe-9039-423272f09646
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100253528 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 1.lc_ctrl_csr_mem_rw_with_rand_reset.1100253528
Directory /workspace/1.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.3447103613
Short name T987
Test name
Test status
Simulation time 17835786 ps
CPU time 1.12 seconds
Started Jun 10 05:44:47 PM PDT 24
Finished Jun 10 05:44:49 PM PDT 24
Peak memory 217800 kb
Host smart-8f2327be-9174-49f6-b710-965aa2df35af
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447103613 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_rw.3447103613
Directory /workspace/1.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.3652385234
Short name T981
Test name
Test status
Simulation time 160794231 ps
CPU time 1.08 seconds
Started Jun 10 05:44:45 PM PDT 24
Finished Jun 10 05:44:47 PM PDT 24
Peak memory 209780 kb
Host smart-ae07d07e-8a3d-4c71-9aa0-99b3a164859d
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652385234 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.lc_ctrl_jtag_alert_test.3652385234
Directory /workspace/1.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.3496901883
Short name T882
Test name
Test status
Simulation time 1628703466 ps
CPU time 4.15 seconds
Started Jun 10 05:44:40 PM PDT 24
Finished Jun 10 05:44:44 PM PDT 24
Peak memory 209556 kb
Host smart-1ccef452-56db-4944-8090-8bd935052174
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496901883 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_aliasing.3496901883
Directory /workspace/1.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.2056469818
Short name T953
Test name
Test status
Simulation time 1688662536 ps
CPU time 6.58 seconds
Started Jun 10 05:44:34 PM PDT 24
Finished Jun 10 05:44:41 PM PDT 24
Peak memory 209780 kb
Host smart-064bd11e-bf14-4cdd-a53f-605cbe89b0b0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056469818 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_bit_bash.2056469818
Directory /workspace/1.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.324279333
Short name T991
Test name
Test status
Simulation time 396198248 ps
CPU time 2.64 seconds
Started Jun 10 05:44:46 PM PDT 24
Finished Jun 10 05:44:49 PM PDT 24
Peak memory 218332 kb
Host smart-e58296bd-4270-4e2b-abe8-1f7bb827002c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324279
333 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.324279333
Directory /workspace/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.3758823531
Short name T949
Test name
Test status
Simulation time 73563093 ps
CPU time 2.08 seconds
Started Jun 10 05:44:36 PM PDT 24
Finished Jun 10 05:44:38 PM PDT 24
Peak memory 209768 kb
Host smart-7e3e5be1-a83a-4f89-b988-51afba8e50fe
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758823531 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.lc_ctrl_jtag_csr_rw.3758823531
Directory /workspace/1.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.3093411144
Short name T906
Test name
Test status
Simulation time 29657767 ps
CPU time 1.08 seconds
Started Jun 10 05:44:47 PM PDT 24
Finished Jun 10 05:44:48 PM PDT 24
Peak memory 218152 kb
Host smart-3ec482d9-b2c3-4754-a6c1-a001ab5d61d6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093411144 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.lc_ctrl_jtag_same_csr_outstanding.3093411144
Directory /workspace/1.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.1490505752
Short name T974
Test name
Test status
Simulation time 135508144 ps
CPU time 1.26 seconds
Started Jun 10 05:44:43 PM PDT 24
Finished Jun 10 05:44:44 PM PDT 24
Peak memory 209716 kb
Host smart-2cd0fcaa-d609-4fe1-953e-3e5006cd2711
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490505752 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl
_same_csr_outstanding.1490505752
Directory /workspace/1.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.1664249376
Short name T113
Test name
Test status
Simulation time 126434454 ps
CPU time 2.23 seconds
Started Jun 10 05:44:48 PM PDT 24
Finished Jun 10 05:44:50 PM PDT 24
Peak memory 218624 kb
Host smart-1c346b78-1dc6-4c9a-b86e-4625c6079b46
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664249376 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_errors.1664249376
Directory /workspace/1.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.2331655576
Short name T139
Test name
Test status
Simulation time 212777074 ps
CPU time 1.91 seconds
Started Jun 10 05:44:46 PM PDT 24
Finished Jun 10 05:44:48 PM PDT 24
Peak memory 222448 kb
Host smart-a7f8431f-527d-41be-81d4-7a7231e45eb2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331655576 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_intg_
err.2331655576
Directory /workspace/1.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.3480087699
Short name T966
Test name
Test status
Simulation time 31770381 ps
CPU time 1.25 seconds
Started Jun 10 05:45:20 PM PDT 24
Finished Jun 10 05:45:22 PM PDT 24
Peak memory 218188 kb
Host smart-f82fdd42-c5b6-495c-b644-f59066da9b75
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480087699 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 10.lc_ctrl_csr_mem_rw_with_rand_reset.3480087699
Directory /workspace/10.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.136216659
Short name T929
Test name
Test status
Simulation time 83941431 ps
CPU time 0.9 seconds
Started Jun 10 05:45:29 PM PDT 24
Finished Jun 10 05:45:30 PM PDT 24
Peak memory 209508 kb
Host smart-0c19c143-09ca-4fc3-9fb5-d81256e374a9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136216659 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_csr_rw.136216659
Directory /workspace/10.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.278098816
Short name T962
Test name
Test status
Simulation time 67871680 ps
CPU time 1.44 seconds
Started Jun 10 05:45:27 PM PDT 24
Finished Jun 10 05:45:29 PM PDT 24
Peak memory 211944 kb
Host smart-a2c33def-a777-4eb0-a56d-bba374c67478
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278098816 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl
_same_csr_outstanding.278098816
Directory /workspace/10.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.2610631241
Short name T121
Test name
Test status
Simulation time 133157609 ps
CPU time 3.9 seconds
Started Jun 10 05:45:26 PM PDT 24
Finished Jun 10 05:45:30 PM PDT 24
Peak memory 218176 kb
Host smart-1b68a78b-2842-4dba-b660-d00d15adc700
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610631241 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_errors.2610631241
Directory /workspace/10.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.3183220283
Short name T982
Test name
Test status
Simulation time 20339943 ps
CPU time 1.11 seconds
Started Jun 10 05:45:28 PM PDT 24
Finished Jun 10 05:45:30 PM PDT 24
Peak memory 218192 kb
Host smart-6a907e49-bd64-4004-83b9-c64bb8a9bb24
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183220283 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 11.lc_ctrl_csr_mem_rw_with_rand_reset.3183220283
Directory /workspace/11.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.3546875437
Short name T196
Test name
Test status
Simulation time 40465555 ps
CPU time 0.99 seconds
Started Jun 10 05:45:28 PM PDT 24
Finished Jun 10 05:45:29 PM PDT 24
Peak memory 209568 kb
Host smart-4987f4fe-ba0a-4e19-af4b-93f98ab240fb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546875437 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_csr_rw.3546875437
Directory /workspace/11.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.3118706256
Short name T887
Test name
Test status
Simulation time 39570835 ps
CPU time 1.43 seconds
Started Jun 10 05:45:27 PM PDT 24
Finished Jun 10 05:45:29 PM PDT 24
Peak memory 209992 kb
Host smart-cd0ed155-b344-401c-86fa-f0e5538693c0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118706256 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctr
l_same_csr_outstanding.3118706256
Directory /workspace/11.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.1428810125
Short name T926
Test name
Test status
Simulation time 139027364 ps
CPU time 2.36 seconds
Started Jun 10 05:45:29 PM PDT 24
Finished Jun 10 05:45:32 PM PDT 24
Peak memory 218396 kb
Host smart-574e7e01-e4ec-4cf3-b9f6-1223e77e8615
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428810125 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_errors.1428810125
Directory /workspace/11.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.195811112
Short name T893
Test name
Test status
Simulation time 97951109 ps
CPU time 1.22 seconds
Started Jun 10 05:45:27 PM PDT 24
Finished Jun 10 05:45:29 PM PDT 24
Peak memory 220964 kb
Host smart-23f1501b-e4e6-4c36-99ee-283869cb501a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195811112 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 12.lc_ctrl_csr_mem_rw_with_rand_reset.195811112
Directory /workspace/12.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.2024416827
Short name T189
Test name
Test status
Simulation time 67085582 ps
CPU time 0.92 seconds
Started Jun 10 05:45:30 PM PDT 24
Finished Jun 10 05:45:32 PM PDT 24
Peak memory 209380 kb
Host smart-dc3cf8cc-a2f9-4672-a168-53e6abb15e85
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024416827 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_csr_rw.2024416827
Directory /workspace/12.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.3744453775
Short name T919
Test name
Test status
Simulation time 87749638 ps
CPU time 1.31 seconds
Started Jun 10 05:45:28 PM PDT 24
Finished Jun 10 05:45:30 PM PDT 24
Peak memory 210000 kb
Host smart-d9bb5318-1414-4d6c-b7d3-5c6c1aab958b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744453775 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctr
l_same_csr_outstanding.3744453775
Directory /workspace/12.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.1712968687
Short name T136
Test name
Test status
Simulation time 52910330 ps
CPU time 2.34 seconds
Started Jun 10 05:45:32 PM PDT 24
Finished Jun 10 05:45:35 PM PDT 24
Peak memory 218264 kb
Host smart-2f2144d5-7d42-496b-b29f-b13debc8828e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712968687 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_errors.1712968687
Directory /workspace/12.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.1927596767
Short name T132
Test name
Test status
Simulation time 397987674 ps
CPU time 4.06 seconds
Started Jun 10 05:45:31 PM PDT 24
Finished Jun 10 05:45:35 PM PDT 24
Peak memory 218116 kb
Host smart-c0b11f1e-eb02-4694-a2cd-0ad18b00f726
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927596767 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_intg
_err.1927596767
Directory /workspace/12.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.1277663285
Short name T997
Test name
Test status
Simulation time 21518088 ps
CPU time 1.14 seconds
Started Jun 10 05:45:34 PM PDT 24
Finished Jun 10 05:45:36 PM PDT 24
Peak memory 218216 kb
Host smart-81ed11aa-b0cd-4d41-b648-175c4777f3de
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277663285 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 13.lc_ctrl_csr_mem_rw_with_rand_reset.1277663285
Directory /workspace/13.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.339640046
Short name T199
Test name
Test status
Simulation time 22824034 ps
CPU time 0.83 seconds
Started Jun 10 05:45:29 PM PDT 24
Finished Jun 10 05:45:30 PM PDT 24
Peak memory 209872 kb
Host smart-96fc909c-3373-47b4-9ad1-402f6d53fcb7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339640046 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_csr_rw.339640046
Directory /workspace/13.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.180772749
Short name T933
Test name
Test status
Simulation time 86250916 ps
CPU time 1.28 seconds
Started Jun 10 05:45:34 PM PDT 24
Finished Jun 10 05:45:36 PM PDT 24
Peak memory 209608 kb
Host smart-392fc2b5-0ac0-46f5-8217-c5e33187d9d6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180772749 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl
_same_csr_outstanding.180772749
Directory /workspace/13.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.3882841344
Short name T946
Test name
Test status
Simulation time 146304768 ps
CPU time 5.25 seconds
Started Jun 10 05:45:33 PM PDT 24
Finished Jun 10 05:45:39 PM PDT 24
Peak memory 218120 kb
Host smart-eb08b473-e0c5-48f7-b52c-495e3bf850a6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882841344 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_errors.3882841344
Directory /workspace/13.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.2839752843
Short name T118
Test name
Test status
Simulation time 25255520 ps
CPU time 1.14 seconds
Started Jun 10 05:45:34 PM PDT 24
Finished Jun 10 05:45:36 PM PDT 24
Peak memory 219280 kb
Host smart-1e7ed55a-84b8-4694-8bef-1c2d9d768f1d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839752843 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 14.lc_ctrl_csr_mem_rw_with_rand_reset.2839752843
Directory /workspace/14.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.3921411318
Short name T909
Test name
Test status
Simulation time 37457537 ps
CPU time 0.99 seconds
Started Jun 10 05:45:38 PM PDT 24
Finished Jun 10 05:45:39 PM PDT 24
Peak memory 209896 kb
Host smart-71f400ec-c91e-404b-9da1-95da9d0e8147
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921411318 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_csr_rw.3921411318
Directory /workspace/14.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.3202881565
Short name T896
Test name
Test status
Simulation time 50925284 ps
CPU time 1.1 seconds
Started Jun 10 05:45:32 PM PDT 24
Finished Jun 10 05:45:34 PM PDT 24
Peak memory 209976 kb
Host smart-c14dd139-1612-45a8-b9a0-339a2c88f7ce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202881565 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctr
l_same_csr_outstanding.3202881565
Directory /workspace/14.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.1502408068
Short name T944
Test name
Test status
Simulation time 29346253 ps
CPU time 1.74 seconds
Started Jun 10 05:45:31 PM PDT 24
Finished Jun 10 05:45:33 PM PDT 24
Peak memory 219156 kb
Host smart-56054554-658c-4f85-9d86-729deaf17bf0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502408068 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_errors.1502408068
Directory /workspace/14.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.3388793135
Short name T989
Test name
Test status
Simulation time 168616661 ps
CPU time 2.4 seconds
Started Jun 10 05:45:31 PM PDT 24
Finished Jun 10 05:45:34 PM PDT 24
Peak memory 218152 kb
Host smart-2a827a29-35c6-415c-a74b-3edfeb553038
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388793135 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_intg
_err.3388793135
Directory /workspace/14.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.2758362209
Short name T198
Test name
Test status
Simulation time 29418857 ps
CPU time 0.87 seconds
Started Jun 10 05:45:34 PM PDT 24
Finished Jun 10 05:45:35 PM PDT 24
Peak memory 217972 kb
Host smart-ea8242ce-167b-4b97-a869-99fb956cf681
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758362209 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_csr_rw.2758362209
Directory /workspace/15.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.2644671230
Short name T892
Test name
Test status
Simulation time 51130384 ps
CPU time 1.22 seconds
Started Jun 10 05:45:34 PM PDT 24
Finished Jun 10 05:45:35 PM PDT 24
Peak memory 209624 kb
Host smart-aba1d382-5008-43f8-835d-fb23e8869a82
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644671230 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctr
l_same_csr_outstanding.2644671230
Directory /workspace/15.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.1641492194
Short name T947
Test name
Test status
Simulation time 230337156 ps
CPU time 1.95 seconds
Started Jun 10 05:45:33 PM PDT 24
Finished Jun 10 05:45:36 PM PDT 24
Peak memory 218576 kb
Host smart-97436fad-7bcc-458c-b468-e1ccc95b5f02
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641492194 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_errors.1641492194
Directory /workspace/15.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.2282120507
Short name T993
Test name
Test status
Simulation time 135352810 ps
CPU time 1.81 seconds
Started Jun 10 05:45:34 PM PDT 24
Finished Jun 10 05:45:36 PM PDT 24
Peak memory 223780 kb
Host smart-cf89ae40-0d4c-4437-8b51-f48b8c9cfb07
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282120507 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 16.lc_ctrl_csr_mem_rw_with_rand_reset.2282120507
Directory /workspace/16.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.37754440
Short name T938
Test name
Test status
Simulation time 47790598 ps
CPU time 1 seconds
Started Jun 10 05:45:41 PM PDT 24
Finished Jun 10 05:45:42 PM PDT 24
Peak memory 209896 kb
Host smart-bbf098bd-a95e-453b-98b7-e1fdf8a657f4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37754440 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_csr_rw.37754440
Directory /workspace/16.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.3641891153
Short name T922
Test name
Test status
Simulation time 151092290 ps
CPU time 1.45 seconds
Started Jun 10 05:45:37 PM PDT 24
Finished Jun 10 05:45:39 PM PDT 24
Peak memory 209972 kb
Host smart-cb08db8e-436a-4441-88ee-05a8de43045e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641891153 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctr
l_same_csr_outstanding.3641891153
Directory /workspace/16.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.2513972726
Short name T952
Test name
Test status
Simulation time 71921457 ps
CPU time 3.02 seconds
Started Jun 10 05:45:35 PM PDT 24
Finished Jun 10 05:45:39 PM PDT 24
Peak memory 218124 kb
Host smart-f1824312-daa0-4a98-8720-28e05ed3ab27
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513972726 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_errors.2513972726
Directory /workspace/16.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.3952743318
Short name T897
Test name
Test status
Simulation time 14790308 ps
CPU time 0.98 seconds
Started Jun 10 05:45:35 PM PDT 24
Finished Jun 10 05:45:36 PM PDT 24
Peak memory 218296 kb
Host smart-572e41f0-b816-414e-b170-8a4011d399df
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952743318 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 17.lc_ctrl_csr_mem_rw_with_rand_reset.3952743318
Directory /workspace/17.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.1915611588
Short name T903
Test name
Test status
Simulation time 45143042 ps
CPU time 0.89 seconds
Started Jun 10 05:45:40 PM PDT 24
Finished Jun 10 05:45:42 PM PDT 24
Peak memory 209644 kb
Host smart-9dae46bd-2fb7-44d7-969b-713186ccff30
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915611588 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_csr_rw.1915611588
Directory /workspace/17.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.148003562
Short name T957
Test name
Test status
Simulation time 223898746 ps
CPU time 4.29 seconds
Started Jun 10 05:45:36 PM PDT 24
Finished Jun 10 05:45:41 PM PDT 24
Peak memory 218232 kb
Host smart-6c903068-b495-442a-94cb-e70a8e10f431
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148003562 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_errors.148003562
Directory /workspace/17.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.1458753277
Short name T965
Test name
Test status
Simulation time 51852271 ps
CPU time 2.2 seconds
Started Jun 10 05:45:38 PM PDT 24
Finished Jun 10 05:45:41 PM PDT 24
Peak memory 218232 kb
Host smart-b719fcce-4b73-4931-94a1-6d0cdd07f26b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458753277 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 18.lc_ctrl_csr_mem_rw_with_rand_reset.1458753277
Directory /workspace/18.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.3160316637
Short name T193
Test name
Test status
Simulation time 26727587 ps
CPU time 0.87 seconds
Started Jun 10 05:45:37 PM PDT 24
Finished Jun 10 05:45:38 PM PDT 24
Peak memory 209160 kb
Host smart-83912f15-f755-4691-a57f-bc57afb7d708
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160316637 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_csr_rw.3160316637
Directory /workspace/18.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.2063432829
Short name T930
Test name
Test status
Simulation time 25513066 ps
CPU time 1.15 seconds
Started Jun 10 05:45:39 PM PDT 24
Finished Jun 10 05:45:40 PM PDT 24
Peak memory 218148 kb
Host smart-15ea7429-7b23-441a-a16b-b878bc23684a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063432829 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctr
l_same_csr_outstanding.2063432829
Directory /workspace/18.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.381032073
Short name T140
Test name
Test status
Simulation time 374278989 ps
CPU time 1.84 seconds
Started Jun 10 05:45:36 PM PDT 24
Finished Jun 10 05:45:38 PM PDT 24
Peak memory 222552 kb
Host smart-f0994583-093f-4087-a761-13b647027332
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381032073 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_intg_
err.381032073
Directory /workspace/18.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.1430658321
Short name T888
Test name
Test status
Simulation time 242403347 ps
CPU time 1.19 seconds
Started Jun 10 05:45:47 PM PDT 24
Finished Jun 10 05:45:48 PM PDT 24
Peak memory 218272 kb
Host smart-d7aa7a05-dacd-4965-b5ce-d72ef46c26dc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430658321 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 19.lc_ctrl_csr_mem_rw_with_rand_reset.1430658321
Directory /workspace/19.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.3790950122
Short name T913
Test name
Test status
Simulation time 18527241 ps
CPU time 0.82 seconds
Started Jun 10 05:45:42 PM PDT 24
Finished Jun 10 05:45:43 PM PDT 24
Peak memory 209712 kb
Host smart-04a8c4f1-eaba-4bc5-a64c-31f6ba27bbc3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790950122 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_csr_rw.3790950122
Directory /workspace/19.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.2163911859
Short name T205
Test name
Test status
Simulation time 47988777 ps
CPU time 1.35 seconds
Started Jun 10 05:45:41 PM PDT 24
Finished Jun 10 05:45:42 PM PDT 24
Peak memory 209956 kb
Host smart-abd6533c-1499-43fa-bf0c-639c2d938c37
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163911859 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctr
l_same_csr_outstanding.2163911859
Directory /workspace/19.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.343821880
Short name T123
Test name
Test status
Simulation time 81042261 ps
CPU time 2.53 seconds
Started Jun 10 05:45:42 PM PDT 24
Finished Jun 10 05:45:45 PM PDT 24
Peak memory 218168 kb
Host smart-7869dff1-e041-4aa5-9bea-7ce6abf2e6f9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343821880 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_errors.343821880
Directory /workspace/19.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.3552854548
Short name T135
Test name
Test status
Simulation time 44093180 ps
CPU time 2.16 seconds
Started Jun 10 05:45:42 PM PDT 24
Finished Jun 10 05:45:45 PM PDT 24
Peak memory 222404 kb
Host smart-ec35333f-c05a-4200-b94c-f8baf69b50b7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552854548 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_intg
_err.3552854548
Directory /workspace/19.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.1265048343
Short name T931
Test name
Test status
Simulation time 39477851 ps
CPU time 1.21 seconds
Started Jun 10 05:44:47 PM PDT 24
Finished Jun 10 05:44:49 PM PDT 24
Peak memory 209892 kb
Host smart-aa01566f-0b37-4a43-a486-cf92139a2a00
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265048343 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_aliasin
g.1265048343
Directory /workspace/2.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.4198734653
Short name T941
Test name
Test status
Simulation time 79051156 ps
CPU time 1.31 seconds
Started Jun 10 05:44:49 PM PDT 24
Finished Jun 10 05:44:51 PM PDT 24
Peak memory 217264 kb
Host smart-be7a8608-971a-4b46-9713-bce48747319d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198734653 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_bit_bas
h.4198734653
Directory /workspace/2.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.3589748418
Short name T875
Test name
Test status
Simulation time 43899353 ps
CPU time 1.03 seconds
Started Jun 10 05:44:49 PM PDT 24
Finished Jun 10 05:44:51 PM PDT 24
Peak memory 210336 kb
Host smart-694637e7-41fa-460c-b7dc-8c8731f3856c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589748418 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_hw_rese
t.3589748418
Directory /workspace/2.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.2019503417
Short name T968
Test name
Test status
Simulation time 67035335 ps
CPU time 1.23 seconds
Started Jun 10 05:44:54 PM PDT 24
Finished Jun 10 05:44:56 PM PDT 24
Peak memory 218392 kb
Host smart-a6aa7dff-967b-4069-8770-e09aa9e9b815
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019503417 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 2.lc_ctrl_csr_mem_rw_with_rand_reset.2019503417
Directory /workspace/2.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.489631882
Short name T934
Test name
Test status
Simulation time 183679474 ps
CPU time 1.14 seconds
Started Jun 10 05:44:44 PM PDT 24
Finished Jun 10 05:44:46 PM PDT 24
Peak memory 209268 kb
Host smart-55ecd4bd-ae63-401e-9970-776262f719c6
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489631882 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 2.lc_ctrl_jtag_alert_test.489631882
Directory /workspace/2.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.1065695066
Short name T891
Test name
Test status
Simulation time 441492389 ps
CPU time 10.18 seconds
Started Jun 10 05:44:46 PM PDT 24
Finished Jun 10 05:44:57 PM PDT 24
Peak memory 209576 kb
Host smart-aaa3cd92-87ef-4b85-92c2-63390b14cdad
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065695066 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_aliasing.1065695066
Directory /workspace/2.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.3418219868
Short name T985
Test name
Test status
Simulation time 4265325302 ps
CPU time 23.62 seconds
Started Jun 10 05:44:45 PM PDT 24
Finished Jun 10 05:45:09 PM PDT 24
Peak memory 209872 kb
Host smart-3c512031-1e33-458f-907c-d428b5a41d21
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418219868 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_bit_bash.3418219868
Directory /workspace/2.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.4198504904
Short name T928
Test name
Test status
Simulation time 81527819 ps
CPU time 1.32 seconds
Started Jun 10 05:44:43 PM PDT 24
Finished Jun 10 05:44:44 PM PDT 24
Peak memory 211192 kb
Host smart-ccfe5511-1820-45b8-828b-b84d58e847c8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198504904 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_hw_reset.4198504904
Directory /workspace/2.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.754386294
Short name T124
Test name
Test status
Simulation time 118799572 ps
CPU time 2.81 seconds
Started Jun 10 05:44:45 PM PDT 24
Finished Jun 10 05:44:49 PM PDT 24
Peak memory 218264 kb
Host smart-b094a58b-f978-42a4-bfa2-13e93f746851
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754386
294 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.754386294
Directory /workspace/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.3152580159
Short name T921
Test name
Test status
Simulation time 45897109 ps
CPU time 1.88 seconds
Started Jun 10 05:44:46 PM PDT 24
Finished Jun 10 05:44:48 PM PDT 24
Peak memory 209740 kb
Host smart-04beedc6-423f-40c2-bdfb-6a02f00d8ad6
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152580159 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.lc_ctrl_jtag_csr_rw.3152580159
Directory /workspace/2.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.119173960
Short name T950
Test name
Test status
Simulation time 51325739 ps
CPU time 1.51 seconds
Started Jun 10 05:44:47 PM PDT 24
Finished Jun 10 05:44:49 PM PDT 24
Peak memory 218068 kb
Host smart-1963207c-d320-44da-abca-5ee8b16791dc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119173960 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.lc_ctrl_jtag_same_csr_outstanding.119173960
Directory /workspace/2.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.2198075758
Short name T203
Test name
Test status
Simulation time 175809920 ps
CPU time 1.79 seconds
Started Jun 10 05:44:54 PM PDT 24
Finished Jun 10 05:44:56 PM PDT 24
Peak memory 218140 kb
Host smart-733a89d2-1bef-47af-b837-106ec06e9d46
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198075758 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl
_same_csr_outstanding.2198075758
Directory /workspace/2.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.697331437
Short name T983
Test name
Test status
Simulation time 122251300 ps
CPU time 3.52 seconds
Started Jun 10 05:44:49 PM PDT 24
Finished Jun 10 05:44:53 PM PDT 24
Peak memory 218816 kb
Host smart-d86aa545-96a4-4c06-af5b-a349c3e48614
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697331437 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_errors.697331437
Directory /workspace/2.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.526661756
Short name T914
Test name
Test status
Simulation time 35955913 ps
CPU time 1.33 seconds
Started Jun 10 05:44:56 PM PDT 24
Finished Jun 10 05:44:58 PM PDT 24
Peak memory 209476 kb
Host smart-4a6dfd46-e147-46c5-a81e-7c9dab1a7bdf
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526661756 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_aliasing
.526661756
Directory /workspace/3.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.2273671459
Short name T992
Test name
Test status
Simulation time 39601486 ps
CPU time 1.25 seconds
Started Jun 10 05:44:54 PM PDT 24
Finished Jun 10 05:44:56 PM PDT 24
Peak memory 209704 kb
Host smart-56d42b30-b84a-4b08-9279-1d0796855806
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273671459 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_bit_bas
h.2273671459
Directory /workspace/3.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.3024593586
Short name T873
Test name
Test status
Simulation time 23292493 ps
CPU time 1.08 seconds
Started Jun 10 05:44:50 PM PDT 24
Finished Jun 10 05:44:51 PM PDT 24
Peak memory 210224 kb
Host smart-a3437c57-0f4a-475a-8498-c0a356816c8e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024593586 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_hw_rese
t.3024593586
Directory /workspace/3.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.3189844997
Short name T134
Test name
Test status
Simulation time 25850917 ps
CPU time 1.49 seconds
Started Jun 10 05:44:57 PM PDT 24
Finished Jun 10 05:44:59 PM PDT 24
Peak memory 218244 kb
Host smart-727630d4-0de2-4177-8c29-eb1ebdcce4af
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189844997 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 3.lc_ctrl_csr_mem_rw_with_rand_reset.3189844997
Directory /workspace/3.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.2894255830
Short name T125
Test name
Test status
Simulation time 106623892 ps
CPU time 0.89 seconds
Started Jun 10 05:44:56 PM PDT 24
Finished Jun 10 05:44:57 PM PDT 24
Peak memory 209904 kb
Host smart-95a998ff-54d9-4ab5-ac95-eaedb2922c69
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894255830 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_rw.2894255830
Directory /workspace/3.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.657417766
Short name T908
Test name
Test status
Simulation time 105884041 ps
CPU time 1.26 seconds
Started Jun 10 05:44:52 PM PDT 24
Finished Jun 10 05:44:53 PM PDT 24
Peak memory 209760 kb
Host smart-cf889cc6-b446-4eb5-a5d7-1c226d6ab580
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657417766 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 3.lc_ctrl_jtag_alert_test.657417766
Directory /workspace/3.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.1852195352
Short name T148
Test name
Test status
Simulation time 3698616809 ps
CPU time 14.32 seconds
Started Jun 10 05:44:56 PM PDT 24
Finished Jun 10 05:45:11 PM PDT 24
Peak memory 209860 kb
Host smart-e552bd7d-7aea-4e39-bf88-b4addc3c972d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852195352 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_aliasing.1852195352
Directory /workspace/3.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.3370912072
Short name T945
Test name
Test status
Simulation time 2210970168 ps
CPU time 15.53 seconds
Started Jun 10 05:44:54 PM PDT 24
Finished Jun 10 05:45:10 PM PDT 24
Peak memory 209828 kb
Host smart-2ed468e4-6a25-40e1-9f4f-df59892feba0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370912072 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_bit_bash.3370912072
Directory /workspace/3.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.3818600708
Short name T146
Test name
Test status
Simulation time 445185480 ps
CPU time 4.53 seconds
Started Jun 10 05:44:53 PM PDT 24
Finished Jun 10 05:44:59 PM PDT 24
Peak memory 211496 kb
Host smart-ca96a4f4-c389-4aee-bd6f-dc45baeed3d9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818600708 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_hw_reset.3818600708
Directory /workspace/3.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3095604247
Short name T972
Test name
Test status
Simulation time 64081348 ps
CPU time 1.89 seconds
Started Jun 10 05:44:57 PM PDT 24
Finished Jun 10 05:44:59 PM PDT 24
Peak memory 222468 kb
Host smart-98b3c041-0594-4912-916b-633c0790b0d1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309560
4247 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3095604247
Directory /workspace/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.2673026913
Short name T986
Test name
Test status
Simulation time 57187220 ps
CPU time 1.23 seconds
Started Jun 10 05:44:54 PM PDT 24
Finished Jun 10 05:44:55 PM PDT 24
Peak memory 209804 kb
Host smart-ea8f56e9-7d58-496f-b3c7-a952dc2d831a
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673026913 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.lc_ctrl_jtag_csr_rw.2673026913
Directory /workspace/3.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.1877085599
Short name T942
Test name
Test status
Simulation time 78753751 ps
CPU time 1.46 seconds
Started Jun 10 05:44:56 PM PDT 24
Finished Jun 10 05:44:58 PM PDT 24
Peak memory 212084 kb
Host smart-8471b4c4-41c8-4b31-b156-bceb5f4c4217
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877085599 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.lc_ctrl_jtag_same_csr_outstanding.1877085599
Directory /workspace/3.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.2221728648
Short name T902
Test name
Test status
Simulation time 261816933 ps
CPU time 1.44 seconds
Started Jun 10 05:44:59 PM PDT 24
Finished Jun 10 05:45:01 PM PDT 24
Peak memory 209936 kb
Host smart-4a8b20b1-05f9-49c2-9a45-87c3f704207a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221728648 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl
_same_csr_outstanding.2221728648
Directory /workspace/3.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.576918789
Short name T920
Test name
Test status
Simulation time 57636443 ps
CPU time 1.68 seconds
Started Jun 10 05:44:54 PM PDT 24
Finished Jun 10 05:44:56 PM PDT 24
Peak memory 218160 kb
Host smart-55c2eb31-a086-46ad-96b8-76287176facf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576918789 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_errors.576918789
Directory /workspace/3.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.1454623315
Short name T194
Test name
Test status
Simulation time 98434016 ps
CPU time 1.26 seconds
Started Jun 10 05:45:09 PM PDT 24
Finished Jun 10 05:45:11 PM PDT 24
Peak memory 209776 kb
Host smart-e2ae1220-9eee-4d67-a0db-e52b25fb0764
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454623315 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_aliasin
g.1454623315
Directory /workspace/4.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.3536632279
Short name T980
Test name
Test status
Simulation time 384300959 ps
CPU time 3.13 seconds
Started Jun 10 05:45:07 PM PDT 24
Finished Jun 10 05:45:10 PM PDT 24
Peak memory 209888 kb
Host smart-b2e8336f-74f6-4803-b7f0-19e7b8f315b5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536632279 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_bit_bas
h.3536632279
Directory /workspace/4.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.2118001189
Short name T195
Test name
Test status
Simulation time 168721358 ps
CPU time 1.04 seconds
Started Jun 10 05:45:01 PM PDT 24
Finished Jun 10 05:45:02 PM PDT 24
Peak memory 210448 kb
Host smart-ae8271d4-1c66-486d-9cf7-83c3557783c6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118001189 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_hw_rese
t.2118001189
Directory /workspace/4.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.3041125758
Short name T161
Test name
Test status
Simulation time 65567503 ps
CPU time 1.12 seconds
Started Jun 10 05:45:06 PM PDT 24
Finished Jun 10 05:45:07 PM PDT 24
Peak memory 219292 kb
Host smart-28fd9e7a-b932-4135-803f-d5c253a38b9a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041125758 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 4.lc_ctrl_csr_mem_rw_with_rand_reset.3041125758
Directory /workspace/4.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.3011575567
Short name T881
Test name
Test status
Simulation time 14362344 ps
CPU time 1.1 seconds
Started Jun 10 05:45:01 PM PDT 24
Finished Jun 10 05:45:02 PM PDT 24
Peak memory 209564 kb
Host smart-7e1ec29b-e00c-4da8-bb3f-5a21642ceb77
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011575567 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_rw.3011575567
Directory /workspace/4.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.3340511664
Short name T900
Test name
Test status
Simulation time 93362676 ps
CPU time 1.38 seconds
Started Jun 10 05:45:04 PM PDT 24
Finished Jun 10 05:45:05 PM PDT 24
Peak memory 209744 kb
Host smart-0c2b5e92-5b2f-414b-b681-898c5f27ed7d
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340511664 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.lc_ctrl_jtag_alert_test.3340511664
Directory /workspace/4.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.4047451878
Short name T905
Test name
Test status
Simulation time 5866389915 ps
CPU time 6.81 seconds
Started Jun 10 05:44:56 PM PDT 24
Finished Jun 10 05:45:03 PM PDT 24
Peak memory 217940 kb
Host smart-2b1832d5-bac4-4417-ba50-081ee70a4071
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047451878 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_aliasing.4047451878
Directory /workspace/4.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.3003679453
Short name T967
Test name
Test status
Simulation time 2849693095 ps
CPU time 5.32 seconds
Started Jun 10 05:45:01 PM PDT 24
Finished Jun 10 05:45:07 PM PDT 24
Peak memory 209752 kb
Host smart-ecc41d98-4d4e-45cd-bd20-86e6c8789a98
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003679453 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_bit_bash.3003679453
Directory /workspace/4.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.731078447
Short name T995
Test name
Test status
Simulation time 86407300 ps
CPU time 1.53 seconds
Started Jun 10 05:45:00 PM PDT 24
Finished Jun 10 05:45:02 PM PDT 24
Peak memory 211180 kb
Host smart-0ec033f7-36aa-401a-995b-bc46e8943463
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731078447 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 4.lc_ctrl_jtag_csr_hw_reset.731078447
Directory /workspace/4.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1154838971
Short name T925
Test name
Test status
Simulation time 664148039 ps
CPU time 2.6 seconds
Started Jun 10 05:44:59 PM PDT 24
Finished Jun 10 05:45:02 PM PDT 24
Peak memory 219548 kb
Host smart-bea68408-d9f1-4c2a-88ec-a2ed7dbbcd04
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115483
8971 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1154838971
Directory /workspace/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.1760128329
Short name T936
Test name
Test status
Simulation time 79521578 ps
CPU time 1.45 seconds
Started Jun 10 05:45:01 PM PDT 24
Finished Jun 10 05:45:03 PM PDT 24
Peak memory 209836 kb
Host smart-bcd52d38-59b7-4c66-8e78-5f11f9aef70a
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760128329 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.lc_ctrl_jtag_csr_rw.1760128329
Directory /workspace/4.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.4235761455
Short name T120
Test name
Test status
Simulation time 99548922 ps
CPU time 2.19 seconds
Started Jun 10 05:44:59 PM PDT 24
Finished Jun 10 05:45:01 PM PDT 24
Peak memory 211948 kb
Host smart-83cf7828-dc5b-40b0-9f8f-0351efa676a0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235761455 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.lc_ctrl_jtag_same_csr_outstanding.4235761455
Directory /workspace/4.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.1438067245
Short name T907
Test name
Test status
Simulation time 53651929 ps
CPU time 1.33 seconds
Started Jun 10 05:45:08 PM PDT 24
Finished Jun 10 05:45:09 PM PDT 24
Peak memory 217988 kb
Host smart-a9e10e7f-317f-405d-bbb6-ef596bcab236
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438067245 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl
_same_csr_outstanding.1438067245
Directory /workspace/4.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.1245043479
Short name T128
Test name
Test status
Simulation time 215119011 ps
CPU time 2.1 seconds
Started Jun 10 05:45:03 PM PDT 24
Finished Jun 10 05:45:05 PM PDT 24
Peak memory 218172 kb
Host smart-d7473510-2742-4424-9237-9dfe12667672
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245043479 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_errors.1245043479
Directory /workspace/4.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.461517928
Short name T137
Test name
Test status
Simulation time 138844025 ps
CPU time 2.88 seconds
Started Jun 10 05:45:02 PM PDT 24
Finished Jun 10 05:45:06 PM PDT 24
Peak memory 223024 kb
Host smart-8aee6f6a-9231-484c-8492-3b48d6ef6303
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461517928 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_intg_e
rr.461517928
Directory /workspace/4.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.3501852239
Short name T182
Test name
Test status
Simulation time 132131556 ps
CPU time 1.14 seconds
Started Jun 10 05:45:10 PM PDT 24
Finished Jun 10 05:45:11 PM PDT 24
Peak memory 219760 kb
Host smart-88e0aa0e-72cc-43af-984d-60aa63a371b2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501852239 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 5.lc_ctrl_csr_mem_rw_with_rand_reset.3501852239
Directory /workspace/5.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.218772747
Short name T935
Test name
Test status
Simulation time 16858596 ps
CPU time 0.97 seconds
Started Jun 10 05:45:11 PM PDT 24
Finished Jun 10 05:45:13 PM PDT 24
Peak memory 209800 kb
Host smart-8bc8eea9-5500-4628-bd87-ff016f5304d5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218772747 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_csr_rw.218772747
Directory /workspace/5.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.4266947199
Short name T877
Test name
Test status
Simulation time 71325712 ps
CPU time 1.41 seconds
Started Jun 10 05:45:15 PM PDT 24
Finished Jun 10 05:45:17 PM PDT 24
Peak memory 209288 kb
Host smart-4daf377f-045b-4ae6-9d0c-1ddb90550b07
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266947199 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.lc_ctrl_jtag_alert_test.4266947199
Directory /workspace/5.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.1307282879
Short name T955
Test name
Test status
Simulation time 189658870 ps
CPU time 5.34 seconds
Started Jun 10 05:45:08 PM PDT 24
Finished Jun 10 05:45:13 PM PDT 24
Peak memory 209800 kb
Host smart-1f201df7-4688-41b9-95f0-77b9646ddaf6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307282879 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_aliasing.1307282879
Directory /workspace/5.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.1854292809
Short name T876
Test name
Test status
Simulation time 772168860 ps
CPU time 10.11 seconds
Started Jun 10 05:45:06 PM PDT 24
Finished Jun 10 05:45:17 PM PDT 24
Peak memory 209764 kb
Host smart-fc6b65a2-6299-4637-9021-a1967feb1971
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854292809 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_bit_bash.1854292809
Directory /workspace/5.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.3574165946
Short name T878
Test name
Test status
Simulation time 250212231 ps
CPU time 1.85 seconds
Started Jun 10 05:45:08 PM PDT 24
Finished Jun 10 05:45:10 PM PDT 24
Peak memory 211468 kb
Host smart-0e95ad17-86ae-451f-a7fd-97391b97727b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574165946 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_hw_reset.3574165946
Directory /workspace/5.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2105853778
Short name T910
Test name
Test status
Simulation time 102511726 ps
CPU time 1.96 seconds
Started Jun 10 05:45:10 PM PDT 24
Finished Jun 10 05:45:12 PM PDT 24
Peak memory 219524 kb
Host smart-589856ba-d01d-4a06-9ed0-2779fc3d42de
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210585
3778 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2105853778
Directory /workspace/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.3611462576
Short name T901
Test name
Test status
Simulation time 111281333 ps
CPU time 1.2 seconds
Started Jun 10 05:45:06 PM PDT 24
Finished Jun 10 05:45:08 PM PDT 24
Peak memory 209724 kb
Host smart-c0b93d93-abb8-46c6-a57c-0d020322e318
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611462576 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.lc_ctrl_jtag_csr_rw.3611462576
Directory /workspace/5.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.428097153
Short name T917
Test name
Test status
Simulation time 56731742 ps
CPU time 1.2 seconds
Started Jun 10 05:45:08 PM PDT 24
Finished Jun 10 05:45:10 PM PDT 24
Peak memory 210032 kb
Host smart-93687df8-1c3d-4eb4-96a6-8bae3cedc7fa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428097153 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.lc_ctrl_jtag_same_csr_outstanding.428097153
Directory /workspace/5.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.470423539
Short name T160
Test name
Test status
Simulation time 150418027 ps
CPU time 1.27 seconds
Started Jun 10 05:45:15 PM PDT 24
Finished Jun 10 05:45:17 PM PDT 24
Peak memory 217916 kb
Host smart-eeb05bcd-d671-4878-b601-de7b5255ac80
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470423539 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
same_csr_outstanding.470423539
Directory /workspace/5.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.451683232
Short name T911
Test name
Test status
Simulation time 451176475 ps
CPU time 3.22 seconds
Started Jun 10 05:45:12 PM PDT 24
Finished Jun 10 05:45:15 PM PDT 24
Peak memory 218032 kb
Host smart-7e1a59a9-3e0d-4f2b-af0b-23d17d32717e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451683232 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_errors.451683232
Directory /workspace/5.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.265381017
Short name T143
Test name
Test status
Simulation time 65399575 ps
CPU time 2.46 seconds
Started Jun 10 05:45:17 PM PDT 24
Finished Jun 10 05:45:19 PM PDT 24
Peak memory 218148 kb
Host smart-5d25c67e-7dd1-4c96-8b15-7019036bc446
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265381017 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_intg_e
rr.265381017
Directory /workspace/5.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.180774654
Short name T958
Test name
Test status
Simulation time 75211155 ps
CPU time 1.46 seconds
Started Jun 10 05:45:14 PM PDT 24
Finished Jun 10 05:45:16 PM PDT 24
Peak memory 218228 kb
Host smart-98be53a5-ff3b-409a-8c8f-e8e7c2f4db37
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180774654 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 6.lc_ctrl_csr_mem_rw_with_rand_reset.180774654
Directory /workspace/6.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.314354543
Short name T201
Test name
Test status
Simulation time 33958441 ps
CPU time 0.93 seconds
Started Jun 10 05:45:12 PM PDT 24
Finished Jun 10 05:45:13 PM PDT 24
Peak memory 209880 kb
Host smart-9298e6e6-57ac-4d13-ae9d-e6819d2318bb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314354543 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_csr_rw.314354543
Directory /workspace/6.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.2342627887
Short name T874
Test name
Test status
Simulation time 29225116 ps
CPU time 0.96 seconds
Started Jun 10 05:45:11 PM PDT 24
Finished Jun 10 05:45:12 PM PDT 24
Peak memory 209164 kb
Host smart-faef5bd7-2639-4719-af6f-a75b1b09f4c7
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342627887 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.lc_ctrl_jtag_alert_test.2342627887
Directory /workspace/6.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.2671996107
Short name T960
Test name
Test status
Simulation time 1098669711 ps
CPU time 6.62 seconds
Started Jun 10 05:45:15 PM PDT 24
Finished Jun 10 05:45:22 PM PDT 24
Peak memory 209472 kb
Host smart-1c747581-2726-4a9e-a88c-9075d71d7dcc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671996107 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_aliasing.2671996107
Directory /workspace/6.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.1859886285
Short name T880
Test name
Test status
Simulation time 3460968487 ps
CPU time 10.13 seconds
Started Jun 10 05:45:09 PM PDT 24
Finished Jun 10 05:45:20 PM PDT 24
Peak memory 209900 kb
Host smart-073f1ee3-9b79-4097-87ba-7b5e392274fb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859886285 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_bit_bash.1859886285
Directory /workspace/6.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.2636477116
Short name T898
Test name
Test status
Simulation time 121017910 ps
CPU time 1.27 seconds
Started Jun 10 05:45:13 PM PDT 24
Finished Jun 10 05:45:14 PM PDT 24
Peak memory 218040 kb
Host smart-90a6f8b1-248c-4420-afc3-472c13e12397
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636477116 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_hw_reset.2636477116
Directory /workspace/6.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3026792198
Short name T998
Test name
Test status
Simulation time 82590529 ps
CPU time 1.8 seconds
Started Jun 10 05:45:08 PM PDT 24
Finished Jun 10 05:45:10 PM PDT 24
Peak memory 218304 kb
Host smart-65d5b783-4805-4ba6-8212-907279f73fbd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302679
2198 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3026792198
Directory /workspace/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.1355079318
Short name T932
Test name
Test status
Simulation time 1258829487 ps
CPU time 2.49 seconds
Started Jun 10 05:45:14 PM PDT 24
Finished Jun 10 05:45:17 PM PDT 24
Peak memory 217852 kb
Host smart-4bb9ff25-6e36-4b80-95d6-ba0fb7a23edc
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355079318 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.lc_ctrl_jtag_csr_rw.1355079318
Directory /workspace/6.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.956486639
Short name T969
Test name
Test status
Simulation time 37844389 ps
CPU time 1.97 seconds
Started Jun 10 05:45:12 PM PDT 24
Finished Jun 10 05:45:15 PM PDT 24
Peak memory 211860 kb
Host smart-c4baadeb-e80d-4c6a-a7db-f1243cdb9dde
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956486639 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.lc_ctrl_jtag_same_csr_outstanding.956486639
Directory /workspace/6.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.3182577608
Short name T990
Test name
Test status
Simulation time 76610780 ps
CPU time 1.21 seconds
Started Jun 10 05:45:15 PM PDT 24
Finished Jun 10 05:45:17 PM PDT 24
Peak memory 209952 kb
Host smart-a7934aa7-581e-4663-accf-3f868c90b0bc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182577608 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl
_same_csr_outstanding.3182577608
Directory /workspace/6.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.2957421406
Short name T115
Test name
Test status
Simulation time 336175785 ps
CPU time 3.41 seconds
Started Jun 10 05:45:17 PM PDT 24
Finished Jun 10 05:45:21 PM PDT 24
Peak memory 218140 kb
Host smart-6ce3d9b7-fe8b-461a-a9f0-6ebebfb1ee5e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957421406 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_errors.2957421406
Directory /workspace/6.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.3069321596
Short name T978
Test name
Test status
Simulation time 41930761 ps
CPU time 2.15 seconds
Started Jun 10 05:45:12 PM PDT 24
Finished Jun 10 05:45:15 PM PDT 24
Peak memory 218128 kb
Host smart-30d7f862-41bd-4836-a483-a319c5191e2a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069321596 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_intg_
err.3069321596
Directory /workspace/6.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.3716062978
Short name T940
Test name
Test status
Simulation time 90381610 ps
CPU time 1.53 seconds
Started Jun 10 05:45:18 PM PDT 24
Finished Jun 10 05:45:20 PM PDT 24
Peak memory 218244 kb
Host smart-f90c68d2-21ea-4742-a73c-ffe32077c379
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716062978 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 7.lc_ctrl_csr_mem_rw_with_rand_reset.3716062978
Directory /workspace/7.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.2721995334
Short name T192
Test name
Test status
Simulation time 13879234 ps
CPU time 0.84 seconds
Started Jun 10 05:45:11 PM PDT 24
Finished Jun 10 05:45:12 PM PDT 24
Peak memory 209744 kb
Host smart-e574cc38-27da-48ee-b96f-54c79fcafa67
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721995334 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_csr_rw.2721995334
Directory /workspace/7.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.692714006
Short name T149
Test name
Test status
Simulation time 41117809 ps
CPU time 1.28 seconds
Started Jun 10 05:45:16 PM PDT 24
Finished Jun 10 05:45:17 PM PDT 24
Peak memory 209696 kb
Host smart-6702eaaf-14d5-4fb5-8673-a5d881fd7179
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692714006 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 7.lc_ctrl_jtag_alert_test.692714006
Directory /workspace/7.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.3330912006
Short name T883
Test name
Test status
Simulation time 223382131 ps
CPU time 2.84 seconds
Started Jun 10 05:45:15 PM PDT 24
Finished Jun 10 05:45:18 PM PDT 24
Peak memory 209084 kb
Host smart-38bb744d-ec82-4917-aaf0-8ed5c1b24fa1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330912006 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_aliasing.3330912006
Directory /workspace/7.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.2390433483
Short name T994
Test name
Test status
Simulation time 425159493 ps
CPU time 6.23 seconds
Started Jun 10 05:45:14 PM PDT 24
Finished Jun 10 05:45:21 PM PDT 24
Peak memory 209576 kb
Host smart-29138259-abe8-414e-8838-37655040ee4b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390433483 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_bit_bash.2390433483
Directory /workspace/7.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.1516760063
Short name T959
Test name
Test status
Simulation time 366430715 ps
CPU time 5.68 seconds
Started Jun 10 05:45:16 PM PDT 24
Finished Jun 10 05:45:22 PM PDT 24
Peak memory 211464 kb
Host smart-92211a25-6b42-429e-bd97-726efcf58fd0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516760063 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_hw_reset.1516760063
Directory /workspace/7.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2355423620
Short name T937
Test name
Test status
Simulation time 247180717 ps
CPU time 2.41 seconds
Started Jun 10 05:45:11 PM PDT 24
Finished Jun 10 05:45:14 PM PDT 24
Peak memory 219368 kb
Host smart-10cf4888-63f3-4c00-86ac-8de2424888e1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235542
3620 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2355423620
Directory /workspace/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.2647510095
Short name T951
Test name
Test status
Simulation time 169154080 ps
CPU time 2.02 seconds
Started Jun 10 05:45:38 PM PDT 24
Finished Jun 10 05:45:40 PM PDT 24
Peak memory 209768 kb
Host smart-8003a6a2-c614-4fa4-895f-2b0a9e86948c
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647510095 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.lc_ctrl_jtag_csr_rw.2647510095
Directory /workspace/7.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.2459583897
Short name T119
Test name
Test status
Simulation time 77218784 ps
CPU time 1.23 seconds
Started Jun 10 05:45:16 PM PDT 24
Finished Jun 10 05:45:17 PM PDT 24
Peak memory 209768 kb
Host smart-c9acfff1-616b-442e-b4ad-85e36ce727ed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459583897 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.lc_ctrl_jtag_same_csr_outstanding.2459583897
Directory /workspace/7.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.239998227
Short name T961
Test name
Test status
Simulation time 24368359 ps
CPU time 1.32 seconds
Started Jun 10 05:45:16 PM PDT 24
Finished Jun 10 05:45:17 PM PDT 24
Peak memory 209968 kb
Host smart-54ade421-b930-43ce-b127-39c712c9a6b5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239998227 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
same_csr_outstanding.239998227
Directory /workspace/7.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.383853061
Short name T948
Test name
Test status
Simulation time 100943488 ps
CPU time 2.35 seconds
Started Jun 10 05:45:16 PM PDT 24
Finished Jun 10 05:45:18 PM PDT 24
Peak memory 218248 kb
Host smart-149c6575-1cf5-46e5-ab04-1efbecfcb065
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383853061 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_errors.383853061
Directory /workspace/7.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.4006229544
Short name T142
Test name
Test status
Simulation time 420751002 ps
CPU time 4.09 seconds
Started Jun 10 05:45:15 PM PDT 24
Finished Jun 10 05:45:19 PM PDT 24
Peak memory 217992 kb
Host smart-306e290c-cef2-4bc1-8914-1c2722dc62b7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006229544 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_intg_
err.4006229544
Directory /workspace/7.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.276459060
Short name T996
Test name
Test status
Simulation time 61291233 ps
CPU time 1.43 seconds
Started Jun 10 05:45:24 PM PDT 24
Finished Jun 10 05:45:26 PM PDT 24
Peak memory 218220 kb
Host smart-baac2999-f6dd-4592-997b-29ff37115f26
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276459060 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 8.lc_ctrl_csr_mem_rw_with_rand_reset.276459060
Directory /workspace/8.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.2716072398
Short name T927
Test name
Test status
Simulation time 38667697 ps
CPU time 0.87 seconds
Started Jun 10 05:45:24 PM PDT 24
Finished Jun 10 05:45:25 PM PDT 24
Peak memory 209352 kb
Host smart-b429472c-9e17-4fed-a3ed-e1b611776063
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716072398 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_csr_rw.2716072398
Directory /workspace/8.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.3416269954
Short name T923
Test name
Test status
Simulation time 76933441 ps
CPU time 0.98 seconds
Started Jun 10 05:45:22 PM PDT 24
Finished Jun 10 05:45:23 PM PDT 24
Peak memory 209032 kb
Host smart-8458aa44-59f2-473b-b5e3-b9e7886c474a
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416269954 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.lc_ctrl_jtag_alert_test.3416269954
Directory /workspace/8.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.163300664
Short name T885
Test name
Test status
Simulation time 230122554 ps
CPU time 3.08 seconds
Started Jun 10 05:45:20 PM PDT 24
Finished Jun 10 05:45:23 PM PDT 24
Peak memory 209588 kb
Host smart-ecfba5de-088d-4e99-909c-ae1d1fd852dd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163300664 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 8.lc_ctrl_jtag_csr_aliasing.163300664
Directory /workspace/8.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.359743634
Short name T879
Test name
Test status
Simulation time 7567532356 ps
CPU time 27.5 seconds
Started Jun 10 05:45:19 PM PDT 24
Finished Jun 10 05:45:47 PM PDT 24
Peak memory 217948 kb
Host smart-894399d9-feaa-4dda-a230-9c05f5c46c47
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359743634 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 8.lc_ctrl_jtag_csr_bit_bash.359743634
Directory /workspace/8.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.3307405539
Short name T979
Test name
Test status
Simulation time 244918970 ps
CPU time 1.47 seconds
Started Jun 10 05:45:20 PM PDT 24
Finished Jun 10 05:45:22 PM PDT 24
Peak memory 218040 kb
Host smart-0cd691b8-b087-4815-953a-3b202b584110
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307405539 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_hw_reset.3307405539
Directory /workspace/8.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2742480271
Short name T173
Test name
Test status
Simulation time 399548625 ps
CPU time 3.14 seconds
Started Jun 10 05:45:19 PM PDT 24
Finished Jun 10 05:45:22 PM PDT 24
Peak memory 218296 kb
Host smart-73437106-08b6-4a03-a163-3dff9e4ee114
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274248
0271 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2742480271
Directory /workspace/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.903823789
Short name T890
Test name
Test status
Simulation time 199689787 ps
CPU time 1.64 seconds
Started Jun 10 05:45:20 PM PDT 24
Finished Jun 10 05:45:22 PM PDT 24
Peak memory 209832 kb
Host smart-e09eacd1-a921-44f4-9e46-df0131a041ee
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903823789 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.lc_ctrl_jtag_csr_rw.903823789
Directory /workspace/8.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.1075272502
Short name T973
Test name
Test status
Simulation time 86788837 ps
CPU time 1.42 seconds
Started Jun 10 05:45:20 PM PDT 24
Finished Jun 10 05:45:22 PM PDT 24
Peak memory 218168 kb
Host smart-17124b0f-042e-4eb2-a0b3-9c7d64c3bcfd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075272502 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.lc_ctrl_jtag_same_csr_outstanding.1075272502
Directory /workspace/8.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.2059209711
Short name T971
Test name
Test status
Simulation time 19302934 ps
CPU time 1.2 seconds
Started Jun 10 05:45:25 PM PDT 24
Finished Jun 10 05:45:26 PM PDT 24
Peak memory 209992 kb
Host smart-ab1f478a-6769-4c0a-85a2-061fc7448a01
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059209711 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl
_same_csr_outstanding.2059209711
Directory /workspace/8.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.2092815494
Short name T943
Test name
Test status
Simulation time 151702519 ps
CPU time 3.56 seconds
Started Jun 10 05:45:20 PM PDT 24
Finished Jun 10 05:45:24 PM PDT 24
Peak memory 218120 kb
Host smart-7f694859-990e-456b-85d6-48c8d31bf47c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092815494 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_errors.2092815494
Directory /workspace/8.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.850230881
Short name T138
Test name
Test status
Simulation time 199531785 ps
CPU time 1.99 seconds
Started Jun 10 05:45:20 PM PDT 24
Finished Jun 10 05:45:22 PM PDT 24
Peak memory 222528 kb
Host smart-5a95d2ee-5531-4b5e-8f57-5b1abd607908
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850230881 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_intg_e
rr.850230881
Directory /workspace/8.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.2321255631
Short name T954
Test name
Test status
Simulation time 206006945 ps
CPU time 1.87 seconds
Started Jun 10 05:45:27 PM PDT 24
Finished Jun 10 05:45:29 PM PDT 24
Peak memory 223516 kb
Host smart-5d43f341-81f3-4b9b-95ce-2517b74dcb72
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321255631 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 9.lc_ctrl_csr_mem_rw_with_rand_reset.2321255631
Directory /workspace/9.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.2048276758
Short name T190
Test name
Test status
Simulation time 32144748 ps
CPU time 0.94 seconds
Started Jun 10 05:45:22 PM PDT 24
Finished Jun 10 05:45:23 PM PDT 24
Peak memory 209860 kb
Host smart-ea7e402c-0b12-4699-9ab9-efd17f017d53
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048276758 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_csr_rw.2048276758
Directory /workspace/9.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.1902160202
Short name T939
Test name
Test status
Simulation time 207318730 ps
CPU time 1.19 seconds
Started Jun 10 05:45:20 PM PDT 24
Finished Jun 10 05:45:22 PM PDT 24
Peak memory 209784 kb
Host smart-3eb7d124-a9fb-4646-a89e-6fe3e28fd65d
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902160202 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.lc_ctrl_jtag_alert_test.1902160202
Directory /workspace/9.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.3939848210
Short name T975
Test name
Test status
Simulation time 547858152 ps
CPU time 12.35 seconds
Started Jun 10 05:45:25 PM PDT 24
Finished Jun 10 05:45:38 PM PDT 24
Peak memory 217604 kb
Host smart-6bae5aff-d85b-4170-b1de-14b62fc87c57
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939848210 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_aliasing.3939848210
Directory /workspace/9.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.4094244343
Short name T999
Test name
Test status
Simulation time 2922676236 ps
CPU time 19.15 seconds
Started Jun 10 05:45:27 PM PDT 24
Finished Jun 10 05:45:47 PM PDT 24
Peak memory 209708 kb
Host smart-d43f2bf4-7ff7-4c66-9d18-56d653bd7c51
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094244343 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_bit_bash.4094244343
Directory /workspace/9.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.1712816790
Short name T894
Test name
Test status
Simulation time 129408271 ps
CPU time 3.93 seconds
Started Jun 10 05:45:30 PM PDT 24
Finished Jun 10 05:45:34 PM PDT 24
Peak memory 218028 kb
Host smart-5c0cd573-a167-40a1-b8bc-edf20c208a6c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712816790 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_hw_reset.1712816790
Directory /workspace/9.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1161428605
Short name T970
Test name
Test status
Simulation time 60907054 ps
CPU time 2.16 seconds
Started Jun 10 05:45:25 PM PDT 24
Finished Jun 10 05:45:27 PM PDT 24
Peak memory 218528 kb
Host smart-0c208d33-e537-4f5a-bf44-da65abaff6e8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116142
8605 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1161428605
Directory /workspace/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.1574470054
Short name T145
Test name
Test status
Simulation time 641675309 ps
CPU time 1.56 seconds
Started Jun 10 05:45:24 PM PDT 24
Finished Jun 10 05:45:26 PM PDT 24
Peak memory 217880 kb
Host smart-f7c453bb-01ac-45b1-97d5-c462664299bf
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574470054 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.lc_ctrl_jtag_csr_rw.1574470054
Directory /workspace/9.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.1594478757
Short name T889
Test name
Test status
Simulation time 15435820 ps
CPU time 0.99 seconds
Started Jun 10 05:45:27 PM PDT 24
Finished Jun 10 05:45:28 PM PDT 24
Peak memory 218044 kb
Host smart-e2d67f7b-e4c4-4b60-9bcd-265b46361d82
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594478757 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.lc_ctrl_jtag_same_csr_outstanding.1594478757
Directory /workspace/9.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.2308310792
Short name T202
Test name
Test status
Simulation time 44215510 ps
CPU time 1.35 seconds
Started Jun 10 05:45:25 PM PDT 24
Finished Jun 10 05:45:26 PM PDT 24
Peak memory 217844 kb
Host smart-1c6af755-b9a7-4eba-93ff-e26ed1dfe86b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308310792 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl
_same_csr_outstanding.2308310792
Directory /workspace/9.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.4023161245
Short name T964
Test name
Test status
Simulation time 757724583 ps
CPU time 5.44 seconds
Started Jun 10 05:45:26 PM PDT 24
Finished Jun 10 05:45:32 PM PDT 24
Peak memory 218156 kb
Host smart-b5201504-cacc-4e66-92e9-88982980fbad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023161245 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_errors.4023161245
Directory /workspace/9.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.4268138172
Short name T116
Test name
Test status
Simulation time 109556664 ps
CPU time 4.5 seconds
Started Jun 10 05:45:21 PM PDT 24
Finished Jun 10 05:45:26 PM PDT 24
Peak memory 218260 kb
Host smart-d72c6b2d-c067-4eab-b00e-46e72837b9fb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268138172 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_intg_
err.4268138172
Directory /workspace/9.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_alert_test.3256496971
Short name T785
Test name
Test status
Simulation time 14135776 ps
CPU time 0.87 seconds
Started Jun 10 05:46:36 PM PDT 24
Finished Jun 10 05:46:37 PM PDT 24
Peak memory 209424 kb
Host smart-f9739d86-7c25-43b4-bea6-83dc70f965dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256496971 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_alert_test.3256496971
Directory /workspace/0.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.lc_ctrl_errors.3556721485
Short name T735
Test name
Test status
Simulation time 1165555177 ps
CPU time 10.2 seconds
Started Jun 10 05:46:30 PM PDT 24
Finished Jun 10 05:46:40 PM PDT 24
Peak memory 218760 kb
Host smart-8d62a999-d1c2-45fc-a922-1be687a8c974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556721485 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_errors.3556721485
Directory /workspace/0.lc_ctrl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_access.3773331004
Short name T359
Test name
Test status
Simulation time 75213228 ps
CPU time 1.63 seconds
Started Jun 10 05:46:31 PM PDT 24
Finished Jun 10 05:46:33 PM PDT 24
Peak memory 217588 kb
Host smart-c1bc0b04-ee26-428d-a580-f8f80922f561
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773331004 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_access.3773331004
Directory /workspace/0.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_errors.667032147
Short name T826
Test name
Test status
Simulation time 26581187096 ps
CPU time 50.46 seconds
Started Jun 10 05:46:33 PM PDT 24
Finished Jun 10 05:47:24 PM PDT 24
Peak memory 219452 kb
Host smart-ed7d33e7-fb6c-4c27-9d6e-4a77dd2284b0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667032147 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_err
ors.667032147
Directory /workspace/0.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_priority.2393687463
Short name T358
Test name
Test status
Simulation time 288684844 ps
CPU time 2.55 seconds
Started Jun 10 05:46:33 PM PDT 24
Finished Jun 10 05:46:37 PM PDT 24
Peak memory 217964 kb
Host smart-011ee8f3-d7eb-4cb5-8b37-3c4582075226
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393687463 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_priority.2
393687463
Directory /workspace/0.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_prog_failure.1956359100
Short name T831
Test name
Test status
Simulation time 3151660623 ps
CPU time 7.99 seconds
Started Jun 10 05:46:32 PM PDT 24
Finished Jun 10 05:46:41 PM PDT 24
Peak memory 218756 kb
Host smart-854b5233-9423-4e60-a371-ffe3adeda4c6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956359100 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag
_prog_failure.1956359100
Directory /workspace/0.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_regwen_during_op.3908209692
Short name T597
Test name
Test status
Simulation time 1007539969 ps
CPU time 18.41 seconds
Started Jun 10 05:46:33 PM PDT 24
Finished Jun 10 05:46:52 PM PDT 24
Peak memory 218216 kb
Host smart-6e05ebc6-7f3e-4a4d-85a5-09afbf07b20d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908209692 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_regwen_during_op.3908209692
Directory /workspace/0.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_smoke.3314926768
Short name T813
Test name
Test status
Simulation time 105557280 ps
CPU time 2.51 seconds
Started Jun 10 05:46:30 PM PDT 24
Finished Jun 10 05:46:33 PM PDT 24
Peak memory 218244 kb
Host smart-190c9a4f-e17a-40a5-bc38-e09a1333b267
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314926768 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_smoke.
3314926768
Directory /workspace/0.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_failure.3153719759
Short name T224
Test name
Test status
Simulation time 12424421318 ps
CPU time 48.88 seconds
Started Jun 10 05:46:34 PM PDT 24
Finished Jun 10 05:47:24 PM PDT 24
Peak memory 251524 kb
Host smart-c57205ab-f349-41cd-b471-265c867e4c78
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153719759 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jta
g_state_failure.3153719759
Directory /workspace/0.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_post_trans.3098270867
Short name T739
Test name
Test status
Simulation time 1280906811 ps
CPU time 15.84 seconds
Started Jun 10 05:46:33 PM PDT 24
Finished Jun 10 05:46:50 PM PDT 24
Peak memory 251408 kb
Host smart-311739e6-b16f-4b72-9700-fbe64620ea70
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098270867 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_state_post_trans.3098270867
Directory /workspace/0.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_prog_failure.432172806
Short name T452
Test name
Test status
Simulation time 66872168 ps
CPU time 3.37 seconds
Started Jun 10 05:46:35 PM PDT 24
Finished Jun 10 05:46:39 PM PDT 24
Peak memory 218680 kb
Host smart-94df664b-fa63-4044-8d43-3a9c9042414a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432172806 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_prog_failure.432172806
Directory /workspace/0.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_regwen_during_op.2341041228
Short name T688
Test name
Test status
Simulation time 582112373 ps
CPU time 19.46 seconds
Started Jun 10 05:46:32 PM PDT 24
Finished Jun 10 05:46:52 PM PDT 24
Peak memory 218132 kb
Host smart-09f60bad-7993-4fb8-9fcf-44017174df5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341041228 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_regwen_during_op.2341041228
Directory /workspace/0.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_cm.2132589574
Short name T106
Test name
Test status
Simulation time 114935326 ps
CPU time 24.35 seconds
Started Jun 10 05:46:36 PM PDT 24
Finished Jun 10 05:47:01 PM PDT 24
Peak memory 283196 kb
Host smart-3ea18fe2-1885-4dee-9bbc-94026bb12027
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132589574 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_cm.2132589574
Directory /workspace/0.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_mubi.627350740
Short name T381
Test name
Test status
Simulation time 1019366471 ps
CPU time 7.55 seconds
Started Jun 10 05:46:35 PM PDT 24
Finished Jun 10 05:46:43 PM PDT 24
Peak memory 218736 kb
Host smart-f8bf1bcc-b9ca-4009-98a9-4b0ac6042b59
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627350740 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_mubi.627350740
Directory /workspace/0.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_digest.1539304938
Short name T761
Test name
Test status
Simulation time 2086357209 ps
CPU time 13.57 seconds
Started Jun 10 05:46:33 PM PDT 24
Finished Jun 10 05:46:47 PM PDT 24
Peak memory 218728 kb
Host smart-76acd043-571e-42a5-a691-cd2c3a77c011
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539304938 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_di
gest.1539304938
Directory /workspace/0.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_mux.219442810
Short name T810
Test name
Test status
Simulation time 934128929 ps
CPU time 7.24 seconds
Started Jun 10 05:46:31 PM PDT 24
Finished Jun 10 05:46:39 PM PDT 24
Peak memory 218724 kb
Host smart-b3cf7434-9d14-4827-9849-0216cb59a49c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219442810 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_mux.219442810
Directory /workspace/0.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/0.lc_ctrl_security_escalation.69818244
Short name T582
Test name
Test status
Simulation time 537662314 ps
CPU time 11.41 seconds
Started Jun 10 05:46:30 PM PDT 24
Finished Jun 10 05:46:42 PM PDT 24
Peak memory 226564 kb
Host smart-110fb33f-7ec2-4b9f-9ae2-c66be89c666c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69818244 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_security_escalation.69818244
Directory /workspace/0.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/0.lc_ctrl_smoke.3061133974
Short name T87
Test name
Test status
Simulation time 57289180 ps
CPU time 2.63 seconds
Started Jun 10 05:46:33 PM PDT 24
Finished Jun 10 05:46:36 PM PDT 24
Peak memory 215260 kb
Host smart-2a2cc05c-b03c-46de-839a-b32491714dd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061133974 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_smoke.3061133974
Directory /workspace/0.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_failure.1291113231
Short name T727
Test name
Test status
Simulation time 1956476803 ps
CPU time 31.23 seconds
Started Jun 10 05:46:30 PM PDT 24
Finished Jun 10 05:47:02 PM PDT 24
Peak memory 251504 kb
Host smart-cf90742e-3f23-4951-b725-f85ef0f7041e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291113231 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_failure.1291113231
Directory /workspace/0.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_post_trans.1710316609
Short name T294
Test name
Test status
Simulation time 93898219 ps
CPU time 8.46 seconds
Started Jun 10 05:46:29 PM PDT 24
Finished Jun 10 05:46:38 PM PDT 24
Peak memory 250888 kb
Host smart-1964743f-9b07-425f-ae39-7044035681d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710316609 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_post_trans.1710316609
Directory /workspace/0.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all.820264727
Short name T624
Test name
Test status
Simulation time 12691992254 ps
CPU time 243.81 seconds
Started Jun 10 05:46:33 PM PDT 24
Finished Jun 10 05:50:38 PM PDT 24
Peak memory 284196 kb
Host smart-8332a1c1-b57f-4cbd-9405-fbe3dc2fd430
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820264727 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.lc_ctrl_stress_all.820264727
Directory /workspace/0.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.lc_ctrl_volatile_unlock_smoke.1660236095
Short name T663
Test name
Test status
Simulation time 18431715 ps
CPU time 1.03 seconds
Started Jun 10 05:46:32 PM PDT 24
Finished Jun 10 05:46:34 PM PDT 24
Peak memory 218336 kb
Host smart-f931b040-2f05-4349-ac8e-d1cbf6792a81
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660236095 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ct
rl_volatile_unlock_smoke.1660236095
Directory /workspace/0.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_alert_test.1595055640
Short name T353
Test name
Test status
Simulation time 15398283 ps
CPU time 1.09 seconds
Started Jun 10 05:46:37 PM PDT 24
Finished Jun 10 05:46:38 PM PDT 24
Peak memory 209456 kb
Host smart-5099d973-8b84-49ca-ac1c-a9ba2d97600d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595055640 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_alert_test.1595055640
Directory /workspace/1.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.lc_ctrl_errors.2642635635
Short name T221
Test name
Test status
Simulation time 648620232 ps
CPU time 25.37 seconds
Started Jun 10 05:46:34 PM PDT 24
Finished Jun 10 05:47:00 PM PDT 24
Peak memory 218596 kb
Host smart-5c681125-c117-4721-8ba7-db319b4e3818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642635635 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_errors.2642635635
Directory /workspace/1.lc_ctrl_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_access.3796838313
Short name T619
Test name
Test status
Simulation time 3617701107 ps
CPU time 8.31 seconds
Started Jun 10 05:46:35 PM PDT 24
Finished Jun 10 05:46:44 PM PDT 24
Peak memory 218284 kb
Host smart-9c3a0c7a-1c20-41ed-8c57-79413d569001
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796838313 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_access.3796838313
Directory /workspace/1.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_errors.4062763398
Short name T102
Test name
Test status
Simulation time 27295219124 ps
CPU time 41.03 seconds
Started Jun 10 05:46:39 PM PDT 24
Finished Jun 10 05:47:20 PM PDT 24
Peak memory 219396 kb
Host smart-deaaeef9-c815-4bd9-b520-50358611646e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062763398 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_er
rors.4062763398
Directory /workspace/1.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_priority.2040428989
Short name T501
Test name
Test status
Simulation time 111338639 ps
CPU time 2.33 seconds
Started Jun 10 05:46:32 PM PDT 24
Finished Jun 10 05:46:35 PM PDT 24
Peak memory 217796 kb
Host smart-d4d6436b-7311-4a33-bde0-22125c662038
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040428989 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_priority.2
040428989
Directory /workspace/1.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_prog_failure.2707694600
Short name T554
Test name
Test status
Simulation time 1322979951 ps
CPU time 8.88 seconds
Started Jun 10 05:46:41 PM PDT 24
Finished Jun 10 05:46:50 PM PDT 24
Peak memory 223596 kb
Host smart-1b8cbc92-74df-4780-8b05-4aa0a079764f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707694600 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag
_prog_failure.2707694600
Directory /workspace/1.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_regwen_during_op.282089192
Short name T343
Test name
Test status
Simulation time 994105454 ps
CPU time 30.2 seconds
Started Jun 10 05:46:36 PM PDT 24
Finished Jun 10 05:47:06 PM PDT 24
Peak memory 218200 kb
Host smart-3f8b2c50-7d3c-403c-9fa2-57737bec2f4f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282089192 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_j
tag_regwen_during_op.282089192
Directory /workspace/1.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_smoke.1946142469
Short name T751
Test name
Test status
Simulation time 2064904689 ps
CPU time 8.83 seconds
Started Jun 10 05:46:41 PM PDT 24
Finished Jun 10 05:46:50 PM PDT 24
Peak memory 218144 kb
Host smart-610d0c88-7a94-4953-8c34-d56c4ef92061
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946142469 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_smoke.
1946142469
Directory /workspace/1.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_failure.2581222423
Short name T329
Test name
Test status
Simulation time 9757477627 ps
CPU time 80.64 seconds
Started Jun 10 05:46:36 PM PDT 24
Finished Jun 10 05:47:57 PM PDT 24
Peak memory 250780 kb
Host smart-f9f62323-14cd-4832-80dc-748c306226c8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581222423 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jta
g_state_failure.2581222423
Directory /workspace/1.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_post_trans.3696423112
Short name T804
Test name
Test status
Simulation time 1830308135 ps
CPU time 9.56 seconds
Started Jun 10 05:46:40 PM PDT 24
Finished Jun 10 05:46:50 PM PDT 24
Peak memory 218572 kb
Host smart-5b5078ee-a9f8-4fcb-9c71-33a8e5b1d44b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696423112 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_state_post_trans.3696423112
Directory /workspace/1.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_prog_failure.3695855667
Short name T865
Test name
Test status
Simulation time 73409775 ps
CPU time 3.24 seconds
Started Jun 10 05:46:36 PM PDT 24
Finished Jun 10 05:46:39 PM PDT 24
Peak memory 218684 kb
Host smart-6e1fb1ac-c10f-4b66-add8-8d2905e389b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695855667 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_prog_failure.3695855667
Directory /workspace/1.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_regwen_during_op.2048823715
Short name T743
Test name
Test status
Simulation time 1301611500 ps
CPU time 17.42 seconds
Started Jun 10 05:46:38 PM PDT 24
Finished Jun 10 05:46:56 PM PDT 24
Peak memory 218256 kb
Host smart-2640ce45-8578-4265-a148-9e863d79f9a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048823715 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_regwen_during_op.2048823715
Directory /workspace/1.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_cm.1359916921
Short name T89
Test name
Test status
Simulation time 743998326 ps
CPU time 41.58 seconds
Started Jun 10 05:46:41 PM PDT 24
Finished Jun 10 05:47:23 PM PDT 24
Peak memory 284956 kb
Host smart-06a0b54c-d20c-46e5-83b9-45bb89856b16
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359916921 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_cm.1359916921
Directory /workspace/1.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_mubi.2388522708
Short name T456
Test name
Test status
Simulation time 909891829 ps
CPU time 22.71 seconds
Started Jun 10 05:46:34 PM PDT 24
Finished Jun 10 05:46:58 PM PDT 24
Peak memory 219420 kb
Host smart-f993fdec-8316-4ffb-9a44-ded9469d8c01
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388522708 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_mubi.2388522708
Directory /workspace/1.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_digest.138912700
Short name T435
Test name
Test status
Simulation time 1130963388 ps
CPU time 8.08 seconds
Started Jun 10 05:46:42 PM PDT 24
Finished Jun 10 05:46:50 PM PDT 24
Peak memory 218724 kb
Host smart-89ac8fa8-4e6e-4565-9ed0-47bf226fb628
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138912700 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_dig
est.138912700
Directory /workspace/1.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_mux.2273477900
Short name T408
Test name
Test status
Simulation time 231725998 ps
CPU time 7.98 seconds
Started Jun 10 05:46:42 PM PDT 24
Finished Jun 10 05:46:50 PM PDT 24
Peak memory 218556 kb
Host smart-25437ef1-b13d-4424-947f-89c102b45606
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273477900 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_mux.2
273477900
Directory /workspace/1.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/1.lc_ctrl_security_escalation.2789393415
Short name T273
Test name
Test status
Simulation time 1128501555 ps
CPU time 8.95 seconds
Started Jun 10 05:46:38 PM PDT 24
Finished Jun 10 05:46:47 PM PDT 24
Peak memory 225912 kb
Host smart-400e296a-ae60-47a0-8944-43fc6ced6716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789393415 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_security_escalation.2789393415
Directory /workspace/1.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/1.lc_ctrl_smoke.3273568132
Short name T784
Test name
Test status
Simulation time 56102625 ps
CPU time 3.13 seconds
Started Jun 10 05:46:35 PM PDT 24
Finished Jun 10 05:46:39 PM PDT 24
Peak memory 215096 kb
Host smart-1dfb795f-0c8c-432d-9c45-1fe1883108db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273568132 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_smoke.3273568132
Directory /workspace/1.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_failure.1408545360
Short name T355
Test name
Test status
Simulation time 263703539 ps
CPU time 18.23 seconds
Started Jun 10 05:46:41 PM PDT 24
Finished Jun 10 05:46:59 PM PDT 24
Peak memory 251360 kb
Host smart-097cdb09-eab0-4853-911b-5a2a6ffeef27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408545360 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_failure.1408545360
Directory /workspace/1.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_post_trans.628013180
Short name T416
Test name
Test status
Simulation time 188893844 ps
CPU time 8.71 seconds
Started Jun 10 05:46:37 PM PDT 24
Finished Jun 10 05:46:46 PM PDT 24
Peak memory 251616 kb
Host smart-234c64c4-1724-4680-9792-27b8721a6c6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628013180 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_post_trans.628013180
Directory /workspace/1.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_stress_all.2301673103
Short name T185
Test name
Test status
Simulation time 12379985688 ps
CPU time 150.16 seconds
Started Jun 10 05:46:41 PM PDT 24
Finished Jun 10 05:49:11 PM PDT 24
Peak memory 273360 kb
Host smart-f9cbd559-6ba9-4bd7-aefe-fd76226a2317
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301673103 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.lc_ctrl_stress_all.2301673103
Directory /workspace/1.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.lc_ctrl_volatile_unlock_smoke.1577904480
Short name T384
Test name
Test status
Simulation time 17085320 ps
CPU time 1.2 seconds
Started Jun 10 05:46:36 PM PDT 24
Finished Jun 10 05:46:38 PM PDT 24
Peak memory 213468 kb
Host smart-f93427da-e0f2-400e-9dac-2fa4ae7ace12
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577904480 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ct
rl_volatile_unlock_smoke.1577904480
Directory /workspace/1.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_alert_test.1938877790
Short name T92
Test name
Test status
Simulation time 35186532 ps
CPU time 1.14 seconds
Started Jun 10 05:47:39 PM PDT 24
Finished Jun 10 05:47:41 PM PDT 24
Peak memory 209596 kb
Host smart-f038ecdf-8343-43ea-ac61-6529768a37e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938877790 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_alert_test.1938877790
Directory /workspace/10.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.lc_ctrl_errors.391662094
Short name T792
Test name
Test status
Simulation time 973639628 ps
CPU time 11.11 seconds
Started Jun 10 05:47:27 PM PDT 24
Finished Jun 10 05:47:39 PM PDT 24
Peak memory 218672 kb
Host smart-c22d2a32-d937-4f69-9d7c-b61e61b87dc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391662094 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_errors.391662094
Directory /workspace/10.lc_ctrl_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_access.1968648797
Short name T25
Test name
Test status
Simulation time 3975354321 ps
CPU time 8.37 seconds
Started Jun 10 05:47:29 PM PDT 24
Finished Jun 10 05:47:38 PM PDT 24
Peak memory 218136 kb
Host smart-c2c02439-d424-4ce4-be2f-45bdb743a6c4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968648797 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_access.1968648797
Directory /workspace/10.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_errors.3230975242
Short name T45
Test name
Test status
Simulation time 1032837505 ps
CPU time 20.43 seconds
Started Jun 10 05:47:31 PM PDT 24
Finished Jun 10 05:47:52 PM PDT 24
Peak memory 218796 kb
Host smart-c8b70768-7767-418c-a7d3-dfbecbfb1b0f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230975242 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_e
rrors.3230975242
Directory /workspace/10.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_prog_failure.341489087
Short name T422
Test name
Test status
Simulation time 188855275 ps
CPU time 4.64 seconds
Started Jun 10 05:47:30 PM PDT 24
Finished Jun 10 05:47:35 PM PDT 24
Peak memory 218716 kb
Host smart-30d84f0b-7682-4f85-b2e7-2a62b22511f7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341489087 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag
_prog_failure.341489087
Directory /workspace/10.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_smoke.2985065609
Short name T569
Test name
Test status
Simulation time 1571439532 ps
CPU time 4.85 seconds
Started Jun 10 05:47:31 PM PDT 24
Finished Jun 10 05:47:36 PM PDT 24
Peak memory 218268 kb
Host smart-3c39ced1-49b0-4a59-98ff-d886c84dd6b6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985065609 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_smoke
.2985065609
Directory /workspace/10.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_failure.1603669206
Short name T734
Test name
Test status
Simulation time 1737094397 ps
CPU time 39.72 seconds
Started Jun 10 05:47:31 PM PDT 24
Finished Jun 10 05:48:11 PM PDT 24
Peak memory 252064 kb
Host smart-44198162-23b3-4d8c-9a95-0e7d1c8c4cae
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603669206 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jt
ag_state_failure.1603669206
Directory /workspace/10.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_post_trans.4215068828
Short name T847
Test name
Test status
Simulation time 728113702 ps
CPU time 24.94 seconds
Started Jun 10 05:47:30 PM PDT 24
Finished Jun 10 05:47:56 PM PDT 24
Peak memory 246408 kb
Host smart-45bfa2e3-cc1e-417e-bd75-d91a7fd1965e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215068828 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl
_jtag_state_post_trans.4215068828
Directory /workspace/10.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_prog_failure.3281643120
Short name T557
Test name
Test status
Simulation time 50216198 ps
CPU time 2.55 seconds
Started Jun 10 05:47:30 PM PDT 24
Finished Jun 10 05:47:33 PM PDT 24
Peak memory 222564 kb
Host smart-1dab9b80-0428-4908-81ff-f2bf6b9f3b45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281643120 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_prog_failure.3281643120
Directory /workspace/10.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_mubi.3800160334
Short name T240
Test name
Test status
Simulation time 369451545 ps
CPU time 11.74 seconds
Started Jun 10 05:47:30 PM PDT 24
Finished Jun 10 05:47:42 PM PDT 24
Peak memory 226548 kb
Host smart-5b015ea6-39ec-4ecf-b36b-591ffabb4801
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800160334 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_mubi.3800160334
Directory /workspace/10.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_digest.3827517751
Short name T864
Test name
Test status
Simulation time 654633262 ps
CPU time 7.87 seconds
Started Jun 10 05:47:31 PM PDT 24
Finished Jun 10 05:47:39 PM PDT 24
Peak memory 218644 kb
Host smart-5cc0cfdd-79fb-4d20-8ad8-51fce08d749b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827517751 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_d
igest.3827517751
Directory /workspace/10.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_mux.901016866
Short name T594
Test name
Test status
Simulation time 275870971 ps
CPU time 11.39 seconds
Started Jun 10 05:47:27 PM PDT 24
Finished Jun 10 05:47:39 PM PDT 24
Peak memory 218720 kb
Host smart-fec42357-5fd1-4fb2-a887-bd58ea99a205
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901016866 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_mux.901016866
Directory /workspace/10.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/10.lc_ctrl_security_escalation.3211853699
Short name T860
Test name
Test status
Simulation time 354797043 ps
CPU time 11.39 seconds
Started Jun 10 05:47:28 PM PDT 24
Finished Jun 10 05:47:40 PM PDT 24
Peak memory 226648 kb
Host smart-e8fba3ca-fe4c-4d02-9e5b-df219ef8fb4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211853699 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_security_escalation.3211853699
Directory /workspace/10.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/10.lc_ctrl_smoke.2720273686
Short name T252
Test name
Test status
Simulation time 30061312 ps
CPU time 1.18 seconds
Started Jun 10 05:47:33 PM PDT 24
Finished Jun 10 05:47:35 PM PDT 24
Peak memory 214072 kb
Host smart-2be6d15b-0b08-459c-a102-64b95b07fdb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720273686 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_smoke.2720273686
Directory /workspace/10.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_failure.2513586539
Short name T693
Test name
Test status
Simulation time 766758964 ps
CPU time 32.55 seconds
Started Jun 10 05:47:28 PM PDT 24
Finished Jun 10 05:48:01 PM PDT 24
Peak memory 251452 kb
Host smart-73f98cae-c72d-4f91-8b68-31898f51ed76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513586539 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_failure.2513586539
Directory /workspace/10.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_post_trans.4092166161
Short name T374
Test name
Test status
Simulation time 45420061 ps
CPU time 3.09 seconds
Started Jun 10 05:47:31 PM PDT 24
Finished Jun 10 05:47:34 PM PDT 24
Peak memory 222880 kb
Host smart-7edf831f-3151-4570-b723-8a027f1ad89d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092166161 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_post_trans.4092166161
Directory /workspace/10.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all.3173647915
Short name T581
Test name
Test status
Simulation time 7698879221 ps
CPU time 64.48 seconds
Started Jun 10 05:47:27 PM PDT 24
Finished Jun 10 05:48:32 PM PDT 24
Peak memory 279224 kb
Host smart-e704854d-2a84-4482-aea8-f8a31c91430d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173647915 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.lc_ctrl_stress_all.3173647915
Directory /workspace/10.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all_with_rand_reset.3895078627
Short name T73
Test name
Test status
Simulation time 32221275383 ps
CPU time 585.12 seconds
Started Jun 10 05:47:34 PM PDT 24
Finished Jun 10 05:57:19 PM PDT 24
Peak memory 284100 kb
Host smart-5b36fa18-7ea5-4646-88f5-bee451d06f67
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3895078627 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_stress_all_with_rand_reset.3895078627
Directory /workspace/10.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.lc_ctrl_volatile_unlock_smoke.685948722
Short name T798
Test name
Test status
Simulation time 56881526 ps
CPU time 1.1 seconds
Started Jun 10 05:47:34 PM PDT 24
Finished Jun 10 05:47:35 PM PDT 24
Peak memory 218316 kb
Host smart-4a236eaf-0892-489b-9f23-5d3caa0eab22
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685948722 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ct
rl_volatile_unlock_smoke.685948722
Directory /workspace/10.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_alert_test.1149764987
Short name T725
Test name
Test status
Simulation time 21217386 ps
CPU time 1 seconds
Started Jun 10 05:47:41 PM PDT 24
Finished Jun 10 05:47:42 PM PDT 24
Peak memory 209460 kb
Host smart-33e221f2-1c24-4853-ab85-2a68354c3e38
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149764987 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_alert_test.1149764987
Directory /workspace/11.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.lc_ctrl_errors.3235917199
Short name T50
Test name
Test status
Simulation time 1047869617 ps
CPU time 10.13 seconds
Started Jun 10 05:47:33 PM PDT 24
Finished Jun 10 05:47:44 PM PDT 24
Peak memory 218684 kb
Host smart-048fbd05-61cf-4401-bd2a-1f3ba2f97091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235917199 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_errors.3235917199
Directory /workspace/11.lc_ctrl_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_access.3120922978
Short name T24
Test name
Test status
Simulation time 4507132699 ps
CPU time 13.55 seconds
Started Jun 10 05:47:34 PM PDT 24
Finished Jun 10 05:47:48 PM PDT 24
Peak memory 218188 kb
Host smart-f7ce17d6-84f2-46d5-9831-4011403d6e9b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120922978 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_access.3120922978
Directory /workspace/11.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_errors.2263652136
Short name T781
Test name
Test status
Simulation time 1584412570 ps
CPU time 43.9 seconds
Started Jun 10 05:47:35 PM PDT 24
Finished Jun 10 05:48:19 PM PDT 24
Peak memory 218708 kb
Host smart-1d62b313-748e-49b1-8d48-f90c089507c4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263652136 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_e
rrors.2263652136
Directory /workspace/11.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_prog_failure.2365839324
Short name T484
Test name
Test status
Simulation time 475583855 ps
CPU time 9.08 seconds
Started Jun 10 05:47:40 PM PDT 24
Finished Jun 10 05:47:49 PM PDT 24
Peak memory 218712 kb
Host smart-1712e0e3-9568-43f2-ba09-9a2ace782653
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365839324 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jta
g_prog_failure.2365839324
Directory /workspace/11.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_smoke.311704654
Short name T231
Test name
Test status
Simulation time 179308853 ps
CPU time 2.64 seconds
Started Jun 10 05:47:36 PM PDT 24
Finished Jun 10 05:47:39 PM PDT 24
Peak memory 218216 kb
Host smart-7a9a8740-7067-44e7-acee-0b8f4253e7a4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311704654 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_smoke.
311704654
Directory /workspace/11.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_failure.2624051324
Short name T791
Test name
Test status
Simulation time 13215871004 ps
CPU time 63.83 seconds
Started Jun 10 05:47:35 PM PDT 24
Finished Jun 10 05:48:39 PM PDT 24
Peak memory 277404 kb
Host smart-5335a89c-129b-49dd-a178-96108e4948cb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624051324 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jt
ag_state_failure.2624051324
Directory /workspace/11.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_post_trans.1037232845
Short name T260
Test name
Test status
Simulation time 2065496306 ps
CPU time 15.58 seconds
Started Jun 10 05:47:35 PM PDT 24
Finished Jun 10 05:47:51 PM PDT 24
Peak memory 218724 kb
Host smart-0022993a-848a-458f-8c3c-4aee94d046cd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037232845 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl
_jtag_state_post_trans.1037232845
Directory /workspace/11.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_prog_failure.4013609233
Short name T65
Test name
Test status
Simulation time 99835544 ps
CPU time 2.51 seconds
Started Jun 10 05:47:35 PM PDT 24
Finished Jun 10 05:47:38 PM PDT 24
Peak memory 222896 kb
Host smart-4efcf99a-2a75-4701-823f-3fd9a38596b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013609233 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_prog_failure.4013609233
Directory /workspace/11.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_mubi.4130598908
Short name T592
Test name
Test status
Simulation time 351299510 ps
CPU time 13.33 seconds
Started Jun 10 05:47:39 PM PDT 24
Finished Jun 10 05:47:53 PM PDT 24
Peak memory 218804 kb
Host smart-857458d6-afcb-4c71-bfb8-c5d3b56d584c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130598908 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_mubi.4130598908
Directory /workspace/11.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_digest.1199928090
Short name T401
Test name
Test status
Simulation time 413751324 ps
CPU time 16.09 seconds
Started Jun 10 05:47:39 PM PDT 24
Finished Jun 10 05:47:55 PM PDT 24
Peak memory 218748 kb
Host smart-52d4f91f-ad4a-44a5-be06-cdee3e0a4292
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199928090 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_d
igest.1199928090
Directory /workspace/11.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_mux.2031544372
Short name T267
Test name
Test status
Simulation time 1633618272 ps
CPU time 8.47 seconds
Started Jun 10 05:47:34 PM PDT 24
Finished Jun 10 05:47:43 PM PDT 24
Peak memory 218728 kb
Host smart-60eb7d51-c935-4d8a-8d04-8f936fc9b83a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031544372 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_mux.
2031544372
Directory /workspace/11.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/11.lc_ctrl_security_escalation.1534218330
Short name T544
Test name
Test status
Simulation time 589772747 ps
CPU time 11.31 seconds
Started Jun 10 05:47:36 PM PDT 24
Finished Jun 10 05:47:48 PM PDT 24
Peak memory 218588 kb
Host smart-ffa71ab4-8c42-4744-a49f-91f195078d8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534218330 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_security_escalation.1534218330
Directory /workspace/11.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/11.lc_ctrl_smoke.2016140221
Short name T333
Test name
Test status
Simulation time 40734594 ps
CPU time 1.27 seconds
Started Jun 10 05:47:34 PM PDT 24
Finished Jun 10 05:47:35 PM PDT 24
Peak memory 218240 kb
Host smart-f6bd57fd-6145-4768-886f-d9b7575260b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016140221 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_smoke.2016140221
Directory /workspace/11.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_failure.807052705
Short name T472
Test name
Test status
Simulation time 820187473 ps
CPU time 19.5 seconds
Started Jun 10 05:47:32 PM PDT 24
Finished Jun 10 05:47:52 PM PDT 24
Peak memory 251480 kb
Host smart-386b27eb-f048-4ac6-b255-17653fd3d2b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807052705 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_failure.807052705
Directory /workspace/11.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_post_trans.738920595
Short name T241
Test name
Test status
Simulation time 112737308 ps
CPU time 7 seconds
Started Jun 10 05:47:35 PM PDT 24
Finished Jun 10 05:47:42 PM PDT 24
Peak memory 251536 kb
Host smart-c5027c65-7924-4fdd-bd4c-e550d066d362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738920595 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_post_trans.738920595
Directory /workspace/11.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_stress_all.4032887653
Short name T443
Test name
Test status
Simulation time 171303931474 ps
CPU time 144.26 seconds
Started Jun 10 05:47:37 PM PDT 24
Finished Jun 10 05:50:01 PM PDT 24
Peak memory 284260 kb
Host smart-e05c2416-166f-4b5d-8f23-bb324a0e0b3b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032887653 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.lc_ctrl_stress_all.4032887653
Directory /workspace/11.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.lc_ctrl_stress_all_with_rand_reset.3191959619
Short name T744
Test name
Test status
Simulation time 72187381962 ps
CPU time 653.75 seconds
Started Jun 10 05:47:36 PM PDT 24
Finished Jun 10 05:58:31 PM PDT 24
Peak memory 284332 kb
Host smart-22cddaf1-907b-466c-b70e-af56804bded9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3191959619 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_stress_all_with_rand_reset.3191959619
Directory /workspace/11.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.lc_ctrl_volatile_unlock_smoke.4251522723
Short name T661
Test name
Test status
Simulation time 21238439 ps
CPU time 0.94 seconds
Started Jun 10 05:47:33 PM PDT 24
Finished Jun 10 05:47:35 PM PDT 24
Peak memory 209588 kb
Host smart-7b3e405a-faa3-4e04-9a5a-7fd478d05b53
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251522723 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_c
trl_volatile_unlock_smoke.4251522723
Directory /workspace/11.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_alert_test.3834277294
Short name T236
Test name
Test status
Simulation time 16413832 ps
CPU time 0.97 seconds
Started Jun 10 05:47:42 PM PDT 24
Finished Jun 10 05:47:44 PM PDT 24
Peak memory 209404 kb
Host smart-775b393d-5a5e-4fe0-ab16-0c4b39fe2604
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834277294 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_alert_test.3834277294
Directory /workspace/12.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.lc_ctrl_errors.160715132
Short name T605
Test name
Test status
Simulation time 558708298 ps
CPU time 13.66 seconds
Started Jun 10 05:47:39 PM PDT 24
Finished Jun 10 05:47:53 PM PDT 24
Peak memory 226536 kb
Host smart-14836afe-5774-44c8-a743-ee8f79abc137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160715132 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_errors.160715132
Directory /workspace/12.lc_ctrl_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_access.83437995
Short name T658
Test name
Test status
Simulation time 160626455 ps
CPU time 2 seconds
Started Jun 10 05:47:41 PM PDT 24
Finished Jun 10 05:47:43 PM PDT 24
Peak memory 217744 kb
Host smart-1fa4c091-4a0c-400b-8090-eaafc343d6a3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83437995 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_access.83437995
Directory /workspace/12.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_errors.2105063566
Short name T631
Test name
Test status
Simulation time 15122339557 ps
CPU time 40.07 seconds
Started Jun 10 05:47:42 PM PDT 24
Finished Jun 10 05:48:22 PM PDT 24
Peak memory 219452 kb
Host smart-7251237f-706d-47b3-a375-ed9b3c641baa
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105063566 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_e
rrors.2105063566
Directory /workspace/12.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_prog_failure.3845729413
Short name T641
Test name
Test status
Simulation time 464110360 ps
CPU time 4.43 seconds
Started Jun 10 05:47:38 PM PDT 24
Finished Jun 10 05:47:43 PM PDT 24
Peak memory 222264 kb
Host smart-801930e8-2211-4e78-82e9-59685f2da777
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845729413 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jta
g_prog_failure.3845729413
Directory /workspace/12.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_smoke.1333309517
Short name T675
Test name
Test status
Simulation time 171767601 ps
CPU time 4.87 seconds
Started Jun 10 05:47:35 PM PDT 24
Finished Jun 10 05:47:40 PM PDT 24
Peak memory 218248 kb
Host smart-4ce29fb2-2922-48a3-a508-43fb788e2578
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333309517 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_smoke
.1333309517
Directory /workspace/12.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_failure.4105826091
Short name T869
Test name
Test status
Simulation time 2502482926 ps
CPU time 50.7 seconds
Started Jun 10 05:47:35 PM PDT 24
Finished Jun 10 05:48:26 PM PDT 24
Peak memory 283932 kb
Host smart-1e4d1b87-88f4-46d3-b8f9-37dbdaf9ee6c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105826091 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jt
ag_state_failure.4105826091
Directory /workspace/12.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_post_trans.3762312435
Short name T298
Test name
Test status
Simulation time 3947734456 ps
CPU time 31.87 seconds
Started Jun 10 05:47:40 PM PDT 24
Finished Jun 10 05:48:12 PM PDT 24
Peak memory 248972 kb
Host smart-631c79f3-de16-44e7-847e-b7e7a0c93948
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762312435 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl
_jtag_state_post_trans.3762312435
Directory /workspace/12.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_prog_failure.2332163105
Short name T220
Test name
Test status
Simulation time 573383473 ps
CPU time 3.25 seconds
Started Jun 10 05:47:38 PM PDT 24
Finished Jun 10 05:47:41 PM PDT 24
Peak memory 218684 kb
Host smart-47ca9d9f-a8cf-404e-a198-4dbe5c22b060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332163105 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_prog_failure.2332163105
Directory /workspace/12.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_mubi.974856733
Short name T812
Test name
Test status
Simulation time 1671144512 ps
CPU time 29.66 seconds
Started Jun 10 05:47:42 PM PDT 24
Finished Jun 10 05:48:11 PM PDT 24
Peak memory 219300 kb
Host smart-4b752197-f07c-43a3-a104-5b99ffb6bf72
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974856733 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_mubi.974856733
Directory /workspace/12.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_digest.2969445890
Short name T453
Test name
Test status
Simulation time 855976597 ps
CPU time 8.82 seconds
Started Jun 10 05:47:42 PM PDT 24
Finished Jun 10 05:47:52 PM PDT 24
Peak memory 218660 kb
Host smart-2e83c20a-9459-4260-9771-a5182c90a23e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969445890 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_d
igest.2969445890
Directory /workspace/12.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_mux.1424641061
Short name T832
Test name
Test status
Simulation time 9526331777 ps
CPU time 27.27 seconds
Started Jun 10 05:47:42 PM PDT 24
Finished Jun 10 05:48:10 PM PDT 24
Peak memory 226600 kb
Host smart-87a305f3-1a20-4e16-8d1d-fbe78af1bd87
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424641061 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_mux.
1424641061
Directory /workspace/12.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/12.lc_ctrl_security_escalation.4175938764
Short name T491
Test name
Test status
Simulation time 2679194216 ps
CPU time 7.69 seconds
Started Jun 10 05:47:38 PM PDT 24
Finished Jun 10 05:47:46 PM PDT 24
Peak memory 226020 kb
Host smart-ec09cbeb-4c61-44a2-b12e-77e102d87a78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175938764 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_security_escalation.4175938764
Directory /workspace/12.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/12.lc_ctrl_smoke.3926938829
Short name T311
Test name
Test status
Simulation time 128704685 ps
CPU time 3.23 seconds
Started Jun 10 05:47:39 PM PDT 24
Finished Jun 10 05:47:42 PM PDT 24
Peak memory 215036 kb
Host smart-5b8d43c9-58ef-4769-95bc-73944fd4026d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926938829 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_smoke.3926938829
Directory /workspace/12.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_failure.2266373984
Short name T623
Test name
Test status
Simulation time 644924299 ps
CPU time 18.99 seconds
Started Jun 10 05:47:40 PM PDT 24
Finished Jun 10 05:47:59 PM PDT 24
Peak memory 251452 kb
Host smart-7b35c8f8-eff5-48e4-a895-5a7dcf64c0c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266373984 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_failure.2266373984
Directory /workspace/12.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_post_trans.2054352903
Short name T371
Test name
Test status
Simulation time 78825053 ps
CPU time 6.47 seconds
Started Jun 10 05:47:36 PM PDT 24
Finished Jun 10 05:47:43 PM PDT 24
Peak memory 251468 kb
Host smart-106d2b1a-1592-4fd0-8c65-e26aaaeba29e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054352903 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_post_trans.2054352903
Directory /workspace/12.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_stress_all.1306680984
Short name T548
Test name
Test status
Simulation time 5108885341 ps
CPU time 102.25 seconds
Started Jun 10 05:47:43 PM PDT 24
Finished Jun 10 05:49:26 PM PDT 24
Peak memory 251452 kb
Host smart-ff33e9ca-639f-46a4-a8f5-84276a2a6d6a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306680984 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.lc_ctrl_stress_all.1306680984
Directory /workspace/12.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.lc_ctrl_errors.1228194645
Short name T611
Test name
Test status
Simulation time 218296608 ps
CPU time 8.77 seconds
Started Jun 10 05:47:41 PM PDT 24
Finished Jun 10 05:47:50 PM PDT 24
Peak memory 218676 kb
Host smart-ff58ea7c-b094-4c7c-be43-2ca6cd1d25a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228194645 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_errors.1228194645
Directory /workspace/13.lc_ctrl_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_access.554421084
Short name T186
Test name
Test status
Simulation time 11171300385 ps
CPU time 9.41 seconds
Started Jun 10 05:47:47 PM PDT 24
Finished Jun 10 05:47:57 PM PDT 24
Peak memory 218212 kb
Host smart-183605f4-f138-4ee4-bcbd-2e0b46eabec9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554421084 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_access.554421084
Directory /workspace/13.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_errors.511136492
Short name T777
Test name
Test status
Simulation time 1605643861 ps
CPU time 47.01 seconds
Started Jun 10 05:47:44 PM PDT 24
Finished Jun 10 05:48:31 PM PDT 24
Peak memory 226020 kb
Host smart-22048d61-1b02-4c25-82e8-af2dde74b782
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511136492 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_er
rors.511136492
Directory /workspace/13.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_prog_failure.3204799202
Short name T655
Test name
Test status
Simulation time 1052228449 ps
CPU time 9.57 seconds
Started Jun 10 05:47:46 PM PDT 24
Finished Jun 10 05:47:56 PM PDT 24
Peak memory 224632 kb
Host smart-bf2a5433-b4a7-4902-9244-a4b85d33884f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204799202 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jta
g_prog_failure.3204799202
Directory /workspace/13.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_smoke.495339606
Short name T29
Test name
Test status
Simulation time 251609797 ps
CPU time 2.8 seconds
Started Jun 10 05:47:47 PM PDT 24
Finished Jun 10 05:47:50 PM PDT 24
Peak memory 218052 kb
Host smart-cea8736c-6d5a-4094-8556-2fa3068665b3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495339606 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_smoke.
495339606
Directory /workspace/13.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_failure.2638845571
Short name T600
Test name
Test status
Simulation time 2365904960 ps
CPU time 46.8 seconds
Started Jun 10 05:47:46 PM PDT 24
Finished Jun 10 05:48:34 PM PDT 24
Peak memory 267900 kb
Host smart-819f19f5-7ef4-43ce-8c48-ca20138b3096
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638845571 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jt
ag_state_failure.2638845571
Directory /workspace/13.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_post_trans.4027322272
Short name T678
Test name
Test status
Simulation time 1749025127 ps
CPU time 15.42 seconds
Started Jun 10 05:47:45 PM PDT 24
Finished Jun 10 05:48:02 PM PDT 24
Peak memory 251444 kb
Host smart-0ad34a6e-de4d-415c-9cdd-dcb70e373ad6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027322272 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl
_jtag_state_post_trans.4027322272
Directory /workspace/13.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_prog_failure.1815001070
Short name T340
Test name
Test status
Simulation time 17730380 ps
CPU time 1.74 seconds
Started Jun 10 05:47:44 PM PDT 24
Finished Jun 10 05:47:46 PM PDT 24
Peak memory 218632 kb
Host smart-21648119-c379-4d71-82fc-49bbabf34a72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815001070 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_prog_failure.1815001070
Directory /workspace/13.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_mubi.1083964714
Short name T219
Test name
Test status
Simulation time 4489768574 ps
CPU time 10.91 seconds
Started Jun 10 05:47:45 PM PDT 24
Finished Jun 10 05:47:57 PM PDT 24
Peak memory 218852 kb
Host smart-4f4bdc94-2af3-47d3-b3f5-5a84720f7def
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083964714 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_mubi.1083964714
Directory /workspace/13.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_digest.2526202144
Short name T274
Test name
Test status
Simulation time 1596118685 ps
CPU time 10.29 seconds
Started Jun 10 05:47:45 PM PDT 24
Finished Jun 10 05:47:57 PM PDT 24
Peak memory 226552 kb
Host smart-d41a762b-784d-48df-96a5-9683749dfd29
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526202144 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_d
igest.2526202144
Directory /workspace/13.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_mux.2396189566
Short name T234
Test name
Test status
Simulation time 1074589499 ps
CPU time 10.08 seconds
Started Jun 10 05:47:48 PM PDT 24
Finished Jun 10 05:47:58 PM PDT 24
Peak memory 218688 kb
Host smart-31cede44-879e-480f-be99-9d1ee0372c6a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396189566 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_mux.
2396189566
Directory /workspace/13.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/13.lc_ctrl_security_escalation.2129025080
Short name T395
Test name
Test status
Simulation time 780315755 ps
CPU time 6.21 seconds
Started Jun 10 05:47:47 PM PDT 24
Finished Jun 10 05:47:53 PM PDT 24
Peak memory 225444 kb
Host smart-e10ab9d5-8910-4a47-9b7b-0e25529127c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129025080 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_security_escalation.2129025080
Directory /workspace/13.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/13.lc_ctrl_smoke.2814587921
Short name T593
Test name
Test status
Simulation time 65789652 ps
CPU time 1.43 seconds
Started Jun 10 05:47:42 PM PDT 24
Finished Jun 10 05:47:44 PM PDT 24
Peak memory 223204 kb
Host smart-4fa57c11-7e6d-4b93-ac63-7692b4966b9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814587921 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_smoke.2814587921
Directory /workspace/13.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_failure.212817944
Short name T845
Test name
Test status
Simulation time 258855585 ps
CPU time 20.07 seconds
Started Jun 10 05:47:41 PM PDT 24
Finished Jun 10 05:48:01 PM PDT 24
Peak memory 251476 kb
Host smart-1f9256c6-4b8f-4c2b-89a5-e0d307263b76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212817944 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_failure.212817944
Directory /workspace/13.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_post_trans.3716015620
Short name T689
Test name
Test status
Simulation time 489881945 ps
CPU time 3.2 seconds
Started Jun 10 05:47:43 PM PDT 24
Finished Jun 10 05:47:47 PM PDT 24
Peak memory 226824 kb
Host smart-c884688b-7820-40dd-a78b-122d3a7b3d3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716015620 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_post_trans.3716015620
Directory /workspace/13.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all_with_rand_reset.974222642
Short name T153
Test name
Test status
Simulation time 29904284694 ps
CPU time 558.92 seconds
Started Jun 10 05:47:52 PM PDT 24
Finished Jun 10 05:57:12 PM PDT 24
Peak memory 268316 kb
Host smart-a401088d-1f44-4375-9c96-c6d747cc3982
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=974222642 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_stress_all_with_rand_reset.974222642
Directory /workspace/13.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.lc_ctrl_volatile_unlock_smoke.1893557612
Short name T413
Test name
Test status
Simulation time 14162784 ps
CPU time 1.12 seconds
Started Jun 10 05:47:42 PM PDT 24
Finished Jun 10 05:47:44 PM PDT 24
Peak memory 212416 kb
Host smart-e00e19a9-002a-4e07-8fa4-e436c8c8ec09
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893557612 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_c
trl_volatile_unlock_smoke.1893557612
Directory /workspace/13.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_alert_test.187341135
Short name T549
Test name
Test status
Simulation time 17171503 ps
CPU time 0.94 seconds
Started Jun 10 05:47:55 PM PDT 24
Finished Jun 10 05:47:57 PM PDT 24
Peak memory 209440 kb
Host smart-b77e4853-8e95-4e19-a3a1-6925527b1443
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187341135 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_alert_test.187341135
Directory /workspace/14.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.lc_ctrl_errors.2644519004
Short name T757
Test name
Test status
Simulation time 268613646 ps
CPU time 11.6 seconds
Started Jun 10 05:47:51 PM PDT 24
Finished Jun 10 05:48:03 PM PDT 24
Peak memory 218664 kb
Host smart-fc27fbad-fa94-4102-bf68-f9e0f25108cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644519004 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_errors.2644519004
Directory /workspace/14.lc_ctrl_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_access.1118974486
Short name T410
Test name
Test status
Simulation time 1294120597 ps
CPU time 7.34 seconds
Started Jun 10 05:47:52 PM PDT 24
Finished Jun 10 05:48:00 PM PDT 24
Peak memory 217912 kb
Host smart-c50e487a-a0c4-4b84-81b3-beb7a89f3693
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118974486 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_access.1118974486
Directory /workspace/14.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_errors.1897688360
Short name T377
Test name
Test status
Simulation time 5286013086 ps
CPU time 68.69 seconds
Started Jun 10 05:47:48 PM PDT 24
Finished Jun 10 05:48:57 PM PDT 24
Peak memory 219440 kb
Host smart-b0998e99-08fb-4779-9cd3-22495cf29c98
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897688360 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_e
rrors.1897688360
Directory /workspace/14.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_prog_failure.869567182
Short name T770
Test name
Test status
Simulation time 273138915 ps
CPU time 2.16 seconds
Started Jun 10 05:47:54 PM PDT 24
Finished Jun 10 05:47:57 PM PDT 24
Peak memory 218664 kb
Host smart-c16f0c60-3516-457d-8e48-071ed60b3de4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869567182 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag
_prog_failure.869567182
Directory /workspace/14.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_smoke.1503531361
Short name T546
Test name
Test status
Simulation time 1374592256 ps
CPU time 3.46 seconds
Started Jun 10 05:47:51 PM PDT 24
Finished Jun 10 05:47:55 PM PDT 24
Peak memory 218268 kb
Host smart-e2505a7e-f605-4956-bf04-344a190b0535
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503531361 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_smoke
.1503531361
Directory /workspace/14.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_failure.10126470
Short name T281
Test name
Test status
Simulation time 11761351347 ps
CPU time 111.94 seconds
Started Jun 10 05:47:56 PM PDT 24
Finished Jun 10 05:49:48 PM PDT 24
Peak memory 284048 kb
Host smart-1abacd0e-4fa5-4cda-a1b3-89558503c382
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10126470 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_s
tate_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag
_state_failure.10126470
Directory /workspace/14.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_post_trans.4176205635
Short name T477
Test name
Test status
Simulation time 5003238967 ps
CPU time 24.95 seconds
Started Jun 10 05:47:52 PM PDT 24
Finished Jun 10 05:48:17 PM PDT 24
Peak memory 251516 kb
Host smart-e1271983-c9e9-48bc-a5c7-496b7c4199d8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176205635 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl
_jtag_state_post_trans.4176205635
Directory /workspace/14.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_prog_failure.275378947
Short name T268
Test name
Test status
Simulation time 138791582 ps
CPU time 3.49 seconds
Started Jun 10 05:47:56 PM PDT 24
Finished Jun 10 05:48:00 PM PDT 24
Peak memory 222944 kb
Host smart-7b27bb51-4ee8-4b12-8fd4-af84359bd14c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275378947 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_prog_failure.275378947
Directory /workspace/14.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_mubi.2062887616
Short name T786
Test name
Test status
Simulation time 784238221 ps
CPU time 8.87 seconds
Started Jun 10 05:47:54 PM PDT 24
Finished Jun 10 05:48:03 PM PDT 24
Peak memory 226568 kb
Host smart-5d71bc85-5d86-40b3-9c77-dfca6c42b814
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062887616 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_mubi.2062887616
Directory /workspace/14.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_digest.2119010434
Short name T523
Test name
Test status
Simulation time 1499071410 ps
CPU time 13.6 seconds
Started Jun 10 05:47:51 PM PDT 24
Finished Jun 10 05:48:05 PM PDT 24
Peak memory 226552 kb
Host smart-8fe72fae-0f3c-41b6-8f5a-3103a924cc10
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119010434 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_d
igest.2119010434
Directory /workspace/14.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_mux.2593997744
Short name T664
Test name
Test status
Simulation time 353940647 ps
CPU time 14.69 seconds
Started Jun 10 05:47:53 PM PDT 24
Finished Jun 10 05:48:09 PM PDT 24
Peak memory 226540 kb
Host smart-9c04be7f-838e-4f50-aa67-e0f1b9651e78
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593997744 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_mux.
2593997744
Directory /workspace/14.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/14.lc_ctrl_security_escalation.1434945631
Short name T98
Test name
Test status
Simulation time 854774127 ps
CPU time 9.2 seconds
Started Jun 10 05:47:53 PM PDT 24
Finished Jun 10 05:48:03 PM PDT 24
Peak memory 226540 kb
Host smart-2004a990-9182-468c-9788-233137698cad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434945631 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_security_escalation.1434945631
Directory /workspace/14.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/14.lc_ctrl_smoke.3014891427
Short name T503
Test name
Test status
Simulation time 16668906 ps
CPU time 1.25 seconds
Started Jun 10 05:47:54 PM PDT 24
Finished Jun 10 05:47:56 PM PDT 24
Peak memory 214248 kb
Host smart-93d5deb1-7cec-4d49-abb3-8f6201e8c645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014891427 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_smoke.3014891427
Directory /workspace/14.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_failure.1542226640
Short name T570
Test name
Test status
Simulation time 1381325072 ps
CPU time 16.92 seconds
Started Jun 10 05:47:51 PM PDT 24
Finished Jun 10 05:48:08 PM PDT 24
Peak memory 251432 kb
Host smart-f03c0a1b-ce8f-4647-8cbd-9ac700b27f7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542226640 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_failure.1542226640
Directory /workspace/14.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_post_trans.1207736823
Short name T703
Test name
Test status
Simulation time 61840056 ps
CPU time 8.63 seconds
Started Jun 10 05:47:53 PM PDT 24
Finished Jun 10 05:48:03 PM PDT 24
Peak memory 251424 kb
Host smart-2fd69cc5-5405-41ba-9b55-398c256295f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207736823 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_post_trans.1207736823
Directory /workspace/14.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_stress_all.2339793005
Short name T72
Test name
Test status
Simulation time 5173515551 ps
CPU time 94.32 seconds
Started Jun 10 05:47:50 PM PDT 24
Finished Jun 10 05:49:25 PM PDT 24
Peak memory 248416 kb
Host smart-a33e8b36-9fd3-4275-b2a2-180b21fadd6c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339793005 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.lc_ctrl_stress_all.2339793005
Directory /workspace/14.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.lc_ctrl_stress_all_with_rand_reset.606502040
Short name T332
Test name
Test status
Simulation time 29291562815 ps
CPU time 922.96 seconds
Started Jun 10 05:47:48 PM PDT 24
Finished Jun 10 06:03:12 PM PDT 24
Peak memory 294344 kb
Host smart-022d6ed9-c388-4f79-8fc0-16cd507d5a37
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=606502040 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_stress_all_with_rand_reset.606502040
Directory /workspace/14.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.lc_ctrl_volatile_unlock_smoke.3976733900
Short name T844
Test name
Test status
Simulation time 22519567 ps
CPU time 0.94 seconds
Started Jun 10 05:47:51 PM PDT 24
Finished Jun 10 05:47:52 PM PDT 24
Peak memory 212380 kb
Host smart-8a1c58fa-6fa4-4470-a4d7-6b689748f8bc
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976733900 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_c
trl_volatile_unlock_smoke.3976733900
Directory /workspace/14.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_alert_test.686963720
Short name T370
Test name
Test status
Simulation time 27095285 ps
CPU time 0.9 seconds
Started Jun 10 05:47:56 PM PDT 24
Finished Jun 10 05:47:57 PM PDT 24
Peak memory 209448 kb
Host smart-49c42957-3753-4196-a216-0b67771cfd89
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686963720 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_alert_test.686963720
Directory /workspace/15.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.lc_ctrl_errors.3662726345
Short name T633
Test name
Test status
Simulation time 1646254177 ps
CPU time 14.83 seconds
Started Jun 10 05:47:56 PM PDT 24
Finished Jun 10 05:48:12 PM PDT 24
Peak memory 218740 kb
Host smart-f470e9c9-a927-464f-a72f-2c244b2cd005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662726345 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_errors.3662726345
Directory /workspace/15.lc_ctrl_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_access.3779497753
Short name T337
Test name
Test status
Simulation time 974091507 ps
CPU time 11.4 seconds
Started Jun 10 05:47:55 PM PDT 24
Finished Jun 10 05:48:07 PM PDT 24
Peak memory 217712 kb
Host smart-b1d18933-6e6a-4920-83d2-5d33d1fe59f8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779497753 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_access.3779497753
Directory /workspace/15.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_errors.1688957609
Short name T837
Test name
Test status
Simulation time 1702972864 ps
CPU time 52.14 seconds
Started Jun 10 05:47:57 PM PDT 24
Finished Jun 10 05:48:50 PM PDT 24
Peak memory 219380 kb
Host smart-0df20ecc-fffb-4c33-950f-ae6dfe06f88f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688957609 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_e
rrors.1688957609
Directory /workspace/15.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_prog_failure.3737712210
Short name T713
Test name
Test status
Simulation time 570213603 ps
CPU time 9.6 seconds
Started Jun 10 05:47:55 PM PDT 24
Finished Jun 10 05:48:05 PM PDT 24
Peak memory 218612 kb
Host smart-071779c2-ca5a-4df8-ae45-963b6c9bd8eb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737712210 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jta
g_prog_failure.3737712210
Directory /workspace/15.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_smoke.3670270562
Short name T356
Test name
Test status
Simulation time 638774898 ps
CPU time 5.27 seconds
Started Jun 10 05:47:57 PM PDT 24
Finished Jun 10 05:48:02 PM PDT 24
Peak memory 218052 kb
Host smart-c62cbc30-1824-41f7-8ea2-ddcb1db9f257
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670270562 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_smoke
.3670270562
Directory /workspace/15.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_failure.1923861018
Short name T314
Test name
Test status
Simulation time 1317635932 ps
CPU time 63.68 seconds
Started Jun 10 05:47:54 PM PDT 24
Finished Jun 10 05:48:58 PM PDT 24
Peak memory 267800 kb
Host smart-c0a429ae-dbe8-4aa8-a9a6-489f534480b7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923861018 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jt
ag_state_failure.1923861018
Directory /workspace/15.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_post_trans.3935045113
Short name T450
Test name
Test status
Simulation time 9175665785 ps
CPU time 15.38 seconds
Started Jun 10 05:47:56 PM PDT 24
Finished Jun 10 05:48:12 PM PDT 24
Peak memory 249728 kb
Host smart-c44fdd04-0749-4074-ab69-8fee8cacba45
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935045113 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl
_jtag_state_post_trans.3935045113
Directory /workspace/15.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_prog_failure.2332874382
Short name T521
Test name
Test status
Simulation time 89658702 ps
CPU time 3.17 seconds
Started Jun 10 05:47:57 PM PDT 24
Finished Jun 10 05:48:00 PM PDT 24
Peak memory 218708 kb
Host smart-e927a38a-5428-4091-ae73-159930b3622c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332874382 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_prog_failure.2332874382
Directory /workspace/15.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_mubi.1470038617
Short name T636
Test name
Test status
Simulation time 428617815 ps
CPU time 15.03 seconds
Started Jun 10 05:47:54 PM PDT 24
Finished Jun 10 05:48:10 PM PDT 24
Peak memory 226548 kb
Host smart-01ff806a-8503-4517-872b-5f406db0cc7d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470038617 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_mubi.1470038617
Directory /workspace/15.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_digest.2195683395
Short name T591
Test name
Test status
Simulation time 403091673 ps
CPU time 11.04 seconds
Started Jun 10 05:47:56 PM PDT 24
Finished Jun 10 05:48:07 PM PDT 24
Peak memory 218756 kb
Host smart-ca7cebc7-db77-4284-8c3a-769b5f067ec3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195683395 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_d
igest.2195683395
Directory /workspace/15.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_mux.1618308494
Short name T59
Test name
Test status
Simulation time 3821176567 ps
CPU time 7.99 seconds
Started Jun 10 05:47:58 PM PDT 24
Finished Jun 10 05:48:06 PM PDT 24
Peak memory 226576 kb
Host smart-388f2095-4627-47a6-967e-d36fefa8ea5a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618308494 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_mux.
1618308494
Directory /workspace/15.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/15.lc_ctrl_smoke.3479224133
Short name T709
Test name
Test status
Simulation time 354911922 ps
CPU time 2.89 seconds
Started Jun 10 05:47:56 PM PDT 24
Finished Jun 10 05:47:59 PM PDT 24
Peak memory 218180 kb
Host smart-88b0c35a-4bff-4dde-ab3d-500e790816bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479224133 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_smoke.3479224133
Directory /workspace/15.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_failure.1859651271
Short name T543
Test name
Test status
Simulation time 2617996563 ps
CPU time 27.69 seconds
Started Jun 10 05:47:56 PM PDT 24
Finished Jun 10 05:48:24 PM PDT 24
Peak memory 251604 kb
Host smart-2778e8b8-7c4a-4d27-a06c-c858f8beb52a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1859651271 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_failure.1859651271
Directory /workspace/15.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_post_trans.1475876088
Short name T174
Test name
Test status
Simulation time 248902846 ps
CPU time 3.72 seconds
Started Jun 10 05:47:56 PM PDT 24
Finished Jun 10 05:48:00 PM PDT 24
Peak memory 226760 kb
Host smart-0c681f8c-9226-4173-b5f8-271721e843a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475876088 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_post_trans.1475876088
Directory /workspace/15.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all.2714310332
Short name T188
Test name
Test status
Simulation time 6158501526 ps
CPU time 237.81 seconds
Started Jun 10 05:47:55 PM PDT 24
Finished Jun 10 05:51:53 PM PDT 24
Peak memory 269672 kb
Host smart-3576b965-ca1f-4ee5-9981-ca066f284390
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714310332 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.lc_ctrl_stress_all.2714310332
Directory /workspace/15.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.lc_ctrl_volatile_unlock_smoke.1952706523
Short name T488
Test name
Test status
Simulation time 28956231 ps
CPU time 0.81 seconds
Started Jun 10 05:47:56 PM PDT 24
Finished Jun 10 05:47:58 PM PDT 24
Peak memory 209392 kb
Host smart-619fa414-8e63-44b7-9a40-820fd215bb70
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952706523 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_c
trl_volatile_unlock_smoke.1952706523
Directory /workspace/15.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_alert_test.2838758789
Short name T396
Test name
Test status
Simulation time 59992686 ps
CPU time 1.1 seconds
Started Jun 10 05:48:05 PM PDT 24
Finished Jun 10 05:48:07 PM PDT 24
Peak memory 209388 kb
Host smart-19ff0215-a8e9-4f27-b0cf-13218f4e9273
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838758789 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_alert_test.2838758789
Directory /workspace/16.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.lc_ctrl_errors.776059386
Short name T227
Test name
Test status
Simulation time 751237227 ps
CPU time 11.19 seconds
Started Jun 10 05:47:57 PM PDT 24
Finished Jun 10 05:48:08 PM PDT 24
Peak memory 218596 kb
Host smart-0db3f9db-e530-412c-90a4-3042bc760b5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776059386 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_errors.776059386
Directory /workspace/16.lc_ctrl_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_access.1239806095
Short name T181
Test name
Test status
Simulation time 578597728 ps
CPU time 14.89 seconds
Started Jun 10 05:48:00 PM PDT 24
Finished Jun 10 05:48:15 PM PDT 24
Peak memory 217784 kb
Host smart-8535eb17-d1e3-4f74-8e62-30fada0eb104
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239806095 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_access.1239806095
Directory /workspace/16.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_errors.1025066191
Short name T263
Test name
Test status
Simulation time 12667303732 ps
CPU time 84.03 seconds
Started Jun 10 05:47:58 PM PDT 24
Finished Jun 10 05:49:23 PM PDT 24
Peak memory 219252 kb
Host smart-eb06b648-5e36-4e85-acd7-0cdc7e6ae64c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025066191 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_e
rrors.1025066191
Directory /workspace/16.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_prog_failure.1348592866
Short name T412
Test name
Test status
Simulation time 3249406967 ps
CPU time 13.62 seconds
Started Jun 10 05:47:59 PM PDT 24
Finished Jun 10 05:48:13 PM PDT 24
Peak memory 219452 kb
Host smart-620f556f-a472-4387-8957-0b7cb6d98d96
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348592866 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jta
g_prog_failure.1348592866
Directory /workspace/16.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_smoke.1309872461
Short name T686
Test name
Test status
Simulation time 741718863 ps
CPU time 1.99 seconds
Started Jun 10 05:47:59 PM PDT 24
Finished Jun 10 05:48:02 PM PDT 24
Peak memory 218232 kb
Host smart-2fdd1cde-9100-418c-b393-d519befe5140
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309872461 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_smoke
.1309872461
Directory /workspace/16.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_failure.1944881725
Short name T18
Test name
Test status
Simulation time 4072235263 ps
CPU time 42.92 seconds
Started Jun 10 05:48:00 PM PDT 24
Finished Jun 10 05:48:43 PM PDT 24
Peak memory 273200 kb
Host smart-dc4e0b39-6705-468d-bf17-ba4a2eb62293
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944881725 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jt
ag_state_failure.1944881725
Directory /workspace/16.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_post_trans.2063157044
Short name T635
Test name
Test status
Simulation time 1327933585 ps
CPU time 16.53 seconds
Started Jun 10 05:48:00 PM PDT 24
Finished Jun 10 05:48:17 PM PDT 24
Peak memory 251428 kb
Host smart-fea0dfd1-aaa4-47d7-974c-ad2d0aa5992c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063157044 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl
_jtag_state_post_trans.2063157044
Directory /workspace/16.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_prog_failure.621535519
Short name T279
Test name
Test status
Simulation time 52407810 ps
CPU time 2.31 seconds
Started Jun 10 05:48:01 PM PDT 24
Finished Jun 10 05:48:03 PM PDT 24
Peak memory 222560 kb
Host smart-abc10dce-862a-4574-ade3-d91deea32717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621535519 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_prog_failure.621535519
Directory /workspace/16.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_mubi.3643422194
Short name T578
Test name
Test status
Simulation time 898337007 ps
CPU time 12.12 seconds
Started Jun 10 05:48:05 PM PDT 24
Finished Jun 10 05:48:18 PM PDT 24
Peak memory 218808 kb
Host smart-69cb3ad2-0ab8-4231-9f38-5254e7682dc2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643422194 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_mubi.3643422194
Directory /workspace/16.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_digest.1228387345
Short name T558
Test name
Test status
Simulation time 181566360 ps
CPU time 7.89 seconds
Started Jun 10 05:48:02 PM PDT 24
Finished Jun 10 05:48:10 PM PDT 24
Peak memory 226056 kb
Host smart-6c23dca1-1b0e-4cca-aac3-4bbd8610ed48
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228387345 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_d
igest.1228387345
Directory /workspace/16.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_mux.1476376036
Short name T666
Test name
Test status
Simulation time 3458428758 ps
CPU time 9.68 seconds
Started Jun 10 05:48:02 PM PDT 24
Finished Jun 10 05:48:12 PM PDT 24
Peak memory 218816 kb
Host smart-9b78263d-6597-4e77-a06a-76fef5638644
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476376036 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_mux.
1476376036
Directory /workspace/16.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/16.lc_ctrl_security_escalation.2534977241
Short name T165
Test name
Test status
Simulation time 201033173 ps
CPU time 7 seconds
Started Jun 10 05:48:04 PM PDT 24
Finished Jun 10 05:48:11 PM PDT 24
Peak memory 225440 kb
Host smart-8d25ff00-0218-4a9c-ba68-e09519414554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534977241 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_security_escalation.2534977241
Directory /workspace/16.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/16.lc_ctrl_smoke.1815095347
Short name T659
Test name
Test status
Simulation time 67657706 ps
CPU time 1.47 seconds
Started Jun 10 05:48:05 PM PDT 24
Finished Jun 10 05:48:07 PM PDT 24
Peak memory 214256 kb
Host smart-942055a6-b09d-4278-bfff-913c32c56290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815095347 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_smoke.1815095347
Directory /workspace/16.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_failure.1881593620
Short name T825
Test name
Test status
Simulation time 328163124 ps
CPU time 25.23 seconds
Started Jun 10 05:48:01 PM PDT 24
Finished Jun 10 05:48:27 PM PDT 24
Peak memory 251404 kb
Host smart-75856499-efac-4557-a8ff-b3a64a6d89c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1881593620 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_failure.1881593620
Directory /workspace/16.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_post_trans.2680826504
Short name T449
Test name
Test status
Simulation time 562626846 ps
CPU time 8.92 seconds
Started Jun 10 05:48:01 PM PDT 24
Finished Jun 10 05:48:10 PM PDT 24
Peak memory 251372 kb
Host smart-76160bef-65de-46d0-8b12-777b0395ece8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680826504 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_post_trans.2680826504
Directory /workspace/16.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_stress_all.3305908800
Short name T650
Test name
Test status
Simulation time 17067711651 ps
CPU time 109.24 seconds
Started Jun 10 05:48:05 PM PDT 24
Finished Jun 10 05:49:55 PM PDT 24
Peak memory 284016 kb
Host smart-c2ec832a-dc0b-459c-9e4d-83345dc53e4d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305908800 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.lc_ctrl_stress_all.3305908800
Directory /workspace/16.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.lc_ctrl_stress_all_with_rand_reset.3221165984
Short name T497
Test name
Test status
Simulation time 12861512428 ps
CPU time 315.38 seconds
Started Jun 10 05:48:02 PM PDT 24
Finished Jun 10 05:53:18 PM PDT 24
Peak memory 513852 kb
Host smart-3aaea576-a8a7-414f-b64e-82d5b11c385f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3221165984 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_stress_all_with_rand_reset.3221165984
Directory /workspace/16.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.lc_ctrl_volatile_unlock_smoke.1070295985
Short name T36
Test name
Test status
Simulation time 37510274 ps
CPU time 1.01 seconds
Started Jun 10 05:48:02 PM PDT 24
Finished Jun 10 05:48:04 PM PDT 24
Peak memory 212444 kb
Host smart-1216da4b-0e85-48e9-84b1-f07bb1e4ccb1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070295985 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_c
trl_volatile_unlock_smoke.1070295985
Directory /workspace/16.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_alert_test.3820661849
Short name T575
Test name
Test status
Simulation time 30901420 ps
CPU time 0.95 seconds
Started Jun 10 05:48:03 PM PDT 24
Finished Jun 10 05:48:04 PM PDT 24
Peak memory 209380 kb
Host smart-70964b27-8806-4be3-abcc-5df814baa11f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820661849 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_alert_test.3820661849
Directory /workspace/17.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.lc_ctrl_errors.3671076438
Short name T763
Test name
Test status
Simulation time 544704802 ps
CPU time 15.18 seconds
Started Jun 10 05:48:05 PM PDT 24
Finished Jun 10 05:48:21 PM PDT 24
Peak memory 218632 kb
Host smart-8d2f3ac3-0bbc-42f5-af11-c3215d0db7a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671076438 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_errors.3671076438
Directory /workspace/17.lc_ctrl_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_access.2265741249
Short name T362
Test name
Test status
Simulation time 340021477 ps
CPU time 8.35 seconds
Started Jun 10 05:48:05 PM PDT 24
Finished Jun 10 05:48:13 PM PDT 24
Peak memory 217740 kb
Host smart-36a01bb4-2d0e-4ef2-a5b4-fd14aec4c302
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265741249 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_access.2265741249
Directory /workspace/17.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_errors.2206328329
Short name T280
Test name
Test status
Simulation time 10468810226 ps
CPU time 67.79 seconds
Started Jun 10 05:48:05 PM PDT 24
Finished Jun 10 05:49:13 PM PDT 24
Peak memory 219464 kb
Host smart-1b49c9b2-132c-4d1a-a21e-eea787baca52
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206328329 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_e
rrors.2206328329
Directory /workspace/17.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_prog_failure.323977341
Short name T175
Test name
Test status
Simulation time 870736198 ps
CPU time 4.16 seconds
Started Jun 10 05:48:05 PM PDT 24
Finished Jun 10 05:48:10 PM PDT 24
Peak memory 223332 kb
Host smart-2b078858-fa92-427f-ad3d-a3e3afc5b18a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323977341 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag
_prog_failure.323977341
Directory /workspace/17.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_smoke.352658501
Short name T86
Test name
Test status
Simulation time 312255089 ps
CPU time 2.74 seconds
Started Jun 10 05:48:05 PM PDT 24
Finished Jun 10 05:48:08 PM PDT 24
Peak memory 218208 kb
Host smart-4915fe4f-409e-4ce4-bb1e-16441246c93e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352658501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_smoke.
352658501
Directory /workspace/17.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_failure.3794770707
Short name T284
Test name
Test status
Simulation time 14993436512 ps
CPU time 78.82 seconds
Started Jun 10 05:48:06 PM PDT 24
Finished Jun 10 05:49:25 PM PDT 24
Peak memory 281956 kb
Host smart-2bde23e9-ac3d-4ad0-b90a-45932576600e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794770707 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jt
ag_state_failure.3794770707
Directory /workspace/17.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_post_trans.3348650578
Short name T726
Test name
Test status
Simulation time 418130383 ps
CPU time 14.52 seconds
Started Jun 10 05:48:08 PM PDT 24
Finished Jun 10 05:48:23 PM PDT 24
Peak memory 226840 kb
Host smart-a0c3e7a9-e76e-4672-bcd1-556f0a5e2c48
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348650578 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl
_jtag_state_post_trans.3348650578
Directory /workspace/17.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_prog_failure.592038165
Short name T325
Test name
Test status
Simulation time 70420863 ps
CPU time 1.55 seconds
Started Jun 10 05:48:00 PM PDT 24
Finished Jun 10 05:48:02 PM PDT 24
Peak memory 222180 kb
Host smart-1385b316-d314-4dd0-8996-846aff50f8b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592038165 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_prog_failure.592038165
Directory /workspace/17.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_mubi.2805289930
Short name T229
Test name
Test status
Simulation time 300726737 ps
CPU time 10.95 seconds
Started Jun 10 05:48:05 PM PDT 24
Finished Jun 10 05:48:16 PM PDT 24
Peak memory 219396 kb
Host smart-b761ee2b-9a1e-451e-a2d6-75b40379949d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805289930 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_mubi.2805289930
Directory /workspace/17.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_digest.314678809
Short name T533
Test name
Test status
Simulation time 2139284360 ps
CPU time 15.69 seconds
Started Jun 10 05:48:04 PM PDT 24
Finished Jun 10 05:48:20 PM PDT 24
Peak memory 218736 kb
Host smart-e95284a5-73ba-4f29-88ec-9a4350c7a46c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314678809 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_di
gest.314678809
Directory /workspace/17.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_mux.2765338947
Short name T317
Test name
Test status
Simulation time 5774291801 ps
CPU time 7.21 seconds
Started Jun 10 05:48:06 PM PDT 24
Finished Jun 10 05:48:13 PM PDT 24
Peak memory 218748 kb
Host smart-ccbe56a7-8c59-4404-b09b-4b9a0e52f05a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765338947 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_mux.
2765338947
Directory /workspace/17.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/17.lc_ctrl_smoke.585265527
Short name T460
Test name
Test status
Simulation time 207176989 ps
CPU time 4.28 seconds
Started Jun 10 05:48:01 PM PDT 24
Finished Jun 10 05:48:05 PM PDT 24
Peak memory 224136 kb
Host smart-1a50d010-b5f0-435e-9171-786ea0213cc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=585265527 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_smoke.585265527
Directory /workspace/17.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_failure.4141744982
Short name T349
Test name
Test status
Simulation time 416720427 ps
CPU time 22.61 seconds
Started Jun 10 05:48:04 PM PDT 24
Finished Jun 10 05:48:27 PM PDT 24
Peak memory 251360 kb
Host smart-01c9e4d2-0a91-403c-b91c-091fc8bbedc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141744982 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_failure.4141744982
Directory /workspace/17.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_post_trans.4232773174
Short name T256
Test name
Test status
Simulation time 56419682 ps
CPU time 2.95 seconds
Started Jun 10 05:48:05 PM PDT 24
Finished Jun 10 05:48:09 PM PDT 24
Peak memory 226784 kb
Host smart-fe739b6b-466a-4cdb-be3c-b702974f6eab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232773174 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_post_trans.4232773174
Directory /workspace/17.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all.3681222231
Short name T328
Test name
Test status
Simulation time 14896581646 ps
CPU time 56.64 seconds
Started Jun 10 05:48:05 PM PDT 24
Finished Jun 10 05:49:02 PM PDT 24
Peak memory 251088 kb
Host smart-07b7be94-be29-4464-986e-ea4fc0f560ae
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681222231 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.lc_ctrl_stress_all.3681222231
Directory /workspace/17.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all_with_rand_reset.243595467
Short name T147
Test name
Test status
Simulation time 184873913483 ps
CPU time 395.83 seconds
Started Jun 10 05:48:05 PM PDT 24
Finished Jun 10 05:54:41 PM PDT 24
Peak memory 284356 kb
Host smart-f939d1aa-17f9-4007-91c6-f0760a22bbb2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=243595467 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_stress_all_with_rand_reset.243595467
Directory /workspace/17.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.lc_ctrl_volatile_unlock_smoke.2777974130
Short name T43
Test name
Test status
Simulation time 16399821 ps
CPU time 0.99 seconds
Started Jun 10 05:47:59 PM PDT 24
Finished Jun 10 05:48:01 PM PDT 24
Peak memory 209368 kb
Host smart-f958ef0f-0058-40ed-bd31-938ecab0c811
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777974130 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_c
trl_volatile_unlock_smoke.2777974130
Directory /workspace/17.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_alert_test.2183702730
Short name T653
Test name
Test status
Simulation time 12255743 ps
CPU time 0.87 seconds
Started Jun 10 05:48:09 PM PDT 24
Finished Jun 10 05:48:11 PM PDT 24
Peak memory 209280 kb
Host smart-2d6dccd4-df4c-41f5-8a22-5bd0ddf56493
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183702730 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_alert_test.2183702730
Directory /workspace/18.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.lc_ctrl_errors.1662925924
Short name T637
Test name
Test status
Simulation time 974850965 ps
CPU time 8.41 seconds
Started Jun 10 05:48:12 PM PDT 24
Finished Jun 10 05:48:21 PM PDT 24
Peak memory 218640 kb
Host smart-d766e2bd-0f0e-47da-9631-9a338e424d54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662925924 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_errors.1662925924
Directory /workspace/18.lc_ctrl_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_access.3812862376
Short name T361
Test name
Test status
Simulation time 649430413 ps
CPU time 15.34 seconds
Started Jun 10 05:48:10 PM PDT 24
Finished Jun 10 05:48:25 PM PDT 24
Peak memory 217972 kb
Host smart-c47ee426-e51d-42d7-8f24-ba9f4a002574
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812862376 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_access.3812862376
Directory /workspace/18.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_errors.666920347
Short name T576
Test name
Test status
Simulation time 6766957160 ps
CPU time 36.9 seconds
Started Jun 10 05:48:12 PM PDT 24
Finished Jun 10 05:48:49 PM PDT 24
Peak memory 226612 kb
Host smart-f6fd0a63-6815-4b67-94b1-fedc856a5a13
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666920347 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_er
rors.666920347
Directory /workspace/18.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_prog_failure.2301418507
Short name T335
Test name
Test status
Simulation time 20020901963 ps
CPU time 31.12 seconds
Started Jun 10 05:48:15 PM PDT 24
Finished Jun 10 05:48:47 PM PDT 24
Peak memory 226600 kb
Host smart-edbbd407-6fb4-4778-8be0-73c3a08939cf
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301418507 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jta
g_prog_failure.2301418507
Directory /workspace/18.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_smoke.2568201252
Short name T238
Test name
Test status
Simulation time 795077198 ps
CPU time 6.17 seconds
Started Jun 10 05:48:12 PM PDT 24
Finished Jun 10 05:48:18 PM PDT 24
Peak memory 218196 kb
Host smart-1d46ea7c-267d-4155-a1d5-c323639691b7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568201252 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_smoke
.2568201252
Directory /workspace/18.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_failure.4005137501
Short name T818
Test name
Test status
Simulation time 1871517832 ps
CPU time 41.73 seconds
Started Jun 10 05:48:08 PM PDT 24
Finished Jun 10 05:48:50 PM PDT 24
Peak memory 254428 kb
Host smart-7e2d7e11-d5f9-471e-b0ae-d52b1c9b6ea1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005137501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jt
ag_state_failure.4005137501
Directory /workspace/18.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_post_trans.1014351671
Short name T159
Test name
Test status
Simulation time 2173541624 ps
CPU time 9.29 seconds
Started Jun 10 05:48:12 PM PDT 24
Finished Jun 10 05:48:22 PM PDT 24
Peak memory 226916 kb
Host smart-034451c0-9a45-4fa3-b2e3-0533245af9fe
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014351671 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl
_jtag_state_post_trans.1014351671
Directory /workspace/18.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_prog_failure.292297581
Short name T667
Test name
Test status
Simulation time 27356562 ps
CPU time 1.81 seconds
Started Jun 10 05:48:10 PM PDT 24
Finished Jun 10 05:48:13 PM PDT 24
Peak memory 218684 kb
Host smart-53746c33-0f08-452f-b2ce-01dd02d88bf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292297581 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_prog_failure.292297581
Directory /workspace/18.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_mubi.426234602
Short name T364
Test name
Test status
Simulation time 1427105673 ps
CPU time 14.12 seconds
Started Jun 10 05:48:09 PM PDT 24
Finished Jun 10 05:48:24 PM PDT 24
Peak memory 219364 kb
Host smart-05dc4bf0-94e2-4f48-b0c6-126585cfc5cd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426234602 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_mubi.426234602
Directory /workspace/18.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_digest.1419256569
Short name T493
Test name
Test status
Simulation time 277395724 ps
CPU time 10.01 seconds
Started Jun 10 05:48:11 PM PDT 24
Finished Jun 10 05:48:22 PM PDT 24
Peak memory 218736 kb
Host smart-94838390-a72b-401f-a464-aecbf3697707
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419256569 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_d
igest.1419256569
Directory /workspace/18.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_mux.2884923637
Short name T863
Test name
Test status
Simulation time 629722204 ps
CPU time 11.47 seconds
Started Jun 10 05:48:10 PM PDT 24
Finished Jun 10 05:48:22 PM PDT 24
Peak memory 218720 kb
Host smart-90f95924-c6f0-41f9-8940-4832bf3e4761
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884923637 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_mux.
2884923637
Directory /workspace/18.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/18.lc_ctrl_security_escalation.2039986749
Short name T351
Test name
Test status
Simulation time 356502368 ps
CPU time 8.81 seconds
Started Jun 10 05:48:12 PM PDT 24
Finished Jun 10 05:48:21 PM PDT 24
Peak memory 225428 kb
Host smart-a2ee1fe3-e26a-482c-b9a5-cebc75e2e9e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039986749 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_security_escalation.2039986749
Directory /workspace/18.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/18.lc_ctrl_smoke.2002930430
Short name T517
Test name
Test status
Simulation time 275725846 ps
CPU time 3.22 seconds
Started Jun 10 05:48:04 PM PDT 24
Finished Jun 10 05:48:08 PM PDT 24
Peak memory 218224 kb
Host smart-7d9e4ff3-d795-4a86-964a-84c67a9e53ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002930430 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_smoke.2002930430
Directory /workspace/18.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_failure.2106729125
Short name T426
Test name
Test status
Simulation time 321217137 ps
CPU time 22.53 seconds
Started Jun 10 05:48:12 PM PDT 24
Finished Jun 10 05:48:35 PM PDT 24
Peak memory 251444 kb
Host smart-ff945c85-1b83-4b84-8c54-af1b5095e792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106729125 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_failure.2106729125
Directory /workspace/18.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_post_trans.488253454
Short name T657
Test name
Test status
Simulation time 292054901 ps
CPU time 7.43 seconds
Started Jun 10 05:48:11 PM PDT 24
Finished Jun 10 05:48:19 PM PDT 24
Peak memory 250832 kb
Host smart-39633c84-fb7d-454e-8b2d-ebcaf7530afd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488253454 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_post_trans.488253454
Directory /workspace/18.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all.589242216
Short name T162
Test name
Test status
Simulation time 10940758202 ps
CPU time 82.03 seconds
Started Jun 10 05:48:10 PM PDT 24
Finished Jun 10 05:49:33 PM PDT 24
Peak memory 251492 kb
Host smart-fc0ed616-177d-4036-b940-ea2ae33f8391
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589242216 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.lc_ctrl_stress_all.589242216
Directory /workspace/18.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.lc_ctrl_volatile_unlock_smoke.308249439
Short name T305
Test name
Test status
Simulation time 64142921 ps
CPU time 1.06 seconds
Started Jun 10 05:48:13 PM PDT 24
Finished Jun 10 05:48:15 PM PDT 24
Peak memory 212368 kb
Host smart-7edc9db7-cafd-43ba-adca-215d28926933
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308249439 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ct
rl_volatile_unlock_smoke.308249439
Directory /workspace/18.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_alert_test.2551149977
Short name T394
Test name
Test status
Simulation time 39740709 ps
CPU time 0.95 seconds
Started Jun 10 05:48:18 PM PDT 24
Finished Jun 10 05:48:19 PM PDT 24
Peak memory 209472 kb
Host smart-4f224bec-201e-490a-9756-6b3d0eee5c50
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551149977 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_alert_test.2551149977
Directory /workspace/19.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.lc_ctrl_errors.2500251373
Short name T819
Test name
Test status
Simulation time 171056085 ps
CPU time 8.59 seconds
Started Jun 10 05:48:19 PM PDT 24
Finished Jun 10 05:48:28 PM PDT 24
Peak memory 218704 kb
Host smart-b577780f-a768-474c-bfc6-4257e8202c0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2500251373 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_errors.2500251373
Directory /workspace/19.lc_ctrl_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_access.1297682965
Short name T457
Test name
Test status
Simulation time 593724975 ps
CPU time 15.52 seconds
Started Jun 10 05:48:13 PM PDT 24
Finished Jun 10 05:48:29 PM PDT 24
Peak memory 217908 kb
Host smart-42b6b336-eb92-47c5-a8e0-374296d483f5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297682965 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_access.1297682965
Directory /workspace/19.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_errors.3221684774
Short name T48
Test name
Test status
Simulation time 3320798260 ps
CPU time 89.3 seconds
Started Jun 10 05:48:11 PM PDT 24
Finished Jun 10 05:49:41 PM PDT 24
Peak memory 220740 kb
Host smart-4b05db1c-7d93-4e08-baa9-3f237ffe638c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221684774 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_e
rrors.3221684774
Directory /workspace/19.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_prog_failure.2117488310
Short name T604
Test name
Test status
Simulation time 939087513 ps
CPU time 7.05 seconds
Started Jun 10 05:48:18 PM PDT 24
Finished Jun 10 05:48:26 PM PDT 24
Peak memory 223348 kb
Host smart-550f2eea-aad6-4ca3-9767-74c8b397f0ab
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117488310 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jta
g_prog_failure.2117488310
Directory /workspace/19.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_smoke.1007046249
Short name T750
Test name
Test status
Simulation time 604234524 ps
CPU time 4.77 seconds
Started Jun 10 05:48:15 PM PDT 24
Finished Jun 10 05:48:21 PM PDT 24
Peak memory 218340 kb
Host smart-3d8dff2f-ca16-4b0d-b44c-e5351eb1041f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007046249 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_smoke
.1007046249
Directory /workspace/19.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_failure.2328216110
Short name T5
Test name
Test status
Simulation time 1573930181 ps
CPU time 39.24 seconds
Started Jun 10 05:48:19 PM PDT 24
Finished Jun 10 05:48:59 PM PDT 24
Peak memory 267756 kb
Host smart-84450f49-867b-4237-b390-37842cee4006
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328216110 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jt
ag_state_failure.2328216110
Directory /workspace/19.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_post_trans.2982911265
Short name T330
Test name
Test status
Simulation time 842056772 ps
CPU time 16.05 seconds
Started Jun 10 05:48:17 PM PDT 24
Finished Jun 10 05:48:33 PM PDT 24
Peak memory 251472 kb
Host smart-6cac6a1f-e630-4b44-ac62-d6f86eea7558
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982911265 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl
_jtag_state_post_trans.2982911265
Directory /workspace/19.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_prog_failure.2448861280
Short name T64
Test name
Test status
Simulation time 18245234 ps
CPU time 1.75 seconds
Started Jun 10 05:48:13 PM PDT 24
Finished Jun 10 05:48:15 PM PDT 24
Peak memory 218672 kb
Host smart-6b995f52-ea61-4409-8eeb-c40ee2594ac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448861280 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_prog_failure.2448861280
Directory /workspace/19.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_mubi.3785448694
Short name T253
Test name
Test status
Simulation time 272518472 ps
CPU time 11.61 seconds
Started Jun 10 05:48:13 PM PDT 24
Finished Jun 10 05:48:25 PM PDT 24
Peak memory 218824 kb
Host smart-0270ff31-30f9-4912-9da2-aac99958b427
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785448694 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_mubi.3785448694
Directory /workspace/19.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_digest.606492804
Short name T479
Test name
Test status
Simulation time 387750187 ps
CPU time 12.25 seconds
Started Jun 10 05:48:19 PM PDT 24
Finished Jun 10 05:48:32 PM PDT 24
Peak memory 226560 kb
Host smart-a0b3a4e2-3ceb-40d4-883d-12ad316a1cd5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606492804 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_di
gest.606492804
Directory /workspace/19.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_mux.2497494640
Short name T169
Test name
Test status
Simulation time 268124811 ps
CPU time 11.54 seconds
Started Jun 10 05:48:13 PM PDT 24
Finished Jun 10 05:48:25 PM PDT 24
Peak memory 218732 kb
Host smart-d3c0270d-7c2f-4ceb-b15e-0b30df92d617
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497494640 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_mux.
2497494640
Directory /workspace/19.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/19.lc_ctrl_security_escalation.3017482638
Short name T685
Test name
Test status
Simulation time 373779954 ps
CPU time 7.76 seconds
Started Jun 10 05:48:11 PM PDT 24
Finished Jun 10 05:48:19 PM PDT 24
Peak memory 225340 kb
Host smart-a6bb1d7c-6213-4e53-bd91-5681aff73f64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017482638 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_security_escalation.3017482638
Directory /workspace/19.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/19.lc_ctrl_smoke.2372864105
Short name T669
Test name
Test status
Simulation time 81878510 ps
CPU time 2.01 seconds
Started Jun 10 05:48:11 PM PDT 24
Finished Jun 10 05:48:14 PM PDT 24
Peak memory 218204 kb
Host smart-cb6b3528-153e-4752-87cb-d301f106de90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372864105 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_smoke.2372864105
Directory /workspace/19.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_failure.3073771445
Short name T459
Test name
Test status
Simulation time 277883849 ps
CPU time 29.79 seconds
Started Jun 10 05:48:16 PM PDT 24
Finished Jun 10 05:48:47 PM PDT 24
Peak memory 251444 kb
Host smart-32d29aab-c181-48d9-9632-a99528003675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073771445 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_failure.3073771445
Directory /workspace/19.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_post_trans.2895617751
Short name T694
Test name
Test status
Simulation time 74716943 ps
CPU time 3.4 seconds
Started Jun 10 05:48:15 PM PDT 24
Finished Jun 10 05:48:19 PM PDT 24
Peak memory 226868 kb
Host smart-beabdf6f-540f-402e-ba36-e475343dcada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895617751 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_post_trans.2895617751
Directory /workspace/19.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all_with_rand_reset.1031159128
Short name T150
Test name
Test status
Simulation time 28412976081 ps
CPU time 950.05 seconds
Started Jun 10 05:48:19 PM PDT 24
Finished Jun 10 06:04:09 PM PDT 24
Peak memory 497372 kb
Host smart-9c453de8-4733-4960-acdb-5bffff5c0695
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1031159128 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_stress_all_with_rand_reset.1031159128
Directory /workspace/19.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.lc_ctrl_volatile_unlock_smoke.48422525
Short name T418
Test name
Test status
Simulation time 45396449 ps
CPU time 1.04 seconds
Started Jun 10 05:48:13 PM PDT 24
Finished Jun 10 05:48:14 PM PDT 24
Peak memory 212460 kb
Host smart-7dbe3fcd-a622-4cab-b4f6-6ee1a514eef5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48422525 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vol
atile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctr
l_volatile_unlock_smoke.48422525
Directory /workspace/19.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_alert_test.2946310391
Short name T687
Test name
Test status
Simulation time 263049686 ps
CPU time 0.99 seconds
Started Jun 10 05:46:45 PM PDT 24
Finished Jun 10 05:46:46 PM PDT 24
Peak memory 209488 kb
Host smart-2fb0bc0d-d570-4b06-9acc-bd95f5e450a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946310391 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_alert_test.2946310391
Directory /workspace/2.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.lc_ctrl_claim_transition_if.1265432982
Short name T515
Test name
Test status
Simulation time 84667775 ps
CPU time 0.83 seconds
Started Jun 10 05:46:43 PM PDT 24
Finished Jun 10 05:46:44 PM PDT 24
Peak memory 209436 kb
Host smart-a9d56be7-06d8-45df-a568-5d3aa7d9a9ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265432982 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_claim_transition_if.1265432982
Directory /workspace/2.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/2.lc_ctrl_errors.2510345221
Short name T60
Test name
Test status
Simulation time 773465929 ps
CPU time 19.43 seconds
Started Jun 10 05:46:39 PM PDT 24
Finished Jun 10 05:46:59 PM PDT 24
Peak memory 218764 kb
Host smart-54b3d745-fbe0-4498-bfb7-f2073fe3158b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510345221 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_errors.2510345221
Directory /workspace/2.lc_ctrl_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_access.835170812
Short name T588
Test name
Test status
Simulation time 1810771071 ps
CPU time 4.07 seconds
Started Jun 10 05:46:45 PM PDT 24
Finished Jun 10 05:46:49 PM PDT 24
Peak memory 217616 kb
Host smart-b7ba44c6-5fec-4b17-a4e2-d460d2cb3a74
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835170812 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_access.835170812
Directory /workspace/2.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_errors.1460055499
Short name T244
Test name
Test status
Simulation time 10628759700 ps
CPU time 74.36 seconds
Started Jun 10 05:46:42 PM PDT 24
Finished Jun 10 05:47:57 PM PDT 24
Peak memory 219504 kb
Host smart-ccc60521-09d3-4eb8-bf5c-6d54c4d07894
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460055499 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_er
rors.1460055499
Directory /workspace/2.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_priority.2832926919
Short name T529
Test name
Test status
Simulation time 1402008126 ps
CPU time 12.54 seconds
Started Jun 10 05:47:38 PM PDT 24
Finished Jun 10 05:47:51 PM PDT 24
Peak memory 218056 kb
Host smart-6c40e99c-c038-47cf-b1d1-adcb77f43fbc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832926919 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_priority.2
832926919
Directory /workspace/2.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_prog_failure.3202377512
Short name T530
Test name
Test status
Simulation time 174119376 ps
CPU time 3.78 seconds
Started Jun 10 05:46:45 PM PDT 24
Finished Jun 10 05:46:49 PM PDT 24
Peak memory 218536 kb
Host smart-620ec504-38e4-49e8-8050-6d6cbb786ab5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202377512 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag
_prog_failure.3202377512
Directory /workspace/2.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_regwen_during_op.2718958096
Short name T6
Test name
Test status
Simulation time 723814261 ps
CPU time 16.22 seconds
Started Jun 10 05:46:42 PM PDT 24
Finished Jun 10 05:46:59 PM PDT 24
Peak memory 218188 kb
Host smart-853db4d5-fbd7-40ab-8f98-3d70cb1d84f6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718958096 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_regwen_during_op.2718958096
Directory /workspace/2.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_smoke.4248831041
Short name T68
Test name
Test status
Simulation time 601736289 ps
CPU time 3.07 seconds
Started Jun 10 05:46:46 PM PDT 24
Finished Jun 10 05:46:49 PM PDT 24
Peak memory 218336 kb
Host smart-4eaa32f1-a79a-4b0a-bcad-33c45a1b8a33
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248831041 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_smoke.
4248831041
Directory /workspace/2.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_failure.4095512127
Short name T498
Test name
Test status
Simulation time 1406468499 ps
CPU time 62.8 seconds
Started Jun 10 05:46:42 PM PDT 24
Finished Jun 10 05:47:46 PM PDT 24
Peak memory 251496 kb
Host smart-38e4df44-e425-4992-802c-8149f3020a20
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095512127 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jta
g_state_failure.4095512127
Directory /workspace/2.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_post_trans.1397809780
Short name T310
Test name
Test status
Simulation time 990567780 ps
CPU time 18.87 seconds
Started Jun 10 05:46:45 PM PDT 24
Finished Jun 10 05:47:05 PM PDT 24
Peak memory 246880 kb
Host smart-af8d2c40-41e1-49fe-81dd-d0825576a520
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397809780 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_state_post_trans.1397809780
Directory /workspace/2.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_prog_failure.3494800834
Short name T612
Test name
Test status
Simulation time 72582716 ps
CPU time 2.97 seconds
Started Jun 10 05:46:37 PM PDT 24
Finished Jun 10 05:46:40 PM PDT 24
Peak memory 223008 kb
Host smart-c3d44269-e49a-48c9-beff-e7bca2d59513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494800834 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_prog_failure.3494800834
Directory /workspace/2.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_regwen_during_op.1006356241
Short name T613
Test name
Test status
Simulation time 1313227421 ps
CPU time 12.77 seconds
Started Jun 10 05:46:44 PM PDT 24
Finished Jun 10 05:46:57 PM PDT 24
Peak memory 214468 kb
Host smart-756f5608-6714-4438-b312-3355785f4565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006356241 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_regwen_during_op.1006356241
Directory /workspace/2.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_mubi.745673269
Short name T403
Test name
Test status
Simulation time 242040404 ps
CPU time 13.15 seconds
Started Jun 10 05:46:44 PM PDT 24
Finished Jun 10 05:46:58 PM PDT 24
Peak memory 226552 kb
Host smart-29ba75c8-d4eb-48df-9582-5f8c1f704e44
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745673269 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_mubi.745673269
Directory /workspace/2.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_digest.2418379535
Short name T622
Test name
Test status
Simulation time 1113007182 ps
CPU time 12.99 seconds
Started Jun 10 05:46:46 PM PDT 24
Finished Jun 10 05:47:00 PM PDT 24
Peak memory 218560 kb
Host smart-f5a28d19-ea8a-4167-ae60-d6dcb543e180
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418379535 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_di
gest.2418379535
Directory /workspace/2.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_mux.2145064949
Short name T602
Test name
Test status
Simulation time 1176982075 ps
CPU time 11.68 seconds
Started Jun 10 05:46:46 PM PDT 24
Finished Jun 10 05:46:58 PM PDT 24
Peak memory 218832 kb
Host smart-79624712-714b-40f8-a98b-a1e3991f95d9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145064949 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_mux.2
145064949
Directory /workspace/2.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/2.lc_ctrl_security_escalation.1935383158
Short name T58
Test name
Test status
Simulation time 337025605 ps
CPU time 10.74 seconds
Started Jun 10 05:46:41 PM PDT 24
Finished Jun 10 05:46:52 PM PDT 24
Peak memory 218688 kb
Host smart-b4999ced-48d4-47c8-967f-fc923b6d1009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935383158 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_security_escalation.1935383158
Directory /workspace/2.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/2.lc_ctrl_smoke.3698529980
Short name T338
Test name
Test status
Simulation time 127341306 ps
CPU time 1.79 seconds
Started Jun 10 05:46:39 PM PDT 24
Finished Jun 10 05:46:41 PM PDT 24
Peak memory 218200 kb
Host smart-6eb4ec94-c9ee-4edc-b2a4-39356dda74c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698529980 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_smoke.3698529980
Directory /workspace/2.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_failure.1176945675
Short name T42
Test name
Test status
Simulation time 728383924 ps
CPU time 33.18 seconds
Started Jun 10 05:46:41 PM PDT 24
Finished Jun 10 05:47:15 PM PDT 24
Peak memory 251448 kb
Host smart-4171c6ff-6916-4a9f-b680-b76b847b9fb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176945675 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_failure.1176945675
Directory /workspace/2.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_post_trans.1094240738
Short name T691
Test name
Test status
Simulation time 345747709 ps
CPU time 7.02 seconds
Started Jun 10 05:46:41 PM PDT 24
Finished Jun 10 05:46:49 PM PDT 24
Peak memory 251396 kb
Host smart-f58d96c7-2c59-402e-abd1-a2f38e132a60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094240738 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_post_trans.1094240738
Directory /workspace/2.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all.1897601095
Short name T644
Test name
Test status
Simulation time 56261903046 ps
CPU time 296.67 seconds
Started Jun 10 05:46:46 PM PDT 24
Finished Jun 10 05:51:43 PM PDT 24
Peak memory 316856 kb
Host smart-d41288e4-6ccb-43c6-9c50-adab49bd3c53
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897601095 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.lc_ctrl_stress_all.1897601095
Directory /workspace/2.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all_with_rand_reset.1339182478
Short name T172
Test name
Test status
Simulation time 222125355710 ps
CPU time 234.14 seconds
Started Jun 10 05:46:42 PM PDT 24
Finished Jun 10 05:50:37 PM PDT 24
Peak memory 259764 kb
Host smart-0c2ebfa3-73ce-4fb9-8d40-3e8a44247474
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1339182478 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_stress_all_with_rand_reset.1339182478
Directory /workspace/2.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.lc_ctrl_volatile_unlock_smoke.248617689
Short name T513
Test name
Test status
Simulation time 14415474 ps
CPU time 1 seconds
Started Jun 10 05:46:40 PM PDT 24
Finished Jun 10 05:46:42 PM PDT 24
Peak memory 218420 kb
Host smart-5bcdf20b-4270-487b-a1ed-004257e51eb0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248617689 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctr
l_volatile_unlock_smoke.248617689
Directory /workspace/2.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_alert_test.2310478667
Short name T91
Test name
Test status
Simulation time 54190152 ps
CPU time 0.92 seconds
Started Jun 10 05:48:17 PM PDT 24
Finished Jun 10 05:48:18 PM PDT 24
Peak memory 209416 kb
Host smart-d82a6e85-09db-4211-9148-e858c76bcd77
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310478667 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_alert_test.2310478667
Directory /workspace/20.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.lc_ctrl_errors.2087318665
Short name T568
Test name
Test status
Simulation time 2339621951 ps
CPU time 12.32 seconds
Started Jun 10 05:48:20 PM PDT 24
Finished Jun 10 05:48:32 PM PDT 24
Peak memory 218812 kb
Host smart-cc72c30c-ee08-4fa2-89d4-866cd0d6adb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087318665 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_errors.2087318665
Directory /workspace/20.lc_ctrl_errors/latest

Test location /workspace/coverage/default/20.lc_ctrl_jtag_access.686854917
Short name T470
Test name
Test status
Simulation time 268960999 ps
CPU time 8.05 seconds
Started Jun 10 05:48:18 PM PDT 24
Finished Jun 10 05:48:26 PM PDT 24
Peak memory 217972 kb
Host smart-e6fece63-721c-4163-80cc-88de3942fbd5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686854917 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_jtag_access.686854917
Directory /workspace/20.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/20.lc_ctrl_prog_failure.3027985392
Short name T509
Test name
Test status
Simulation time 67057673 ps
CPU time 1.53 seconds
Started Jun 10 05:48:17 PM PDT 24
Finished Jun 10 05:48:19 PM PDT 24
Peak memory 218680 kb
Host smart-1299b2ab-b908-4910-8004-76865a074071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027985392 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_prog_failure.3027985392
Directory /workspace/20.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_mubi.2977492555
Short name T218
Test name
Test status
Simulation time 1970450690 ps
CPU time 19.08 seconds
Started Jun 10 05:48:17 PM PDT 24
Finished Jun 10 05:48:37 PM PDT 24
Peak memory 219504 kb
Host smart-9365cb49-2b61-4514-af31-8b628073651f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977492555 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_mubi.2977492555
Directory /workspace/20.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_digest.3576557503
Short name T415
Test name
Test status
Simulation time 3360897032 ps
CPU time 26.61 seconds
Started Jun 10 05:48:18 PM PDT 24
Finished Jun 10 05:48:45 PM PDT 24
Peak memory 219440 kb
Host smart-512f3d46-8259-455d-9709-0f1a018370b8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576557503 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_d
igest.3576557503
Directory /workspace/20.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_mux.2929461268
Short name T259
Test name
Test status
Simulation time 1509568112 ps
CPU time 12.03 seconds
Started Jun 10 05:48:19 PM PDT 24
Finished Jun 10 05:48:32 PM PDT 24
Peak memory 218740 kb
Host smart-7a0c0324-b9c1-41fc-b13d-c3250e58ce92
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929461268 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_mux.
2929461268
Directory /workspace/20.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/20.lc_ctrl_security_escalation.2409640702
Short name T424
Test name
Test status
Simulation time 374701994 ps
CPU time 14.1 seconds
Started Jun 10 05:48:17 PM PDT 24
Finished Jun 10 05:48:31 PM PDT 24
Peak memory 218784 kb
Host smart-63b04320-9914-4c38-9779-cd3ae8123b31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409640702 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_security_escalation.2409640702
Directory /workspace/20.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/20.lc_ctrl_smoke.3644467732
Short name T872
Test name
Test status
Simulation time 106623068 ps
CPU time 1.71 seconds
Started Jun 10 05:48:18 PM PDT 24
Finished Jun 10 05:48:20 PM PDT 24
Peak memory 214664 kb
Host smart-1dcc0585-f192-4e18-bf7b-4888babc1b17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644467732 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_smoke.3644467732
Directory /workspace/20.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_failure.830777093
Short name T382
Test name
Test status
Simulation time 348111097 ps
CPU time 33.21 seconds
Started Jun 10 05:48:21 PM PDT 24
Finished Jun 10 05:48:54 PM PDT 24
Peak memory 251332 kb
Host smart-186f3c7d-af3e-4d20-a144-53b19f4fa4d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830777093 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_failure.830777093
Directory /workspace/20.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_post_trans.92621674
Short name T834
Test name
Test status
Simulation time 55609326 ps
CPU time 9.47 seconds
Started Jun 10 05:48:19 PM PDT 24
Finished Jun 10 05:48:29 PM PDT 24
Peak memory 251432 kb
Host smart-56280a50-a78b-4dd7-959a-596556ea81c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92621674 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_post_trans.92621674
Directory /workspace/20.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/20.lc_ctrl_stress_all.4177122451
Short name T81
Test name
Test status
Simulation time 8669918370 ps
CPU time 152.86 seconds
Started Jun 10 05:48:18 PM PDT 24
Finished Jun 10 05:50:51 PM PDT 24
Peak memory 251492 kb
Host smart-4094a4f4-6e53-4927-88ad-69f0bf748fc6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177122451 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.lc_ctrl_stress_all.4177122451
Directory /workspace/20.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.lc_ctrl_volatile_unlock_smoke.2139389514
Short name T37
Test name
Test status
Simulation time 96171891 ps
CPU time 0.91 seconds
Started Jun 10 05:48:19 PM PDT 24
Finished Jun 10 05:48:20 PM PDT 24
Peak memory 209472 kb
Host smart-b6f711f8-02aa-4e58-817d-3b5e58699f37
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139389514 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_c
trl_volatile_unlock_smoke.2139389514
Directory /workspace/20.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_alert_test.282372352
Short name T580
Test name
Test status
Simulation time 53303195 ps
CPU time 1.35 seconds
Started Jun 10 05:48:28 PM PDT 24
Finished Jun 10 05:48:29 PM PDT 24
Peak memory 209456 kb
Host smart-0c9f50fc-0cf1-4d60-b043-7238a0487139
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282372352 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_alert_test.282372352
Directory /workspace/21.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.lc_ctrl_errors.331733182
Short name T271
Test name
Test status
Simulation time 917067629 ps
CPU time 8.24 seconds
Started Jun 10 05:48:21 PM PDT 24
Finished Jun 10 05:48:30 PM PDT 24
Peak memory 218756 kb
Host smart-c0f65985-9cff-44d3-ba8e-87a108958a25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331733182 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_errors.331733182
Directory /workspace/21.lc_ctrl_errors/latest

Test location /workspace/coverage/default/21.lc_ctrl_jtag_access.721746829
Short name T318
Test name
Test status
Simulation time 661719556 ps
CPU time 3.7 seconds
Started Jun 10 05:48:18 PM PDT 24
Finished Jun 10 05:48:22 PM PDT 24
Peak memory 217608 kb
Host smart-55c85bc8-8170-4959-8273-8d4725c0661b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721746829 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_jtag_access.721746829
Directory /workspace/21.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/21.lc_ctrl_prog_failure.1464073617
Short name T249
Test name
Test status
Simulation time 43038848 ps
CPU time 1.92 seconds
Started Jun 10 05:48:22 PM PDT 24
Finished Jun 10 05:48:24 PM PDT 24
Peak memory 218684 kb
Host smart-b77ba69b-89f8-4e30-8e1f-fae7756c6b7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464073617 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_prog_failure.1464073617
Directory /workspace/21.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_mubi.419923109
Short name T583
Test name
Test status
Simulation time 319605406 ps
CPU time 11.69 seconds
Started Jun 10 05:48:23 PM PDT 24
Finished Jun 10 05:48:35 PM PDT 24
Peak memory 218756 kb
Host smart-c6f3bad5-1a2e-4b93-82fc-bbc74a3bb101
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419923109 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_mubi.419923109
Directory /workspace/21.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_digest.3959187685
Short name T670
Test name
Test status
Simulation time 424223900 ps
CPU time 8.32 seconds
Started Jun 10 05:48:23 PM PDT 24
Finished Jun 10 05:48:32 PM PDT 24
Peak memory 218728 kb
Host smart-1e5b1e59-4d3a-495f-978d-187750c61b30
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959187685 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_d
igest.3959187685
Directory /workspace/21.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_mux.2077051056
Short name T226
Test name
Test status
Simulation time 1284493629 ps
CPU time 8.04 seconds
Started Jun 10 05:48:23 PM PDT 24
Finished Jun 10 05:48:31 PM PDT 24
Peak memory 218680 kb
Host smart-45c2f748-5789-4279-a264-37b6105fc2d1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077051056 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_mux.
2077051056
Directory /workspace/21.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/21.lc_ctrl_security_escalation.3442803141
Short name T414
Test name
Test status
Simulation time 702050910 ps
CPU time 11.66 seconds
Started Jun 10 05:48:19 PM PDT 24
Finished Jun 10 05:48:31 PM PDT 24
Peak memory 226528 kb
Host smart-52207eaa-6e1d-45b9-9a55-adfb755585df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442803141 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_security_escalation.3442803141
Directory /workspace/21.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/21.lc_ctrl_smoke.4124169846
Short name T585
Test name
Test status
Simulation time 64496835 ps
CPU time 1.75 seconds
Started Jun 10 05:48:17 PM PDT 24
Finished Jun 10 05:48:19 PM PDT 24
Peak memory 218144 kb
Host smart-da7721d1-3534-4402-a28d-4d67d41572dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124169846 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_smoke.4124169846
Directory /workspace/21.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_failure.682598534
Short name T707
Test name
Test status
Simulation time 1138356118 ps
CPU time 25.36 seconds
Started Jun 10 05:48:14 PM PDT 24
Finished Jun 10 05:48:40 PM PDT 24
Peak memory 251404 kb
Host smart-6047e395-9a96-44c3-bc9e-cea4b26fbd07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682598534 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_failure.682598534
Directory /workspace/21.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_post_trans.441940009
Short name T331
Test name
Test status
Simulation time 193231020 ps
CPU time 6.84 seconds
Started Jun 10 05:48:21 PM PDT 24
Finished Jun 10 05:48:28 PM PDT 24
Peak memory 250936 kb
Host smart-4fbb047d-77b3-423c-8d29-17ffbf8c6790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441940009 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_post_trans.441940009
Directory /workspace/21.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/21.lc_ctrl_stress_all.2832610305
Short name T526
Test name
Test status
Simulation time 12853303081 ps
CPU time 72.16 seconds
Started Jun 10 05:48:23 PM PDT 24
Finished Jun 10 05:49:35 PM PDT 24
Peak memory 278812 kb
Host smart-17597075-be1b-4351-982d-ba44ddb3c188
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832610305 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.lc_ctrl_stress_all.2832610305
Directory /workspace/21.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.lc_ctrl_volatile_unlock_smoke.143560424
Short name T720
Test name
Test status
Simulation time 12310864 ps
CPU time 0.95 seconds
Started Jun 10 05:48:21 PM PDT 24
Finished Jun 10 05:48:22 PM PDT 24
Peak memory 209284 kb
Host smart-b714da24-e220-46c4-be6a-412f2c157fb7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143560424 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ct
rl_volatile_unlock_smoke.143560424
Directory /workspace/21.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_alert_test.1580433704
Short name T290
Test name
Test status
Simulation time 23032064 ps
CPU time 1.25 seconds
Started Jun 10 05:48:26 PM PDT 24
Finished Jun 10 05:48:27 PM PDT 24
Peak memory 209528 kb
Host smart-2ec70359-3e05-432d-923a-767aad4bf705
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580433704 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_alert_test.1580433704
Directory /workspace/22.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.lc_ctrl_errors.4274424270
Short name T156
Test name
Test status
Simulation time 1771077829 ps
CPU time 19.73 seconds
Started Jun 10 05:48:26 PM PDT 24
Finished Jun 10 05:48:46 PM PDT 24
Peak memory 218712 kb
Host smart-297bb75d-6813-42b3-a4ef-ed7f8f4c0569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274424270 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_errors.4274424270
Directory /workspace/22.lc_ctrl_errors/latest

Test location /workspace/coverage/default/22.lc_ctrl_jtag_access.3263938026
Short name T490
Test name
Test status
Simulation time 263094552 ps
CPU time 8 seconds
Started Jun 10 05:48:27 PM PDT 24
Finished Jun 10 05:48:35 PM PDT 24
Peak memory 217772 kb
Host smart-53a5099b-2d8f-4c10-a0d5-bc638c0aad48
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263938026 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_jtag_access.3263938026
Directory /workspace/22.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/22.lc_ctrl_prog_failure.2313571066
Short name T482
Test name
Test status
Simulation time 72311363 ps
CPU time 1.94 seconds
Started Jun 10 05:48:27 PM PDT 24
Finished Jun 10 05:48:29 PM PDT 24
Peak memory 222480 kb
Host smart-a0d3c53b-d3ec-4fa9-847b-9eff09732aa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313571066 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_prog_failure.2313571066
Directory /workspace/22.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_mubi.1290153921
Short name T473
Test name
Test status
Simulation time 901289549 ps
CPU time 10.18 seconds
Started Jun 10 05:48:28 PM PDT 24
Finished Jun 10 05:48:38 PM PDT 24
Peak memory 226552 kb
Host smart-5f4ac098-91f9-471d-964b-7b1ff107cb63
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290153921 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_mubi.1290153921
Directory /workspace/22.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_digest.3775786669
Short name T789
Test name
Test status
Simulation time 548987372 ps
CPU time 13.85 seconds
Started Jun 10 05:48:26 PM PDT 24
Finished Jun 10 05:48:40 PM PDT 24
Peak memory 226492 kb
Host smart-6bc7e48f-b25d-44e1-9f3e-f0605300b65a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775786669 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_d
igest.3775786669
Directory /workspace/22.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_mux.504574033
Short name T610
Test name
Test status
Simulation time 635256729 ps
CPU time 12.09 seconds
Started Jun 10 05:48:26 PM PDT 24
Finished Jun 10 05:48:38 PM PDT 24
Peak memory 218660 kb
Host smart-107f01b4-7419-4d28-8937-47214d65f9eb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504574033 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_mux.504574033
Directory /workspace/22.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/22.lc_ctrl_security_escalation.1273968380
Short name T855
Test name
Test status
Simulation time 912814750 ps
CPU time 9.58 seconds
Started Jun 10 05:48:27 PM PDT 24
Finished Jun 10 05:48:37 PM PDT 24
Peak memory 226132 kb
Host smart-0341e34c-2fc4-4bdd-984d-1c332f0d3b97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273968380 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_security_escalation.1273968380
Directory /workspace/22.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/22.lc_ctrl_smoke.3099323949
Short name T79
Test name
Test status
Simulation time 55388965 ps
CPU time 3.26 seconds
Started Jun 10 05:48:27 PM PDT 24
Finished Jun 10 05:48:30 PM PDT 24
Peak memory 215480 kb
Host smart-4f0a3810-809f-4e5e-8fde-d649dd0e7043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099323949 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_smoke.3099323949
Directory /workspace/22.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_failure.2433902125
Short name T590
Test name
Test status
Simulation time 1325631459 ps
CPU time 28.73 seconds
Started Jun 10 05:48:27 PM PDT 24
Finished Jun 10 05:48:56 PM PDT 24
Peak memory 251360 kb
Host smart-ce10c50e-e818-4c76-b4be-94264103112c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433902125 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_failure.2433902125
Directory /workspace/22.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_post_trans.3834755018
Short name T251
Test name
Test status
Simulation time 385185437 ps
CPU time 3.77 seconds
Started Jun 10 05:48:27 PM PDT 24
Finished Jun 10 05:48:31 PM PDT 24
Peak memory 226844 kb
Host smart-2d824654-fcbc-47e5-98e4-65bbdddcaae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834755018 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_post_trans.3834755018
Directory /workspace/22.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/22.lc_ctrl_stress_all.1929395295
Short name T746
Test name
Test status
Simulation time 6263833927 ps
CPU time 125.19 seconds
Started Jun 10 05:48:26 PM PDT 24
Finished Jun 10 05:50:31 PM PDT 24
Peak memory 267832 kb
Host smart-f59d78dc-c21f-4648-9112-cc0389f88c88
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929395295 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.lc_ctrl_stress_all.1929395295
Directory /workspace/22.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.lc_ctrl_stress_all_with_rand_reset.1990273655
Short name T82
Test name
Test status
Simulation time 4921114456 ps
CPU time 207.77 seconds
Started Jun 10 05:48:29 PM PDT 24
Finished Jun 10 05:51:57 PM PDT 24
Peak memory 333528 kb
Host smart-8dc15420-dc6f-44a8-9e4d-4567a863f70b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1990273655 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_stress_all_with_rand_reset.1990273655
Directory /workspace/22.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.lc_ctrl_volatile_unlock_smoke.2886839834
Short name T715
Test name
Test status
Simulation time 45227509 ps
CPU time 0.96 seconds
Started Jun 10 05:48:26 PM PDT 24
Finished Jun 10 05:48:28 PM PDT 24
Peak memory 212376 kb
Host smart-1b265820-5077-49b8-a104-612266ecc49d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886839834 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_c
trl_volatile_unlock_smoke.2886839834
Directory /workspace/22.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_alert_test.4229857821
Short name T756
Test name
Test status
Simulation time 96949173 ps
CPU time 1.39 seconds
Started Jun 10 05:48:32 PM PDT 24
Finished Jun 10 05:48:33 PM PDT 24
Peak memory 209472 kb
Host smart-34ad1eb8-7ac6-46c3-8520-a834a11f052f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229857821 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_alert_test.4229857821
Directory /workspace/23.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.lc_ctrl_errors.1865909512
Short name T752
Test name
Test status
Simulation time 2790020482 ps
CPU time 14.28 seconds
Started Jun 10 05:48:37 PM PDT 24
Finished Jun 10 05:48:52 PM PDT 24
Peak memory 219396 kb
Host smart-de82ffbd-b0e8-416c-8b7b-1e81148942d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865909512 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_errors.1865909512
Directory /workspace/23.lc_ctrl_errors/latest

Test location /workspace/coverage/default/23.lc_ctrl_jtag_access.2855963767
Short name T393
Test name
Test status
Simulation time 2108172190 ps
CPU time 14.32 seconds
Started Jun 10 05:48:27 PM PDT 24
Finished Jun 10 05:48:42 PM PDT 24
Peak memory 217892 kb
Host smart-bbf1ae97-51d5-4bd1-9fe8-63aeb68e7603
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855963767 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_jtag_access.2855963767
Directory /workspace/23.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/23.lc_ctrl_prog_failure.1062473105
Short name T745
Test name
Test status
Simulation time 64249841 ps
CPU time 2.93 seconds
Started Jun 10 05:48:26 PM PDT 24
Finished Jun 10 05:48:29 PM PDT 24
Peak memory 218684 kb
Host smart-7656701d-6273-472e-912c-b1c2d83710e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062473105 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_prog_failure.1062473105
Directory /workspace/23.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_mubi.4292575585
Short name T299
Test name
Test status
Simulation time 1286904597 ps
CPU time 10.71 seconds
Started Jun 10 05:48:33 PM PDT 24
Finished Jun 10 05:48:43 PM PDT 24
Peak memory 219396 kb
Host smart-627b29bb-7dd3-43b7-ab23-25befa573c3b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292575585 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_mubi.4292575585
Directory /workspace/23.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_digest.2350147469
Short name T397
Test name
Test status
Simulation time 972969030 ps
CPU time 21.03 seconds
Started Jun 10 05:48:30 PM PDT 24
Finished Jun 10 05:48:52 PM PDT 24
Peak memory 218732 kb
Host smart-fbb389b4-9584-4267-8b59-b7a69d317cac
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350147469 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_d
igest.2350147469
Directory /workspace/23.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_mux.1325812884
Short name T28
Test name
Test status
Simulation time 407046083 ps
CPU time 12.93 seconds
Started Jun 10 05:48:30 PM PDT 24
Finished Jun 10 05:48:43 PM PDT 24
Peak memory 226508 kb
Host smart-e92fb1ea-196e-4ee8-aa2a-82850820aca3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325812884 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_mux.
1325812884
Directory /workspace/23.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/23.lc_ctrl_security_escalation.3907334621
Short name T304
Test name
Test status
Simulation time 1058399318 ps
CPU time 7.85 seconds
Started Jun 10 05:48:28 PM PDT 24
Finished Jun 10 05:48:37 PM PDT 24
Peak memory 218740 kb
Host smart-316816cb-1f58-4782-a3b0-f9bfdfecd2a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907334621 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_security_escalation.3907334621
Directory /workspace/23.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/23.lc_ctrl_smoke.36425449
Short name T61
Test name
Test status
Simulation time 65776900 ps
CPU time 1.65 seconds
Started Jun 10 05:48:25 PM PDT 24
Finished Jun 10 05:48:27 PM PDT 24
Peak memory 214384 kb
Host smart-f4bd8484-a26c-4e58-9ea2-8a2e2aaa18cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36425449 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_smoke.36425449
Directory /workspace/23.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_failure.4026873689
Short name T742
Test name
Test status
Simulation time 2618323000 ps
CPU time 19.26 seconds
Started Jun 10 05:48:29 PM PDT 24
Finished Jun 10 05:48:48 PM PDT 24
Peak memory 251388 kb
Host smart-2a807fd3-6c60-425f-99dc-ddc5ca5fc94a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026873689 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_failure.4026873689
Directory /workspace/23.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_post_trans.499153433
Short name T827
Test name
Test status
Simulation time 218633200 ps
CPU time 6.89 seconds
Started Jun 10 05:48:35 PM PDT 24
Finished Jun 10 05:48:42 PM PDT 24
Peak memory 251016 kb
Host smart-eb07d06e-57ac-4f90-9fc7-88b6da80fcbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499153433 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_post_trans.499153433
Directory /workspace/23.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all.3483327476
Short name T164
Test name
Test status
Simulation time 11075592396 ps
CPU time 222.73 seconds
Started Jun 10 05:48:32 PM PDT 24
Finished Jun 10 05:52:15 PM PDT 24
Peak memory 226596 kb
Host smart-0ffb4ac9-83fb-40ab-970c-5c6418ae5319
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483327476 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.lc_ctrl_stress_all.3483327476
Directory /workspace/23.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all_with_rand_reset.320351790
Short name T151
Test name
Test status
Simulation time 68537364544 ps
CPU time 424.43 seconds
Started Jun 10 05:48:26 PM PDT 24
Finished Jun 10 05:55:31 PM PDT 24
Peak memory 300676 kb
Host smart-4cefaf38-75b9-44cb-8a7e-52f024394608
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=320351790 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_stress_all_with_rand_reset.320351790
Directory /workspace/23.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.lc_ctrl_volatile_unlock_smoke.2086917430
Short name T101
Test name
Test status
Simulation time 80955531 ps
CPU time 0.91 seconds
Started Jun 10 05:48:36 PM PDT 24
Finished Jun 10 05:48:38 PM PDT 24
Peak memory 212376 kb
Host smart-c82d54e5-625d-4fc5-8464-5faad3a76c24
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086917430 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_c
trl_volatile_unlock_smoke.2086917430
Directory /workspace/23.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_alert_test.2356545550
Short name T774
Test name
Test status
Simulation time 42754157 ps
CPU time 0.84 seconds
Started Jun 10 05:48:36 PM PDT 24
Finished Jun 10 05:48:38 PM PDT 24
Peak memory 209048 kb
Host smart-6bbb6a13-3465-46c0-9c76-bd41e9c8d01b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356545550 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_alert_test.2356545550
Directory /workspace/24.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.lc_ctrl_errors.666126804
Short name T788
Test name
Test status
Simulation time 1766473956 ps
CPU time 11.25 seconds
Started Jun 10 05:48:32 PM PDT 24
Finished Jun 10 05:48:43 PM PDT 24
Peak memory 218536 kb
Host smart-c78d7475-d722-4fea-b72f-f30b6eaca717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666126804 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_errors.666126804
Directory /workspace/24.lc_ctrl_errors/latest

Test location /workspace/coverage/default/24.lc_ctrl_jtag_access.1033529668
Short name T11
Test name
Test status
Simulation time 814092600 ps
CPU time 3.05 seconds
Started Jun 10 05:48:32 PM PDT 24
Finished Jun 10 05:48:35 PM PDT 24
Peak memory 217464 kb
Host smart-19e88ddf-bafd-464e-b3e9-b85d5c67243f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033529668 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_jtag_access.1033529668
Directory /workspace/24.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/24.lc_ctrl_prog_failure.3178967438
Short name T815
Test name
Test status
Simulation time 47607520 ps
CPU time 2.91 seconds
Started Jun 10 05:48:29 PM PDT 24
Finished Jun 10 05:48:32 PM PDT 24
Peak memory 222844 kb
Host smart-dc614cd9-ddfd-47e4-9b00-e0f32de2eb85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178967438 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_prog_failure.3178967438
Directory /workspace/24.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_mubi.6522750
Short name T672
Test name
Test status
Simulation time 930808034 ps
CPU time 10.8 seconds
Started Jun 10 05:48:37 PM PDT 24
Finished Jun 10 05:48:48 PM PDT 24
Peak memory 218676 kb
Host smart-f6ca1e06-846d-4207-8ef3-a9fbacad54ac
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6522750 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_mubi.6522750
Directory /workspace/24.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_digest.749909576
Short name T433
Test name
Test status
Simulation time 924064494 ps
CPU time 8.21 seconds
Started Jun 10 05:48:36 PM PDT 24
Finished Jun 10 05:48:45 PM PDT 24
Peak memory 218792 kb
Host smart-bf9d4a5b-3fba-4d94-914f-5394a581ef73
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749909576 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_di
gest.749909576
Directory /workspace/24.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_mux.3828885648
Short name T235
Test name
Test status
Simulation time 463130083 ps
CPU time 9.18 seconds
Started Jun 10 05:48:29 PM PDT 24
Finished Jun 10 05:48:39 PM PDT 24
Peak memory 218676 kb
Host smart-df724f04-fd01-4434-8252-e289b90430c0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828885648 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_mux.
3828885648
Directory /workspace/24.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/24.lc_ctrl_security_escalation.3807674480
Short name T348
Test name
Test status
Simulation time 282154847 ps
CPU time 11.11 seconds
Started Jun 10 05:48:31 PM PDT 24
Finished Jun 10 05:48:43 PM PDT 24
Peak memory 218940 kb
Host smart-5b67561d-f8aa-4b45-ba16-d23331f48b2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807674480 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_security_escalation.3807674480
Directory /workspace/24.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/24.lc_ctrl_smoke.1534602375
Short name T801
Test name
Test status
Simulation time 76615660 ps
CPU time 3.49 seconds
Started Jun 10 05:48:32 PM PDT 24
Finished Jun 10 05:48:36 PM PDT 24
Peak memory 215536 kb
Host smart-c8c06701-29e1-4d98-919c-7727827ea368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534602375 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_smoke.1534602375
Directory /workspace/24.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_failure.4135491995
Short name T496
Test name
Test status
Simulation time 212117038 ps
CPU time 25.49 seconds
Started Jun 10 05:48:31 PM PDT 24
Finished Jun 10 05:48:57 PM PDT 24
Peak memory 251536 kb
Host smart-4b88e495-226d-41c8-90d9-5dcfe982f2c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135491995 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_failure.4135491995
Directory /workspace/24.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_post_trans.2110116565
Short name T421
Test name
Test status
Simulation time 1191899391 ps
CPU time 3.81 seconds
Started Jun 10 05:48:37 PM PDT 24
Finished Jun 10 05:48:41 PM PDT 24
Peak memory 226784 kb
Host smart-6b0792fd-a38e-465f-9c9a-6d87dc6b2edb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110116565 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_post_trans.2110116565
Directory /workspace/24.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all.3293641348
Short name T455
Test name
Test status
Simulation time 6536745563 ps
CPU time 93.81 seconds
Started Jun 10 05:48:30 PM PDT 24
Finished Jun 10 05:50:04 PM PDT 24
Peak memory 226708 kb
Host smart-9286791d-c466-4175-8e91-b34ed887fae3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293641348 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.lc_ctrl_stress_all.3293641348
Directory /workspace/24.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.lc_ctrl_volatile_unlock_smoke.3225509712
Short name T402
Test name
Test status
Simulation time 16760120 ps
CPU time 1.24 seconds
Started Jun 10 05:48:33 PM PDT 24
Finished Jun 10 05:48:34 PM PDT 24
Peak memory 213244 kb
Host smart-76bba3aa-124f-49d9-8e56-7575ced4e244
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225509712 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_c
trl_volatile_unlock_smoke.3225509712
Directory /workspace/24.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_alert_test.1794611690
Short name T295
Test name
Test status
Simulation time 14173549 ps
CPU time 1.05 seconds
Started Jun 10 05:48:40 PM PDT 24
Finished Jun 10 05:48:42 PM PDT 24
Peak memory 209408 kb
Host smart-58ed678e-b44a-4e61-bd4e-5726291be4ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794611690 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_alert_test.1794611690
Directory /workspace/25.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.lc_ctrl_errors.1777855638
Short name T434
Test name
Test status
Simulation time 401994059 ps
CPU time 8.78 seconds
Started Jun 10 05:48:35 PM PDT 24
Finished Jun 10 05:48:44 PM PDT 24
Peak memory 218772 kb
Host smart-3881b641-e50e-446a-9079-227e0fd0c968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777855638 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_errors.1777855638
Directory /workspace/25.lc_ctrl_errors/latest

Test location /workspace/coverage/default/25.lc_ctrl_jtag_access.3356996504
Short name T779
Test name
Test status
Simulation time 398229607 ps
CPU time 11.5 seconds
Started Jun 10 05:48:36 PM PDT 24
Finished Jun 10 05:48:48 PM PDT 24
Peak memory 217804 kb
Host smart-7885841f-2147-4182-9d66-06364d84914a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356996504 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_jtag_access.3356996504
Directory /workspace/25.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/25.lc_ctrl_prog_failure.3418957845
Short name T431
Test name
Test status
Simulation time 36402612 ps
CPU time 2.08 seconds
Started Jun 10 05:48:33 PM PDT 24
Finished Jun 10 05:48:35 PM PDT 24
Peak memory 222512 kb
Host smart-201df731-6d3a-46f7-b233-c9ffd95ecff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418957845 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_prog_failure.3418957845
Directory /workspace/25.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_mubi.2236556032
Short name T368
Test name
Test status
Simulation time 386812095 ps
CPU time 14.72 seconds
Started Jun 10 05:48:36 PM PDT 24
Finished Jun 10 05:48:51 PM PDT 24
Peak memory 226596 kb
Host smart-d38e5d39-a7ea-426a-8ed1-5a41770adc01
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236556032 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_mubi.2236556032
Directory /workspace/25.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_digest.665319462
Short name T369
Test name
Test status
Simulation time 832114845 ps
CPU time 11.85 seconds
Started Jun 10 05:48:39 PM PDT 24
Finished Jun 10 05:48:51 PM PDT 24
Peak memory 226376 kb
Host smart-02b715d0-5b6e-4c3a-8f63-63b8145fb3d4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665319462 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_di
gest.665319462
Directory /workspace/25.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_mux.1630496712
Short name T289
Test name
Test status
Simulation time 1377269164 ps
CPU time 9.09 seconds
Started Jun 10 05:48:40 PM PDT 24
Finished Jun 10 05:48:49 PM PDT 24
Peak memory 225632 kb
Host smart-10b3d05a-a7b6-4345-a86e-f83bce55eb1a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630496712 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_mux.
1630496712
Directory /workspace/25.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/25.lc_ctrl_security_escalation.720426826
Short name T859
Test name
Test status
Simulation time 1455806726 ps
CPU time 8.58 seconds
Started Jun 10 05:48:35 PM PDT 24
Finished Jun 10 05:48:44 PM PDT 24
Peak memory 218760 kb
Host smart-7f210a0a-81cb-4ba1-b718-8e13aa654b25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720426826 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_security_escalation.720426826
Directory /workspace/25.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/25.lc_ctrl_smoke.214482297
Short name T632
Test name
Test status
Simulation time 278754885 ps
CPU time 2.48 seconds
Started Jun 10 05:48:35 PM PDT 24
Finished Jun 10 05:48:38 PM PDT 24
Peak memory 214996 kb
Host smart-c3dede11-bb11-4a56-9e29-b717d165d382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214482297 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_smoke.214482297
Directory /workspace/25.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_failure.1337519112
Short name T722
Test name
Test status
Simulation time 488112694 ps
CPU time 29.41 seconds
Started Jun 10 05:48:36 PM PDT 24
Finished Jun 10 05:49:06 PM PDT 24
Peak memory 251392 kb
Host smart-171a5e38-8ce2-40ed-ba0f-e318aa1d05df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337519112 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_failure.1337519112
Directory /workspace/25.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_post_trans.3767117779
Short name T668
Test name
Test status
Simulation time 305532092 ps
CPU time 7.21 seconds
Started Jun 10 05:48:37 PM PDT 24
Finished Jun 10 05:48:45 PM PDT 24
Peak memory 247540 kb
Host smart-d284b891-6482-47cd-b48d-091860f0b506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767117779 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_post_trans.3767117779
Directory /workspace/25.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/25.lc_ctrl_stress_all.2105831688
Short name T468
Test name
Test status
Simulation time 5342083312 ps
CPU time 62.95 seconds
Started Jun 10 05:48:40 PM PDT 24
Finished Jun 10 05:49:43 PM PDT 24
Peak memory 251652 kb
Host smart-0e9d5d2e-cb1b-48de-93b4-3507b2d832a2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105831688 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.lc_ctrl_stress_all.2105831688
Directory /workspace/25.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.lc_ctrl_volatile_unlock_smoke.720795398
Short name T379
Test name
Test status
Simulation time 18455603 ps
CPU time 1 seconds
Started Jun 10 05:48:36 PM PDT 24
Finished Jun 10 05:48:38 PM PDT 24
Peak memory 213436 kb
Host smart-475bfa1a-11ce-4487-98ab-6d75f70ada9a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720795398 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ct
rl_volatile_unlock_smoke.720795398
Directory /workspace/25.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_alert_test.1297391352
Short name T276
Test name
Test status
Simulation time 21462674 ps
CPU time 1.1 seconds
Started Jun 10 05:48:42 PM PDT 24
Finished Jun 10 05:48:44 PM PDT 24
Peak memory 209396 kb
Host smart-17a78db3-27be-407c-8d6e-4438347df4c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297391352 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_alert_test.1297391352
Directory /workspace/26.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.lc_ctrl_errors.622791138
Short name T711
Test name
Test status
Simulation time 345695900 ps
CPU time 14.81 seconds
Started Jun 10 05:48:39 PM PDT 24
Finished Jun 10 05:48:54 PM PDT 24
Peak memory 218740 kb
Host smart-1e079422-f63c-4ed3-812a-019e51c427c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622791138 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_errors.622791138
Directory /workspace/26.lc_ctrl_errors/latest

Test location /workspace/coverage/default/26.lc_ctrl_jtag_access.3408570157
Short name T425
Test name
Test status
Simulation time 580210205 ps
CPU time 13.73 seconds
Started Jun 10 05:48:39 PM PDT 24
Finished Jun 10 05:48:53 PM PDT 24
Peak memory 217648 kb
Host smart-0c9d03d2-183e-4622-8dc5-80d15d36552f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408570157 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_jtag_access.3408570157
Directory /workspace/26.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/26.lc_ctrl_prog_failure.3845126737
Short name T639
Test name
Test status
Simulation time 33289276 ps
CPU time 1.61 seconds
Started Jun 10 05:48:38 PM PDT 24
Finished Jun 10 05:48:40 PM PDT 24
Peak memory 218680 kb
Host smart-92464a61-220b-43b4-9ab5-98b47bb81f65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845126737 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_prog_failure.3845126737
Directory /workspace/26.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_mubi.1201970797
Short name T315
Test name
Test status
Simulation time 452802930 ps
CPU time 11.05 seconds
Started Jun 10 05:48:39 PM PDT 24
Finished Jun 10 05:48:50 PM PDT 24
Peak memory 218760 kb
Host smart-2abf7bae-fb08-48d5-94f6-a3e7ce97deb1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201970797 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_mubi.1201970797
Directory /workspace/26.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_digest.2086001432
Short name T814
Test name
Test status
Simulation time 326095741 ps
CPU time 14.1 seconds
Started Jun 10 05:48:40 PM PDT 24
Finished Jun 10 05:48:55 PM PDT 24
Peak memory 218756 kb
Host smart-b425c9d9-0373-49ca-9f0f-40fc8f53a8ac
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086001432 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_d
igest.2086001432
Directory /workspace/26.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_mux.2752980206
Short name T767
Test name
Test status
Simulation time 390083826 ps
CPU time 11.28 seconds
Started Jun 10 05:48:40 PM PDT 24
Finished Jun 10 05:48:51 PM PDT 24
Peak memory 226456 kb
Host smart-fc7daa18-d52e-4523-80ed-628aaf200711
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752980206 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_mux.
2752980206
Directory /workspace/26.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/26.lc_ctrl_security_escalation.2898781280
Short name T56
Test name
Test status
Simulation time 332535507 ps
CPU time 11.62 seconds
Started Jun 10 05:48:40 PM PDT 24
Finished Jun 10 05:48:52 PM PDT 24
Peak memory 218788 kb
Host smart-2dd7c583-a549-4509-bad3-f6e43bdc2d2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898781280 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_security_escalation.2898781280
Directory /workspace/26.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/26.lc_ctrl_smoke.417929148
Short name T411
Test name
Test status
Simulation time 185036840 ps
CPU time 3.08 seconds
Started Jun 10 05:48:38 PM PDT 24
Finished Jun 10 05:48:41 PM PDT 24
Peak memory 218160 kb
Host smart-463e3eba-a3fb-4bf3-b58b-d665e513a894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417929148 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_smoke.417929148
Directory /workspace/26.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_failure.3750707569
Short name T326
Test name
Test status
Simulation time 744335422 ps
CPU time 21.95 seconds
Started Jun 10 05:48:37 PM PDT 24
Finished Jun 10 05:49:00 PM PDT 24
Peak memory 251436 kb
Host smart-e936c40d-89b9-4190-af6d-8498dd391cf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750707569 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_failure.3750707569
Directory /workspace/26.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_post_trans.2021824322
Short name T214
Test name
Test status
Simulation time 80326391 ps
CPU time 7.28 seconds
Started Jun 10 05:48:40 PM PDT 24
Finished Jun 10 05:48:47 PM PDT 24
Peak memory 247348 kb
Host smart-fe872eca-9632-4bf8-be59-6f49e03a2729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021824322 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_post_trans.2021824322
Directory /workspace/26.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all.1297495233
Short name T110
Test name
Test status
Simulation time 12996918225 ps
CPU time 133.56 seconds
Started Jun 10 05:48:39 PM PDT 24
Finished Jun 10 05:50:53 PM PDT 24
Peak memory 277572 kb
Host smart-23f4cb2f-43a5-4cc9-97d3-303114e39108
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297495233 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.lc_ctrl_stress_all.1297495233
Directory /workspace/26.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.lc_ctrl_volatile_unlock_smoke.2268838149
Short name T430
Test name
Test status
Simulation time 16725120 ps
CPU time 1.2 seconds
Started Jun 10 05:48:38 PM PDT 24
Finished Jun 10 05:48:39 PM PDT 24
Peak memory 212424 kb
Host smart-0a420abb-3a30-4eae-a8aa-488dc2472f33
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268838149 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_c
trl_volatile_unlock_smoke.2268838149
Directory /workspace/26.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_alert_test.3344808892
Short name T71
Test name
Test status
Simulation time 54752340 ps
CPU time 0.99 seconds
Started Jun 10 05:48:45 PM PDT 24
Finished Jun 10 05:48:46 PM PDT 24
Peak memory 209468 kb
Host smart-f776f473-256a-4a26-ad41-1ef6682da3ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344808892 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_alert_test.3344808892
Directory /workspace/27.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.lc_ctrl_errors.1389970591
Short name T474
Test name
Test status
Simulation time 1087887118 ps
CPU time 11.36 seconds
Started Jun 10 05:48:41 PM PDT 24
Finished Jun 10 05:48:53 PM PDT 24
Peak memory 218788 kb
Host smart-42d0ee8e-ef70-4bf3-85b1-a722bf4790b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389970591 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_errors.1389970591
Directory /workspace/27.lc_ctrl_errors/latest

Test location /workspace/coverage/default/27.lc_ctrl_jtag_access.1308822587
Short name T738
Test name
Test status
Simulation time 140260173 ps
CPU time 4.08 seconds
Started Jun 10 05:48:43 PM PDT 24
Finished Jun 10 05:48:47 PM PDT 24
Peak memory 217540 kb
Host smart-7ecd9dd5-7176-4625-85c6-ff085d0e5f4f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308822587 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_jtag_access.1308822587
Directory /workspace/27.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/27.lc_ctrl_prog_failure.3471727491
Short name T407
Test name
Test status
Simulation time 246353073 ps
CPU time 2.68 seconds
Started Jun 10 05:48:43 PM PDT 24
Finished Jun 10 05:48:45 PM PDT 24
Peak memory 222804 kb
Host smart-01d4e1a3-8724-4ba3-9dde-002377f3a051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471727491 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_prog_failure.3471727491
Directory /workspace/27.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_mubi.1839694677
Short name T527
Test name
Test status
Simulation time 536729766 ps
CPU time 13.98 seconds
Started Jun 10 05:48:46 PM PDT 24
Finished Jun 10 05:49:00 PM PDT 24
Peak memory 226380 kb
Host smart-fb79dd25-63d0-448d-8a9f-a1b84fbee7ed
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839694677 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_mubi.1839694677
Directory /workspace/27.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_digest.2526934227
Short name T854
Test name
Test status
Simulation time 435956027 ps
CPU time 12.66 seconds
Started Jun 10 05:48:43 PM PDT 24
Finished Jun 10 05:48:56 PM PDT 24
Peak memory 218692 kb
Host smart-c826d351-204b-4a44-923d-6d83a9cbc379
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526934227 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_d
igest.2526934227
Directory /workspace/27.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_mux.1346710850
Short name T858
Test name
Test status
Simulation time 216374469 ps
CPU time 9.82 seconds
Started Jun 10 05:48:43 PM PDT 24
Finished Jun 10 05:48:54 PM PDT 24
Peak memory 218736 kb
Host smart-cbe8f4a3-5126-4a7f-8fdf-1e15af91d55a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346710850 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_mux.
1346710850
Directory /workspace/27.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/27.lc_ctrl_security_escalation.2894904031
Short name T504
Test name
Test status
Simulation time 289604670 ps
CPU time 9.62 seconds
Started Jun 10 05:48:45 PM PDT 24
Finished Jun 10 05:48:55 PM PDT 24
Peak memory 225404 kb
Host smart-a1fab609-56dc-431b-9242-6a37d613749e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894904031 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_security_escalation.2894904031
Directory /workspace/27.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/27.lc_ctrl_smoke.4006857299
Short name T797
Test name
Test status
Simulation time 114464331 ps
CPU time 1.58 seconds
Started Jun 10 05:48:43 PM PDT 24
Finished Jun 10 05:48:45 PM PDT 24
Peak memory 218216 kb
Host smart-ec89ff05-cee0-4d17-8201-8467f95b99f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006857299 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_smoke.4006857299
Directory /workspace/27.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_failure.1645321090
Short name T665
Test name
Test status
Simulation time 274334978 ps
CPU time 32.46 seconds
Started Jun 10 05:48:44 PM PDT 24
Finished Jun 10 05:49:17 PM PDT 24
Peak memory 251432 kb
Host smart-316d992b-0de9-4571-bce9-e1b53bd1fd2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645321090 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_failure.1645321090
Directory /workspace/27.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_post_trans.3398804466
Short name T480
Test name
Test status
Simulation time 205866716 ps
CPU time 6.78 seconds
Started Jun 10 05:48:44 PM PDT 24
Finished Jun 10 05:48:51 PM PDT 24
Peak memory 243156 kb
Host smart-e47c7c0e-da1b-41db-9572-0a2b597909fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398804466 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_post_trans.3398804466
Directory /workspace/27.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all.1698161959
Short name T223
Test name
Test status
Simulation time 6935602032 ps
CPU time 71.9 seconds
Started Jun 10 05:48:44 PM PDT 24
Finished Jun 10 05:49:56 PM PDT 24
Peak memory 251472 kb
Host smart-c7ee9c7f-2b10-4576-8424-bc4a276bed7d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698161959 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.lc_ctrl_stress_all.1698161959
Directory /workspace/27.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.lc_ctrl_volatile_unlock_smoke.1486318033
Short name T245
Test name
Test status
Simulation time 13386674 ps
CPU time 0.97 seconds
Started Jun 10 05:48:42 PM PDT 24
Finished Jun 10 05:48:43 PM PDT 24
Peak memory 212516 kb
Host smart-a69595b8-2831-4b87-805f-f59eb23ac093
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486318033 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_c
trl_volatile_unlock_smoke.1486318033
Directory /workspace/27.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_alert_test.1906468721
Short name T327
Test name
Test status
Simulation time 130367475 ps
CPU time 0.92 seconds
Started Jun 10 05:48:43 PM PDT 24
Finished Jun 10 05:48:44 PM PDT 24
Peak memory 209500 kb
Host smart-a5fcb773-6cbc-49e0-9b5a-ee1b5d21dac2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906468721 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_alert_test.1906468721
Directory /workspace/28.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.lc_ctrl_errors.1349922312
Short name T645
Test name
Test status
Simulation time 898281673 ps
CPU time 8.81 seconds
Started Jun 10 05:48:47 PM PDT 24
Finished Jun 10 05:48:56 PM PDT 24
Peak memory 218696 kb
Host smart-03b7865c-67a0-48b2-94fc-b6e60ebb8fc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349922312 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_errors.1349922312
Directory /workspace/28.lc_ctrl_errors/latest

Test location /workspace/coverage/default/28.lc_ctrl_jtag_access.4224250901
Short name T518
Test name
Test status
Simulation time 5278173890 ps
CPU time 11.82 seconds
Started Jun 10 05:48:46 PM PDT 24
Finished Jun 10 05:48:58 PM PDT 24
Peak memory 218248 kb
Host smart-75f180c1-c0b9-4efb-b590-a18ec5b55b70
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224250901 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_jtag_access.4224250901
Directory /workspace/28.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/28.lc_ctrl_prog_failure.3877870213
Short name T436
Test name
Test status
Simulation time 31738152 ps
CPU time 2.26 seconds
Started Jun 10 05:48:49 PM PDT 24
Finished Jun 10 05:48:51 PM PDT 24
Peak memory 218680 kb
Host smart-6bb205ab-378e-46f0-a843-572a81f1cf86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877870213 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_prog_failure.3877870213
Directory /workspace/28.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_mubi.4267850863
Short name T324
Test name
Test status
Simulation time 574136335 ps
CPU time 13.16 seconds
Started Jun 10 05:48:50 PM PDT 24
Finished Jun 10 05:49:04 PM PDT 24
Peak memory 218736 kb
Host smart-6365b376-dd44-4f20-9c70-dc2248ab8f12
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267850863 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_mubi.4267850863
Directory /workspace/28.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_digest.3778721449
Short name T723
Test name
Test status
Simulation time 229133912 ps
CPU time 9.68 seconds
Started Jun 10 05:48:46 PM PDT 24
Finished Jun 10 05:48:56 PM PDT 24
Peak memory 218652 kb
Host smart-c5c2c937-c96a-4a9a-94a5-9ced334c691c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778721449 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_d
igest.3778721449
Directory /workspace/28.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_mux.60558679
Short name T345
Test name
Test status
Simulation time 293195866 ps
CPU time 12.62 seconds
Started Jun 10 05:48:44 PM PDT 24
Finished Jun 10 05:48:57 PM PDT 24
Peak memory 218700 kb
Host smart-85822439-1411-40e8-8c03-66c3f158177e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60558679 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_mux.60558679
Directory /workspace/28.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/28.lc_ctrl_security_escalation.2467365657
Short name T409
Test name
Test status
Simulation time 181110440 ps
CPU time 9.47 seconds
Started Jun 10 05:48:47 PM PDT 24
Finished Jun 10 05:48:57 PM PDT 24
Peak memory 226548 kb
Host smart-d7740e39-4fd6-4437-9672-225479b4c84f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467365657 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_security_escalation.2467365657
Directory /workspace/28.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/28.lc_ctrl_smoke.3350395027
Short name T74
Test name
Test status
Simulation time 214872535 ps
CPU time 7.61 seconds
Started Jun 10 05:48:46 PM PDT 24
Finished Jun 10 05:48:54 PM PDT 24
Peak memory 218296 kb
Host smart-a70e2c4b-19be-4563-8108-ca22d74160ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350395027 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_smoke.3350395027
Directory /workspace/28.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_failure.56608036
Short name T14
Test name
Test status
Simulation time 782240449 ps
CPU time 19.4 seconds
Started Jun 10 05:48:47 PM PDT 24
Finished Jun 10 05:49:06 PM PDT 24
Peak memory 251432 kb
Host smart-b5c44ff3-48e7-419d-b47a-9f8a662c10c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56608036 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_failure.56608036
Directory /workspace/28.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_post_trans.2259047222
Short name T261
Test name
Test status
Simulation time 86104702 ps
CPU time 3.11 seconds
Started Jun 10 05:48:45 PM PDT 24
Finished Jun 10 05:48:49 PM PDT 24
Peak memory 223172 kb
Host smart-98e47b3b-929f-4e9b-90ee-72230da3c1c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259047222 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_post_trans.2259047222
Directory /workspace/28.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/28.lc_ctrl_stress_all.1848196379
Short name T297
Test name
Test status
Simulation time 3577034120 ps
CPU time 126.42 seconds
Started Jun 10 05:48:49 PM PDT 24
Finished Jun 10 05:50:56 PM PDT 24
Peak memory 279488 kb
Host smart-03698d96-2727-4b4a-ba55-b702aa9ea817
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848196379 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.lc_ctrl_stress_all.1848196379
Directory /workspace/28.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.lc_ctrl_volatile_unlock_smoke.451481812
Short name T522
Test name
Test status
Simulation time 23708281 ps
CPU time 0.97 seconds
Started Jun 10 05:48:45 PM PDT 24
Finished Jun 10 05:48:47 PM PDT 24
Peak memory 212352 kb
Host smart-af3f941b-361d-49ef-9f95-f19619e0797f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451481812 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ct
rl_volatile_unlock_smoke.451481812
Directory /workspace/28.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_alert_test.31611182
Short name T760
Test name
Test status
Simulation time 97528723 ps
CPU time 0.98 seconds
Started Jun 10 05:48:50 PM PDT 24
Finished Jun 10 05:48:52 PM PDT 24
Peak memory 209480 kb
Host smart-da0bb166-b5b1-43ec-bf4c-fd3ed82248a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31611182 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_alert_test.31611182
Directory /workspace/29.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.lc_ctrl_errors.282231073
Short name T390
Test name
Test status
Simulation time 5131858540 ps
CPU time 15.66 seconds
Started Jun 10 05:48:49 PM PDT 24
Finished Jun 10 05:49:05 PM PDT 24
Peak memory 226600 kb
Host smart-736e8b74-943c-4f1f-b8e4-b77ee264c84f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282231073 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_errors.282231073
Directory /workspace/29.lc_ctrl_errors/latest

Test location /workspace/coverage/default/29.lc_ctrl_jtag_access.1416232206
Short name T719
Test name
Test status
Simulation time 2278517586 ps
CPU time 14.16 seconds
Started Jun 10 05:48:50 PM PDT 24
Finished Jun 10 05:49:05 PM PDT 24
Peak memory 217716 kb
Host smart-ac0fa50f-a402-4181-897d-86bbc69b102d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416232206 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_jtag_access.1416232206
Directory /workspace/29.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/29.lc_ctrl_prog_failure.3814799100
Short name T681
Test name
Test status
Simulation time 110256543 ps
CPU time 3 seconds
Started Jun 10 05:48:45 PM PDT 24
Finished Jun 10 05:48:48 PM PDT 24
Peak memory 222792 kb
Host smart-5af8d478-ca5c-472e-aedc-8e6e78d9f58f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814799100 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_prog_failure.3814799100
Directory /workspace/29.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_mubi.2963404041
Short name T363
Test name
Test status
Simulation time 757416414 ps
CPU time 9.95 seconds
Started Jun 10 05:48:51 PM PDT 24
Finished Jun 10 05:49:01 PM PDT 24
Peak memory 218812 kb
Host smart-6abd8094-17ae-4178-b83c-a239f77f0f24
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963404041 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_mubi.2963404041
Directory /workspace/29.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_digest.142406040
Short name T444
Test name
Test status
Simulation time 367355542 ps
CPU time 12.39 seconds
Started Jun 10 05:48:53 PM PDT 24
Finished Jun 10 05:49:05 PM PDT 24
Peak memory 226448 kb
Host smart-380fa497-099e-47ea-ba19-b41a3523f77d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142406040 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_di
gest.142406040
Directory /workspace/29.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_mux.60191079
Short name T562
Test name
Test status
Simulation time 1092316145 ps
CPU time 8.28 seconds
Started Jun 10 05:48:48 PM PDT 24
Finished Jun 10 05:48:57 PM PDT 24
Peak memory 218664 kb
Host smart-34dd1bba-d51b-4f49-82de-a726bd29d16e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60191079 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_mux.60191079
Directory /workspace/29.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/29.lc_ctrl_security_escalation.2061240656
Short name T419
Test name
Test status
Simulation time 2272664124 ps
CPU time 10.56 seconds
Started Jun 10 05:48:46 PM PDT 24
Finished Jun 10 05:48:57 PM PDT 24
Peak memory 226596 kb
Host smart-e171ccbb-d700-4b36-81bd-4f9fbe2d7ede
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061240656 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_security_escalation.2061240656
Directory /workspace/29.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/29.lc_ctrl_smoke.665226748
Short name T32
Test name
Test status
Simulation time 246972037 ps
CPU time 7.56 seconds
Started Jun 10 05:48:45 PM PDT 24
Finished Jun 10 05:48:53 PM PDT 24
Peak memory 218252 kb
Host smart-f362ee59-7509-4f9e-bc4d-c8a8b8df9a53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665226748 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_smoke.665226748
Directory /workspace/29.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_failure.2012813948
Short name T836
Test name
Test status
Simulation time 324180944 ps
CPU time 31.52 seconds
Started Jun 10 05:48:46 PM PDT 24
Finished Jun 10 05:49:18 PM PDT 24
Peak memory 251420 kb
Host smart-36a3ad10-78da-4f20-8bb4-d90d4375d2fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012813948 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_failure.2012813948
Directory /workspace/29.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_post_trans.3263807905
Short name T469
Test name
Test status
Simulation time 59198195 ps
CPU time 8.08 seconds
Started Jun 10 05:48:50 PM PDT 24
Finished Jun 10 05:48:59 PM PDT 24
Peak memory 243176 kb
Host smart-f57539ae-61f7-44cb-a3c2-43eeb815a62c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263807905 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_post_trans.3263807905
Directory /workspace/29.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/29.lc_ctrl_stress_all.902604954
Short name T31
Test name
Test status
Simulation time 4615301625 ps
CPU time 71.32 seconds
Started Jun 10 05:48:51 PM PDT 24
Finished Jun 10 05:50:03 PM PDT 24
Peak memory 268008 kb
Host smart-60563c08-a586-49a7-821e-f96144c9d3a3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902604954 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.lc_ctrl_stress_all.902604954
Directory /workspace/29.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.lc_ctrl_stress_all_with_rand_reset.2455558302
Short name T152
Test name
Test status
Simulation time 21699341985 ps
CPU time 802.55 seconds
Started Jun 10 05:48:52 PM PDT 24
Finished Jun 10 06:02:15 PM PDT 24
Peak memory 520044 kb
Host smart-0ca6a4d0-28d9-4d3e-b18a-ed27edd1d975
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2455558302 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_stress_all_with_rand_reset.2455558302
Directory /workspace/29.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.lc_ctrl_volatile_unlock_smoke.3153668402
Short name T34
Test name
Test status
Simulation time 17413965 ps
CPU time 0.95 seconds
Started Jun 10 05:48:46 PM PDT 24
Finished Jun 10 05:48:47 PM PDT 24
Peak memory 213384 kb
Host smart-0d4ac727-585a-425d-affc-f76817d3e5af
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153668402 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_c
trl_volatile_unlock_smoke.3153668402
Directory /workspace/29.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_alert_test.1655526483
Short name T571
Test name
Test status
Simulation time 17664061 ps
CPU time 0.98 seconds
Started Jun 10 05:46:49 PM PDT 24
Finished Jun 10 05:46:50 PM PDT 24
Peak memory 209444 kb
Host smart-e605533d-5b78-455b-9a92-3aeb55e4c49e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655526483 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_alert_test.1655526483
Directory /workspace/3.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.lc_ctrl_errors.228210988
Short name T293
Test name
Test status
Simulation time 1875594533 ps
CPU time 8.76 seconds
Started Jun 10 05:46:47 PM PDT 24
Finished Jun 10 05:46:56 PM PDT 24
Peak memory 218712 kb
Host smart-14c26882-22f6-4bac-85f1-a09f0881e777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228210988 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_errors.228210988
Directory /workspace/3.lc_ctrl_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_access.2570613158
Short name T26
Test name
Test status
Simulation time 4557006960 ps
CPU time 6.14 seconds
Started Jun 10 05:46:48 PM PDT 24
Finished Jun 10 05:46:55 PM PDT 24
Peak memory 218272 kb
Host smart-68daecfc-5f56-4692-85cf-0f3dd4fe0a25
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570613158 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_access.2570613158
Directory /workspace/3.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_errors.477916772
Short name T467
Test name
Test status
Simulation time 3776381735 ps
CPU time 35.7 seconds
Started Jun 10 05:46:48 PM PDT 24
Finished Jun 10 05:47:24 PM PDT 24
Peak memory 226596 kb
Host smart-9b5f521e-2455-4719-b658-50cf483f62d2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477916772 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_err
ors.477916772
Directory /workspace/3.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_priority.1070227053
Short name T654
Test name
Test status
Simulation time 499846296 ps
CPU time 11.98 seconds
Started Jun 10 05:46:52 PM PDT 24
Finished Jun 10 05:47:04 PM PDT 24
Peak memory 218072 kb
Host smart-a2667c93-6643-4829-934d-2325acd6c072
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070227053 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_priority.1
070227053
Directory /workspace/3.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_prog_failure.296598866
Short name T465
Test name
Test status
Simulation time 584694348 ps
CPU time 5.53 seconds
Started Jun 10 05:46:52 PM PDT 24
Finished Jun 10 05:46:58 PM PDT 24
Peak memory 218732 kb
Host smart-20e1a2be-1ccc-481c-a926-4a0e31297a42
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296598866 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_
prog_failure.296598866
Directory /workspace/3.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_regwen_during_op.1213751685
Short name T537
Test name
Test status
Simulation time 2854609466 ps
CPU time 40.04 seconds
Started Jun 10 05:46:51 PM PDT 24
Finished Jun 10 05:47:32 PM PDT 24
Peak memory 218308 kb
Host smart-7a28bc96-0301-449c-876d-5955a1491a3a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213751685 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_regwen_during_op.1213751685
Directory /workspace/3.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_smoke.1924239513
Short name T76
Test name
Test status
Simulation time 354245255 ps
CPU time 5.36 seconds
Started Jun 10 05:46:48 PM PDT 24
Finished Jun 10 05:46:54 PM PDT 24
Peak memory 218216 kb
Host smart-e13a89e5-8513-4d96-b2e5-c8610f273102
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924239513 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_smoke.
1924239513
Directory /workspace/3.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_failure.1662708124
Short name T487
Test name
Test status
Simulation time 1962856805 ps
CPU time 82.91 seconds
Started Jun 10 05:46:46 PM PDT 24
Finished Jun 10 05:48:09 PM PDT 24
Peak memory 276672 kb
Host smart-a136051e-557f-43bd-a917-b7ff5746fdf7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662708124 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jta
g_state_failure.1662708124
Directory /workspace/3.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_post_trans.3483205354
Short name T839
Test name
Test status
Simulation time 928093803 ps
CPU time 19.75 seconds
Started Jun 10 05:46:49 PM PDT 24
Finished Jun 10 05:47:09 PM PDT 24
Peak memory 251460 kb
Host smart-d2170792-cb13-41bb-a71a-d67bb6116892
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483205354 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_state_post_trans.3483205354
Directory /workspace/3.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_prog_failure.4017223193
Short name T166
Test name
Test status
Simulation time 54619367 ps
CPU time 1.58 seconds
Started Jun 10 05:46:42 PM PDT 24
Finished Jun 10 05:46:44 PM PDT 24
Peak memory 222420 kb
Host smart-cae8caac-bfb5-4d0c-95ae-82e986e55a1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017223193 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_prog_failure.4017223193
Directory /workspace/3.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_regwen_during_op.237774847
Short name T258
Test name
Test status
Simulation time 285376351 ps
CPU time 7.43 seconds
Started Jun 10 05:46:47 PM PDT 24
Finished Jun 10 05:46:55 PM PDT 24
Peak memory 218208 kb
Host smart-b90a542a-5b45-4c63-ad1a-0005355e2ca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237774847 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_regwen_during_op.237774847
Directory /workspace/3.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_mubi.11496499
Short name T536
Test name
Test status
Simulation time 243142017 ps
CPU time 11.19 seconds
Started Jun 10 05:46:50 PM PDT 24
Finished Jun 10 05:47:02 PM PDT 24
Peak memory 219352 kb
Host smart-a906d222-c4cc-416e-aa49-bc087e80637a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11496499 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_mubi.11496499
Directory /workspace/3.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_digest.2544723084
Short name T702
Test name
Test status
Simulation time 573966810 ps
CPU time 11.64 seconds
Started Jun 10 05:46:45 PM PDT 24
Finished Jun 10 05:46:57 PM PDT 24
Peak memory 226424 kb
Host smart-58846155-ce61-44a2-888e-fddea7e77d32
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544723084 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_di
gest.2544723084
Directory /workspace/3.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_mux.1820000477
Short name T97
Test name
Test status
Simulation time 7552943166 ps
CPU time 11.7 seconds
Started Jun 10 05:46:52 PM PDT 24
Finished Jun 10 05:47:04 PM PDT 24
Peak memory 218808 kb
Host smart-c68b8a6c-1227-437d-baf5-81ac287b70cb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820000477 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_mux.1
820000477
Directory /workspace/3.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/3.lc_ctrl_smoke.899852983
Short name T83
Test name
Test status
Simulation time 144508571 ps
CPU time 3.35 seconds
Started Jun 10 05:46:42 PM PDT 24
Finished Jun 10 05:46:46 PM PDT 24
Peak memory 218188 kb
Host smart-2897ab09-ba19-4bf2-b0b6-2d4eabcc1705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899852983 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_smoke.899852983
Directory /workspace/3.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_failure.2616059159
Short name T626
Test name
Test status
Simulation time 375996098 ps
CPU time 30.79 seconds
Started Jun 10 05:46:42 PM PDT 24
Finished Jun 10 05:47:13 PM PDT 24
Peak memory 251452 kb
Host smart-951e5e18-ff5a-4d23-b3bd-fca320e543b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616059159 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_failure.2616059159
Directory /workspace/3.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_post_trans.1586707200
Short name T103
Test name
Test status
Simulation time 123150760 ps
CPU time 7.7 seconds
Started Jun 10 05:46:46 PM PDT 24
Finished Jun 10 05:46:54 PM PDT 24
Peak memory 251528 kb
Host smart-e82b171d-2a9b-4344-a7d3-5cf2ebc089af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586707200 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_post_trans.1586707200
Directory /workspace/3.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_stress_all.3915216119
Short name T428
Test name
Test status
Simulation time 53233395593 ps
CPU time 391.79 seconds
Started Jun 10 05:46:47 PM PDT 24
Finished Jun 10 05:53:19 PM PDT 24
Peak memory 284212 kb
Host smart-74b7acee-f0c9-4d0c-bcd7-0435fc9a7f1c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915216119 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.lc_ctrl_stress_all.3915216119
Directory /workspace/3.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.lc_ctrl_volatile_unlock_smoke.2900743406
Short name T724
Test name
Test status
Simulation time 47916707 ps
CPU time 0.76 seconds
Started Jun 10 05:46:46 PM PDT 24
Finished Jun 10 05:46:47 PM PDT 24
Peak memory 208612 kb
Host smart-a6bd6849-0820-4ae8-a674-769d42c2e038
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900743406 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ct
rl_volatile_unlock_smoke.2900743406
Directory /workspace/3.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_alert_test.1729262870
Short name T375
Test name
Test status
Simulation time 26202491 ps
CPU time 1.24 seconds
Started Jun 10 05:48:53 PM PDT 24
Finished Jun 10 05:48:55 PM PDT 24
Peak memory 209544 kb
Host smart-9dfe9c72-649e-4b1f-bdfe-2c73d013d4b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729262870 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_alert_test.1729262870
Directory /workspace/30.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.lc_ctrl_errors.1493096299
Short name T230
Test name
Test status
Simulation time 701495353 ps
CPU time 13.02 seconds
Started Jun 10 05:48:54 PM PDT 24
Finished Jun 10 05:49:08 PM PDT 24
Peak memory 218700 kb
Host smart-3ab0da73-7eee-4adb-90f8-c84ec2f62395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493096299 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_errors.1493096299
Directory /workspace/30.lc_ctrl_errors/latest

Test location /workspace/coverage/default/30.lc_ctrl_jtag_access.3351487244
Short name T23
Test name
Test status
Simulation time 1052671119 ps
CPU time 12 seconds
Started Jun 10 05:48:56 PM PDT 24
Finished Jun 10 05:49:08 PM PDT 24
Peak memory 217772 kb
Host smart-35b64412-3697-4bcb-af6a-3ea71a1ed906
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351487244 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_jtag_access.3351487244
Directory /workspace/30.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/30.lc_ctrl_prog_failure.2034486617
Short name T660
Test name
Test status
Simulation time 69511126 ps
CPU time 2.42 seconds
Started Jun 10 05:48:56 PM PDT 24
Finished Jun 10 05:48:59 PM PDT 24
Peak memory 222780 kb
Host smart-4f500d3f-820a-4c48-89e8-7b5615d18fb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034486617 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_prog_failure.2034486617
Directory /workspace/30.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_digest.698055304
Short name T555
Test name
Test status
Simulation time 450035697 ps
CPU time 17.29 seconds
Started Jun 10 05:48:56 PM PDT 24
Finished Jun 10 05:49:13 PM PDT 24
Peak memory 226500 kb
Host smart-6fdd0529-afdd-4d69-b9bd-59afa71d3087
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698055304 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_di
gest.698055304
Directory /workspace/30.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_mux.1341103346
Short name T417
Test name
Test status
Simulation time 200925108 ps
CPU time 6.31 seconds
Started Jun 10 05:48:58 PM PDT 24
Finished Jun 10 05:49:04 PM PDT 24
Peak memory 225552 kb
Host smart-dda1cbcc-534e-4c50-8094-63d183ccc74d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341103346 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_mux.
1341103346
Directory /workspace/30.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/30.lc_ctrl_security_escalation.486365605
Short name T264
Test name
Test status
Simulation time 169615973 ps
CPU time 6.09 seconds
Started Jun 10 05:48:56 PM PDT 24
Finished Jun 10 05:49:03 PM PDT 24
Peak memory 225224 kb
Host smart-cb765e7d-3197-43f0-a51a-dc76d7dbf49d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486365605 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_security_escalation.486365605
Directory /workspace/30.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/30.lc_ctrl_smoke.401906704
Short name T614
Test name
Test status
Simulation time 51967886 ps
CPU time 2.14 seconds
Started Jun 10 05:48:51 PM PDT 24
Finished Jun 10 05:48:54 PM PDT 24
Peak memory 218160 kb
Host smart-0fdd4d24-edda-46a6-8d16-5e15803faf8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401906704 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_smoke.401906704
Directory /workspace/30.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_failure.1337399454
Short name T507
Test name
Test status
Simulation time 724185350 ps
CPU time 24.73 seconds
Started Jun 10 05:48:57 PM PDT 24
Finished Jun 10 05:49:22 PM PDT 24
Peak memory 251456 kb
Host smart-8dcd4a97-b666-4b2f-b5e1-e44f53dad682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337399454 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_failure.1337399454
Directory /workspace/30.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_post_trans.3167119367
Short name T776
Test name
Test status
Simulation time 143073717 ps
CPU time 4.04 seconds
Started Jun 10 05:48:57 PM PDT 24
Finished Jun 10 05:49:01 PM PDT 24
Peak memory 226864 kb
Host smart-d2b7cb06-fc7b-4959-96d5-fa28634f7785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167119367 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_post_trans.3167119367
Directory /workspace/30.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/30.lc_ctrl_volatile_unlock_smoke.653664482
Short name T500
Test name
Test status
Simulation time 21669304 ps
CPU time 1.03 seconds
Started Jun 10 05:48:50 PM PDT 24
Finished Jun 10 05:48:52 PM PDT 24
Peak memory 213440 kb
Host smart-4554b234-1c1a-4d1b-8314-7a980a648752
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653664482 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ct
rl_volatile_unlock_smoke.653664482
Directory /workspace/30.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_alert_test.3180880373
Short name T671
Test name
Test status
Simulation time 56987663 ps
CPU time 0.91 seconds
Started Jun 10 05:48:58 PM PDT 24
Finished Jun 10 05:48:59 PM PDT 24
Peak memory 209488 kb
Host smart-7fd644ee-df5a-418a-b305-134ac3787458
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180880373 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_alert_test.3180880373
Directory /workspace/31.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.lc_ctrl_errors.1312109841
Short name T620
Test name
Test status
Simulation time 1220486401 ps
CPU time 17.16 seconds
Started Jun 10 05:48:55 PM PDT 24
Finished Jun 10 05:49:13 PM PDT 24
Peak memory 218696 kb
Host smart-ee90026e-6ba8-4ad8-8c3f-bcae91376635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312109841 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_errors.1312109841
Directory /workspace/31.lc_ctrl_errors/latest

Test location /workspace/coverage/default/31.lc_ctrl_jtag_access.844476676
Short name T303
Test name
Test status
Simulation time 618805345 ps
CPU time 7.13 seconds
Started Jun 10 05:48:54 PM PDT 24
Finished Jun 10 05:49:02 PM PDT 24
Peak memory 217856 kb
Host smart-18018577-1736-4eda-bef5-ac7a472076c6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844476676 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_jtag_access.844476676
Directory /workspace/31.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/31.lc_ctrl_prog_failure.4209758814
Short name T319
Test name
Test status
Simulation time 77391353 ps
CPU time 2.59 seconds
Started Jun 10 05:48:54 PM PDT 24
Finished Jun 10 05:48:57 PM PDT 24
Peak memory 218644 kb
Host smart-8a62ca23-e2de-4a7d-9e87-72e3f1f72eb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209758814 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_prog_failure.4209758814
Directory /workspace/31.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_mubi.2735843161
Short name T603
Test name
Test status
Simulation time 4476146314 ps
CPU time 11.89 seconds
Started Jun 10 05:48:55 PM PDT 24
Finished Jun 10 05:49:07 PM PDT 24
Peak memory 219132 kb
Host smart-be3c12a7-8a3b-472e-8708-4e7eaac8c6ad
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735843161 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_mubi.2735843161
Directory /workspace/31.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_digest.4205042406
Short name T373
Test name
Test status
Simulation time 1465485946 ps
CPU time 11.46 seconds
Started Jun 10 05:49:00 PM PDT 24
Finished Jun 10 05:49:12 PM PDT 24
Peak memory 218728 kb
Host smart-20114e0c-9df4-4c9a-89db-8fa87ac52a26
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205042406 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_d
igest.4205042406
Directory /workspace/31.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_mux.3671558864
Short name T392
Test name
Test status
Simulation time 642028920 ps
CPU time 12.15 seconds
Started Jun 10 05:48:58 PM PDT 24
Finished Jun 10 05:49:10 PM PDT 24
Peak memory 218708 kb
Host smart-3d1c052d-63ab-47cb-84c1-5c125160b5be
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671558864 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_mux.
3671558864
Directory /workspace/31.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/31.lc_ctrl_security_escalation.762201977
Short name T749
Test name
Test status
Simulation time 340596840 ps
CPU time 10.33 seconds
Started Jun 10 05:48:54 PM PDT 24
Finished Jun 10 05:49:05 PM PDT 24
Peak memory 226604 kb
Host smart-5d6ed068-b4f8-4a9d-ae86-509d98a97812
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762201977 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_security_escalation.762201977
Directory /workspace/31.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/31.lc_ctrl_smoke.1491124922
Short name T105
Test name
Test status
Simulation time 78455035 ps
CPU time 3.04 seconds
Started Jun 10 05:48:53 PM PDT 24
Finished Jun 10 05:48:57 PM PDT 24
Peak memory 218268 kb
Host smart-3b40220f-1d40-42b7-a58e-a8c45e5c74eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491124922 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_smoke.1491124922
Directory /workspace/31.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_failure.4001183027
Short name T389
Test name
Test status
Simulation time 255004488 ps
CPU time 21.63 seconds
Started Jun 10 05:48:59 PM PDT 24
Finished Jun 10 05:49:21 PM PDT 24
Peak memory 251412 kb
Host smart-5e1bdf61-4b6a-4203-a806-ad6fba181c02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001183027 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_failure.4001183027
Directory /workspace/31.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_post_trans.509375118
Short name T559
Test name
Test status
Simulation time 618413503 ps
CPU time 8.42 seconds
Started Jun 10 05:48:57 PM PDT 24
Finished Jun 10 05:49:06 PM PDT 24
Peak memory 244236 kb
Host smart-e23eb130-17c1-4bbc-9b80-6452eba6ae85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509375118 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_post_trans.509375118
Directory /workspace/31.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/31.lc_ctrl_stress_all.956592403
Short name T323
Test name
Test status
Simulation time 1403451404 ps
CPU time 64.32 seconds
Started Jun 10 05:48:59 PM PDT 24
Finished Jun 10 05:50:04 PM PDT 24
Peak memory 268744 kb
Host smart-0fad42df-c77a-4a71-af1f-3a9a0e892881
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956592403 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.lc_ctrl_stress_all.956592403
Directory /workspace/31.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.lc_ctrl_volatile_unlock_smoke.2131240842
Short name T442
Test name
Test status
Simulation time 13023355 ps
CPU time 0.86 seconds
Started Jun 10 05:48:54 PM PDT 24
Finished Jun 10 05:48:55 PM PDT 24
Peak memory 209520 kb
Host smart-7142e2d8-6f9d-449c-b2ff-94c19ab93f99
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131240842 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_c
trl_volatile_unlock_smoke.2131240842
Directory /workspace/31.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_alert_test.3041554862
Short name T339
Test name
Test status
Simulation time 26332342 ps
CPU time 0.92 seconds
Started Jun 10 05:49:03 PM PDT 24
Finished Jun 10 05:49:04 PM PDT 24
Peak memory 209276 kb
Host smart-5da31ebe-e00a-4e9f-8454-e4549a0dd047
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041554862 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_alert_test.3041554862
Directory /workspace/32.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.lc_ctrl_errors.2917051954
Short name T516
Test name
Test status
Simulation time 1613513800 ps
CPU time 11.96 seconds
Started Jun 10 05:48:59 PM PDT 24
Finished Jun 10 05:49:12 PM PDT 24
Peak memory 218608 kb
Host smart-b034d7d5-ab99-4b0c-97b5-798ea763aa02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917051954 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_errors.2917051954
Directory /workspace/32.lc_ctrl_errors/latest

Test location /workspace/coverage/default/32.lc_ctrl_jtag_access.1182779131
Short name T656
Test name
Test status
Simulation time 949991441 ps
CPU time 6.46 seconds
Started Jun 10 05:49:03 PM PDT 24
Finished Jun 10 05:49:10 PM PDT 24
Peak memory 217820 kb
Host smart-5403d0a4-5cd5-4721-bfd5-dfbe4542a2b9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182779131 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_jtag_access.1182779131
Directory /workspace/32.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/32.lc_ctrl_prog_failure.586072032
Short name T447
Test name
Test status
Simulation time 48614351 ps
CPU time 2.19 seconds
Started Jun 10 05:48:58 PM PDT 24
Finished Jun 10 05:49:01 PM PDT 24
Peak memory 222604 kb
Host smart-16fb9df3-c197-4dea-bae4-42e9dcd26d8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=586072032 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_prog_failure.586072032
Directory /workspace/32.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_mubi.3870295522
Short name T367
Test name
Test status
Simulation time 502860796 ps
CPU time 12.29 seconds
Started Jun 10 05:49:02 PM PDT 24
Finished Jun 10 05:49:15 PM PDT 24
Peak memory 226520 kb
Host smart-6a0c99e4-924b-4006-97fc-622745a28c82
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870295522 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_mubi.3870295522
Directory /workspace/32.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_digest.817122997
Short name T647
Test name
Test status
Simulation time 1123393862 ps
CPU time 12.22 seconds
Started Jun 10 05:48:58 PM PDT 24
Finished Jun 10 05:49:11 PM PDT 24
Peak memory 226552 kb
Host smart-6d27fd69-79fb-43f7-b1b1-1fe99b7235b5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817122997 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_di
gest.817122997
Directory /workspace/32.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_mux.1513000321
Short name T564
Test name
Test status
Simulation time 310166024 ps
CPU time 8.94 seconds
Started Jun 10 05:49:02 PM PDT 24
Finished Jun 10 05:49:11 PM PDT 24
Peak memory 218752 kb
Host smart-f1712ccb-3061-4241-a53c-2cfcc1e7637e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513000321 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_mux.
1513000321
Directory /workspace/32.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/32.lc_ctrl_security_escalation.479717751
Short name T520
Test name
Test status
Simulation time 1167376004 ps
CPU time 17.62 seconds
Started Jun 10 05:49:00 PM PDT 24
Finished Jun 10 05:49:18 PM PDT 24
Peak memory 226520 kb
Host smart-33a58941-9727-4571-8b5a-c6e4feed16f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479717751 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_security_escalation.479717751
Directory /workspace/32.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/32.lc_ctrl_smoke.910241921
Short name T737
Test name
Test status
Simulation time 40376137 ps
CPU time 3.1 seconds
Started Jun 10 05:49:00 PM PDT 24
Finished Jun 10 05:49:03 PM PDT 24
Peak memory 214628 kb
Host smart-4deff2c7-9a19-4fca-92f8-30560d723e34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910241921 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_smoke.910241921
Directory /workspace/32.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_failure.3445883454
Short name T494
Test name
Test status
Simulation time 874370587 ps
CPU time 18.61 seconds
Started Jun 10 05:48:59 PM PDT 24
Finished Jun 10 05:49:18 PM PDT 24
Peak memory 251388 kb
Host smart-4db143da-9e4b-48d9-9e29-44b3f486829c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445883454 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_failure.3445883454
Directory /workspace/32.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_post_trans.4271596015
Short name T817
Test name
Test status
Simulation time 1149118009 ps
CPU time 8.83 seconds
Started Jun 10 05:48:59 PM PDT 24
Finished Jun 10 05:49:08 PM PDT 24
Peak memory 251508 kb
Host smart-247830af-24b3-43f2-97e5-4d5151c18837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271596015 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_post_trans.4271596015
Directory /workspace/32.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all.3988452058
Short name T733
Test name
Test status
Simulation time 2312305007 ps
CPU time 70.65 seconds
Started Jun 10 05:49:05 PM PDT 24
Finished Jun 10 05:50:16 PM PDT 24
Peak memory 278908 kb
Host smart-edff210e-97a8-45e6-b1d4-afcf811716fd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988452058 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.lc_ctrl_stress_all.3988452058
Directory /workspace/32.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.lc_ctrl_volatile_unlock_smoke.3889203414
Short name T531
Test name
Test status
Simulation time 26598598 ps
CPU time 0.83 seconds
Started Jun 10 05:49:01 PM PDT 24
Finished Jun 10 05:49:02 PM PDT 24
Peak memory 209540 kb
Host smart-477456cf-48e7-4c16-bdc1-11689a04fe71
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889203414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_c
trl_volatile_unlock_smoke.3889203414
Directory /workspace/32.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_alert_test.3418517835
Short name T365
Test name
Test status
Simulation time 75203005 ps
CPU time 1.25 seconds
Started Jun 10 05:49:05 PM PDT 24
Finished Jun 10 05:49:06 PM PDT 24
Peak memory 209448 kb
Host smart-f7439d7d-99cb-4560-998c-f4bc2d6328cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418517835 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_alert_test.3418517835
Directory /workspace/33.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.lc_ctrl_errors.973326251
Short name T476
Test name
Test status
Simulation time 460228239 ps
CPU time 10.91 seconds
Started Jun 10 05:49:05 PM PDT 24
Finished Jun 10 05:49:17 PM PDT 24
Peak memory 218624 kb
Host smart-d770e52b-26e2-4443-a9f8-3fc23d77ea64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973326251 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_errors.973326251
Directory /workspace/33.lc_ctrl_errors/latest

Test location /workspace/coverage/default/33.lc_ctrl_prog_failure.4260180341
Short name T857
Test name
Test status
Simulation time 141417214 ps
CPU time 2.09 seconds
Started Jun 10 05:49:01 PM PDT 24
Finished Jun 10 05:49:03 PM PDT 24
Peak memory 218648 kb
Host smart-aa770b3e-a816-4035-a137-3fd210eaa969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4260180341 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_prog_failure.4260180341
Directory /workspace/33.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_mubi.781274237
Short name T33
Test name
Test status
Simulation time 2351568485 ps
CPU time 11.86 seconds
Started Jun 10 05:49:04 PM PDT 24
Finished Jun 10 05:49:16 PM PDT 24
Peak memory 226608 kb
Host smart-964d489e-f5ad-49ac-83cf-b9843879f474
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781274237 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_mubi.781274237
Directory /workspace/33.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_digest.436021862
Short name T852
Test name
Test status
Simulation time 3409152272 ps
CPU time 11.83 seconds
Started Jun 10 05:49:02 PM PDT 24
Finished Jun 10 05:49:14 PM PDT 24
Peak memory 219460 kb
Host smart-ddfcd17e-140b-4ab9-a365-021a2abfd51e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436021862 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_di
gest.436021862
Directory /workspace/33.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_mux.2665762656
Short name T598
Test name
Test status
Simulation time 560385124 ps
CPU time 14.26 seconds
Started Jun 10 05:49:03 PM PDT 24
Finished Jun 10 05:49:18 PM PDT 24
Peak memory 226540 kb
Host smart-e52c8699-2ce8-4be5-9501-5d1cd055d13f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665762656 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_mux.
2665762656
Directory /workspace/33.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/33.lc_ctrl_security_escalation.2786209040
Short name T766
Test name
Test status
Simulation time 1262294074 ps
CPU time 11.89 seconds
Started Jun 10 05:49:05 PM PDT 24
Finished Jun 10 05:49:17 PM PDT 24
Peak memory 226112 kb
Host smart-4827e97a-414d-48bb-bc95-a1d29617abe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786209040 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_security_escalation.2786209040
Directory /workspace/33.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/33.lc_ctrl_smoke.2254322672
Short name T566
Test name
Test status
Simulation time 297762665 ps
CPU time 1.93 seconds
Started Jun 10 05:49:04 PM PDT 24
Finished Jun 10 05:49:06 PM PDT 24
Peak memory 214468 kb
Host smart-0e9678df-652d-4b38-8801-c1ff4306d465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254322672 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_smoke.2254322672
Directory /workspace/33.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_failure.947700410
Short name T595
Test name
Test status
Simulation time 318122872 ps
CPU time 32.16 seconds
Started Jun 10 05:49:03 PM PDT 24
Finished Jun 10 05:49:36 PM PDT 24
Peak memory 251428 kb
Host smart-35045a01-5ef2-4679-bdc0-34c49052e4c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947700410 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_failure.947700410
Directory /workspace/33.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_post_trans.1783039899
Short name T454
Test name
Test status
Simulation time 269883357 ps
CPU time 6.64 seconds
Started Jun 10 05:49:04 PM PDT 24
Finished Jun 10 05:49:11 PM PDT 24
Peak memory 250872 kb
Host smart-e57ae70c-9739-40d9-91e8-6f3b9dda53a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783039899 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_post_trans.1783039899
Directory /workspace/33.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all.4138826659
Short name T184
Test name
Test status
Simulation time 15222353789 ps
CPU time 137.86 seconds
Started Jun 10 05:49:04 PM PDT 24
Finished Jun 10 05:51:22 PM PDT 24
Peak memory 251480 kb
Host smart-15230996-999a-4db3-844d-a813d2959908
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138826659 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.lc_ctrl_stress_all.4138826659
Directory /workspace/33.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.lc_ctrl_volatile_unlock_smoke.1912158180
Short name T627
Test name
Test status
Simulation time 11508076 ps
CPU time 0.9 seconds
Started Jun 10 05:49:01 PM PDT 24
Finished Jun 10 05:49:02 PM PDT 24
Peak memory 209348 kb
Host smart-8210a205-b878-44f7-8542-7f3a62aad917
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912158180 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_c
trl_volatile_unlock_smoke.1912158180
Directory /workspace/33.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_alert_test.1894924395
Short name T75
Test name
Test status
Simulation time 51861194 ps
CPU time 0.9 seconds
Started Jun 10 05:49:04 PM PDT 24
Finished Jun 10 05:49:06 PM PDT 24
Peak memory 209468 kb
Host smart-14ef8a75-e607-41fd-af02-c58a37a276f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894924395 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_alert_test.1894924395
Directory /workspace/34.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.lc_ctrl_errors.2882247857
Short name T868
Test name
Test status
Simulation time 1439691902 ps
CPU time 17.66 seconds
Started Jun 10 05:49:09 PM PDT 24
Finished Jun 10 05:49:27 PM PDT 24
Peak memory 218740 kb
Host smart-6244075e-d71a-4b73-815a-50b4d8f2fffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882247857 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_errors.2882247857
Directory /workspace/34.lc_ctrl_errors/latest

Test location /workspace/coverage/default/34.lc_ctrl_jtag_access.3569187357
Short name T823
Test name
Test status
Simulation time 466808816 ps
CPU time 3.51 seconds
Started Jun 10 05:49:07 PM PDT 24
Finished Jun 10 05:49:11 PM PDT 24
Peak memory 217568 kb
Host smart-633bafed-ef2f-4709-963d-43af91c50da3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569187357 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_jtag_access.3569187357
Directory /workspace/34.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/34.lc_ctrl_prog_failure.3329842595
Short name T432
Test name
Test status
Simulation time 50088837 ps
CPU time 1.79 seconds
Started Jun 10 05:49:10 PM PDT 24
Finished Jun 10 05:49:12 PM PDT 24
Peak memory 218700 kb
Host smart-6ab46b0d-48b0-4530-980f-b458cf375109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3329842595 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_prog_failure.3329842595
Directory /workspace/34.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_mubi.600457241
Short name T155
Test name
Test status
Simulation time 638860193 ps
CPU time 12.92 seconds
Started Jun 10 05:49:07 PM PDT 24
Finished Jun 10 05:49:20 PM PDT 24
Peak memory 219428 kb
Host smart-ca0f1f46-c096-4284-8ab2-74c4f5e2e2c8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600457241 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_mubi.600457241
Directory /workspace/34.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_digest.2786570387
Short name T306
Test name
Test status
Simulation time 3063310776 ps
CPU time 9.71 seconds
Started Jun 10 05:49:06 PM PDT 24
Finished Jun 10 05:49:16 PM PDT 24
Peak memory 218788 kb
Host smart-0722241b-36b5-44e1-b9fc-66b8ecb4b87f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786570387 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_d
igest.2786570387
Directory /workspace/34.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_mux.1831967275
Short name T717
Test name
Test status
Simulation time 514975210 ps
CPU time 7.95 seconds
Started Jun 10 05:49:07 PM PDT 24
Finished Jun 10 05:49:15 PM PDT 24
Peak memory 218724 kb
Host smart-54f41574-148a-40b6-9f35-b8b5fd55ddb2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831967275 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_mux.
1831967275
Directory /workspace/34.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/34.lc_ctrl_security_escalation.584813535
Short name T640
Test name
Test status
Simulation time 6122448384 ps
CPU time 12.03 seconds
Started Jun 10 05:49:09 PM PDT 24
Finished Jun 10 05:49:21 PM PDT 24
Peak memory 218760 kb
Host smart-d9489daf-9c78-4728-843c-0d140314041c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584813535 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_security_escalation.584813535
Directory /workspace/34.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/34.lc_ctrl_smoke.3964838446
Short name T336
Test name
Test status
Simulation time 33218632 ps
CPU time 1.36 seconds
Started Jun 10 05:49:05 PM PDT 24
Finished Jun 10 05:49:06 PM PDT 24
Peak memory 218228 kb
Host smart-5c57ba43-639c-4f8d-9312-90ff40122f69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964838446 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_smoke.3964838446
Directory /workspace/34.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_failure.2181373894
Short name T167
Test name
Test status
Simulation time 348200651 ps
CPU time 30.23 seconds
Started Jun 10 05:49:08 PM PDT 24
Finished Jun 10 05:49:38 PM PDT 24
Peak memory 251404 kb
Host smart-52741cb0-672b-4f30-925e-d68dfb6f29f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181373894 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_failure.2181373894
Directory /workspace/34.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_post_trans.1450544909
Short name T807
Test name
Test status
Simulation time 58091039 ps
CPU time 3.22 seconds
Started Jun 10 05:49:09 PM PDT 24
Finished Jun 10 05:49:13 PM PDT 24
Peak memory 222808 kb
Host smart-7b003a6f-3e80-48d9-9a1b-e7657a023ed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450544909 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_post_trans.1450544909
Directory /workspace/34.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all.2102819565
Short name T77
Test name
Test status
Simulation time 8962068141 ps
CPU time 34.77 seconds
Started Jun 10 05:49:07 PM PDT 24
Finished Jun 10 05:49:42 PM PDT 24
Peak memory 251416 kb
Host smart-b33d893e-fcab-4c7e-9712-e94a371ee163
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102819565 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.lc_ctrl_stress_all.2102819565
Directory /workspace/34.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.lc_ctrl_volatile_unlock_smoke.1856456994
Short name T248
Test name
Test status
Simulation time 20790994 ps
CPU time 1.37 seconds
Started Jun 10 05:49:09 PM PDT 24
Finished Jun 10 05:49:10 PM PDT 24
Peak memory 218204 kb
Host smart-bdee5fd2-64a4-4235-b87c-80eee216883a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856456994 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_c
trl_volatile_unlock_smoke.1856456994
Directory /workspace/34.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_alert_test.2216266601
Short name T838
Test name
Test status
Simulation time 22669427 ps
CPU time 1.06 seconds
Started Jun 10 05:49:11 PM PDT 24
Finished Jun 10 05:49:12 PM PDT 24
Peak memory 209536 kb
Host smart-bb62bfc7-5abe-4f29-8c58-d1d78d6d0539
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216266601 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_alert_test.2216266601
Directory /workspace/35.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.lc_ctrl_errors.1106392824
Short name T697
Test name
Test status
Simulation time 252921927 ps
CPU time 10.73 seconds
Started Jun 10 05:49:13 PM PDT 24
Finished Jun 10 05:49:24 PM PDT 24
Peak memory 218636 kb
Host smart-4c2ffb7c-831d-4c87-8b92-52ce8b01c241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106392824 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_errors.1106392824
Directory /workspace/35.lc_ctrl_errors/latest

Test location /workspace/coverage/default/35.lc_ctrl_jtag_access.4163511440
Short name T699
Test name
Test status
Simulation time 2480083437 ps
CPU time 17.89 seconds
Started Jun 10 05:49:12 PM PDT 24
Finished Jun 10 05:49:30 PM PDT 24
Peak memory 218268 kb
Host smart-116e57a9-1d48-4645-be54-44715e9fed49
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163511440 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_jtag_access.4163511440
Directory /workspace/35.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/35.lc_ctrl_prog_failure.134550540
Short name T586
Test name
Test status
Simulation time 267858469 ps
CPU time 2.56 seconds
Started Jun 10 05:49:08 PM PDT 24
Finished Jun 10 05:49:11 PM PDT 24
Peak memory 218704 kb
Host smart-1d98ca9b-7892-4e16-932c-4c442d2eb774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134550540 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_prog_failure.134550540
Directory /workspace/35.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_mubi.4019979775
Short name T269
Test name
Test status
Simulation time 938474272 ps
CPU time 10.8 seconds
Started Jun 10 05:49:10 PM PDT 24
Finished Jun 10 05:49:21 PM PDT 24
Peak memory 218740 kb
Host smart-b9d10d64-85c6-4387-ad2b-f140c49a81b9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019979775 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_mubi.4019979775
Directory /workspace/35.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_digest.3726401199
Short name T445
Test name
Test status
Simulation time 4410084827 ps
CPU time 11.22 seconds
Started Jun 10 05:49:12 PM PDT 24
Finished Jun 10 05:49:24 PM PDT 24
Peak memory 218552 kb
Host smart-967d7192-e18f-4dfa-be8e-931a4da5c4c0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726401199 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_d
igest.3726401199
Directory /workspace/35.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_mux.4241835949
Short name T242
Test name
Test status
Simulation time 445057282 ps
CPU time 11.25 seconds
Started Jun 10 05:49:14 PM PDT 24
Finished Jun 10 05:49:26 PM PDT 24
Peak memory 226540 kb
Host smart-a21e45dd-5548-4295-8866-8d8e65194021
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241835949 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_mux.
4241835949
Directory /workspace/35.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/35.lc_ctrl_security_escalation.2979932460
Short name T617
Test name
Test status
Simulation time 767128909 ps
CPU time 11.07 seconds
Started Jun 10 05:49:13 PM PDT 24
Finished Jun 10 05:49:24 PM PDT 24
Peak memory 226532 kb
Host smart-2337c44c-eabc-4ad8-b0dd-8f025ac75b88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979932460 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_security_escalation.2979932460
Directory /workspace/35.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/35.lc_ctrl_smoke.4272393566
Short name T366
Test name
Test status
Simulation time 183459044 ps
CPU time 5.46 seconds
Started Jun 10 05:49:09 PM PDT 24
Finished Jun 10 05:49:15 PM PDT 24
Peak memory 218204 kb
Host smart-e1f532dd-57d6-481e-acc6-a51d14a041d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272393566 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_smoke.4272393566
Directory /workspace/35.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_failure.1846636231
Short name T154
Test name
Test status
Simulation time 379406618 ps
CPU time 23.67 seconds
Started Jun 10 05:49:11 PM PDT 24
Finished Jun 10 05:49:35 PM PDT 24
Peak memory 251448 kb
Host smart-db3b21c9-8e39-4cc9-a8e6-493d6714947b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846636231 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_failure.1846636231
Directory /workspace/35.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_post_trans.903704283
Short name T291
Test name
Test status
Simulation time 56174023 ps
CPU time 7.72 seconds
Started Jun 10 05:49:07 PM PDT 24
Finished Jun 10 05:49:15 PM PDT 24
Peak memory 251524 kb
Host smart-7e55f9c4-4958-4acb-a8d1-dadead0e33dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903704283 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_post_trans.903704283
Directory /workspace/35.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all.3634385458
Short name T475
Test name
Test status
Simulation time 1316819559 ps
CPU time 20.41 seconds
Started Jun 10 05:49:14 PM PDT 24
Finished Jun 10 05:49:35 PM PDT 24
Peak memory 226980 kb
Host smart-473fc3be-4c88-43bf-a5e2-1215a6e1c008
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634385458 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.lc_ctrl_stress_all.3634385458
Directory /workspace/35.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.lc_ctrl_volatile_unlock_smoke.38091964
Short name T840
Test name
Test status
Simulation time 15460263 ps
CPU time 1.2 seconds
Started Jun 10 05:49:08 PM PDT 24
Finished Jun 10 05:49:09 PM PDT 24
Peak memory 212364 kb
Host smart-9bc3d7be-d655-4961-8662-2d566e0c6182
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38091964 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vol
atile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctr
l_volatile_unlock_smoke.38091964
Directory /workspace/35.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_alert_test.3054847689
Short name T682
Test name
Test status
Simulation time 19415292 ps
CPU time 1.16 seconds
Started Jun 10 05:49:20 PM PDT 24
Finished Jun 10 05:49:22 PM PDT 24
Peak memory 209492 kb
Host smart-85cf2671-76d4-4571-8c08-93926b639989
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054847689 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_alert_test.3054847689
Directory /workspace/36.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.lc_ctrl_errors.2761002401
Short name T275
Test name
Test status
Simulation time 2232481894 ps
CPU time 11.15 seconds
Started Jun 10 05:49:13 PM PDT 24
Finished Jun 10 05:49:24 PM PDT 24
Peak memory 218760 kb
Host smart-3f88560a-a4e0-40fd-9cc8-9bedd0af9651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761002401 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_errors.2761002401
Directory /workspace/36.lc_ctrl_errors/latest

Test location /workspace/coverage/default/36.lc_ctrl_jtag_access.351425148
Short name T20
Test name
Test status
Simulation time 296672965 ps
CPU time 3.44 seconds
Started Jun 10 05:49:18 PM PDT 24
Finished Jun 10 05:49:22 PM PDT 24
Peak memory 217816 kb
Host smart-0957d8ee-23ff-45a2-8935-45d858c5420b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351425148 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_jtag_access.351425148
Directory /workspace/36.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/36.lc_ctrl_prog_failure.1004525324
Short name T731
Test name
Test status
Simulation time 22200768 ps
CPU time 1.82 seconds
Started Jun 10 05:49:13 PM PDT 24
Finished Jun 10 05:49:16 PM PDT 24
Peak memory 218640 kb
Host smart-4b3e272f-eed3-42f9-8618-a1c5fac5dee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004525324 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_prog_failure.1004525324
Directory /workspace/36.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_mubi.3278081842
Short name T652
Test name
Test status
Simulation time 793552428 ps
CPU time 20.65 seconds
Started Jun 10 05:49:15 PM PDT 24
Finished Jun 10 05:49:36 PM PDT 24
Peak memory 226552 kb
Host smart-87cd27c4-a55d-47d4-ae5e-01c33790b576
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278081842 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_mubi.3278081842
Directory /workspace/36.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_digest.3727790951
Short name T841
Test name
Test status
Simulation time 3118144805 ps
CPU time 7.11 seconds
Started Jun 10 05:49:17 PM PDT 24
Finished Jun 10 05:49:24 PM PDT 24
Peak memory 218684 kb
Host smart-3e24edce-ef20-4ece-871c-4253db21c3bc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727790951 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_d
igest.3727790951
Directory /workspace/36.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_mux.2402025226
Short name T40
Test name
Test status
Simulation time 849911151 ps
CPU time 7 seconds
Started Jun 10 05:49:16 PM PDT 24
Finished Jun 10 05:49:24 PM PDT 24
Peak memory 225928 kb
Host smart-d4f8bcc3-e15c-4b8a-a672-3b3e8fb7ce50
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402025226 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_mux.
2402025226
Directory /workspace/36.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/36.lc_ctrl_security_escalation.3553168929
Short name T307
Test name
Test status
Simulation time 676476424 ps
CPU time 8.32 seconds
Started Jun 10 05:49:20 PM PDT 24
Finished Jun 10 05:49:29 PM PDT 24
Peak memory 226476 kb
Host smart-2ef9495d-f436-4874-9a7b-ea5d1c8cac2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553168929 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_security_escalation.3553168929
Directory /workspace/36.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/36.lc_ctrl_smoke.121438881
Short name T565
Test name
Test status
Simulation time 566548675 ps
CPU time 3.02 seconds
Started Jun 10 05:49:12 PM PDT 24
Finished Jun 10 05:49:16 PM PDT 24
Peak memory 218224 kb
Host smart-0f189140-66ca-4639-bbb8-90e611d2ce53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121438881 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_smoke.121438881
Directory /workspace/36.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_failure.2774358626
Short name T378
Test name
Test status
Simulation time 227640764 ps
CPU time 21.12 seconds
Started Jun 10 05:49:10 PM PDT 24
Finished Jun 10 05:49:31 PM PDT 24
Peak memory 251460 kb
Host smart-40a46c7e-d25e-4bf9-972d-a178cd4cc02f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774358626 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_failure.2774358626
Directory /workspace/36.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_post_trans.2422753206
Short name T158
Test name
Test status
Simulation time 175175139 ps
CPU time 5.79 seconds
Started Jun 10 05:49:08 PM PDT 24
Finished Jun 10 05:49:14 PM PDT 24
Peak memory 247356 kb
Host smart-017e64a7-2d9d-4280-b3fd-d79caad488d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422753206 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_post_trans.2422753206
Directory /workspace/36.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/36.lc_ctrl_volatile_unlock_smoke.3404618740
Short name T524
Test name
Test status
Simulation time 24054625 ps
CPU time 0.93 seconds
Started Jun 10 05:49:13 PM PDT 24
Finished Jun 10 05:49:14 PM PDT 24
Peak memory 209436 kb
Host smart-4a96f56f-c7eb-45f4-98df-0aaaf3169b57
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404618740 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_c
trl_volatile_unlock_smoke.3404618740
Directory /workspace/36.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_alert_test.1579203858
Short name T376
Test name
Test status
Simulation time 13139168 ps
CPU time 1.08 seconds
Started Jun 10 05:49:21 PM PDT 24
Finished Jun 10 05:49:22 PM PDT 24
Peak memory 209320 kb
Host smart-6762d01a-54a0-44d8-8236-69897aaedb70
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579203858 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_alert_test.1579203858
Directory /workspace/37.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.lc_ctrl_errors.2158523072
Short name T216
Test name
Test status
Simulation time 1546283858 ps
CPU time 10.39 seconds
Started Jun 10 05:49:19 PM PDT 24
Finished Jun 10 05:49:29 PM PDT 24
Peak memory 218640 kb
Host smart-d8d2632b-7822-4464-8c76-0f90cb268890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2158523072 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_errors.2158523072
Directory /workspace/37.lc_ctrl_errors/latest

Test location /workspace/coverage/default/37.lc_ctrl_jtag_access.2770295093
Short name T799
Test name
Test status
Simulation time 4200711447 ps
CPU time 7.07 seconds
Started Jun 10 05:49:20 PM PDT 24
Finished Jun 10 05:49:27 PM PDT 24
Peak memory 218208 kb
Host smart-416f9b03-abf7-4848-8999-3ea123b5d975
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770295093 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_jtag_access.2770295093
Directory /workspace/37.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/37.lc_ctrl_prog_failure.901934371
Short name T796
Test name
Test status
Simulation time 125459107 ps
CPU time 2.75 seconds
Started Jun 10 05:49:18 PM PDT 24
Finished Jun 10 05:49:21 PM PDT 24
Peak memory 218680 kb
Host smart-57ebb79f-75e3-447f-9fa7-da6eaf68186f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901934371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_prog_failure.901934371
Directory /workspace/37.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_mubi.2964445545
Short name T822
Test name
Test status
Simulation time 313219107 ps
CPU time 15.35 seconds
Started Jun 10 05:49:20 PM PDT 24
Finished Jun 10 05:49:36 PM PDT 24
Peak memory 219420 kb
Host smart-c433ca24-d6e4-48b5-b6c5-e7cba12257b0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964445545 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_mubi.2964445545
Directory /workspace/37.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_digest.2329298882
Short name T552
Test name
Test status
Simulation time 922761899 ps
CPU time 10.91 seconds
Started Jun 10 05:49:22 PM PDT 24
Finished Jun 10 05:49:34 PM PDT 24
Peak memory 218732 kb
Host smart-97d82ec0-a609-462b-94b5-2f166ad7a26b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329298882 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_d
igest.2329298882
Directory /workspace/37.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_mux.3740165391
Short name T163
Test name
Test status
Simulation time 346978655 ps
CPU time 8.56 seconds
Started Jun 10 05:49:20 PM PDT 24
Finished Jun 10 05:49:29 PM PDT 24
Peak memory 226540 kb
Host smart-18659786-a408-467b-bb1c-a5a58343dc82
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740165391 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_mux.
3740165391
Directory /workspace/37.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/37.lc_ctrl_security_escalation.3209299116
Short name T171
Test name
Test status
Simulation time 385320074 ps
CPU time 8.84 seconds
Started Jun 10 05:49:16 PM PDT 24
Finished Jun 10 05:49:26 PM PDT 24
Peak memory 226548 kb
Host smart-76765b3e-7b61-4c81-b078-1c1760895fed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209299116 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_security_escalation.3209299116
Directory /workspace/37.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/37.lc_ctrl_smoke.549342246
Short name T708
Test name
Test status
Simulation time 122184921 ps
CPU time 2.63 seconds
Started Jun 10 05:49:13 PM PDT 24
Finished Jun 10 05:49:16 PM PDT 24
Peak memory 215232 kb
Host smart-7fbb97df-6af3-464a-9010-7716d218a7f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549342246 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_smoke.549342246
Directory /workspace/37.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_failure.3786599588
Short name T630
Test name
Test status
Simulation time 193059709 ps
CPU time 23.26 seconds
Started Jun 10 05:49:18 PM PDT 24
Finished Jun 10 05:49:41 PM PDT 24
Peak memory 251452 kb
Host smart-69256fc8-a751-4050-bb1c-1355ed0a25f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786599588 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_failure.3786599588
Directory /workspace/37.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_post_trans.1766259030
Short name T771
Test name
Test status
Simulation time 88050306 ps
CPU time 6.82 seconds
Started Jun 10 05:49:20 PM PDT 24
Finished Jun 10 05:49:27 PM PDT 24
Peak memory 247856 kb
Host smart-8e8ca2c3-6747-4f61-ae6d-aa45c80349da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766259030 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_post_trans.1766259030
Directory /workspace/37.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all.2753292065
Short name T560
Test name
Test status
Simulation time 38580826981 ps
CPU time 144.91 seconds
Started Jun 10 05:49:17 PM PDT 24
Finished Jun 10 05:51:42 PM PDT 24
Peak memory 284300 kb
Host smart-23e8fd7f-c566-4661-9356-35956c5bc367
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753292065 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.lc_ctrl_stress_all.2753292065
Directory /workspace/37.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.lc_ctrl_volatile_unlock_smoke.2734870996
Short name T483
Test name
Test status
Simulation time 42426530 ps
CPU time 0.82 seconds
Started Jun 10 05:49:20 PM PDT 24
Finished Jun 10 05:49:21 PM PDT 24
Peak memory 209180 kb
Host smart-889ad14b-bb71-45bb-b85f-b49041481dcf
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734870996 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_c
trl_volatile_unlock_smoke.2734870996
Directory /workspace/37.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_alert_test.3513861727
Short name T344
Test name
Test status
Simulation time 26055485 ps
CPU time 1.32 seconds
Started Jun 10 05:49:21 PM PDT 24
Finished Jun 10 05:49:23 PM PDT 24
Peak memory 209616 kb
Host smart-cbf459e2-2be8-40b5-9c07-83836c02651b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513861727 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_alert_test.3513861727
Directory /workspace/38.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.lc_ctrl_errors.2236247414
Short name T535
Test name
Test status
Simulation time 335239033 ps
CPU time 11.93 seconds
Started Jun 10 05:49:21 PM PDT 24
Finished Jun 10 05:49:34 PM PDT 24
Peak memory 218636 kb
Host smart-a32e4075-44e1-4877-917d-c2b326dbb15e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236247414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_errors.2236247414
Directory /workspace/38.lc_ctrl_errors/latest

Test location /workspace/coverage/default/38.lc_ctrl_jtag_access.3742478129
Short name T266
Test name
Test status
Simulation time 97162617 ps
CPU time 3.03 seconds
Started Jun 10 05:49:18 PM PDT 24
Finished Jun 10 05:49:21 PM PDT 24
Peak memory 217540 kb
Host smart-f255b640-dd6f-4c0b-b666-079f5f29b040
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742478129 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_jtag_access.3742478129
Directory /workspace/38.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/38.lc_ctrl_prog_failure.1927888732
Short name T239
Test name
Test status
Simulation time 230043317 ps
CPU time 2.95 seconds
Started Jun 10 05:49:19 PM PDT 24
Finished Jun 10 05:49:22 PM PDT 24
Peak memory 222636 kb
Host smart-c2a413ec-6400-48e4-92e5-96e41ca023a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927888732 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_prog_failure.1927888732
Directory /workspace/38.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_mubi.1367927174
Short name T540
Test name
Test status
Simulation time 1084268245 ps
CPU time 14.37 seconds
Started Jun 10 05:49:22 PM PDT 24
Finished Jun 10 05:49:36 PM PDT 24
Peak memory 218636 kb
Host smart-33bee7e5-ebe4-4333-ab81-17fc4a633172
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367927174 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_mubi.1367927174
Directory /workspace/38.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_digest.90731227
Short name T587
Test name
Test status
Simulation time 361545812 ps
CPU time 12.83 seconds
Started Jun 10 05:49:22 PM PDT 24
Finished Jun 10 05:49:35 PM PDT 24
Peak memory 218736 kb
Host smart-a1046339-0b9a-4854-987b-117c3698dee3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90731227 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_dig
est_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_dig
est.90731227
Directory /workspace/38.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_mux.872241352
Short name T842
Test name
Test status
Simulation time 534977637 ps
CPU time 10.88 seconds
Started Jun 10 05:49:20 PM PDT 24
Finished Jun 10 05:49:31 PM PDT 24
Peak memory 218644 kb
Host smart-53989018-667e-4449-abee-071c299121c7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872241352 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_mux.872241352
Directory /workspace/38.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/38.lc_ctrl_security_escalation.3525236703
Short name T643
Test name
Test status
Simulation time 207830659 ps
CPU time 9.19 seconds
Started Jun 10 05:49:22 PM PDT 24
Finished Jun 10 05:49:31 PM PDT 24
Peak memory 226372 kb
Host smart-3ca6e912-2ef8-46d6-9397-d8517598abbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525236703 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_security_escalation.3525236703
Directory /workspace/38.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/38.lc_ctrl_smoke.2884675211
Short name T85
Test name
Test status
Simulation time 225889143 ps
CPU time 2.86 seconds
Started Jun 10 05:49:18 PM PDT 24
Finished Jun 10 05:49:21 PM PDT 24
Peak memory 218188 kb
Host smart-cf168622-6ff0-4d5c-8fdb-7becfd9b92d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2884675211 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_smoke.2884675211
Directory /workspace/38.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_failure.2395428623
Short name T157
Test name
Test status
Simulation time 852257985 ps
CPU time 19.88 seconds
Started Jun 10 05:49:16 PM PDT 24
Finished Jun 10 05:49:36 PM PDT 24
Peak memory 251408 kb
Host smart-b428304e-a8c4-4b2e-8dcf-89e6e0e1f459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395428623 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_failure.2395428623
Directory /workspace/38.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_post_trans.3889702630
Short name T398
Test name
Test status
Simulation time 282898973 ps
CPU time 2.89 seconds
Started Jun 10 05:49:22 PM PDT 24
Finished Jun 10 05:49:25 PM PDT 24
Peak memory 222576 kb
Host smart-3da181ba-aae7-4b8c-9c84-bcf152e65807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889702630 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_post_trans.3889702630
Directory /workspace/38.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all.4050187065
Short name T334
Test name
Test status
Simulation time 39614913633 ps
CPU time 51.73 seconds
Started Jun 10 05:49:21 PM PDT 24
Finished Jun 10 05:50:13 PM PDT 24
Peak memory 220016 kb
Host smart-29afb7a0-6135-4925-87b9-b48da7bc003b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050187065 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.lc_ctrl_stress_all.4050187065
Directory /workspace/38.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.lc_ctrl_volatile_unlock_smoke.2353686714
Short name T341
Test name
Test status
Simulation time 48921227 ps
CPU time 0.95 seconds
Started Jun 10 05:49:21 PM PDT 24
Finished Jun 10 05:49:22 PM PDT 24
Peak memory 212296 kb
Host smart-5ed21d5f-88b7-49d4-9e2d-4ec65632825b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353686714 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_c
trl_volatile_unlock_smoke.2353686714
Directory /workspace/38.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_alert_test.3540652262
Short name T400
Test name
Test status
Simulation time 21844531 ps
CPU time 1.16 seconds
Started Jun 10 05:49:24 PM PDT 24
Finished Jun 10 05:49:25 PM PDT 24
Peak memory 209392 kb
Host smart-f4d64249-de8a-4a1b-9815-c30d5452240b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540652262 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_alert_test.3540652262
Directory /workspace/39.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.lc_ctrl_errors.185089418
Short name T787
Test name
Test status
Simulation time 247241694 ps
CPU time 11.53 seconds
Started Jun 10 05:49:22 PM PDT 24
Finished Jun 10 05:49:34 PM PDT 24
Peak memory 218688 kb
Host smart-3b1226d1-6da5-46ca-8bdf-81e6b7fce053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185089418 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_errors.185089418
Directory /workspace/39.lc_ctrl_errors/latest

Test location /workspace/coverage/default/39.lc_ctrl_jtag_access.582193194
Short name T187
Test name
Test status
Simulation time 247208000 ps
CPU time 7.35 seconds
Started Jun 10 05:49:27 PM PDT 24
Finished Jun 10 05:49:35 PM PDT 24
Peak memory 217876 kb
Host smart-2487c96c-e292-494f-a1a6-8f4560ee2b91
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582193194 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_jtag_access.582193194
Directory /workspace/39.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/39.lc_ctrl_prog_failure.442956660
Short name T437
Test name
Test status
Simulation time 138527753 ps
CPU time 2.9 seconds
Started Jun 10 05:49:23 PM PDT 24
Finished Jun 10 05:49:26 PM PDT 24
Peak memory 222780 kb
Host smart-0f87ced6-0301-4523-8da0-d1970fbfbbff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442956660 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_prog_failure.442956660
Directory /workspace/39.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_mubi.3019096502
Short name T556
Test name
Test status
Simulation time 220358528 ps
CPU time 11.01 seconds
Started Jun 10 05:49:28 PM PDT 24
Finished Jun 10 05:49:39 PM PDT 24
Peak memory 218808 kb
Host smart-087cb340-6b46-4bd4-aba4-326e7ff6a6d8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019096502 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_mubi.3019096502
Directory /workspace/39.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_digest.3627030676
Short name T262
Test name
Test status
Simulation time 803819309 ps
CPU time 14.25 seconds
Started Jun 10 05:49:26 PM PDT 24
Finished Jun 10 05:49:40 PM PDT 24
Peak memory 218644 kb
Host smart-94bb6d4b-ffb2-44ea-833e-907313c19076
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627030676 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_d
igest.3627030676
Directory /workspace/39.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_mux.1553939782
Short name T510
Test name
Test status
Simulation time 272889620 ps
CPU time 11.07 seconds
Started Jun 10 05:49:26 PM PDT 24
Finished Jun 10 05:49:37 PM PDT 24
Peak memory 226468 kb
Host smart-5dbb48c1-4bf1-400c-af75-cb5cc2cb9f87
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553939782 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_mux.
1553939782
Directory /workspace/39.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/39.lc_ctrl_security_escalation.449118150
Short name T835
Test name
Test status
Simulation time 1327817963 ps
CPU time 8.94 seconds
Started Jun 10 05:49:24 PM PDT 24
Finished Jun 10 05:49:33 PM PDT 24
Peak memory 226640 kb
Host smart-bed16a5e-6d45-42f9-a2d3-837b3849c578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449118150 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_security_escalation.449118150
Directory /workspace/39.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/39.lc_ctrl_smoke.575501545
Short name T773
Test name
Test status
Simulation time 60714523 ps
CPU time 2.22 seconds
Started Jun 10 05:49:19 PM PDT 24
Finished Jun 10 05:49:21 PM PDT 24
Peak memory 218224 kb
Host smart-a93529de-c477-43ab-8d7b-1c37a05face0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575501545 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_smoke.575501545
Directory /workspace/39.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_failure.2140194024
Short name T95
Test name
Test status
Simulation time 855529227 ps
CPU time 25.49 seconds
Started Jun 10 05:49:26 PM PDT 24
Finished Jun 10 05:49:52 PM PDT 24
Peak memory 251420 kb
Host smart-db415382-af6b-42e9-818f-bfe2569df3e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140194024 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_failure.2140194024
Directory /workspace/39.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_post_trans.3776647643
Short name T866
Test name
Test status
Simulation time 237164224 ps
CPU time 8.01 seconds
Started Jun 10 05:49:27 PM PDT 24
Finished Jun 10 05:49:36 PM PDT 24
Peak memory 251364 kb
Host smart-67622917-b7f7-465d-bb17-22f1956a1952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776647643 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_post_trans.3776647643
Directory /workspace/39.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all.4159571501
Short name T346
Test name
Test status
Simulation time 2347284047 ps
CPU time 72.39 seconds
Started Jun 10 05:49:24 PM PDT 24
Finished Jun 10 05:50:37 PM PDT 24
Peak memory 251376 kb
Host smart-3b065637-e1f1-4745-b98a-0c2fb44e0317
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159571501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.lc_ctrl_stress_all.4159571501
Directory /workspace/39.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.lc_ctrl_volatile_unlock_smoke.3306397320
Short name T803
Test name
Test status
Simulation time 26824569 ps
CPU time 1.15 seconds
Started Jun 10 05:49:24 PM PDT 24
Finished Jun 10 05:49:25 PM PDT 24
Peak memory 218240 kb
Host smart-10d0b9de-dfd0-4d7f-9c81-23d651a5fc0e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306397320 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_c
trl_volatile_unlock_smoke.3306397320
Directory /workspace/39.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_alert_test.2376286408
Short name T821
Test name
Test status
Simulation time 197579429 ps
CPU time 0.87 seconds
Started Jun 10 05:46:58 PM PDT 24
Finished Jun 10 05:46:59 PM PDT 24
Peak memory 209300 kb
Host smart-b1e9fefc-ce4f-41cb-93e4-e1e7ed8607d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376286408 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_alert_test.2376286408
Directory /workspace/4.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.lc_ctrl_claim_transition_if.3104505188
Short name T828
Test name
Test status
Simulation time 42226922 ps
CPU time 0.91 seconds
Started Jun 10 05:46:49 PM PDT 24
Finished Jun 10 05:46:50 PM PDT 24
Peak memory 209408 kb
Host smart-05c62093-5901-445f-83ad-e400ea1566e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104505188 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_claim_transition_if.3104505188
Directory /workspace/4.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/4.lc_ctrl_errors.2206816317
Short name T485
Test name
Test status
Simulation time 506014377 ps
CPU time 13.86 seconds
Started Jun 10 05:46:52 PM PDT 24
Finished Jun 10 05:47:06 PM PDT 24
Peak memory 226520 kb
Host smart-adb9bbce-33d1-4db6-b1e7-6927879460bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206816317 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_errors.2206816317
Directory /workspace/4.lc_ctrl_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_access.3777407614
Short name T502
Test name
Test status
Simulation time 1364614188 ps
CPU time 10.5 seconds
Started Jun 10 05:46:54 PM PDT 24
Finished Jun 10 05:47:05 PM PDT 24
Peak memory 217716 kb
Host smart-92b0bcc3-a23c-471f-b3bf-0f40e4e78c5f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777407614 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_access.3777407614
Directory /workspace/4.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_errors.267274658
Short name T4
Test name
Test status
Simulation time 4503162642 ps
CPU time 33.21 seconds
Started Jun 10 05:46:48 PM PDT 24
Finished Jun 10 05:47:22 PM PDT 24
Peak memory 219452 kb
Host smart-51cba089-167e-4018-b591-85337fc47058
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267274658 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_err
ors.267274658
Directory /workspace/4.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_priority.1948008183
Short name T360
Test name
Test status
Simulation time 3835483352 ps
CPU time 3.9 seconds
Started Jun 10 05:46:49 PM PDT 24
Finished Jun 10 05:46:53 PM PDT 24
Peak memory 218368 kb
Host smart-65eee4d3-cb94-400f-9fe1-4dbc5fe7b397
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948008183 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_priority.1
948008183
Directory /workspace/4.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_prog_failure.215419503
Short name T705
Test name
Test status
Simulation time 3493177443 ps
CPU time 11.52 seconds
Started Jun 10 05:46:53 PM PDT 24
Finished Jun 10 05:47:05 PM PDT 24
Peak memory 218800 kb
Host smart-00a21b09-07ed-446f-bdf4-d3dae1d4ebbe
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215419503 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_
prog_failure.215419503
Directory /workspace/4.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_regwen_during_op.3208727444
Short name T388
Test name
Test status
Simulation time 1429094533 ps
CPU time 20 seconds
Started Jun 10 05:46:53 PM PDT 24
Finished Jun 10 05:47:14 PM PDT 24
Peak memory 218040 kb
Host smart-bdbfdb18-1ee9-4242-9562-8d82192f2afe
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208727444 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_regwen_during_op.3208727444
Directory /workspace/4.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_smoke.2419614353
Short name T621
Test name
Test status
Simulation time 513046036 ps
CPU time 3.63 seconds
Started Jun 10 05:46:51 PM PDT 24
Finished Jun 10 05:46:55 PM PDT 24
Peak memory 218220 kb
Host smart-1ac93927-77db-491f-9068-bac84a69d70d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419614353 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_smoke.
2419614353
Directory /workspace/4.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_failure.2101179421
Short name T795
Test name
Test status
Simulation time 17882077474 ps
CPU time 75.95 seconds
Started Jun 10 05:46:54 PM PDT 24
Finished Jun 10 05:48:10 PM PDT 24
Peak memory 284244 kb
Host smart-9a08f88f-436b-41fa-a1ee-0af8de1a5a47
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101179421 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jta
g_state_failure.2101179421
Directory /workspace/4.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_post_trans.2896615072
Short name T481
Test name
Test status
Simulation time 2072842150 ps
CPU time 18.82 seconds
Started Jun 10 05:46:54 PM PDT 24
Finished Jun 10 05:47:13 PM PDT 24
Peak memory 224988 kb
Host smart-0f9f8724-17bd-4ced-87cf-34a46a366630
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896615072 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_state_post_trans.2896615072
Directory /workspace/4.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_prog_failure.496659099
Short name T695
Test name
Test status
Simulation time 163571438 ps
CPU time 3.07 seconds
Started Jun 10 05:46:51 PM PDT 24
Finished Jun 10 05:46:55 PM PDT 24
Peak memory 218604 kb
Host smart-100f2159-381c-49f8-a158-ace85f3e8b4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496659099 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_prog_failure.496659099
Directory /workspace/4.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_regwen_during_op.1406058348
Short name T464
Test name
Test status
Simulation time 437102062 ps
CPU time 11.71 seconds
Started Jun 10 05:46:54 PM PDT 24
Finished Jun 10 05:47:06 PM PDT 24
Peak memory 218236 kb
Host smart-99d26b89-86a6-4bc6-80fa-17349e8a2274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406058348 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_regwen_during_op.1406058348
Directory /workspace/4.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_cm.2195294469
Short name T107
Test name
Test status
Simulation time 217837478 ps
CPU time 35.35 seconds
Started Jun 10 05:46:55 PM PDT 24
Finished Jun 10 05:47:31 PM PDT 24
Peak memory 282548 kb
Host smart-62a494c4-448a-4574-83b9-b0422f8355ec
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195294469 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_cm.2195294469
Directory /workspace/4.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_mubi.367078121
Short name T461
Test name
Test status
Simulation time 478988849 ps
CPU time 13.57 seconds
Started Jun 10 05:46:57 PM PDT 24
Finished Jun 10 05:47:11 PM PDT 24
Peak memory 226556 kb
Host smart-3cf65c02-32b4-417c-9a7d-52ec4f5def6f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367078121 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_mubi.367078121
Directory /workspace/4.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_digest.2376776038
Short name T225
Test name
Test status
Simulation time 367300569 ps
CPU time 14.35 seconds
Started Jun 10 05:46:58 PM PDT 24
Finished Jun 10 05:47:13 PM PDT 24
Peak memory 218644 kb
Host smart-4d90ff4f-8e8b-49e6-bef3-30c8bd1175d4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376776038 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_di
gest.2376776038
Directory /workspace/4.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_mux.802879805
Short name T386
Test name
Test status
Simulation time 400263534 ps
CPU time 14.62 seconds
Started Jun 10 05:46:56 PM PDT 24
Finished Jun 10 05:47:11 PM PDT 24
Peak memory 218776 kb
Host smart-430a1fe1-6eb0-477a-ac5a-b907b7e30c75
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802879805 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_mux.802879805
Directory /workspace/4.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/4.lc_ctrl_security_escalation.145106035
Short name T308
Test name
Test status
Simulation time 948659358 ps
CPU time 9.99 seconds
Started Jun 10 05:46:49 PM PDT 24
Finished Jun 10 05:47:00 PM PDT 24
Peak memory 218828 kb
Host smart-666b2d17-bb9b-4e65-a5d9-0f85df112ff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145106035 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_security_escalation.145106035
Directory /workspace/4.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/4.lc_ctrl_smoke.4198599536
Short name T528
Test name
Test status
Simulation time 141266259 ps
CPU time 1.1 seconds
Started Jun 10 05:46:49 PM PDT 24
Finished Jun 10 05:46:50 PM PDT 24
Peak memory 212824 kb
Host smart-eb5a91d8-d76b-4462-a05f-e8b913a14dae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198599536 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_smoke.4198599536
Directory /workspace/4.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_failure.4187502401
Short name T88
Test name
Test status
Simulation time 1467489651 ps
CPU time 24.96 seconds
Started Jun 10 05:46:52 PM PDT 24
Finished Jun 10 05:47:17 PM PDT 24
Peak memory 251372 kb
Host smart-e34df672-0148-4d33-a7c3-a10d3207b3a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187502401 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_failure.4187502401
Directory /workspace/4.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_post_trans.913229077
Short name T856
Test name
Test status
Simulation time 170036108 ps
CPU time 3.13 seconds
Started Jun 10 05:46:51 PM PDT 24
Finished Jun 10 05:46:55 PM PDT 24
Peak memory 218636 kb
Host smart-2e6d821b-f318-4537-90f8-6b8106e9c174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913229077 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_post_trans.913229077
Directory /workspace/4.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_stress_all.2418218244
Short name T94
Test name
Test status
Simulation time 1511892361 ps
CPU time 67.28 seconds
Started Jun 10 05:46:57 PM PDT 24
Finished Jun 10 05:48:05 PM PDT 24
Peak memory 251340 kb
Host smart-7d6afcab-e5fd-4945-b218-03fa27d3264e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418218244 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.lc_ctrl_stress_all.2418218244
Directory /workspace/4.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.lc_ctrl_volatile_unlock_smoke.2339157158
Short name T168
Test name
Test status
Simulation time 15968081 ps
CPU time 1 seconds
Started Jun 10 05:46:52 PM PDT 24
Finished Jun 10 05:46:54 PM PDT 24
Peak memory 218352 kb
Host smart-8eff8306-9e60-4f33-9658-dfbb6e59a246
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339157158 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ct
rl_volatile_unlock_smoke.2339157158
Directory /workspace/4.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_alert_test.3551199731
Short name T505
Test name
Test status
Simulation time 20265740 ps
CPU time 1.12 seconds
Started Jun 10 05:49:28 PM PDT 24
Finished Jun 10 05:49:29 PM PDT 24
Peak memory 209468 kb
Host smart-69e989cf-db2d-4df3-be8f-48fab29a80bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551199731 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_alert_test.3551199731
Directory /workspace/40.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.lc_ctrl_errors.4245911044
Short name T584
Test name
Test status
Simulation time 1623432473 ps
CPU time 11.97 seconds
Started Jun 10 05:49:23 PM PDT 24
Finished Jun 10 05:49:36 PM PDT 24
Peak memory 218664 kb
Host smart-fe46b5f3-1906-428b-a67a-8b72c789fa5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245911044 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_errors.4245911044
Directory /workspace/40.lc_ctrl_errors/latest

Test location /workspace/coverage/default/40.lc_ctrl_jtag_access.2511572280
Short name T843
Test name
Test status
Simulation time 325437908 ps
CPU time 4.65 seconds
Started Jun 10 05:49:32 PM PDT 24
Finished Jun 10 05:49:38 PM PDT 24
Peak memory 217800 kb
Host smart-c1f1c830-e195-4f89-aba4-3d24e4929616
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511572280 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_jtag_access.2511572280
Directory /workspace/40.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/40.lc_ctrl_prog_failure.2394900944
Short name T539
Test name
Test status
Simulation time 420356955 ps
CPU time 4.5 seconds
Started Jun 10 05:49:28 PM PDT 24
Finished Jun 10 05:49:33 PM PDT 24
Peak memory 218680 kb
Host smart-4d1c37a5-2706-494b-806d-566f1f22e258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394900944 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_prog_failure.2394900944
Directory /workspace/40.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_mubi.1729369875
Short name T805
Test name
Test status
Simulation time 403030154 ps
CPU time 13.68 seconds
Started Jun 10 05:49:27 PM PDT 24
Finished Jun 10 05:49:41 PM PDT 24
Peak memory 219588 kb
Host smart-c80e2106-075a-4033-9e5c-296e4e2b968b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729369875 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_mubi.1729369875
Directory /workspace/40.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_digest.2118736148
Short name T357
Test name
Test status
Simulation time 369783418 ps
CPU time 14.56 seconds
Started Jun 10 05:49:28 PM PDT 24
Finished Jun 10 05:49:43 PM PDT 24
Peak memory 218656 kb
Host smart-368cd499-db3d-47d7-9baa-88e5ffa06775
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118736148 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_d
igest.2118736148
Directory /workspace/40.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_mux.3603642198
Short name T300
Test name
Test status
Simulation time 380866213 ps
CPU time 14.32 seconds
Started Jun 10 05:49:31 PM PDT 24
Finished Jun 10 05:49:46 PM PDT 24
Peak memory 218644 kb
Host smart-2095eefb-17f0-4555-ad3c-56f3a7d901fc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603642198 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_mux.
3603642198
Directory /workspace/40.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/40.lc_ctrl_security_escalation.3493103119
Short name T809
Test name
Test status
Simulation time 1156187420 ps
CPU time 10.21 seconds
Started Jun 10 05:49:29 PM PDT 24
Finished Jun 10 05:49:39 PM PDT 24
Peak memory 218760 kb
Host smart-7e5ab60f-e8bd-4129-94b4-bf9e3e85b785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493103119 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_security_escalation.3493103119
Directory /workspace/40.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/40.lc_ctrl_smoke.501461080
Short name T851
Test name
Test status
Simulation time 906472776 ps
CPU time 6.29 seconds
Started Jun 10 05:49:23 PM PDT 24
Finished Jun 10 05:49:30 PM PDT 24
Peak memory 218216 kb
Host smart-689853af-4e8c-4e4d-8359-8d3811257cc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501461080 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_smoke.501461080
Directory /workspace/40.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_failure.1064550927
Short name T712
Test name
Test status
Simulation time 1076454167 ps
CPU time 20.13 seconds
Started Jun 10 05:49:22 PM PDT 24
Finished Jun 10 05:49:42 PM PDT 24
Peak memory 251452 kb
Host smart-e86a59f5-8275-4967-a1cb-1f2b23996060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064550927 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_failure.1064550927
Directory /workspace/40.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_post_trans.2779859102
Short name T313
Test name
Test status
Simulation time 121831146 ps
CPU time 6.84 seconds
Started Jun 10 05:49:22 PM PDT 24
Finished Jun 10 05:49:29 PM PDT 24
Peak memory 250988 kb
Host smart-10c5e533-a77d-4404-89c5-1fe74caf797b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779859102 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_post_trans.2779859102
Directory /workspace/40.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/40.lc_ctrl_stress_all.3683896528
Short name T850
Test name
Test status
Simulation time 11289138894 ps
CPU time 109.68 seconds
Started Jun 10 05:49:33 PM PDT 24
Finished Jun 10 05:51:23 PM PDT 24
Peak memory 278652 kb
Host smart-e650a992-6804-416e-ae38-a5e6aa2810f2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683896528 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.lc_ctrl_stress_all.3683896528
Directory /workspace/40.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.lc_ctrl_volatile_unlock_smoke.3225226691
Short name T861
Test name
Test status
Simulation time 19078769 ps
CPU time 0.9 seconds
Started Jun 10 05:49:26 PM PDT 24
Finished Jun 10 05:49:28 PM PDT 24
Peak memory 209608 kb
Host smart-02488f8c-01b0-4a72-91ca-24f18e882ce8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225226691 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_c
trl_volatile_unlock_smoke.3225226691
Directory /workspace/40.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_alert_test.2496540120
Short name T846
Test name
Test status
Simulation time 16919067 ps
CPU time 1.08 seconds
Started Jun 10 05:49:30 PM PDT 24
Finished Jun 10 05:49:32 PM PDT 24
Peak memory 209440 kb
Host smart-e6b62106-3316-470e-9759-870a37b330c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496540120 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_alert_test.2496540120
Directory /workspace/41.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.lc_ctrl_errors.2191108014
Short name T46
Test name
Test status
Simulation time 706171393 ps
CPU time 7.97 seconds
Started Jun 10 05:49:33 PM PDT 24
Finished Jun 10 05:49:42 PM PDT 24
Peak memory 218672 kb
Host smart-8413c6f0-4bc3-40de-bc22-3287bf3ba5b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191108014 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_errors.2191108014
Directory /workspace/41.lc_ctrl_errors/latest

Test location /workspace/coverage/default/41.lc_ctrl_jtag_access.2540879002
Short name T257
Test name
Test status
Simulation time 150244776 ps
CPU time 2.63 seconds
Started Jun 10 05:49:31 PM PDT 24
Finished Jun 10 05:49:34 PM PDT 24
Peak memory 217492 kb
Host smart-b876bb24-d01f-4f14-8811-6c466da29922
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540879002 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_jtag_access.2540879002
Directory /workspace/41.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/41.lc_ctrl_prog_failure.4169434892
Short name T829
Test name
Test status
Simulation time 226881230 ps
CPU time 2.96 seconds
Started Jun 10 05:49:30 PM PDT 24
Finished Jun 10 05:49:33 PM PDT 24
Peak memory 223008 kb
Host smart-b94b48a2-e550-4737-a9ed-f6a519eec177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169434892 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_prog_failure.4169434892
Directory /workspace/41.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_mubi.2532933651
Short name T768
Test name
Test status
Simulation time 256122168 ps
CPU time 8.24 seconds
Started Jun 10 05:49:28 PM PDT 24
Finished Jun 10 05:49:37 PM PDT 24
Peak memory 226552 kb
Host smart-3af49cb4-f9fa-403b-be35-3b7f7f8857b3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532933651 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_mubi.2532933651
Directory /workspace/41.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_digest.1498356456
Short name T2
Test name
Test status
Simulation time 390839621 ps
CPU time 7.9 seconds
Started Jun 10 05:49:30 PM PDT 24
Finished Jun 10 05:49:38 PM PDT 24
Peak memory 218712 kb
Host smart-202e136a-f91a-4e7f-b781-84623721c76d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498356456 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_d
igest.1498356456
Directory /workspace/41.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_mux.1491259706
Short name T512
Test name
Test status
Simulation time 454087076 ps
CPU time 7.95 seconds
Started Jun 10 05:49:28 PM PDT 24
Finished Jun 10 05:49:36 PM PDT 24
Peak memory 218724 kb
Host smart-e1290a44-39d9-4c5f-878b-a150b3fc8dd3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491259706 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_mux.
1491259706
Directory /workspace/41.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/41.lc_ctrl_security_escalation.2139156413
Short name T730
Test name
Test status
Simulation time 850578326 ps
CPU time 9.3 seconds
Started Jun 10 05:49:28 PM PDT 24
Finished Jun 10 05:49:37 PM PDT 24
Peak memory 225872 kb
Host smart-7aa32c26-9cf0-45f1-965f-620b6ef817e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139156413 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_security_escalation.2139156413
Directory /workspace/41.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/41.lc_ctrl_smoke.951879219
Short name T254
Test name
Test status
Simulation time 1000948980 ps
CPU time 5.08 seconds
Started Jun 10 05:49:30 PM PDT 24
Finished Jun 10 05:49:35 PM PDT 24
Peak memory 218232 kb
Host smart-2c75e20a-3306-454e-a4e0-e410c0b48d76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951879219 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_smoke.951879219
Directory /workspace/41.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_failure.1185763163
Short name T429
Test name
Test status
Simulation time 1514196146 ps
CPU time 23.05 seconds
Started Jun 10 05:49:32 PM PDT 24
Finished Jun 10 05:49:55 PM PDT 24
Peak memory 251432 kb
Host smart-8b0218ef-3850-4de2-a33c-b56e70d2a7bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185763163 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_failure.1185763163
Directory /workspace/41.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_post_trans.975407326
Short name T427
Test name
Test status
Simulation time 90328184 ps
CPU time 3.62 seconds
Started Jun 10 05:49:34 PM PDT 24
Finished Jun 10 05:49:38 PM PDT 24
Peak memory 218648 kb
Host smart-334f79be-7432-4ea0-98a5-7e9c6ad99655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975407326 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_post_trans.975407326
Directory /workspace/41.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all.2958793448
Short name T309
Test name
Test status
Simulation time 70187879761 ps
CPU time 208.92 seconds
Started Jun 10 05:49:30 PM PDT 24
Finished Jun 10 05:52:59 PM PDT 24
Peak memory 267848 kb
Host smart-bc154b9c-d601-4de8-9aa4-ec9b58daa796
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958793448 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.lc_ctrl_stress_all.2958793448
Directory /workspace/41.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.lc_ctrl_volatile_unlock_smoke.1418477714
Short name T780
Test name
Test status
Simulation time 40802337 ps
CPU time 0.98 seconds
Started Jun 10 05:49:31 PM PDT 24
Finished Jun 10 05:49:32 PM PDT 24
Peak memory 212296 kb
Host smart-84b5e819-6f2e-48a2-a0df-e75a0152b834
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418477714 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_c
trl_volatile_unlock_smoke.1418477714
Directory /workspace/41.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_alert_test.3071589808
Short name T618
Test name
Test status
Simulation time 47945619 ps
CPU time 1.16 seconds
Started Jun 10 05:49:32 PM PDT 24
Finished Jun 10 05:49:35 PM PDT 24
Peak memory 209392 kb
Host smart-78ab2e15-6e81-4206-ae2d-160d2c31a26b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071589808 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_alert_test.3071589808
Directory /workspace/42.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.lc_ctrl_errors.882338884
Short name T380
Test name
Test status
Simulation time 1044242022 ps
CPU time 14.67 seconds
Started Jun 10 05:49:32 PM PDT 24
Finished Jun 10 05:49:48 PM PDT 24
Peak memory 218672 kb
Host smart-398fcbab-0663-4408-9a98-879278a744bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882338884 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_errors.882338884
Directory /workspace/42.lc_ctrl_errors/latest

Test location /workspace/coverage/default/42.lc_ctrl_jtag_access.3004376352
Short name T607
Test name
Test status
Simulation time 1505776695 ps
CPU time 10.29 seconds
Started Jun 10 05:49:36 PM PDT 24
Finished Jun 10 05:49:47 PM PDT 24
Peak memory 217904 kb
Host smart-15f4ddd0-d491-44db-b83b-b0e429387739
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004376352 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_jtag_access.3004376352
Directory /workspace/42.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/42.lc_ctrl_prog_failure.2394727506
Short name T30
Test name
Test status
Simulation time 281367522 ps
CPU time 5.04 seconds
Started Jun 10 05:49:32 PM PDT 24
Finished Jun 10 05:49:38 PM PDT 24
Peak memory 218732 kb
Host smart-c12744ea-e927-4631-8deb-22baba59a409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394727506 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_prog_failure.2394727506
Directory /workspace/42.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_mubi.113833097
Short name T47
Test name
Test status
Simulation time 1224837429 ps
CPU time 15.12 seconds
Started Jun 10 05:49:31 PM PDT 24
Finished Jun 10 05:49:46 PM PDT 24
Peak memory 226596 kb
Host smart-a6cdd59b-de95-4e02-888e-eaede9f5c03d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113833097 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_mubi.113833097
Directory /workspace/42.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_digest.2472776678
Short name T176
Test name
Test status
Simulation time 1516702258 ps
CPU time 14.93 seconds
Started Jun 10 05:49:33 PM PDT 24
Finished Jun 10 05:49:48 PM PDT 24
Peak memory 226472 kb
Host smart-91229386-f7a7-4377-b98b-712f7335eda5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472776678 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_d
igest.2472776678
Directory /workspace/42.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_mux.29703273
Short name T277
Test name
Test status
Simulation time 1263720109 ps
CPU time 7.76 seconds
Started Jun 10 05:49:33 PM PDT 24
Finished Jun 10 05:49:42 PM PDT 24
Peak memory 225136 kb
Host smart-a61f91ac-b40b-4d16-aa13-a669ff4b81fe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29703273 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_mux.29703273
Directory /workspace/42.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/42.lc_ctrl_security_escalation.3614591067
Short name T463
Test name
Test status
Simulation time 403161853 ps
CPU time 9.52 seconds
Started Jun 10 05:49:29 PM PDT 24
Finished Jun 10 05:49:39 PM PDT 24
Peak memory 225524 kb
Host smart-2940633d-048f-4a2d-b197-bcfec7b46d61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614591067 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_security_escalation.3614591067
Directory /workspace/42.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/42.lc_ctrl_smoke.2139762164
Short name T69
Test name
Test status
Simulation time 439452766 ps
CPU time 1.89 seconds
Started Jun 10 05:49:34 PM PDT 24
Finished Jun 10 05:49:36 PM PDT 24
Peak memory 214732 kb
Host smart-fa4fdc57-ade4-42cf-8962-05c49e3da461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139762164 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_smoke.2139762164
Directory /workspace/42.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_failure.809848525
Short name T601
Test name
Test status
Simulation time 262636390 ps
CPU time 16.51 seconds
Started Jun 10 05:49:33 PM PDT 24
Finished Jun 10 05:49:51 PM PDT 24
Peak memory 251424 kb
Host smart-8d8098a9-1609-4866-bc19-3738c1b447e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809848525 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_failure.809848525
Directory /workspace/42.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_post_trans.3927248802
Short name T525
Test name
Test status
Simulation time 601795660 ps
CPU time 7.25 seconds
Started Jun 10 05:49:36 PM PDT 24
Finished Jun 10 05:49:44 PM PDT 24
Peak memory 250780 kb
Host smart-99970e5d-958b-49c3-951d-ccb3e6fb3c9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927248802 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_post_trans.3927248802
Directory /workspace/42.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/42.lc_ctrl_stress_all.901225957
Short name T183
Test name
Test status
Simulation time 14999856268 ps
CPU time 482.26 seconds
Started Jun 10 05:49:32 PM PDT 24
Finished Jun 10 05:57:35 PM PDT 24
Peak memory 264868 kb
Host smart-d317c163-fa27-48c1-93ce-9d63612752f6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901225957 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.lc_ctrl_stress_all.901225957
Directory /workspace/42.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.lc_ctrl_volatile_unlock_smoke.903992343
Short name T783
Test name
Test status
Simulation time 40364555 ps
CPU time 1 seconds
Started Jun 10 05:49:30 PM PDT 24
Finished Jun 10 05:49:32 PM PDT 24
Peak memory 212356 kb
Host smart-408637cb-a855-4011-a9f2-a27a9bb51e10
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903992343 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ct
rl_volatile_unlock_smoke.903992343
Directory /workspace/42.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_alert_test.2620340761
Short name T180
Test name
Test status
Simulation time 20627357 ps
CPU time 1.03 seconds
Started Jun 10 05:49:36 PM PDT 24
Finished Jun 10 05:49:37 PM PDT 24
Peak memory 209608 kb
Host smart-bb6a1f0b-e69f-4730-b656-3203dfb8de5d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620340761 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_alert_test.2620340761
Directory /workspace/43.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.lc_ctrl_errors.2752940091
Short name T848
Test name
Test status
Simulation time 1115823539 ps
CPU time 12.65 seconds
Started Jun 10 05:49:31 PM PDT 24
Finished Jun 10 05:49:45 PM PDT 24
Peak memory 218600 kb
Host smart-c84b06ee-4bea-4665-9b05-7b90157819ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752940091 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_errors.2752940091
Directory /workspace/43.lc_ctrl_errors/latest

Test location /workspace/coverage/default/43.lc_ctrl_jtag_access.4221665795
Short name T462
Test name
Test status
Simulation time 186875145 ps
CPU time 2.99 seconds
Started Jun 10 05:49:38 PM PDT 24
Finished Jun 10 05:49:42 PM PDT 24
Peak memory 217624 kb
Host smart-a3407a3f-b1c3-42f7-a012-9673a9d339c1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221665795 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_jtag_access.4221665795
Directory /workspace/43.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/43.lc_ctrl_prog_failure.3241856151
Short name T108
Test name
Test status
Simulation time 285443255 ps
CPU time 2.19 seconds
Started Jun 10 05:49:32 PM PDT 24
Finished Jun 10 05:49:34 PM PDT 24
Peak memory 218712 kb
Host smart-e76f5b14-ffd1-45d4-9805-d3963a44306d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241856151 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_prog_failure.3241856151
Directory /workspace/43.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_mubi.842041743
Short name T399
Test name
Test status
Simulation time 971134830 ps
CPU time 10.39 seconds
Started Jun 10 05:49:34 PM PDT 24
Finished Jun 10 05:49:45 PM PDT 24
Peak memory 218676 kb
Host smart-21806cce-38b0-43e8-8b2d-84c3bca3848c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842041743 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_mubi.842041743
Directory /workspace/43.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_digest.2332593783
Short name T606
Test name
Test status
Simulation time 368223065 ps
CPU time 11.41 seconds
Started Jun 10 05:49:37 PM PDT 24
Finished Jun 10 05:49:49 PM PDT 24
Peak memory 218748 kb
Host smart-8da21f7c-55e8-4f5e-9e51-753220d27c2a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332593783 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_d
igest.2332593783
Directory /workspace/43.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_mux.1909889542
Short name T222
Test name
Test status
Simulation time 445974239 ps
CPU time 15.57 seconds
Started Jun 10 05:49:34 PM PDT 24
Finished Jun 10 05:49:51 PM PDT 24
Peak memory 218716 kb
Host smart-87ef95d3-516e-4713-adee-674169dd07fa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909889542 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_mux.
1909889542
Directory /workspace/43.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/43.lc_ctrl_security_escalation.512504774
Short name T212
Test name
Test status
Simulation time 1488077445 ps
CPU time 9.86 seconds
Started Jun 10 05:49:32 PM PDT 24
Finished Jun 10 05:49:42 PM PDT 24
Peak memory 226656 kb
Host smart-a0ed9643-6899-4e32-980a-7acb0223a113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512504774 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_security_escalation.512504774
Directory /workspace/43.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/43.lc_ctrl_smoke.842468353
Short name T391
Test name
Test status
Simulation time 59454735 ps
CPU time 3.37 seconds
Started Jun 10 05:49:33 PM PDT 24
Finished Jun 10 05:49:38 PM PDT 24
Peak memory 223176 kb
Host smart-4b6c52db-afec-4066-8aa2-f1aa399c801c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842468353 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_smoke.842468353
Directory /workspace/43.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_failure.2104785769
Short name T550
Test name
Test status
Simulation time 163580263 ps
CPU time 21.27 seconds
Started Jun 10 05:49:33 PM PDT 24
Finished Jun 10 05:49:55 PM PDT 24
Peak memory 251428 kb
Host smart-4156ab3d-3f9b-47f2-ac6e-9a1154102c75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104785769 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_failure.2104785769
Directory /workspace/43.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_post_trans.1031940545
Short name T255
Test name
Test status
Simulation time 164166486 ps
CPU time 6.43 seconds
Started Jun 10 05:49:33 PM PDT 24
Finished Jun 10 05:49:40 PM PDT 24
Peak memory 250832 kb
Host smart-980080b9-2648-47d2-aded-5eba83463124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031940545 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_post_trans.1031940545
Directory /workspace/43.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all.1654868836
Short name T372
Test name
Test status
Simulation time 33071394063 ps
CPU time 142.29 seconds
Started Jun 10 05:49:35 PM PDT 24
Finished Jun 10 05:51:58 PM PDT 24
Peak memory 284248 kb
Host smart-900b0335-9839-463f-8188-3867c4fb703b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654868836 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.lc_ctrl_stress_all.1654868836
Directory /workspace/43.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.lc_ctrl_volatile_unlock_smoke.460555538
Short name T38
Test name
Test status
Simulation time 94170440 ps
CPU time 0.88 seconds
Started Jun 10 05:49:32 PM PDT 24
Finished Jun 10 05:49:34 PM PDT 24
Peak memory 209596 kb
Host smart-f2c5a477-94ec-4a1f-983d-0d61948d45e2
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460555538 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ct
rl_volatile_unlock_smoke.460555538
Directory /workspace/43.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_alert_test.885391215
Short name T385
Test name
Test status
Simulation time 55347431 ps
CPU time 1.15 seconds
Started Jun 10 05:49:38 PM PDT 24
Finished Jun 10 05:49:40 PM PDT 24
Peak memory 209532 kb
Host smart-ead5a707-4efb-4334-a1da-9e24ce54aca3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885391215 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_alert_test.885391215
Directory /workspace/44.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.lc_ctrl_errors.1148321475
Short name T690
Test name
Test status
Simulation time 2947765498 ps
CPU time 16.61 seconds
Started Jun 10 05:49:41 PM PDT 24
Finished Jun 10 05:49:58 PM PDT 24
Peak memory 219456 kb
Host smart-575f3d71-d004-419a-ab8d-ba227108ea6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148321475 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_errors.1148321475
Directory /workspace/44.lc_ctrl_errors/latest

Test location /workspace/coverage/default/44.lc_ctrl_jtag_access.3568272543
Short name T10
Test name
Test status
Simulation time 1421315203 ps
CPU time 1.71 seconds
Started Jun 10 05:49:40 PM PDT 24
Finished Jun 10 05:49:42 PM PDT 24
Peak memory 217532 kb
Host smart-7650eaf8-eb60-4f2c-b27d-ee25fb3c2ff5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568272543 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_jtag_access.3568272543
Directory /workspace/44.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/44.lc_ctrl_prog_failure.4010870146
Short name T287
Test name
Test status
Simulation time 92144638 ps
CPU time 2.21 seconds
Started Jun 10 05:49:35 PM PDT 24
Finished Jun 10 05:49:38 PM PDT 24
Peak memory 222496 kb
Host smart-fe9df4b7-205f-4ef1-9fc9-c2a71963ba14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010870146 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_prog_failure.4010870146
Directory /workspace/44.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_mubi.3644202440
Short name T532
Test name
Test status
Simulation time 277307520 ps
CPU time 14.21 seconds
Started Jun 10 05:49:35 PM PDT 24
Finished Jun 10 05:49:50 PM PDT 24
Peak memory 219416 kb
Host smart-934d5278-a867-4fa3-951d-9c1e15cc775a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644202440 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_mubi.3644202440
Directory /workspace/44.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_digest.3490075838
Short name T41
Test name
Test status
Simulation time 465537359 ps
CPU time 18.77 seconds
Started Jun 10 05:49:37 PM PDT 24
Finished Jun 10 05:49:56 PM PDT 24
Peak memory 218756 kb
Host smart-0a3d6473-3b6f-4efb-acc5-d8dbf26bc490
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490075838 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_d
igest.3490075838
Directory /workspace/44.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_mux.827164065
Short name T762
Test name
Test status
Simulation time 811270171 ps
CPU time 13.9 seconds
Started Jun 10 05:49:38 PM PDT 24
Finished Jun 10 05:49:52 PM PDT 24
Peak memory 226544 kb
Host smart-7600de76-72ff-44ed-9a25-bd558b0361ee
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827164065 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_mux.827164065
Directory /workspace/44.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/44.lc_ctrl_security_escalation.2024677675
Short name T782
Test name
Test status
Simulation time 1187724441 ps
CPU time 7.13 seconds
Started Jun 10 05:49:38 PM PDT 24
Finished Jun 10 05:49:45 PM PDT 24
Peak memory 225392 kb
Host smart-95ae7554-a3e5-47b8-a55b-4d29d8500192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024677675 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_security_escalation.2024677675
Directory /workspace/44.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/44.lc_ctrl_smoke.1401461735
Short name T446
Test name
Test status
Simulation time 141824525 ps
CPU time 2.28 seconds
Started Jun 10 05:49:37 PM PDT 24
Finished Jun 10 05:49:40 PM PDT 24
Peak memory 214960 kb
Host smart-ca0f0654-c67d-4fd8-bce8-2038f18b90d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401461735 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_smoke.1401461735
Directory /workspace/44.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_failure.2255742478
Short name T676
Test name
Test status
Simulation time 789802459 ps
CPU time 22.98 seconds
Started Jun 10 05:49:37 PM PDT 24
Finished Jun 10 05:50:00 PM PDT 24
Peak memory 251312 kb
Host smart-d28ce95c-e9f5-4047-b088-53b8f51f64df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255742478 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_failure.2255742478
Directory /workspace/44.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_post_trans.91199766
Short name T285
Test name
Test status
Simulation time 77506796 ps
CPU time 6.59 seconds
Started Jun 10 05:49:40 PM PDT 24
Finished Jun 10 05:49:47 PM PDT 24
Peak memory 251368 kb
Host smart-884c6c2b-cfe9-4721-be71-2dd9e5ee145e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91199766 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_post_trans.91199766
Directory /workspace/44.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/44.lc_ctrl_stress_all.979885440
Short name T406
Test name
Test status
Simulation time 20970595751 ps
CPU time 175.24 seconds
Started Jun 10 05:49:36 PM PDT 24
Finished Jun 10 05:52:32 PM PDT 24
Peak memory 274060 kb
Host smart-8ed28c0d-a060-49e0-a758-39656db7e5ad
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979885440 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.lc_ctrl_stress_all.979885440
Directory /workspace/44.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.lc_ctrl_stress_all_with_rand_reset.759075405
Short name T52
Test name
Test status
Simulation time 8816704217 ps
CPU time 179.92 seconds
Started Jun 10 05:49:38 PM PDT 24
Finished Jun 10 05:52:38 PM PDT 24
Peak memory 270324 kb
Host smart-85091f24-99b5-4d51-942e-d05c864ee876
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=759075405 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_stress_all_with_rand_reset.759075405
Directory /workspace/44.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.lc_ctrl_volatile_unlock_smoke.3120143079
Short name T625
Test name
Test status
Simulation time 35780600 ps
CPU time 0.9 seconds
Started Jun 10 05:49:33 PM PDT 24
Finished Jun 10 05:49:35 PM PDT 24
Peak memory 209412 kb
Host smart-878764db-098e-4b4e-9f6d-df65faa50cd4
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120143079 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_c
trl_volatile_unlock_smoke.3120143079
Directory /workspace/44.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_alert_test.170145521
Short name T302
Test name
Test status
Simulation time 66956783 ps
CPU time 1.1 seconds
Started Jun 10 05:49:42 PM PDT 24
Finished Jun 10 05:49:43 PM PDT 24
Peak memory 209352 kb
Host smart-ef172c77-a620-49f9-ad8c-0387bb1eb0f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170145521 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_alert_test.170145521
Directory /workspace/45.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.lc_ctrl_errors.2423300218
Short name T867
Test name
Test status
Simulation time 1245067762 ps
CPU time 12.92 seconds
Started Jun 10 05:49:42 PM PDT 24
Finished Jun 10 05:49:55 PM PDT 24
Peak memory 218692 kb
Host smart-5b9906c4-dc4a-4e91-8e36-cea20428ae04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423300218 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_errors.2423300218
Directory /workspace/45.lc_ctrl_errors/latest

Test location /workspace/coverage/default/45.lc_ctrl_jtag_access.1228683881
Short name T538
Test name
Test status
Simulation time 2155998769 ps
CPU time 8.73 seconds
Started Jun 10 05:49:40 PM PDT 24
Finished Jun 10 05:49:50 PM PDT 24
Peak memory 218052 kb
Host smart-da03abd5-c85a-499e-ab2a-3ca0f13d7b2e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228683881 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_jtag_access.1228683881
Directory /workspace/45.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/45.lc_ctrl_prog_failure.2090076027
Short name T542
Test name
Test status
Simulation time 53056648 ps
CPU time 2.79 seconds
Started Jun 10 05:49:41 PM PDT 24
Finished Jun 10 05:49:45 PM PDT 24
Peak memory 218672 kb
Host smart-edcd32ec-39f6-4350-b50c-97b13b2e02c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090076027 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_prog_failure.2090076027
Directory /workspace/45.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_mubi.1431821948
Short name T342
Test name
Test status
Simulation time 1447049709 ps
CPU time 13.01 seconds
Started Jun 10 05:49:41 PM PDT 24
Finished Jun 10 05:49:54 PM PDT 24
Peak memory 219516 kb
Host smart-aac9534f-ab4a-4a5e-8394-90e6868acd32
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431821948 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_mubi.1431821948
Directory /workspace/45.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_digest.2019203671
Short name T247
Test name
Test status
Simulation time 214128895 ps
CPU time 9.38 seconds
Started Jun 10 05:49:40 PM PDT 24
Finished Jun 10 05:49:50 PM PDT 24
Peak memory 226568 kb
Host smart-027146ea-8369-49ca-9a88-098a02cbc1af
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019203671 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_d
igest.2019203671
Directory /workspace/45.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_mux.2327856557
Short name T700
Test name
Test status
Simulation time 2674458757 ps
CPU time 10.81 seconds
Started Jun 10 05:49:41 PM PDT 24
Finished Jun 10 05:49:52 PM PDT 24
Peak memory 226604 kb
Host smart-0748dc77-acbc-416f-9e30-1bff25b35002
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327856557 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_mux.
2327856557
Directory /workspace/45.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/45.lc_ctrl_security_escalation.1420839125
Short name T628
Test name
Test status
Simulation time 2744850017 ps
CPU time 8.5 seconds
Started Jun 10 05:49:39 PM PDT 24
Finished Jun 10 05:49:48 PM PDT 24
Peak memory 226648 kb
Host smart-efa8462f-f9bf-4284-93aa-5f74ab3e68f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420839125 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_security_escalation.1420839125
Directory /workspace/45.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/45.lc_ctrl_smoke.2609457939
Short name T616
Test name
Test status
Simulation time 21343858 ps
CPU time 1.26 seconds
Started Jun 10 05:49:41 PM PDT 24
Finished Jun 10 05:49:43 PM PDT 24
Peak memory 214056 kb
Host smart-4b22b419-31e0-436e-a583-afbf26816cde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609457939 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_smoke.2609457939
Directory /workspace/45.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_failure.3519022523
Short name T728
Test name
Test status
Simulation time 938390136 ps
CPU time 15.93 seconds
Started Jun 10 05:49:42 PM PDT 24
Finished Jun 10 05:49:58 PM PDT 24
Peak memory 251440 kb
Host smart-92666d0d-7333-4698-b753-01ccc35bd10f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519022523 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_failure.3519022523
Directory /workspace/45.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_post_trans.487906167
Short name T740
Test name
Test status
Simulation time 87317878 ps
CPU time 10.17 seconds
Started Jun 10 05:49:40 PM PDT 24
Finished Jun 10 05:49:50 PM PDT 24
Peak memory 244676 kb
Host smart-2cd2195c-dbd7-4d5a-a038-073071624e5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487906167 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_post_trans.487906167
Directory /workspace/45.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/45.lc_ctrl_stress_all.4057608059
Short name T853
Test name
Test status
Simulation time 8992867592 ps
CPU time 65.02 seconds
Started Jun 10 05:49:41 PM PDT 24
Finished Jun 10 05:50:46 PM PDT 24
Peak memory 251484 kb
Host smart-c3e0c9b1-245a-4693-9a46-b6c6309de1e1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057608059 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.lc_ctrl_stress_all.4057608059
Directory /workspace/45.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.lc_ctrl_stress_all_with_rand_reset.2609912608
Short name T683
Test name
Test status
Simulation time 15234543093 ps
CPU time 412.58 seconds
Started Jun 10 05:49:42 PM PDT 24
Finished Jun 10 05:56:35 PM PDT 24
Peak memory 389748 kb
Host smart-88909522-d2e8-4243-baf8-fcf165b58850
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2609912608 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_stress_all_with_rand_reset.2609912608
Directory /workspace/45.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.lc_ctrl_volatile_unlock_smoke.1859976494
Short name T44
Test name
Test status
Simulation time 42818837 ps
CPU time 0.94 seconds
Started Jun 10 05:49:44 PM PDT 24
Finished Jun 10 05:49:45 PM PDT 24
Peak memory 209596 kb
Host smart-3095a0cd-2780-43f3-905d-5015667a2f17
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859976494 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_c
trl_volatile_unlock_smoke.1859976494
Directory /workspace/45.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_alert_test.1149486728
Short name T596
Test name
Test status
Simulation time 50508914 ps
CPU time 1.36 seconds
Started Jun 10 05:49:45 PM PDT 24
Finished Jun 10 05:49:47 PM PDT 24
Peak memory 209512 kb
Host smart-4870b02f-909d-4f89-b7d2-5941146c9dc9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149486728 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_alert_test.1149486728
Directory /workspace/46.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.lc_ctrl_errors.3438396207
Short name T599
Test name
Test status
Simulation time 2398819067 ps
CPU time 22.98 seconds
Started Jun 10 05:49:48 PM PDT 24
Finished Jun 10 05:50:11 PM PDT 24
Peak memory 219404 kb
Host smart-544d6fab-db49-42ee-8fd9-e10f45d25fa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438396207 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_errors.3438396207
Directory /workspace/46.lc_ctrl_errors/latest

Test location /workspace/coverage/default/46.lc_ctrl_jtag_access.2608108886
Short name T519
Test name
Test status
Simulation time 1198425660 ps
CPU time 8.43 seconds
Started Jun 10 05:49:46 PM PDT 24
Finished Jun 10 05:49:55 PM PDT 24
Peak memory 217904 kb
Host smart-ecac593f-b5b9-4159-b322-e6094044a3fc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608108886 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_jtag_access.2608108886
Directory /workspace/46.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/46.lc_ctrl_prog_failure.2530082154
Short name T12
Test name
Test status
Simulation time 167656416 ps
CPU time 2.33 seconds
Started Jun 10 05:49:44 PM PDT 24
Finished Jun 10 05:49:46 PM PDT 24
Peak memory 222636 kb
Host smart-79454a54-a5ff-475e-896c-06cfb78fb29d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530082154 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_prog_failure.2530082154
Directory /workspace/46.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_mubi.1021352375
Short name T794
Test name
Test status
Simulation time 1066309801 ps
CPU time 13.08 seconds
Started Jun 10 05:49:46 PM PDT 24
Finished Jun 10 05:49:59 PM PDT 24
Peak memory 226556 kb
Host smart-5acf7f4a-06e8-405f-bae8-9f45532b7adc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021352375 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_mubi.1021352375
Directory /workspace/46.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_digest.1521522898
Short name T741
Test name
Test status
Simulation time 1140138825 ps
CPU time 10.59 seconds
Started Jun 10 05:49:48 PM PDT 24
Finished Jun 10 05:49:59 PM PDT 24
Peak memory 218676 kb
Host smart-fd365527-e4a8-4640-b7ba-5aa67bc96aa6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521522898 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_d
igest.1521522898
Directory /workspace/46.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_mux.1309794063
Short name T27
Test name
Test status
Simulation time 201341034 ps
CPU time 8.09 seconds
Started Jun 10 05:49:45 PM PDT 24
Finished Jun 10 05:49:53 PM PDT 24
Peak memory 218732 kb
Host smart-54eabd55-eb77-40b9-bc0d-5d2cfd469612
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309794063 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_mux.
1309794063
Directory /workspace/46.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/46.lc_ctrl_security_escalation.1120135815
Short name T638
Test name
Test status
Simulation time 1115997669 ps
CPU time 10.49 seconds
Started Jun 10 05:49:45 PM PDT 24
Finished Jun 10 05:49:56 PM PDT 24
Peak memory 225352 kb
Host smart-58ed8191-20d6-469a-aecd-1e13cab5083f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120135815 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_security_escalation.1120135815
Directory /workspace/46.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/46.lc_ctrl_smoke.386284054
Short name T811
Test name
Test status
Simulation time 20823209 ps
CPU time 1.64 seconds
Started Jun 10 05:49:40 PM PDT 24
Finished Jun 10 05:49:42 PM PDT 24
Peak memory 214636 kb
Host smart-ce4047cb-8c6e-44d9-8335-6faf46e21ecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386284054 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_smoke.386284054
Directory /workspace/46.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_failure.3745694884
Short name T178
Test name
Test status
Simulation time 261404827 ps
CPU time 32.23 seconds
Started Jun 10 05:49:43 PM PDT 24
Finished Jun 10 05:50:16 PM PDT 24
Peak memory 251444 kb
Host smart-ce5a4823-ffd7-4241-9a13-30e2bd430120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745694884 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_failure.3745694884
Directory /workspace/46.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_post_trans.254747942
Short name T439
Test name
Test status
Simulation time 114369163 ps
CPU time 3.33 seconds
Started Jun 10 05:49:44 PM PDT 24
Finished Jun 10 05:49:48 PM PDT 24
Peak memory 222712 kb
Host smart-6160605a-0f57-445d-bf88-476cf93f8249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254747942 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_post_trans.254747942
Directory /workspace/46.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/46.lc_ctrl_volatile_unlock_smoke.4268993638
Short name T790
Test name
Test status
Simulation time 29799923 ps
CPU time 0.9 seconds
Started Jun 10 05:49:41 PM PDT 24
Finished Jun 10 05:49:43 PM PDT 24
Peak memory 213388 kb
Host smart-3707494e-792f-4347-b516-5879a5e92a15
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268993638 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_c
trl_volatile_unlock_smoke.4268993638
Directory /workspace/46.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_alert_test.2198089412
Short name T170
Test name
Test status
Simulation time 86377964 ps
CPU time 1.12 seconds
Started Jun 10 05:49:49 PM PDT 24
Finished Jun 10 05:49:51 PM PDT 24
Peak memory 209416 kb
Host smart-5f070a2a-0ac0-4ec8-9351-34a0ca9bac9b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198089412 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_alert_test.2198089412
Directory /workspace/47.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.lc_ctrl_errors.2852629917
Short name T296
Test name
Test status
Simulation time 1407308279 ps
CPU time 11.4 seconds
Started Jun 10 05:49:50 PM PDT 24
Finished Jun 10 05:50:02 PM PDT 24
Peak memory 218540 kb
Host smart-d3f3d78d-41d8-4dcc-a08b-23cc9a4f5c5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852629917 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_errors.2852629917
Directory /workspace/47.lc_ctrl_errors/latest

Test location /workspace/coverage/default/47.lc_ctrl_jtag_access.2944806343
Short name T233
Test name
Test status
Simulation time 276647270 ps
CPU time 1.46 seconds
Started Jun 10 05:49:48 PM PDT 24
Finished Jun 10 05:49:50 PM PDT 24
Peak memory 217592 kb
Host smart-f903a4ed-8524-4922-8949-681363c64f7e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944806343 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_jtag_access.2944806343
Directory /workspace/47.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/47.lc_ctrl_prog_failure.3642202912
Short name T246
Test name
Test status
Simulation time 140990751 ps
CPU time 3.98 seconds
Started Jun 10 05:49:59 PM PDT 24
Finished Jun 10 05:50:03 PM PDT 24
Peak memory 222988 kb
Host smart-0f090628-856c-4523-a7ae-3a9c9a6f6434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642202912 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_prog_failure.3642202912
Directory /workspace/47.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_mubi.2383599552
Short name T634
Test name
Test status
Simulation time 680274057 ps
CPU time 16.97 seconds
Started Jun 10 05:49:59 PM PDT 24
Finished Jun 10 05:50:16 PM PDT 24
Peak memory 219400 kb
Host smart-7cd4f6fc-9d47-4384-963d-f0ab5201f162
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383599552 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_mubi.2383599552
Directory /workspace/47.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_digest.2433728479
Short name T495
Test name
Test status
Simulation time 2674222754 ps
CPU time 11.21 seconds
Started Jun 10 05:49:50 PM PDT 24
Finished Jun 10 05:50:01 PM PDT 24
Peak memory 218740 kb
Host smart-85883519-ad80-4967-b1b7-3b740cb89dc0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433728479 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_d
igest.2433728479
Directory /workspace/47.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_mux.648320105
Short name T350
Test name
Test status
Simulation time 443205258 ps
CPU time 7.79 seconds
Started Jun 10 05:49:50 PM PDT 24
Finished Jun 10 05:49:58 PM PDT 24
Peak memory 226552 kb
Host smart-3547103e-20b4-4007-b6d6-96b626c67ad1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648320105 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_mux.648320105
Directory /workspace/47.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/47.lc_ctrl_security_escalation.457491445
Short name T347
Test name
Test status
Simulation time 1558190309 ps
CPU time 9.27 seconds
Started Jun 10 05:49:46 PM PDT 24
Finished Jun 10 05:49:56 PM PDT 24
Peak memory 226524 kb
Host smart-d35d6024-e70b-4840-8e4a-93a0e2a928a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457491445 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_security_escalation.457491445
Directory /workspace/47.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/47.lc_ctrl_smoke.2367527198
Short name T545
Test name
Test status
Simulation time 25814374 ps
CPU time 2.35 seconds
Started Jun 10 05:49:46 PM PDT 24
Finished Jun 10 05:49:48 PM PDT 24
Peak memory 222740 kb
Host smart-056001d9-e90e-4f5e-9140-36ceeb1540c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367527198 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_smoke.2367527198
Directory /workspace/47.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_failure.589226350
Short name T680
Test name
Test status
Simulation time 284073981 ps
CPU time 28.1 seconds
Started Jun 10 05:49:46 PM PDT 24
Finished Jun 10 05:50:15 PM PDT 24
Peak memory 251456 kb
Host smart-b25c22c3-f87f-4871-ba1c-b7ed74325cce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589226350 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_failure.589226350
Directory /workspace/47.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_post_trans.923043109
Short name T802
Test name
Test status
Simulation time 76121681 ps
CPU time 8.14 seconds
Started Jun 10 05:49:44 PM PDT 24
Finished Jun 10 05:49:52 PM PDT 24
Peak memory 251456 kb
Host smart-d7d48009-9dd4-482f-a49c-b3be6dda3eac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923043109 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_post_trans.923043109
Directory /workspace/47.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/47.lc_ctrl_volatile_unlock_smoke.2727008621
Short name T499
Test name
Test status
Simulation time 15696854 ps
CPU time 0.89 seconds
Started Jun 10 05:49:46 PM PDT 24
Finished Jun 10 05:49:47 PM PDT 24
Peak memory 209664 kb
Host smart-0bf08135-d08e-470a-a3ce-2a2dbb0e8dd3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727008621 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_c
trl_volatile_unlock_smoke.2727008621
Directory /workspace/47.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_alert_test.4137474673
Short name T448
Test name
Test status
Simulation time 62233837 ps
CPU time 1.14 seconds
Started Jun 10 05:49:54 PM PDT 24
Finished Jun 10 05:49:56 PM PDT 24
Peak memory 209468 kb
Host smart-a5976fa4-96d4-4057-af41-621c9f7b6de3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137474673 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_alert_test.4137474673
Directory /workspace/48.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.lc_ctrl_errors.3580624937
Short name T292
Test name
Test status
Simulation time 268477527 ps
CPU time 10.98 seconds
Started Jun 10 05:49:45 PM PDT 24
Finished Jun 10 05:49:57 PM PDT 24
Peak memory 218732 kb
Host smart-a46f3ba3-ef86-4193-8a30-f6678ae2c448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580624937 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_errors.3580624937
Directory /workspace/48.lc_ctrl_errors/latest

Test location /workspace/coverage/default/48.lc_ctrl_jtag_access.2341249349
Short name T514
Test name
Test status
Simulation time 332958175 ps
CPU time 2.9 seconds
Started Jun 10 05:49:59 PM PDT 24
Finished Jun 10 05:50:02 PM PDT 24
Peak memory 217516 kb
Host smart-b1f4a1fb-9a82-485e-b199-e8796aeaadd2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341249349 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_jtag_access.2341249349
Directory /workspace/48.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/48.lc_ctrl_prog_failure.1231131834
Short name T320
Test name
Test status
Simulation time 352925626 ps
CPU time 3.46 seconds
Started Jun 10 05:49:59 PM PDT 24
Finished Jun 10 05:50:03 PM PDT 24
Peak memory 223256 kb
Host smart-28c3ebbf-3db1-48d3-8495-f1b35dd8be78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231131834 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_prog_failure.1231131834
Directory /workspace/48.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_mubi.859333742
Short name T830
Test name
Test status
Simulation time 1343022782 ps
CPU time 10.47 seconds
Started Jun 10 05:49:49 PM PDT 24
Finished Jun 10 05:50:00 PM PDT 24
Peak memory 226548 kb
Host smart-56b8669a-2f5c-473f-b687-d658bbb80357
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859333742 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_mubi.859333742
Directory /workspace/48.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_digest.3179568126
Short name T673
Test name
Test status
Simulation time 420390487 ps
CPU time 12.5 seconds
Started Jun 10 05:49:59 PM PDT 24
Finished Jun 10 05:50:12 PM PDT 24
Peak memory 218688 kb
Host smart-914eb644-8838-4c62-98e6-7d0aee6417a9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179568126 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_d
igest.3179568126
Directory /workspace/48.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_mux.2335761928
Short name T352
Test name
Test status
Simulation time 3881675427 ps
CPU time 10.55 seconds
Started Jun 10 05:49:49 PM PDT 24
Finished Jun 10 05:50:00 PM PDT 24
Peak memory 218788 kb
Host smart-220e7c24-b2e6-46bb-87ac-d2d99671e824
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335761928 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_mux.
2335761928
Directory /workspace/48.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/48.lc_ctrl_security_escalation.150094918
Short name T646
Test name
Test status
Simulation time 2849537424 ps
CPU time 7.85 seconds
Started Jun 10 05:49:50 PM PDT 24
Finished Jun 10 05:49:58 PM PDT 24
Peak memory 226628 kb
Host smart-e0778b30-e1ff-48e7-9069-91fc00d1d417
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150094918 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_security_escalation.150094918
Directory /workspace/48.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/48.lc_ctrl_smoke.3654726397
Short name T577
Test name
Test status
Simulation time 25268779 ps
CPU time 1.77 seconds
Started Jun 10 05:49:59 PM PDT 24
Finished Jun 10 05:50:01 PM PDT 24
Peak memory 218228 kb
Host smart-4f787725-78ca-4f25-b4b3-7a325515e22b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654726397 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_smoke.3654726397
Directory /workspace/48.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_failure.551898235
Short name T579
Test name
Test status
Simulation time 851175271 ps
CPU time 25.92 seconds
Started Jun 10 05:49:50 PM PDT 24
Finished Jun 10 05:50:16 PM PDT 24
Peak memory 251444 kb
Host smart-2e1b419b-e025-45ac-9520-5e2653134075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551898235 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_failure.551898235
Directory /workspace/48.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_post_trans.3827441646
Short name T471
Test name
Test status
Simulation time 102740733 ps
CPU time 3.61 seconds
Started Jun 10 05:49:51 PM PDT 24
Finished Jun 10 05:49:55 PM PDT 24
Peak memory 226864 kb
Host smart-43a7462b-93b2-43ec-ac41-f08702191adf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3827441646 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_post_trans.3827441646
Directory /workspace/48.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all.3816789017
Short name T282
Test name
Test status
Simulation time 5805128729 ps
CPU time 61.62 seconds
Started Jun 10 05:49:54 PM PDT 24
Finished Jun 10 05:50:56 PM PDT 24
Peak memory 251392 kb
Host smart-2f751671-fbab-479c-a6cb-248cd2b220ec
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816789017 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.lc_ctrl_stress_all.3816789017
Directory /workspace/48.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.lc_ctrl_volatile_unlock_smoke.67850003
Short name T674
Test name
Test status
Simulation time 36183126 ps
CPU time 0.77 seconds
Started Jun 10 05:50:00 PM PDT 24
Finished Jun 10 05:50:01 PM PDT 24
Peak memory 209192 kb
Host smart-7edc1a90-55ed-47a1-b701-3c10a9598534
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67850003 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vol
atile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctr
l_volatile_unlock_smoke.67850003
Directory /workspace/48.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_alert_test.4122635318
Short name T736
Test name
Test status
Simulation time 29717819 ps
CPU time 1.01 seconds
Started Jun 10 05:49:57 PM PDT 24
Finished Jun 10 05:49:58 PM PDT 24
Peak memory 209436 kb
Host smart-124946e0-eb10-4ed2-89b9-aee6179427f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122635318 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_alert_test.4122635318
Directory /workspace/49.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.lc_ctrl_errors.3898891817
Short name T692
Test name
Test status
Simulation time 3800605591 ps
CPU time 13.84 seconds
Started Jun 10 05:49:55 PM PDT 24
Finished Jun 10 05:50:09 PM PDT 24
Peak memory 219472 kb
Host smart-c147107f-02f8-4b9b-881b-9950e38b8967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898891817 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_errors.3898891817
Directory /workspace/49.lc_ctrl_errors/latest

Test location /workspace/coverage/default/49.lc_ctrl_jtag_access.4192545084
Short name T99
Test name
Test status
Simulation time 1267240758 ps
CPU time 8.09 seconds
Started Jun 10 05:49:59 PM PDT 24
Finished Jun 10 05:50:08 PM PDT 24
Peak memory 217620 kb
Host smart-061ddaef-6d6c-468e-89ea-c95cfae5bfe3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192545084 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_jtag_access.4192545084
Directory /workspace/49.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/49.lc_ctrl_prog_failure.911073232
Short name T243
Test name
Test status
Simulation time 287496406 ps
CPU time 2.84 seconds
Started Jun 10 05:49:55 PM PDT 24
Finished Jun 10 05:49:58 PM PDT 24
Peak memory 218700 kb
Host smart-69a405e3-c3d5-4ac9-9841-fd6985a8a6fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=911073232 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_prog_failure.911073232
Directory /workspace/49.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_mubi.2857530209
Short name T551
Test name
Test status
Simulation time 264192163 ps
CPU time 9.01 seconds
Started Jun 10 05:50:00 PM PDT 24
Finished Jun 10 05:50:09 PM PDT 24
Peak memory 218744 kb
Host smart-f22a4ff5-02d6-47fc-aad6-77bc1582b39d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857530209 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_mubi.2857530209
Directory /workspace/49.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_digest.2432920193
Short name T755
Test name
Test status
Simulation time 721379305 ps
CPU time 6.69 seconds
Started Jun 10 05:49:58 PM PDT 24
Finished Jun 10 05:50:05 PM PDT 24
Peak memory 218808 kb
Host smart-adcb8b2d-c624-4b1c-84a4-e70820c2b961
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432920193 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_d
igest.2432920193
Directory /workspace/49.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_mux.1216342394
Short name T769
Test name
Test status
Simulation time 1593234137 ps
CPU time 13.61 seconds
Started Jun 10 05:50:02 PM PDT 24
Finished Jun 10 05:50:16 PM PDT 24
Peak memory 218712 kb
Host smart-4a478413-b04d-40a6-97c9-8b547bf49164
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216342394 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_mux.
1216342394
Directory /workspace/49.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/49.lc_ctrl_security_escalation.3759969204
Short name T213
Test name
Test status
Simulation time 1408439348 ps
CPU time 12.42 seconds
Started Jun 10 05:49:58 PM PDT 24
Finished Jun 10 05:50:12 PM PDT 24
Peak memory 226488 kb
Host smart-de071090-e749-4cc4-89aa-80e82edee627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759969204 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_security_escalation.3759969204
Directory /workspace/49.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/49.lc_ctrl_smoke.4083754612
Short name T870
Test name
Test status
Simulation time 228455546 ps
CPU time 3.64 seconds
Started Jun 10 05:49:51 PM PDT 24
Finished Jun 10 05:49:55 PM PDT 24
Peak memory 218180 kb
Host smart-a6bd1016-c551-4ba2-9867-6f280ab15749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083754612 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_smoke.4083754612
Directory /workspace/49.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_failure.1043994130
Short name T478
Test name
Test status
Simulation time 415615925 ps
CPU time 26.63 seconds
Started Jun 10 05:49:52 PM PDT 24
Finished Jun 10 05:50:19 PM PDT 24
Peak memory 251432 kb
Host smart-f8db0300-1deb-4c9c-9050-1815f2951e66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043994130 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_failure.1043994130
Directory /workspace/49.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_post_trans.434410276
Short name T278
Test name
Test status
Simulation time 51756179 ps
CPU time 9.07 seconds
Started Jun 10 05:49:51 PM PDT 24
Finished Jun 10 05:50:00 PM PDT 24
Peak memory 251420 kb
Host smart-37232cef-0f6d-4948-a0dc-6b2e7fb633dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434410276 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_post_trans.434410276
Directory /workspace/49.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/49.lc_ctrl_stress_all.2288622070
Short name T63
Test name
Test status
Simulation time 18159191213 ps
CPU time 149.57 seconds
Started Jun 10 05:50:03 PM PDT 24
Finished Jun 10 05:52:33 PM PDT 24
Peak memory 283752 kb
Host smart-0978bf56-4d81-4115-b659-16e4b699c2f9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288622070 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.lc_ctrl_stress_all.2288622070
Directory /workspace/49.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.lc_ctrl_stress_all_with_rand_reset.16532720
Short name T111
Test name
Test status
Simulation time 21318366439 ps
CPU time 745.18 seconds
Started Jun 10 05:50:02 PM PDT 24
Finished Jun 10 06:02:27 PM PDT 24
Peak memory 284316 kb
Host smart-0e3101eb-c8be-4486-9736-ab9cc999d7ba
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=16532720 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_stress_all_with_rand_reset.16532720
Directory /workspace/49.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.lc_ctrl_volatile_unlock_smoke.1526051577
Short name T541
Test name
Test status
Simulation time 32680899 ps
CPU time 0.84 seconds
Started Jun 10 05:49:55 PM PDT 24
Finished Jun 10 05:49:56 PM PDT 24
Peak memory 209396 kb
Host smart-583227d7-3877-4694-92b8-63e7cb4d9967
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526051577 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_c
trl_volatile_unlock_smoke.1526051577
Directory /workspace/49.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_alert_test.215599184
Short name T753
Test name
Test status
Simulation time 22842970 ps
CPU time 1 seconds
Started Jun 10 05:47:00 PM PDT 24
Finished Jun 10 05:47:01 PM PDT 24
Peak memory 209528 kb
Host smart-48bee3a9-2225-498c-816c-91e74a11ff75
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215599184 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_alert_test.215599184
Directory /workspace/5.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.lc_ctrl_errors.2885603009
Short name T679
Test name
Test status
Simulation time 1025465885 ps
CPU time 11.75 seconds
Started Jun 10 05:46:59 PM PDT 24
Finished Jun 10 05:47:11 PM PDT 24
Peak memory 226548 kb
Host smart-f160c68f-9c11-4403-aff1-97963b5cfb8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885603009 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_errors.2885603009
Directory /workspace/5.lc_ctrl_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_access.3520311572
Short name T716
Test name
Test status
Simulation time 176124403 ps
CPU time 1.85 seconds
Started Jun 10 05:46:57 PM PDT 24
Finished Jun 10 05:46:59 PM PDT 24
Peak memory 217560 kb
Host smart-18e8cc78-d757-4d19-bea9-a117f395633c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520311572 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_access.3520311572
Directory /workspace/5.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_errors.181359567
Short name T765
Test name
Test status
Simulation time 3564675118 ps
CPU time 49.64 seconds
Started Jun 10 05:47:01 PM PDT 24
Finished Jun 10 05:47:51 PM PDT 24
Peak memory 219596 kb
Host smart-db98245f-3581-4b91-abd5-cc672d297489
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181359567 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_err
ors.181359567
Directory /workspace/5.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_priority.3989574274
Short name T7
Test name
Test status
Simulation time 1105384382 ps
CPU time 4.18 seconds
Started Jun 10 05:46:57 PM PDT 24
Finished Jun 10 05:47:02 PM PDT 24
Peak memory 217796 kb
Host smart-f76f848d-c038-4e23-b2f9-ddf1a92a3fbb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989574274 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_priority.3
989574274
Directory /workspace/5.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_prog_failure.3346706227
Short name T778
Test name
Test status
Simulation time 916548241 ps
CPU time 8.87 seconds
Started Jun 10 05:46:53 PM PDT 24
Finished Jun 10 05:47:02 PM PDT 24
Peak memory 218712 kb
Host smart-2b532445-5a09-475e-8cd9-cb7ed1df67da
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346706227 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag
_prog_failure.3346706227
Directory /workspace/5.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_regwen_during_op.51573382
Short name T232
Test name
Test status
Simulation time 15981322928 ps
CPU time 34.3 seconds
Started Jun 10 05:46:58 PM PDT 24
Finished Jun 10 05:47:33 PM PDT 24
Peak memory 218284 kb
Host smart-e0b5963d-a5d1-4fd6-9baa-c28ef4b421fc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51573382 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_r
egwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jt
ag_regwen_during_op.51573382
Directory /workspace/5.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_smoke.233614881
Short name T732
Test name
Test status
Simulation time 1763415997 ps
CPU time 8.21 seconds
Started Jun 10 05:46:57 PM PDT 24
Finished Jun 10 05:47:06 PM PDT 24
Peak memory 218272 kb
Host smart-5e03f34f-dbf6-4c7d-ae4e-96c89098e6b4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233614881 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_smoke.233614881
Directory /workspace/5.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_failure.3366738080
Short name T458
Test name
Test status
Simulation time 6253991310 ps
CPU time 41.44 seconds
Started Jun 10 05:46:58 PM PDT 24
Finished Jun 10 05:47:40 PM PDT 24
Peak memory 284236 kb
Host smart-bec9c450-01a9-42a2-bc1f-fc1f942d1dd3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366738080 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jta
g_state_failure.3366738080
Directory /workspace/5.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_post_trans.544890038
Short name T423
Test name
Test status
Simulation time 445703702 ps
CPU time 8.34 seconds
Started Jun 10 05:47:01 PM PDT 24
Finished Jun 10 05:47:10 PM PDT 24
Peak memory 223504 kb
Host smart-00903735-f698-4f41-ba1c-7f397f3e83c3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544890038 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_j
tag_state_post_trans.544890038
Directory /workspace/5.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_prog_failure.3275305739
Short name T871
Test name
Test status
Simulation time 33763909 ps
CPU time 2.43 seconds
Started Jun 10 05:46:56 PM PDT 24
Finished Jun 10 05:46:59 PM PDT 24
Peak memory 218668 kb
Host smart-ca4b0c07-ddf3-4638-8629-7aa6a7015b42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275305739 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_prog_failure.3275305739
Directory /workspace/5.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_regwen_during_op.4250054080
Short name T698
Test name
Test status
Simulation time 1766204492 ps
CPU time 13.47 seconds
Started Jun 10 05:46:58 PM PDT 24
Finished Jun 10 05:47:12 PM PDT 24
Peak memory 215112 kb
Host smart-a6aa0542-3d94-412c-aecb-426e05c863ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250054080 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_regwen_during_op.4250054080
Directory /workspace/5.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_mubi.359594486
Short name T820
Test name
Test status
Simulation time 276785995 ps
CPU time 14.45 seconds
Started Jun 10 05:46:59 PM PDT 24
Finished Jun 10 05:47:14 PM PDT 24
Peak memory 219400 kb
Host smart-8ae2c2c9-64ac-4bfb-9cce-045cd8181246
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359594486 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_mubi.359594486
Directory /workspace/5.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_digest.3612546560
Short name T217
Test name
Test status
Simulation time 555443496 ps
CPU time 12.99 seconds
Started Jun 10 05:47:01 PM PDT 24
Finished Jun 10 05:47:15 PM PDT 24
Peak memory 218760 kb
Host smart-e1623270-0cbd-4fc5-bfc7-1de717e970b1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612546560 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_di
gest.3612546560
Directory /workspace/5.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_mux.1175022578
Short name T177
Test name
Test status
Simulation time 312404454 ps
CPU time 8.11 seconds
Started Jun 10 05:47:00 PM PDT 24
Finished Jun 10 05:47:09 PM PDT 24
Peak memory 218676 kb
Host smart-eadc1655-116d-456a-b67b-18396fb28649
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175022578 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_mux.1
175022578
Directory /workspace/5.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/5.lc_ctrl_security_escalation.1312555386
Short name T55
Test name
Test status
Simulation time 1025051769 ps
CPU time 13.05 seconds
Started Jun 10 05:46:52 PM PDT 24
Finished Jun 10 05:47:05 PM PDT 24
Peak memory 218812 kb
Host smart-ba4488a2-3e20-431e-88c9-3d5f6f3e52b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312555386 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_security_escalation.1312555386
Directory /workspace/5.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/5.lc_ctrl_smoke.720471773
Short name T816
Test name
Test status
Simulation time 190278091 ps
CPU time 4 seconds
Started Jun 10 05:46:56 PM PDT 24
Finished Jun 10 05:47:01 PM PDT 24
Peak memory 218232 kb
Host smart-57ceacb5-1bcf-4c86-b0e1-bb232f87eafa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720471773 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_smoke.720471773
Directory /workspace/5.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_failure.367165400
Short name T553
Test name
Test status
Simulation time 813514470 ps
CPU time 23.48 seconds
Started Jun 10 05:46:54 PM PDT 24
Finished Jun 10 05:47:18 PM PDT 24
Peak memory 251444 kb
Host smart-2d32df4f-74c0-4841-ac4b-9e35828dabab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367165400 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_failure.367165400
Directory /workspace/5.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_post_trans.37859759
Short name T747
Test name
Test status
Simulation time 221600769 ps
CPU time 6.2 seconds
Started Jun 10 05:46:57 PM PDT 24
Finished Jun 10 05:47:03 PM PDT 24
Peak memory 247348 kb
Host smart-f37192cd-8913-489c-8df0-c2ecbbd3f495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37859759 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_post_trans.37859759
Directory /workspace/5.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_stress_all.3271768309
Short name T706
Test name
Test status
Simulation time 16073223959 ps
CPU time 175.94 seconds
Started Jun 10 05:47:00 PM PDT 24
Finished Jun 10 05:49:56 PM PDT 24
Peak memory 276196 kb
Host smart-742bebfb-7643-4eee-90a3-9ffbb5a586ef
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271768309 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.lc_ctrl_stress_all.3271768309
Directory /workspace/5.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.lc_ctrl_volatile_unlock_smoke.2387163712
Short name T772
Test name
Test status
Simulation time 13458335 ps
CPU time 1.08 seconds
Started Jun 10 05:46:54 PM PDT 24
Finished Jun 10 05:46:56 PM PDT 24
Peak memory 213392 kb
Host smart-565a3574-9790-4c76-ab2e-2081f072ad8e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387163712 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ct
rl_volatile_unlock_smoke.2387163712
Directory /workspace/5.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_alert_test.1112256873
Short name T793
Test name
Test status
Simulation time 93812429 ps
CPU time 1.23 seconds
Started Jun 10 05:47:20 PM PDT 24
Finished Jun 10 05:47:21 PM PDT 24
Peak memory 209388 kb
Host smart-db42aa89-c8cd-4d80-b1da-0b1a9d23354b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112256873 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_alert_test.1112256873
Directory /workspace/6.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.lc_ctrl_claim_transition_if.2836804017
Short name T561
Test name
Test status
Simulation time 48373632 ps
CPU time 0.81 seconds
Started Jun 10 05:47:04 PM PDT 24
Finished Jun 10 05:47:05 PM PDT 24
Peak memory 209488 kb
Host smart-784a7ea0-c727-464f-acf2-eeddb03323fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836804017 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_claim_transition_if.2836804017
Directory /workspace/6.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/6.lc_ctrl_errors.402734839
Short name T179
Test name
Test status
Simulation time 770593651 ps
CPU time 12.43 seconds
Started Jun 10 05:47:04 PM PDT 24
Finished Jun 10 05:47:16 PM PDT 24
Peak memory 218760 kb
Host smart-9a41e9d8-0262-4dbe-8dae-7c57c544ad95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402734839 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_errors.402734839
Directory /workspace/6.lc_ctrl_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_access.2922197643
Short name T629
Test name
Test status
Simulation time 1604620468 ps
CPU time 9.78 seconds
Started Jun 10 05:47:09 PM PDT 24
Finished Jun 10 05:47:19 PM PDT 24
Peak memory 217884 kb
Host smart-0f72ac9f-ca1d-4142-88e5-94257e571f71
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922197643 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_access.2922197643
Directory /workspace/6.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_errors.3899185918
Short name T265
Test name
Test status
Simulation time 2859686935 ps
CPU time 46.52 seconds
Started Jun 10 05:47:08 PM PDT 24
Finished Jun 10 05:47:54 PM PDT 24
Peak memory 219424 kb
Host smart-cb3b22d4-fc61-42be-9da4-a5978bb0aa9c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899185918 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_er
rors.3899185918
Directory /workspace/6.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_priority.757750015
Short name T642
Test name
Test status
Simulation time 723721672 ps
CPU time 5.36 seconds
Started Jun 10 05:47:09 PM PDT 24
Finished Jun 10 05:47:15 PM PDT 24
Peak memory 218112 kb
Host smart-e8578801-5dd8-4fdb-ac8b-ba9a48b75e50
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757750015 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_priority.757750015
Directory /workspace/6.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_prog_failure.111602885
Short name T567
Test name
Test status
Simulation time 514347637 ps
CPU time 8 seconds
Started Jun 10 05:47:14 PM PDT 24
Finished Jun 10 05:47:22 PM PDT 24
Peak memory 222368 kb
Host smart-73408061-692b-4b48-a6f3-035bdc38625e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111602885 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_
prog_failure.111602885
Directory /workspace/6.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_regwen_during_op.2336035061
Short name T662
Test name
Test status
Simulation time 660597134 ps
CPU time 10.84 seconds
Started Jun 10 05:47:11 PM PDT 24
Finished Jun 10 05:47:22 PM PDT 24
Peak memory 218140 kb
Host smart-5dd310ed-3677-452d-a46e-192bb9705d87
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336035061 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_regwen_during_op.2336035061
Directory /workspace/6.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_smoke.4072426754
Short name T84
Test name
Test status
Simulation time 113104283 ps
CPU time 3.95 seconds
Started Jun 10 05:47:13 PM PDT 24
Finished Jun 10 05:47:17 PM PDT 24
Peak memory 218240 kb
Host smart-d95c879a-455f-4502-9eca-527876341049
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072426754 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_smoke.
4072426754
Directory /workspace/6.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_failure.700186386
Short name T718
Test name
Test status
Simulation time 2003469949 ps
CPU time 28.92 seconds
Started Jun 10 05:47:20 PM PDT 24
Finished Jun 10 05:47:50 PM PDT 24
Peak memory 251448 kb
Host smart-54e62597-862d-4574-90c1-723b55e19e3f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700186386 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag
_state_failure.700186386
Directory /workspace/6.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_post_trans.1925968485
Short name T440
Test name
Test status
Simulation time 1135493229 ps
CPU time 21.3 seconds
Started Jun 10 05:47:12 PM PDT 24
Finished Jun 10 05:47:34 PM PDT 24
Peak memory 248416 kb
Host smart-12f2eb61-ef49-472d-8210-2f77433d2c68
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925968485 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_state_post_trans.1925968485
Directory /workspace/6.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_prog_failure.1073232874
Short name T833
Test name
Test status
Simulation time 452501965 ps
CPU time 3.01 seconds
Started Jun 10 05:47:00 PM PDT 24
Finished Jun 10 05:47:03 PM PDT 24
Peak memory 222544 kb
Host smart-34eda271-aca3-4dd8-931b-ae83430371d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073232874 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_prog_failure.1073232874
Directory /workspace/6.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_regwen_during_op.3651436241
Short name T354
Test name
Test status
Simulation time 284633865 ps
CPU time 8.74 seconds
Started Jun 10 05:47:04 PM PDT 24
Finished Jun 10 05:47:13 PM PDT 24
Peak memory 218224 kb
Host smart-44a61623-20ed-4d05-bca7-e062f43a88f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651436241 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_regwen_during_op.3651436241
Directory /workspace/6.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_digest.2170598964
Short name T250
Test name
Test status
Simulation time 3376458452 ps
CPU time 22.48 seconds
Started Jun 10 05:47:11 PM PDT 24
Finished Jun 10 05:47:34 PM PDT 24
Peak memory 226604 kb
Host smart-9aef1b15-d13b-4f7d-a338-2a15d9314868
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170598964 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_di
gest.2170598964
Directory /workspace/6.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_mux.1451372427
Short name T849
Test name
Test status
Simulation time 508125043 ps
CPU time 10.73 seconds
Started Jun 10 05:47:11 PM PDT 24
Finished Jun 10 05:47:22 PM PDT 24
Peak memory 218744 kb
Host smart-c1e1ea74-8146-4447-b92e-f754fb78d7c1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451372427 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_mux.1
451372427
Directory /workspace/6.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/6.lc_ctrl_security_escalation.2856949131
Short name T684
Test name
Test status
Simulation time 1081008293 ps
CPU time 11.06 seconds
Started Jun 10 05:47:06 PM PDT 24
Finished Jun 10 05:47:17 PM PDT 24
Peak memory 218676 kb
Host smart-3369eb93-eabe-4059-bfda-89a1b187339e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856949131 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_security_escalation.2856949131
Directory /workspace/6.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/6.lc_ctrl_smoke.2224429293
Short name T70
Test name
Test status
Simulation time 13701241 ps
CPU time 1.03 seconds
Started Jun 10 05:47:01 PM PDT 24
Finished Jun 10 05:47:03 PM PDT 24
Peak memory 212488 kb
Host smart-deb13cc4-29a2-4851-a9bf-12e2b2e85197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224429293 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_smoke.2224429293
Directory /workspace/6.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_failure.1472861265
Short name T563
Test name
Test status
Simulation time 506243051 ps
CPU time 25.72 seconds
Started Jun 10 05:47:05 PM PDT 24
Finished Jun 10 05:47:31 PM PDT 24
Peak memory 251436 kb
Host smart-d186978f-4cb9-4b5f-bea3-bc0204136039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472861265 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_failure.1472861265
Directory /workspace/6.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_post_trans.2118343400
Short name T775
Test name
Test status
Simulation time 153689723 ps
CPU time 6.16 seconds
Started Jun 10 05:47:05 PM PDT 24
Finished Jun 10 05:47:12 PM PDT 24
Peak memory 246592 kb
Host smart-1812573b-130d-40ad-9a86-431abee8eb1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118343400 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_post_trans.2118343400
Directory /workspace/6.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all.2402962961
Short name T492
Test name
Test status
Simulation time 4548590291 ps
CPU time 39.41 seconds
Started Jun 10 05:47:13 PM PDT 24
Finished Jun 10 05:47:52 PM PDT 24
Peak memory 251504 kb
Host smart-f03a37d2-ff69-4900-ae68-2024b60bf6d4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402962961 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.lc_ctrl_stress_all.2402962961
Directory /workspace/6.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.lc_ctrl_volatile_unlock_smoke.1083854883
Short name T312
Test name
Test status
Simulation time 12175936 ps
CPU time 0.75 seconds
Started Jun 10 05:47:06 PM PDT 24
Finished Jun 10 05:47:07 PM PDT 24
Peak memory 208632 kb
Host smart-3535b471-9783-491c-882a-1cf778f5ca60
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083854883 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ct
rl_volatile_unlock_smoke.1083854883
Directory /workspace/6.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_alert_test.1885394929
Short name T104
Test name
Test status
Simulation time 17044621 ps
CPU time 1.05 seconds
Started Jun 10 05:47:20 PM PDT 24
Finished Jun 10 05:47:21 PM PDT 24
Peak memory 209452 kb
Host smart-715f5240-12e0-43b7-8365-000cbd4b68eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885394929 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_alert_test.1885394929
Directory /workspace/7.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.lc_ctrl_claim_transition_if.626073959
Short name T208
Test name
Test status
Simulation time 22722709 ps
CPU time 0.97 seconds
Started Jun 10 05:47:12 PM PDT 24
Finished Jun 10 05:47:13 PM PDT 24
Peak memory 209504 kb
Host smart-611ab8d2-f67c-4d36-85c3-bece637cf2c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626073959 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_claim_transition_if.626073959
Directory /workspace/7.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/7.lc_ctrl_errors.3446172052
Short name T759
Test name
Test status
Simulation time 1184099698 ps
CPU time 10.47 seconds
Started Jun 10 05:47:14 PM PDT 24
Finished Jun 10 05:47:25 PM PDT 24
Peak memory 218624 kb
Host smart-1c801a04-1bad-4be9-9026-66174e282504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446172052 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_errors.3446172052
Directory /workspace/7.lc_ctrl_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_access.3892879877
Short name T22
Test name
Test status
Simulation time 896520521 ps
CPU time 13.77 seconds
Started Jun 10 05:47:14 PM PDT 24
Finished Jun 10 05:47:29 PM PDT 24
Peak memory 217996 kb
Host smart-d27fa329-2610-4457-b2d6-1c0782a3e6cd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892879877 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_access.3892879877
Directory /workspace/7.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_errors.2452413876
Short name T301
Test name
Test status
Simulation time 7467099726 ps
CPU time 28.52 seconds
Started Jun 10 05:47:15 PM PDT 24
Finished Jun 10 05:47:44 PM PDT 24
Peak memory 218828 kb
Host smart-d6d81429-796f-43eb-bd6c-6705224fef0b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452413876 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_er
rors.2452413876
Directory /workspace/7.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_priority.221564252
Short name T441
Test name
Test status
Simulation time 916746590 ps
CPU time 2.46 seconds
Started Jun 10 05:47:14 PM PDT 24
Finished Jun 10 05:47:16 PM PDT 24
Peak memory 218268 kb
Host smart-f2561532-a8d8-49b0-abf0-542829c18bd4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221564252 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_priority.221564252
Directory /workspace/7.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_prog_failure.2540849937
Short name T283
Test name
Test status
Simulation time 199452268 ps
CPU time 4.77 seconds
Started Jun 10 05:47:12 PM PDT 24
Finished Jun 10 05:47:17 PM PDT 24
Peak memory 218708 kb
Host smart-684d1ecf-80ab-498b-b056-0976baad5343
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540849937 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag
_prog_failure.2540849937
Directory /workspace/7.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_regwen_during_op.133937144
Short name T80
Test name
Test status
Simulation time 3372985792 ps
CPU time 10.67 seconds
Started Jun 10 05:47:14 PM PDT 24
Finished Jun 10 05:47:25 PM PDT 24
Peak memory 218292 kb
Host smart-af3d1324-f3b5-4fe7-a8a7-7a0691e9050e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133937144 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_j
tag_regwen_during_op.133937144
Directory /workspace/7.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_smoke.3264051007
Short name T648
Test name
Test status
Simulation time 304989685 ps
CPU time 3.26 seconds
Started Jun 10 05:47:19 PM PDT 24
Finished Jun 10 05:47:23 PM PDT 24
Peak memory 218160 kb
Host smart-1df74101-7c38-46c5-9fa4-0361c426aaed
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264051007 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_smoke.
3264051007
Directory /workspace/7.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_failure.2136943142
Short name T534
Test name
Test status
Simulation time 2165514449 ps
CPU time 58.76 seconds
Started Jun 10 05:47:11 PM PDT 24
Finished Jun 10 05:48:10 PM PDT 24
Peak memory 276620 kb
Host smart-776013b5-34b3-479c-91d4-8c0549eacc94
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136943142 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jta
g_state_failure.2136943142
Directory /workspace/7.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_post_trans.3701970460
Short name T404
Test name
Test status
Simulation time 794183912 ps
CPU time 17.12 seconds
Started Jun 10 05:47:07 PM PDT 24
Finished Jun 10 05:47:25 PM PDT 24
Peak memory 250920 kb
Host smart-d310a3fa-3f41-4d39-9633-872fe2b76969
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701970460 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_state_post_trans.3701970460
Directory /workspace/7.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_prog_failure.1421063424
Short name T608
Test name
Test status
Simulation time 174421033 ps
CPU time 3.75 seconds
Started Jun 10 05:47:07 PM PDT 24
Finished Jun 10 05:47:11 PM PDT 24
Peak memory 218704 kb
Host smart-8ea6f626-8496-455d-b3c6-65b6b77b0b3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421063424 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_prog_failure.1421063424
Directory /workspace/7.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_regwen_during_op.2332030607
Short name T288
Test name
Test status
Simulation time 350199050 ps
CPU time 20.07 seconds
Started Jun 10 05:47:10 PM PDT 24
Finished Jun 10 05:47:30 PM PDT 24
Peak memory 215280 kb
Host smart-22272545-82c4-4d1a-a976-bd9c6e54c379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332030607 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_regwen_during_op.2332030607
Directory /workspace/7.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_mubi.298725097
Short name T615
Test name
Test status
Simulation time 283264958 ps
CPU time 13.19 seconds
Started Jun 10 05:47:16 PM PDT 24
Finished Jun 10 05:47:29 PM PDT 24
Peak memory 218760 kb
Host smart-2682e5e8-5133-4ac9-83a4-fe3b13332052
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298725097 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_mubi.298725097
Directory /workspace/7.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_digest.3999680144
Short name T100
Test name
Test status
Simulation time 220128288 ps
CPU time 8.29 seconds
Started Jun 10 05:47:15 PM PDT 24
Finished Jun 10 05:47:24 PM PDT 24
Peak memory 218684 kb
Host smart-4249f5ca-8ebc-49a5-a5cd-c3f2a46fe13e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999680144 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_di
gest.3999680144
Directory /workspace/7.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/7.lc_ctrl_security_escalation.22393030
Short name T862
Test name
Test status
Simulation time 172202235 ps
CPU time 6.4 seconds
Started Jun 10 05:47:12 PM PDT 24
Finished Jun 10 05:47:19 PM PDT 24
Peak memory 225156 kb
Host smart-b4a5329d-a62b-4204-af9a-4e999303c066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22393030 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_security_escalation.22393030
Directory /workspace/7.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/7.lc_ctrl_smoke.1999825262
Short name T572
Test name
Test status
Simulation time 24111170 ps
CPU time 1.79 seconds
Started Jun 10 05:47:13 PM PDT 24
Finished Jun 10 05:47:15 PM PDT 24
Peak memory 214368 kb
Host smart-8df489ab-d705-4480-8ab6-f176e1a04cfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999825262 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_smoke.1999825262
Directory /workspace/7.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_failure.1864563672
Short name T466
Test name
Test status
Simulation time 582544455 ps
CPU time 27.03 seconds
Started Jun 10 05:47:12 PM PDT 24
Finished Jun 10 05:47:40 PM PDT 24
Peak memory 251436 kb
Host smart-68bede9f-da6a-4b23-a48d-4725e2374314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864563672 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_failure.1864563672
Directory /workspace/7.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_post_trans.3924096452
Short name T321
Test name
Test status
Simulation time 93475002 ps
CPU time 7.02 seconds
Started Jun 10 05:47:14 PM PDT 24
Finished Jun 10 05:47:21 PM PDT 24
Peak memory 250964 kb
Host smart-e65150ec-f868-4fdd-ba07-9c3ea837227f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924096452 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_post_trans.3924096452
Directory /workspace/7.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_stress_all.1856285428
Short name T649
Test name
Test status
Simulation time 29826752331 ps
CPU time 162.79 seconds
Started Jun 10 05:47:12 PM PDT 24
Finished Jun 10 05:49:56 PM PDT 24
Peak memory 251580 kb
Host smart-97e897cf-e347-49f0-9d14-fb00ca0bf879
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856285428 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.lc_ctrl_stress_all.1856285428
Directory /workspace/7.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.lc_ctrl_volatile_unlock_smoke.2595244219
Short name T704
Test name
Test status
Simulation time 22576413 ps
CPU time 0.91 seconds
Started Jun 10 05:47:19 PM PDT 24
Finished Jun 10 05:47:20 PM PDT 24
Peak memory 209556 kb
Host smart-d54d846a-fc11-4488-96af-961b1142c875
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595244219 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ct
rl_volatile_unlock_smoke.2595244219
Directory /workspace/7.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_alert_test.4158149422
Short name T701
Test name
Test status
Simulation time 26732065 ps
CPU time 1.15 seconds
Started Jun 10 05:47:23 PM PDT 24
Finished Jun 10 05:47:24 PM PDT 24
Peak memory 209484 kb
Host smart-f91643d6-1af7-4fb7-bddb-eb74b638ef60
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158149422 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_alert_test.4158149422
Directory /workspace/8.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.lc_ctrl_claim_transition_if.2435492007
Short name T209
Test name
Test status
Simulation time 14006348 ps
CPU time 0.98 seconds
Started Jun 10 05:47:14 PM PDT 24
Finished Jun 10 05:47:16 PM PDT 24
Peak memory 209520 kb
Host smart-629df49d-c4fc-48e4-9506-a2ded807ec28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435492007 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_claim_transition_if.2435492007
Directory /workspace/8.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/8.lc_ctrl_errors.3572908637
Short name T651
Test name
Test status
Simulation time 1625683884 ps
CPU time 13.32 seconds
Started Jun 10 05:47:19 PM PDT 24
Finished Jun 10 05:47:33 PM PDT 24
Peak memory 218636 kb
Host smart-1203ab25-04b8-43a2-9c9f-fe00d8d5ee09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572908637 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_errors.3572908637
Directory /workspace/8.lc_ctrl_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_access.536973254
Short name T21
Test name
Test status
Simulation time 171701432 ps
CPU time 5.2 seconds
Started Jun 10 05:47:14 PM PDT 24
Finished Jun 10 05:47:20 PM PDT 24
Peak memory 217556 kb
Host smart-a35b2795-bd35-43bd-bad5-1e5416cf1944
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536973254 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_access.536973254
Directory /workspace/8.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_errors.3472273418
Short name T286
Test name
Test status
Simulation time 1899537158 ps
CPU time 56.29 seconds
Started Jun 10 05:47:17 PM PDT 24
Finished Jun 10 05:48:14 PM PDT 24
Peak memory 219364 kb
Host smart-b2525e70-8e45-43ea-a9a2-f39c68d6d7db
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472273418 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_er
rors.3472273418
Directory /workspace/8.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_priority.1208763737
Short name T8
Test name
Test status
Simulation time 1468314488 ps
CPU time 5.36 seconds
Started Jun 10 05:47:13 PM PDT 24
Finished Jun 10 05:47:19 PM PDT 24
Peak memory 218272 kb
Host smart-2beb3200-fe39-482a-81cd-a55f290fbc82
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208763737 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_priority.1
208763737
Directory /workspace/8.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_prog_failure.207386902
Short name T322
Test name
Test status
Simulation time 1980398915 ps
CPU time 6.42 seconds
Started Jun 10 05:47:12 PM PDT 24
Finished Jun 10 05:47:19 PM PDT 24
Peak memory 218716 kb
Host smart-e1892113-6772-4c8d-a66c-9c81aa2c50b0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207386902 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_
prog_failure.207386902
Directory /workspace/8.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_regwen_during_op.1387898641
Short name T721
Test name
Test status
Simulation time 1247498824 ps
CPU time 34.79 seconds
Started Jun 10 05:47:18 PM PDT 24
Finished Jun 10 05:47:53 PM PDT 24
Peak memory 218220 kb
Host smart-4acaa443-b206-48d6-9887-8775a7b4faf9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387898641 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_regwen_during_op.1387898641
Directory /workspace/8.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_smoke.2509024740
Short name T316
Test name
Test status
Simulation time 129192542 ps
CPU time 4.4 seconds
Started Jun 10 05:47:18 PM PDT 24
Finished Jun 10 05:47:22 PM PDT 24
Peak memory 218236 kb
Host smart-b144e9be-cb56-41e1-9290-ea18faf94860
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509024740 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_smoke.
2509024740
Directory /workspace/8.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_failure.2345181777
Short name T511
Test name
Test status
Simulation time 2301462624 ps
CPU time 51.02 seconds
Started Jun 10 05:47:17 PM PDT 24
Finished Jun 10 05:48:08 PM PDT 24
Peak memory 278348 kb
Host smart-23dc46ca-3ffb-4467-b1e1-d838d9bcca94
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345181777 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jta
g_state_failure.2345181777
Directory /workspace/8.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_post_trans.1859243596
Short name T228
Test name
Test status
Simulation time 1250108307 ps
CPU time 36.01 seconds
Started Jun 10 05:47:18 PM PDT 24
Finished Jun 10 05:47:54 PM PDT 24
Peak memory 251420 kb
Host smart-f734d1de-21fb-4976-8e65-1aeb1208ff80
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859243596 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_state_post_trans.1859243596
Directory /workspace/8.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_prog_failure.1675001975
Short name T486
Test name
Test status
Simulation time 824391179 ps
CPU time 4.11 seconds
Started Jun 10 05:47:14 PM PDT 24
Finished Jun 10 05:47:18 PM PDT 24
Peak memory 218696 kb
Host smart-3fbb1956-3074-492d-b1e7-bc4de256101d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675001975 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_prog_failure.1675001975
Directory /workspace/8.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_regwen_during_op.3800445019
Short name T489
Test name
Test status
Simulation time 410491982 ps
CPU time 15.07 seconds
Started Jun 10 05:47:13 PM PDT 24
Finished Jun 10 05:47:29 PM PDT 24
Peak memory 218340 kb
Host smart-a9add272-3310-486a-8e75-2e44046e7dca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800445019 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_regwen_during_op.3800445019
Directory /workspace/8.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_mubi.4276166272
Short name T748
Test name
Test status
Simulation time 1359580616 ps
CPU time 17.6 seconds
Started Jun 10 05:47:16 PM PDT 24
Finished Jun 10 05:47:34 PM PDT 24
Peak memory 219404 kb
Host smart-32ae06c8-a8d5-4b4b-b4ca-7cf8f5f16550
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276166272 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_mubi.4276166272
Directory /workspace/8.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_digest.1471017320
Short name T15
Test name
Test status
Simulation time 1145819647 ps
CPU time 11.62 seconds
Started Jun 10 05:47:21 PM PDT 24
Finished Jun 10 05:47:33 PM PDT 24
Peak memory 218760 kb
Host smart-605753ec-e070-4f13-9225-555c7964ff9c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471017320 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_di
gest.1471017320
Directory /workspace/8.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_mux.3103225329
Short name T405
Test name
Test status
Simulation time 430060244 ps
CPU time 9.32 seconds
Started Jun 10 05:47:17 PM PDT 24
Finished Jun 10 05:47:27 PM PDT 24
Peak memory 218712 kb
Host smart-01954bdb-1056-4c3e-b897-9cf967aaa3be
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103225329 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_mux.3
103225329
Directory /workspace/8.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/8.lc_ctrl_security_escalation.1931048573
Short name T420
Test name
Test status
Simulation time 1386649446 ps
CPU time 13.81 seconds
Started Jun 10 05:47:18 PM PDT 24
Finished Jun 10 05:47:32 PM PDT 24
Peak memory 226560 kb
Host smart-d2dae1ce-6669-4071-bf98-42f66694ccb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931048573 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_security_escalation.1931048573
Directory /workspace/8.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/8.lc_ctrl_smoke.827445901
Short name T573
Test name
Test status
Simulation time 86245607 ps
CPU time 3.06 seconds
Started Jun 10 05:47:13 PM PDT 24
Finished Jun 10 05:47:16 PM PDT 24
Peak memory 218228 kb
Host smart-09b79e85-30a7-4545-9154-bcdc03cc6fc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827445901 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_smoke.827445901
Directory /workspace/8.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_failure.2207402428
Short name T764
Test name
Test status
Simulation time 265069930 ps
CPU time 28.08 seconds
Started Jun 10 05:47:15 PM PDT 24
Finished Jun 10 05:47:43 PM PDT 24
Peak memory 251416 kb
Host smart-bdcc461b-a7f3-49ef-b1d3-dd383f4396b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207402428 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_failure.2207402428
Directory /workspace/8.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_post_trans.1703383602
Short name T574
Test name
Test status
Simulation time 61279525 ps
CPU time 3.41 seconds
Started Jun 10 05:47:19 PM PDT 24
Finished Jun 10 05:47:23 PM PDT 24
Peak memory 222644 kb
Host smart-ec66cb38-1ae4-4b64-86c6-3ad6b0e51fb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1703383602 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_post_trans.1703383602
Directory /workspace/8.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all.3813505063
Short name T451
Test name
Test status
Simulation time 11793748445 ps
CPU time 95.55 seconds
Started Jun 10 05:47:23 PM PDT 24
Finished Jun 10 05:48:59 PM PDT 24
Peak memory 251392 kb
Host smart-da81434c-c7a8-43c4-b89c-fbdbbea75053
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813505063 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.lc_ctrl_stress_all.3813505063
Directory /workspace/8.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.lc_ctrl_volatile_unlock_smoke.880602763
Short name T506
Test name
Test status
Simulation time 48609726 ps
CPU time 0.93 seconds
Started Jun 10 05:47:12 PM PDT 24
Finished Jun 10 05:47:13 PM PDT 24
Peak memory 212332 kb
Host smart-3cedeb48-c77e-4e5d-88f6-c0fb6fa0245d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880602763 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctr
l_volatile_unlock_smoke.880602763
Directory /workspace/8.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_alert_test.1778378577
Short name T824
Test name
Test status
Simulation time 73330978 ps
CPU time 0.98 seconds
Started Jun 10 05:47:27 PM PDT 24
Finished Jun 10 05:47:28 PM PDT 24
Peak memory 209456 kb
Host smart-1e07ea52-42bb-4226-8f6e-3c563516fed8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778378577 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_alert_test.1778378577
Directory /workspace/9.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.lc_ctrl_claim_transition_if.292356082
Short name T383
Test name
Test status
Simulation time 33975789 ps
CPU time 0.91 seconds
Started Jun 10 05:47:22 PM PDT 24
Finished Jun 10 05:47:23 PM PDT 24
Peak memory 209428 kb
Host smart-f20b62d9-1a28-431a-a884-64b6a9a8f638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292356082 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_claim_transition_if.292356082
Directory /workspace/9.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/9.lc_ctrl_errors.248350883
Short name T729
Test name
Test status
Simulation time 1057095491 ps
CPU time 9.75 seconds
Started Jun 10 05:47:21 PM PDT 24
Finished Jun 10 05:47:31 PM PDT 24
Peak memory 218628 kb
Host smart-a8747ab3-d203-47af-94c9-e3a273f56739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248350883 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_errors.248350883
Directory /workspace/9.lc_ctrl_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_access.141482763
Short name T609
Test name
Test status
Simulation time 6328432546 ps
CPU time 13.78 seconds
Started Jun 10 05:47:25 PM PDT 24
Finished Jun 10 05:47:39 PM PDT 24
Peak memory 218208 kb
Host smart-fd43c2f0-7fbf-4538-8e30-125c754a0d0f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141482763 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_access.141482763
Directory /workspace/9.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_errors.3321097227
Short name T696
Test name
Test status
Simulation time 7958835928 ps
CPU time 57.88 seconds
Started Jun 10 05:47:24 PM PDT 24
Finished Jun 10 05:48:22 PM PDT 24
Peak memory 218868 kb
Host smart-26995871-966c-4faa-9b30-271b93cafe86
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321097227 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_er
rors.3321097227
Directory /workspace/9.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_priority.2033711483
Short name T438
Test name
Test status
Simulation time 804554624 ps
CPU time 3.28 seconds
Started Jun 10 05:47:27 PM PDT 24
Finished Jun 10 05:47:31 PM PDT 24
Peak memory 218244 kb
Host smart-0834dca8-fe38-4bbd-a413-b6b67be3ac70
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033711483 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_priority.2
033711483
Directory /workspace/9.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_prog_failure.1815793785
Short name T237
Test name
Test status
Simulation time 3501363521 ps
CPU time 12.91 seconds
Started Jun 10 05:47:23 PM PDT 24
Finished Jun 10 05:47:37 PM PDT 24
Peak memory 218764 kb
Host smart-41f1c2dd-f14d-47a3-af69-c2b106670950
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815793785 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag
_prog_failure.1815793785
Directory /workspace/9.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_regwen_during_op.3111130209
Short name T589
Test name
Test status
Simulation time 1676630877 ps
CPU time 18.94 seconds
Started Jun 10 05:47:29 PM PDT 24
Finished Jun 10 05:47:48 PM PDT 24
Peak memory 218192 kb
Host smart-a01335cb-d15c-46d3-b624-f9d19570a907
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111130209 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_regwen_during_op.3111130209
Directory /workspace/9.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_smoke.2223409643
Short name T800
Test name
Test status
Simulation time 1313380985 ps
CPU time 10.5 seconds
Started Jun 10 05:47:26 PM PDT 24
Finished Jun 10 05:47:37 PM PDT 24
Peak memory 218232 kb
Host smart-8c87b802-d56c-48c2-8666-e4075bcb648f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223409643 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_smoke.
2223409643
Directory /workspace/9.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_failure.1092622775
Short name T387
Test name
Test status
Simulation time 28153456348 ps
CPU time 78.59 seconds
Started Jun 10 05:47:34 PM PDT 24
Finished Jun 10 05:48:53 PM PDT 24
Peak memory 276244 kb
Host smart-1f5c467c-136a-4fdd-bedb-c6885f78b93c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092622775 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jta
g_state_failure.1092622775
Directory /workspace/9.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_post_trans.2710908149
Short name T808
Test name
Test status
Simulation time 3228666323 ps
CPU time 12.5 seconds
Started Jun 10 05:47:34 PM PDT 24
Finished Jun 10 05:47:47 PM PDT 24
Peak memory 251488 kb
Host smart-f30b3352-8a8c-4df8-bd4f-a20a6c403355
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710908149 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_state_post_trans.2710908149
Directory /workspace/9.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_prog_failure.2533801883
Short name T677
Test name
Test status
Simulation time 192071760 ps
CPU time 2.49 seconds
Started Jun 10 05:47:20 PM PDT 24
Finished Jun 10 05:47:23 PM PDT 24
Peak memory 218684 kb
Host smart-15367fa5-c4a8-4bc3-a5fa-e06011d59256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2533801883 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_prog_failure.2533801883
Directory /workspace/9.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_regwen_during_op.3874821714
Short name T710
Test name
Test status
Simulation time 1408679539 ps
CPU time 8.56 seconds
Started Jun 10 05:47:26 PM PDT 24
Finished Jun 10 05:47:35 PM PDT 24
Peak memory 215276 kb
Host smart-f1b6cdd3-df0f-4fcf-8cd5-562d645d4d31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874821714 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_regwen_during_op.3874821714
Directory /workspace/9.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_mubi.3903495546
Short name T754
Test name
Test status
Simulation time 1158745698 ps
CPU time 12.83 seconds
Started Jun 10 05:47:25 PM PDT 24
Finished Jun 10 05:47:38 PM PDT 24
Peak memory 220576 kb
Host smart-2ea7c78e-ce11-4142-8d16-30144f77dc72
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903495546 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_mubi.3903495546
Directory /workspace/9.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_digest.3917688179
Short name T270
Test name
Test status
Simulation time 1165629647 ps
CPU time 10.37 seconds
Started Jun 10 05:47:25 PM PDT 24
Finished Jun 10 05:47:36 PM PDT 24
Peak memory 218756 kb
Host smart-2fb2eea0-8fcb-4e8f-99e3-dd39258be53f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917688179 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_di
gest.3917688179
Directory /workspace/9.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_mux.2792312571
Short name T547
Test name
Test status
Simulation time 1643643695 ps
CPU time 9.38 seconds
Started Jun 10 05:47:32 PM PDT 24
Finished Jun 10 05:47:41 PM PDT 24
Peak memory 218844 kb
Host smart-73887772-0b79-4619-88f7-da947fe9e3b6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792312571 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_mux.2
792312571
Directory /workspace/9.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/9.lc_ctrl_security_escalation.953195970
Short name T714
Test name
Test status
Simulation time 1440877070 ps
CPU time 8.23 seconds
Started Jun 10 05:47:25 PM PDT 24
Finished Jun 10 05:47:34 PM PDT 24
Peak memory 218748 kb
Host smart-5dfb4321-f38d-48ba-93e8-8de5a653a982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=953195970 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_security_escalation.953195970
Directory /workspace/9.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/9.lc_ctrl_smoke.4094604273
Short name T272
Test name
Test status
Simulation time 62722341 ps
CPU time 1.51 seconds
Started Jun 10 05:47:22 PM PDT 24
Finished Jun 10 05:47:23 PM PDT 24
Peak memory 214340 kb
Host smart-ee1c8185-ab77-4866-9c96-e59a7015270c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094604273 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_smoke.4094604273
Directory /workspace/9.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_failure.602567753
Short name T806
Test name
Test status
Simulation time 584877891 ps
CPU time 32 seconds
Started Jun 10 05:47:19 PM PDT 24
Finished Jun 10 05:47:52 PM PDT 24
Peak memory 251404 kb
Host smart-617a73ac-1f5b-45ce-b90e-f321ffdad7f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602567753 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_failure.602567753
Directory /workspace/9.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_post_trans.2225052234
Short name T508
Test name
Test status
Simulation time 107331395 ps
CPU time 7.74 seconds
Started Jun 10 05:47:22 PM PDT 24
Finished Jun 10 05:47:30 PM PDT 24
Peak memory 251444 kb
Host smart-5950c250-4666-4099-95ae-6594bfa7e083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225052234 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_post_trans.2225052234
Directory /workspace/9.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_stress_all.2678785258
Short name T758
Test name
Test status
Simulation time 5396823239 ps
CPU time 177.82 seconds
Started Jun 10 05:47:33 PM PDT 24
Finished Jun 10 05:50:31 PM PDT 24
Peak memory 267892 kb
Host smart-c2276ab9-c6d0-4ddb-95ac-02bd0c082d2a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678785258 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.lc_ctrl_stress_all.2678785258
Directory /workspace/9.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.lc_ctrl_volatile_unlock_smoke.1112049008
Short name T35
Test name
Test status
Simulation time 26797545 ps
CPU time 1.12 seconds
Started Jun 10 05:47:17 PM PDT 24
Finished Jun 10 05:47:18 PM PDT 24
Peak memory 212396 kb
Host smart-03855786-52c9-4df3-9dde-fa4b18a359dc
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112049008 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ct
rl_volatile_unlock_smoke.1112049008
Directory /workspace/9.lc_ctrl_volatile_unlock_smoke/latest
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