Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

99505196

1

T1

1866

T2

26241

T3

44909

auto[1]

1381254

1

T4

297

T15

11940

T5

6687

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

99467288

1

T1

1866

T2

26241

T3

44909

auto[1]

1419162

1

T4

495

T14

99

T15

10784

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	7440008	1			T1	792		T2	110		T3	8446
auto[IdleSt]	21400046	1			T1	214		T2	26131		T3	2783
auto[ClkMuxSt]	35096	1			T1	14		T3	86		T4	94
auto[CntIncrSt]	34826	1			T1	7		T3	86		T4	94
auto[CntProgSt]	1226393	1			T1	14		T3	19559		T4	1312
auto[TransCheckSt]	26989	1			T1	7		T3	86		T4	77
auto[TokenHashSt]	38363293	1			T1	143		T3	474		T4	744
auto[FlashRmaSt]	26831	1			T1	7		T3	62		T4	52
auto[TokenCheck0St]	12376	1			T1	7		T3	34		T4	27
auto[TokenCheck1St]	9023	1			T1	7		T3	8		T4	16
auto[TransProgSt]	299791	1			T1	14		T4	273		T12	30
auto[PostTransSt]	13010237	1			T1	640		T3	13285		T4	127291
auto[ScrapSt]	296785	1			T15	3		T5	15		T16	35
auto[EscalateSt]	6818980	1			T4	5063		T14	198		T15	15639
auto[InvalidSt]	11883797	1			T14	96		T5	200189		T9	183118

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1979	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	11883797	1			T14	96		T5	200189		T9	183118
EscalateSt	6818980	1			T4	5063		T14	198		T15	15639
ScrapSt	296785	1			T15	3		T5	15		T16	35
PostTransSt	13010237	1			T1	640		T3	13285		T4	127291
TransProgSt	299791	1			T1	14		T4	273		T12	30
TokenCheck1St	9023	1			T1	7		T3	8		T4	16
TokenCheck0St	12376	1			T1	7		T3	34		T4	27
FlashRmaSt	26831	1			T1	7		T3	62		T4	52
TokenHashSt	38363293	1			T1	143		T3	474		T4	744
TransCheckSt	26989	1			T1	7		T3	86		T4	77
CntProgSt	1226393	1			T1	14		T3	19559		T4	1312
CntIncrSt	34826	1			T1	7		T3	86		T4	94
ClkMuxSt	35096	1			T1	14		T3	86		T4	94
IdleSt	21400046	1			T1	214		T2	26131		T3	2783
ResetSt	7440008	1			T1	792		T2	110		T3	8446
arcs[ResetSt=>IdleSt]	53625	1			T1	7		T2	1		T3	87
arcs[IdleSt=>ScrapSt]	277	1			T15	1		T5	1		T16	1
arcs[IdleSt=>ClkMuxSt]	34873	1			T1	7		T3	86		T4	94
arcs[ClkMuxSt=>CntIncrSt]	34826	1			T1	7		T3	86		T4	94
arcs[CntIncrSt=>PostTransSt]	1872	1			T4	9		T5	7		T34	9
arcs[CntIncrSt=>CntProgSt]	32900	1			T1	7		T3	86		T4	85
arcs[CntProgSt=>PostTransSt]	4781	1			T4	8		T5	8		T41	15
arcs[CntProgSt=>TransCheckSt]	26989	1			T1	7		T3	86		T4	77
arcs[TransCheckSt=>PostTransSt]	3654	1			T3	43		T4	9		T5	8
arcs[TransCheckSt=>TokenHashSt]	23238	1			T1	7		T3	43		T4	68
arcs[TokenHashSt=>PostTransSt]	10056	1			T3	9		T4	41		T13	65
arcs[TokenHashSt=>FlashRmaSt]	12449	1			T1	7		T3	34		T4	27
arcs[FlashRmaSt=>TokenCheck0St]	12376	1			T1	7		T3	34		T4	27
arcs[TokenCheck0St=>PostTransSt]	3336	1			T3	26		T4	11		T5	10
arcs[TokenCheck0St=>TokenCheck1St]	9023	1			T1	7		T3	8		T4	16
arcs[TokenCheck1St=>PostTransSt]	633	1			T3	8		T5	1		T41	2
arcs[TransProgSt=>PostTransSt]	7478	1			T1	7		T4	16		T12	15
arcs[IdleSt=>EscalateSt]	160	1			T35	9		T51	7		T52	3
arcs[ClkMuxSt=>EscalateSt]	47	1			T15	2		T49	1		T50	2
arcs[CntIncrSt=>EscalateSt]	54	1			T15	3		T49	1		T50	3
arcs[CntProgSt=>EscalateSt]	1130	1			T15	36		T35	17		T49	40
arcs[TransCheckSt=>EscalateSt]	97	1			T15	1		T49	1		T52	5
arcs[TokenHashSt=>EscalateSt]	732	1			T15	12		T35	6		T49	9
arcs[FlashRmaSt=>EscalateSt]	73	1			T15	7		T35	2		T49	3
arcs[TokenCheck0St=>EscalateSt]	17	1			T50	1		T56	1		T57	1
arcs[TokenCheck1St=>EscalateSt]	153	1			T15	6		T35	2		T49	3
arcs[TransProgSt=>EscalateSt]	759	1			T15	17		T35	13		T49	11
arcs[PostTransSt=>EscalateSt]	5002	1			T4	8		T15	2		T5	8
arcs[InvalidSt=>EscalateSt]	14191	1			T14	1		T5	145		T9	64

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7439836	1			T1	792		T2	110		T3	8446
auto[0]	auto[IdleSt]	21399937	1			T1	214		T2	26131		T3	2783
auto[0]	auto[ClkMuxSt]	35058	1			T1	14		T3	86		T4	94
auto[0]	auto[CntIncrSt]	34794	1			T1	7		T3	86		T4	94
auto[0]	auto[CntProgSt]	1225649	1			T1	14		T3	19559		T4	1312
auto[0]	auto[TransCheckSt]	26922	1			T1	7		T3	86		T4	77
auto[0]	auto[TokenHashSt]	38362813	1			T1	143		T3	474		T4	744
auto[0]	auto[FlashRmaSt]	26781	1			T1	7		T3	62		T4	52
auto[0]	auto[TokenCheck0St]	12366	1			T1	7		T3	34		T4	27
auto[0]	auto[TokenCheck1St]	8930	1			T1	7		T3	8		T4	16
auto[0]	auto[TransProgSt]	299280	1			T1	14		T4	273		T12	30
auto[0]	auto[PostTransSt]	13007749	1			T1	640		T3	13285		T4	127288
auto[0]	auto[ScrapSt]	296742	1			T15	3		T5	15		T16	35
auto[0]	auto[EscalateSt]	5449550	1			T4	4769		T14	198		T15	3769
auto[0]	auto[InvalidSt]	11876810	1			T14	96		T5	200124		T9	183082
auto[1]	auto[ResetSt]	172	1			T15	7		T35	1		T49	3
auto[1]	auto[IdleSt]	109	1			T35	8		T51	5		T52	2
auto[1]	auto[ClkMuxSt]	38	1			T15	1		T49	1		T50	2
auto[1]	auto[CntIncrSt]	32	1			T15	2		T50	2		T51	1
auto[1]	auto[CntProgSt]	744	1			T15	30		T35	13		T49	27
auto[1]	auto[TransCheckSt]	67	1			T15	1		T49	1		T52	3
auto[1]	auto[TokenHashSt]	480	1			T15	8		T35	4		T49	8
auto[1]	auto[FlashRmaSt]	50	1			T15	6		T35	2		T49	1
auto[1]	auto[TokenCheck0St]	10	1			T209	1		T210	1		T211	1
auto[1]	auto[TokenCheck1St]	93	1			T15	3		T35	2		T49	1
auto[1]	auto[TransProgSt]	511	1			T15	11		T35	9		T49	9
auto[1]	auto[PostTransSt]	2488	1			T4	3		T15	1		T5	3
auto[1]	auto[ScrapSt]	43	1			T52	3		T56	1		T212	1
auto[1]	auto[EscalateSt]	1369430	1			T4	294		T15	11870		T5	6619
auto[1]	auto[InvalidSt]	6987	1			T5	65		T9	36		T40	28

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7439838	1			T1	792		T2	110		T3	8446
auto[0]	auto[IdleSt]	21399931	1			T1	214		T2	26131		T3	2783
auto[0]	auto[ClkMuxSt]	35071	1			T1	14		T3	86		T4	94
auto[0]	auto[CntIncrSt]	34790	1			T1	7		T3	86		T4	94
auto[0]	auto[CntProgSt]	1225624	1			T1	14		T3	19559		T4	1312
auto[0]	auto[TransCheckSt]	26924	1			T1	7		T3	86		T4	77
auto[0]	auto[TokenHashSt]	38362808	1			T1	143		T3	474		T4	744
auto[0]	auto[FlashRmaSt]	26779	1			T1	7		T3	62		T4	52
auto[0]	auto[TokenCheck0St]	12363	1			T1	7		T3	34		T4	27
auto[0]	auto[TokenCheck1St]	8914	1			T1	7		T3	8		T4	16
auto[0]	auto[TransProgSt]	299292	1			T1	14		T4	273		T12	30
auto[0]	auto[PostTransSt]	13007653	1			T1	640		T3	13285		T4	127286
auto[0]	auto[ScrapSt]	296742	1			T15	2		T5	15		T16	35
auto[0]	auto[EscalateSt]	5411987	1			T4	4573		T14	100		T15	4920
auto[0]	auto[InvalidSt]	11876593	1			T14	95		T5	200109		T9	183090
auto[1]	auto[ResetSt]	170	1			T15	5		T35	2		T49	4
auto[1]	auto[IdleSt]	115	1			T35	8		T51	6		T52	2
auto[1]	auto[ClkMuxSt]	25	1			T15	1		T50	1		T51	1
auto[1]	auto[CntIncrSt]	36	1			T15	3		T49	1		T50	1
auto[1]	auto[CntProgSt]	769	1			T15	22		T35	9		T49	19
auto[1]	auto[TransCheckSt]	65	1			T15	1		T49	1		T52	5
auto[1]	auto[TokenHashSt]	485	1			T15	8		T35	5		T49	6
auto[1]	auto[FlashRmaSt]	52	1			T15	6		T35	2		T49	3
auto[1]	auto[TokenCheck0St]	13	1			T50	1		T56	1		T57	1
auto[1]	auto[TokenCheck1St]	109	1			T15	5		T35	1		T49	2
auto[1]	auto[TransProgSt]	499	1			T15	12		T35	9		T49	8
auto[1]	auto[PostTransSt]	2584	1			T4	5		T15	1		T5	5
auto[1]	auto[ScrapSt]	43	1			T15	1		T51	1		T53	1
auto[1]	auto[EscalateSt]	1406993	1			T4	490		T14	98		T15	10719
auto[1]	auto[InvalidSt]	7204	1			T14	1		T5	80		T9	28