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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.87 97.99 95.68 93.38 97.67 98.55 98.51 96.29


Total test records in report: 995
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T810 /workspace/coverage/default/29.lc_ctrl_sec_token_digest.3161018115 Jun 11 02:14:01 PM PDT 24 Jun 11 02:14:14 PM PDT 24 363906515 ps
T811 /workspace/coverage/default/21.lc_ctrl_errors.3560170839 Jun 11 02:13:47 PM PDT 24 Jun 11 02:13:57 PM PDT 24 163383362 ps
T812 /workspace/coverage/default/6.lc_ctrl_errors.2053132625 Jun 11 02:12:52 PM PDT 24 Jun 11 02:13:06 PM PDT 24 2482842148 ps
T813 /workspace/coverage/default/37.lc_ctrl_volatile_unlock_smoke.2591790808 Jun 11 02:14:14 PM PDT 24 Jun 11 02:14:17 PM PDT 24 13227805 ps
T814 /workspace/coverage/default/4.lc_ctrl_jtag_priority.2767042115 Jun 11 02:12:43 PM PDT 24 Jun 11 02:12:47 PM PDT 24 170924172 ps
T815 /workspace/coverage/default/16.lc_ctrl_jtag_access.4237868166 Jun 11 02:13:28 PM PDT 24 Jun 11 02:13:38 PM PDT 24 617727395 ps
T816 /workspace/coverage/default/2.lc_ctrl_sec_token_mux.2247224701 Jun 11 02:12:46 PM PDT 24 Jun 11 02:12:58 PM PDT 24 277176458 ps
T817 /workspace/coverage/default/23.lc_ctrl_state_failure.2800212195 Jun 11 02:13:50 PM PDT 24 Jun 11 02:14:14 PM PDT 24 353011444 ps
T818 /workspace/coverage/default/16.lc_ctrl_prog_failure.1392965485 Jun 11 02:13:31 PM PDT 24 Jun 11 02:13:35 PM PDT 24 792507470 ps
T819 /workspace/coverage/default/4.lc_ctrl_sec_token_digest.1453249767 Jun 11 02:12:44 PM PDT 24 Jun 11 02:12:58 PM PDT 24 1223742583 ps
T820 /workspace/coverage/default/45.lc_ctrl_errors.817228836 Jun 11 02:14:31 PM PDT 24 Jun 11 02:14:47 PM PDT 24 314612758 ps
T821 /workspace/coverage/default/8.lc_ctrl_errors.2584802477 Jun 11 02:12:57 PM PDT 24 Jun 11 02:13:13 PM PDT 24 5095720192 ps
T822 /workspace/coverage/default/44.lc_ctrl_state_post_trans.1536765718 Jun 11 02:14:32 PM PDT 24 Jun 11 02:14:42 PM PDT 24 1592169381 ps
T823 /workspace/coverage/default/13.lc_ctrl_state_post_trans.578193343 Jun 11 02:13:11 PM PDT 24 Jun 11 02:13:15 PM PDT 24 975606150 ps
T824 /workspace/coverage/default/6.lc_ctrl_jtag_access.4277439027 Jun 11 02:12:53 PM PDT 24 Jun 11 02:13:03 PM PDT 24 527920605 ps
T825 /workspace/coverage/default/49.lc_ctrl_alert_test.341420505 Jun 11 02:14:55 PM PDT 24 Jun 11 02:14:58 PM PDT 24 31115043 ps
T826 /workspace/coverage/default/1.lc_ctrl_jtag_smoke.341547827 Jun 11 02:12:28 PM PDT 24 Jun 11 02:12:36 PM PDT 24 481278320 ps
T827 /workspace/coverage/default/17.lc_ctrl_prog_failure.1940283035 Jun 11 02:13:24 PM PDT 24 Jun 11 02:13:28 PM PDT 24 46751919 ps
T828 /workspace/coverage/default/7.lc_ctrl_state_failure.1703507535 Jun 11 02:12:52 PM PDT 24 Jun 11 02:13:13 PM PDT 24 194068913 ps
T829 /workspace/coverage/default/8.lc_ctrl_jtag_state_failure.2362388957 Jun 11 02:13:04 PM PDT 24 Jun 11 02:13:55 PM PDT 24 4591529049 ps
T830 /workspace/coverage/default/3.lc_ctrl_errors.2772252662 Jun 11 02:12:44 PM PDT 24 Jun 11 02:12:55 PM PDT 24 2962101207 ps
T831 /workspace/coverage/default/4.lc_ctrl_jtag_prog_failure.223197764 Jun 11 02:12:44 PM PDT 24 Jun 11 02:12:55 PM PDT 24 1030376523 ps
T832 /workspace/coverage/default/17.lc_ctrl_jtag_state_failure.2302889946 Jun 11 02:13:22 PM PDT 24 Jun 11 02:14:25 PM PDT 24 1624259971 ps
T833 /workspace/coverage/default/3.lc_ctrl_jtag_priority.2533150032 Jun 11 02:12:42 PM PDT 24 Jun 11 02:12:47 PM PDT 24 423188530 ps
T834 /workspace/coverage/default/40.lc_ctrl_alert_test.934337006 Jun 11 02:14:26 PM PDT 24 Jun 11 02:14:28 PM PDT 24 21884863 ps
T835 /workspace/coverage/default/19.lc_ctrl_stress_all.2930904613 Jun 11 02:13:36 PM PDT 24 Jun 11 02:22:39 PM PDT 24 16514215678 ps
T836 /workspace/coverage/default/47.lc_ctrl_stress_all.953744507 Jun 11 02:14:41 PM PDT 24 Jun 11 02:16:34 PM PDT 24 14041313561 ps
T837 /workspace/coverage/default/42.lc_ctrl_stress_all.751921599 Jun 11 02:14:31 PM PDT 24 Jun 11 02:15:46 PM PDT 24 8459811186 ps
T838 /workspace/coverage/default/31.lc_ctrl_jtag_access.3024799988 Jun 11 02:14:05 PM PDT 24 Jun 11 02:14:16 PM PDT 24 840457409 ps
T839 /workspace/coverage/default/42.lc_ctrl_jtag_access.902266999 Jun 11 02:14:32 PM PDT 24 Jun 11 02:14:50 PM PDT 24 2674689224 ps
T840 /workspace/coverage/default/40.lc_ctrl_errors.3374963661 Jun 11 02:14:24 PM PDT 24 Jun 11 02:14:38 PM PDT 24 2526871365 ps
T841 /workspace/coverage/default/41.lc_ctrl_stress_all.1362147723 Jun 11 02:14:25 PM PDT 24 Jun 11 02:16:05 PM PDT 24 9191997628 ps
T842 /workspace/coverage/default/7.lc_ctrl_state_post_trans.1497848502 Jun 11 02:12:53 PM PDT 24 Jun 11 02:13:03 PM PDT 24 131426726 ps
T843 /workspace/coverage/default/39.lc_ctrl_sec_token_digest.118372150 Jun 11 02:14:25 PM PDT 24 Jun 11 02:14:42 PM PDT 24 2968179898 ps
T844 /workspace/coverage/default/22.lc_ctrl_jtag_access.939807277 Jun 11 02:13:46 PM PDT 24 Jun 11 02:13:53 PM PDT 24 413497420 ps
T845 /workspace/coverage/default/44.lc_ctrl_stress_all.2195223893 Jun 11 02:14:32 PM PDT 24 Jun 11 02:16:56 PM PDT 24 7106059227 ps
T846 /workspace/coverage/default/19.lc_ctrl_smoke.792038456 Jun 11 02:13:34 PM PDT 24 Jun 11 02:13:38 PM PDT 24 26122262 ps
T847 /workspace/coverage/default/9.lc_ctrl_state_failure.1523733543 Jun 11 02:13:12 PM PDT 24 Jun 11 02:13:35 PM PDT 24 367048794 ps
T848 /workspace/coverage/default/23.lc_ctrl_state_post_trans.3239765815 Jun 11 02:13:48 PM PDT 24 Jun 11 02:13:57 PM PDT 24 85036506 ps
T849 /workspace/coverage/default/2.lc_ctrl_jtag_state_failure.4148693861 Jun 11 02:12:30 PM PDT 24 Jun 11 02:13:51 PM PDT 24 2220991195 ps
T850 /workspace/coverage/default/14.lc_ctrl_jtag_state_post_trans.1444456397 Jun 11 02:13:14 PM PDT 24 Jun 11 02:13:30 PM PDT 24 948782346 ps
T851 /workspace/coverage/default/34.lc_ctrl_security_escalation.1837551584 Jun 11 02:14:06 PM PDT 24 Jun 11 02:14:18 PM PDT 24 224027119 ps
T852 /workspace/coverage/default/6.lc_ctrl_volatile_unlock_smoke.1959101781 Jun 11 02:12:51 PM PDT 24 Jun 11 02:12:53 PM PDT 24 81654193 ps
T853 /workspace/coverage/default/9.lc_ctrl_sec_token_mux.2106983979 Jun 11 02:13:02 PM PDT 24 Jun 11 02:13:15 PM PDT 24 2063178855 ps
T854 /workspace/coverage/default/18.lc_ctrl_jtag_smoke.2268028681 Jun 11 02:13:32 PM PDT 24 Jun 11 02:13:39 PM PDT 24 646510387 ps
T855 /workspace/coverage/default/18.lc_ctrl_sec_token_mux.2818538140 Jun 11 02:13:35 PM PDT 24 Jun 11 02:13:48 PM PDT 24 276010786 ps
T856 /workspace/coverage/default/43.lc_ctrl_volatile_unlock_smoke.1620390359 Jun 11 02:14:38 PM PDT 24 Jun 11 02:14:40 PM PDT 24 15148885 ps
T100 /workspace/coverage/default/38.lc_ctrl_state_failure.796747711 Jun 11 02:14:14 PM PDT 24 Jun 11 02:14:41 PM PDT 24 1801433933 ps
T857 /workspace/coverage/default/27.lc_ctrl_jtag_access.3421535186 Jun 11 02:13:58 PM PDT 24 Jun 11 02:14:02 PM PDT 24 278823734 ps
T858 /workspace/coverage/default/20.lc_ctrl_stress_all.940835310 Jun 11 02:13:54 PM PDT 24 Jun 11 02:17:56 PM PDT 24 8888832075 ps
T859 /workspace/coverage/default/13.lc_ctrl_stress_all.3613560026 Jun 11 02:13:18 PM PDT 24 Jun 11 02:13:44 PM PDT 24 3179432218 ps
T860 /workspace/coverage/default/31.lc_ctrl_security_escalation.1251268822 Jun 11 02:14:09 PM PDT 24 Jun 11 02:14:20 PM PDT 24 361627479 ps
T861 /workspace/coverage/default/17.lc_ctrl_sec_token_mux.523883765 Jun 11 02:13:35 PM PDT 24 Jun 11 02:13:44 PM PDT 24 321600987 ps
T862 /workspace/coverage/default/9.lc_ctrl_jtag_smoke.3728958056 Jun 11 02:13:13 PM PDT 24 Jun 11 02:13:17 PM PDT 24 78474268 ps
T863 /workspace/coverage/default/1.lc_ctrl_stress_all_with_rand_reset.2814181931 Jun 11 02:12:31 PM PDT 24 Jun 11 02:22:19 PM PDT 24 24347638559 ps
T864 /workspace/coverage/default/5.lc_ctrl_sec_token_digest.3728231146 Jun 11 02:12:52 PM PDT 24 Jun 11 02:13:05 PM PDT 24 546528506 ps
T865 /workspace/coverage/default/49.lc_ctrl_sec_token_mux.3955243773 Jun 11 02:14:43 PM PDT 24 Jun 11 02:14:51 PM PDT 24 738934448 ps
T866 /workspace/coverage/default/3.lc_ctrl_jtag_regwen_during_op.2671271539 Jun 11 02:12:44 PM PDT 24 Jun 11 02:13:00 PM PDT 24 788071347 ps
T867 /workspace/coverage/default/22.lc_ctrl_security_escalation.1326376324 Jun 11 02:13:48 PM PDT 24 Jun 11 02:13:59 PM PDT 24 949656191 ps
T868 /workspace/coverage/default/13.lc_ctrl_jtag_smoke.2301242650 Jun 11 02:13:14 PM PDT 24 Jun 11 02:13:22 PM PDT 24 4128225322 ps
T107 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.4181127360 Jun 11 12:53:22 PM PDT 24 Jun 11 12:53:25 PM PDT 24 643139696 ps
T115 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.601723278 Jun 11 12:54:01 PM PDT 24 Jun 11 12:54:03 PM PDT 24 22366432 ps
T101 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.4265769985 Jun 11 12:53:34 PM PDT 24 Jun 11 12:53:37 PM PDT 24 54098117 ps
T116 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.1434838846 Jun 11 12:53:49 PM PDT 24 Jun 11 12:53:52 PM PDT 24 351461566 ps
T108 /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.140196694 Jun 11 12:54:13 PM PDT 24 Jun 11 12:54:16 PM PDT 24 29145005 ps
T102 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.3947817239 Jun 11 12:54:29 PM PDT 24 Jun 11 12:54:33 PM PDT 24 286858807 ps
T133 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.3001903706 Jun 11 12:54:01 PM PDT 24 Jun 11 12:54:04 PM PDT 24 21026904 ps
T136 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.1927481030 Jun 11 12:54:12 PM PDT 24 Jun 11 12:54:18 PM PDT 24 737389573 ps
T147 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.279130472 Jun 11 12:53:59 PM PDT 24 Jun 11 12:54:02 PM PDT 24 40213941 ps
T148 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.3441289211 Jun 11 12:53:32 PM PDT 24 Jun 11 12:53:35 PM PDT 24 93611568 ps
T103 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.677790089 Jun 11 12:54:13 PM PDT 24 Jun 11 12:54:17 PM PDT 24 60176239 ps
T104 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.787968765 Jun 11 12:54:22 PM PDT 24 Jun 11 12:54:26 PM PDT 24 329629046 ps
T105 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.611879822 Jun 11 12:54:18 PM PDT 24 Jun 11 12:54:21 PM PDT 24 256927080 ps
T869 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.2511400077 Jun 11 12:53:50 PM PDT 24 Jun 11 12:54:16 PM PDT 24 4581116812 ps
T106 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.2612028104 Jun 11 12:54:12 PM PDT 24 Jun 11 12:54:14 PM PDT 24 15555832 ps
T870 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.3818102235 Jun 11 12:54:21 PM PDT 24 Jun 11 12:54:23 PM PDT 24 24500705 ps
T125 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.21970068 Jun 11 12:53:35 PM PDT 24 Jun 11 12:53:39 PM PDT 24 272003991 ps
T109 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.4261432920 Jun 11 12:54:23 PM PDT 24 Jun 11 12:54:28 PM PDT 24 162437547 ps
T134 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.748518027 Jun 11 12:53:33 PM PDT 24 Jun 11 12:53:36 PM PDT 24 433111700 ps
T149 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.879195518 Jun 11 12:53:56 PM PDT 24 Jun 11 12:53:58 PM PDT 24 105336164 ps
T182 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.1291417911 Jun 11 12:53:37 PM PDT 24 Jun 11 12:53:39 PM PDT 24 13616068 ps
T110 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.127034692 Jun 11 12:53:58 PM PDT 24 Jun 11 12:54:04 PM PDT 24 298645299 ps
T871 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.2295319651 Jun 11 12:53:57 PM PDT 24 Jun 11 12:54:17 PM PDT 24 836749862 ps
T872 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.350223065 Jun 11 12:54:23 PM PDT 24 Jun 11 12:54:26 PM PDT 24 29703155 ps
T130 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.157284171 Jun 11 12:53:59 PM PDT 24 Jun 11 12:54:03 PM PDT 24 73951489 ps
T873 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.1974971395 Jun 11 12:54:12 PM PDT 24 Jun 11 12:54:17 PM PDT 24 224328166 ps
T183 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.2654668033 Jun 11 12:53:22 PM PDT 24 Jun 11 12:53:25 PM PDT 24 18530894 ps
T113 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.589652038 Jun 11 12:54:26 PM PDT 24 Jun 11 12:54:29 PM PDT 24 123507743 ps
T874 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.3617613497 Jun 11 12:54:27 PM PDT 24 Jun 11 12:54:30 PM PDT 24 79112936 ps
T875 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.4180730336 Jun 11 12:53:21 PM PDT 24 Jun 11 12:53:23 PM PDT 24 102567480 ps
T184 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.3705732026 Jun 11 12:53:49 PM PDT 24 Jun 11 12:53:51 PM PDT 24 25154963 ps
T120 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.2389405824 Jun 11 12:54:21 PM PDT 24 Jun 11 12:54:25 PM PDT 24 259153309 ps
T876 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.205814045 Jun 11 12:53:35 PM PDT 24 Jun 11 12:54:04 PM PDT 24 1302316466 ps
T877 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.2949738013 Jun 11 12:53:33 PM PDT 24 Jun 11 12:53:35 PM PDT 24 54031132 ps
T185 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.2861137426 Jun 11 12:53:50 PM PDT 24 Jun 11 12:53:52 PM PDT 24 51380365 ps
T121 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.2049504727 Jun 11 12:54:22 PM PDT 24 Jun 11 12:54:25 PM PDT 24 84002687 ps
T878 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.2717548118 Jun 11 12:53:33 PM PDT 24 Jun 11 12:53:35 PM PDT 24 89887045 ps
T879 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.2958218320 Jun 11 12:53:32 PM PDT 24 Jun 11 12:53:36 PM PDT 24 112751376 ps
T880 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.1383969801 Jun 11 12:53:48 PM PDT 24 Jun 11 12:53:50 PM PDT 24 18269044 ps
T881 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.2618802726 Jun 11 12:53:34 PM PDT 24 Jun 11 12:53:42 PM PDT 24 3906202883 ps
T117 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.1464433487 Jun 11 12:54:11 PM PDT 24 Jun 11 12:54:14 PM PDT 24 224168860 ps
T882 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.2620283788 Jun 11 12:53:59 PM PDT 24 Jun 11 12:54:02 PM PDT 24 62047471 ps
T883 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.738555759 Jun 11 12:54:12 PM PDT 24 Jun 11 12:54:17 PM PDT 24 601098836 ps
T884 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.659892833 Jun 11 12:54:13 PM PDT 24 Jun 11 12:54:17 PM PDT 24 311681694 ps
T885 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.2049535724 Jun 11 12:53:49 PM PDT 24 Jun 11 12:53:52 PM PDT 24 226860424 ps
T194 /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.2599891340 Jun 11 12:53:47 PM PDT 24 Jun 11 12:53:49 PM PDT 24 199485088 ps
T886 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.872289255 Jun 11 12:53:23 PM PDT 24 Jun 11 12:53:38 PM PDT 24 588960324 ps
T195 /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.1472416664 Jun 11 12:54:22 PM PDT 24 Jun 11 12:54:24 PM PDT 24 20070202 ps
T887 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.2313919110 Jun 11 12:54:23 PM PDT 24 Jun 11 12:54:25 PM PDT 24 210261220 ps
T196 /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.3421275314 Jun 11 12:53:47 PM PDT 24 Jun 11 12:53:48 PM PDT 24 26865844 ps
T888 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.1700904228 Jun 11 12:53:56 PM PDT 24 Jun 11 12:54:01 PM PDT 24 1384780741 ps
T889 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.4188592488 Jun 11 12:54:12 PM PDT 24 Jun 11 12:54:15 PM PDT 24 194504402 ps
T890 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.414342384 Jun 11 12:53:23 PM PDT 24 Jun 11 12:53:26 PM PDT 24 46604334 ps
T114 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.4055241315 Jun 11 12:54:22 PM PDT 24 Jun 11 12:54:27 PM PDT 24 89799153 ps
T186 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.3938098229 Jun 11 12:54:22 PM PDT 24 Jun 11 12:54:25 PM PDT 24 16111521 ps
T197 /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.2869684634 Jun 11 12:54:13 PM PDT 24 Jun 11 12:54:16 PM PDT 24 108876483 ps
T891 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.4263933663 Jun 11 12:54:18 PM PDT 24 Jun 11 12:54:20 PM PDT 24 22414422 ps
T892 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.2386541268 Jun 11 12:54:13 PM PDT 24 Jun 11 12:54:20 PM PDT 24 491785895 ps
T198 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.1061410415 Jun 11 12:53:35 PM PDT 24 Jun 11 12:53:38 PM PDT 24 22518501 ps
T893 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.3336300362 Jun 11 12:53:47 PM PDT 24 Jun 11 12:53:49 PM PDT 24 81868143 ps
T199 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.1391169632 Jun 11 12:54:17 PM PDT 24 Jun 11 12:54:20 PM PDT 24 40955705 ps
T894 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.807022701 Jun 11 12:54:24 PM PDT 24 Jun 11 12:54:27 PM PDT 24 29267504 ps
T200 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.4129636674 Jun 11 12:54:11 PM PDT 24 Jun 11 12:54:13 PM PDT 24 21903786 ps
T895 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.1250386733 Jun 11 12:53:56 PM PDT 24 Jun 11 12:53:58 PM PDT 24 79874656 ps
T896 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.1993653863 Jun 11 12:54:11 PM PDT 24 Jun 11 12:54:14 PM PDT 24 21506414 ps
T897 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.2043257051 Jun 11 12:54:12 PM PDT 24 Jun 11 12:54:17 PM PDT 24 479569346 ps
T187 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.3146251936 Jun 11 12:54:34 PM PDT 24 Jun 11 12:54:36 PM PDT 24 24670112 ps
T898 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.3922404978 Jun 11 12:54:02 PM PDT 24 Jun 11 12:54:06 PM PDT 24 117677940 ps
T899 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.37529048 Jun 11 12:53:24 PM PDT 24 Jun 11 12:53:38 PM PDT 24 2420121855 ps
T900 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.2012439284 Jun 11 12:53:47 PM PDT 24 Jun 11 12:53:49 PM PDT 24 21085013 ps
T135 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3474597933 Jun 11 12:54:00 PM PDT 24 Jun 11 12:54:03 PM PDT 24 383552789 ps
T901 /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.3552360577 Jun 11 12:54:37 PM PDT 24 Jun 11 12:54:39 PM PDT 24 86134132 ps
T188 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.2124590563 Jun 11 12:54:29 PM PDT 24 Jun 11 12:54:30 PM PDT 24 55611749 ps
T902 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.3681994415 Jun 11 12:53:59 PM PDT 24 Jun 11 12:54:03 PM PDT 24 492255381 ps
T903 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.2798911920 Jun 11 12:54:01 PM PDT 24 Jun 11 12:54:04 PM PDT 24 203695818 ps
T118 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.137878393 Jun 11 12:53:23 PM PDT 24 Jun 11 12:53:28 PM PDT 24 962508835 ps
T904 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.3744914540 Jun 11 12:53:35 PM PDT 24 Jun 11 12:53:42 PM PDT 24 1863737288 ps
T905 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.165711173 Jun 11 12:54:13 PM PDT 24 Jun 11 12:54:16 PM PDT 24 579870442 ps
T906 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.1371089376 Jun 11 12:53:59 PM PDT 24 Jun 11 12:54:02 PM PDT 24 56664499 ps
T907 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.4265203584 Jun 11 12:54:12 PM PDT 24 Jun 11 12:54:15 PM PDT 24 18242892 ps
T908 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.2732890103 Jun 11 12:53:35 PM PDT 24 Jun 11 12:53:38 PM PDT 24 134483940 ps
T909 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.4174016761 Jun 11 12:53:22 PM PDT 24 Jun 11 12:53:27 PM PDT 24 97514103 ps
T910 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.3509291322 Jun 11 12:53:49 PM PDT 24 Jun 11 12:53:52 PM PDT 24 93150889 ps
T911 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.2428384559 Jun 11 12:54:21 PM PDT 24 Jun 11 12:54:25 PM PDT 24 71052401 ps
T189 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.1243475571 Jun 11 12:54:24 PM PDT 24 Jun 11 12:54:27 PM PDT 24 17767169 ps
T912 /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.62091081 Jun 11 12:54:15 PM PDT 24 Jun 11 12:54:18 PM PDT 24 73634634 ps
T913 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.1816473961 Jun 11 12:54:10 PM PDT 24 Jun 11 12:54:12 PM PDT 24 224637164 ps
T914 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.3139728503 Jun 11 12:54:15 PM PDT 24 Jun 11 12:54:37 PM PDT 24 1652009671 ps
T915 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.1997750078 Jun 11 12:54:12 PM PDT 24 Jun 11 12:54:14 PM PDT 24 61232801 ps
T916 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.1346784167 Jun 11 12:53:59 PM PDT 24 Jun 11 12:54:01 PM PDT 24 69358593 ps
T917 /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.4072155630 Jun 11 12:54:23 PM PDT 24 Jun 11 12:54:25 PM PDT 24 28738287 ps
T918 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.2491337922 Jun 11 12:54:21 PM PDT 24 Jun 11 12:54:26 PM PDT 24 138357309 ps
T919 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.585121046 Jun 11 12:53:48 PM PDT 24 Jun 11 12:53:50 PM PDT 24 54728383 ps
T920 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.1226749671 Jun 11 12:54:03 PM PDT 24 Jun 11 12:54:13 PM PDT 24 368498017 ps
T119 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.2764810136 Jun 11 12:53:36 PM PDT 24 Jun 11 12:53:40 PM PDT 24 78359601 ps
T921 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.539416327 Jun 11 12:54:00 PM PDT 24 Jun 11 12:54:05 PM PDT 24 605533209 ps
T922 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.3694022507 Jun 11 12:53:33 PM PDT 24 Jun 11 12:53:36 PM PDT 24 18724462 ps
T923 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.2150761329 Jun 11 12:54:00 PM PDT 24 Jun 11 12:54:03 PM PDT 24 433655007 ps
T924 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.3202136462 Jun 11 12:53:55 PM PDT 24 Jun 11 12:53:57 PM PDT 24 18177283 ps
T925 /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.2966250210 Jun 11 12:54:01 PM PDT 24 Jun 11 12:54:03 PM PDT 24 17090837 ps
T926 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.4023888583 Jun 11 12:53:56 PM PDT 24 Jun 11 12:54:10 PM PDT 24 1516081627 ps
T111 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.3700091338 Jun 11 12:54:20 PM PDT 24 Jun 11 12:54:23 PM PDT 24 145191078 ps
T927 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.2994576295 Jun 11 12:53:49 PM PDT 24 Jun 11 12:53:51 PM PDT 24 145917676 ps
T928 /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.1243147813 Jun 11 12:53:23 PM PDT 24 Jun 11 12:53:26 PM PDT 24 43480520 ps
T929 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.796685360 Jun 11 12:53:48 PM PDT 24 Jun 11 12:53:51 PM PDT 24 40394879 ps
T930 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.4177052630 Jun 11 12:53:37 PM PDT 24 Jun 11 12:53:39 PM PDT 24 664928335 ps
T931 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.3342090490 Jun 11 12:54:00 PM PDT 24 Jun 11 12:54:11 PM PDT 24 1656531259 ps
T932 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.1716590578 Jun 11 12:53:49 PM PDT 24 Jun 11 12:53:53 PM PDT 24 176594302 ps
T933 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.1120235969 Jun 11 12:54:12 PM PDT 24 Jun 11 12:54:15 PM PDT 24 59043195 ps
T934 /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.2021672199 Jun 11 12:53:34 PM PDT 24 Jun 11 12:53:36 PM PDT 24 100666923 ps
T935 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.1860736930 Jun 11 12:53:21 PM PDT 24 Jun 11 12:53:23 PM PDT 24 342417417 ps
T127 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.1437619711 Jun 11 12:53:50 PM PDT 24 Jun 11 12:53:54 PM PDT 24 76775182 ps
T936 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3455300066 Jun 11 12:54:13 PM PDT 24 Jun 11 12:54:17 PM PDT 24 330037302 ps
T937 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.778705361 Jun 11 12:53:49 PM PDT 24 Jun 11 12:53:55 PM PDT 24 1032112762 ps
T938 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.2554632760 Jun 11 12:54:33 PM PDT 24 Jun 11 12:54:36 PM PDT 24 23293231 ps
T939 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.1955893904 Jun 11 12:53:48 PM PDT 24 Jun 11 12:53:50 PM PDT 24 40807226 ps
T940 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.1151538073 Jun 11 12:53:33 PM PDT 24 Jun 11 12:54:01 PM PDT 24 1244112842 ps
T941 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.637464975 Jun 11 12:54:17 PM PDT 24 Jun 11 12:54:20 PM PDT 24 258694131 ps
T942 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.1005863950 Jun 11 12:54:12 PM PDT 24 Jun 11 12:54:15 PM PDT 24 17046466 ps
T943 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1261741408 Jun 11 12:54:01 PM PDT 24 Jun 11 12:54:04 PM PDT 24 207379806 ps
T944 /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.3657217719 Jun 11 12:54:27 PM PDT 24 Jun 11 12:54:29 PM PDT 24 31226277 ps
T945 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.176781194 Jun 11 12:54:11 PM PDT 24 Jun 11 12:54:14 PM PDT 24 15541166 ps
T946 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.560520845 Jun 11 12:53:49 PM PDT 24 Jun 11 12:53:52 PM PDT 24 51510856 ps
T947 /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.97006714 Jun 11 12:54:27 PM PDT 24 Jun 11 12:54:29 PM PDT 24 30603879 ps
T948 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.1468336732 Jun 11 12:53:48 PM PDT 24 Jun 11 12:53:50 PM PDT 24 87908913 ps
T190 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.3428969333 Jun 11 12:53:35 PM PDT 24 Jun 11 12:53:37 PM PDT 24 62665856 ps
T949 /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.1467059022 Jun 11 12:54:26 PM PDT 24 Jun 11 12:54:29 PM PDT 24 680360695 ps
T950 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.1045090232 Jun 11 12:53:55 PM PDT 24 Jun 11 12:53:58 PM PDT 24 46026454 ps
T951 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.1247541503 Jun 11 12:54:15 PM PDT 24 Jun 11 12:54:21 PM PDT 24 108824808 ps
T952 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.37606126 Jun 11 12:53:22 PM PDT 24 Jun 11 12:53:29 PM PDT 24 628273753 ps
T953 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.164632261 Jun 11 12:53:24 PM PDT 24 Jun 11 12:53:27 PM PDT 24 23082705 ps
T954 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.3810197585 Jun 11 12:54:24 PM PDT 24 Jun 11 12:54:27 PM PDT 24 25248584 ps
T122 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.2304186493 Jun 11 12:54:22 PM PDT 24 Jun 11 12:54:27 PM PDT 24 786702678 ps
T955 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.1136977083 Jun 11 12:54:24 PM PDT 24 Jun 11 12:54:26 PM PDT 24 26979483 ps
T956 /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.424448331 Jun 11 12:54:00 PM PDT 24 Jun 11 12:54:03 PM PDT 24 24552772 ps
T957 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.352465975 Jun 11 12:53:47 PM PDT 24 Jun 11 12:53:49 PM PDT 24 383442228 ps
T128 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.3694554454 Jun 11 12:54:12 PM PDT 24 Jun 11 12:54:15 PM PDT 24 930265688 ps
T958 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.1234152276 Jun 11 12:54:13 PM PDT 24 Jun 11 12:54:17 PM PDT 24 47702692 ps
T129 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.705226771 Jun 11 12:54:24 PM PDT 24 Jun 11 12:54:31 PM PDT 24 623901663 ps
T126 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.2018517344 Jun 11 12:54:12 PM PDT 24 Jun 11 12:54:17 PM PDT 24 82219212 ps
T959 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.1696407327 Jun 11 12:54:21 PM PDT 24 Jun 11 12:54:24 PM PDT 24 15720715 ps
T192 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.1869804015 Jun 11 12:53:23 PM PDT 24 Jun 11 12:53:27 PM PDT 24 45979850 ps
T960 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.3121516627 Jun 11 12:53:59 PM PDT 24 Jun 11 12:54:03 PM PDT 24 311881655 ps
T961 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.13415283 Jun 11 12:54:13 PM PDT 24 Jun 11 12:54:36 PM PDT 24 7264169205 ps
T962 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.733429579 Jun 11 12:54:29 PM PDT 24 Jun 11 12:54:33 PM PDT 24 25317604 ps
T963 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.463293904 Jun 11 12:53:22 PM PDT 24 Jun 11 12:53:26 PM PDT 24 38160880 ps
T964 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2623110717 Jun 11 12:53:35 PM PDT 24 Jun 11 12:53:38 PM PDT 24 72637404 ps
T965 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.2534897901 Jun 11 12:54:13 PM PDT 24 Jun 11 12:54:16 PM PDT 24 128560176 ps
T131 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.1652456191 Jun 11 12:54:11 PM PDT 24 Jun 11 12:54:15 PM PDT 24 55659071 ps
T966 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.2381224335 Jun 11 12:53:47 PM PDT 24 Jun 11 12:53:51 PM PDT 24 91245217 ps
T967 /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.1926536496 Jun 11 12:54:27 PM PDT 24 Jun 11 12:54:30 PM PDT 24 86341725 ps
T132 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.3146391759 Jun 11 12:54:24 PM PDT 24 Jun 11 12:54:27 PM PDT 24 113684962 ps
T968 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.1814678459 Jun 11 12:54:21 PM PDT 24 Jun 11 12:54:24 PM PDT 24 61669820 ps
T123 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.806798838 Jun 11 12:53:47 PM PDT 24 Jun 11 12:53:50 PM PDT 24 107974960 ps
T969 /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.3254345411 Jun 11 12:53:59 PM PDT 24 Jun 11 12:54:01 PM PDT 24 274685286 ps
T970 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.3353536804 Jun 11 12:54:25 PM PDT 24 Jun 11 12:54:28 PM PDT 24 61371518 ps
T971 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.3714431118 Jun 11 12:53:50 PM PDT 24 Jun 11 12:53:52 PM PDT 24 27516059 ps
T972 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.4054116339 Jun 11 12:53:20 PM PDT 24 Jun 11 12:53:22 PM PDT 24 20018323 ps
T973 /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.4206771706 Jun 11 12:54:12 PM PDT 24 Jun 11 12:54:15 PM PDT 24 19765155 ps
T974 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.1122384801 Jun 11 12:54:23 PM PDT 24 Jun 11 12:54:27 PM PDT 24 602584807 ps
T975 /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.2235258840 Jun 11 12:54:29 PM PDT 24 Jun 11 12:54:31 PM PDT 24 58167763 ps
T976 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.30155955 Jun 11 12:53:58 PM PDT 24 Jun 11 12:54:04 PM PDT 24 775200015 ps
T193 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.1826107575 Jun 11 12:54:00 PM PDT 24 Jun 11 12:54:02 PM PDT 24 14506788 ps
T124 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.1635741138 Jun 11 12:54:27 PM PDT 24 Jun 11 12:54:31 PM PDT 24 627616271 ps
T977 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2332834212 Jun 11 12:54:10 PM PDT 24 Jun 11 12:54:13 PM PDT 24 213728682 ps
T978 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.216375798 Jun 11 12:54:14 PM PDT 24 Jun 11 12:54:18 PM PDT 24 142914705 ps
T979 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.3751592736 Jun 11 12:53:50 PM PDT 24 Jun 11 12:53:54 PM PDT 24 345441691 ps
T980 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3174338611 Jun 11 12:53:21 PM PDT 24 Jun 11 12:53:25 PM PDT 24 175988258 ps
T981 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.482388417 Jun 11 12:54:22 PM PDT 24 Jun 11 12:54:25 PM PDT 24 108820866 ps
T982 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.3357327380 Jun 11 12:54:13 PM PDT 24 Jun 11 12:54:18 PM PDT 24 62461687 ps
T983 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.2355583445 Jun 11 12:54:12 PM PDT 24 Jun 11 12:54:15 PM PDT 24 110889879 ps
T984 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.3179779536 Jun 11 12:54:29 PM PDT 24 Jun 11 12:54:30 PM PDT 24 12308719 ps
T985 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.589342561 Jun 11 12:54:13 PM PDT 24 Jun 11 12:54:26 PM PDT 24 4292309365 ps
T986 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.2321307221 Jun 11 12:54:13 PM PDT 24 Jun 11 12:54:17 PM PDT 24 94226292 ps
T987 /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.3014509690 Jun 11 12:54:22 PM PDT 24 Jun 11 12:54:25 PM PDT 24 127240090 ps
T191 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.3225981266 Jun 11 12:54:20 PM PDT 24 Jun 11 12:54:22 PM PDT 24 40734416 ps
T988 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.1326912358 Jun 11 12:53:34 PM PDT 24 Jun 11 12:53:36 PM PDT 24 24793555 ps
T989 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.3350402989 Jun 11 12:53:49 PM PDT 24 Jun 11 12:54:00 PM PDT 24 10132107286 ps
T112 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.1542811157 Jun 11 12:53:59 PM PDT 24 Jun 11 12:54:05 PM PDT 24 408722237 ps
T990 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.2099727841 Jun 11 12:54:11 PM PDT 24 Jun 11 12:54:13 PM PDT 24 20604549 ps
T991 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4101070223 Jun 11 12:53:50 PM PDT 24 Jun 11 12:53:53 PM PDT 24 103241872 ps
T992 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.3007060314 Jun 11 12:53:32 PM PDT 24 Jun 11 12:53:35 PM PDT 24 32400961 ps
T993 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.1589145128 Jun 11 12:53:48 PM PDT 24 Jun 11 12:53:50 PM PDT 24 58416024 ps
T994 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.1128689829 Jun 11 12:53:34 PM PDT 24 Jun 11 12:53:37 PM PDT 24 124394823 ps
T995 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.2273755157 Jun 11 12:54:10 PM PDT 24 Jun 11 12:54:12 PM PDT 24 22524660 ps

Test location /workspace/coverage/default/45.lc_ctrl_security_escalation.2430048538
Short name T15
Test name
Test status
Simulation time 1259949003 ps
CPU time 12.78 seconds
Started Jun 11 02:14:31 PM PDT 24
Finished Jun 11 02:14:45 PM PDT 24
Peak memory 226544 kb
Host smart-e37f1c5e-965f-4c9e-bf50-2266b25cf673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430048538 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_security_escalation.2430048538
Directory /workspace/45.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all.1530013688
Short name T5
Test name
Test status
Simulation time 8549163159 ps
CPU time 238.34 seconds
Started Jun 11 02:14:13 PM PDT 24
Finished Jun 11 02:18:12 PM PDT 24
Peak memory 280144 kb
Host smart-868e7768-9f31-4f62-a40f-6abf314541d8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530013688 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.lc_ctrl_stress_all.1530013688
Directory /workspace/33.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_mubi.9733373
Short name T38
Test name
Test status
Simulation time 388241130 ps
CPU time 12.92 seconds
Started Jun 11 02:13:15 PM PDT 24
Finished Jun 11 02:13:30 PM PDT 24
Peak memory 218844 kb
Host smart-c696f10e-b90f-40f5-98db-f096693b5f50
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9733373 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_mubi.9733373
Directory /workspace/13.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/10.lc_ctrl_security_escalation.987446749
Short name T35
Test name
Test status
Simulation time 426666688 ps
CPU time 7.06 seconds
Started Jun 11 02:13:02 PM PDT 24
Finished Jun 11 02:13:13 PM PDT 24
Peak memory 226424 kb
Host smart-b048b722-93c6-419e-a36d-a6eb404d3ec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987446749 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_security_escalation.987446749
Directory /workspace/10.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all_with_rand_reset.3696563305
Short name T58
Test name
Test status
Simulation time 173380102965 ps
CPU time 896.98 seconds
Started Jun 11 02:13:04 PM PDT 24
Finished Jun 11 02:28:04 PM PDT 24
Peak memory 422468 kb
Host smart-4f96c9ae-5fea-4062-b351-be90a829b608
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3696563305 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_stress_all_with_rand_reset.3696563305
Directory /workspace/10.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.677790089
Short name T103
Test name
Test status
Simulation time 60176239 ps
CPU time 2.15 seconds
Started Jun 11 12:54:13 PM PDT 24
Finished Jun 11 12:54:17 PM PDT 24
Peak memory 218172 kb
Host smart-9d6b6ae3-d80a-45fa-8ed3-fc169c1c9239
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677790089 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_errors.677790089
Directory /workspace/11.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_volatile_unlock_smoke.798259994
Short name T31
Test name
Test status
Simulation time 43363382 ps
CPU time 0.88 seconds
Started Jun 11 02:12:43 PM PDT 24
Finished Jun 11 02:12:45 PM PDT 24
Peak memory 209440 kb
Host smart-0feab251-fe96-4c1a-9b7f-d55d9c128179
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798259994 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctr
l_volatile_unlock_smoke.798259994
Directory /workspace/4.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_cm.1010261735
Short name T55
Test name
Test status
Simulation time 432063893 ps
CPU time 33.98 seconds
Started Jun 11 02:12:32 PM PDT 24
Finished Jun 11 02:13:07 PM PDT 24
Peak memory 270260 kb
Host smart-4a0dc32e-a909-497c-88e5-34a6c1d009fb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010261735 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_cm.1010261735
Directory /workspace/0.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/38.lc_ctrl_jtag_access.4286830184
Short name T2
Test name
Test status
Simulation time 1874525985 ps
CPU time 4.06 seconds
Started Jun 11 02:14:22 PM PDT 24
Finished Jun 11 02:14:27 PM PDT 24
Peak memory 217536 kb
Host smart-0f392c43-242a-4b87-8cc7-d593f9a44265
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286830184 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_jtag_access.4286830184
Directory /workspace/38.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/12.lc_ctrl_stress_all_with_rand_reset.3846627527
Short name T83
Test name
Test status
Simulation time 141957751882 ps
CPU time 2104.87 seconds
Started Jun 11 02:13:16 PM PDT 24
Finished Jun 11 02:48:23 PM PDT 24
Peak memory 530120 kb
Host smart-802a72ad-2fef-4d76-91fc-495c839d719d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3846627527 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_stress_all_with_rand_reset.3846627527
Directory /workspace/12.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.611879822
Short name T105
Test name
Test status
Simulation time 256927080 ps
CPU time 2.37 seconds
Started Jun 11 12:54:18 PM PDT 24
Finished Jun 11 12:54:21 PM PDT 24
Peak memory 218116 kb
Host smart-c5a05556-df81-4c66-9348-ee7392126823
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611879822 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_intg_
err.611879822
Directory /workspace/11.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/8.lc_ctrl_security_escalation.2624568686
Short name T210
Test name
Test status
Simulation time 1706604701 ps
CPU time 15.45 seconds
Started Jun 11 02:12:56 PM PDT 24
Finished Jun 11 02:13:15 PM PDT 24
Peak memory 226484 kb
Host smart-f8cea6e3-26f5-4a59-b2a4-9f4cf8fc8a84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624568686 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_security_escalation.2624568686
Directory /workspace/8.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_mux.3522279296
Short name T3
Test name
Test status
Simulation time 935617079 ps
CPU time 17.07 seconds
Started Jun 11 02:14:19 PM PDT 24
Finished Jun 11 02:14:37 PM PDT 24
Peak memory 218732 kb
Host smart-46fd1ec5-ea4d-4ece-be6b-4d059b5564c3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522279296 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_mux.
3522279296
Directory /workspace/36.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/28.lc_ctrl_alert_test.752619202
Short name T10
Test name
Test status
Simulation time 19597188 ps
CPU time 0.94 seconds
Started Jun 11 02:13:58 PM PDT 24
Finished Jun 11 02:14:01 PM PDT 24
Peak memory 209364 kb
Host smart-a12b7c8b-c1df-4c4a-8359-488329f2c776
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752619202 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_alert_test.752619202
Directory /workspace/28.lc_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.2654668033
Short name T183
Test name
Test status
Simulation time 18530894 ps
CPU time 1.13 seconds
Started Jun 11 12:53:22 PM PDT 24
Finished Jun 11 12:53:25 PM PDT 24
Peak memory 209824 kb
Host smart-f7c22e94-e05d-4142-8562-01b17231ee5a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654668033 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_rw.2654668033
Directory /workspace/0.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.4181127360
Short name T107
Test name
Test status
Simulation time 643139696 ps
CPU time 2.22 seconds
Started Jun 11 12:53:22 PM PDT 24
Finished Jun 11 12:53:25 PM PDT 24
Peak memory 209808 kb
Host smart-0ceb56c0-d24f-4c76-8d78-1bf6a9e3ce81
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181127360 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.lc_ctrl_jtag_csr_rw.4181127360
Directory /workspace/0.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/default/32.lc_ctrl_errors.1119417634
Short name T42
Test name
Test status
Simulation time 2192764413 ps
CPU time 11.09 seconds
Started Jun 11 02:14:05 PM PDT 24
Finished Jun 11 02:14:18 PM PDT 24
Peak memory 218756 kb
Host smart-63a37732-30d4-4ed0-b00a-0f10e82256bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119417634 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_errors.1119417634
Directory /workspace/32.lc_ctrl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.137878393
Short name T118
Test name
Test status
Simulation time 962508835 ps
CPU time 2.99 seconds
Started Jun 11 12:53:23 PM PDT 24
Finished Jun 11 12:53:28 PM PDT 24
Peak memory 222776 kb
Host smart-7ec66d61-d374-458b-b489-8b5a142f8e42
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137878393 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_intg_e
rr.137878393
Directory /workspace/0.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_errors.2841284703
Short name T4
Test name
Test status
Simulation time 30085103999 ps
CPU time 87.63 seconds
Started Jun 11 02:13:06 PM PDT 24
Finished Jun 11 02:14:37 PM PDT 24
Peak memory 219528 kb
Host smart-f91436e6-b332-412a-9e48-7bf0c0548ffc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841284703 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_e
rrors.2841284703
Directory /workspace/10.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.2764810136
Short name T119
Test name
Test status
Simulation time 78359601 ps
CPU time 3.45 seconds
Started Jun 11 12:53:36 PM PDT 24
Finished Jun 11 12:53:40 PM PDT 24
Peak memory 222848 kb
Host smart-85c02f00-5100-4cc6-bfba-d275f1fcd68a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764810136 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_intg_
err.2764810136
Directory /workspace/1.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.2389405824
Short name T120
Test name
Test status
Simulation time 259153309 ps
CPU time 3.13 seconds
Started Jun 11 12:54:21 PM PDT 24
Finished Jun 11 12:54:25 PM PDT 24
Peak memory 222632 kb
Host smart-dca2fc18-662a-42fd-929a-da546c525e3b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389405824 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_intg
_err.2389405824
Directory /workspace/15.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_failure.796747711
Short name T100
Test name
Test status
Simulation time 1801433933 ps
CPU time 25.42 seconds
Started Jun 11 02:14:14 PM PDT 24
Finished Jun 11 02:14:41 PM PDT 24
Peak memory 251476 kb
Host smart-5b61b108-f2d1-4dfe-a717-8e18a9420989
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796747711 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_failure.796747711
Directory /workspace/38.lc_ctrl_state_failure/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.1437619711
Short name T127
Test name
Test status
Simulation time 76775182 ps
CPU time 2.74 seconds
Started Jun 11 12:53:50 PM PDT 24
Finished Jun 11 12:53:54 PM PDT 24
Peak memory 223040 kb
Host smart-15c08a2f-d01b-416a-b8e1-3310256dfea3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437619711 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_intg_
err.1437619711
Directory /workspace/3.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.157284171
Short name T130
Test name
Test status
Simulation time 73951489 ps
CPU time 3.42 seconds
Started Jun 11 12:53:59 PM PDT 24
Finished Jun 11 12:54:03 PM PDT 24
Peak memory 222656 kb
Host smart-71b08ce3-25d9-4663-a034-5dd436ed7411
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157284171 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_intg_e
rr.157284171
Directory /workspace/6.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.1247541503
Short name T951
Test name
Test status
Simulation time 108824808 ps
CPU time 4.39 seconds
Started Jun 11 12:54:15 PM PDT 24
Finished Jun 11 12:54:21 PM PDT 24
Peak memory 217888 kb
Host smart-06059a48-dcbe-4668-9351-ab9f63f3c0b8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247541503 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_errors.1247541503
Directory /workspace/10.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.1635741138
Short name T124
Test name
Test status
Simulation time 627616271 ps
CPU time 2.92 seconds
Started Jun 11 12:54:27 PM PDT 24
Finished Jun 11 12:54:31 PM PDT 24
Peak memory 218080 kb
Host smart-67b157d9-9ec7-4206-a579-954188103de3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635741138 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_intg
_err.1635741138
Directory /workspace/12.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.21970068
Short name T125
Test name
Test status
Simulation time 272003991 ps
CPU time 3.07 seconds
Started Jun 11 12:53:35 PM PDT 24
Finished Jun 11 12:53:39 PM PDT 24
Peak memory 218148 kb
Host smart-14c371fd-ff37-42e1-9eb9-9d9832b7a38c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21970068 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_intg_er
r.21970068
Directory /workspace/2.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/1.lc_ctrl_claim_transition_if.3079726780
Short name T206
Test name
Test status
Simulation time 14125605 ps
CPU time 0.82 seconds
Started Jun 11 02:12:29 PM PDT 24
Finished Jun 11 02:12:32 PM PDT 24
Peak memory 209224 kb
Host smart-9535bfb0-85b8-4846-a310-361064e48b76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079726780 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_claim_transition_if.3079726780
Directory /workspace/1.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/4.lc_ctrl_claim_transition_if.2649968508
Short name T203
Test name
Test status
Simulation time 19336540 ps
CPU time 0.92 seconds
Started Jun 11 02:12:45 PM PDT 24
Finished Jun 11 02:12:47 PM PDT 24
Peak memory 209324 kb
Host smart-c1aa18ec-2c07-4fd8-9bd5-170a2c05ec6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649968508 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_claim_transition_if.2649968508
Directory /workspace/4.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/7.lc_ctrl_claim_transition_if.515491234
Short name T208
Test name
Test status
Simulation time 12025566 ps
CPU time 0.84 seconds
Started Jun 11 02:12:52 PM PDT 24
Finished Jun 11 02:12:54 PM PDT 24
Peak memory 209380 kb
Host smart-0f7f9cb8-a80c-4fcb-b0d1-47b46f5d377c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515491234 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_claim_transition_if.515491234
Directory /workspace/7.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/8.lc_ctrl_claim_transition_if.2579960421
Short name T70
Test name
Test status
Simulation time 17980630 ps
CPU time 0.81 seconds
Started Jun 11 02:12:55 PM PDT 24
Finished Jun 11 02:12:59 PM PDT 24
Peak memory 209248 kb
Host smart-7301d6b8-557a-4402-8e59-3b8a1528e989
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579960421 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_claim_transition_if.2579960421
Directory /workspace/8.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_failure.3965545787
Short name T9
Test name
Test status
Simulation time 14012883719 ps
CPU time 96.7 seconds
Started Jun 11 02:13:33 PM PDT 24
Finished Jun 11 02:15:11 PM PDT 24
Peak memory 284072 kb
Host smart-13c404e9-b480-4d8c-a73e-f3f530716d6c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965545787 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jt
ag_state_failure.3965545787
Directory /workspace/15.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.3700091338
Short name T111
Test name
Test status
Simulation time 145191078 ps
CPU time 1.78 seconds
Started Jun 11 12:54:20 PM PDT 24
Finished Jun 11 12:54:23 PM PDT 24
Peak memory 222132 kb
Host smart-317262c7-01cb-47b9-8ffe-d5d91e1b8884
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700091338 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_intg
_err.3700091338
Directory /workspace/19.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.2018517344
Short name T126
Test name
Test status
Simulation time 82219212 ps
CPU time 3.56 seconds
Started Jun 11 12:54:12 PM PDT 24
Finished Jun 11 12:54:17 PM PDT 24
Peak memory 222932 kb
Host smart-34415b17-b926-42d2-aed6-bc64f251744f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018517344 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_intg_
err.2018517344
Directory /workspace/7.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.1464433487
Short name T117
Test name
Test status
Simulation time 224168860 ps
CPU time 1.95 seconds
Started Jun 11 12:54:11 PM PDT 24
Finished Jun 11 12:54:14 PM PDT 24
Peak memory 222416 kb
Host smart-16118f4c-9734-4723-860d-b7f10adde935
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464433487 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_intg_
err.1464433487
Directory /workspace/9.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all.1530712826
Short name T18
Test name
Test status
Simulation time 21286509868 ps
CPU time 213.55 seconds
Started Jun 11 02:12:29 PM PDT 24
Finished Jun 11 02:16:04 PM PDT 24
Peak memory 350012 kb
Host smart-ca030458-a6ff-4944-8ca2-77cd5fb3f7d4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530712826 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.lc_ctrl_stress_all.1530712826
Directory /workspace/0.lc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.1869804015
Short name T192
Test name
Test status
Simulation time 45979850 ps
CPU time 1.43 seconds
Started Jun 11 12:53:23 PM PDT 24
Finished Jun 11 12:53:27 PM PDT 24
Peak memory 217688 kb
Host smart-f493b529-f8b7-43df-a5a4-bcb2ff59bcc8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869804015 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_aliasin
g.1869804015
Directory /workspace/0.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.4174016761
Short name T909
Test name
Test status
Simulation time 97514103 ps
CPU time 3.18 seconds
Started Jun 11 12:53:22 PM PDT 24
Finished Jun 11 12:53:27 PM PDT 24
Peak memory 209804 kb
Host smart-1598c80a-01d3-4d62-a735-664d9bfc6e56
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174016761 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_bit_bas
h.4174016761
Directory /workspace/0.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.4054116339
Short name T972
Test name
Test status
Simulation time 20018323 ps
CPU time 1.28 seconds
Started Jun 11 12:53:20 PM PDT 24
Finished Jun 11 12:53:22 PM PDT 24
Peak memory 218540 kb
Host smart-a1a14ea6-4ebf-4ecd-b86c-f77051f7f015
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054116339 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_hw_rese
t.4054116339
Directory /workspace/0.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.164632261
Short name T953
Test name
Test status
Simulation time 23082705 ps
CPU time 1.39 seconds
Started Jun 11 12:53:24 PM PDT 24
Finished Jun 11 12:53:27 PM PDT 24
Peak memory 219316 kb
Host smart-245b48d3-ab80-4792-8918-c65c686d68b7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164632261 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 0.lc_ctrl_csr_mem_rw_with_rand_reset.164632261
Directory /workspace/0.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.1860736930
Short name T935
Test name
Test status
Simulation time 342417417 ps
CPU time 1.15 seconds
Started Jun 11 12:53:21 PM PDT 24
Finished Jun 11 12:53:23 PM PDT 24
Peak memory 209704 kb
Host smart-4f8244bc-5321-4efe-9a96-41774998c9cf
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860736930 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.lc_ctrl_jtag_alert_test.1860736930
Directory /workspace/0.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.872289255
Short name T886
Test name
Test status
Simulation time 588960324 ps
CPU time 13.18 seconds
Started Jun 11 12:53:23 PM PDT 24
Finished Jun 11 12:53:38 PM PDT 24
Peak memory 209504 kb
Host smart-6a17b5e9-c993-4a85-9aa2-738088ac66ca
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872289255 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 0.lc_ctrl_jtag_csr_aliasing.872289255
Directory /workspace/0.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.37529048
Short name T899
Test name
Test status
Simulation time 2420121855 ps
CPU time 12.18 seconds
Started Jun 11 12:53:24 PM PDT 24
Finished Jun 11 12:53:38 PM PDT 24
Peak memory 217400 kb
Host smart-15ec79e1-002d-47d0-b673-14a92b8b74ca
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37529048 -assert nopostproc +UVM_TESTNAME=lc_ctrl_bas
e_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 0.lc_ctrl_jtag_csr_bit_bash.37529048
Directory /workspace/0.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.4180730336
Short name T875
Test name
Test status
Simulation time 102567480 ps
CPU time 1.29 seconds
Started Jun 11 12:53:21 PM PDT 24
Finished Jun 11 12:53:23 PM PDT 24
Peak memory 211240 kb
Host smart-e926df1d-9dab-4778-8017-ab6996647f8c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180730336 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_hw_reset.4180730336
Directory /workspace/0.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3174338611
Short name T980
Test name
Test status
Simulation time 175988258 ps
CPU time 3.15 seconds
Started Jun 11 12:53:21 PM PDT 24
Finished Jun 11 12:53:25 PM PDT 24
Peak memory 219068 kb
Host smart-5166b5b7-fe16-4ce5-aadb-0b07d73beec7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317433
8611 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3174338611
Directory /workspace/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.463293904
Short name T963
Test name
Test status
Simulation time 38160880 ps
CPU time 1.25 seconds
Started Jun 11 12:53:22 PM PDT 24
Finished Jun 11 12:53:26 PM PDT 24
Peak memory 209912 kb
Host smart-b43b0f9a-ed03-4eb7-ae10-2851d629b3fb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463293904 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.lc_ctrl_jtag_same_csr_outstanding.463293904
Directory /workspace/0.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.1243147813
Short name T928
Test name
Test status
Simulation time 43480520 ps
CPU time 1 seconds
Started Jun 11 12:53:23 PM PDT 24
Finished Jun 11 12:53:26 PM PDT 24
Peak memory 209604 kb
Host smart-9df53ff8-03e1-4a23-bd7b-0d2db41ff8e2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243147813 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl
_same_csr_outstanding.1243147813
Directory /workspace/0.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.37606126
Short name T952
Test name
Test status
Simulation time 628273753 ps
CPU time 5.02 seconds
Started Jun 11 12:53:22 PM PDT 24
Finished Jun 11 12:53:29 PM PDT 24
Peak memory 218324 kb
Host smart-6ed44a4d-da04-4839-bbb3-38402774065d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37606126 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_errors.37606126
Directory /workspace/0.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.3441289211
Short name T148
Test name
Test status
Simulation time 93611568 ps
CPU time 1.35 seconds
Started Jun 11 12:53:32 PM PDT 24
Finished Jun 11 12:53:35 PM PDT 24
Peak memory 209880 kb
Host smart-cf622513-2ac6-4084-9a67-527331209723
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441289211 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_aliasin
g.3441289211
Directory /workspace/1.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.2949738013
Short name T877
Test name
Test status
Simulation time 54031132 ps
CPU time 1.34 seconds
Started Jun 11 12:53:33 PM PDT 24
Finished Jun 11 12:53:35 PM PDT 24
Peak memory 209604 kb
Host smart-2e021e00-4073-43a8-91ec-8ea43b953afe
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949738013 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_bit_bas
h.2949738013
Directory /workspace/1.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.1291417911
Short name T182
Test name
Test status
Simulation time 13616068 ps
CPU time 1.02 seconds
Started Jun 11 12:53:37 PM PDT 24
Finished Jun 11 12:53:39 PM PDT 24
Peak memory 210728 kb
Host smart-310395cc-9328-4147-9c0c-a6d30a1e37c2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291417911 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_hw_rese
t.1291417911
Directory /workspace/1.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.3007060314
Short name T992
Test name
Test status
Simulation time 32400961 ps
CPU time 1.16 seconds
Started Jun 11 12:53:32 PM PDT 24
Finished Jun 11 12:53:35 PM PDT 24
Peak memory 219608 kb
Host smart-f4f9b41c-8020-4114-b059-4f992606a9eb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007060314 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 1.lc_ctrl_csr_mem_rw_with_rand_reset.3007060314
Directory /workspace/1.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.3428969333
Short name T190
Test name
Test status
Simulation time 62665856 ps
CPU time 1.06 seconds
Started Jun 11 12:53:35 PM PDT 24
Finished Jun 11 12:53:37 PM PDT 24
Peak memory 210056 kb
Host smart-04b779c3-9673-4e01-9c00-a7b5bacf98cc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428969333 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_rw.3428969333
Directory /workspace/1.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.2732890103
Short name T908
Test name
Test status
Simulation time 134483940 ps
CPU time 2.28 seconds
Started Jun 11 12:53:35 PM PDT 24
Finished Jun 11 12:53:38 PM PDT 24
Peak memory 209940 kb
Host smart-532db2ed-7cbc-4ffe-b1da-88637dfd5d73
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732890103 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.lc_ctrl_jtag_alert_test.2732890103
Directory /workspace/1.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.205814045
Short name T876
Test name
Test status
Simulation time 1302316466 ps
CPU time 28.66 seconds
Started Jun 11 12:53:35 PM PDT 24
Finished Jun 11 12:54:04 PM PDT 24
Peak memory 209832 kb
Host smart-3d235129-60f5-4af7-a175-dfb2f7e419d4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205814045 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 1.lc_ctrl_jtag_csr_aliasing.205814045
Directory /workspace/1.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.3744914540
Short name T904
Test name
Test status
Simulation time 1863737288 ps
CPU time 6.31 seconds
Started Jun 11 12:53:35 PM PDT 24
Finished Jun 11 12:53:42 PM PDT 24
Peak memory 209736 kb
Host smart-df7ff34b-c5ec-4b12-86cb-dfb22191174e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744914540 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_bit_bash.3744914540
Directory /workspace/1.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.414342384
Short name T890
Test name
Test status
Simulation time 46604334 ps
CPU time 1.76 seconds
Started Jun 11 12:53:23 PM PDT 24
Finished Jun 11 12:53:26 PM PDT 24
Peak memory 217956 kb
Host smart-068e622f-7f11-469a-9740-21873aa02e91
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414342384 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 1.lc_ctrl_jtag_csr_hw_reset.414342384
Directory /workspace/1.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2623110717
Short name T964
Test name
Test status
Simulation time 72637404 ps
CPU time 1.51 seconds
Started Jun 11 12:53:35 PM PDT 24
Finished Jun 11 12:53:38 PM PDT 24
Peak memory 219228 kb
Host smart-21cf8f54-6442-4ac4-a3eb-e93a3f9f04df
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262311
0717 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2623110717
Directory /workspace/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.2717548118
Short name T878
Test name
Test status
Simulation time 89887045 ps
CPU time 1.12 seconds
Started Jun 11 12:53:33 PM PDT 24
Finished Jun 11 12:53:35 PM PDT 24
Peak memory 209708 kb
Host smart-6fc3863e-240d-4080-b520-2b5d059d0849
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717548118 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.lc_ctrl_jtag_csr_rw.2717548118
Directory /workspace/1.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.1061410415
Short name T198
Test name
Test status
Simulation time 22518501 ps
CPU time 1.38 seconds
Started Jun 11 12:53:35 PM PDT 24
Finished Jun 11 12:53:38 PM PDT 24
Peak memory 218148 kb
Host smart-ea984cca-1ce3-4446-af6e-eb73a2ca20d7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061410415 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.lc_ctrl_jtag_same_csr_outstanding.1061410415
Directory /workspace/1.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.2021672199
Short name T934
Test name
Test status
Simulation time 100666923 ps
CPU time 1.01 seconds
Started Jun 11 12:53:34 PM PDT 24
Finished Jun 11 12:53:36 PM PDT 24
Peak memory 209940 kb
Host smart-2357a7c8-5e77-4543-8d6b-c1ac2079e478
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021672199 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl
_same_csr_outstanding.2021672199
Directory /workspace/1.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.4265769985
Short name T101
Test name
Test status
Simulation time 54098117 ps
CPU time 1.7 seconds
Started Jun 11 12:53:34 PM PDT 24
Finished Jun 11 12:53:37 PM PDT 24
Peak memory 219220 kb
Host smart-92a2947c-1654-4fd2-9b49-30146b12b5e4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265769985 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_errors.4265769985
Directory /workspace/1.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.4263933663
Short name T891
Test name
Test status
Simulation time 22414422 ps
CPU time 1.08 seconds
Started Jun 11 12:54:18 PM PDT 24
Finished Jun 11 12:54:20 PM PDT 24
Peak memory 219480 kb
Host smart-2d93f4c8-f3d8-42ad-8c5f-22d6e2c4bdb6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263933663 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 10.lc_ctrl_csr_mem_rw_with_rand_reset.4263933663
Directory /workspace/10.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.2355583445
Short name T983
Test name
Test status
Simulation time 110889879 ps
CPU time 1.11 seconds
Started Jun 11 12:54:12 PM PDT 24
Finished Jun 11 12:54:15 PM PDT 24
Peak memory 209852 kb
Host smart-2863d898-0338-4466-91c1-f66083213b1c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355583445 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_csr_rw.2355583445
Directory /workspace/10.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.140196694
Short name T108
Test name
Test status
Simulation time 29145005 ps
CPU time 1.51 seconds
Started Jun 11 12:54:13 PM PDT 24
Finished Jun 11 12:54:16 PM PDT 24
Peak memory 209920 kb
Host smart-a937d3c4-5cc8-4f18-90b0-a544a942c7b8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140196694 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl
_same_csr_outstanding.140196694
Directory /workspace/10.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.1652456191
Short name T131
Test name
Test status
Simulation time 55659071 ps
CPU time 2.65 seconds
Started Jun 11 12:54:11 PM PDT 24
Finished Jun 11 12:54:15 PM PDT 24
Peak memory 218172 kb
Host smart-1bfbe6e6-6778-4e44-b616-e9fe4c45fb81
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652456191 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_intg
_err.1652456191
Directory /workspace/10.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.3617613497
Short name T874
Test name
Test status
Simulation time 79112936 ps
CPU time 1.44 seconds
Started Jun 11 12:54:27 PM PDT 24
Finished Jun 11 12:54:30 PM PDT 24
Peak memory 222136 kb
Host smart-f1f52596-a5b6-4593-84e0-5ce327973271
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617613497 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 11.lc_ctrl_csr_mem_rw_with_rand_reset.3617613497
Directory /workspace/11.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.3938098229
Short name T186
Test name
Test status
Simulation time 16111521 ps
CPU time 0.94 seconds
Started Jun 11 12:54:22 PM PDT 24
Finished Jun 11 12:54:25 PM PDT 24
Peak memory 209216 kb
Host smart-81725c8f-b979-40ad-b158-18343be51348
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938098229 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_csr_rw.3938098229
Directory /workspace/11.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.1467059022
Short name T949
Test name
Test status
Simulation time 680360695 ps
CPU time 1.37 seconds
Started Jun 11 12:54:26 PM PDT 24
Finished Jun 11 12:54:29 PM PDT 24
Peak memory 211756 kb
Host smart-62ee983f-475e-4d65-a6c0-af556d54d973
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467059022 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctr
l_same_csr_outstanding.1467059022
Directory /workspace/11.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.482388417
Short name T981
Test name
Test status
Simulation time 108820866 ps
CPU time 1.24 seconds
Started Jun 11 12:54:22 PM PDT 24
Finished Jun 11 12:54:25 PM PDT 24
Peak memory 219364 kb
Host smart-f57e135f-094d-4859-8721-7cc53263df38
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482388417 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 12.lc_ctrl_csr_mem_rw_with_rand_reset.482388417
Directory /workspace/12.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.1136977083
Short name T955
Test name
Test status
Simulation time 26979483 ps
CPU time 1.03 seconds
Started Jun 11 12:54:24 PM PDT 24
Finished Jun 11 12:54:26 PM PDT 24
Peak memory 209872 kb
Host smart-a279d586-f3ef-4393-babf-d98956cb7a03
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136977083 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_csr_rw.1136977083
Directory /workspace/12.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.2235258840
Short name T975
Test name
Test status
Simulation time 58167763 ps
CPU time 1.49 seconds
Started Jun 11 12:54:29 PM PDT 24
Finished Jun 11 12:54:31 PM PDT 24
Peak memory 211996 kb
Host smart-10b622f5-7fde-4dae-b6ae-5bd7e9a29cb8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235258840 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctr
l_same_csr_outstanding.2235258840
Directory /workspace/12.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.2491337922
Short name T918
Test name
Test status
Simulation time 138357309 ps
CPU time 4.54 seconds
Started Jun 11 12:54:21 PM PDT 24
Finished Jun 11 12:54:26 PM PDT 24
Peak memory 218692 kb
Host smart-1028d118-7a92-4e11-8d82-eac662b43b52
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491337922 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_errors.2491337922
Directory /workspace/12.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.3810197585
Short name T954
Test name
Test status
Simulation time 25248584 ps
CPU time 1.37 seconds
Started Jun 11 12:54:24 PM PDT 24
Finished Jun 11 12:54:27 PM PDT 24
Peak memory 218456 kb
Host smart-db7e0a94-db21-4168-be96-6d82aa60b745
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810197585 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 13.lc_ctrl_csr_mem_rw_with_rand_reset.3810197585
Directory /workspace/13.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.3225981266
Short name T191
Test name
Test status
Simulation time 40734416 ps
CPU time 1.08 seconds
Started Jun 11 12:54:20 PM PDT 24
Finished Jun 11 12:54:22 PM PDT 24
Peak memory 209352 kb
Host smart-92887f42-cb51-4c29-9566-b267830149f8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225981266 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_csr_rw.3225981266
Directory /workspace/13.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.1926536496
Short name T967
Test name
Test status
Simulation time 86341725 ps
CPU time 1.92 seconds
Started Jun 11 12:54:27 PM PDT 24
Finished Jun 11 12:54:30 PM PDT 24
Peak memory 211788 kb
Host smart-eb08d8eb-e440-4091-9af6-791008019d7b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926536496 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctr
l_same_csr_outstanding.1926536496
Directory /workspace/13.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.589652038
Short name T113
Test name
Test status
Simulation time 123507743 ps
CPU time 2.01 seconds
Started Jun 11 12:54:26 PM PDT 24
Finished Jun 11 12:54:29 PM PDT 24
Peak memory 218248 kb
Host smart-45b28031-f593-406a-b496-5dc1a727e704
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589652038 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_errors.589652038
Directory /workspace/13.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.705226771
Short name T129
Test name
Test status
Simulation time 623901663 ps
CPU time 5.17 seconds
Started Jun 11 12:54:24 PM PDT 24
Finished Jun 11 12:54:31 PM PDT 24
Peak memory 218056 kb
Host smart-a17821bb-3dcd-448f-bb50-d852a3a56701
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705226771 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_intg_
err.705226771
Directory /workspace/13.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.350223065
Short name T872
Test name
Test status
Simulation time 29703155 ps
CPU time 1.64 seconds
Started Jun 11 12:54:23 PM PDT 24
Finished Jun 11 12:54:26 PM PDT 24
Peak memory 219028 kb
Host smart-0ee93007-2272-4be7-a380-d8b25a19b744
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350223065 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 14.lc_ctrl_csr_mem_rw_with_rand_reset.350223065
Directory /workspace/14.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.1696407327
Short name T959
Test name
Test status
Simulation time 15720715 ps
CPU time 1.08 seconds
Started Jun 11 12:54:21 PM PDT 24
Finished Jun 11 12:54:24 PM PDT 24
Peak memory 209792 kb
Host smart-ad33b21c-1ca6-4631-9149-2800a76974a7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696407327 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_csr_rw.1696407327
Directory /workspace/14.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.3014509690
Short name T987
Test name
Test status
Simulation time 127240090 ps
CPU time 0.94 seconds
Started Jun 11 12:54:22 PM PDT 24
Finished Jun 11 12:54:25 PM PDT 24
Peak memory 217808 kb
Host smart-f00f87ad-99dd-4904-b532-fb5f72775f7d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014509690 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctr
l_same_csr_outstanding.3014509690
Directory /workspace/14.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.4261432920
Short name T109
Test name
Test status
Simulation time 162437547 ps
CPU time 3.04 seconds
Started Jun 11 12:54:23 PM PDT 24
Finished Jun 11 12:54:28 PM PDT 24
Peak memory 218084 kb
Host smart-6db18434-4156-45c5-a478-c6070903109a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261432920 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_errors.4261432920
Directory /workspace/14.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.3146391759
Short name T132
Test name
Test status
Simulation time 113684962 ps
CPU time 2.06 seconds
Started Jun 11 12:54:24 PM PDT 24
Finished Jun 11 12:54:27 PM PDT 24
Peak memory 222400 kb
Host smart-4479862e-508b-4574-8c7b-ee5350058823
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146391759 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_intg
_err.3146391759
Directory /workspace/14.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.2313919110
Short name T887
Test name
Test status
Simulation time 210261220 ps
CPU time 1.13 seconds
Started Jun 11 12:54:23 PM PDT 24
Finished Jun 11 12:54:25 PM PDT 24
Peak memory 220180 kb
Host smart-e93c456b-add2-493d-adce-fbf64c837676
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313919110 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 15.lc_ctrl_csr_mem_rw_with_rand_reset.2313919110
Directory /workspace/15.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.2124590563
Short name T188
Test name
Test status
Simulation time 55611749 ps
CPU time 0.9 seconds
Started Jun 11 12:54:29 PM PDT 24
Finished Jun 11 12:54:30 PM PDT 24
Peak memory 209632 kb
Host smart-34c97f6e-354f-4e74-b3ff-6441f2ba2aa4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124590563 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_csr_rw.2124590563
Directory /workspace/15.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.4072155630
Short name T917
Test name
Test status
Simulation time 28738287 ps
CPU time 1.01 seconds
Started Jun 11 12:54:23 PM PDT 24
Finished Jun 11 12:54:25 PM PDT 24
Peak memory 210172 kb
Host smart-4a782519-3f4c-4b6f-9b13-13368cf4d385
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072155630 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctr
l_same_csr_outstanding.4072155630
Directory /workspace/15.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.1122384801
Short name T974
Test name
Test status
Simulation time 602584807 ps
CPU time 2.76 seconds
Started Jun 11 12:54:23 PM PDT 24
Finished Jun 11 12:54:27 PM PDT 24
Peak memory 218084 kb
Host smart-59a699f3-38d6-4cc1-8169-680f41431d06
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122384801 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_errors.1122384801
Directory /workspace/15.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.1814678459
Short name T968
Test name
Test status
Simulation time 61669820 ps
CPU time 1.5 seconds
Started Jun 11 12:54:21 PM PDT 24
Finished Jun 11 12:54:24 PM PDT 24
Peak memory 218112 kb
Host smart-0f6d6930-e78d-4f65-9bef-8fc06aaaa635
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814678459 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 16.lc_ctrl_csr_mem_rw_with_rand_reset.1814678459
Directory /workspace/16.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.3818102235
Short name T870
Test name
Test status
Simulation time 24500705 ps
CPU time 0.96 seconds
Started Jun 11 12:54:21 PM PDT 24
Finished Jun 11 12:54:23 PM PDT 24
Peak memory 209512 kb
Host smart-8dc50aa8-d5c9-4364-9eb1-1534d2513040
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818102235 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_csr_rw.3818102235
Directory /workspace/16.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.97006714
Short name T947
Test name
Test status
Simulation time 30603879 ps
CPU time 1.09 seconds
Started Jun 11 12:54:27 PM PDT 24
Finished Jun 11 12:54:29 PM PDT 24
Peak memory 209880 kb
Host smart-e8ed688b-a2c7-4cf7-adc6-d16ca5d13e2d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97006714 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_
same_csr_outstanding.97006714
Directory /workspace/16.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.3353536804
Short name T970
Test name
Test status
Simulation time 61371518 ps
CPU time 2.04 seconds
Started Jun 11 12:54:25 PM PDT 24
Finished Jun 11 12:54:28 PM PDT 24
Peak memory 218480 kb
Host smart-b0bab8e1-d549-48cd-ba4b-544e7adb5a75
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353536804 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_errors.3353536804
Directory /workspace/16.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.3947817239
Short name T102
Test name
Test status
Simulation time 286858807 ps
CPU time 3.33 seconds
Started Jun 11 12:54:29 PM PDT 24
Finished Jun 11 12:54:33 PM PDT 24
Peak memory 222780 kb
Host smart-afb09f42-02c4-4df3-8d65-67e50c0b1b96
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947817239 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_intg
_err.3947817239
Directory /workspace/16.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.807022701
Short name T894
Test name
Test status
Simulation time 29267504 ps
CPU time 1.05 seconds
Started Jun 11 12:54:24 PM PDT 24
Finished Jun 11 12:54:27 PM PDT 24
Peak memory 218128 kb
Host smart-a514e08b-888a-47c5-a2b5-8d73b8937f97
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807022701 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 17.lc_ctrl_csr_mem_rw_with_rand_reset.807022701
Directory /workspace/17.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.3179779536
Short name T984
Test name
Test status
Simulation time 12308719 ps
CPU time 0.9 seconds
Started Jun 11 12:54:29 PM PDT 24
Finished Jun 11 12:54:30 PM PDT 24
Peak memory 209292 kb
Host smart-ead85e38-5f2d-44f1-9bb1-4cfa37a79fb7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179779536 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_csr_rw.3179779536
Directory /workspace/17.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.1472416664
Short name T195
Test name
Test status
Simulation time 20070202 ps
CPU time 1.15 seconds
Started Jun 11 12:54:22 PM PDT 24
Finished Jun 11 12:54:24 PM PDT 24
Peak memory 210036 kb
Host smart-113a2496-9ebe-472e-b2f3-9982a67a3532
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472416664 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctr
l_same_csr_outstanding.1472416664
Directory /workspace/17.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.2049504727
Short name T121
Test name
Test status
Simulation time 84002687 ps
CPU time 1.51 seconds
Started Jun 11 12:54:22 PM PDT 24
Finished Jun 11 12:54:25 PM PDT 24
Peak memory 218240 kb
Host smart-df53285b-7734-46b6-8201-a0e688a5e78a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049504727 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_errors.2049504727
Directory /workspace/17.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.2304186493
Short name T122
Test name
Test status
Simulation time 786702678 ps
CPU time 3 seconds
Started Jun 11 12:54:22 PM PDT 24
Finished Jun 11 12:54:27 PM PDT 24
Peak memory 222684 kb
Host smart-300065a9-b69d-4800-b736-1c2fc201f48f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304186493 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_intg
_err.2304186493
Directory /workspace/17.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.733429579
Short name T962
Test name
Test status
Simulation time 25317604 ps
CPU time 1.64 seconds
Started Jun 11 12:54:29 PM PDT 24
Finished Jun 11 12:54:33 PM PDT 24
Peak memory 218196 kb
Host smart-e0c03463-f9cf-4df3-b76a-a6ab109fac2f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733429579 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 18.lc_ctrl_csr_mem_rw_with_rand_reset.733429579
Directory /workspace/18.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.1243475571
Short name T189
Test name
Test status
Simulation time 17767169 ps
CPU time 0.98 seconds
Started Jun 11 12:54:24 PM PDT 24
Finished Jun 11 12:54:27 PM PDT 24
Peak memory 209584 kb
Host smart-c359fd2c-dac5-4ef7-8ddd-462f53896c95
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243475571 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_csr_rw.1243475571
Directory /workspace/18.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.3657217719
Short name T944
Test name
Test status
Simulation time 31226277 ps
CPU time 1.55 seconds
Started Jun 11 12:54:27 PM PDT 24
Finished Jun 11 12:54:29 PM PDT 24
Peak memory 217804 kb
Host smart-fe7e1bc5-ce5b-4f70-aedf-0f7c2e42b938
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657217719 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctr
l_same_csr_outstanding.3657217719
Directory /workspace/18.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.4055241315
Short name T114
Test name
Test status
Simulation time 89799153 ps
CPU time 3.56 seconds
Started Jun 11 12:54:22 PM PDT 24
Finished Jun 11 12:54:27 PM PDT 24
Peak memory 218116 kb
Host smart-ba32a06c-1ba4-426f-afcb-c93fdf71dc0a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055241315 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_errors.4055241315
Directory /workspace/18.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.787968765
Short name T104
Test name
Test status
Simulation time 329629046 ps
CPU time 1.88 seconds
Started Jun 11 12:54:22 PM PDT 24
Finished Jun 11 12:54:26 PM PDT 24
Peak memory 222336 kb
Host smart-d78c8024-074b-43c8-9283-09bf73b49b25
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787968765 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_intg_
err.787968765
Directory /workspace/18.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.2554632760
Short name T938
Test name
Test status
Simulation time 23293231 ps
CPU time 1.38 seconds
Started Jun 11 12:54:33 PM PDT 24
Finished Jun 11 12:54:36 PM PDT 24
Peak memory 218168 kb
Host smart-a20753c9-ebd6-40b2-b0df-aa94d565d61c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554632760 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 19.lc_ctrl_csr_mem_rw_with_rand_reset.2554632760
Directory /workspace/19.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.3146251936
Short name T187
Test name
Test status
Simulation time 24670112 ps
CPU time 1.04 seconds
Started Jun 11 12:54:34 PM PDT 24
Finished Jun 11 12:54:36 PM PDT 24
Peak memory 209852 kb
Host smart-bb1aff8c-62a6-4932-ae45-4d02cfe2f5d8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146251936 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_csr_rw.3146251936
Directory /workspace/19.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.3552360577
Short name T901
Test name
Test status
Simulation time 86134132 ps
CPU time 1.5 seconds
Started Jun 11 12:54:37 PM PDT 24
Finished Jun 11 12:54:39 PM PDT 24
Peak memory 212044 kb
Host smart-2f070c3b-3efa-4bd2-937d-37f65b3419ad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552360577 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctr
l_same_csr_outstanding.3552360577
Directory /workspace/19.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.2428384559
Short name T911
Test name
Test status
Simulation time 71052401 ps
CPU time 2.81 seconds
Started Jun 11 12:54:21 PM PDT 24
Finished Jun 11 12:54:25 PM PDT 24
Peak memory 218112 kb
Host smart-4d4d4123-2b0b-4914-8fd2-482c26f00ea0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428384559 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_errors.2428384559
Directory /workspace/19.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.3336300362
Short name T893
Test name
Test status
Simulation time 81868143 ps
CPU time 1.1 seconds
Started Jun 11 12:53:47 PM PDT 24
Finished Jun 11 12:53:49 PM PDT 24
Peak memory 217548 kb
Host smart-81799160-0212-489d-93b0-71abc3b00667
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336300362 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_aliasin
g.3336300362
Directory /workspace/2.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.796685360
Short name T929
Test name
Test status
Simulation time 40394879 ps
CPU time 1.87 seconds
Started Jun 11 12:53:48 PM PDT 24
Finished Jun 11 12:53:51 PM PDT 24
Peak memory 209444 kb
Host smart-09a7047b-34dd-4866-b336-f32c22e3137a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796685360 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_bit_bash
.796685360
Directory /workspace/2.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.1589145128
Short name T993
Test name
Test status
Simulation time 58416024 ps
CPU time 1.15 seconds
Started Jun 11 12:53:48 PM PDT 24
Finished Jun 11 12:53:50 PM PDT 24
Peak memory 211888 kb
Host smart-9c0df202-b83f-4d2b-b171-2eacd10d8550
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589145128 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_hw_rese
t.1589145128
Directory /workspace/2.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.1955893904
Short name T939
Test name
Test status
Simulation time 40807226 ps
CPU time 1.38 seconds
Started Jun 11 12:53:48 PM PDT 24
Finished Jun 11 12:53:50 PM PDT 24
Peak memory 219668 kb
Host smart-cbb9c4e0-d4da-4548-b7e3-554ca5dc4cec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955893904 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 2.lc_ctrl_csr_mem_rw_with_rand_reset.1955893904
Directory /workspace/2.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.2861137426
Short name T185
Test name
Test status
Simulation time 51380365 ps
CPU time 0.8 seconds
Started Jun 11 12:53:50 PM PDT 24
Finished Jun 11 12:53:52 PM PDT 24
Peak memory 209912 kb
Host smart-3cf0f460-f631-48ba-a182-de9124cfbe93
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861137426 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_rw.2861137426
Directory /workspace/2.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.4177052630
Short name T930
Test name
Test status
Simulation time 664928335 ps
CPU time 1.7 seconds
Started Jun 11 12:53:37 PM PDT 24
Finished Jun 11 12:53:39 PM PDT 24
Peak memory 209012 kb
Host smart-8ee5c56b-281f-4711-8b74-a0de469ae78c
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177052630 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.lc_ctrl_jtag_alert_test.4177052630
Directory /workspace/2.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.2618802726
Short name T881
Test name
Test status
Simulation time 3906202883 ps
CPU time 6.45 seconds
Started Jun 11 12:53:34 PM PDT 24
Finished Jun 11 12:53:42 PM PDT 24
Peak memory 209896 kb
Host smart-5877f747-6b08-4bce-a9e9-c084582b72d7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618802726 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_aliasing.2618802726
Directory /workspace/2.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.1151538073
Short name T940
Test name
Test status
Simulation time 1244112842 ps
CPU time 27.26 seconds
Started Jun 11 12:53:33 PM PDT 24
Finished Jun 11 12:54:01 PM PDT 24
Peak memory 209740 kb
Host smart-bc293612-4310-4cbf-8059-3e5760a7a6c1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151538073 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_bit_bash.1151538073
Directory /workspace/2.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.2958218320
Short name T879
Test name
Test status
Simulation time 112751376 ps
CPU time 3.23 seconds
Started Jun 11 12:53:32 PM PDT 24
Finished Jun 11 12:53:36 PM PDT 24
Peak memory 217996 kb
Host smart-43d9850f-df74-4d80-a73f-3f9c8f2b06b4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958218320 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_hw_reset.2958218320
Directory /workspace/2.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.748518027
Short name T134
Test name
Test status
Simulation time 433111700 ps
CPU time 1.93 seconds
Started Jun 11 12:53:33 PM PDT 24
Finished Jun 11 12:53:36 PM PDT 24
Peak memory 218304 kb
Host smart-8f87c67e-d03c-411c-848f-83f93d00962d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748518
027 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.748518027
Directory /workspace/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.1128689829
Short name T994
Test name
Test status
Simulation time 124394823 ps
CPU time 1.48 seconds
Started Jun 11 12:53:34 PM PDT 24
Finished Jun 11 12:53:37 PM PDT 24
Peak memory 209708 kb
Host smart-b6e477b5-2b98-4e32-88fc-893303b86b34
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128689829 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.lc_ctrl_jtag_csr_rw.1128689829
Directory /workspace/2.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.1326912358
Short name T988
Test name
Test status
Simulation time 24793555 ps
CPU time 1.13 seconds
Started Jun 11 12:53:34 PM PDT 24
Finished Jun 11 12:53:36 PM PDT 24
Peak memory 209692 kb
Host smart-3de3b30f-b05a-4f82-b85c-358b7e10470a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326912358 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.lc_ctrl_jtag_same_csr_outstanding.1326912358
Directory /workspace/2.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.3421275314
Short name T196
Test name
Test status
Simulation time 26865844 ps
CPU time 1.15 seconds
Started Jun 11 12:53:47 PM PDT 24
Finished Jun 11 12:53:48 PM PDT 24
Peak memory 217920 kb
Host smart-a9e3d216-58c4-4e47-addc-f900c36c81fc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421275314 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl
_same_csr_outstanding.3421275314
Directory /workspace/2.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.3694022507
Short name T922
Test name
Test status
Simulation time 18724462 ps
CPU time 1.76 seconds
Started Jun 11 12:53:33 PM PDT 24
Finished Jun 11 12:53:36 PM PDT 24
Peak memory 218116 kb
Host smart-fa17efad-3317-43e5-8ec6-4e33295f61b4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694022507 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_errors.3694022507
Directory /workspace/2.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.1468336732
Short name T948
Test name
Test status
Simulation time 87908913 ps
CPU time 1.32 seconds
Started Jun 11 12:53:48 PM PDT 24
Finished Jun 11 12:53:50 PM PDT 24
Peak memory 209860 kb
Host smart-c4c15911-22c7-4304-ace2-5c9dcd176a76
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468336732 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_aliasin
g.1468336732
Directory /workspace/3.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.3509291322
Short name T910
Test name
Test status
Simulation time 93150889 ps
CPU time 1.74 seconds
Started Jun 11 12:53:49 PM PDT 24
Finished Jun 11 12:53:52 PM PDT 24
Peak memory 209920 kb
Host smart-86372225-bb3a-4ad3-b224-308b4bed5f18
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509291322 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_bit_bas
h.3509291322
Directory /workspace/3.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.560520845
Short name T946
Test name
Test status
Simulation time 51510856 ps
CPU time 1.08 seconds
Started Jun 11 12:53:49 PM PDT 24
Finished Jun 11 12:53:52 PM PDT 24
Peak memory 210504 kb
Host smart-138fc9ee-84f0-400c-a966-351dc6b46d5a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560520845 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_hw_reset
.560520845
Directory /workspace/3.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.3202136462
Short name T924
Test name
Test status
Simulation time 18177283 ps
CPU time 1.23 seconds
Started Jun 11 12:53:55 PM PDT 24
Finished Jun 11 12:53:57 PM PDT 24
Peak memory 220296 kb
Host smart-b3d9a51f-b3f2-4937-9f95-604122d0fbaf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202136462 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 3.lc_ctrl_csr_mem_rw_with_rand_reset.3202136462
Directory /workspace/3.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.2012439284
Short name T900
Test name
Test status
Simulation time 21085013 ps
CPU time 0.83 seconds
Started Jun 11 12:53:47 PM PDT 24
Finished Jun 11 12:53:49 PM PDT 24
Peak memory 209732 kb
Host smart-14fa5303-4d40-4ff6-aead-b32502288aa6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012439284 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_rw.2012439284
Directory /workspace/3.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.3714431118
Short name T971
Test name
Test status
Simulation time 27516059 ps
CPU time 0.97 seconds
Started Jun 11 12:53:50 PM PDT 24
Finished Jun 11 12:53:52 PM PDT 24
Peak memory 209016 kb
Host smart-dd19fbe1-3f29-463a-9d98-0dce055860c7
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714431118 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.lc_ctrl_jtag_alert_test.3714431118
Directory /workspace/3.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.3350402989
Short name T989
Test name
Test status
Simulation time 10132107286 ps
CPU time 9.87 seconds
Started Jun 11 12:53:49 PM PDT 24
Finished Jun 11 12:54:00 PM PDT 24
Peak memory 209752 kb
Host smart-8ccd2d09-ca28-4489-b6b7-15f076542b15
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350402989 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_aliasing.3350402989
Directory /workspace/3.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.1700904228
Short name T888
Test name
Test status
Simulation time 1384780741 ps
CPU time 4.47 seconds
Started Jun 11 12:53:56 PM PDT 24
Finished Jun 11 12:54:01 PM PDT 24
Peak memory 217312 kb
Host smart-d1a2c6ec-d715-4cc7-bd02-bba02570389c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700904228 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_bit_bash.1700904228
Directory /workspace/3.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.352465975
Short name T957
Test name
Test status
Simulation time 383442228 ps
CPU time 1.54 seconds
Started Jun 11 12:53:47 PM PDT 24
Finished Jun 11 12:53:49 PM PDT 24
Peak memory 211208 kb
Host smart-d2bbb0fc-27da-4740-8ae1-a5b6757b409d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352465975 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 3.lc_ctrl_jtag_csr_hw_reset.352465975
Directory /workspace/3.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4101070223
Short name T991
Test name
Test status
Simulation time 103241872 ps
CPU time 2.53 seconds
Started Jun 11 12:53:50 PM PDT 24
Finished Jun 11 12:53:53 PM PDT 24
Peak memory 221816 kb
Host smart-212acaba-daae-4dce-a491-9768858e0a40
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410107
0223 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4101070223
Directory /workspace/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.3751592736
Short name T979
Test name
Test status
Simulation time 345441691 ps
CPU time 2.67 seconds
Started Jun 11 12:53:50 PM PDT 24
Finished Jun 11 12:53:54 PM PDT 24
Peak memory 217296 kb
Host smart-4515d37f-d204-43cf-b57d-a6f7f1b99024
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751592736 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.lc_ctrl_jtag_csr_rw.3751592736
Directory /workspace/3.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.2994576295
Short name T927
Test name
Test status
Simulation time 145917676 ps
CPU time 1.02 seconds
Started Jun 11 12:53:49 PM PDT 24
Finished Jun 11 12:53:51 PM PDT 24
Peak memory 209908 kb
Host smart-64429ec9-7d2b-4044-8e88-cbf286ac6cd2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994576295 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.lc_ctrl_jtag_same_csr_outstanding.2994576295
Directory /workspace/3.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.2599891340
Short name T194
Test name
Test status
Simulation time 199485088 ps
CPU time 1.17 seconds
Started Jun 11 12:53:47 PM PDT 24
Finished Jun 11 12:53:49 PM PDT 24
Peak memory 217912 kb
Host smart-59a243a4-32b2-44af-b625-0d0b1c1315ff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599891340 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl
_same_csr_outstanding.2599891340
Directory /workspace/3.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.585121046
Short name T919
Test name
Test status
Simulation time 54728383 ps
CPU time 1.9 seconds
Started Jun 11 12:53:48 PM PDT 24
Finished Jun 11 12:53:50 PM PDT 24
Peak memory 218376 kb
Host smart-d240ca49-6c86-41d6-b990-01ca82e71650
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585121046 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_errors.585121046
Directory /workspace/3.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.2049535724
Short name T885
Test name
Test status
Simulation time 226860424 ps
CPU time 1.31 seconds
Started Jun 11 12:53:49 PM PDT 24
Finished Jun 11 12:53:52 PM PDT 24
Peak memory 217820 kb
Host smart-e7ef2479-25aa-48f9-b651-f76740aa9142
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049535724 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_aliasin
g.2049535724
Directory /workspace/4.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.879195518
Short name T149
Test name
Test status
Simulation time 105336164 ps
CPU time 1.4 seconds
Started Jun 11 12:53:56 PM PDT 24
Finished Jun 11 12:53:58 PM PDT 24
Peak memory 209884 kb
Host smart-e61556bc-3dcd-4906-936c-3177fe078738
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879195518 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_bit_bash
.879195518
Directory /workspace/4.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.1383969801
Short name T880
Test name
Test status
Simulation time 18269044 ps
CPU time 1.02 seconds
Started Jun 11 12:53:48 PM PDT 24
Finished Jun 11 12:53:50 PM PDT 24
Peak memory 211928 kb
Host smart-135ece57-7267-4029-99f3-6bac71fe460d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383969801 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_hw_rese
t.1383969801
Directory /workspace/4.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.3001903706
Short name T133
Test name
Test status
Simulation time 21026904 ps
CPU time 1.47 seconds
Started Jun 11 12:54:01 PM PDT 24
Finished Jun 11 12:54:04 PM PDT 24
Peak memory 219832 kb
Host smart-d9b4a6b1-dc64-4ee1-bf85-2661db5c9f13
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001903706 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 4.lc_ctrl_csr_mem_rw_with_rand_reset.3001903706
Directory /workspace/4.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.3705732026
Short name T184
Test name
Test status
Simulation time 25154963 ps
CPU time 0.9 seconds
Started Jun 11 12:53:49 PM PDT 24
Finished Jun 11 12:53:51 PM PDT 24
Peak memory 209396 kb
Host smart-05f247be-c21f-4a33-91e2-97c5913ad97d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705732026 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_rw.3705732026
Directory /workspace/4.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.1250386733
Short name T895
Test name
Test status
Simulation time 79874656 ps
CPU time 1.08 seconds
Started Jun 11 12:53:56 PM PDT 24
Finished Jun 11 12:53:58 PM PDT 24
Peak memory 209776 kb
Host smart-f9b45e9b-eb70-4f51-9423-4bd0cf457a11
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250386733 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.lc_ctrl_jtag_alert_test.1250386733
Directory /workspace/4.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.2511400077
Short name T869
Test name
Test status
Simulation time 4581116812 ps
CPU time 24.28 seconds
Started Jun 11 12:53:50 PM PDT 24
Finished Jun 11 12:54:16 PM PDT 24
Peak memory 218108 kb
Host smart-0b774008-a84a-4ac5-98f6-6becd6eb8873
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511400077 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_aliasing.2511400077
Directory /workspace/4.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.4023888583
Short name T926
Test name
Test status
Simulation time 1516081627 ps
CPU time 13.45 seconds
Started Jun 11 12:53:56 PM PDT 24
Finished Jun 11 12:54:10 PM PDT 24
Peak memory 209800 kb
Host smart-8bf1941a-2c0b-40a5-b358-89c7ce0a9620
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023888583 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_bit_bash.4023888583
Directory /workspace/4.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.1434838846
Short name T116
Test name
Test status
Simulation time 351461566 ps
CPU time 1.8 seconds
Started Jun 11 12:53:49 PM PDT 24
Finished Jun 11 12:53:52 PM PDT 24
Peak memory 211152 kb
Host smart-ca5bab97-dab2-4baa-9d3d-c48dcb523d2d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434838846 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_hw_reset.1434838846
Directory /workspace/4.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.778705361
Short name T937
Test name
Test status
Simulation time 1032112762 ps
CPU time 5.13 seconds
Started Jun 11 12:53:49 PM PDT 24
Finished Jun 11 12:53:55 PM PDT 24
Peak memory 219644 kb
Host smart-349a99eb-eea9-4833-b903-bf46fb6b02bc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778705
361 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.778705361
Directory /workspace/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.1716590578
Short name T932
Test name
Test status
Simulation time 176594302 ps
CPU time 2.05 seconds
Started Jun 11 12:53:49 PM PDT 24
Finished Jun 11 12:53:53 PM PDT 24
Peak memory 209788 kb
Host smart-dadeb812-b8df-4234-bcb9-d0f215d8d5ea
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716590578 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.lc_ctrl_jtag_csr_rw.1716590578
Directory /workspace/4.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.1045090232
Short name T950
Test name
Test status
Simulation time 46026454 ps
CPU time 1.41 seconds
Started Jun 11 12:53:55 PM PDT 24
Finished Jun 11 12:53:58 PM PDT 24
Peak memory 211836 kb
Host smart-3c951095-7603-4bee-9e78-4c42ccb330ad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045090232 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.lc_ctrl_jtag_same_csr_outstanding.1045090232
Directory /workspace/4.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.424448331
Short name T956
Test name
Test status
Simulation time 24552772 ps
CPU time 1.03 seconds
Started Jun 11 12:54:00 PM PDT 24
Finished Jun 11 12:54:03 PM PDT 24
Peak memory 218092 kb
Host smart-35e0a96d-c40e-4182-bb66-df86cfbe978e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424448331 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
same_csr_outstanding.424448331
Directory /workspace/4.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.2381224335
Short name T966
Test name
Test status
Simulation time 91245217 ps
CPU time 2.77 seconds
Started Jun 11 12:53:47 PM PDT 24
Finished Jun 11 12:53:51 PM PDT 24
Peak memory 218084 kb
Host smart-9076d660-8ede-475c-ad93-30d5cc1b158b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381224335 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_errors.2381224335
Directory /workspace/4.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.806798838
Short name T123
Test name
Test status
Simulation time 107974960 ps
CPU time 2.47 seconds
Started Jun 11 12:53:47 PM PDT 24
Finished Jun 11 12:53:50 PM PDT 24
Peak memory 218164 kb
Host smart-5ddf1b99-db8d-463c-865e-86468f86a929
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806798838 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_intg_e
rr.806798838
Directory /workspace/4.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.279130472
Short name T147
Test name
Test status
Simulation time 40213941 ps
CPU time 1.33 seconds
Started Jun 11 12:53:59 PM PDT 24
Finished Jun 11 12:54:02 PM PDT 24
Peak memory 218200 kb
Host smart-cf9b760b-2ce2-4e0b-888a-00340709e7bf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279130472 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 5.lc_ctrl_csr_mem_rw_with_rand_reset.279130472
Directory /workspace/5.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.601723278
Short name T115
Test name
Test status
Simulation time 22366432 ps
CPU time 1.01 seconds
Started Jun 11 12:54:01 PM PDT 24
Finished Jun 11 12:54:03 PM PDT 24
Peak memory 209872 kb
Host smart-a3b813ab-20f5-4d64-8236-ee122e320e65
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601723278 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_csr_rw.601723278
Directory /workspace/5.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.3121516627
Short name T960
Test name
Test status
Simulation time 311881655 ps
CPU time 2.91 seconds
Started Jun 11 12:53:59 PM PDT 24
Finished Jun 11 12:54:03 PM PDT 24
Peak memory 209784 kb
Host smart-9bc47a92-a70e-44bc-b8b1-b6b3c846e5b9
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121516627 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.lc_ctrl_jtag_alert_test.3121516627
Directory /workspace/5.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.3681994415
Short name T902
Test name
Test status
Simulation time 492255381 ps
CPU time 3.84 seconds
Started Jun 11 12:53:59 PM PDT 24
Finished Jun 11 12:54:03 PM PDT 24
Peak memory 209448 kb
Host smart-9114399f-4715-452f-abbf-bbecf6ad6afd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681994415 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_aliasing.3681994415
Directory /workspace/5.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.2295319651
Short name T871
Test name
Test status
Simulation time 836749862 ps
CPU time 19.54 seconds
Started Jun 11 12:53:57 PM PDT 24
Finished Jun 11 12:54:17 PM PDT 24
Peak memory 209772 kb
Host smart-ddcb6b08-b593-46e4-8c27-205c5b2f042d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295319651 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_bit_bash.2295319651
Directory /workspace/5.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.30155955
Short name T976
Test name
Test status
Simulation time 775200015 ps
CPU time 4.76 seconds
Started Jun 11 12:53:58 PM PDT 24
Finished Jun 11 12:54:04 PM PDT 24
Peak memory 217924 kb
Host smart-8ef0d501-bc15-4e1f-9cc2-df014da0844d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30155955 -assert nopostproc +UVM_TESTNAME=lc_ctrl_bas
e_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 5.lc_ctrl_jtag_csr_hw_reset.30155955
Directory /workspace/5.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1261741408
Short name T943
Test name
Test status
Simulation time 207379806 ps
CPU time 2.55 seconds
Started Jun 11 12:54:01 PM PDT 24
Finished Jun 11 12:54:04 PM PDT 24
Peak memory 219092 kb
Host smart-263a7f69-3f28-4a6d-bb87-2dbd4eef23f7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126174
1408 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1261741408
Directory /workspace/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.539416327
Short name T921
Test name
Test status
Simulation time 605533209 ps
CPU time 4.2 seconds
Started Jun 11 12:54:00 PM PDT 24
Finished Jun 11 12:54:05 PM PDT 24
Peak memory 209992 kb
Host smart-c1de98fd-56e7-4453-ab8c-940e7b478cdc
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539416327 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.lc_ctrl_jtag_csr_rw.539416327
Directory /workspace/5.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.1346784167
Short name T916
Test name
Test status
Simulation time 69358593 ps
CPU time 1.43 seconds
Started Jun 11 12:53:59 PM PDT 24
Finished Jun 11 12:54:01 PM PDT 24
Peak memory 211824 kb
Host smart-230b5acd-147a-415b-adb9-d29b536f52c3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346784167 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.lc_ctrl_jtag_same_csr_outstanding.1346784167
Directory /workspace/5.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.2966250210
Short name T925
Test name
Test status
Simulation time 17090837 ps
CPU time 1.22 seconds
Started Jun 11 12:54:01 PM PDT 24
Finished Jun 11 12:54:03 PM PDT 24
Peak memory 209184 kb
Host smart-b32f591f-dd36-4329-b91a-f905516d4130
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966250210 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl
_same_csr_outstanding.2966250210
Directory /workspace/5.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.127034692
Short name T110
Test name
Test status
Simulation time 298645299 ps
CPU time 5.45 seconds
Started Jun 11 12:53:58 PM PDT 24
Finished Jun 11 12:54:04 PM PDT 24
Peak memory 218088 kb
Host smart-f376e923-728d-42c3-b6bd-c789f14c2cfb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127034692 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_errors.127034692
Directory /workspace/5.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.1542811157
Short name T112
Test name
Test status
Simulation time 408722237 ps
CPU time 4.29 seconds
Started Jun 11 12:53:59 PM PDT 24
Finished Jun 11 12:54:05 PM PDT 24
Peak memory 218096 kb
Host smart-8894893c-1b9c-4935-a15c-f12ec727c8e0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542811157 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_intg_
err.1542811157
Directory /workspace/5.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.2273755157
Short name T995
Test name
Test status
Simulation time 22524660 ps
CPU time 1.1 seconds
Started Jun 11 12:54:10 PM PDT 24
Finished Jun 11 12:54:12 PM PDT 24
Peak memory 219132 kb
Host smart-02f38ce6-6c70-4cd0-907c-64042ba54407
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273755157 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 6.lc_ctrl_csr_mem_rw_with_rand_reset.2273755157
Directory /workspace/6.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.1826107575
Short name T193
Test name
Test status
Simulation time 14506788 ps
CPU time 0.94 seconds
Started Jun 11 12:54:00 PM PDT 24
Finished Jun 11 12:54:02 PM PDT 24
Peak memory 209460 kb
Host smart-e4fc28aa-f09d-4c03-9f38-1a18dbcb74bd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826107575 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_csr_rw.1826107575
Directory /workspace/6.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.2150761329
Short name T923
Test name
Test status
Simulation time 433655007 ps
CPU time 2.23 seconds
Started Jun 11 12:54:00 PM PDT 24
Finished Jun 11 12:54:03 PM PDT 24
Peak memory 209752 kb
Host smart-e767b0e1-74a8-444c-b334-43dab11c1c14
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150761329 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.lc_ctrl_jtag_alert_test.2150761329
Directory /workspace/6.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.1226749671
Short name T920
Test name
Test status
Simulation time 368498017 ps
CPU time 9.86 seconds
Started Jun 11 12:54:03 PM PDT 24
Finished Jun 11 12:54:13 PM PDT 24
Peak memory 209756 kb
Host smart-a76a1999-2702-4ba3-a3c0-9dde4856e304
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226749671 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_aliasing.1226749671
Directory /workspace/6.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.3342090490
Short name T931
Test name
Test status
Simulation time 1656531259 ps
CPU time 10.42 seconds
Started Jun 11 12:54:00 PM PDT 24
Finished Jun 11 12:54:11 PM PDT 24
Peak memory 217212 kb
Host smart-d1ac43ba-f7d4-4d90-af99-9b71fc332372
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342090490 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_bit_bash.3342090490
Directory /workspace/6.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.2798911920
Short name T903
Test name
Test status
Simulation time 203695818 ps
CPU time 2.06 seconds
Started Jun 11 12:54:01 PM PDT 24
Finished Jun 11 12:54:04 PM PDT 24
Peak memory 208896 kb
Host smart-b5966be4-1d2b-4192-87fc-20c8bbc46f7c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798911920 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_hw_reset.2798911920
Directory /workspace/6.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3474597933
Short name T135
Test name
Test status
Simulation time 383552789 ps
CPU time 1.91 seconds
Started Jun 11 12:54:00 PM PDT 24
Finished Jun 11 12:54:03 PM PDT 24
Peak memory 218380 kb
Host smart-36df503f-199f-4446-b532-eaa27a8b3f36
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347459
7933 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3474597933
Directory /workspace/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.2620283788
Short name T882
Test name
Test status
Simulation time 62047471 ps
CPU time 1.58 seconds
Started Jun 11 12:53:59 PM PDT 24
Finished Jun 11 12:54:02 PM PDT 24
Peak memory 209800 kb
Host smart-dc141f62-25fc-4f7f-a1af-a04222c98b7a
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620283788 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.lc_ctrl_jtag_csr_rw.2620283788
Directory /workspace/6.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.1371089376
Short name T906
Test name
Test status
Simulation time 56664499 ps
CPU time 1.1 seconds
Started Jun 11 12:53:59 PM PDT 24
Finished Jun 11 12:54:02 PM PDT 24
Peak memory 209904 kb
Host smart-833176d3-8086-4697-aff7-7c4dcd86d5c0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371089376 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.lc_ctrl_jtag_same_csr_outstanding.1371089376
Directory /workspace/6.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.3254345411
Short name T969
Test name
Test status
Simulation time 274685286 ps
CPU time 1.45 seconds
Started Jun 11 12:53:59 PM PDT 24
Finished Jun 11 12:54:01 PM PDT 24
Peak memory 212024 kb
Host smart-984bc83b-80f6-4b1c-ac9f-c241859a3a69
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254345411 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl
_same_csr_outstanding.3254345411
Directory /workspace/6.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.3922404978
Short name T898
Test name
Test status
Simulation time 117677940 ps
CPU time 2.42 seconds
Started Jun 11 12:54:02 PM PDT 24
Finished Jun 11 12:54:06 PM PDT 24
Peak memory 219128 kb
Host smart-1b9e531c-4605-460f-aa54-ebc00958097d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922404978 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_errors.3922404978
Directory /workspace/6.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.1993653863
Short name T896
Test name
Test status
Simulation time 21506414 ps
CPU time 1.51 seconds
Started Jun 11 12:54:11 PM PDT 24
Finished Jun 11 12:54:14 PM PDT 24
Peak memory 218152 kb
Host smart-72b5ba14-925d-44e8-a59e-c91654911d70
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993653863 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 7.lc_ctrl_csr_mem_rw_with_rand_reset.1993653863
Directory /workspace/7.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.4129636674
Short name T200
Test name
Test status
Simulation time 21903786 ps
CPU time 0.98 seconds
Started Jun 11 12:54:11 PM PDT 24
Finished Jun 11 12:54:13 PM PDT 24
Peak memory 209544 kb
Host smart-cbbd9d1c-641b-4df1-947c-531fa9d8fb23
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129636674 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_csr_rw.4129636674
Directory /workspace/7.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.4188592488
Short name T889
Test name
Test status
Simulation time 194504402 ps
CPU time 1.9 seconds
Started Jun 11 12:54:12 PM PDT 24
Finished Jun 11 12:54:15 PM PDT 24
Peak memory 209704 kb
Host smart-a92294f4-438c-4bc8-a702-1224680a41d1
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188592488 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.lc_ctrl_jtag_alert_test.4188592488
Directory /workspace/7.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.1927481030
Short name T136
Test name
Test status
Simulation time 737389573 ps
CPU time 5.43 seconds
Started Jun 11 12:54:12 PM PDT 24
Finished Jun 11 12:54:18 PM PDT 24
Peak memory 209480 kb
Host smart-d98ba157-5250-4055-9dda-9a57b11a72ac
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927481030 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_aliasing.1927481030
Directory /workspace/7.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.2386541268
Short name T892
Test name
Test status
Simulation time 491785895 ps
CPU time 5.27 seconds
Started Jun 11 12:54:13 PM PDT 24
Finished Jun 11 12:54:20 PM PDT 24
Peak memory 209380 kb
Host smart-91836801-b0d9-425e-956b-d87742219567
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386541268 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_bit_bash.2386541268
Directory /workspace/7.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.1974971395
Short name T873
Test name
Test status
Simulation time 224328166 ps
CPU time 3.27 seconds
Started Jun 11 12:54:12 PM PDT 24
Finished Jun 11 12:54:17 PM PDT 24
Peak memory 218016 kb
Host smart-abf5c8b7-9118-4610-9b23-2762a6becaa1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974971395 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_hw_reset.1974971395
Directory /workspace/7.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2332834212
Short name T977
Test name
Test status
Simulation time 213728682 ps
CPU time 1.62 seconds
Started Jun 11 12:54:10 PM PDT 24
Finished Jun 11 12:54:13 PM PDT 24
Peak memory 218208 kb
Host smart-247f899c-2d0a-49c6-b91a-1505ebb9d710
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233283
4212 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2332834212
Directory /workspace/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.1234152276
Short name T958
Test name
Test status
Simulation time 47702692 ps
CPU time 1.86 seconds
Started Jun 11 12:54:13 PM PDT 24
Finished Jun 11 12:54:17 PM PDT 24
Peak memory 217272 kb
Host smart-b72994ea-ff0e-4e7e-892b-8a530177d317
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234152276 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.lc_ctrl_jtag_csr_rw.1234152276
Directory /workspace/7.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.1816473961
Short name T913
Test name
Test status
Simulation time 224637164 ps
CPU time 1.42 seconds
Started Jun 11 12:54:10 PM PDT 24
Finished Jun 11 12:54:12 PM PDT 24
Peak memory 210048 kb
Host smart-31dbdba9-df76-47d4-896b-eeee92145a1b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816473961 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.lc_ctrl_jtag_same_csr_outstanding.1816473961
Directory /workspace/7.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.62091081
Short name T912
Test name
Test status
Simulation time 73634634 ps
CPU time 1.45 seconds
Started Jun 11 12:54:15 PM PDT 24
Finished Jun 11 12:54:18 PM PDT 24
Peak memory 217804 kb
Host smart-ee8ed46c-5993-423d-9766-cae7caa75f41
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62091081 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_s
ame_csr_outstanding.62091081
Directory /workspace/7.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.3357327380
Short name T982
Test name
Test status
Simulation time 62461687 ps
CPU time 2.91 seconds
Started Jun 11 12:54:13 PM PDT 24
Finished Jun 11 12:54:18 PM PDT 24
Peak memory 218160 kb
Host smart-88695052-675e-4d3e-a046-06d9b820d0ee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357327380 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_errors.3357327380
Directory /workspace/7.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.4265203584
Short name T907
Test name
Test status
Simulation time 18242892 ps
CPU time 1.43 seconds
Started Jun 11 12:54:12 PM PDT 24
Finished Jun 11 12:54:15 PM PDT 24
Peak memory 224892 kb
Host smart-1841c7eb-bf5f-4897-9224-fb87811e87d4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265203584 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 8.lc_ctrl_csr_mem_rw_with_rand_reset.4265203584
Directory /workspace/8.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.2099727841
Short name T990
Test name
Test status
Simulation time 20604549 ps
CPU time 0.83 seconds
Started Jun 11 12:54:11 PM PDT 24
Finished Jun 11 12:54:13 PM PDT 24
Peak memory 209692 kb
Host smart-ddde1f4c-fdd6-44f2-992d-2e8855cd0572
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099727841 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_csr_rw.2099727841
Directory /workspace/8.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.1120235969
Short name T933
Test name
Test status
Simulation time 59043195 ps
CPU time 1.64 seconds
Started Jun 11 12:54:12 PM PDT 24
Finished Jun 11 12:54:15 PM PDT 24
Peak memory 209736 kb
Host smart-528cf6bc-4b71-48bc-a1f5-7d6dcd7edec5
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120235969 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.lc_ctrl_jtag_alert_test.1120235969
Directory /workspace/8.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.738555759
Short name T883
Test name
Test status
Simulation time 601098836 ps
CPU time 4.02 seconds
Started Jun 11 12:54:12 PM PDT 24
Finished Jun 11 12:54:17 PM PDT 24
Peak memory 209404 kb
Host smart-b9e16fd2-b2c1-4bfb-a964-e2d436e44755
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738555759 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 8.lc_ctrl_jtag_csr_aliasing.738555759
Directory /workspace/8.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.3139728503
Short name T914
Test name
Test status
Simulation time 1652009671 ps
CPU time 20.41 seconds
Started Jun 11 12:54:15 PM PDT 24
Finished Jun 11 12:54:37 PM PDT 24
Peak memory 209636 kb
Host smart-80cc7c25-d279-4f97-8806-6d1cba34ced3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139728503 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_bit_bash.3139728503
Directory /workspace/8.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.659892833
Short name T884
Test name
Test status
Simulation time 311681694 ps
CPU time 1.98 seconds
Started Jun 11 12:54:13 PM PDT 24
Finished Jun 11 12:54:17 PM PDT 24
Peak memory 217928 kb
Host smart-1baf2715-46ff-40a8-9602-0a91202516ed
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659892833 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 8.lc_ctrl_jtag_csr_hw_reset.659892833
Directory /workspace/8.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3455300066
Short name T936
Test name
Test status
Simulation time 330037302 ps
CPU time 2.7 seconds
Started Jun 11 12:54:13 PM PDT 24
Finished Jun 11 12:54:17 PM PDT 24
Peak memory 219272 kb
Host smart-82f5d5fa-7a7f-479b-a4cc-676da3aced5e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345530
0066 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3455300066
Directory /workspace/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.2321307221
Short name T986
Test name
Test status
Simulation time 94226292 ps
CPU time 2.83 seconds
Started Jun 11 12:54:13 PM PDT 24
Finished Jun 11 12:54:17 PM PDT 24
Peak memory 209732 kb
Host smart-2e4b3487-4d6d-4371-8614-476ae0d1caf6
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321307221 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.lc_ctrl_jtag_csr_rw.2321307221
Directory /workspace/8.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.1391169632
Short name T199
Test name
Test status
Simulation time 40955705 ps
CPU time 1.9 seconds
Started Jun 11 12:54:17 PM PDT 24
Finished Jun 11 12:54:20 PM PDT 24
Peak memory 209912 kb
Host smart-87aab808-6b61-431a-902b-3f55d7c17ed5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391169632 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.lc_ctrl_jtag_same_csr_outstanding.1391169632
Directory /workspace/8.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.4206771706
Short name T973
Test name
Test status
Simulation time 19765155 ps
CPU time 1.21 seconds
Started Jun 11 12:54:12 PM PDT 24
Finished Jun 11 12:54:15 PM PDT 24
Peak memory 210052 kb
Host smart-8d6db23f-d8d9-4b1c-9ed0-4ef3f769c8e3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206771706 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl
_same_csr_outstanding.4206771706
Directory /workspace/8.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.2043257051
Short name T897
Test name
Test status
Simulation time 479569346 ps
CPU time 3.15 seconds
Started Jun 11 12:54:12 PM PDT 24
Finished Jun 11 12:54:17 PM PDT 24
Peak memory 218160 kb
Host smart-b0e259d1-6b8d-4218-afa2-85fe4cbb2421
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043257051 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_errors.2043257051
Directory /workspace/8.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.3694554454
Short name T128
Test name
Test status
Simulation time 930265688 ps
CPU time 1.94 seconds
Started Jun 11 12:54:12 PM PDT 24
Finished Jun 11 12:54:15 PM PDT 24
Peak memory 222256 kb
Host smart-81a1e954-dd0e-4639-9562-57a1a07c9b66
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694554454 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_intg_
err.3694554454
Directory /workspace/8.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.2612028104
Short name T106
Test name
Test status
Simulation time 15555832 ps
CPU time 1.11 seconds
Started Jun 11 12:54:12 PM PDT 24
Finished Jun 11 12:54:14 PM PDT 24
Peak memory 221312 kb
Host smart-2d223707-39be-483c-9ce7-cc615305900c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612028104 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 9.lc_ctrl_csr_mem_rw_with_rand_reset.2612028104
Directory /workspace/9.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.1005863950
Short name T942
Test name
Test status
Simulation time 17046466 ps
CPU time 0.93 seconds
Started Jun 11 12:54:12 PM PDT 24
Finished Jun 11 12:54:15 PM PDT 24
Peak memory 209896 kb
Host smart-3da75208-4df5-4ed2-9554-284abb926c95
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005863950 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_csr_rw.1005863950
Directory /workspace/9.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.2534897901
Short name T965
Test name
Test status
Simulation time 128560176 ps
CPU time 1.14 seconds
Started Jun 11 12:54:13 PM PDT 24
Finished Jun 11 12:54:16 PM PDT 24
Peak memory 209928 kb
Host smart-482ab724-c964-48e4-97fb-b62156f117e5
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534897901 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.lc_ctrl_jtag_alert_test.2534897901
Directory /workspace/9.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.589342561
Short name T985
Test name
Test status
Simulation time 4292309365 ps
CPU time 11.4 seconds
Started Jun 11 12:54:13 PM PDT 24
Finished Jun 11 12:54:26 PM PDT 24
Peak memory 217316 kb
Host smart-39d3d331-cf3a-44c6-8853-d18e5038a214
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589342561 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 9.lc_ctrl_jtag_csr_aliasing.589342561
Directory /workspace/9.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.13415283
Short name T961
Test name
Test status
Simulation time 7264169205 ps
CPU time 21.06 seconds
Started Jun 11 12:54:13 PM PDT 24
Finished Jun 11 12:54:36 PM PDT 24
Peak memory 217860 kb
Host smart-c1aa0bef-138a-4786-a3ce-b48cd8e7e2f9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13415283 -assert nopostproc +UVM_TESTNAME=lc_ctrl_bas
e_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 9.lc_ctrl_jtag_csr_bit_bash.13415283
Directory /workspace/9.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.165711173
Short name T905
Test name
Test status
Simulation time 579870442 ps
CPU time 1.47 seconds
Started Jun 11 12:54:13 PM PDT 24
Finished Jun 11 12:54:16 PM PDT 24
Peak memory 210792 kb
Host smart-23e3e5c4-a454-4b3f-b74d-a3772a5900ef
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165711173 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 9.lc_ctrl_jtag_csr_hw_reset.165711173
Directory /workspace/9.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.216375798
Short name T978
Test name
Test status
Simulation time 142914705 ps
CPU time 2.72 seconds
Started Jun 11 12:54:14 PM PDT 24
Finished Jun 11 12:54:18 PM PDT 24
Peak memory 219856 kb
Host smart-7c61f948-c53b-4c3e-87bf-06f815895b0d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216375
798 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.216375798
Directory /workspace/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.1997750078
Short name T915
Test name
Test status
Simulation time 61232801 ps
CPU time 1.5 seconds
Started Jun 11 12:54:12 PM PDT 24
Finished Jun 11 12:54:14 PM PDT 24
Peak memory 209668 kb
Host smart-2aa05409-f4a6-406f-9e0c-4d8a3a3d65a9
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997750078 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.lc_ctrl_jtag_csr_rw.1997750078
Directory /workspace/9.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.176781194
Short name T945
Test name
Test status
Simulation time 15541166 ps
CPU time 1.02 seconds
Started Jun 11 12:54:11 PM PDT 24
Finished Jun 11 12:54:14 PM PDT 24
Peak memory 209884 kb
Host smart-39253651-2e4e-4622-8bac-45768f7e770f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176781194 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.lc_ctrl_jtag_same_csr_outstanding.176781194
Directory /workspace/9.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.2869684634
Short name T197
Test name
Test status
Simulation time 108876483 ps
CPU time 1.49 seconds
Started Jun 11 12:54:13 PM PDT 24
Finished Jun 11 12:54:16 PM PDT 24
Peak memory 210036 kb
Host smart-e865c1d4-8bc4-45ef-bf68-2512f57b8d5f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869684634 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl
_same_csr_outstanding.2869684634
Directory /workspace/9.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.637464975
Short name T941
Test name
Test status
Simulation time 258694131 ps
CPU time 2.11 seconds
Started Jun 11 12:54:17 PM PDT 24
Finished Jun 11 12:54:20 PM PDT 24
Peak memory 218248 kb
Host smart-5b0dbdf2-bef9-4dbd-9fc3-e0e802c352b4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637464975 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_errors.637464975
Directory /workspace/9.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_alert_test.2567560554
Short name T298
Test name
Test status
Simulation time 27144701 ps
CPU time 0.94 seconds
Started Jun 11 02:12:45 PM PDT 24
Finished Jun 11 02:12:48 PM PDT 24
Peak memory 209312 kb
Host smart-9777aec8-6d4e-4ee2-8c4e-ae9dd81ddb69
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567560554 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_alert_test.2567560554
Directory /workspace/0.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.lc_ctrl_claim_transition_if.438403164
Short name T725
Test name
Test status
Simulation time 13230621 ps
CPU time 0.83 seconds
Started Jun 11 02:12:24 PM PDT 24
Finished Jun 11 02:12:27 PM PDT 24
Peak memory 209224 kb
Host smart-6d11dd61-3d5f-43e7-9892-4c4b06996588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438403164 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_claim_transition_if.438403164
Directory /workspace/0.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/0.lc_ctrl_errors.80107183
Short name T610
Test name
Test status
Simulation time 489410507 ps
CPU time 19.02 seconds
Started Jun 11 02:12:26 PM PDT 24
Finished Jun 11 02:12:46 PM PDT 24
Peak memory 218564 kb
Host smart-fa6c69b0-49ac-4c85-bfc4-ad15e3677b84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80107183 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_errors.80107183
Directory /workspace/0.lc_ctrl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_access.3941986990
Short name T533
Test name
Test status
Simulation time 554744301 ps
CPU time 6.1 seconds
Started Jun 11 02:12:24 PM PDT 24
Finished Jun 11 02:12:32 PM PDT 24
Peak memory 217664 kb
Host smart-5ea18ea1-5c10-4b93-b837-ce0b357d3f07
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941986990 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_access.3941986990
Directory /workspace/0.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_errors.2081053271
Short name T593
Test name
Test status
Simulation time 2912726547 ps
CPU time 42.81 seconds
Started Jun 11 02:12:26 PM PDT 24
Finished Jun 11 02:13:10 PM PDT 24
Peak memory 218656 kb
Host smart-5c4b3cae-48a1-4fb2-8e7f-6316083f9a95
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081053271 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_er
rors.2081053271
Directory /workspace/0.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_priority.2372008328
Short name T804
Test name
Test status
Simulation time 355938260 ps
CPU time 1.65 seconds
Started Jun 11 02:12:20 PM PDT 24
Finished Jun 11 02:12:24 PM PDT 24
Peak memory 217876 kb
Host smart-bdc8d5b1-db01-4033-bc50-5cbada873d3b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372008328 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_priority.2
372008328
Directory /workspace/0.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_prog_failure.3139416778
Short name T771
Test name
Test status
Simulation time 1215141621 ps
CPU time 17.18 seconds
Started Jun 11 02:12:20 PM PDT 24
Finished Jun 11 02:12:39 PM PDT 24
Peak memory 224548 kb
Host smart-ea61dba1-234b-48e1-999d-5afbdf08894c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139416778 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag
_prog_failure.3139416778
Directory /workspace/0.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_regwen_during_op.2296433204
Short name T289
Test name
Test status
Simulation time 1079924154 ps
CPU time 19.47 seconds
Started Jun 11 02:12:29 PM PDT 24
Finished Jun 11 02:12:49 PM PDT 24
Peak memory 218228 kb
Host smart-78be4b72-18a3-475f-b4cf-d3b79ae4fb5f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296433204 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_regwen_during_op.2296433204
Directory /workspace/0.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_smoke.916200330
Short name T77
Test name
Test status
Simulation time 108702839 ps
CPU time 3.89 seconds
Started Jun 11 02:12:20 PM PDT 24
Finished Jun 11 02:12:25 PM PDT 24
Peak memory 218196 kb
Host smart-939a9f14-0c20-4cf7-9d9d-795957c8b871
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916200330 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_smoke.916200330
Directory /workspace/0.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_failure.1526996288
Short name T761
Test name
Test status
Simulation time 6323279118 ps
CPU time 57.54 seconds
Started Jun 11 02:12:21 PM PDT 24
Finished Jun 11 02:13:21 PM PDT 24
Peak memory 267884 kb
Host smart-1de08b9a-ea51-490c-9648-3b23077d87c5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526996288 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jta
g_state_failure.1526996288
Directory /workspace/0.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_post_trans.2783186095
Short name T482
Test name
Test status
Simulation time 815062218 ps
CPU time 25.9 seconds
Started Jun 11 02:12:23 PM PDT 24
Finished Jun 11 02:12:51 PM PDT 24
Peak memory 250648 kb
Host smart-d3b9bd10-9bfe-4803-b317-82941ab414dd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783186095 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_state_post_trans.2783186095
Directory /workspace/0.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_prog_failure.3067171577
Short name T278
Test name
Test status
Simulation time 460339547 ps
CPU time 2.72 seconds
Started Jun 11 02:12:22 PM PDT 24
Finished Jun 11 02:12:27 PM PDT 24
Peak memory 222652 kb
Host smart-ada194cb-1ab5-4984-9da7-16ea4e4955dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067171577 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_prog_failure.3067171577
Directory /workspace/0.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_regwen_during_op.3861011152
Short name T202
Test name
Test status
Simulation time 403329995 ps
CPU time 13.12 seconds
Started Jun 11 02:12:21 PM PDT 24
Finished Jun 11 02:12:36 PM PDT 24
Peak memory 215252 kb
Host smart-99d71eb6-4f8d-48d0-8f70-ee2635b4449d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861011152 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_regwen_during_op.3861011152
Directory /workspace/0.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_mubi.3369296716
Short name T175
Test name
Test status
Simulation time 1991469885 ps
CPU time 13.09 seconds
Started Jun 11 02:12:29 PM PDT 24
Finished Jun 11 02:12:44 PM PDT 24
Peak memory 218796 kb
Host smart-973bb00e-4389-4035-9e0b-fa2120e52995
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369296716 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_mubi.3369296716
Directory /workspace/0.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_digest.2526372244
Short name T260
Test name
Test status
Simulation time 1728178938 ps
CPU time 9.69 seconds
Started Jun 11 02:12:32 PM PDT 24
Finished Jun 11 02:12:43 PM PDT 24
Peak memory 218692 kb
Host smart-7059bbaf-4bac-441c-a839-e8a11798a332
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526372244 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_di
gest.2526372244
Directory /workspace/0.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_mux.248409159
Short name T93
Test name
Test status
Simulation time 1760675666 ps
CPU time 15.87 seconds
Started Jun 11 02:12:29 PM PDT 24
Finished Jun 11 02:12:46 PM PDT 24
Peak memory 218648 kb
Host smart-dc747f71-7f28-48f3-baf7-871e1cc7efe3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248409159 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_mux.248409159
Directory /workspace/0.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/0.lc_ctrl_security_escalation.2540989532
Short name T785
Test name
Test status
Simulation time 274965492 ps
CPU time 6.95 seconds
Started Jun 11 02:12:24 PM PDT 24
Finished Jun 11 02:12:33 PM PDT 24
Peak memory 225380 kb
Host smart-3731db9e-8d48-44fe-83ac-266827e5ef66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540989532 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_security_escalation.2540989532
Directory /workspace/0.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/0.lc_ctrl_smoke.1841883243
Short name T732
Test name
Test status
Simulation time 91860559 ps
CPU time 2.65 seconds
Started Jun 11 02:12:19 PM PDT 24
Finished Jun 11 02:12:23 PM PDT 24
Peak memory 215072 kb
Host smart-2118d6c3-dcbf-40ce-ac96-31150e30e253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841883243 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_smoke.1841883243
Directory /workspace/0.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_failure.4280762228
Short name T457
Test name
Test status
Simulation time 1257971709 ps
CPU time 31.81 seconds
Started Jun 11 02:12:24 PM PDT 24
Finished Jun 11 02:12:58 PM PDT 24
Peak memory 251384 kb
Host smart-fad9d190-688a-46e0-bd3b-8b15ab33f2d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280762228 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_failure.4280762228
Directory /workspace/0.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_post_trans.1222257158
Short name T618
Test name
Test status
Simulation time 188128378 ps
CPU time 9.25 seconds
Started Jun 11 02:12:19 PM PDT 24
Finished Jun 11 02:12:30 PM PDT 24
Peak memory 251400 kb
Host smart-206a2f95-ebc7-479c-b616-f6e1bde4befa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222257158 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_post_trans.1222257158
Directory /workspace/0.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_volatile_unlock_smoke.564974441
Short name T354
Test name
Test status
Simulation time 12161576 ps
CPU time 1.09 seconds
Started Jun 11 02:12:24 PM PDT 24
Finished Jun 11 02:12:27 PM PDT 24
Peak memory 212228 kb
Host smart-28bf8e61-7597-4e0c-9ea6-c18428dd2fea
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564974441 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctr
l_volatile_unlock_smoke.564974441
Directory /workspace/0.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_alert_test.1170633325
Short name T708
Test name
Test status
Simulation time 27625580 ps
CPU time 0.89 seconds
Started Jun 11 02:12:29 PM PDT 24
Finished Jun 11 02:12:31 PM PDT 24
Peak memory 209296 kb
Host smart-ebe683cd-46ad-4a9f-9012-9b42192dc7d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170633325 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_alert_test.1170633325
Directory /workspace/1.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.lc_ctrl_errors.1641754151
Short name T151
Test name
Test status
Simulation time 242616215 ps
CPU time 8.78 seconds
Started Jun 11 02:12:32 PM PDT 24
Finished Jun 11 02:12:42 PM PDT 24
Peak memory 218644 kb
Host smart-df9bb425-86c3-4e25-b08b-b85865883566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641754151 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_errors.1641754151
Directory /workspace/1.lc_ctrl_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_access.1582257578
Short name T693
Test name
Test status
Simulation time 204375723 ps
CPU time 3.37 seconds
Started Jun 11 02:12:32 PM PDT 24
Finished Jun 11 02:12:37 PM PDT 24
Peak memory 217572 kb
Host smart-43b55d2e-6ecb-443c-85b3-08b9da795cb3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582257578 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_access.1582257578
Directory /workspace/1.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_errors.2584990425
Short name T307
Test name
Test status
Simulation time 2875076615 ps
CPU time 40.15 seconds
Started Jun 11 02:12:34 PM PDT 24
Finished Jun 11 02:13:15 PM PDT 24
Peak memory 219500 kb
Host smart-8bd2ce96-3c4d-4ee3-ac9b-13206d9f2218
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584990425 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_er
rors.2584990425
Directory /workspace/1.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_priority.2572114924
Short name T414
Test name
Test status
Simulation time 291935099 ps
CPU time 2.24 seconds
Started Jun 11 02:12:30 PM PDT 24
Finished Jun 11 02:12:33 PM PDT 24
Peak memory 217844 kb
Host smart-52c47197-8737-463d-8142-1a230f19eb3b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572114924 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_priority.2
572114924
Directory /workspace/1.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_prog_failure.2723106319
Short name T696
Test name
Test status
Simulation time 285156855 ps
CPU time 2.95 seconds
Started Jun 11 02:12:30 PM PDT 24
Finished Jun 11 02:12:34 PM PDT 24
Peak memory 218676 kb
Host smart-c906e932-7725-4860-9023-25c2fa786015
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723106319 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag
_prog_failure.2723106319
Directory /workspace/1.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_regwen_during_op.2296470169
Short name T89
Test name
Test status
Simulation time 8415133679 ps
CPU time 40.14 seconds
Started Jun 11 02:12:31 PM PDT 24
Finished Jun 11 02:13:13 PM PDT 24
Peak memory 218256 kb
Host smart-1512c308-0dc2-474f-a671-0edad29c61fb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296470169 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_regwen_during_op.2296470169
Directory /workspace/1.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_smoke.341547827
Short name T826
Test name
Test status
Simulation time 481278320 ps
CPU time 6.88 seconds
Started Jun 11 02:12:28 PM PDT 24
Finished Jun 11 02:12:36 PM PDT 24
Peak memory 218128 kb
Host smart-4aca353f-8daf-4aae-8652-b0b2ed6d5ab6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341547827 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_smoke.341547827
Directory /workspace/1.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_failure.2843637644
Short name T410
Test name
Test status
Simulation time 3313339581 ps
CPU time 41.09 seconds
Started Jun 11 02:12:29 PM PDT 24
Finished Jun 11 02:13:11 PM PDT 24
Peak memory 251640 kb
Host smart-57726e6a-fb26-41a0-a954-8dc43a6aa49f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843637644 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jta
g_state_failure.2843637644
Directory /workspace/1.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_post_trans.1157145217
Short name T158
Test name
Test status
Simulation time 1148038180 ps
CPU time 23.52 seconds
Started Jun 11 02:12:30 PM PDT 24
Finished Jun 11 02:12:55 PM PDT 24
Peak memory 251424 kb
Host smart-8e1259b3-f5fe-4fff-993a-90c56b74a376
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157145217 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_state_post_trans.1157145217
Directory /workspace/1.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_prog_failure.2141729053
Short name T713
Test name
Test status
Simulation time 605326192 ps
CPU time 1.92 seconds
Started Jun 11 02:12:28 PM PDT 24
Finished Jun 11 02:12:31 PM PDT 24
Peak memory 222628 kb
Host smart-f802b17d-59a0-4498-9e6a-225982ad8105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141729053 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_prog_failure.2141729053
Directory /workspace/1.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_regwen_during_op.1469503448
Short name T691
Test name
Test status
Simulation time 352287226 ps
CPU time 19.65 seconds
Started Jun 11 02:12:31 PM PDT 24
Finished Jun 11 02:12:52 PM PDT 24
Peak memory 218408 kb
Host smart-c45ae191-89cb-4fa0-a712-cf6a792a0931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469503448 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_regwen_during_op.1469503448
Directory /workspace/1.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_cm.966654495
Short name T82
Test name
Test status
Simulation time 881300664 ps
CPU time 26.43 seconds
Started Jun 11 02:12:30 PM PDT 24
Finished Jun 11 02:12:58 PM PDT 24
Peak memory 282576 kb
Host smart-05d01505-ee1f-42e0-91fd-d5e1736c7182
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966654495 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_cm.966654495
Directory /workspace/1.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_mubi.3759352903
Short name T161
Test name
Test status
Simulation time 1249338235 ps
CPU time 15.13 seconds
Started Jun 11 02:12:31 PM PDT 24
Finished Jun 11 02:12:48 PM PDT 24
Peak memory 226388 kb
Host smart-d9ee37ce-696f-49f2-b047-ff6e2f30a7d0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759352903 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_mubi.3759352903
Directory /workspace/1.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_digest.2300486982
Short name T253
Test name
Test status
Simulation time 591020079 ps
CPU time 12.62 seconds
Started Jun 11 02:12:30 PM PDT 24
Finished Jun 11 02:12:44 PM PDT 24
Peak memory 218752 kb
Host smart-805c95f0-7510-4717-8fd7-56a0a983289a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300486982 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_di
gest.2300486982
Directory /workspace/1.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_mux.105234762
Short name T565
Test name
Test status
Simulation time 2437263919 ps
CPU time 6.63 seconds
Started Jun 11 02:12:27 PM PDT 24
Finished Jun 11 02:12:35 PM PDT 24
Peak memory 218968 kb
Host smart-4e64b752-d769-45c3-855c-8a0bd2561fc4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105234762 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_mux.105234762
Directory /workspace/1.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/1.lc_ctrl_security_escalation.3618745679
Short name T245
Test name
Test status
Simulation time 218247029 ps
CPU time 9.3 seconds
Started Jun 11 02:12:32 PM PDT 24
Finished Jun 11 02:12:43 PM PDT 24
Peak memory 225332 kb
Host smart-caa79fbe-b29a-4464-9196-8d10ab6362c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618745679 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_security_escalation.3618745679
Directory /workspace/1.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/1.lc_ctrl_smoke.4103216872
Short name T1
Test name
Test status
Simulation time 109816519 ps
CPU time 1.93 seconds
Started Jun 11 02:12:29 PM PDT 24
Finished Jun 11 02:12:32 PM PDT 24
Peak memory 214392 kb
Host smart-954c8b86-0028-4659-ad97-507a5e6d9a89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103216872 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_smoke.4103216872
Directory /workspace/1.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_failure.2373804669
Short name T730
Test name
Test status
Simulation time 331414425 ps
CPU time 26.67 seconds
Started Jun 11 02:12:28 PM PDT 24
Finished Jun 11 02:12:56 PM PDT 24
Peak memory 251408 kb
Host smart-790f5f8a-3e66-46a9-9518-84f65cfe43f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373804669 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_failure.2373804669
Directory /workspace/1.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_post_trans.406883937
Short name T579
Test name
Test status
Simulation time 184695642 ps
CPU time 6.66 seconds
Started Jun 11 02:12:32 PM PDT 24
Finished Jun 11 02:12:40 PM PDT 24
Peak memory 250920 kb
Host smart-bffd197c-991e-4979-97e9-c36e24e998cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406883937 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_post_trans.406883937
Directory /workspace/1.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_stress_all.1944808921
Short name T757
Test name
Test status
Simulation time 6129627797 ps
CPU time 77.57 seconds
Started Jun 11 02:12:28 PM PDT 24
Finished Jun 11 02:13:47 PM PDT 24
Peak memory 273288 kb
Host smart-10a1afa6-7a34-4197-be9d-5f817d4f1f9d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944808921 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.lc_ctrl_stress_all.1944808921
Directory /workspace/1.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.lc_ctrl_stress_all_with_rand_reset.2814181931
Short name T863
Test name
Test status
Simulation time 24347638559 ps
CPU time 586.37 seconds
Started Jun 11 02:12:31 PM PDT 24
Finished Jun 11 02:22:19 PM PDT 24
Peak memory 448200 kb
Host smart-39f3d281-69d1-4de4-8978-bb9e596decb0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2814181931 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_stress_all_with_rand_reset.2814181931
Directory /workspace/1.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.lc_ctrl_volatile_unlock_smoke.271330494
Short name T724
Test name
Test status
Simulation time 32791947 ps
CPU time 1.2 seconds
Started Jun 11 02:12:29 PM PDT 24
Finished Jun 11 02:12:32 PM PDT 24
Peak memory 213416 kb
Host smart-d3fd88bf-b77d-43a6-99a8-48584d0b5f6d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271330494 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctr
l_volatile_unlock_smoke.271330494
Directory /workspace/1.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_alert_test.1257343971
Short name T421
Test name
Test status
Simulation time 34799234 ps
CPU time 1.09 seconds
Started Jun 11 02:13:05 PM PDT 24
Finished Jun 11 02:13:09 PM PDT 24
Peak memory 209440 kb
Host smart-aca081a3-d592-4762-94e2-f783a1e21303
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257343971 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_alert_test.1257343971
Directory /workspace/10.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.lc_ctrl_errors.3195331869
Short name T518
Test name
Test status
Simulation time 2109737643 ps
CPU time 13.31 seconds
Started Jun 11 02:13:02 PM PDT 24
Finished Jun 11 02:13:19 PM PDT 24
Peak memory 218748 kb
Host smart-e67e15ab-d377-482c-855b-7f48ddeb33a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195331869 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_errors.3195331869
Directory /workspace/10.lc_ctrl_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_access.240107526
Short name T25
Test name
Test status
Simulation time 287877587 ps
CPU time 3.8 seconds
Started Jun 11 02:13:06 PM PDT 24
Finished Jun 11 02:13:13 PM PDT 24
Peak memory 217628 kb
Host smart-8ddd87ba-2697-4a11-87fc-fb9310e76fb1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240107526 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_access.240107526
Directory /workspace/10.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_prog_failure.2698337587
Short name T566
Test name
Test status
Simulation time 1274237208 ps
CPU time 19.03 seconds
Started Jun 11 02:13:01 PM PDT 24
Finished Jun 11 02:13:23 PM PDT 24
Peak memory 218696 kb
Host smart-78ef22e3-ec92-4564-8f92-3d95520f1193
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698337587 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jta
g_prog_failure.2698337587
Directory /workspace/10.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_smoke.2834449729
Short name T475
Test name
Test status
Simulation time 637605147 ps
CPU time 15.09 seconds
Started Jun 11 02:13:09 PM PDT 24
Finished Jun 11 02:13:26 PM PDT 24
Peak memory 218300 kb
Host smart-2520c985-f939-432c-87ef-f9f37fa0cec6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834449729 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_smoke
.2834449729
Directory /workspace/10.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_failure.1826349602
Short name T746
Test name
Test status
Simulation time 5762816804 ps
CPU time 46.95 seconds
Started Jun 11 02:13:06 PM PDT 24
Finished Jun 11 02:13:56 PM PDT 24
Peak memory 269328 kb
Host smart-e3f0e53f-35eb-4b64-8cb7-f08348b8aa71
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826349602 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jt
ag_state_failure.1826349602
Directory /workspace/10.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_post_trans.2533128426
Short name T458
Test name
Test status
Simulation time 730248934 ps
CPU time 11.83 seconds
Started Jun 11 02:13:06 PM PDT 24
Finished Jun 11 02:13:21 PM PDT 24
Peak memory 251464 kb
Host smart-9177c147-f238-4f88-add8-c71678c40272
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533128426 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl
_jtag_state_post_trans.2533128426
Directory /workspace/10.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_prog_failure.627686066
Short name T802
Test name
Test status
Simulation time 360101693 ps
CPU time 3.09 seconds
Started Jun 11 02:13:06 PM PDT 24
Finished Jun 11 02:13:12 PM PDT 24
Peak memory 218728 kb
Host smart-f5143b53-c245-4e1f-b913-c881fe464eac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627686066 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_prog_failure.627686066
Directory /workspace/10.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_mubi.500545511
Short name T41
Test name
Test status
Simulation time 471086274 ps
CPU time 14.85 seconds
Started Jun 11 02:13:07 PM PDT 24
Finished Jun 11 02:13:25 PM PDT 24
Peak memory 218720 kb
Host smart-1fa632cc-ba8a-4750-bfb9-eb46b9f00597
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500545511 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_mubi.500545511
Directory /workspace/10.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_digest.906063791
Short name T380
Test name
Test status
Simulation time 1222094161 ps
CPU time 16.33 seconds
Started Jun 11 02:13:02 PM PDT 24
Finished Jun 11 02:13:22 PM PDT 24
Peak memory 218744 kb
Host smart-ff064c19-e550-4c09-b51d-9885f3d0d6d2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906063791 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_di
gest.906063791
Directory /workspace/10.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_mux.2919644263
Short name T48
Test name
Test status
Simulation time 753410629 ps
CPU time 6.33 seconds
Started Jun 11 02:13:13 PM PDT 24
Finished Jun 11 02:13:21 PM PDT 24
Peak memory 225344 kb
Host smart-ea7cc378-fca6-4221-8d6d-f9d6fec37ddd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919644263 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_mux.
2919644263
Directory /workspace/10.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/10.lc_ctrl_smoke.215816957
Short name T777
Test name
Test status
Simulation time 49249099 ps
CPU time 3.58 seconds
Started Jun 11 02:13:04 PM PDT 24
Finished Jun 11 02:13:11 PM PDT 24
Peak memory 218232 kb
Host smart-d43cb3a4-6eba-41a4-9132-6f498f9a4e1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215816957 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_smoke.215816957
Directory /workspace/10.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_failure.3908725830
Short name T290
Test name
Test status
Simulation time 1097284996 ps
CPU time 26.47 seconds
Started Jun 11 02:13:01 PM PDT 24
Finished Jun 11 02:13:32 PM PDT 24
Peak memory 251444 kb
Host smart-c2dd4b40-3097-41b3-9b81-52845aad5298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908725830 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_failure.3908725830
Directory /workspace/10.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_post_trans.1994177031
Short name T620
Test name
Test status
Simulation time 785717383 ps
CPU time 4.23 seconds
Started Jun 11 02:13:07 PM PDT 24
Finished Jun 11 02:13:14 PM PDT 24
Peak memory 222684 kb
Host smart-6e76f801-7d78-4097-8d4d-c13d5d36370a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1994177031 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_post_trans.1994177031
Directory /workspace/10.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all.4137648720
Short name T20
Test name
Test status
Simulation time 2716623166 ps
CPU time 109.38 seconds
Started Jun 11 02:13:03 PM PDT 24
Finished Jun 11 02:14:56 PM PDT 24
Peak memory 271964 kb
Host smart-9f761635-8af7-4f29-a528-730129094a51
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137648720 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.lc_ctrl_stress_all.4137648720
Directory /workspace/10.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.lc_ctrl_volatile_unlock_smoke.2285688729
Short name T300
Test name
Test status
Simulation time 39872293 ps
CPU time 0.86 seconds
Started Jun 11 02:13:04 PM PDT 24
Finished Jun 11 02:13:08 PM PDT 24
Peak memory 209544 kb
Host smart-adb815d0-8835-4937-8ee9-af1e5913d23a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285688729 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_c
trl_volatile_unlock_smoke.2285688729
Directory /workspace/10.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_alert_test.2231890338
Short name T803
Test name
Test status
Simulation time 19588546 ps
CPU time 1.02 seconds
Started Jun 11 02:13:02 PM PDT 24
Finished Jun 11 02:13:07 PM PDT 24
Peak memory 209452 kb
Host smart-1632b2ac-bf75-40c0-b6b8-fefe17553cf3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231890338 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_alert_test.2231890338
Directory /workspace/11.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.lc_ctrl_errors.2325001182
Short name T717
Test name
Test status
Simulation time 1859179695 ps
CPU time 14.4 seconds
Started Jun 11 02:13:02 PM PDT 24
Finished Jun 11 02:13:20 PM PDT 24
Peak memory 218740 kb
Host smart-a941858a-1499-4404-99dd-4cdb7ad3d606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325001182 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_errors.2325001182
Directory /workspace/11.lc_ctrl_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_access.1755185724
Short name T570
Test name
Test status
Simulation time 737918061 ps
CPU time 10.07 seconds
Started Jun 11 02:13:14 PM PDT 24
Finished Jun 11 02:13:26 PM PDT 24
Peak memory 218204 kb
Host smart-25c2253c-f5a4-4cc2-af73-a26c5a2eb57b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755185724 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_access.1755185724
Directory /workspace/11.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_errors.84921900
Short name T679
Test name
Test status
Simulation time 2409470987 ps
CPU time 35.23 seconds
Started Jun 11 02:13:15 PM PDT 24
Finished Jun 11 02:13:52 PM PDT 24
Peak memory 226440 kb
Host smart-f9ee84b4-5e6a-460e-8a49-11c5ad6dfe7f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84921900 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_l
c_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_err
ors.84921900
Directory /workspace/11.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_prog_failure.4251669810
Short name T251
Test name
Test status
Simulation time 350616583 ps
CPU time 6.16 seconds
Started Jun 11 02:13:14 PM PDT 24
Finished Jun 11 02:13:23 PM PDT 24
Peak memory 218752 kb
Host smart-fb7c843a-8081-4b51-970e-3ad81fd3948e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251669810 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jta
g_prog_failure.4251669810
Directory /workspace/11.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_smoke.2219497932
Short name T531
Test name
Test status
Simulation time 162679772 ps
CPU time 3.13 seconds
Started Jun 11 02:13:07 PM PDT 24
Finished Jun 11 02:13:13 PM PDT 24
Peak memory 218112 kb
Host smart-f024756d-3c4b-4593-97eb-ec64dab2f5ec
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219497932 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_smoke
.2219497932
Directory /workspace/11.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_failure.2268888860
Short name T526
Test name
Test status
Simulation time 3532126533 ps
CPU time 36.59 seconds
Started Jun 11 02:13:14 PM PDT 24
Finished Jun 11 02:13:53 PM PDT 24
Peak memory 251476 kb
Host smart-33dd0b4d-47c8-4872-b4b9-ca7d81e9aedd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268888860 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jt
ag_state_failure.2268888860
Directory /workspace/11.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_post_trans.3773220744
Short name T303
Test name
Test status
Simulation time 6216986413 ps
CPU time 27.53 seconds
Started Jun 11 02:13:14 PM PDT 24
Finished Jun 11 02:13:44 PM PDT 24
Peak memory 251268 kb
Host smart-0be8eccb-8784-4003-b0c2-9d92dc7cc79a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773220744 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl
_jtag_state_post_trans.3773220744
Directory /workspace/11.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_prog_failure.214035676
Short name T423
Test name
Test status
Simulation time 167495308 ps
CPU time 2.22 seconds
Started Jun 11 02:13:02 PM PDT 24
Finished Jun 11 02:13:08 PM PDT 24
Peak memory 218864 kb
Host smart-6db4f648-7458-4263-a0fa-64f8a1773c26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214035676 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_prog_failure.214035676
Directory /workspace/11.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_mubi.2523636115
Short name T36
Test name
Test status
Simulation time 364622979 ps
CPU time 13.65 seconds
Started Jun 11 02:13:13 PM PDT 24
Finished Jun 11 02:13:27 PM PDT 24
Peak memory 219404 kb
Host smart-17742e91-0b24-4e46-b529-6f18e0854676
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523636115 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_mubi.2523636115
Directory /workspace/11.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_digest.145589187
Short name T326
Test name
Test status
Simulation time 415048575 ps
CPU time 14.61 seconds
Started Jun 11 02:13:15 PM PDT 24
Finished Jun 11 02:13:31 PM PDT 24
Peak memory 226528 kb
Host smart-49d9e27f-61e8-4102-9fd1-ac54e9f1007e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145589187 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_di
gest.145589187
Directory /workspace/11.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_mux.872639546
Short name T670
Test name
Test status
Simulation time 901432610 ps
CPU time 7.34 seconds
Started Jun 11 02:13:03 PM PDT 24
Finished Jun 11 02:13:14 PM PDT 24
Peak memory 218792 kb
Host smart-e7fd2eec-99ce-41c8-9ebc-5f1aca6bb3e1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872639546 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_mux.872639546
Directory /workspace/11.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/11.lc_ctrl_security_escalation.94831786
Short name T613
Test name
Test status
Simulation time 609981754 ps
CPU time 6.08 seconds
Started Jun 11 02:13:13 PM PDT 24
Finished Jun 11 02:13:20 PM PDT 24
Peak memory 218756 kb
Host smart-1ea7e581-8b87-4417-bd74-adeb9e1dafa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94831786 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_security_escalation.94831786
Directory /workspace/11.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/11.lc_ctrl_smoke.3710047373
Short name T239
Test name
Test status
Simulation time 21079578 ps
CPU time 1.48 seconds
Started Jun 11 02:13:06 PM PDT 24
Finished Jun 11 02:13:10 PM PDT 24
Peak memory 218228 kb
Host smart-87f19e44-f379-4bb3-8845-138d6aa375b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710047373 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_smoke.3710047373
Directory /workspace/11.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_failure.3252355342
Short name T95
Test name
Test status
Simulation time 1095396721 ps
CPU time 23.59 seconds
Started Jun 11 02:13:04 PM PDT 24
Finished Jun 11 02:13:31 PM PDT 24
Peak memory 251424 kb
Host smart-eaae5271-5ce4-4b40-9237-df6cf03a55b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252355342 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_failure.3252355342
Directory /workspace/11.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_post_trans.466541
Short name T493
Test name
Test status
Simulation time 73229911 ps
CPU time 3.3 seconds
Started Jun 11 02:13:04 PM PDT 24
Finished Jun 11 02:13:11 PM PDT 24
Peak memory 222868 kb
Host smart-279048ad-b2da-437d-8e15-299f66756758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466541 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_post_trans.466541
Directory /workspace/11.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_stress_all.3951313741
Short name T459
Test name
Test status
Simulation time 21218758290 ps
CPU time 147.84 seconds
Started Jun 11 02:13:13 PM PDT 24
Finished Jun 11 02:15:43 PM PDT 24
Peak memory 271944 kb
Host smart-72e239be-0ea0-44af-9543-7d6f67bd986b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951313741 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.lc_ctrl_stress_all.3951313741
Directory /workspace/11.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.lc_ctrl_volatile_unlock_smoke.1602430477
Short name T709
Test name
Test status
Simulation time 41313877 ps
CPU time 1.02 seconds
Started Jun 11 02:13:07 PM PDT 24
Finished Jun 11 02:13:11 PM PDT 24
Peak memory 212408 kb
Host smart-94bfd7b8-f2cc-4b72-b237-4d4815242ae3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602430477 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_c
trl_volatile_unlock_smoke.1602430477
Directory /workspace/11.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_alert_test.1949092553
Short name T66
Test name
Test status
Simulation time 134832204 ps
CPU time 0.96 seconds
Started Jun 11 02:13:23 PM PDT 24
Finished Jun 11 02:13:26 PM PDT 24
Peak memory 209400 kb
Host smart-47ea0af8-979b-4f02-9ac4-f3cf9fe8e1ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949092553 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_alert_test.1949092553
Directory /workspace/12.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.lc_ctrl_errors.804739781
Short name T395
Test name
Test status
Simulation time 191365308 ps
CPU time 7.51 seconds
Started Jun 11 02:13:14 PM PDT 24
Finished Jun 11 02:13:23 PM PDT 24
Peak memory 218792 kb
Host smart-106565c1-ee1b-4f78-9e39-ba3279cb10a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804739781 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_errors.804739781
Directory /workspace/12.lc_ctrl_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_access.3739653065
Short name T719
Test name
Test status
Simulation time 1635063347 ps
CPU time 5.7 seconds
Started Jun 11 02:13:15 PM PDT 24
Finished Jun 11 02:13:22 PM PDT 24
Peak memory 217912 kb
Host smart-b08d7e05-fdee-40e0-bc5f-e0c9776576b4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739653065 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_access.3739653065
Directory /workspace/12.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_errors.3780336738
Short name T770
Test name
Test status
Simulation time 4865063598 ps
CPU time 127.58 seconds
Started Jun 11 02:13:16 PM PDT 24
Finished Jun 11 02:15:25 PM PDT 24
Peak memory 220376 kb
Host smart-a3b7ba8e-8787-4a80-ae91-d2133f3da3e0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780336738 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_e
rrors.3780336738
Directory /workspace/12.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_prog_failure.2731955935
Short name T536
Test name
Test status
Simulation time 1790471542 ps
CPU time 13.73 seconds
Started Jun 11 02:13:14 PM PDT 24
Finished Jun 11 02:13:29 PM PDT 24
Peak memory 218732 kb
Host smart-1e3a1f6d-3c05-4ff6-8d5d-b0910224fa8b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731955935 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jta
g_prog_failure.2731955935
Directory /workspace/12.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_smoke.218553993
Short name T726
Test name
Test status
Simulation time 263353215 ps
CPU time 2.74 seconds
Started Jun 11 02:13:17 PM PDT 24
Finished Jun 11 02:13:21 PM PDT 24
Peak memory 218284 kb
Host smart-ee8c2302-6b5c-432a-a3a7-1892b0e632ad
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218553993 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_smoke.
218553993
Directory /workspace/12.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_failure.1483314144
Short name T646
Test name
Test status
Simulation time 8179890451 ps
CPU time 32.79 seconds
Started Jun 11 02:13:15 PM PDT 24
Finished Jun 11 02:13:49 PM PDT 24
Peak memory 276164 kb
Host smart-ac21562d-200f-44ae-bc14-524feb2a2533
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483314144 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jt
ag_state_failure.1483314144
Directory /workspace/12.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_post_trans.3827507900
Short name T214
Test name
Test status
Simulation time 940221413 ps
CPU time 19.48 seconds
Started Jun 11 02:13:15 PM PDT 24
Finished Jun 11 02:13:36 PM PDT 24
Peak memory 244828 kb
Host smart-52de9521-3984-42a7-a7be-993f8c1d06d5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827507900 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl
_jtag_state_post_trans.3827507900
Directory /workspace/12.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_prog_failure.2363246286
Short name T269
Test name
Test status
Simulation time 307439252 ps
CPU time 3.07 seconds
Started Jun 11 02:13:13 PM PDT 24
Finished Jun 11 02:13:18 PM PDT 24
Peak memory 218696 kb
Host smart-d5b1b77f-a179-4c03-9f36-f155976847fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2363246286 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_prog_failure.2363246286
Directory /workspace/12.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_mubi.1663415732
Short name T152
Test name
Test status
Simulation time 512572295 ps
CPU time 11.72 seconds
Started Jun 11 02:13:15 PM PDT 24
Finished Jun 11 02:13:29 PM PDT 24
Peak memory 219380 kb
Host smart-c980c97d-77ef-4a01-9cdb-347a803bd39c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663415732 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_mubi.1663415732
Directory /workspace/12.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_digest.1258204407
Short name T632
Test name
Test status
Simulation time 351992597 ps
CPU time 10.5 seconds
Started Jun 11 02:13:16 PM PDT 24
Finished Jun 11 02:13:28 PM PDT 24
Peak memory 218612 kb
Host smart-f989724f-6c40-469b-b922-8f2384029bfc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258204407 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_d
igest.1258204407
Directory /workspace/12.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_mux.826977820
Short name T389
Test name
Test status
Simulation time 2538198913 ps
CPU time 8.73 seconds
Started Jun 11 02:13:14 PM PDT 24
Finished Jun 11 02:13:25 PM PDT 24
Peak memory 218704 kb
Host smart-284cb9bf-1eef-44fb-9e5a-05553fe7a497
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826977820 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_mux.826977820
Directory /workspace/12.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/12.lc_ctrl_security_escalation.491185501
Short name T695
Test name
Test status
Simulation time 288572948 ps
CPU time 7.9 seconds
Started Jun 11 02:13:13 PM PDT 24
Finished Jun 11 02:13:23 PM PDT 24
Peak memory 225628 kb
Host smart-b1fecdf3-4e13-4f78-9c9f-4e64e05c3405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491185501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_security_escalation.491185501
Directory /workspace/12.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/12.lc_ctrl_smoke.584507733
Short name T359
Test name
Test status
Simulation time 325402649 ps
CPU time 3.45 seconds
Started Jun 11 02:13:14 PM PDT 24
Finished Jun 11 02:13:19 PM PDT 24
Peak memory 218212 kb
Host smart-9b03a328-c695-46f2-b64e-118934952045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584507733 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_smoke.584507733
Directory /workspace/12.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_failure.2639131180
Short name T334
Test name
Test status
Simulation time 969668343 ps
CPU time 25.76 seconds
Started Jun 11 02:13:16 PM PDT 24
Finished Jun 11 02:13:44 PM PDT 24
Peak memory 251432 kb
Host smart-b1edae12-74ba-4f0e-b879-78ea70272339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2639131180 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_failure.2639131180
Directory /workspace/12.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_post_trans.2847503838
Short name T393
Test name
Test status
Simulation time 57833848 ps
CPU time 6.3 seconds
Started Jun 11 02:13:13 PM PDT 24
Finished Jun 11 02:13:21 PM PDT 24
Peak memory 247620 kb
Host smart-c92b2c8e-8044-450e-866d-62de74fd8fc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847503838 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_post_trans.2847503838
Directory /workspace/12.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_stress_all.1052892992
Short name T586
Test name
Test status
Simulation time 9429894825 ps
CPU time 52.39 seconds
Started Jun 11 02:13:15 PM PDT 24
Finished Jun 11 02:14:10 PM PDT 24
Peak memory 284208 kb
Host smart-9d999da8-8387-41bf-8108-4dd544fc98f5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052892992 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.lc_ctrl_stress_all.1052892992
Directory /workspace/12.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.lc_ctrl_volatile_unlock_smoke.4156492060
Short name T79
Test name
Test status
Simulation time 13616324 ps
CPU time 1.11 seconds
Started Jun 11 02:13:13 PM PDT 24
Finished Jun 11 02:13:15 PM PDT 24
Peak memory 212352 kb
Host smart-3f2afc7e-76bb-4e6d-bfec-5c244ec54614
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156492060 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_c
trl_volatile_unlock_smoke.4156492060
Directory /workspace/12.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_alert_test.2400201527
Short name T767
Test name
Test status
Simulation time 150777036 ps
CPU time 0.99 seconds
Started Jun 11 02:13:15 PM PDT 24
Finished Jun 11 02:13:18 PM PDT 24
Peak memory 209468 kb
Host smart-59409150-0263-47d4-9c11-ad504f47c1a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400201527 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_alert_test.2400201527
Directory /workspace/13.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.lc_ctrl_errors.1748112783
Short name T749
Test name
Test status
Simulation time 3107710666 ps
CPU time 8.1 seconds
Started Jun 11 02:13:19 PM PDT 24
Finished Jun 11 02:13:28 PM PDT 24
Peak memory 218764 kb
Host smart-88a9e674-a9a3-4c32-81ff-667829de2f1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748112783 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_errors.1748112783
Directory /workspace/13.lc_ctrl_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_access.3635386091
Short name T180
Test name
Test status
Simulation time 4168198675 ps
CPU time 7.31 seconds
Started Jun 11 02:13:14 PM PDT 24
Finished Jun 11 02:13:23 PM PDT 24
Peak memory 218280 kb
Host smart-3b5a8bdb-cf8a-4880-bb4b-44d53d784145
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635386091 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_access.3635386091
Directory /workspace/13.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_errors.2452656718
Short name T47
Test name
Test status
Simulation time 9943475254 ps
CPU time 42.27 seconds
Started Jun 11 02:13:14 PM PDT 24
Finished Jun 11 02:13:59 PM PDT 24
Peak memory 219324 kb
Host smart-00b2da7e-af9c-4ca7-bcb6-edf3c511379e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452656718 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_e
rrors.2452656718
Directory /workspace/13.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_prog_failure.439082879
Short name T625
Test name
Test status
Simulation time 155255076 ps
CPU time 3.36 seconds
Started Jun 11 02:13:15 PM PDT 24
Finished Jun 11 02:13:20 PM PDT 24
Peak memory 222256 kb
Host smart-7391a257-0e62-4f6c-a61a-f026c3d43f2e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439082879 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag
_prog_failure.439082879
Directory /workspace/13.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_smoke.2301242650
Short name T868
Test name
Test status
Simulation time 4128225322 ps
CPU time 5.78 seconds
Started Jun 11 02:13:14 PM PDT 24
Finished Jun 11 02:13:22 PM PDT 24
Peak memory 218288 kb
Host smart-d5b7e4d9-cbd1-4b81-b402-e815a2a13ecc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301242650 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_smoke
.2301242650
Directory /workspace/13.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_failure.596599598
Short name T416
Test name
Test status
Simulation time 1066988927 ps
CPU time 45.33 seconds
Started Jun 11 02:13:15 PM PDT 24
Finished Jun 11 02:14:02 PM PDT 24
Peak memory 251336 kb
Host smart-492cba9f-b74d-40c5-9e5d-90e311117449
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596599598 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jta
g_state_failure.596599598
Directory /workspace/13.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_post_trans.2100987859
Short name T647
Test name
Test status
Simulation time 579767945 ps
CPU time 16.12 seconds
Started Jun 11 02:13:15 PM PDT 24
Finished Jun 11 02:13:33 PM PDT 24
Peak memory 251456 kb
Host smart-cc8c9f3c-aabe-4646-86f1-cc229d428485
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100987859 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl
_jtag_state_post_trans.2100987859
Directory /workspace/13.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_prog_failure.3401795390
Short name T301
Test name
Test status
Simulation time 47658202 ps
CPU time 2.05 seconds
Started Jun 11 02:13:13 PM PDT 24
Finished Jun 11 02:13:17 PM PDT 24
Peak memory 222572 kb
Host smart-d41757e1-0f0f-46c0-83f3-9782f991bc66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401795390 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_prog_failure.3401795390
Directory /workspace/13.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_digest.1076853392
Short name T544
Test name
Test status
Simulation time 277443038 ps
CPU time 9.05 seconds
Started Jun 11 02:13:14 PM PDT 24
Finished Jun 11 02:13:25 PM PDT 24
Peak memory 226524 kb
Host smart-1460247b-94ca-4dc8-b3f9-8e306ff6e664
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076853392 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_d
igest.1076853392
Directory /workspace/13.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_mux.1637948252
Short name T336
Test name
Test status
Simulation time 454795153 ps
CPU time 10.65 seconds
Started Jun 11 02:13:17 PM PDT 24
Finished Jun 11 02:13:29 PM PDT 24
Peak memory 218744 kb
Host smart-b8d7a267-4ac2-480b-85f6-1a3b8ad66f5d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637948252 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_mux.
1637948252
Directory /workspace/13.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/13.lc_ctrl_security_escalation.2671914124
Short name T621
Test name
Test status
Simulation time 289051914 ps
CPU time 12.78 seconds
Started Jun 11 02:13:14 PM PDT 24
Finished Jun 11 02:13:28 PM PDT 24
Peak memory 226520 kb
Host smart-ea524216-2127-43e6-9ef0-dc2e92599ce5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671914124 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_security_escalation.2671914124
Directory /workspace/13.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/13.lc_ctrl_smoke.417315523
Short name T62
Test name
Test status
Simulation time 34035301 ps
CPU time 2.69 seconds
Started Jun 11 02:13:22 PM PDT 24
Finished Jun 11 02:13:27 PM PDT 24
Peak memory 214768 kb
Host smart-1c220cdb-60bf-486c-94d8-231d85b7e4cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417315523 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_smoke.417315523
Directory /workspace/13.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_failure.411473347
Short name T396
Test name
Test status
Simulation time 263854815 ps
CPU time 33.81 seconds
Started Jun 11 02:13:15 PM PDT 24
Finished Jun 11 02:13:51 PM PDT 24
Peak memory 251452 kb
Host smart-0e55748f-85cb-4745-961c-8faa7dd7224f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411473347 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_failure.411473347
Directory /workspace/13.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_post_trans.578193343
Short name T823
Test name
Test status
Simulation time 975606150 ps
CPU time 3.02 seconds
Started Jun 11 02:13:11 PM PDT 24
Finished Jun 11 02:13:15 PM PDT 24
Peak memory 218616 kb
Host smart-a54183f6-5e2e-40d6-8967-f6731b1edf7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578193343 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_post_trans.578193343
Directory /workspace/13.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all.3613560026
Short name T859
Test name
Test status
Simulation time 3179432218 ps
CPU time 25.42 seconds
Started Jun 11 02:13:18 PM PDT 24
Finished Jun 11 02:13:44 PM PDT 24
Peak memory 247372 kb
Host smart-24a384dd-9db3-47be-a77c-409bafb8a41a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613560026 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.lc_ctrl_stress_all.3613560026
Directory /workspace/13.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.lc_ctrl_volatile_unlock_smoke.3311123976
Short name T669
Test name
Test status
Simulation time 35641200 ps
CPU time 0.79 seconds
Started Jun 11 02:13:19 PM PDT 24
Finished Jun 11 02:13:20 PM PDT 24
Peak memory 209532 kb
Host smart-8f170324-f1f1-4060-b025-13334b815d47
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311123976 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_c
trl_volatile_unlock_smoke.3311123976
Directory /workspace/13.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_alert_test.459954330
Short name T554
Test name
Test status
Simulation time 20630119 ps
CPU time 0.93 seconds
Started Jun 11 02:13:11 PM PDT 24
Finished Jun 11 02:13:13 PM PDT 24
Peak memory 209388 kb
Host smart-2bba1936-08f5-4829-8b4c-802667b506e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459954330 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_alert_test.459954330
Directory /workspace/14.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.lc_ctrl_errors.3728460499
Short name T743
Test name
Test status
Simulation time 516700427 ps
CPU time 13.4 seconds
Started Jun 11 02:13:16 PM PDT 24
Finished Jun 11 02:13:31 PM PDT 24
Peak memory 218696 kb
Host smart-0edffd22-d12d-41e0-9b89-f968fd5ad45b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728460499 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_errors.3728460499
Directory /workspace/14.lc_ctrl_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_access.3632491413
Short name T29
Test name
Test status
Simulation time 5268536401 ps
CPU time 13.31 seconds
Started Jun 11 02:13:15 PM PDT 24
Finished Jun 11 02:13:31 PM PDT 24
Peak memory 218248 kb
Host smart-a2907b4b-25a9-4719-864d-7c12e496ba17
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632491413 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_access.3632491413
Directory /workspace/14.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_errors.1996308503
Short name T626
Test name
Test status
Simulation time 1244320104 ps
CPU time 39.36 seconds
Started Jun 11 02:13:15 PM PDT 24
Finished Jun 11 02:13:57 PM PDT 24
Peak memory 218724 kb
Host smart-6bd517af-7298-4584-a9d4-7b0269083398
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996308503 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_e
rrors.1996308503
Directory /workspace/14.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_prog_failure.1070073645
Short name T261
Test name
Test status
Simulation time 1035826567 ps
CPU time 8.32 seconds
Started Jun 11 02:13:16 PM PDT 24
Finished Jun 11 02:13:26 PM PDT 24
Peak memory 218720 kb
Host smart-9e4ed569-0406-4419-8287-e095c8632265
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070073645 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jta
g_prog_failure.1070073645
Directory /workspace/14.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_smoke.3946953826
Short name T558
Test name
Test status
Simulation time 44919453 ps
CPU time 1.86 seconds
Started Jun 11 02:13:17 PM PDT 24
Finished Jun 11 02:13:20 PM PDT 24
Peak memory 218252 kb
Host smart-c03e89be-ed9b-4f92-9fe0-987477f7f086
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946953826 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_smoke
.3946953826
Directory /workspace/14.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_failure.4094999829
Short name T409
Test name
Test status
Simulation time 2806409472 ps
CPU time 40.25 seconds
Started Jun 11 02:13:15 PM PDT 24
Finished Jun 11 02:13:58 PM PDT 24
Peak memory 251596 kb
Host smart-1a3b36bd-ea79-4798-ae26-0e9d19e3c87a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094999829 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jt
ag_state_failure.4094999829
Directory /workspace/14.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_post_trans.1444456397
Short name T850
Test name
Test status
Simulation time 948782346 ps
CPU time 14.34 seconds
Started Jun 11 02:13:14 PM PDT 24
Finished Jun 11 02:13:30 PM PDT 24
Peak memory 225420 kb
Host smart-34706dae-212c-47d7-af23-ba6ee8d841a4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444456397 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl
_jtag_state_post_trans.1444456397
Directory /workspace/14.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_prog_failure.330068804
Short name T344
Test name
Test status
Simulation time 47082938 ps
CPU time 2.74 seconds
Started Jun 11 02:13:13 PM PDT 24
Finished Jun 11 02:13:17 PM PDT 24
Peak memory 222720 kb
Host smart-e54b0ae9-773c-4c48-96d3-2b7c08073e59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330068804 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_prog_failure.330068804
Directory /workspace/14.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_mubi.10228498
Short name T381
Test name
Test status
Simulation time 598116034 ps
CPU time 12.35 seconds
Started Jun 11 02:13:14 PM PDT 24
Finished Jun 11 02:13:27 PM PDT 24
Peak memory 226580 kb
Host smart-e7df3e49-a6c0-433e-936b-363e18cccdb2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10228498 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_mubi.10228498
Directory /workspace/14.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_digest.1372955894
Short name T652
Test name
Test status
Simulation time 1246323019 ps
CPU time 12.66 seconds
Started Jun 11 02:13:14 PM PDT 24
Finished Jun 11 02:13:29 PM PDT 24
Peak memory 218660 kb
Host smart-2bce8783-dac5-4703-9471-7805e82de589
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372955894 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_d
igest.1372955894
Directory /workspace/14.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_mux.2131665542
Short name T94
Test name
Test status
Simulation time 529060766 ps
CPU time 9.56 seconds
Started Jun 11 02:13:13 PM PDT 24
Finished Jun 11 02:13:23 PM PDT 24
Peak memory 218640 kb
Host smart-5b2d559c-9d20-4c20-aa03-0bdd14474458
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131665542 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_mux.
2131665542
Directory /workspace/14.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/14.lc_ctrl_security_escalation.3535078960
Short name T602
Test name
Test status
Simulation time 759118883 ps
CPU time 10.92 seconds
Started Jun 11 02:13:12 PM PDT 24
Finished Jun 11 02:13:24 PM PDT 24
Peak memory 226496 kb
Host smart-e7478fd5-03f5-4f53-8092-cf6038a3b883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535078960 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_security_escalation.3535078960
Directory /workspace/14.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/14.lc_ctrl_smoke.3449606512
Short name T157
Test name
Test status
Simulation time 77457999 ps
CPU time 3 seconds
Started Jun 11 02:13:15 PM PDT 24
Finished Jun 11 02:13:20 PM PDT 24
Peak memory 215200 kb
Host smart-4744e495-a879-485b-946f-b94c4bc835c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449606512 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_smoke.3449606512
Directory /workspace/14.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_failure.421912718
Short name T546
Test name
Test status
Simulation time 1187690884 ps
CPU time 29.25 seconds
Started Jun 11 02:13:22 PM PDT 24
Finished Jun 11 02:13:54 PM PDT 24
Peak memory 251396 kb
Host smart-e676056b-1534-40b8-9e57-b00181b48c35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421912718 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_failure.421912718
Directory /workspace/14.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_post_trans.2569939952
Short name T480
Test name
Test status
Simulation time 61812299 ps
CPU time 9.09 seconds
Started Jun 11 02:13:14 PM PDT 24
Finished Jun 11 02:13:25 PM PDT 24
Peak memory 251448 kb
Host smart-a9d11858-b825-4c5f-92fd-6da509bb310f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569939952 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_post_trans.2569939952
Directory /workspace/14.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_stress_all.2998448528
Short name T348
Test name
Test status
Simulation time 25961660034 ps
CPU time 129.38 seconds
Started Jun 11 02:13:15 PM PDT 24
Finished Jun 11 02:15:26 PM PDT 24
Peak memory 251456 kb
Host smart-21d45bbb-23f5-4ef7-b8a7-4ada16b4eeed
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998448528 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.lc_ctrl_stress_all.2998448528
Directory /workspace/14.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.lc_ctrl_volatile_unlock_smoke.2554888037
Short name T402
Test name
Test status
Simulation time 40245691 ps
CPU time 0.89 seconds
Started Jun 11 02:13:13 PM PDT 24
Finished Jun 11 02:13:16 PM PDT 24
Peak memory 208688 kb
Host smart-c0c815f4-92da-48d6-9d4a-8273ade678a6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554888037 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_c
trl_volatile_unlock_smoke.2554888037
Directory /workspace/14.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_alert_test.2938224427
Short name T692
Test name
Test status
Simulation time 74278392 ps
CPU time 0.89 seconds
Started Jun 11 02:13:35 PM PDT 24
Finished Jun 11 02:13:38 PM PDT 24
Peak memory 209388 kb
Host smart-09984871-bfa6-474c-ba08-8861fe5a669f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938224427 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_alert_test.2938224427
Directory /workspace/15.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.lc_ctrl_errors.3284592644
Short name T446
Test name
Test status
Simulation time 1351816704 ps
CPU time 10.53 seconds
Started Jun 11 02:13:33 PM PDT 24
Finished Jun 11 02:13:45 PM PDT 24
Peak memory 218760 kb
Host smart-fd603840-9799-4e5e-a70a-9514012a9f91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284592644 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_errors.3284592644
Directory /workspace/15.lc_ctrl_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_access.2556942236
Short name T282
Test name
Test status
Simulation time 344235933 ps
CPU time 1.38 seconds
Started Jun 11 02:13:33 PM PDT 24
Finished Jun 11 02:13:37 PM PDT 24
Peak memory 217544 kb
Host smart-65a077d5-e64b-4b07-ab5c-6cdcf0682914
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556942236 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_access.2556942236
Directory /workspace/15.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_errors.3767234741
Short name T422
Test name
Test status
Simulation time 12005023263 ps
CPU time 46.43 seconds
Started Jun 11 02:13:32 PM PDT 24
Finished Jun 11 02:14:20 PM PDT 24
Peak memory 226556 kb
Host smart-8c573c7a-8d6d-48f5-be16-48a7092f4c5e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767234741 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_e
rrors.3767234741
Directory /workspace/15.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_prog_failure.63315548
Short name T765
Test name
Test status
Simulation time 618921223 ps
CPU time 5.61 seconds
Started Jun 11 02:13:31 PM PDT 24
Finished Jun 11 02:13:37 PM PDT 24
Peak memory 222364 kb
Host smart-9beeac5d-6781-4784-b04b-ea031aaf6499
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63315548 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_p
rog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_
prog_failure.63315548
Directory /workspace/15.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_smoke.4055173411
Short name T581
Test name
Test status
Simulation time 498752356 ps
CPU time 13.03 seconds
Started Jun 11 02:13:23 PM PDT 24
Finished Jun 11 02:13:38 PM PDT 24
Peak memory 218256 kb
Host smart-f77805ae-a69d-4a1a-a718-f85a3b83c208
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055173411 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_smoke
.4055173411
Directory /workspace/15.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_post_trans.20525792
Short name T417
Test name
Test status
Simulation time 514077271 ps
CPU time 12.43 seconds
Started Jun 11 02:13:31 PM PDT 24
Finished Jun 11 02:13:45 PM PDT 24
Peak memory 243224 kb
Host smart-4e2f632a-c2eb-490e-b9cc-df24a19dac09
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20525792 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_s
tate_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_j
tag_state_post_trans.20525792
Directory /workspace/15.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_prog_failure.972866663
Short name T727
Test name
Test status
Simulation time 293576759 ps
CPU time 3.3 seconds
Started Jun 11 02:13:22 PM PDT 24
Finished Jun 11 02:13:28 PM PDT 24
Peak memory 223112 kb
Host smart-acf036d7-f81e-4edd-bd43-8dd14e8fe074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=972866663 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_prog_failure.972866663
Directory /workspace/15.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_mubi.1409545036
Short name T629
Test name
Test status
Simulation time 257692843 ps
CPU time 12.33 seconds
Started Jun 11 02:13:22 PM PDT 24
Finished Jun 11 02:13:36 PM PDT 24
Peak memory 226512 kb
Host smart-c3d5d6f9-6980-4093-b565-d8e848973611
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409545036 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_mubi.1409545036
Directory /workspace/15.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_digest.2789354594
Short name T537
Test name
Test status
Simulation time 291001466 ps
CPU time 7.74 seconds
Started Jun 11 02:13:22 PM PDT 24
Finished Jun 11 02:13:32 PM PDT 24
Peak memory 226556 kb
Host smart-bec47cbc-85db-4baa-9275-19428ffcbfdb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789354594 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_d
igest.2789354594
Directory /workspace/15.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_mux.3424861074
Short name T238
Test name
Test status
Simulation time 743815688 ps
CPU time 9.1 seconds
Started Jun 11 02:13:32 PM PDT 24
Finished Jun 11 02:13:43 PM PDT 24
Peak memory 218708 kb
Host smart-bc566631-0b0d-4e05-aaad-1b408db53d09
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424861074 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_mux.
3424861074
Directory /workspace/15.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/15.lc_ctrl_security_escalation.3283971153
Short name T451
Test name
Test status
Simulation time 497475518 ps
CPU time 8.63 seconds
Started Jun 11 02:13:22 PM PDT 24
Finished Jun 11 02:13:33 PM PDT 24
Peak memory 226540 kb
Host smart-cdd96664-251b-493f-9a6d-229b78b20593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283971153 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_security_escalation.3283971153
Directory /workspace/15.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/15.lc_ctrl_smoke.1053041860
Short name T68
Test name
Test status
Simulation time 110924911 ps
CPU time 3.6 seconds
Started Jun 11 02:13:23 PM PDT 24
Finished Jun 11 02:13:28 PM PDT 24
Peak memory 218196 kb
Host smart-2cb2194c-8de6-41ec-9886-e0d174e3f4b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053041860 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_smoke.1053041860
Directory /workspace/15.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_failure.998428072
Short name T419
Test name
Test status
Simulation time 213500778 ps
CPU time 24.15 seconds
Started Jun 11 02:13:23 PM PDT 24
Finished Jun 11 02:13:49 PM PDT 24
Peak memory 251364 kb
Host smart-4ba9133b-04fc-4650-9b2c-920a65c20529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998428072 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_failure.998428072
Directory /workspace/15.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_post_trans.3372216533
Short name T707
Test name
Test status
Simulation time 63896424 ps
CPU time 7.41 seconds
Started Jun 11 02:13:22 PM PDT 24
Finished Jun 11 02:13:31 PM PDT 24
Peak memory 251392 kb
Host smart-d2be4793-d142-48d5-8bd4-1815196f24c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372216533 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_post_trans.3372216533
Directory /workspace/15.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all.3979644809
Short name T170
Test name
Test status
Simulation time 5259238212 ps
CPU time 171.95 seconds
Started Jun 11 02:13:31 PM PDT 24
Finished Jun 11 02:16:25 PM PDT 24
Peak memory 284260 kb
Host smart-62f1a965-e756-462a-990d-2179fa437e14
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979644809 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.lc_ctrl_stress_all.3979644809
Directory /workspace/15.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.lc_ctrl_volatile_unlock_smoke.2090835666
Short name T78
Test name
Test status
Simulation time 155128707 ps
CPU time 0.92 seconds
Started Jun 11 02:13:22 PM PDT 24
Finished Jun 11 02:13:25 PM PDT 24
Peak memory 212336 kb
Host smart-9ab8de39-7ff8-4725-a6e3-ff4830ad5aef
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090835666 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_c
trl_volatile_unlock_smoke.2090835666
Directory /workspace/15.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_alert_test.1422521426
Short name T433
Test name
Test status
Simulation time 17094528 ps
CPU time 1.15 seconds
Started Jun 11 02:13:24 PM PDT 24
Finished Jun 11 02:13:27 PM PDT 24
Peak memory 209484 kb
Host smart-8c05395c-450b-4a7d-a0de-bc502cf8662c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422521426 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_alert_test.1422521426
Directory /workspace/16.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.lc_ctrl_errors.2379162909
Short name T490
Test name
Test status
Simulation time 899264748 ps
CPU time 10.15 seconds
Started Jun 11 02:13:34 PM PDT 24
Finished Jun 11 02:13:46 PM PDT 24
Peak memory 218592 kb
Host smart-fc3f8a2a-91cb-45a4-9387-5d4ca1d785e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379162909 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_errors.2379162909
Directory /workspace/16.lc_ctrl_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_access.4237868166
Short name T815
Test name
Test status
Simulation time 617727395 ps
CPU time 8.7 seconds
Started Jun 11 02:13:28 PM PDT 24
Finished Jun 11 02:13:38 PM PDT 24
Peak memory 217892 kb
Host smart-cb72727a-b850-47ff-8d6c-2ed19fbb6da5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237868166 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_access.4237868166
Directory /workspace/16.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_errors.651027472
Short name T313
Test name
Test status
Simulation time 2882445026 ps
CPU time 25.36 seconds
Started Jun 11 02:13:31 PM PDT 24
Finished Jun 11 02:13:57 PM PDT 24
Peak memory 218772 kb
Host smart-cb0e37c8-40ad-47b4-a624-41705e85bd9e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651027472 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_er
rors.651027472
Directory /workspace/16.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_prog_failure.791120405
Short name T291
Test name
Test status
Simulation time 508097649 ps
CPU time 4.37 seconds
Started Jun 11 02:13:22 PM PDT 24
Finished Jun 11 02:13:29 PM PDT 24
Peak memory 222084 kb
Host smart-32eada9e-0cea-474a-8773-4bd98e03e314
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791120405 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag
_prog_failure.791120405
Directory /workspace/16.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_smoke.2285848135
Short name T762
Test name
Test status
Simulation time 1759244424 ps
CPU time 9.43 seconds
Started Jun 11 02:13:21 PM PDT 24
Finished Jun 11 02:13:32 PM PDT 24
Peak memory 218244 kb
Host smart-82458784-c6d3-4c9d-aed3-a99e62c9ac71
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285848135 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_smoke
.2285848135
Directory /workspace/16.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_failure.2815028268
Short name T398
Test name
Test status
Simulation time 2586942206 ps
CPU time 50.31 seconds
Started Jun 11 02:13:25 PM PDT 24
Finished Jun 11 02:14:16 PM PDT 24
Peak memory 278352 kb
Host smart-0d65191c-3478-46ec-b897-167aa22859aa
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815028268 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jt
ag_state_failure.2815028268
Directory /workspace/16.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_post_trans.2264990001
Short name T215
Test name
Test status
Simulation time 2046262333 ps
CPU time 13.59 seconds
Started Jun 11 02:13:23 PM PDT 24
Finished Jun 11 02:13:38 PM PDT 24
Peak memory 226748 kb
Host smart-2f1b2445-36d1-4d7c-aeff-050f1b749a96
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264990001 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl
_jtag_state_post_trans.2264990001
Directory /workspace/16.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_prog_failure.1392965485
Short name T818
Test name
Test status
Simulation time 792507470 ps
CPU time 3.21 seconds
Started Jun 11 02:13:31 PM PDT 24
Finished Jun 11 02:13:35 PM PDT 24
Peak memory 218664 kb
Host smart-b618f949-cf34-4169-a1fc-5c8c98b4b946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1392965485 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_prog_failure.1392965485
Directory /workspace/16.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_mubi.2751329554
Short name T460
Test name
Test status
Simulation time 285121464 ps
CPU time 11.08 seconds
Started Jun 11 02:13:32 PM PDT 24
Finished Jun 11 02:13:44 PM PDT 24
Peak memory 218716 kb
Host smart-03774ad2-523d-44dd-b418-328c9e043ffe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751329554 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_mubi.2751329554
Directory /workspace/16.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_digest.2610377591
Short name T431
Test name
Test status
Simulation time 435164651 ps
CPU time 7.28 seconds
Started Jun 11 02:13:32 PM PDT 24
Finished Jun 11 02:13:41 PM PDT 24
Peak memory 218768 kb
Host smart-2d3802c8-9b42-4bbd-a0f5-ff88dafa4108
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610377591 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_d
igest.2610377591
Directory /workspace/16.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_mux.2659627843
Short name T637
Test name
Test status
Simulation time 247596035 ps
CPU time 7.96 seconds
Started Jun 11 02:13:24 PM PDT 24
Finished Jun 11 02:13:34 PM PDT 24
Peak memory 218704 kb
Host smart-3e51791a-965d-4fc8-b063-71daa0e91fcf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659627843 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_mux.
2659627843
Directory /workspace/16.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/16.lc_ctrl_security_escalation.2940692527
Short name T675
Test name
Test status
Simulation time 1979866666 ps
CPU time 11.15 seconds
Started Jun 11 02:13:25 PM PDT 24
Finished Jun 11 02:13:38 PM PDT 24
Peak memory 226472 kb
Host smart-a2381057-70ee-4d4f-a4c3-5ff0e41c0e77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940692527 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_security_escalation.2940692527
Directory /workspace/16.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/16.lc_ctrl_smoke.623751623
Short name T347
Test name
Test status
Simulation time 19044766 ps
CPU time 1.56 seconds
Started Jun 11 02:13:29 PM PDT 24
Finished Jun 11 02:13:31 PM PDT 24
Peak memory 214396 kb
Host smart-085ba5ba-44cc-4dbc-84aa-d76279f40092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623751623 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_smoke.623751623
Directory /workspace/16.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_failure.2946135504
Short name T255
Test name
Test status
Simulation time 948890604 ps
CPU time 22.59 seconds
Started Jun 11 02:13:22 PM PDT 24
Finished Jun 11 02:13:47 PM PDT 24
Peak memory 251384 kb
Host smart-715eac97-1044-44c1-a76a-ba25a2d9a17d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946135504 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_failure.2946135504
Directory /workspace/16.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_post_trans.3991611935
Short name T171
Test name
Test status
Simulation time 140369209 ps
CPU time 9.97 seconds
Started Jun 11 02:13:24 PM PDT 24
Finished Jun 11 02:13:36 PM PDT 24
Peak memory 251424 kb
Host smart-e721e172-ec8a-4441-90cd-b3dc5c6ca731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991611935 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_post_trans.3991611935
Directory /workspace/16.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_stress_all.1677765178
Short name T424
Test name
Test status
Simulation time 4468410958 ps
CPU time 79.63 seconds
Started Jun 11 02:13:30 PM PDT 24
Finished Jun 11 02:14:50 PM PDT 24
Peak memory 251396 kb
Host smart-8620ef46-331a-4c11-a9be-5db50592aa9e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677765178 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.lc_ctrl_stress_all.1677765178
Directory /workspace/16.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.lc_ctrl_stress_all_with_rand_reset.2834132870
Short name T138
Test name
Test status
Simulation time 273023853274 ps
CPU time 839.21 seconds
Started Jun 11 02:13:23 PM PDT 24
Finished Jun 11 02:27:24 PM PDT 24
Peak memory 356760 kb
Host smart-3b2d3e0d-9172-427f-9845-b084330599d7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2834132870 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_stress_all_with_rand_reset.2834132870
Directory /workspace/16.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.lc_ctrl_volatile_unlock_smoke.933847169
Short name T425
Test name
Test status
Simulation time 17035793 ps
CPU time 0.87 seconds
Started Jun 11 02:13:22 PM PDT 24
Finished Jun 11 02:13:26 PM PDT 24
Peak memory 209348 kb
Host smart-82c5fead-0eca-44c6-be4f-e7938c2d6855
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933847169 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ct
rl_volatile_unlock_smoke.933847169
Directory /workspace/16.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_alert_test.34591002
Short name T412
Test name
Test status
Simulation time 93224364 ps
CPU time 1.81 seconds
Started Jun 11 02:13:33 PM PDT 24
Finished Jun 11 02:13:37 PM PDT 24
Peak memory 209464 kb
Host smart-6a3bdd4a-3a6e-4e50-b43f-9efd186292b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34591002 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_alert_test.34591002
Directory /workspace/17.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.lc_ctrl_errors.4219970806
Short name T270
Test name
Test status
Simulation time 259877324 ps
CPU time 11.43 seconds
Started Jun 11 02:13:23 PM PDT 24
Finished Jun 11 02:13:36 PM PDT 24
Peak memory 218660 kb
Host smart-9c4545d4-a9d3-443c-b854-3c6754d1b74b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219970806 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_errors.4219970806
Directory /workspace/17.lc_ctrl_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_access.2339241060
Short name T23
Test name
Test status
Simulation time 2717208606 ps
CPU time 11.51 seconds
Started Jun 11 02:13:35 PM PDT 24
Finished Jun 11 02:13:48 PM PDT 24
Peak memory 217964 kb
Host smart-a6aa7e77-f52a-40b1-96b8-1bb7e2de81c3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339241060 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_access.2339241060
Directory /workspace/17.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_errors.1463861697
Short name T688
Test name
Test status
Simulation time 5793986049 ps
CPU time 45.6 seconds
Started Jun 11 02:13:36 PM PDT 24
Finished Jun 11 02:14:24 PM PDT 24
Peak memory 219356 kb
Host smart-b99b36db-7ef6-4ed2-884c-c19d5a7e52fb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463861697 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_e
rrors.1463861697
Directory /workspace/17.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_prog_failure.535157423
Short name T234
Test name
Test status
Simulation time 70284409 ps
CPU time 3.09 seconds
Started Jun 11 02:13:36 PM PDT 24
Finished Jun 11 02:13:41 PM PDT 24
Peak memory 218964 kb
Host smart-b1d0b68a-7f02-471b-9980-d54421764d3f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535157423 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag
_prog_failure.535157423
Directory /workspace/17.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_smoke.2919250093
Short name T760
Test name
Test status
Simulation time 100818736 ps
CPU time 2.9 seconds
Started Jun 11 02:13:22 PM PDT 24
Finished Jun 11 02:13:26 PM PDT 24
Peak memory 218180 kb
Host smart-81386b9a-297d-43a6-b31a-a2197e98e2dc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919250093 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_smoke
.2919250093
Directory /workspace/17.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_failure.2302889946
Short name T832
Test name
Test status
Simulation time 1624259971 ps
CPU time 60.6 seconds
Started Jun 11 02:13:22 PM PDT 24
Finished Jun 11 02:14:25 PM PDT 24
Peak memory 273448 kb
Host smart-a596a147-3fee-4950-b089-71e48f71a778
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302889946 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jt
ag_state_failure.2302889946
Directory /workspace/17.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_post_trans.2375326608
Short name T308
Test name
Test status
Simulation time 1176673931 ps
CPU time 7.39 seconds
Started Jun 11 02:13:30 PM PDT 24
Finished Jun 11 02:13:39 PM PDT 24
Peak memory 223460 kb
Host smart-7cf54079-d1de-4af1-b1bf-d10bdec33dad
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375326608 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl
_jtag_state_post_trans.2375326608
Directory /workspace/17.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_prog_failure.1940283035
Short name T827
Test name
Test status
Simulation time 46751919 ps
CPU time 2.15 seconds
Started Jun 11 02:13:24 PM PDT 24
Finished Jun 11 02:13:28 PM PDT 24
Peak memory 218676 kb
Host smart-2eed8587-2330-42a8-be8e-dbfb92f4e3b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940283035 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_prog_failure.1940283035
Directory /workspace/17.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_mubi.2007835319
Short name T345
Test name
Test status
Simulation time 1825288211 ps
CPU time 18.91 seconds
Started Jun 11 02:13:34 PM PDT 24
Finished Jun 11 02:13:55 PM PDT 24
Peak memory 226532 kb
Host smart-bf1e03a9-eeac-4d90-8fa4-d7e2aeb071ed
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007835319 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_mubi.2007835319
Directory /workspace/17.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_digest.2987430621
Short name T272
Test name
Test status
Simulation time 389083065 ps
CPU time 14.83 seconds
Started Jun 11 02:13:36 PM PDT 24
Finished Jun 11 02:13:53 PM PDT 24
Peak memory 218712 kb
Host smart-9836b3a2-bb00-4de9-acc9-869d04915f6b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987430621 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_d
igest.2987430621
Directory /workspace/17.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_mux.523883765
Short name T861
Test name
Test status
Simulation time 321600987 ps
CPU time 7.24 seconds
Started Jun 11 02:13:35 PM PDT 24
Finished Jun 11 02:13:44 PM PDT 24
Peak memory 218668 kb
Host smart-c115e270-aa06-47b3-8d39-a2408b4bc049
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523883765 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_mux.523883765
Directory /workspace/17.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/17.lc_ctrl_security_escalation.748897903
Short name T51
Test name
Test status
Simulation time 866338158 ps
CPU time 15.38 seconds
Started Jun 11 02:13:22 PM PDT 24
Finished Jun 11 02:13:40 PM PDT 24
Peak memory 226440 kb
Host smart-79cfd727-70e5-40da-8a59-7c378b9a8025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748897903 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_security_escalation.748897903
Directory /workspace/17.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/17.lc_ctrl_smoke.2429125836
Short name T479
Test name
Test status
Simulation time 51878657 ps
CPU time 1.79 seconds
Started Jun 11 02:13:31 PM PDT 24
Finished Jun 11 02:13:35 PM PDT 24
Peak memory 214492 kb
Host smart-b66efaa3-39e3-4c02-874c-df28bd405cbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429125836 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_smoke.2429125836
Directory /workspace/17.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_failure.716019879
Short name T639
Test name
Test status
Simulation time 1182065877 ps
CPU time 28.06 seconds
Started Jun 11 02:13:21 PM PDT 24
Finished Jun 11 02:13:50 PM PDT 24
Peak memory 251396 kb
Host smart-1ba761ff-124c-4024-8d5d-234e8f2789f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716019879 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_failure.716019879
Directory /workspace/17.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_post_trans.3986545163
Short name T321
Test name
Test status
Simulation time 150804042 ps
CPU time 2.81 seconds
Started Jun 11 02:13:22 PM PDT 24
Finished Jun 11 02:13:27 PM PDT 24
Peak memory 222260 kb
Host smart-626f9745-6679-42b6-8698-88f2f1f8f049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986545163 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_post_trans.3986545163
Directory /workspace/17.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all.2216150580
Short name T662
Test name
Test status
Simulation time 49979041157 ps
CPU time 178.23 seconds
Started Jun 11 02:13:33 PM PDT 24
Finished Jun 11 02:16:33 PM PDT 24
Peak memory 270912 kb
Host smart-b7cd0250-019e-4285-9cd4-db818f16ef96
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216150580 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.lc_ctrl_stress_all.2216150580
Directory /workspace/17.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.lc_ctrl_volatile_unlock_smoke.312133147
Short name T521
Test name
Test status
Simulation time 40247005 ps
CPU time 0.99 seconds
Started Jun 11 02:13:22 PM PDT 24
Finished Jun 11 02:13:25 PM PDT 24
Peak memory 213660 kb
Host smart-a0bacf92-29c9-4f71-99dd-50fd3fccbdfb
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312133147 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ct
rl_volatile_unlock_smoke.312133147
Directory /workspace/17.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_alert_test.3353789484
Short name T733
Test name
Test status
Simulation time 24619478 ps
CPU time 1.27 seconds
Started Jun 11 02:13:33 PM PDT 24
Finished Jun 11 02:13:36 PM PDT 24
Peak memory 209504 kb
Host smart-489361e1-4716-48bd-931f-3481ee8e390e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353789484 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_alert_test.3353789484
Directory /workspace/18.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.lc_ctrl_errors.2283979806
Short name T305
Test name
Test status
Simulation time 1336112623 ps
CPU time 15.57 seconds
Started Jun 11 02:13:36 PM PDT 24
Finished Jun 11 02:13:53 PM PDT 24
Peak memory 218592 kb
Host smart-e32edf09-bef8-4b25-a220-6a72bcd2a75e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283979806 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_errors.2283979806
Directory /workspace/18.lc_ctrl_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_access.291116716
Short name T594
Test name
Test status
Simulation time 748240501 ps
CPU time 7.64 seconds
Started Jun 11 02:13:36 PM PDT 24
Finished Jun 11 02:13:46 PM PDT 24
Peak memory 217580 kb
Host smart-49f0bc7d-c2ec-4a43-b41a-c3fc8c2dc775
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291116716 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_access.291116716
Directory /workspace/18.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_errors.1878776894
Short name T154
Test name
Test status
Simulation time 6620824118 ps
CPU time 43.16 seconds
Started Jun 11 02:13:33 PM PDT 24
Finished Jun 11 02:14:18 PM PDT 24
Peak memory 218760 kb
Host smart-d9d44e55-e604-4b43-b728-39137256fc13
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878776894 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_e
rrors.1878776894
Directory /workspace/18.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_prog_failure.4272899012
Short name T217
Test name
Test status
Simulation time 269872949 ps
CPU time 5.01 seconds
Started Jun 11 02:13:32 PM PDT 24
Finished Jun 11 02:13:39 PM PDT 24
Peak memory 218696 kb
Host smart-c20de6f7-d79a-4266-8acb-26b3b1da230d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272899012 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jta
g_prog_failure.4272899012
Directory /workspace/18.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_smoke.2268028681
Short name T854
Test name
Test status
Simulation time 646510387 ps
CPU time 5.32 seconds
Started Jun 11 02:13:32 PM PDT 24
Finished Jun 11 02:13:39 PM PDT 24
Peak memory 218216 kb
Host smart-89999083-80b7-416e-9d3f-fe78d3091a2a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268028681 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_smoke
.2268028681
Directory /workspace/18.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_failure.2378777146
Short name T19
Test name
Test status
Simulation time 5272688418 ps
CPU time 70.44 seconds
Started Jun 11 02:13:35 PM PDT 24
Finished Jun 11 02:14:48 PM PDT 24
Peak memory 284208 kb
Host smart-4d3f1e4a-c401-41dc-b246-e603ae953ad4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378777146 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jt
ag_state_failure.2378777146
Directory /workspace/18.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_post_trans.2115044184
Short name T780
Test name
Test status
Simulation time 1716055624 ps
CPU time 12.86 seconds
Started Jun 11 02:13:33 PM PDT 24
Finished Jun 11 02:13:47 PM PDT 24
Peak memory 251364 kb
Host smart-9d2cec70-ce38-4ff5-8b63-6f7b66080b65
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115044184 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl
_jtag_state_post_trans.2115044184
Directory /workspace/18.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_prog_failure.3239553240
Short name T450
Test name
Test status
Simulation time 64584431 ps
CPU time 2.93 seconds
Started Jun 11 02:13:36 PM PDT 24
Finished Jun 11 02:13:41 PM PDT 24
Peak memory 222872 kb
Host smart-4ff876fd-f413-4252-bacd-e39583bcc652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239553240 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_prog_failure.3239553240
Directory /workspace/18.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_mubi.2771757654
Short name T474
Test name
Test status
Simulation time 3921768102 ps
CPU time 8.97 seconds
Started Jun 11 02:13:36 PM PDT 24
Finished Jun 11 02:13:47 PM PDT 24
Peak memory 220492 kb
Host smart-fe00bbb0-f43c-4500-9f5c-011c7fa6b5e9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771757654 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_mubi.2771757654
Directory /workspace/18.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_digest.3260693619
Short name T440
Test name
Test status
Simulation time 206395365 ps
CPU time 9.15 seconds
Started Jun 11 02:13:33 PM PDT 24
Finished Jun 11 02:13:44 PM PDT 24
Peak memory 218732 kb
Host smart-c33ee239-e566-4088-bea3-5359f754e84b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260693619 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_d
igest.3260693619
Directory /workspace/18.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_mux.2818538140
Short name T855
Test name
Test status
Simulation time 276010786 ps
CPU time 10.78 seconds
Started Jun 11 02:13:35 PM PDT 24
Finished Jun 11 02:13:48 PM PDT 24
Peak memory 218732 kb
Host smart-08ddc470-b3c9-4e16-bacb-310bd94b3fa5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818538140 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_mux.
2818538140
Directory /workspace/18.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/18.lc_ctrl_security_escalation.2602183471
Short name T306
Test name
Test status
Simulation time 1625618987 ps
CPU time 11.32 seconds
Started Jun 11 02:13:36 PM PDT 24
Finished Jun 11 02:13:50 PM PDT 24
Peak memory 226608 kb
Host smart-6405d3c0-6579-4a9a-b39b-882ae36cc4f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602183471 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_security_escalation.2602183471
Directory /workspace/18.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/18.lc_ctrl_smoke.375749977
Short name T600
Test name
Test status
Simulation time 708572687 ps
CPU time 2.82 seconds
Started Jun 11 02:13:36 PM PDT 24
Finished Jun 11 02:13:40 PM PDT 24
Peak memory 215004 kb
Host smart-4c86576c-b6b8-4e99-a3db-409a40516162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375749977 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_smoke.375749977
Directory /workspace/18.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_failure.1631827994
Short name T615
Test name
Test status
Simulation time 3241516988 ps
CPU time 27.88 seconds
Started Jun 11 02:13:33 PM PDT 24
Finished Jun 11 02:14:03 PM PDT 24
Peak memory 251456 kb
Host smart-4fab4fb8-fa40-468b-a405-3aa353841495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631827994 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_failure.1631827994
Directory /workspace/18.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_post_trans.2829539802
Short name T645
Test name
Test status
Simulation time 74569563 ps
CPU time 8.35 seconds
Started Jun 11 02:13:35 PM PDT 24
Finished Jun 11 02:13:46 PM PDT 24
Peak memory 251352 kb
Host smart-d257a13a-acff-4c62-88d2-ddd57a8f2551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829539802 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_post_trans.2829539802
Directory /workspace/18.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all.3647560778
Short name T90
Test name
Test status
Simulation time 36774476217 ps
CPU time 194.78 seconds
Started Jun 11 02:13:35 PM PDT 24
Finished Jun 11 02:16:52 PM PDT 24
Peak memory 275828 kb
Host smart-4046097a-9c53-4006-a334-ec6ad02f393d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647560778 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.lc_ctrl_stress_all.3647560778
Directory /workspace/18.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.lc_ctrl_volatile_unlock_smoke.243876762
Short name T634
Test name
Test status
Simulation time 16243307 ps
CPU time 0.82 seconds
Started Jun 11 02:13:36 PM PDT 24
Finished Jun 11 02:13:39 PM PDT 24
Peak memory 209300 kb
Host smart-1799a38b-5a5a-4de5-afda-1e9c87da4fc0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243876762 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ct
rl_volatile_unlock_smoke.243876762
Directory /workspace/18.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_alert_test.847358515
Short name T666
Test name
Test status
Simulation time 47024061 ps
CPU time 1.08 seconds
Started Jun 11 02:13:46 PM PDT 24
Finished Jun 11 02:13:49 PM PDT 24
Peak memory 209260 kb
Host smart-053ac4f9-5e8a-4924-ab0c-95db4fb7f69b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847358515 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_alert_test.847358515
Directory /workspace/19.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.lc_ctrl_errors.2187222383
Short name T532
Test name
Test status
Simulation time 442523310 ps
CPU time 15.16 seconds
Started Jun 11 02:13:33 PM PDT 24
Finished Jun 11 02:13:51 PM PDT 24
Peak memory 218804 kb
Host smart-470e9590-858d-4fa0-aeff-105f9373d27d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187222383 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_errors.2187222383
Directory /workspace/19.lc_ctrl_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_access.2521582639
Short name T642
Test name
Test status
Simulation time 355214158 ps
CPU time 5.15 seconds
Started Jun 11 02:13:33 PM PDT 24
Finished Jun 11 02:13:40 PM PDT 24
Peak memory 217684 kb
Host smart-a5b400ad-e7c5-4dea-86a9-b37b55c30e11
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521582639 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_access.2521582639
Directory /workspace/19.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_errors.2417553688
Short name T659
Test name
Test status
Simulation time 7076729482 ps
CPU time 46.73 seconds
Started Jun 11 02:13:33 PM PDT 24
Finished Jun 11 02:14:22 PM PDT 24
Peak memory 219476 kb
Host smart-bf5e8bf4-0e52-4d1f-a5ef-9c6400a10d3e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417553688 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_e
rrors.2417553688
Directory /workspace/19.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_prog_failure.3350393167
Short name T784
Test name
Test status
Simulation time 739790037 ps
CPU time 6.76 seconds
Started Jun 11 02:13:34 PM PDT 24
Finished Jun 11 02:13:43 PM PDT 24
Peak memory 218700 kb
Host smart-d3a89d69-e1e5-43d9-bf82-5eb439b6fbca
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350393167 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jta
g_prog_failure.3350393167
Directory /workspace/19.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_smoke.2432443351
Short name T492
Test name
Test status
Simulation time 306445533 ps
CPU time 8.91 seconds
Started Jun 11 02:13:35 PM PDT 24
Finished Jun 11 02:13:46 PM PDT 24
Peak memory 218212 kb
Host smart-9115c061-5f2c-417f-ae65-cb311be1f165
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432443351 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_smoke
.2432443351
Directory /workspace/19.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_failure.2168799185
Short name T328
Test name
Test status
Simulation time 4689050334 ps
CPU time 39.03 seconds
Started Jun 11 02:13:34 PM PDT 24
Finished Jun 11 02:14:16 PM PDT 24
Peak memory 267980 kb
Host smart-37e52238-984d-4ef5-bb51-f6acb94dd08c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168799185 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jt
ag_state_failure.2168799185
Directory /workspace/19.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_post_trans.1940347297
Short name T700
Test name
Test status
Simulation time 290028364 ps
CPU time 11.72 seconds
Started Jun 11 02:13:35 PM PDT 24
Finished Jun 11 02:13:49 PM PDT 24
Peak memory 251432 kb
Host smart-9f639135-6b99-4058-ab28-ce18be821695
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940347297 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl
_jtag_state_post_trans.1940347297
Directory /workspace/19.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_prog_failure.769776626
Short name T310
Test name
Test status
Simulation time 40269851 ps
CPU time 1.86 seconds
Started Jun 11 02:13:36 PM PDT 24
Finished Jun 11 02:13:40 PM PDT 24
Peak memory 218684 kb
Host smart-879f5475-3c1f-4e8c-96b7-2f9ec7cf0b8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769776626 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_prog_failure.769776626
Directory /workspace/19.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_mubi.3591486646
Short name T737
Test name
Test status
Simulation time 1871540799 ps
CPU time 10.61 seconds
Started Jun 11 02:13:33 PM PDT 24
Finished Jun 11 02:13:46 PM PDT 24
Peak memory 219472 kb
Host smart-19de0098-8cdd-4a25-9e0c-01fdf06537c5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591486646 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_mubi.3591486646
Directory /workspace/19.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_digest.3312518171
Short name T258
Test name
Test status
Simulation time 1432986247 ps
CPU time 12.5 seconds
Started Jun 11 02:13:35 PM PDT 24
Finished Jun 11 02:13:50 PM PDT 24
Peak memory 218712 kb
Host smart-8a910284-74f9-4a8f-a210-22ebe55d9e91
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312518171 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_d
igest.3312518171
Directory /workspace/19.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_mux.3708125007
Short name T394
Test name
Test status
Simulation time 309040736 ps
CPU time 7.33 seconds
Started Jun 11 02:13:35 PM PDT 24
Finished Jun 11 02:13:44 PM PDT 24
Peak memory 225508 kb
Host smart-a5aa3fef-00a8-4775-af18-836ebdfd6e80
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708125007 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_mux.
3708125007
Directory /workspace/19.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/19.lc_ctrl_security_escalation.2180602964
Short name T701
Test name
Test status
Simulation time 1075675570 ps
CPU time 7.04 seconds
Started Jun 11 02:13:36 PM PDT 24
Finished Jun 11 02:13:45 PM PDT 24
Peak memory 226504 kb
Host smart-263ff5c2-dcd8-47f7-b811-338f4979e9b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180602964 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_security_escalation.2180602964
Directory /workspace/19.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/19.lc_ctrl_smoke.792038456
Short name T846
Test name
Test status
Simulation time 26122262 ps
CPU time 1.37 seconds
Started Jun 11 02:13:34 PM PDT 24
Finished Jun 11 02:13:38 PM PDT 24
Peak memory 214156 kb
Host smart-5d77cab6-8c0b-4b70-900c-dc04f9b10cb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792038456 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_smoke.792038456
Directory /workspace/19.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_failure.4232548583
Short name T339
Test name
Test status
Simulation time 199805793 ps
CPU time 21.35 seconds
Started Jun 11 02:13:38 PM PDT 24
Finished Jun 11 02:14:01 PM PDT 24
Peak memory 251456 kb
Host smart-fb7a795b-474b-4674-a7e9-1e6471e9ac27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232548583 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_failure.4232548583
Directory /workspace/19.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_post_trans.173984969
Short name T14
Test name
Test status
Simulation time 194100141 ps
CPU time 2.57 seconds
Started Jun 11 02:13:33 PM PDT 24
Finished Jun 11 02:13:38 PM PDT 24
Peak memory 224660 kb
Host smart-9b17630c-8d26-472a-bc79-fcaae5fb437b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173984969 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_post_trans.173984969
Directory /workspace/19.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all.2930904613
Short name T835
Test name
Test status
Simulation time 16514215678 ps
CPU time 540.71 seconds
Started Jun 11 02:13:36 PM PDT 24
Finished Jun 11 02:22:39 PM PDT 24
Peak memory 251548 kb
Host smart-48095e40-035a-4c25-bd93-868630a91c0c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930904613 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.lc_ctrl_stress_all.2930904613
Directory /workspace/19.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.lc_ctrl_volatile_unlock_smoke.1551448655
Short name T349
Test name
Test status
Simulation time 14950715 ps
CPU time 0.94 seconds
Started Jun 11 02:13:35 PM PDT 24
Finished Jun 11 02:13:38 PM PDT 24
Peak memory 212436 kb
Host smart-149cce5f-7313-4e9f-ae10-ca1b4c8d4b87
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551448655 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_c
trl_volatile_unlock_smoke.1551448655
Directory /workspace/19.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_alert_test.4189063731
Short name T481
Test name
Test status
Simulation time 26933354 ps
CPU time 1.08 seconds
Started Jun 11 02:12:45 PM PDT 24
Finished Jun 11 02:12:48 PM PDT 24
Peak memory 209464 kb
Host smart-30407e6d-56b9-4b29-8818-99ef610d47ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189063731 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_alert_test.4189063731
Directory /workspace/2.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.lc_ctrl_claim_transition_if.2218920642
Short name T564
Test name
Test status
Simulation time 17240156 ps
CPU time 0.78 seconds
Started Jun 11 02:12:32 PM PDT 24
Finished Jun 11 02:12:34 PM PDT 24
Peak memory 209508 kb
Host smart-0fd09826-7670-411f-bcdf-430ca5bced23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218920642 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_claim_transition_if.2218920642
Directory /workspace/2.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/2.lc_ctrl_errors.2856162577
Short name T599
Test name
Test status
Simulation time 2495042291 ps
CPU time 12.36 seconds
Started Jun 11 02:12:30 PM PDT 24
Finished Jun 11 02:12:44 PM PDT 24
Peak memory 219432 kb
Host smart-81946e8c-fa15-42d2-a84d-488da57939da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856162577 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_errors.2856162577
Directory /workspace/2.lc_ctrl_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_access.4082019709
Short name T28
Test name
Test status
Simulation time 491332661 ps
CPU time 13.03 seconds
Started Jun 11 02:12:32 PM PDT 24
Finished Jun 11 02:12:46 PM PDT 24
Peak memory 217628 kb
Host smart-50d89f39-1ecd-4cab-9493-37d6692b8c1a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082019709 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_access.4082019709
Directory /workspace/2.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_errors.528731613
Short name T163
Test name
Test status
Simulation time 5524626182 ps
CPU time 22.84 seconds
Started Jun 11 02:12:30 PM PDT 24
Finished Jun 11 02:12:55 PM PDT 24
Peak memory 219444 kb
Host smart-6f67893d-75ab-47d2-9d5c-1616f10ed446
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528731613 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_err
ors.528731613
Directory /workspace/2.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_priority.3957014935
Short name T470
Test name
Test status
Simulation time 278031691 ps
CPU time 7.38 seconds
Started Jun 11 02:12:30 PM PDT 24
Finished Jun 11 02:12:39 PM PDT 24
Peak memory 217824 kb
Host smart-7b7392a7-3d80-45b6-a580-3e2067711b2b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957014935 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_priority.3
957014935
Directory /workspace/2.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_prog_failure.4268935631
Short name T552
Test name
Test status
Simulation time 292462846 ps
CPU time 8.59 seconds
Started Jun 11 02:12:31 PM PDT 24
Finished Jun 11 02:12:41 PM PDT 24
Peak memory 218908 kb
Host smart-13055ac5-503a-45f4-b484-63f09876748e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268935631 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag
_prog_failure.4268935631
Directory /workspace/2.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_regwen_during_op.1921759969
Short name T557
Test name
Test status
Simulation time 5424223360 ps
CPU time 19.48 seconds
Started Jun 11 02:12:30 PM PDT 24
Finished Jun 11 02:12:51 PM PDT 24
Peak memory 218268 kb
Host smart-6aba9190-7745-4013-aba0-8c4111b5c4ae
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921759969 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_regwen_during_op.1921759969
Directory /workspace/2.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_smoke.3474209443
Short name T661
Test name
Test status
Simulation time 133895004 ps
CPU time 2.4 seconds
Started Jun 11 02:12:31 PM PDT 24
Finished Jun 11 02:12:35 PM PDT 24
Peak memory 218260 kb
Host smart-22ec50d1-d8ef-41f2-9d57-6354b424cd1f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474209443 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_smoke.
3474209443
Directory /workspace/2.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_failure.4148693861
Short name T849
Test name
Test status
Simulation time 2220991195 ps
CPU time 79.66 seconds
Started Jun 11 02:12:30 PM PDT 24
Finished Jun 11 02:13:51 PM PDT 24
Peak memory 268596 kb
Host smart-8c41cf08-c036-4be0-800a-ba98a8bd106f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148693861 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jta
g_state_failure.4148693861
Directory /workspace/2.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_post_trans.3651407749
Short name T324
Test name
Test status
Simulation time 332717127 ps
CPU time 11.74 seconds
Started Jun 11 02:12:29 PM PDT 24
Finished Jun 11 02:12:42 PM PDT 24
Peak memory 251340 kb
Host smart-08f86cf4-f71d-4b61-bc51-8be92842c3e9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651407749 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_state_post_trans.3651407749
Directory /workspace/2.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_prog_failure.1877202177
Short name T631
Test name
Test status
Simulation time 124500636 ps
CPU time 3.16 seconds
Started Jun 11 02:12:30 PM PDT 24
Finished Jun 11 02:12:35 PM PDT 24
Peak memory 222892 kb
Host smart-3e5641e5-ef7d-46c9-8334-abf5fd532e09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877202177 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_prog_failure.1877202177
Directory /workspace/2.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_regwen_during_op.2514444201
Short name T434
Test name
Test status
Simulation time 781221676 ps
CPU time 7.24 seconds
Started Jun 11 02:12:29 PM PDT 24
Finished Jun 11 02:12:38 PM PDT 24
Peak memory 218204 kb
Host smart-f825e026-59ec-468e-bbc1-a4d0c148a4ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514444201 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_regwen_during_op.2514444201
Directory /workspace/2.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_cm.2539133052
Short name T87
Test name
Test status
Simulation time 126045560 ps
CPU time 23.94 seconds
Started Jun 11 02:12:43 PM PDT 24
Finished Jun 11 02:13:09 PM PDT 24
Peak memory 282948 kb
Host smart-cf4468ba-c7bf-41a2-a39f-b81cc829bf5b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539133052 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_cm.2539133052
Directory /workspace/2.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_mubi.1581382700
Short name T623
Test name
Test status
Simulation time 452434665 ps
CPU time 11.64 seconds
Started Jun 11 02:12:47 PM PDT 24
Finished Jun 11 02:13:00 PM PDT 24
Peak memory 226504 kb
Host smart-fedb9740-b78b-47a7-9248-f7c0c8474938
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581382700 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_mubi.1581382700
Directory /workspace/2.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_digest.185121733
Short name T372
Test name
Test status
Simulation time 377651352 ps
CPU time 9.62 seconds
Started Jun 11 02:12:41 PM PDT 24
Finished Jun 11 02:12:52 PM PDT 24
Peak memory 226504 kb
Host smart-57e133c7-0707-4bf5-a961-dfb8cb08f293
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185121733 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_dig
est.185121733
Directory /workspace/2.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_mux.2247224701
Short name T816
Test name
Test status
Simulation time 277176458 ps
CPU time 10.24 seconds
Started Jun 11 02:12:46 PM PDT 24
Finished Jun 11 02:12:58 PM PDT 24
Peak memory 226504 kb
Host smart-2384a7b6-0363-4cc7-b328-6142290d88c9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247224701 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_mux.2
247224701
Directory /workspace/2.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/2.lc_ctrl_security_escalation.1532257437
Short name T212
Test name
Test status
Simulation time 341793538 ps
CPU time 7.91 seconds
Started Jun 11 02:12:30 PM PDT 24
Finished Jun 11 02:12:40 PM PDT 24
Peak memory 218736 kb
Host smart-f6229f8d-a7b2-4e0d-8efd-dd30f036c3df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532257437 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_security_escalation.1532257437
Directory /workspace/2.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/2.lc_ctrl_smoke.3373935489
Short name T545
Test name
Test status
Simulation time 43143677 ps
CPU time 1.04 seconds
Started Jun 11 02:12:29 PM PDT 24
Finished Jun 11 02:12:31 PM PDT 24
Peak memory 218240 kb
Host smart-842b545f-1ac8-4fd7-b1c6-7887c30acb24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373935489 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_smoke.3373935489
Directory /workspace/2.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_failure.2149640520
Short name T229
Test name
Test status
Simulation time 896520117 ps
CPU time 27.45 seconds
Started Jun 11 02:12:31 PM PDT 24
Finished Jun 11 02:13:00 PM PDT 24
Peak memory 251356 kb
Host smart-119caafb-08f0-4fe0-a7ff-bcd2d6a9fc62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149640520 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_failure.2149640520
Directory /workspace/2.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_post_trans.1860050598
Short name T654
Test name
Test status
Simulation time 259440584 ps
CPU time 3.92 seconds
Started Jun 11 02:12:32 PM PDT 24
Finished Jun 11 02:12:37 PM PDT 24
Peak memory 222616 kb
Host smart-376e2a69-00bc-4d54-b4b9-086621dfb8a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860050598 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_post_trans.1860050598
Directory /workspace/2.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all.1535477493
Short name T463
Test name
Test status
Simulation time 5628804726 ps
CPU time 197.22 seconds
Started Jun 11 02:12:43 PM PDT 24
Finished Jun 11 02:16:02 PM PDT 24
Peak memory 284268 kb
Host smart-c8b39e14-2fea-4a3c-9f9a-0b9ddc86e9a7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535477493 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.lc_ctrl_stress_all.1535477493
Directory /workspace/2.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.lc_ctrl_volatile_unlock_smoke.3525090165
Short name T309
Test name
Test status
Simulation time 46938354 ps
CPU time 0.96 seconds
Started Jun 11 02:12:31 PM PDT 24
Finished Jun 11 02:12:34 PM PDT 24
Peak memory 209388 kb
Host smart-1426c933-d289-4792-9990-2196eb04d846
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525090165 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ct
rl_volatile_unlock_smoke.3525090165
Directory /workspace/2.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_alert_test.3671653000
Short name T236
Test name
Test status
Simulation time 205829473 ps
CPU time 0.9 seconds
Started Jun 11 02:13:48 PM PDT 24
Finished Jun 11 02:13:51 PM PDT 24
Peak memory 209408 kb
Host smart-7a814225-e375-4d01-a65f-82046be494a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671653000 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_alert_test.3671653000
Directory /workspace/20.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.lc_ctrl_errors.1588908672
Short name T169
Test name
Test status
Simulation time 1372006492 ps
CPU time 12.84 seconds
Started Jun 11 02:13:47 PM PDT 24
Finished Jun 11 02:14:01 PM PDT 24
Peak memory 218716 kb
Host smart-13a01c80-a5c6-4b57-83c9-7ce176b6e576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588908672 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_errors.1588908672
Directory /workspace/20.lc_ctrl_errors/latest

Test location /workspace/coverage/default/20.lc_ctrl_jtag_access.1412740237
Short name T353
Test name
Test status
Simulation time 154640275 ps
CPU time 4.76 seconds
Started Jun 11 02:13:46 PM PDT 24
Finished Jun 11 02:13:52 PM PDT 24
Peak memory 217556 kb
Host smart-ec13992b-6afe-4e49-97c8-fb932b22b0df
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412740237 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_jtag_access.1412740237
Directory /workspace/20.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/20.lc_ctrl_prog_failure.369212199
Short name T466
Test name
Test status
Simulation time 746685184 ps
CPU time 3.89 seconds
Started Jun 11 02:13:48 PM PDT 24
Finished Jun 11 02:13:54 PM PDT 24
Peak memory 218596 kb
Host smart-a7cdc132-1477-4969-be6e-0e12d354203c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369212199 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_prog_failure.369212199
Directory /workspace/20.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_mubi.2368075467
Short name T445
Test name
Test status
Simulation time 675077556 ps
CPU time 11.13 seconds
Started Jun 11 02:13:50 PM PDT 24
Finished Jun 11 02:14:03 PM PDT 24
Peak memory 219404 kb
Host smart-3c1c4cbb-9d83-4e33-af56-1d6dd8ac6e11
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368075467 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_mubi.2368075467
Directory /workspace/20.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_digest.2287947975
Short name T407
Test name
Test status
Simulation time 402557737 ps
CPU time 15.88 seconds
Started Jun 11 02:13:49 PM PDT 24
Finished Jun 11 02:14:06 PM PDT 24
Peak memory 226532 kb
Host smart-4e404373-40ec-46c3-b21b-b52323428bb4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287947975 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_d
igest.2287947975
Directory /workspace/20.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_mux.2320903356
Short name T259
Test name
Test status
Simulation time 274185473 ps
CPU time 6.85 seconds
Started Jun 11 02:13:50 PM PDT 24
Finished Jun 11 02:13:58 PM PDT 24
Peak memory 218684 kb
Host smart-779e512c-1369-4859-b232-c0ea1e5f9e22
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320903356 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_mux.
2320903356
Directory /workspace/20.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/20.lc_ctrl_security_escalation.3192477098
Short name T159
Test name
Test status
Simulation time 780898875 ps
CPU time 6.76 seconds
Started Jun 11 02:13:48 PM PDT 24
Finished Jun 11 02:13:56 PM PDT 24
Peak memory 218684 kb
Host smart-a05a3e60-5495-427a-82e0-eb60309839fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192477098 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_security_escalation.3192477098
Directory /workspace/20.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/20.lc_ctrl_smoke.2699495556
Short name T721
Test name
Test status
Simulation time 32781836 ps
CPU time 1.62 seconds
Started Jun 11 02:13:47 PM PDT 24
Finished Jun 11 02:13:50 PM PDT 24
Peak memory 214368 kb
Host smart-0413dd06-66ef-4a15-91d3-32436bed1c7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699495556 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_smoke.2699495556
Directory /workspace/20.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_failure.662888239
Short name T534
Test name
Test status
Simulation time 872983190 ps
CPU time 23.2 seconds
Started Jun 11 02:13:49 PM PDT 24
Finished Jun 11 02:14:14 PM PDT 24
Peak memory 251412 kb
Host smart-2c906ff4-0396-46c3-8695-0959aff1e90a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662888239 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_failure.662888239
Directory /workspace/20.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_post_trans.1320641815
Short name T655
Test name
Test status
Simulation time 48058413 ps
CPU time 7.27 seconds
Started Jun 11 02:13:45 PM PDT 24
Finished Jun 11 02:13:54 PM PDT 24
Peak memory 251332 kb
Host smart-b98d3b80-207a-467e-913f-6ea1e52fdc1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320641815 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_post_trans.1320641815
Directory /workspace/20.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/20.lc_ctrl_stress_all.940835310
Short name T858
Test name
Test status
Simulation time 8888832075 ps
CPU time 240.44 seconds
Started Jun 11 02:13:54 PM PDT 24
Finished Jun 11 02:17:56 PM PDT 24
Peak memory 259540 kb
Host smart-1e081e82-8599-4796-83d0-7f25c996cae8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940835310 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.lc_ctrl_stress_all.940835310
Directory /workspace/20.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.lc_ctrl_stress_all_with_rand_reset.2855719409
Short name T137
Test name
Test status
Simulation time 23348428886 ps
CPU time 828.19 seconds
Started Jun 11 02:13:48 PM PDT 24
Finished Jun 11 02:27:38 PM PDT 24
Peak memory 333072 kb
Host smart-43244014-6032-4838-97b7-f171c55c5484
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2855719409 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_stress_all_with_rand_reset.2855719409
Directory /workspace/20.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.lc_ctrl_volatile_unlock_smoke.1089500924
Short name T343
Test name
Test status
Simulation time 42372084 ps
CPU time 0.95 seconds
Started Jun 11 02:13:45 PM PDT 24
Finished Jun 11 02:13:48 PM PDT 24
Peak memory 212224 kb
Host smart-8f2f6031-47fb-40ca-89a2-65c2e5ae756b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089500924 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_c
trl_volatile_unlock_smoke.1089500924
Directory /workspace/20.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_alert_test.1589566842
Short name T227
Test name
Test status
Simulation time 471574311 ps
CPU time 1.3 seconds
Started Jun 11 02:13:47 PM PDT 24
Finished Jun 11 02:13:50 PM PDT 24
Peak memory 209476 kb
Host smart-00c209f4-3ed6-4569-8890-1bc258b473bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589566842 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_alert_test.1589566842
Directory /workspace/21.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.lc_ctrl_errors.3560170839
Short name T811
Test name
Test status
Simulation time 163383362 ps
CPU time 8.79 seconds
Started Jun 11 02:13:47 PM PDT 24
Finished Jun 11 02:13:57 PM PDT 24
Peak memory 218592 kb
Host smart-0310bba7-adde-47d1-b67f-352f89385585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560170839 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_errors.3560170839
Directory /workspace/21.lc_ctrl_errors/latest

Test location /workspace/coverage/default/21.lc_ctrl_jtag_access.1952318131
Short name T330
Test name
Test status
Simulation time 850331807 ps
CPU time 11.58 seconds
Started Jun 11 02:13:46 PM PDT 24
Finished Jun 11 02:13:59 PM PDT 24
Peak memory 217948 kb
Host smart-6b76489e-9636-4b99-a3ce-20a5f28b53ac
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952318131 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_jtag_access.1952318131
Directory /workspace/21.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/21.lc_ctrl_prog_failure.1295232495
Short name T778
Test name
Test status
Simulation time 36227185 ps
CPU time 2.52 seconds
Started Jun 11 02:13:46 PM PDT 24
Finished Jun 11 02:13:50 PM PDT 24
Peak memory 222760 kb
Host smart-fe00f3ed-9e69-4795-9b3b-30465b083ece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295232495 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_prog_failure.1295232495
Directory /workspace/21.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_mubi.536274299
Short name T241
Test name
Test status
Simulation time 339983337 ps
CPU time 14.02 seconds
Started Jun 11 02:13:46 PM PDT 24
Finished Jun 11 02:14:02 PM PDT 24
Peak memory 219248 kb
Host smart-f4db0685-58b6-41fe-8859-62c1000d174e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536274299 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_mubi.536274299
Directory /workspace/21.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_digest.687363704
Short name T430
Test name
Test status
Simulation time 289921027 ps
CPU time 12.5 seconds
Started Jun 11 02:13:44 PM PDT 24
Finished Jun 11 02:13:57 PM PDT 24
Peak memory 226556 kb
Host smart-b2a31986-4536-4c45-ad25-2c920f3e3c17
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687363704 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_di
gest.687363704
Directory /workspace/21.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_mux.1396129009
Short name T528
Test name
Test status
Simulation time 4158412104 ps
CPU time 10.74 seconds
Started Jun 11 02:13:47 PM PDT 24
Finished Jun 11 02:13:59 PM PDT 24
Peak memory 218848 kb
Host smart-2dbeb6d5-4709-491c-9282-787af57e081d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396129009 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_mux.
1396129009
Directory /workspace/21.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/21.lc_ctrl_security_escalation.2981170671
Short name T49
Test name
Test status
Simulation time 244928861 ps
CPU time 10.35 seconds
Started Jun 11 02:13:49 PM PDT 24
Finished Jun 11 02:14:01 PM PDT 24
Peak memory 226256 kb
Host smart-edec189d-871b-434e-9906-cd42f635ed15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981170671 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_security_escalation.2981170671
Directory /workspace/21.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/21.lc_ctrl_smoke.2194463572
Short name T237
Test name
Test status
Simulation time 39147805 ps
CPU time 2.98 seconds
Started Jun 11 02:13:44 PM PDT 24
Finished Jun 11 02:13:48 PM PDT 24
Peak memory 215296 kb
Host smart-a930e681-65b1-4d73-a9cb-47b6f931a2c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194463572 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_smoke.2194463572
Directory /workspace/21.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_failure.1956668754
Short name T397
Test name
Test status
Simulation time 241332130 ps
CPU time 29.9 seconds
Started Jun 11 02:13:45 PM PDT 24
Finished Jun 11 02:14:15 PM PDT 24
Peak memory 251444 kb
Host smart-94b9ce60-0ac2-465b-bcc0-04c358588024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956668754 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_failure.1956668754
Directory /workspace/21.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_post_trans.2441869872
Short name T768
Test name
Test status
Simulation time 54683678 ps
CPU time 5.87 seconds
Started Jun 11 02:13:56 PM PDT 24
Finished Jun 11 02:14:03 PM PDT 24
Peak memory 247196 kb
Host smart-7a26e4d8-ce91-4a2a-addf-940d979db797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441869872 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_post_trans.2441869872
Directory /workspace/21.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/21.lc_ctrl_stress_all.2244104991
Short name T540
Test name
Test status
Simulation time 24373365245 ps
CPU time 391.78 seconds
Started Jun 11 02:13:47 PM PDT 24
Finished Jun 11 02:20:20 PM PDT 24
Peak memory 281368 kb
Host smart-2a7ca7c6-0a72-4b6b-abdd-6bf1cea9cbe9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244104991 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.lc_ctrl_stress_all.2244104991
Directory /workspace/21.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.lc_ctrl_volatile_unlock_smoke.4097013543
Short name T574
Test name
Test status
Simulation time 13120968 ps
CPU time 0.88 seconds
Started Jun 11 02:13:48 PM PDT 24
Finished Jun 11 02:13:51 PM PDT 24
Peak memory 209368 kb
Host smart-1dc0e291-2642-4513-8fed-dee7ab7e7271
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097013543 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_c
trl_volatile_unlock_smoke.4097013543
Directory /workspace/21.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_alert_test.3271831798
Short name T790
Test name
Test status
Simulation time 115866073 ps
CPU time 0.94 seconds
Started Jun 11 02:13:46 PM PDT 24
Finished Jun 11 02:13:49 PM PDT 24
Peak memory 209440 kb
Host smart-a4c5f2ca-d88c-4ac2-98c0-cf7668400714
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271831798 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_alert_test.3271831798
Directory /workspace/22.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.lc_ctrl_errors.1476501355
Short name T265
Test name
Test status
Simulation time 451702301 ps
CPU time 9.68 seconds
Started Jun 11 02:13:50 PM PDT 24
Finished Jun 11 02:14:01 PM PDT 24
Peak memory 218696 kb
Host smart-56b49f59-bff4-481a-9139-6d5d06b84b2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476501355 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_errors.1476501355
Directory /workspace/22.lc_ctrl_errors/latest

Test location /workspace/coverage/default/22.lc_ctrl_jtag_access.939807277
Short name T844
Test name
Test status
Simulation time 413497420 ps
CPU time 5.78 seconds
Started Jun 11 02:13:46 PM PDT 24
Finished Jun 11 02:13:53 PM PDT 24
Peak memory 217628 kb
Host smart-39ce4123-e896-485d-bce3-3852018b9965
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939807277 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_jtag_access.939807277
Directory /workspace/22.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/22.lc_ctrl_prog_failure.3550703754
Short name T585
Test name
Test status
Simulation time 144005545 ps
CPU time 2.85 seconds
Started Jun 11 02:13:48 PM PDT 24
Finished Jun 11 02:13:53 PM PDT 24
Peak memory 218668 kb
Host smart-c1b91cf9-0169-4f85-9766-13dd84b78805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550703754 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_prog_failure.3550703754
Directory /workspace/22.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_mubi.1394763216
Short name T504
Test name
Test status
Simulation time 2308397976 ps
CPU time 12.84 seconds
Started Jun 11 02:13:46 PM PDT 24
Finished Jun 11 02:14:00 PM PDT 24
Peak memory 219508 kb
Host smart-a522401a-4c75-43d4-a8ef-94e09ecc3a54
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394763216 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_mubi.1394763216
Directory /workspace/22.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_digest.3230368633
Short name T748
Test name
Test status
Simulation time 723748074 ps
CPU time 9.64 seconds
Started Jun 11 02:13:47 PM PDT 24
Finished Jun 11 02:13:59 PM PDT 24
Peak memory 218732 kb
Host smart-64188362-5fd7-4976-b376-ae2b8f6f35b9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230368633 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_d
igest.3230368633
Directory /workspace/22.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_mux.1352573066
Short name T274
Test name
Test status
Simulation time 594822369 ps
CPU time 10.92 seconds
Started Jun 11 02:13:49 PM PDT 24
Finished Jun 11 02:14:02 PM PDT 24
Peak memory 226476 kb
Host smart-36366fe6-6b29-4af0-96fc-765d8b80240b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352573066 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_mux.
1352573066
Directory /workspace/22.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/22.lc_ctrl_security_escalation.1326376324
Short name T867
Test name
Test status
Simulation time 949656191 ps
CPU time 9.13 seconds
Started Jun 11 02:13:48 PM PDT 24
Finished Jun 11 02:13:59 PM PDT 24
Peak memory 218784 kb
Host smart-ff5a7536-5a1b-42e3-baca-09a56601162f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326376324 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_security_escalation.1326376324
Directory /workspace/22.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/22.lc_ctrl_smoke.917937644
Short name T668
Test name
Test status
Simulation time 22932555 ps
CPU time 1.93 seconds
Started Jun 11 02:13:49 PM PDT 24
Finished Jun 11 02:13:52 PM PDT 24
Peak memory 214568 kb
Host smart-aaf37601-7aa4-44cb-9b51-13f9c906d630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917937644 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_smoke.917937644
Directory /workspace/22.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_failure.4186789648
Short name T257
Test name
Test status
Simulation time 1126382837 ps
CPU time 26.64 seconds
Started Jun 11 02:13:47 PM PDT 24
Finished Jun 11 02:14:16 PM PDT 24
Peak memory 251484 kb
Host smart-43f0e374-3ce6-43ef-bfe3-1d12a5709e3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186789648 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_failure.4186789648
Directory /workspace/22.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_post_trans.119968288
Short name T411
Test name
Test status
Simulation time 47495047 ps
CPU time 2.96 seconds
Started Jun 11 02:13:49 PM PDT 24
Finished Jun 11 02:13:54 PM PDT 24
Peak memory 222636 kb
Host smart-12659dda-3921-4b0c-9e4f-7f3445d4cafc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119968288 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_post_trans.119968288
Directory /workspace/22.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/22.lc_ctrl_stress_all.1759481224
Short name T793
Test name
Test status
Simulation time 16110628463 ps
CPU time 169.09 seconds
Started Jun 11 02:13:46 PM PDT 24
Finished Jun 11 02:16:36 PM PDT 24
Peak memory 317056 kb
Host smart-5e9ee91b-de17-4cab-8507-8c79514f3a95
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759481224 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.lc_ctrl_stress_all.1759481224
Directory /workspace/22.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.lc_ctrl_stress_all_with_rand_reset.2947208258
Short name T788
Test name
Test status
Simulation time 151003428110 ps
CPU time 788.54 seconds
Started Jun 11 02:13:48 PM PDT 24
Finished Jun 11 02:26:58 PM PDT 24
Peak memory 439056 kb
Host smart-5dc9a774-9117-4c98-9b01-8367c4050212
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2947208258 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_stress_all_with_rand_reset.2947208258
Directory /workspace/22.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.lc_ctrl_volatile_unlock_smoke.4058851729
Short name T406
Test name
Test status
Simulation time 33190956 ps
CPU time 0.91 seconds
Started Jun 11 02:13:47 PM PDT 24
Finished Jun 11 02:13:50 PM PDT 24
Peak memory 209404 kb
Host smart-195bb3cf-9602-4975-a811-36c6a81ce5c7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058851729 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_c
trl_volatile_unlock_smoke.4058851729
Directory /workspace/22.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_alert_test.4115960439
Short name T219
Test name
Test status
Simulation time 26939234 ps
CPU time 1.06 seconds
Started Jun 11 02:13:49 PM PDT 24
Finished Jun 11 02:13:52 PM PDT 24
Peak memory 209556 kb
Host smart-f97dbaa9-8520-41f0-89e4-f5055eb4f51c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115960439 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_alert_test.4115960439
Directory /workspace/23.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.lc_ctrl_errors.3692677321
Short name T775
Test name
Test status
Simulation time 622671672 ps
CPU time 8.37 seconds
Started Jun 11 02:13:48 PM PDT 24
Finished Jun 11 02:13:58 PM PDT 24
Peak memory 218716 kb
Host smart-8d99705d-dca1-4efa-abc4-221be54c40f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692677321 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_errors.3692677321
Directory /workspace/23.lc_ctrl_errors/latest

Test location /workspace/coverage/default/23.lc_ctrl_jtag_access.2723083687
Short name T6
Test name
Test status
Simulation time 37089303 ps
CPU time 1.13 seconds
Started Jun 11 02:13:46 PM PDT 24
Finished Jun 11 02:13:49 PM PDT 24
Peak memory 217528 kb
Host smart-13941926-3042-4f90-9481-998de74c8345
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723083687 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_jtag_access.2723083687
Directory /workspace/23.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/23.lc_ctrl_prog_failure.2343259235
Short name T641
Test name
Test status
Simulation time 25893992 ps
CPU time 2.01 seconds
Started Jun 11 02:13:48 PM PDT 24
Finished Jun 11 02:13:51 PM PDT 24
Peak memory 218148 kb
Host smart-06f0225b-9337-425d-9f5c-81132861cab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343259235 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_prog_failure.2343259235
Directory /workspace/23.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_mubi.2551165312
Short name T273
Test name
Test status
Simulation time 982779860 ps
CPU time 13.96 seconds
Started Jun 11 02:13:47 PM PDT 24
Finished Jun 11 02:14:02 PM PDT 24
Peak memory 218804 kb
Host smart-f5ae204c-2861-4416-b919-6a1476d5160a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551165312 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_mubi.2551165312
Directory /workspace/23.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_digest.1795616302
Short name T734
Test name
Test status
Simulation time 2583280731 ps
CPU time 22.44 seconds
Started Jun 11 02:13:46 PM PDT 24
Finished Jun 11 02:14:10 PM PDT 24
Peak memory 226576 kb
Host smart-5bfdfe6b-3f7e-4a41-923b-1cd8c31fe2ff
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795616302 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_d
igest.1795616302
Directory /workspace/23.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_mux.2247741969
Short name T299
Test name
Test status
Simulation time 383515784 ps
CPU time 10.13 seconds
Started Jun 11 02:13:54 PM PDT 24
Finished Jun 11 02:14:05 PM PDT 24
Peak memory 226396 kb
Host smart-59ddb93e-ee3b-4cb9-b015-8eccd8ec3b8e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247741969 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_mux.
2247741969
Directory /workspace/23.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/23.lc_ctrl_security_escalation.3620469787
Short name T547
Test name
Test status
Simulation time 680548271 ps
CPU time 10.62 seconds
Started Jun 11 02:13:49 PM PDT 24
Finished Jun 11 02:14:02 PM PDT 24
Peak memory 218740 kb
Host smart-b4fcfa06-9f88-4be6-a653-cd26d81e712e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620469787 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_security_escalation.3620469787
Directory /workspace/23.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/23.lc_ctrl_smoke.955904893
Short name T64
Test name
Test status
Simulation time 59283941 ps
CPU time 2.83 seconds
Started Jun 11 02:13:47 PM PDT 24
Finished Jun 11 02:13:52 PM PDT 24
Peak memory 218312 kb
Host smart-463d072b-c63d-449f-8549-9186f95b1c5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955904893 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_smoke.955904893
Directory /workspace/23.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_failure.2800212195
Short name T817
Test name
Test status
Simulation time 353011444 ps
CPU time 22.35 seconds
Started Jun 11 02:13:50 PM PDT 24
Finished Jun 11 02:14:14 PM PDT 24
Peak memory 251504 kb
Host smart-43943d44-ed1c-4fe9-8421-469fb33eb73f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800212195 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_failure.2800212195
Directory /workspace/23.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_post_trans.3239765815
Short name T848
Test name
Test status
Simulation time 85036506 ps
CPU time 7.25 seconds
Started Jun 11 02:13:48 PM PDT 24
Finished Jun 11 02:13:57 PM PDT 24
Peak memory 248968 kb
Host smart-cfe23932-0ad7-463c-8e3e-8d9bb5449e50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239765815 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_post_trans.3239765815
Directory /workspace/23.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all.1391543147
Short name T680
Test name
Test status
Simulation time 3705842598 ps
CPU time 139.22 seconds
Started Jun 11 02:13:46 PM PDT 24
Finished Jun 11 02:16:07 PM PDT 24
Peak memory 270180 kb
Host smart-033a66b6-014e-48f9-9340-4da99c8b9036
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391543147 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.lc_ctrl_stress_all.1391543147
Directory /workspace/23.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.lc_ctrl_volatile_unlock_smoke.372285372
Short name T437
Test name
Test status
Simulation time 22912671 ps
CPU time 0.81 seconds
Started Jun 11 02:13:48 PM PDT 24
Finished Jun 11 02:13:51 PM PDT 24
Peak memory 209544 kb
Host smart-b6f6da17-29d2-4f76-9695-04f4a33924bd
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372285372 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ct
rl_volatile_unlock_smoke.372285372
Directory /workspace/23.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_alert_test.3611432254
Short name T143
Test name
Test status
Simulation time 73174974 ps
CPU time 0.91 seconds
Started Jun 11 02:13:54 PM PDT 24
Finished Jun 11 02:13:56 PM PDT 24
Peak memory 209476 kb
Host smart-d747b02f-d3ca-4d29-8951-dc349ee88cda
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611432254 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_alert_test.3611432254
Directory /workspace/24.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.lc_ctrl_errors.1222924799
Short name T649
Test name
Test status
Simulation time 293126275 ps
CPU time 14.01 seconds
Started Jun 11 02:13:50 PM PDT 24
Finished Jun 11 02:14:06 PM PDT 24
Peak memory 218708 kb
Host smart-ef467c70-1285-4f29-a2cd-959b4b6578f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222924799 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_errors.1222924799
Directory /workspace/24.lc_ctrl_errors/latest

Test location /workspace/coverage/default/24.lc_ctrl_jtag_access.252132409
Short name T160
Test name
Test status
Simulation time 2002221983 ps
CPU time 7.48 seconds
Started Jun 11 02:13:56 PM PDT 24
Finished Jun 11 02:14:05 PM PDT 24
Peak memory 217644 kb
Host smart-197f2062-5003-4d20-99e4-7995ab2bb5a4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252132409 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_jtag_access.252132409
Directory /workspace/24.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/24.lc_ctrl_prog_failure.3429231812
Short name T254
Test name
Test status
Simulation time 148595952 ps
CPU time 2.37 seconds
Started Jun 11 02:13:50 PM PDT 24
Finished Jun 11 02:13:54 PM PDT 24
Peak memory 218644 kb
Host smart-dd02acaa-b436-4da8-90bd-19bf8eb1983d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429231812 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_prog_failure.3429231812
Directory /workspace/24.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_mubi.61750394
Short name T699
Test name
Test status
Simulation time 408613666 ps
CPU time 8.85 seconds
Started Jun 11 02:13:49 PM PDT 24
Finished Jun 11 02:13:59 PM PDT 24
Peak memory 218784 kb
Host smart-be5729a9-2a91-4b5c-8483-c1df7381f167
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61750394 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_mubi.61750394
Directory /workspace/24.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_digest.11645933
Short name T371
Test name
Test status
Simulation time 271823077 ps
CPU time 11.1 seconds
Started Jun 11 02:13:47 PM PDT 24
Finished Jun 11 02:14:00 PM PDT 24
Peak memory 218724 kb
Host smart-0ddf1e19-662d-4bec-8fbc-9a9ac5235a1c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11645933 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_dig
est_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_dig
est.11645933
Directory /workspace/24.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_mux.1130828303
Short name T644
Test name
Test status
Simulation time 208203689 ps
CPU time 7.4 seconds
Started Jun 11 02:13:56 PM PDT 24
Finished Jun 11 02:14:05 PM PDT 24
Peak memory 218744 kb
Host smart-dc8c9f21-cae1-4e89-99a2-4a29fb8ed527
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130828303 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_mux.
1130828303
Directory /workspace/24.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/24.lc_ctrl_security_escalation.3123932729
Short name T548
Test name
Test status
Simulation time 759675631 ps
CPU time 7.91 seconds
Started Jun 11 02:13:49 PM PDT 24
Finished Jun 11 02:13:59 PM PDT 24
Peak memory 225960 kb
Host smart-2bff6124-c41e-458d-94c0-290a7c98fc58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123932729 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_security_escalation.3123932729
Directory /workspace/24.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/24.lc_ctrl_smoke.371339592
Short name T293
Test name
Test status
Simulation time 40108505 ps
CPU time 2.83 seconds
Started Jun 11 02:13:48 PM PDT 24
Finished Jun 11 02:13:53 PM PDT 24
Peak memory 214932 kb
Host smart-c55e4ed9-e3d6-4195-9e7a-625b7906d77a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371339592 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_smoke.371339592
Directory /workspace/24.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_failure.2187696523
Short name T385
Test name
Test status
Simulation time 198812772 ps
CPU time 27.37 seconds
Started Jun 11 02:13:47 PM PDT 24
Finished Jun 11 02:14:17 PM PDT 24
Peak memory 251348 kb
Host smart-11ee527f-1631-494b-ae4a-a4ddcce5a0d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187696523 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_failure.2187696523
Directory /workspace/24.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_post_trans.3334085343
Short name T560
Test name
Test status
Simulation time 347327520 ps
CPU time 5.81 seconds
Started Jun 11 02:13:48 PM PDT 24
Finished Jun 11 02:13:55 PM PDT 24
Peak memory 247184 kb
Host smart-a18a68cf-9ae0-4da7-a7ec-586c8ef238d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334085343 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_post_trans.3334085343
Directory /workspace/24.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all.2991989651
Short name T606
Test name
Test status
Simulation time 6741758949 ps
CPU time 142.11 seconds
Started Jun 11 02:13:48 PM PDT 24
Finished Jun 11 02:16:12 PM PDT 24
Peak memory 300632 kb
Host smart-dbacf482-fff4-4850-9061-4470a62fa6be
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991989651 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.lc_ctrl_stress_all.2991989651
Directory /workspace/24.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.lc_ctrl_volatile_unlock_smoke.2118310020
Short name T315
Test name
Test status
Simulation time 12757702 ps
CPU time 1.01 seconds
Started Jun 11 02:13:46 PM PDT 24
Finished Jun 11 02:13:49 PM PDT 24
Peak memory 209408 kb
Host smart-655f7548-86f9-4062-8aeb-0b527b67a82e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118310020 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_c
trl_volatile_unlock_smoke.2118310020
Directory /workspace/24.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_alert_test.1571789683
Short name T67
Test name
Test status
Simulation time 63510655 ps
CPU time 1.15 seconds
Started Jun 11 02:14:02 PM PDT 24
Finished Jun 11 02:14:06 PM PDT 24
Peak memory 209500 kb
Host smart-3035b97b-f29a-4053-b01b-877219c941fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571789683 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_alert_test.1571789683
Directory /workspace/25.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.lc_ctrl_errors.2201713034
Short name T297
Test name
Test status
Simulation time 2409911547 ps
CPU time 10.72 seconds
Started Jun 11 02:14:00 PM PDT 24
Finished Jun 11 02:14:13 PM PDT 24
Peak memory 219368 kb
Host smart-0597c8d3-5d05-4219-83be-44cf2b7cc56e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201713034 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_errors.2201713034
Directory /workspace/25.lc_ctrl_errors/latest

Test location /workspace/coverage/default/25.lc_ctrl_jtag_access.1306205675
Short name T24
Test name
Test status
Simulation time 175698497 ps
CPU time 2.86 seconds
Started Jun 11 02:13:59 PM PDT 24
Finished Jun 11 02:14:04 PM PDT 24
Peak memory 217628 kb
Host smart-885b8ef2-28e9-4f5a-8222-1172ca4f65f7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306205675 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_jtag_access.1306205675
Directory /workspace/25.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/25.lc_ctrl_prog_failure.3578850221
Short name T60
Test name
Test status
Simulation time 144945760 ps
CPU time 2.16 seconds
Started Jun 11 02:13:57 PM PDT 24
Finished Jun 11 02:14:01 PM PDT 24
Peak memory 218700 kb
Host smart-a3836975-6d46-4dda-a5e9-40d7f5f7b139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3578850221 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_prog_failure.3578850221
Directory /workspace/25.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_mubi.441054532
Short name T415
Test name
Test status
Simulation time 1054193720 ps
CPU time 17.3 seconds
Started Jun 11 02:13:57 PM PDT 24
Finished Jun 11 02:14:16 PM PDT 24
Peak memory 219484 kb
Host smart-4537616d-23f2-4ca7-af55-7d589162925d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441054532 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_mubi.441054532
Directory /workspace/25.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_digest.3376368379
Short name T337
Test name
Test status
Simulation time 179320609 ps
CPU time 8.81 seconds
Started Jun 11 02:13:56 PM PDT 24
Finished Jun 11 02:14:06 PM PDT 24
Peak memory 218684 kb
Host smart-bdaa0aee-a3c6-4b57-9aa3-8d0ab27bfdf1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376368379 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_d
igest.3376368379
Directory /workspace/25.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_mux.2231896352
Short name T444
Test name
Test status
Simulation time 319096365 ps
CPU time 7.53 seconds
Started Jun 11 02:13:59 PM PDT 24
Finished Jun 11 02:14:09 PM PDT 24
Peak memory 218712 kb
Host smart-8bbfaeb3-5790-4060-88f3-b8e5f6fe8eab
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231896352 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_mux.
2231896352
Directory /workspace/25.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/25.lc_ctrl_security_escalation.846459068
Short name T267
Test name
Test status
Simulation time 225203007 ps
CPU time 6.56 seconds
Started Jun 11 02:13:56 PM PDT 24
Finished Jun 11 02:14:04 PM PDT 24
Peak memory 224856 kb
Host smart-7c359e93-1398-4944-b630-44af157b32fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=846459068 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_security_escalation.846459068
Directory /workspace/25.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/25.lc_ctrl_smoke.1321902559
Short name T72
Test name
Test status
Simulation time 35835643 ps
CPU time 2.38 seconds
Started Jun 11 02:13:59 PM PDT 24
Finished Jun 11 02:14:04 PM PDT 24
Peak memory 215148 kb
Host smart-eade9c7b-e1c7-4402-a656-c9a53931cf5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321902559 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_smoke.1321902559
Directory /workspace/25.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_failure.1157309128
Short name T806
Test name
Test status
Simulation time 510748886 ps
CPU time 21.67 seconds
Started Jun 11 02:14:01 PM PDT 24
Finished Jun 11 02:14:25 PM PDT 24
Peak memory 251516 kb
Host smart-de2a4504-7171-4150-aa5b-34dcde5e75ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157309128 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_failure.1157309128
Directory /workspace/25.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_post_trans.739097452
Short name T346
Test name
Test status
Simulation time 85890006 ps
CPU time 8.82 seconds
Started Jun 11 02:13:56 PM PDT 24
Finished Jun 11 02:14:06 PM PDT 24
Peak memory 251384 kb
Host smart-5c530921-408d-44e0-b702-6fb58c4cbf95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739097452 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_post_trans.739097452
Directory /workspace/25.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/25.lc_ctrl_stress_all.3878640851
Short name T263
Test name
Test status
Simulation time 50517582272 ps
CPU time 232.09 seconds
Started Jun 11 02:14:01 PM PDT 24
Finished Jun 11 02:17:56 PM PDT 24
Peak memory 267876 kb
Host smart-0f4574e3-d24d-4ae5-abfb-f9a8993312d2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878640851 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.lc_ctrl_stress_all.3878640851
Directory /workspace/25.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.lc_ctrl_stress_all_with_rand_reset.2403936059
Short name T98
Test name
Test status
Simulation time 30932138491 ps
CPU time 1060.85 seconds
Started Jun 11 02:14:00 PM PDT 24
Finished Jun 11 02:31:43 PM PDT 24
Peak memory 530076 kb
Host smart-232e9398-5b90-48a6-9135-f70fe0faff07
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2403936059 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_stress_all_with_rand_reset.2403936059
Directory /workspace/25.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.lc_ctrl_volatile_unlock_smoke.1669208559
Short name T650
Test name
Test status
Simulation time 13247252 ps
CPU time 0.75 seconds
Started Jun 11 02:13:57 PM PDT 24
Finished Jun 11 02:13:59 PM PDT 24
Peak memory 208548 kb
Host smart-719c668a-9c14-45b3-aed3-8a08cf166a3d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669208559 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_c
trl_volatile_unlock_smoke.1669208559
Directory /workspace/25.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_alert_test.1272231628
Short name T71
Test name
Test status
Simulation time 19070695 ps
CPU time 0.98 seconds
Started Jun 11 02:14:00 PM PDT 24
Finished Jun 11 02:14:04 PM PDT 24
Peak memory 209428 kb
Host smart-f52cc47e-e8a5-46eb-bcc8-325a8c18bed6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272231628 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_alert_test.1272231628
Directory /workspace/26.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.lc_ctrl_errors.2327351771
Short name T92
Test name
Test status
Simulation time 632050451 ps
CPU time 23.53 seconds
Started Jun 11 02:13:58 PM PDT 24
Finished Jun 11 02:14:24 PM PDT 24
Peak memory 218544 kb
Host smart-e73f8433-491a-4251-8b23-6a825ef3cf2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327351771 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_errors.2327351771
Directory /workspace/26.lc_ctrl_errors/latest

Test location /workspace/coverage/default/26.lc_ctrl_jtag_access.3419400554
Short name T377
Test name
Test status
Simulation time 981003008 ps
CPU time 9.82 seconds
Started Jun 11 02:13:57 PM PDT 24
Finished Jun 11 02:14:08 PM PDT 24
Peak memory 218040 kb
Host smart-c2c0d8a5-9b98-4e84-b1a6-a28a8628ffda
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419400554 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_jtag_access.3419400554
Directory /workspace/26.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/26.lc_ctrl_prog_failure.4238113448
Short name T501
Test name
Test status
Simulation time 98007463 ps
CPU time 3.2 seconds
Started Jun 11 02:13:58 PM PDT 24
Finished Jun 11 02:14:03 PM PDT 24
Peak memory 218524 kb
Host smart-fcdd7083-fc60-4255-9c83-cb3baf683a73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238113448 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_prog_failure.4238113448
Directory /workspace/26.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_mubi.864045692
Short name T461
Test name
Test status
Simulation time 855917604 ps
CPU time 15.57 seconds
Started Jun 11 02:13:58 PM PDT 24
Finished Jun 11 02:14:15 PM PDT 24
Peak memory 226560 kb
Host smart-00610b1c-ac07-44a0-9bc5-125c060b0144
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864045692 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_mubi.864045692
Directory /workspace/26.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_digest.4153814103
Short name T367
Test name
Test status
Simulation time 303850379 ps
CPU time 13.96 seconds
Started Jun 11 02:14:00 PM PDT 24
Finished Jun 11 02:14:17 PM PDT 24
Peak memory 218736 kb
Host smart-5bcc4919-de91-47d5-9f80-c368057fe5a8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153814103 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_d
igest.4153814103
Directory /workspace/26.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_mux.2734447495
Short name T235
Test name
Test status
Simulation time 268912870 ps
CPU time 11.08 seconds
Started Jun 11 02:13:55 PM PDT 24
Finished Jun 11 02:14:07 PM PDT 24
Peak memory 218716 kb
Host smart-c7f89ad0-abf4-4b23-baf6-82286530f6f1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734447495 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_mux.
2734447495
Directory /workspace/26.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/26.lc_ctrl_security_escalation.3593717134
Short name T165
Test name
Test status
Simulation time 247687512 ps
CPU time 8.43 seconds
Started Jun 11 02:13:59 PM PDT 24
Finished Jun 11 02:14:10 PM PDT 24
Peak memory 218812 kb
Host smart-89428907-a9cd-4d77-b47d-e0a2f0744368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593717134 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_security_escalation.3593717134
Directory /workspace/26.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/26.lc_ctrl_smoke.3648835231
Short name T705
Test name
Test status
Simulation time 104003054 ps
CPU time 3.31 seconds
Started Jun 11 02:13:56 PM PDT 24
Finished Jun 11 02:14:01 PM PDT 24
Peak memory 215580 kb
Host smart-efea3d31-89e7-420c-be22-9d8427bd62c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648835231 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_smoke.3648835231
Directory /workspace/26.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_failure.1394647974
Short name T142
Test name
Test status
Simulation time 623687218 ps
CPU time 21.13 seconds
Started Jun 11 02:13:59 PM PDT 24
Finished Jun 11 02:14:23 PM PDT 24
Peak memory 246760 kb
Host smart-a40cc786-9be8-4ef0-959b-643a59243cc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394647974 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_failure.1394647974
Directory /workspace/26.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_post_trans.2236051426
Short name T583
Test name
Test status
Simulation time 80965358 ps
CPU time 6.34 seconds
Started Jun 11 02:13:57 PM PDT 24
Finished Jun 11 02:14:05 PM PDT 24
Peak memory 247060 kb
Host smart-24990bcb-dd77-4aa3-ad62-7d200ebb1647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236051426 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_post_trans.2236051426
Directory /workspace/26.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all.1967216439
Short name T578
Test name
Test status
Simulation time 9107116064 ps
CPU time 111.03 seconds
Started Jun 11 02:14:00 PM PDT 24
Finished Jun 11 02:15:54 PM PDT 24
Peak memory 251424 kb
Host smart-1a576089-b7a8-486a-9ead-17a6a94842d2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967216439 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.lc_ctrl_stress_all.1967216439
Directory /workspace/26.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all_with_rand_reset.3646764669
Short name T97
Test name
Test status
Simulation time 16218933039 ps
CPU time 690.97 seconds
Started Jun 11 02:13:55 PM PDT 24
Finished Jun 11 02:25:27 PM PDT 24
Peak memory 268036 kb
Host smart-d79f2ea0-5485-481b-b6dd-2142c90bbcdf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3646764669 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_stress_all_with_rand_reset.3646764669
Directory /workspace/26.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.lc_ctrl_volatile_unlock_smoke.4091561056
Short name T569
Test name
Test status
Simulation time 24473902 ps
CPU time 0.85 seconds
Started Jun 11 02:13:58 PM PDT 24
Finished Jun 11 02:14:01 PM PDT 24
Peak memory 209396 kb
Host smart-b2e27736-62d7-45a7-ac81-b21794790e59
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091561056 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_c
trl_volatile_unlock_smoke.4091561056
Directory /workspace/26.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_alert_test.2529701926
Short name T561
Test name
Test status
Simulation time 32480759 ps
CPU time 1.08 seconds
Started Jun 11 02:13:57 PM PDT 24
Finished Jun 11 02:13:59 PM PDT 24
Peak memory 209412 kb
Host smart-293a5844-e1d9-4632-82e4-70b78d409f49
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529701926 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_alert_test.2529701926
Directory /workspace/27.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.lc_ctrl_errors.1412307503
Short name T740
Test name
Test status
Simulation time 1654357797 ps
CPU time 13.2 seconds
Started Jun 11 02:13:59 PM PDT 24
Finished Jun 11 02:14:15 PM PDT 24
Peak memory 218568 kb
Host smart-80e421ad-4673-4993-8fa2-663b9f9cd183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412307503 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_errors.1412307503
Directory /workspace/27.lc_ctrl_errors/latest

Test location /workspace/coverage/default/27.lc_ctrl_jtag_access.3421535186
Short name T857
Test name
Test status
Simulation time 278823734 ps
CPU time 1.57 seconds
Started Jun 11 02:13:58 PM PDT 24
Finished Jun 11 02:14:02 PM PDT 24
Peak memory 217604 kb
Host smart-c9706674-17f3-4e2b-ab45-64ccde32e781
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421535186 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_jtag_access.3421535186
Directory /workspace/27.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/27.lc_ctrl_prog_failure.2708217359
Short name T595
Test name
Test status
Simulation time 586980378 ps
CPU time 1.93 seconds
Started Jun 11 02:13:58 PM PDT 24
Finished Jun 11 02:14:02 PM PDT 24
Peak memory 222472 kb
Host smart-3774bb66-26d7-48d0-ac06-faa7de4c44f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708217359 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_prog_failure.2708217359
Directory /workspace/27.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_mubi.2319914769
Short name T588
Test name
Test status
Simulation time 1973368195 ps
CPU time 21.14 seconds
Started Jun 11 02:13:57 PM PDT 24
Finished Jun 11 02:14:19 PM PDT 24
Peak memory 226460 kb
Host smart-30267ab6-a4f3-42e6-a8a3-9daa60929c29
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319914769 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_mubi.2319914769
Directory /workspace/27.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_digest.3605541629
Short name T562
Test name
Test status
Simulation time 917510674 ps
CPU time 13.34 seconds
Started Jun 11 02:13:57 PM PDT 24
Finished Jun 11 02:14:12 PM PDT 24
Peak memory 226356 kb
Host smart-fe48d1c9-c5b5-4534-8b1b-30ccc99337ff
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605541629 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_d
igest.3605541629
Directory /workspace/27.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_mux.2463617806
Short name T341
Test name
Test status
Simulation time 400909182 ps
CPU time 8.42 seconds
Started Jun 11 02:13:57 PM PDT 24
Finished Jun 11 02:14:07 PM PDT 24
Peak memory 226548 kb
Host smart-4dc52d28-24a6-46f5-89b5-51768ea36460
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463617806 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_mux.
2463617806
Directory /workspace/27.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/27.lc_ctrl_security_escalation.539545026
Short name T438
Test name
Test status
Simulation time 1796874046 ps
CPU time 6.22 seconds
Started Jun 11 02:13:57 PM PDT 24
Finished Jun 11 02:14:05 PM PDT 24
Peak memory 224920 kb
Host smart-d4fdb3ad-ba92-4869-86ee-5a0f4d911a15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539545026 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_security_escalation.539545026
Directory /workspace/27.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/27.lc_ctrl_smoke.2308777888
Short name T703
Test name
Test status
Simulation time 34442533 ps
CPU time 2.1 seconds
Started Jun 11 02:13:56 PM PDT 24
Finished Jun 11 02:13:59 PM PDT 24
Peak memory 218184 kb
Host smart-d35336fe-7b8f-497a-8ccb-278c4e3049ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308777888 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_smoke.2308777888
Directory /workspace/27.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_failure.3856787130
Short name T464
Test name
Test status
Simulation time 1036121416 ps
CPU time 24.16 seconds
Started Jun 11 02:13:58 PM PDT 24
Finished Jun 11 02:14:25 PM PDT 24
Peak memory 251404 kb
Host smart-c4516a2e-4ced-4ffa-b10c-25b51f52a94e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856787130 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_failure.3856787130
Directory /workspace/27.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_post_trans.3610219264
Short name T801
Test name
Test status
Simulation time 173327854 ps
CPU time 7.02 seconds
Started Jun 11 02:13:59 PM PDT 24
Finished Jun 11 02:14:08 PM PDT 24
Peak memory 249000 kb
Host smart-fd0e3bf8-768e-48c7-9554-5277b08e7414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610219264 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_post_trans.3610219264
Directory /workspace/27.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all.4262965295
Short name T648
Test name
Test status
Simulation time 4436660139 ps
CPU time 74.06 seconds
Started Jun 11 02:14:00 PM PDT 24
Finished Jun 11 02:15:16 PM PDT 24
Peak memory 259688 kb
Host smart-3efd7ba4-d40f-40ac-a2c4-6d45a71be036
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262965295 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.lc_ctrl_stress_all.4262965295
Directory /workspace/27.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.lc_ctrl_volatile_unlock_smoke.2412905015
Short name T285
Test name
Test status
Simulation time 21710901 ps
CPU time 1.22 seconds
Started Jun 11 02:13:58 PM PDT 24
Finished Jun 11 02:14:02 PM PDT 24
Peak memory 218424 kb
Host smart-cfdaadad-de20-4253-ba8b-2521e29cb187
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412905015 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_c
trl_volatile_unlock_smoke.2412905015
Directory /workspace/27.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_errors.4217271874
Short name T355
Test name
Test status
Simulation time 769126473 ps
CPU time 9.02 seconds
Started Jun 11 02:13:59 PM PDT 24
Finished Jun 11 02:14:11 PM PDT 24
Peak memory 218696 kb
Host smart-dd69609d-c1e1-4259-a892-bdc5236844c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217271874 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_errors.4217271874
Directory /workspace/28.lc_ctrl_errors/latest

Test location /workspace/coverage/default/28.lc_ctrl_jtag_access.2585860027
Short name T744
Test name
Test status
Simulation time 572338241 ps
CPU time 4.17 seconds
Started Jun 11 02:13:59 PM PDT 24
Finished Jun 11 02:14:06 PM PDT 24
Peak memory 217472 kb
Host smart-d3cf44d5-47c4-49d6-b33c-880e4363feb2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585860027 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_jtag_access.2585860027
Directory /workspace/28.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/28.lc_ctrl_prog_failure.3203806842
Short name T484
Test name
Test status
Simulation time 172762820 ps
CPU time 5.16 seconds
Started Jun 11 02:13:58 PM PDT 24
Finished Jun 11 02:14:06 PM PDT 24
Peak memory 218688 kb
Host smart-3e4fcb76-ec0c-454d-80a6-8762502bcb2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203806842 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_prog_failure.3203806842
Directory /workspace/28.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_mubi.3778148234
Short name T141
Test name
Test status
Simulation time 874638373 ps
CPU time 12.97 seconds
Started Jun 11 02:14:01 PM PDT 24
Finished Jun 11 02:14:16 PM PDT 24
Peak memory 219460 kb
Host smart-b05ab6c8-f96f-4f23-bc2e-1bcf9af33f7a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778148234 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_mubi.3778148234
Directory /workspace/28.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_digest.214902908
Short name T773
Test name
Test status
Simulation time 238449039 ps
CPU time 8.5 seconds
Started Jun 11 02:14:00 PM PDT 24
Finished Jun 11 02:14:12 PM PDT 24
Peak memory 218608 kb
Host smart-dcc5c6de-50eb-46e2-9123-c647dfe3dadc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214902908 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_di
gest.214902908
Directory /workspace/28.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_mux.1337097673
Short name T681
Test name
Test status
Simulation time 573567671 ps
CPU time 10.03 seconds
Started Jun 11 02:13:59 PM PDT 24
Finished Jun 11 02:14:12 PM PDT 24
Peak memory 226528 kb
Host smart-9bf24775-d5eb-4b98-a570-bdceacf96d84
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337097673 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_mux.
1337097673
Directory /workspace/28.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/28.lc_ctrl_security_escalation.4282431839
Short name T53
Test name
Test status
Simulation time 350331753 ps
CPU time 10.47 seconds
Started Jun 11 02:13:56 PM PDT 24
Finished Jun 11 02:14:07 PM PDT 24
Peak memory 218692 kb
Host smart-c92ed9ae-05ec-4ed3-814b-8a23945d1ea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282431839 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_security_escalation.4282431839
Directory /workspace/28.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/28.lc_ctrl_smoke.950170209
Short name T442
Test name
Test status
Simulation time 319133084 ps
CPU time 4.51 seconds
Started Jun 11 02:13:58 PM PDT 24
Finished Jun 11 02:14:05 PM PDT 24
Peak memory 218124 kb
Host smart-25cb87bf-8e64-4655-a4d8-71ff4ac47aba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=950170209 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_smoke.950170209
Directory /workspace/28.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_failure.2116048994
Short name T144
Test name
Test status
Simulation time 762463682 ps
CPU time 21.77 seconds
Started Jun 11 02:13:59 PM PDT 24
Finished Jun 11 02:14:24 PM PDT 24
Peak memory 251412 kb
Host smart-5714c366-1b97-46b3-98fd-6d24a657f8fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116048994 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_failure.2116048994
Directory /workspace/28.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_post_trans.140378554
Short name T513
Test name
Test status
Simulation time 128116949 ps
CPU time 8.23 seconds
Started Jun 11 02:13:59 PM PDT 24
Finished Jun 11 02:14:10 PM PDT 24
Peak memory 251436 kb
Host smart-8d119986-bd01-4e5f-9e27-c27dc6124f57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140378554 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_post_trans.140378554
Directory /workspace/28.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/28.lc_ctrl_stress_all.248864321
Short name T741
Test name
Test status
Simulation time 9463706494 ps
CPU time 42.48 seconds
Started Jun 11 02:13:58 PM PDT 24
Finished Jun 11 02:14:42 PM PDT 24
Peak memory 251480 kb
Host smart-b50ea999-1dc9-4b06-8c9a-cdda1abf8d2d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248864321 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.lc_ctrl_stress_all.248864321
Directory /workspace/28.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.lc_ctrl_volatile_unlock_smoke.873803693
Short name T715
Test name
Test status
Simulation time 27163318 ps
CPU time 1.29 seconds
Started Jun 11 02:13:59 PM PDT 24
Finished Jun 11 02:14:03 PM PDT 24
Peak memory 213336 kb
Host smart-7ad9f8db-3b4d-46d8-8321-f65ec6b51145
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873803693 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ct
rl_volatile_unlock_smoke.873803693
Directory /workspace/28.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_alert_test.2577517217
Short name T584
Test name
Test status
Simulation time 19785737 ps
CPU time 1.2 seconds
Started Jun 11 02:14:05 PM PDT 24
Finished Jun 11 02:14:08 PM PDT 24
Peak memory 209436 kb
Host smart-681b1681-0fff-47c5-a4e3-864e46544b05
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577517217 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_alert_test.2577517217
Directory /workspace/29.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.lc_ctrl_errors.628040391
Short name T755
Test name
Test status
Simulation time 353251714 ps
CPU time 10.04 seconds
Started Jun 11 02:13:58 PM PDT 24
Finished Jun 11 02:14:10 PM PDT 24
Peak memory 218712 kb
Host smart-323d9f2f-c7fb-4cf7-b899-b7358a9d3813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628040391 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_errors.628040391
Directory /workspace/29.lc_ctrl_errors/latest

Test location /workspace/coverage/default/29.lc_ctrl_jtag_access.3838913538
Short name T26
Test name
Test status
Simulation time 299323140 ps
CPU time 1.78 seconds
Started Jun 11 02:13:57 PM PDT 24
Finished Jun 11 02:14:01 PM PDT 24
Peak memory 217656 kb
Host smart-f86df459-792b-4e1a-9286-5b6dedbf1268
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838913538 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_jtag_access.3838913538
Directory /workspace/29.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/29.lc_ctrl_prog_failure.2938894853
Short name T611
Test name
Test status
Simulation time 78178296 ps
CPU time 3.05 seconds
Started Jun 11 02:13:58 PM PDT 24
Finished Jun 11 02:14:03 PM PDT 24
Peak memory 222580 kb
Host smart-8b4d0f38-171f-40df-972d-8c6e6a940a9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938894853 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_prog_failure.2938894853
Directory /workspace/29.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_mubi.1188274825
Short name T658
Test name
Test status
Simulation time 431802783 ps
CPU time 13.05 seconds
Started Jun 11 02:14:04 PM PDT 24
Finished Jun 11 02:14:20 PM PDT 24
Peak memory 219392 kb
Host smart-e99691e7-fa10-47d1-9b00-736f67311fb7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188274825 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_mubi.1188274825
Directory /workspace/29.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_digest.3161018115
Short name T810
Test name
Test status
Simulation time 363906515 ps
CPU time 10.31 seconds
Started Jun 11 02:14:01 PM PDT 24
Finished Jun 11 02:14:14 PM PDT 24
Peak memory 226548 kb
Host smart-5007b553-c1ec-4cc2-8c71-a332da830f6c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161018115 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_d
igest.3161018115
Directory /workspace/29.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_mux.967814309
Short name T312
Test name
Test status
Simulation time 331617306 ps
CPU time 8.57 seconds
Started Jun 11 02:14:04 PM PDT 24
Finished Jun 11 02:14:15 PM PDT 24
Peak memory 218728 kb
Host smart-2fd4cf47-1b55-4a18-b032-413b1e0008d3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967814309 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_mux.967814309
Directory /workspace/29.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/29.lc_ctrl_security_escalation.1584986441
Short name T361
Test name
Test status
Simulation time 364612209 ps
CPU time 9.75 seconds
Started Jun 11 02:14:01 PM PDT 24
Finished Jun 11 02:14:13 PM PDT 24
Peak memory 218756 kb
Host smart-7c21ba6d-624a-4fdb-88af-d66369752aef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584986441 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_security_escalation.1584986441
Directory /workspace/29.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/29.lc_ctrl_smoke.2251651592
Short name T63
Test name
Test status
Simulation time 16967871 ps
CPU time 1.1 seconds
Started Jun 11 02:14:03 PM PDT 24
Finished Jun 11 02:14:06 PM PDT 24
Peak memory 222200 kb
Host smart-049c0358-29ea-4582-b769-80a30edd843b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251651592 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_smoke.2251651592
Directory /workspace/29.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_failure.825955941
Short name T329
Test name
Test status
Simulation time 227622281 ps
CPU time 29.25 seconds
Started Jun 11 02:14:03 PM PDT 24
Finished Jun 11 02:14:34 PM PDT 24
Peak memory 251488 kb
Host smart-2eb0d712-f726-45ca-aa8b-30029829d510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825955941 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_failure.825955941
Directory /workspace/29.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_post_trans.1529993337
Short name T323
Test name
Test status
Simulation time 1042482916 ps
CPU time 6.03 seconds
Started Jun 11 02:14:02 PM PDT 24
Finished Jun 11 02:14:10 PM PDT 24
Peak memory 251312 kb
Host smart-4da59742-800d-4efa-b05d-003a7b2be66e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529993337 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_post_trans.1529993337
Directory /workspace/29.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/29.lc_ctrl_stress_all.715855824
Short name T689
Test name
Test status
Simulation time 35285261734 ps
CPU time 277.02 seconds
Started Jun 11 02:14:04 PM PDT 24
Finished Jun 11 02:18:43 PM PDT 24
Peak memory 284236 kb
Host smart-82f51aa6-59b1-4647-95ba-b727c8295ae2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715855824 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.lc_ctrl_stress_all.715855824
Directory /workspace/29.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.lc_ctrl_stress_all_with_rand_reset.2283107127
Short name T84
Test name
Test status
Simulation time 15560606470 ps
CPU time 320.21 seconds
Started Jun 11 02:13:58 PM PDT 24
Finished Jun 11 02:19:20 PM PDT 24
Peak memory 333468 kb
Host smart-4d2803aa-fe9d-4c97-a6c5-26956395e6f6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2283107127 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_stress_all_with_rand_reset.2283107127
Directory /workspace/29.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.lc_ctrl_volatile_unlock_smoke.41096127
Short name T22
Test name
Test status
Simulation time 55827114 ps
CPU time 1.32 seconds
Started Jun 11 02:13:58 PM PDT 24
Finished Jun 11 02:14:01 PM PDT 24
Peak memory 218236 kb
Host smart-4f1d824b-226a-4420-b49f-a28d511861b0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41096127 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vol
atile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctr
l_volatile_unlock_smoke.41096127
Directory /workspace/29.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_alert_test.1110824715
Short name T706
Test name
Test status
Simulation time 79480777 ps
CPU time 1.19 seconds
Started Jun 11 02:12:42 PM PDT 24
Finished Jun 11 02:12:44 PM PDT 24
Peak memory 209508 kb
Host smart-9e46f32e-0086-41a3-b507-a463c1d78b2b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110824715 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_alert_test.1110824715
Directory /workspace/3.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.lc_ctrl_claim_transition_if.2143214084
Short name T205
Test name
Test status
Simulation time 15442486 ps
CPU time 0.82 seconds
Started Jun 11 02:12:45 PM PDT 24
Finished Jun 11 02:12:48 PM PDT 24
Peak memory 209448 kb
Host smart-2c6fc3b2-5925-430a-8ed1-1bd39de519c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143214084 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_claim_transition_if.2143214084
Directory /workspace/3.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/3.lc_ctrl_errors.2772252662
Short name T830
Test name
Test status
Simulation time 2962101207 ps
CPU time 9.28 seconds
Started Jun 11 02:12:44 PM PDT 24
Finished Jun 11 02:12:55 PM PDT 24
Peak memory 219464 kb
Host smart-5892fdc7-8af3-400e-abbc-3ab84297c530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772252662 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_errors.2772252662
Directory /workspace/3.lc_ctrl_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_access.3893715974
Short name T181
Test name
Test status
Simulation time 997550839 ps
CPU time 9.32 seconds
Started Jun 11 02:12:43 PM PDT 24
Finished Jun 11 02:12:53 PM PDT 24
Peak memory 217704 kb
Host smart-d0b84ae2-72a7-48b5-8e66-da85076de2d6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893715974 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_access.3893715974
Directory /workspace/3.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_errors.3158377983
Short name T791
Test name
Test status
Simulation time 14725857134 ps
CPU time 41.51 seconds
Started Jun 11 02:12:43 PM PDT 24
Finished Jun 11 02:13:27 PM PDT 24
Peak memory 219372 kb
Host smart-3f34b75b-8c48-40c9-9382-fd94fd052a73
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158377983 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_er
rors.3158377983
Directory /workspace/3.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_priority.2533150032
Short name T833
Test name
Test status
Simulation time 423188530 ps
CPU time 2.85 seconds
Started Jun 11 02:12:42 PM PDT 24
Finished Jun 11 02:12:47 PM PDT 24
Peak memory 217780 kb
Host smart-5733bcb7-8e9f-46b0-91a3-9ffcfc0c8cdd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533150032 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_priority.2
533150032
Directory /workspace/3.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_prog_failure.3913348931
Short name T286
Test name
Test status
Simulation time 1373284024 ps
CPU time 9.16 seconds
Started Jun 11 02:12:42 PM PDT 24
Finished Jun 11 02:12:53 PM PDT 24
Peak memory 218708 kb
Host smart-ef079a5d-988f-4e53-b18d-6861c4dcc599
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913348931 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag
_prog_failure.3913348931
Directory /workspace/3.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_regwen_during_op.2671271539
Short name T866
Test name
Test status
Simulation time 788071347 ps
CPU time 14.58 seconds
Started Jun 11 02:12:44 PM PDT 24
Finished Jun 11 02:13:00 PM PDT 24
Peak memory 218192 kb
Host smart-4b0073c6-7be4-4e13-8b03-8afe1d886959
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671271539 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_regwen_during_op.2671271539
Directory /workspace/3.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_smoke.1192086090
Short name T428
Test name
Test status
Simulation time 166255146 ps
CPU time 5.28 seconds
Started Jun 11 02:12:43 PM PDT 24
Finished Jun 11 02:12:50 PM PDT 24
Peak memory 218144 kb
Host smart-5d604a1c-1423-4a20-8a18-79e028c78faa
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192086090 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_smoke.
1192086090
Directory /workspace/3.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_failure.3922036278
Short name T403
Test name
Test status
Simulation time 3101290126 ps
CPU time 42.16 seconds
Started Jun 11 02:12:42 PM PDT 24
Finished Jun 11 02:13:25 PM PDT 24
Peak memory 276240 kb
Host smart-5ca5f544-a6a9-421a-8a62-65404cdb2768
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922036278 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jta
g_state_failure.3922036278
Directory /workspace/3.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_post_trans.2753917139
Short name T799
Test name
Test status
Simulation time 2844560551 ps
CPU time 7.21 seconds
Started Jun 11 02:12:46 PM PDT 24
Finished Jun 11 02:12:54 PM PDT 24
Peak memory 223312 kb
Host smart-f6c3cc91-992b-43e2-8eee-3a1f63531f3a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753917139 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_state_post_trans.2753917139
Directory /workspace/3.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_prog_failure.3177122181
Short name T233
Test name
Test status
Simulation time 369468866 ps
CPU time 3.2 seconds
Started Jun 11 02:12:42 PM PDT 24
Finished Jun 11 02:12:46 PM PDT 24
Peak memory 223016 kb
Host smart-2477cafa-3f86-43c6-9ae9-db3068b996a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177122181 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_prog_failure.3177122181
Directory /workspace/3.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_regwen_during_op.3270370053
Short name T277
Test name
Test status
Simulation time 2019622089 ps
CPU time 11.62 seconds
Started Jun 11 02:12:40 PM PDT 24
Finished Jun 11 02:12:53 PM PDT 24
Peak memory 214772 kb
Host smart-fde1557c-41a6-432b-acd2-b5a9f04a8efd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270370053 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_regwen_during_op.3270370053
Directory /workspace/3.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_cm.924194853
Short name T86
Test name
Test status
Simulation time 233938589 ps
CPU time 21.81 seconds
Started Jun 11 02:12:44 PM PDT 24
Finished Jun 11 02:13:07 PM PDT 24
Peak memory 269756 kb
Host smart-9544ddce-0501-42b8-8623-4ee0d28b609c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924194853 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_cm.924194853
Directory /workspace/3.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_mubi.3940175515
Short name T246
Test name
Test status
Simulation time 1638826454 ps
CPU time 20.35 seconds
Started Jun 11 02:12:44 PM PDT 24
Finished Jun 11 02:13:06 PM PDT 24
Peak memory 220416 kb
Host smart-6ddbd1fa-d0c5-4dd9-99cb-a6d160d3d9e1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940175515 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_mubi.3940175515
Directory /workspace/3.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_digest.2204118601
Short name T750
Test name
Test status
Simulation time 346004246 ps
CPU time 10.5 seconds
Started Jun 11 02:12:43 PM PDT 24
Finished Jun 11 02:12:56 PM PDT 24
Peak memory 218708 kb
Host smart-d221d896-3c93-4b9d-9a19-ac789e3e0380
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204118601 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_di
gest.2204118601
Directory /workspace/3.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_mux.104086713
Short name T373
Test name
Test status
Simulation time 406693027 ps
CPU time 9.36 seconds
Started Jun 11 02:12:43 PM PDT 24
Finished Jun 11 02:12:54 PM PDT 24
Peak memory 218912 kb
Host smart-e677e27b-7e01-42d4-b4ef-983cd2295f55
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104086713 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_mux.104086713
Directory /workspace/3.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/3.lc_ctrl_security_escalation.488066918
Short name T448
Test name
Test status
Simulation time 2594583910 ps
CPU time 13.52 seconds
Started Jun 11 02:12:44 PM PDT 24
Finished Jun 11 02:12:59 PM PDT 24
Peak memory 225984 kb
Host smart-002b12d1-3e21-4a23-a130-30fd53204cc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488066918 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_security_escalation.488066918
Directory /workspace/3.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/3.lc_ctrl_smoke.3211240096
Short name T383
Test name
Test status
Simulation time 14913530 ps
CPU time 1.22 seconds
Started Jun 11 02:12:42 PM PDT 24
Finished Jun 11 02:12:44 PM PDT 24
Peak memory 218168 kb
Host smart-0e9a380c-2eab-4645-a99c-3c3c0e43a654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211240096 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_smoke.3211240096
Directory /workspace/3.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_failure.1405472142
Short name T378
Test name
Test status
Simulation time 937137674 ps
CPU time 23.63 seconds
Started Jun 11 02:12:43 PM PDT 24
Finished Jun 11 02:13:08 PM PDT 24
Peak memory 251380 kb
Host smart-da33e84e-4d59-4790-af05-c9d0ed94a274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405472142 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_failure.1405472142
Directory /workspace/3.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_post_trans.1538247351
Short name T592
Test name
Test status
Simulation time 279070174 ps
CPU time 3.13 seconds
Started Jun 11 02:12:40 PM PDT 24
Finished Jun 11 02:12:44 PM PDT 24
Peak memory 218764 kb
Host smart-c1d130da-31e3-4cb6-af31-e0b196f9e7a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538247351 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_post_trans.1538247351
Directory /workspace/3.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_stress_all.3067330489
Short name T664
Test name
Test status
Simulation time 2138770261 ps
CPU time 62.53 seconds
Started Jun 11 02:12:41 PM PDT 24
Finished Jun 11 02:13:44 PM PDT 24
Peak memory 267824 kb
Host smart-d745dda4-80b5-488d-9745-ea71fd791fe4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067330489 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.lc_ctrl_stress_all.3067330489
Directory /workspace/3.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.lc_ctrl_volatile_unlock_smoke.3362737773
Short name T156
Test name
Test status
Simulation time 15682511 ps
CPU time 1.24 seconds
Started Jun 11 02:12:44 PM PDT 24
Finished Jun 11 02:12:47 PM PDT 24
Peak memory 212292 kb
Host smart-87d26e01-9f00-49f3-8088-7e3c35d4c0fe
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362737773 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ct
rl_volatile_unlock_smoke.3362737773
Directory /workspace/3.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_alert_test.2703842308
Short name T400
Test name
Test status
Simulation time 14498898 ps
CPU time 0.92 seconds
Started Jun 11 02:14:05 PM PDT 24
Finished Jun 11 02:14:08 PM PDT 24
Peak memory 209116 kb
Host smart-4d2b888c-3274-425e-ab78-9edd8f8225ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703842308 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_alert_test.2703842308
Directory /workspace/30.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.lc_ctrl_errors.914355373
Short name T226
Test name
Test status
Simulation time 1301766961 ps
CPU time 11.63 seconds
Started Jun 11 02:13:57 PM PDT 24
Finished Jun 11 02:14:10 PM PDT 24
Peak memory 218748 kb
Host smart-52be8321-2824-4f6f-86ad-3696dd99962e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914355373 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_errors.914355373
Directory /workspace/30.lc_ctrl_errors/latest

Test location /workspace/coverage/default/30.lc_ctrl_jtag_access.1300080918
Short name T408
Test name
Test status
Simulation time 267686427 ps
CPU time 7.7 seconds
Started Jun 11 02:14:01 PM PDT 24
Finished Jun 11 02:14:11 PM PDT 24
Peak memory 217656 kb
Host smart-f0b72b4f-c35a-4721-95a0-73066725dc40
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300080918 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_jtag_access.1300080918
Directory /workspace/30.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/30.lc_ctrl_prog_failure.296407431
Short name T764
Test name
Test status
Simulation time 64466768 ps
CPU time 3.43 seconds
Started Jun 11 02:13:58 PM PDT 24
Finished Jun 11 02:14:04 PM PDT 24
Peak memory 222848 kb
Host smart-cebfe936-cf12-43a3-ae7c-75c8dc00708c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296407431 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_prog_failure.296407431
Directory /workspace/30.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_mubi.3282680404
Short name T516
Test name
Test status
Simulation time 397590486 ps
CPU time 14.29 seconds
Started Jun 11 02:14:00 PM PDT 24
Finished Jun 11 02:14:17 PM PDT 24
Peak memory 226420 kb
Host smart-25149844-998a-41b1-8108-9262f6d8174c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282680404 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_mubi.3282680404
Directory /workspace/30.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_digest.292925202
Short name T331
Test name
Test status
Simulation time 965927907 ps
CPU time 9.25 seconds
Started Jun 11 02:14:05 PM PDT 24
Finished Jun 11 02:14:16 PM PDT 24
Peak memory 218712 kb
Host smart-6a8df21f-c0ca-4364-9771-3c4cd7ffa1fa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292925202 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_di
gest.292925202
Directory /workspace/30.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_mux.1205946443
Short name T774
Test name
Test status
Simulation time 1940982829 ps
CPU time 9.06 seconds
Started Jun 11 02:14:05 PM PDT 24
Finished Jun 11 02:14:16 PM PDT 24
Peak memory 218696 kb
Host smart-0dcaeb8d-3da5-4f47-b295-4983cdb5cda3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205946443 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_mux.
1205946443
Directory /workspace/30.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/30.lc_ctrl_security_escalation.3767533628
Short name T332
Test name
Test status
Simulation time 517125145 ps
CPU time 6.38 seconds
Started Jun 11 02:14:00 PM PDT 24
Finished Jun 11 02:14:09 PM PDT 24
Peak memory 224820 kb
Host smart-b2057210-691f-40e1-af23-e8511c8b8a9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767533628 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_security_escalation.3767533628
Directory /workspace/30.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/30.lc_ctrl_smoke.609998133
Short name T657
Test name
Test status
Simulation time 68267984 ps
CPU time 2.92 seconds
Started Jun 11 02:13:58 PM PDT 24
Finished Jun 11 02:14:02 PM PDT 24
Peak memory 215528 kb
Host smart-8475ba13-34c5-4843-a667-6bd67ed83fd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609998133 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_smoke.609998133
Directory /workspace/30.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_failure.3832826646
Short name T225
Test name
Test status
Simulation time 650532921 ps
CPU time 16.49 seconds
Started Jun 11 02:14:05 PM PDT 24
Finished Jun 11 02:14:23 PM PDT 24
Peak memory 251420 kb
Host smart-cd940dc5-1a76-4c5f-a107-792a5b9b96a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832826646 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_failure.3832826646
Directory /workspace/30.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_post_trans.230423574
Short name T468
Test name
Test status
Simulation time 145612036 ps
CPU time 8.15 seconds
Started Jun 11 02:13:59 PM PDT 24
Finished Jun 11 02:14:09 PM PDT 24
Peak memory 251404 kb
Host smart-ede19531-168e-4f6a-9292-08c16d490fd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230423574 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_post_trans.230423574
Directory /workspace/30.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all.2476494145
Short name T575
Test name
Test status
Simulation time 6067427472 ps
CPU time 38.79 seconds
Started Jun 11 02:14:12 PM PDT 24
Finished Jun 11 02:14:52 PM PDT 24
Peak memory 251484 kb
Host smart-08af6fa5-8d61-431a-b1c3-1b934bb4515e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476494145 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.lc_ctrl_stress_all.2476494145
Directory /workspace/30.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all_with_rand_reset.574976014
Short name T139
Test name
Test status
Simulation time 164926259676 ps
CPU time 742.33 seconds
Started Jun 11 02:14:10 PM PDT 24
Finished Jun 11 02:26:34 PM PDT 24
Peak memory 283960 kb
Host smart-3555c4f3-2539-4887-9731-44c4279147b9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=574976014 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_stress_all_with_rand_reset.574976014
Directory /workspace/30.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.lc_ctrl_volatile_unlock_smoke.347082563
Short name T716
Test name
Test status
Simulation time 113648818 ps
CPU time 0.91 seconds
Started Jun 11 02:14:04 PM PDT 24
Finished Jun 11 02:14:07 PM PDT 24
Peak memory 209612 kb
Host smart-cf2856a2-9d73-465a-aff2-2e3a6def3e8b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347082563 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ct
rl_volatile_unlock_smoke.347082563
Directory /workspace/30.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_alert_test.1396459648
Short name T517
Test name
Test status
Simulation time 25708020 ps
CPU time 1.38 seconds
Started Jun 11 02:14:06 PM PDT 24
Finished Jun 11 02:14:09 PM PDT 24
Peak memory 209612 kb
Host smart-39657668-1e5e-4872-9b6f-a77ccf25da2e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396459648 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_alert_test.1396459648
Directory /workspace/31.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.lc_ctrl_errors.921978211
Short name T523
Test name
Test status
Simulation time 743440412 ps
CPU time 17.1 seconds
Started Jun 11 02:14:11 PM PDT 24
Finished Jun 11 02:14:29 PM PDT 24
Peak memory 218700 kb
Host smart-7e7e941d-0962-4cbd-868e-54710f5fcb38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921978211 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_errors.921978211
Directory /workspace/31.lc_ctrl_errors/latest

Test location /workspace/coverage/default/31.lc_ctrl_jtag_access.3024799988
Short name T838
Test name
Test status
Simulation time 840457409 ps
CPU time 8.64 seconds
Started Jun 11 02:14:05 PM PDT 24
Finished Jun 11 02:14:16 PM PDT 24
Peak memory 217760 kb
Host smart-b1d6f5c0-1fc7-497f-9c32-fc86bef38c03
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024799988 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_jtag_access.3024799988
Directory /workspace/31.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/31.lc_ctrl_prog_failure.1275802536
Short name T352
Test name
Test status
Simulation time 470231663 ps
CPU time 4.76 seconds
Started Jun 11 02:14:05 PM PDT 24
Finished Jun 11 02:14:12 PM PDT 24
Peak memory 218724 kb
Host smart-4bdefcab-4b1e-46ad-8ce6-96724985bc48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275802536 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_prog_failure.1275802536
Directory /workspace/31.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_mubi.2118836224
Short name T375
Test name
Test status
Simulation time 2757313811 ps
CPU time 20.1 seconds
Started Jun 11 02:14:11 PM PDT 24
Finished Jun 11 02:14:32 PM PDT 24
Peak memory 226608 kb
Host smart-ead62d27-53c6-4199-820e-6e9e1f474c9c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118836224 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_mubi.2118836224
Directory /workspace/31.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_digest.3417532938
Short name T39
Test name
Test status
Simulation time 896786796 ps
CPU time 12.33 seconds
Started Jun 11 02:14:05 PM PDT 24
Finished Jun 11 02:14:20 PM PDT 24
Peak memory 218708 kb
Host smart-8f25f948-08f8-4665-a272-01d94847e90a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417532938 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_d
igest.3417532938
Directory /workspace/31.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_mux.314922707
Short name T580
Test name
Test status
Simulation time 337656823 ps
CPU time 8.14 seconds
Started Jun 11 02:14:06 PM PDT 24
Finished Jun 11 02:14:16 PM PDT 24
Peak memory 226180 kb
Host smart-0d47f1cf-a152-4f3b-94f6-fbc75a14df45
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314922707 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_mux.314922707
Directory /workspace/31.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/31.lc_ctrl_security_escalation.1251268822
Short name T860
Test name
Test status
Simulation time 361627479 ps
CPU time 10.1 seconds
Started Jun 11 02:14:09 PM PDT 24
Finished Jun 11 02:14:20 PM PDT 24
Peak memory 226468 kb
Host smart-ef7065f2-0d7b-4ea1-8a2e-194de8c534a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251268822 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_security_escalation.1251268822
Directory /workspace/31.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/31.lc_ctrl_smoke.720719485
Short name T73
Test name
Test status
Simulation time 99473088 ps
CPU time 2.76 seconds
Started Jun 11 02:14:05 PM PDT 24
Finished Jun 11 02:14:11 PM PDT 24
Peak memory 215272 kb
Host smart-4f4f1c1b-63c2-41bb-8ca0-8458f784f020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720719485 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_smoke.720719485
Directory /workspace/31.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_failure.1743346444
Short name T697
Test name
Test status
Simulation time 221043394 ps
CPU time 30.32 seconds
Started Jun 11 02:14:10 PM PDT 24
Finished Jun 11 02:14:41 PM PDT 24
Peak memory 251360 kb
Host smart-5b278269-5e4a-4055-aacd-95f9187640a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743346444 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_failure.1743346444
Directory /workspace/31.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_post_trans.1596083730
Short name T360
Test name
Test status
Simulation time 501837503 ps
CPU time 9.77 seconds
Started Jun 11 02:14:06 PM PDT 24
Finished Jun 11 02:14:17 PM PDT 24
Peak memory 251452 kb
Host smart-19003dc9-f998-44c2-9ca1-8c0c7313ee15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1596083730 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_post_trans.1596083730
Directory /workspace/31.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/31.lc_ctrl_stress_all.1222433875
Short name T37
Test name
Test status
Simulation time 35770763474 ps
CPU time 712.3 seconds
Started Jun 11 02:14:05 PM PDT 24
Finished Jun 11 02:26:00 PM PDT 24
Peak memory 267800 kb
Host smart-bb9f13f2-bc78-4e03-ad2e-6c550fe319aa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222433875 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.lc_ctrl_stress_all.1222433875
Directory /workspace/31.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.lc_ctrl_volatile_unlock_smoke.20272286
Short name T32
Test name
Test status
Simulation time 14300864 ps
CPU time 0.86 seconds
Started Jun 11 02:14:05 PM PDT 24
Finished Jun 11 02:14:08 PM PDT 24
Peak memory 209308 kb
Host smart-46478c1c-0b3d-4414-b99d-4a6cf185fc29
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20272286 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vol
atile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctr
l_volatile_unlock_smoke.20272286
Directory /workspace/31.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_alert_test.612402462
Short name T264
Test name
Test status
Simulation time 37345653 ps
CPU time 0.89 seconds
Started Jun 11 02:14:03 PM PDT 24
Finished Jun 11 02:14:06 PM PDT 24
Peak memory 209368 kb
Host smart-050e8e7a-0f09-4f40-93ab-51c790516cb9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612402462 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_alert_test.612402462
Directory /workspace/32.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.lc_ctrl_jtag_access.149387262
Short name T179
Test name
Test status
Simulation time 1259046798 ps
CPU time 6.71 seconds
Started Jun 11 02:14:04 PM PDT 24
Finished Jun 11 02:14:13 PM PDT 24
Peak memory 217796 kb
Host smart-6b837e69-e2f2-4b51-91a7-165ad43089b1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149387262 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_jtag_access.149387262
Directory /workspace/32.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/32.lc_ctrl_prog_failure.1416019918
Short name T268
Test name
Test status
Simulation time 90390108 ps
CPU time 3.22 seconds
Started Jun 11 02:14:06 PM PDT 24
Finished Jun 11 02:14:11 PM PDT 24
Peak memory 218664 kb
Host smart-e86da2e7-3b60-45be-9974-0cc98c0cc9d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416019918 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_prog_failure.1416019918
Directory /workspace/32.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_mubi.1491739674
Short name T302
Test name
Test status
Simulation time 851292051 ps
CPU time 13.81 seconds
Started Jun 11 02:14:05 PM PDT 24
Finished Jun 11 02:14:21 PM PDT 24
Peak memory 219312 kb
Host smart-c2f9c59a-7582-4dc9-b3f9-05256c23e71d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491739674 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_mubi.1491739674
Directory /workspace/32.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_digest.2305628376
Short name T13
Test name
Test status
Simulation time 219199195 ps
CPU time 8.32 seconds
Started Jun 11 02:14:05 PM PDT 24
Finished Jun 11 02:14:16 PM PDT 24
Peak memory 218760 kb
Host smart-ea76366c-ccea-4b1e-a1de-ccc5a8b823b7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305628376 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_d
igest.2305628376
Directory /workspace/32.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_mux.2276080404
Short name T794
Test name
Test status
Simulation time 1209514159 ps
CPU time 11.87 seconds
Started Jun 11 02:14:11 PM PDT 24
Finished Jun 11 02:14:25 PM PDT 24
Peak memory 226544 kb
Host smart-3450d9b9-44c6-4cba-9d1e-4bc2c38c48c4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276080404 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_mux.
2276080404
Directory /workspace/32.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/32.lc_ctrl_security_escalation.2636757877
Short name T759
Test name
Test status
Simulation time 221302532 ps
CPU time 7.05 seconds
Started Jun 11 02:14:06 PM PDT 24
Finished Jun 11 02:14:15 PM PDT 24
Peak memory 218444 kb
Host smart-1256b4fd-4907-4445-b48d-99ff19d4dde9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636757877 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_security_escalation.2636757877
Directory /workspace/32.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/32.lc_ctrl_smoke.4017498255
Short name T80
Test name
Test status
Simulation time 103199716 ps
CPU time 2.3 seconds
Started Jun 11 02:14:04 PM PDT 24
Finished Jun 11 02:14:08 PM PDT 24
Peak memory 218164 kb
Host smart-5751b95e-49c3-4c05-b676-864f23bb4f40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017498255 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_smoke.4017498255
Directory /workspace/32.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_failure.1635635061
Short name T704
Test name
Test status
Simulation time 232609480 ps
CPU time 29.74 seconds
Started Jun 11 02:14:05 PM PDT 24
Finished Jun 11 02:14:37 PM PDT 24
Peak memory 251444 kb
Host smart-20a3f5c2-e8fc-4a49-96d2-60cc5d57aa06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635635061 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_failure.1635635061
Directory /workspace/32.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_post_trans.2764451933
Short name T275
Test name
Test status
Simulation time 208454635 ps
CPU time 7.7 seconds
Started Jun 11 02:14:04 PM PDT 24
Finished Jun 11 02:14:13 PM PDT 24
Peak memory 247604 kb
Host smart-b160397a-19e8-4f66-a9e7-68dee348fb2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764451933 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_post_trans.2764451933
Directory /workspace/32.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all.183166754
Short name T435
Test name
Test status
Simulation time 5588298944 ps
CPU time 45.96 seconds
Started Jun 11 02:14:07 PM PDT 24
Finished Jun 11 02:14:55 PM PDT 24
Peak memory 251396 kb
Host smart-2b181000-6658-48e3-829e-9cd189cd6624
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183166754 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.lc_ctrl_stress_all.183166754
Directory /workspace/32.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.lc_ctrl_volatile_unlock_smoke.3139740701
Short name T603
Test name
Test status
Simulation time 24105249 ps
CPU time 0.94 seconds
Started Jun 11 02:14:04 PM PDT 24
Finished Jun 11 02:14:08 PM PDT 24
Peak memory 212320 kb
Host smart-fe2c8ba8-c0a3-445d-8eb8-040c309d7e1e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139740701 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_c
trl_volatile_unlock_smoke.3139740701
Directory /workspace/32.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_alert_test.3474310267
Short name T456
Test name
Test status
Simulation time 25376139 ps
CPU time 1.33 seconds
Started Jun 11 02:14:06 PM PDT 24
Finished Jun 11 02:14:09 PM PDT 24
Peak memory 209436 kb
Host smart-accd026c-35bd-49cb-a0e2-b11768d851c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474310267 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_alert_test.3474310267
Directory /workspace/33.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.lc_ctrl_errors.2290116360
Short name T280
Test name
Test status
Simulation time 242368800 ps
CPU time 12.65 seconds
Started Jun 11 02:14:06 PM PDT 24
Finished Jun 11 02:14:21 PM PDT 24
Peak memory 218724 kb
Host smart-932c1004-d162-4c72-91b4-238cbaa2b0d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290116360 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_errors.2290116360
Directory /workspace/33.lc_ctrl_errors/latest

Test location /workspace/coverage/default/33.lc_ctrl_jtag_access.2737881555
Short name T686
Test name
Test status
Simulation time 82764911 ps
CPU time 1.28 seconds
Started Jun 11 02:14:04 PM PDT 24
Finished Jun 11 02:14:08 PM PDT 24
Peak memory 217504 kb
Host smart-902fe5a1-12d1-4f20-ad3e-7e01fe48bc90
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737881555 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_jtag_access.2737881555
Directory /workspace/33.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/33.lc_ctrl_prog_failure.3448189052
Short name T653
Test name
Test status
Simulation time 109124016 ps
CPU time 2.07 seconds
Started Jun 11 02:14:08 PM PDT 24
Finished Jun 11 02:14:11 PM PDT 24
Peak memory 222712 kb
Host smart-203fb551-ca03-437b-b682-d9db27727db4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448189052 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_prog_failure.3448189052
Directory /workspace/33.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_mubi.4268142076
Short name T738
Test name
Test status
Simulation time 1032982157 ps
CPU time 10.45 seconds
Started Jun 11 02:14:05 PM PDT 24
Finished Jun 11 02:14:18 PM PDT 24
Peak memory 218812 kb
Host smart-371402e7-7579-4db1-bd31-f56ca7529ade
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268142076 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_mubi.4268142076
Directory /workspace/33.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_digest.3198096709
Short name T220
Test name
Test status
Simulation time 1137228401 ps
CPU time 7.77 seconds
Started Jun 11 02:14:10 PM PDT 24
Finished Jun 11 02:14:19 PM PDT 24
Peak memory 218664 kb
Host smart-8658a02b-b377-4f57-b869-a232df45312b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198096709 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_d
igest.3198096709
Directory /workspace/33.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_mux.3178956008
Short name T244
Test name
Test status
Simulation time 255423870 ps
CPU time 10.1 seconds
Started Jun 11 02:14:09 PM PDT 24
Finished Jun 11 02:14:21 PM PDT 24
Peak memory 218732 kb
Host smart-4fbdc461-e3d4-4301-a2f3-9a4ad31baef4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178956008 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_mux.
3178956008
Directory /workspace/33.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/33.lc_ctrl_security_escalation.948666534
Short name T514
Test name
Test status
Simulation time 2830386472 ps
CPU time 8.16 seconds
Started Jun 11 02:14:06 PM PDT 24
Finished Jun 11 02:14:16 PM PDT 24
Peak memory 226556 kb
Host smart-3c5090d1-ba2e-41d3-8fff-5af9908c2ea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948666534 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_security_escalation.948666534
Directory /workspace/33.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/33.lc_ctrl_smoke.2349273331
Short name T242
Test name
Test status
Simulation time 35094871 ps
CPU time 2.28 seconds
Started Jun 11 02:14:06 PM PDT 24
Finished Jun 11 02:14:10 PM PDT 24
Peak memory 218292 kb
Host smart-75f42282-5c0b-4b5e-80af-371342da6d85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349273331 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_smoke.2349273331
Directory /workspace/33.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_failure.2040484376
Short name T40
Test name
Test status
Simulation time 267780360 ps
CPU time 20.54 seconds
Started Jun 11 02:14:04 PM PDT 24
Finished Jun 11 02:14:27 PM PDT 24
Peak memory 251524 kb
Host smart-ae18c0dc-9c83-4e04-878b-d6cfec2ed5b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040484376 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_failure.2040484376
Directory /workspace/33.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_post_trans.399972118
Short name T153
Test name
Test status
Simulation time 406110014 ps
CPU time 6.45 seconds
Started Jun 11 02:14:03 PM PDT 24
Finished Jun 11 02:14:12 PM PDT 24
Peak memory 247388 kb
Host smart-28744efe-5309-49e3-a2f1-2189841b735d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399972118 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_post_trans.399972118
Directory /workspace/33.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all_with_rand_reset.490280347
Short name T59
Test name
Test status
Simulation time 90487467589 ps
CPU time 840.82 seconds
Started Jun 11 02:14:12 PM PDT 24
Finished Jun 11 02:28:14 PM PDT 24
Peak memory 299512 kb
Host smart-7debbe3f-1a7d-4e43-93c7-0d78553508eb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=490280347 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_stress_all_with_rand_reset.490280347
Directory /workspace/33.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.lc_ctrl_volatile_unlock_smoke.2715045455
Short name T76
Test name
Test status
Simulation time 16029629 ps
CPU time 1.05 seconds
Started Jun 11 02:14:05 PM PDT 24
Finished Jun 11 02:14:09 PM PDT 24
Peak memory 213296 kb
Host smart-28612ca5-d24f-45cb-911a-992438065a91
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715045455 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_c
trl_volatile_unlock_smoke.2715045455
Directory /workspace/33.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_alert_test.33608249
Short name T604
Test name
Test status
Simulation time 39475043 ps
CPU time 1.14 seconds
Started Jun 11 02:14:11 PM PDT 24
Finished Jun 11 02:14:14 PM PDT 24
Peak memory 209444 kb
Host smart-0c396523-4f86-4b67-9033-8d3bb23db9e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33608249 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_alert_test.33608249
Directory /workspace/34.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.lc_ctrl_errors.513094736
Short name T643
Test name
Test status
Simulation time 4658280399 ps
CPU time 18.04 seconds
Started Jun 11 02:14:12 PM PDT 24
Finished Jun 11 02:14:31 PM PDT 24
Peak memory 219488 kb
Host smart-92508791-c687-4677-8f17-3ec77b578796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513094736 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_errors.513094736
Directory /workspace/34.lc_ctrl_errors/latest

Test location /workspace/coverage/default/34.lc_ctrl_jtag_access.3165312068
Short name T471
Test name
Test status
Simulation time 1119081566 ps
CPU time 10.77 seconds
Started Jun 11 02:14:10 PM PDT 24
Finished Jun 11 02:14:22 PM PDT 24
Peak memory 217712 kb
Host smart-ae562102-b474-45ed-b1ac-3247ec3f0a25
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165312068 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_jtag_access.3165312068
Directory /workspace/34.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/34.lc_ctrl_prog_failure.544530854
Short name T374
Test name
Test status
Simulation time 43050888 ps
CPU time 2.65 seconds
Started Jun 11 02:14:06 PM PDT 24
Finished Jun 11 02:14:11 PM PDT 24
Peak memory 218664 kb
Host smart-1b6fba9a-5e1d-4ba2-b0e7-5a9f412a290e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544530854 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_prog_failure.544530854
Directory /workspace/34.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_mubi.3640148231
Short name T587
Test name
Test status
Simulation time 9151854013 ps
CPU time 12.35 seconds
Started Jun 11 02:14:06 PM PDT 24
Finished Jun 11 02:14:20 PM PDT 24
Peak memory 219852 kb
Host smart-86054c57-ec40-48eb-b402-2f7752a38aeb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640148231 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_mubi.3640148231
Directory /workspace/34.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_digest.3787983180
Short name T702
Test name
Test status
Simulation time 1900862420 ps
CPU time 12.71 seconds
Started Jun 11 02:14:12 PM PDT 24
Finished Jun 11 02:14:25 PM PDT 24
Peak memory 226544 kb
Host smart-19386ca1-4171-443d-8c9c-c30bb8ed5b8e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787983180 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_d
igest.3787983180
Directory /workspace/34.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_mux.2150770207
Short name T363
Test name
Test status
Simulation time 221466118 ps
CPU time 7.1 seconds
Started Jun 11 02:14:09 PM PDT 24
Finished Jun 11 02:14:17 PM PDT 24
Peak memory 226472 kb
Host smart-5d723465-4f1c-4a3a-a925-51eacd449dee
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150770207 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_mux.
2150770207
Directory /workspace/34.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/34.lc_ctrl_security_escalation.1837551584
Short name T851
Test name
Test status
Simulation time 224027119 ps
CPU time 10.05 seconds
Started Jun 11 02:14:06 PM PDT 24
Finished Jun 11 02:14:18 PM PDT 24
Peak memory 226520 kb
Host smart-d20fc071-4b40-4a25-bdbe-dd58e947e324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837551584 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_security_escalation.1837551584
Directory /workspace/34.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/34.lc_ctrl_smoke.1332492301
Short name T12
Test name
Test status
Simulation time 314906753 ps
CPU time 2.86 seconds
Started Jun 11 02:14:04 PM PDT 24
Finished Jun 11 02:14:09 PM PDT 24
Peak memory 214852 kb
Host smart-1bca536d-8249-4dcb-87cb-0abb7eb5c59d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332492301 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_smoke.1332492301
Directory /workspace/34.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_failure.2835252578
Short name T665
Test name
Test status
Simulation time 1725423383 ps
CPU time 23.78 seconds
Started Jun 11 02:14:06 PM PDT 24
Finished Jun 11 02:14:31 PM PDT 24
Peak memory 251608 kb
Host smart-f11c5570-58e7-466e-89b9-d217bb509ba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835252578 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_failure.2835252578
Directory /workspace/34.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_post_trans.914675592
Short name T478
Test name
Test status
Simulation time 223835245 ps
CPU time 6.48 seconds
Started Jun 11 02:14:13 PM PDT 24
Finished Jun 11 02:14:20 PM PDT 24
Peak memory 247556 kb
Host smart-6f7033cd-a5a6-4def-833b-1cd4c14687db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914675592 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_post_trans.914675592
Directory /workspace/34.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all.2332651422
Short name T742
Test name
Test status
Simulation time 3041245579 ps
CPU time 119.53 seconds
Started Jun 11 02:14:11 PM PDT 24
Finished Jun 11 02:16:11 PM PDT 24
Peak memory 284216 kb
Host smart-5c6081d4-66f3-42e2-a9e9-f71a331b4be1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332651422 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.lc_ctrl_stress_all.2332651422
Directory /workspace/34.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all_with_rand_reset.3908760233
Short name T145
Test name
Test status
Simulation time 19505550031 ps
CPU time 631.47 seconds
Started Jun 11 02:14:08 PM PDT 24
Finished Jun 11 02:24:41 PM PDT 24
Peak memory 349912 kb
Host smart-3c73191c-2b3f-4f79-881b-ac4b8d38606c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3908760233 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_stress_all_with_rand_reset.3908760233
Directory /workspace/34.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.lc_ctrl_volatile_unlock_smoke.4256733072
Short name T358
Test name
Test status
Simulation time 15824258 ps
CPU time 1.15 seconds
Started Jun 11 02:14:06 PM PDT 24
Finished Jun 11 02:14:09 PM PDT 24
Peak memory 212344 kb
Host smart-9a5ed28d-5628-43a1-8b2c-3d1068031cb2
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256733072 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_c
trl_volatile_unlock_smoke.4256733072
Directory /workspace/34.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_alert_test.197595352
Short name T673
Test name
Test status
Simulation time 24632944 ps
CPU time 0.99 seconds
Started Jun 11 02:14:17 PM PDT 24
Finished Jun 11 02:14:20 PM PDT 24
Peak memory 209504 kb
Host smart-8e945a10-d0cb-4c88-ab31-f91b0a3192d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197595352 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_alert_test.197595352
Directory /workspace/35.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.lc_ctrl_errors.3117050667
Short name T505
Test name
Test status
Simulation time 802730573 ps
CPU time 13.75 seconds
Started Jun 11 02:14:13 PM PDT 24
Finished Jun 11 02:14:28 PM PDT 24
Peak memory 218684 kb
Host smart-d95eaa88-b186-4c13-b387-8a1db44f8398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117050667 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_errors.3117050667
Directory /workspace/35.lc_ctrl_errors/latest

Test location /workspace/coverage/default/35.lc_ctrl_jtag_access.2058712603
Short name T486
Test name
Test status
Simulation time 103287543 ps
CPU time 1.35 seconds
Started Jun 11 02:14:15 PM PDT 24
Finished Jun 11 02:14:19 PM PDT 24
Peak memory 217612 kb
Host smart-5f858382-53c0-4c8e-8f5f-620c64536efb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058712603 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_jtag_access.2058712603
Directory /workspace/35.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/35.lc_ctrl_prog_failure.1069716429
Short name T427
Test name
Test status
Simulation time 37670277 ps
CPU time 2.11 seconds
Started Jun 11 02:14:15 PM PDT 24
Finished Jun 11 02:14:19 PM PDT 24
Peak memory 222840 kb
Host smart-ac53d1dc-b93c-404b-ae95-40e42f0af307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069716429 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_prog_failure.1069716429
Directory /workspace/35.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_mubi.1236934861
Short name T491
Test name
Test status
Simulation time 306107261 ps
CPU time 15.32 seconds
Started Jun 11 02:14:13 PM PDT 24
Finished Jun 11 02:14:30 PM PDT 24
Peak memory 219364 kb
Host smart-35358b60-f869-482c-8d5b-47403ee397fa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236934861 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_mubi.1236934861
Directory /workspace/35.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_digest.180221224
Short name T166
Test name
Test status
Simulation time 1036304323 ps
CPU time 8.44 seconds
Started Jun 11 02:14:13 PM PDT 24
Finished Jun 11 02:14:22 PM PDT 24
Peak memory 226504 kb
Host smart-920d7b12-0860-4bd1-b00c-933c4ca59bf4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180221224 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_di
gest.180221224
Directory /workspace/35.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_mux.2175888647
Short name T469
Test name
Test status
Simulation time 3272384329 ps
CPU time 18.31 seconds
Started Jun 11 02:14:15 PM PDT 24
Finished Jun 11 02:14:35 PM PDT 24
Peak memory 226568 kb
Host smart-3689b5d8-7dd1-432e-924e-ac5178bcc774
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175888647 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_mux.
2175888647
Directory /workspace/35.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/35.lc_ctrl_security_escalation.1085956209
Short name T640
Test name
Test status
Simulation time 211987204 ps
CPU time 8.93 seconds
Started Jun 11 02:14:19 PM PDT 24
Finished Jun 11 02:14:29 PM PDT 24
Peak memory 226536 kb
Host smart-10c886ac-df90-45e4-9012-65001acf523c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085956209 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_security_escalation.1085956209
Directory /workspace/35.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/35.lc_ctrl_smoke.3029800957
Short name T429
Test name
Test status
Simulation time 56102917 ps
CPU time 2.31 seconds
Started Jun 11 02:14:14 PM PDT 24
Finished Jun 11 02:14:18 PM PDT 24
Peak memory 214872 kb
Host smart-0158be53-ead6-4eba-9f51-d0a62094ac3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029800957 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_smoke.3029800957
Directory /workspace/35.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_failure.3468383619
Short name T503
Test name
Test status
Simulation time 636853457 ps
CPU time 27.95 seconds
Started Jun 11 02:14:14 PM PDT 24
Finished Jun 11 02:14:44 PM PDT 24
Peak memory 251468 kb
Host smart-99c52dba-cb95-45e0-b758-460ee0527067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468383619 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_failure.3468383619
Directory /workspace/35.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_post_trans.274307518
Short name T223
Test name
Test status
Simulation time 81620413 ps
CPU time 6.33 seconds
Started Jun 11 02:14:15 PM PDT 24
Finished Jun 11 02:14:23 PM PDT 24
Peak memory 247336 kb
Host smart-64a9d6d6-0507-4b1d-966d-c26fa6721e1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274307518 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_post_trans.274307518
Directory /workspace/35.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all.1411917452
Short name T805
Test name
Test status
Simulation time 15030941157 ps
CPU time 305.7 seconds
Started Jun 11 02:14:16 PM PDT 24
Finished Jun 11 02:19:24 PM PDT 24
Peak memory 284152 kb
Host smart-180c6594-5e04-4ad6-b7f2-9fc2dea20d50
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411917452 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.lc_ctrl_stress_all.1411917452
Directory /workspace/35.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all_with_rand_reset.392421756
Short name T146
Test name
Test status
Simulation time 31822742452 ps
CPU time 277.28 seconds
Started Jun 11 02:14:15 PM PDT 24
Finished Jun 11 02:18:54 PM PDT 24
Peak memory 284100 kb
Host smart-027395d2-63fd-48ee-b16b-012544b4798e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=392421756 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_stress_all_with_rand_reset.392421756
Directory /workspace/35.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.lc_ctrl_volatile_unlock_smoke.1594680474
Short name T30
Test name
Test status
Simulation time 112534897 ps
CPU time 1.12 seconds
Started Jun 11 02:14:14 PM PDT 24
Finished Jun 11 02:14:17 PM PDT 24
Peak memory 212436 kb
Host smart-8fc78a53-be52-4c55-99f4-893d1faeb940
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594680474 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_c
trl_volatile_unlock_smoke.1594680474
Directory /workspace/35.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_alert_test.4175385147
Short name T752
Test name
Test status
Simulation time 15906933 ps
CPU time 0.88 seconds
Started Jun 11 02:14:16 PM PDT 24
Finished Jun 11 02:14:19 PM PDT 24
Peak memory 209232 kb
Host smart-4e85f22d-c946-4f7b-b7d7-b8b53d5faa20
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175385147 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_alert_test.4175385147
Directory /workspace/36.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.lc_ctrl_errors.3096550977
Short name T630
Test name
Test status
Simulation time 446942348 ps
CPU time 11.6 seconds
Started Jun 11 02:14:15 PM PDT 24
Finished Jun 11 02:14:29 PM PDT 24
Peak memory 218764 kb
Host smart-3b4a33d1-c1f2-4d24-a5d5-8f8dbd2998ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096550977 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_errors.3096550977
Directory /workspace/36.lc_ctrl_errors/latest

Test location /workspace/coverage/default/36.lc_ctrl_jtag_access.487543682
Short name T27
Test name
Test status
Simulation time 868574613 ps
CPU time 11.19 seconds
Started Jun 11 02:14:16 PM PDT 24
Finished Jun 11 02:14:29 PM PDT 24
Peak memory 217888 kb
Host smart-f101d519-cc9a-4b32-b7c5-c334c68dd512
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487543682 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_jtag_access.487543682
Directory /workspace/36.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/36.lc_ctrl_prog_failure.956898248
Short name T786
Test name
Test status
Simulation time 29753396 ps
CPU time 1.47 seconds
Started Jun 11 02:14:15 PM PDT 24
Finished Jun 11 02:14:18 PM PDT 24
Peak memory 222216 kb
Host smart-8f9bc372-5538-4ed3-a290-7dd061837b22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956898248 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_prog_failure.956898248
Directory /workspace/36.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_mubi.143280199
Short name T176
Test name
Test status
Simulation time 353596462 ps
CPU time 16.93 seconds
Started Jun 11 02:14:14 PM PDT 24
Finished Jun 11 02:14:33 PM PDT 24
Peak memory 219388 kb
Host smart-9d5a3cf5-7203-40d9-be35-cd2139954b27
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143280199 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_mubi.143280199
Directory /workspace/36.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_digest.923599386
Short name T589
Test name
Test status
Simulation time 278122159 ps
CPU time 10 seconds
Started Jun 11 02:14:18 PM PDT 24
Finished Jun 11 02:14:29 PM PDT 24
Peak memory 218740 kb
Host smart-b6ebac95-e81e-45b3-abf2-ac4bab77f830
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923599386 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_di
gest.923599386
Directory /workspace/36.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/36.lc_ctrl_security_escalation.488155929
Short name T57
Test name
Test status
Simulation time 1662339075 ps
CPU time 6.78 seconds
Started Jun 11 02:14:14 PM PDT 24
Finished Jun 11 02:14:22 PM PDT 24
Peak memory 226552 kb
Host smart-125209bd-ae49-4ec8-bf47-8860aefd56c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488155929 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_security_escalation.488155929
Directory /workspace/36.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/36.lc_ctrl_smoke.133212607
Short name T75
Test name
Test status
Simulation time 59416727 ps
CPU time 2.29 seconds
Started Jun 11 02:14:16 PM PDT 24
Finished Jun 11 02:14:20 PM PDT 24
Peak memory 215256 kb
Host smart-44d1b16d-0600-417e-813d-e915247c7116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133212607 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_smoke.133212607
Directory /workspace/36.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_failure.1271922514
Short name T509
Test name
Test status
Simulation time 304126741 ps
CPU time 33.71 seconds
Started Jun 11 02:14:13 PM PDT 24
Finished Jun 11 02:14:48 PM PDT 24
Peak memory 251436 kb
Host smart-9664989d-81d3-45a5-819e-a9552e098b58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271922514 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_failure.1271922514
Directory /workspace/36.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_post_trans.612965609
Short name T674
Test name
Test status
Simulation time 116924502 ps
CPU time 7.87 seconds
Started Jun 11 02:14:14 PM PDT 24
Finished Jun 11 02:14:24 PM PDT 24
Peak memory 251424 kb
Host smart-577e53e0-039b-4ea5-a55f-a6695e9c10aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612965609 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_post_trans.612965609
Directory /workspace/36.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all.814028172
Short name T228
Test name
Test status
Simulation time 8847699573 ps
CPU time 101.41 seconds
Started Jun 11 02:14:15 PM PDT 24
Finished Jun 11 02:15:58 PM PDT 24
Peak memory 284268 kb
Host smart-402b3e0b-022b-4bf9-b326-fbe178e4ed99
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814028172 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.lc_ctrl_stress_all.814028172
Directory /workspace/36.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.lc_ctrl_volatile_unlock_smoke.329265820
Short name T74
Test name
Test status
Simulation time 25688082 ps
CPU time 1.01 seconds
Started Jun 11 02:14:12 PM PDT 24
Finished Jun 11 02:14:14 PM PDT 24
Peak memory 212328 kb
Host smart-62b206c5-1a8b-486e-b4c1-7bac187ef447
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329265820 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ct
rl_volatile_unlock_smoke.329265820
Directory /workspace/36.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_alert_test.3344588086
Short name T365
Test name
Test status
Simulation time 92866007 ps
CPU time 0.84 seconds
Started Jun 11 02:14:14 PM PDT 24
Finished Jun 11 02:14:16 PM PDT 24
Peak memory 209196 kb
Host smart-f9afa195-9403-4780-9159-347ae5be6cc5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344588086 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_alert_test.3344588086
Directory /workspace/37.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.lc_ctrl_errors.827341544
Short name T723
Test name
Test status
Simulation time 528061982 ps
CPU time 9.6 seconds
Started Jun 11 02:14:17 PM PDT 24
Finished Jun 11 02:14:28 PM PDT 24
Peak memory 218624 kb
Host smart-c6723f8c-5907-4d7a-a04d-01d2392fb299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827341544 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_errors.827341544
Directory /workspace/37.lc_ctrl_errors/latest

Test location /workspace/coverage/default/37.lc_ctrl_jtag_access.3512685261
Short name T628
Test name
Test status
Simulation time 134010668 ps
CPU time 4.18 seconds
Started Jun 11 02:14:15 PM PDT 24
Finished Jun 11 02:14:20 PM PDT 24
Peak memory 217712 kb
Host smart-34c128e0-6285-4710-ac9a-1fdaf417e2bc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512685261 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_jtag_access.3512685261
Directory /workspace/37.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/37.lc_ctrl_prog_failure.538544601
Short name T718
Test name
Test status
Simulation time 33543927 ps
CPU time 1.88 seconds
Started Jun 11 02:14:14 PM PDT 24
Finished Jun 11 02:14:18 PM PDT 24
Peak memory 222640 kb
Host smart-d8438bf9-bc61-41a3-b8cc-7318d74a6937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538544601 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_prog_failure.538544601
Directory /workspace/37.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_mubi.3338124235
Short name T364
Test name
Test status
Simulation time 685883072 ps
CPU time 13.29 seconds
Started Jun 11 02:14:16 PM PDT 24
Finished Jun 11 02:14:31 PM PDT 24
Peak memory 219464 kb
Host smart-c99e76ba-e3c4-4f55-91b1-a4f8fc1da203
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338124235 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_mubi.3338124235
Directory /workspace/37.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_digest.286298935
Short name T379
Test name
Test status
Simulation time 678492986 ps
CPU time 11.97 seconds
Started Jun 11 02:14:14 PM PDT 24
Finished Jun 11 02:14:27 PM PDT 24
Peak memory 226376 kb
Host smart-47e4a46e-9d85-467d-a873-541740b37a33
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286298935 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_di
gest.286298935
Directory /workspace/37.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_mux.1806624709
Short name T519
Test name
Test status
Simulation time 1024211314 ps
CPU time 10.75 seconds
Started Jun 11 02:14:12 PM PDT 24
Finished Jun 11 02:14:24 PM PDT 24
Peak memory 226540 kb
Host smart-7ae6eadf-7268-4569-836e-10579dc5029c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806624709 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_mux.
1806624709
Directory /workspace/37.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/37.lc_ctrl_security_escalation.3121818545
Short name T356
Test name
Test status
Simulation time 1463153101 ps
CPU time 11.61 seconds
Started Jun 11 02:14:16 PM PDT 24
Finished Jun 11 02:14:29 PM PDT 24
Peak memory 226504 kb
Host smart-7c4819b7-ae08-4e59-b42e-127262acdc08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121818545 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_security_escalation.3121818545
Directory /workspace/37.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/37.lc_ctrl_smoke.1026093538
Short name T231
Test name
Test status
Simulation time 244982418 ps
CPU time 3.45 seconds
Started Jun 11 02:14:15 PM PDT 24
Finished Jun 11 02:14:21 PM PDT 24
Peak memory 218156 kb
Host smart-bf8546c6-fdae-4e51-805c-95b39621a0f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026093538 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_smoke.1026093538
Directory /workspace/37.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_failure.1767545643
Short name T222
Test name
Test status
Simulation time 319460289 ps
CPU time 20.15 seconds
Started Jun 11 02:14:17 PM PDT 24
Finished Jun 11 02:14:38 PM PDT 24
Peak memory 251400 kb
Host smart-67e13255-4baf-4b60-8e33-72ff0cb9aa46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767545643 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_failure.1767545643
Directory /workspace/37.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_post_trans.1903567823
Short name T663
Test name
Test status
Simulation time 169965551 ps
CPU time 4.59 seconds
Started Jun 11 02:14:12 PM PDT 24
Finished Jun 11 02:14:18 PM PDT 24
Peak memory 223188 kb
Host smart-a02d6561-f80c-46b2-849b-867cf6ea7107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903567823 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_post_trans.1903567823
Directory /workspace/37.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all.3438377606
Short name T178
Test name
Test status
Simulation time 39353929949 ps
CPU time 178.28 seconds
Started Jun 11 02:14:14 PM PDT 24
Finished Jun 11 02:17:14 PM PDT 24
Peak memory 283252 kb
Host smart-5e7df4a6-74f5-4dc7-a9d1-4aa44feb86ef
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438377606 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.lc_ctrl_stress_all.3438377606
Directory /workspace/37.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.lc_ctrl_volatile_unlock_smoke.2591790808
Short name T813
Test name
Test status
Simulation time 13227805 ps
CPU time 0.95 seconds
Started Jun 11 02:14:14 PM PDT 24
Finished Jun 11 02:14:17 PM PDT 24
Peak memory 209588 kb
Host smart-9c0bab2d-e822-496d-ba8a-1ea167f52b16
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591790808 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_c
trl_volatile_unlock_smoke.2591790808
Directory /workspace/37.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_alert_test.1768241341
Short name T357
Test name
Test status
Simulation time 58773517 ps
CPU time 0.88 seconds
Started Jun 11 02:14:22 PM PDT 24
Finished Jun 11 02:14:25 PM PDT 24
Peak memory 209388 kb
Host smart-c5276e18-4480-489d-8378-d82f1765c934
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768241341 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_alert_test.1768241341
Directory /workspace/38.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.lc_ctrl_errors.1061685213
Short name T250
Test name
Test status
Simulation time 173944612 ps
CPU time 6.92 seconds
Started Jun 11 02:14:16 PM PDT 24
Finished Jun 11 02:14:25 PM PDT 24
Peak memory 218776 kb
Host smart-170c255d-85ba-4781-889b-90dc57052c7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061685213 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_errors.1061685213
Directory /workspace/38.lc_ctrl_errors/latest

Test location /workspace/coverage/default/38.lc_ctrl_prog_failure.1307521213
Short name T694
Test name
Test status
Simulation time 363140560 ps
CPU time 2.87 seconds
Started Jun 11 02:14:14 PM PDT 24
Finished Jun 11 02:14:18 PM PDT 24
Peak memory 218688 kb
Host smart-5dc938bf-a641-4702-a53c-840a02867354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307521213 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_prog_failure.1307521213
Directory /workspace/38.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_mubi.1674160845
Short name T413
Test name
Test status
Simulation time 302933441 ps
CPU time 13.47 seconds
Started Jun 11 02:14:23 PM PDT 24
Finished Jun 11 02:14:39 PM PDT 24
Peak memory 220520 kb
Host smart-c00da956-a336-4935-bcf6-3df95cb301c2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674160845 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_mubi.1674160845
Directory /workspace/38.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_digest.2665129200
Short name T420
Test name
Test status
Simulation time 495416929 ps
CPU time 9.76 seconds
Started Jun 11 02:14:24 PM PDT 24
Finished Jun 11 02:14:35 PM PDT 24
Peak memory 218744 kb
Host smart-2c2ec2c3-f35d-4295-b2f1-79af8447d7ee
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665129200 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_d
igest.2665129200
Directory /workspace/38.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_mux.1816008009
Short name T247
Test name
Test status
Simulation time 989926134 ps
CPU time 9.44 seconds
Started Jun 11 02:14:24 PM PDT 24
Finished Jun 11 02:14:35 PM PDT 24
Peak memory 218708 kb
Host smart-7db592dd-373a-4c23-87f8-21c2178f983b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816008009 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_mux.
1816008009
Directory /workspace/38.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/38.lc_ctrl_security_escalation.2151441019
Short name T614
Test name
Test status
Simulation time 413850934 ps
CPU time 9.55 seconds
Started Jun 11 02:14:14 PM PDT 24
Finished Jun 11 02:14:25 PM PDT 24
Peak memory 225796 kb
Host smart-49a4c5b3-5b71-4384-b6f6-f6df3f148778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151441019 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_security_escalation.2151441019
Directory /workspace/38.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/38.lc_ctrl_smoke.939015790
Short name T335
Test name
Test status
Simulation time 181251699 ps
CPU time 2.99 seconds
Started Jun 11 02:14:17 PM PDT 24
Finished Jun 11 02:14:22 PM PDT 24
Peak memory 215596 kb
Host smart-d22b73bc-ae05-4614-8287-51898f175fcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939015790 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_smoke.939015790
Directory /workspace/38.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_post_trans.596539243
Short name T751
Test name
Test status
Simulation time 78021266 ps
CPU time 3.19 seconds
Started Jun 11 02:14:17 PM PDT 24
Finished Jun 11 02:14:22 PM PDT 24
Peak memory 222804 kb
Host smart-157a9e2a-d125-4ecd-a298-c17db8f2735d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596539243 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_post_trans.596539243
Directory /workspace/38.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all.3979752147
Short name T155
Test name
Test status
Simulation time 3341403380 ps
CPU time 58.48 seconds
Started Jun 11 02:14:30 PM PDT 24
Finished Jun 11 02:15:29 PM PDT 24
Peak memory 251560 kb
Host smart-b5bdbac5-993a-49bb-bace-2895c4382c2a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979752147 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.lc_ctrl_stress_all.3979752147
Directory /workspace/38.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.lc_ctrl_volatile_unlock_smoke.2054446237
Short name T325
Test name
Test status
Simulation time 21841643 ps
CPU time 0.79 seconds
Started Jun 11 02:14:14 PM PDT 24
Finished Jun 11 02:14:16 PM PDT 24
Peak memory 209212 kb
Host smart-d8c9ea64-ef3a-46f1-b2ac-f5bc035f8a3f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054446237 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_c
trl_volatile_unlock_smoke.2054446237
Directory /workspace/38.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_alert_test.3824983963
Short name T11
Test name
Test status
Simulation time 22766631 ps
CPU time 0.93 seconds
Started Jun 11 02:14:22 PM PDT 24
Finished Jun 11 02:14:25 PM PDT 24
Peak memory 209460 kb
Host smart-004710ed-50b7-4c28-aab8-171f8274d7dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824983963 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_alert_test.3824983963
Directory /workspace/39.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.lc_ctrl_errors.3449036969
Short name T539
Test name
Test status
Simulation time 624281439 ps
CPU time 21.05 seconds
Started Jun 11 02:14:26 PM PDT 24
Finished Jun 11 02:14:48 PM PDT 24
Peak memory 218880 kb
Host smart-2635be71-ad25-4e76-9180-3a0d329b15b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449036969 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_errors.3449036969
Directory /workspace/39.lc_ctrl_errors/latest

Test location /workspace/coverage/default/39.lc_ctrl_jtag_access.3618334051
Short name T511
Test name
Test status
Simulation time 1784447987 ps
CPU time 10.58 seconds
Started Jun 11 02:14:30 PM PDT 24
Finished Jun 11 02:14:41 PM PDT 24
Peak memory 217868 kb
Host smart-f48cc6d6-9f6f-4a3b-92ba-d402d1702a81
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618334051 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_jtag_access.3618334051
Directory /workspace/39.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/39.lc_ctrl_prog_failure.225164194
Short name T667
Test name
Test status
Simulation time 207710680 ps
CPU time 2.41 seconds
Started Jun 11 02:14:24 PM PDT 24
Finished Jun 11 02:14:28 PM PDT 24
Peak memory 222936 kb
Host smart-cf516a05-9f8e-463e-8a56-c0b6f75f54d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225164194 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_prog_failure.225164194
Directory /workspace/39.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_mubi.2343792219
Short name T808
Test name
Test status
Simulation time 847303302 ps
CPU time 10.63 seconds
Started Jun 11 02:14:27 PM PDT 24
Finished Jun 11 02:14:39 PM PDT 24
Peak memory 218796 kb
Host smart-75af9829-67f7-4642-bc10-a15ff757a84f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343792219 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_mubi.2343792219
Directory /workspace/39.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_digest.118372150
Short name T843
Test name
Test status
Simulation time 2968179898 ps
CPU time 16.24 seconds
Started Jun 11 02:14:25 PM PDT 24
Finished Jun 11 02:14:42 PM PDT 24
Peak memory 218704 kb
Host smart-b2956863-c8a9-49dc-97da-58cf88ff8f7f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118372150 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_di
gest.118372150
Directory /workspace/39.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_mux.1787739557
Short name T728
Test name
Test status
Simulation time 334698683 ps
CPU time 7.97 seconds
Started Jun 11 02:14:31 PM PDT 24
Finished Jun 11 02:14:39 PM PDT 24
Peak memory 225244 kb
Host smart-9897d86a-4313-4efb-b508-dd019538ddbd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787739557 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_mux.
1787739557
Directory /workspace/39.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/39.lc_ctrl_security_escalation.637912002
Short name T209
Test name
Test status
Simulation time 1182139968 ps
CPU time 8.74 seconds
Started Jun 11 02:14:27 PM PDT 24
Finished Jun 11 02:14:36 PM PDT 24
Peak memory 226544 kb
Host smart-7988d6c7-557d-40be-8f9f-a376d142f715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=637912002 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_security_escalation.637912002
Directory /workspace/39.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/39.lc_ctrl_smoke.1209938930
Short name T756
Test name
Test status
Simulation time 21145730 ps
CPU time 1.55 seconds
Started Jun 11 02:14:22 PM PDT 24
Finished Jun 11 02:14:25 PM PDT 24
Peak memory 214432 kb
Host smart-f7cc1104-db67-46c6-bf90-3cec6994d7de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209938930 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_smoke.1209938930
Directory /workspace/39.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_failure.2581857610
Short name T252
Test name
Test status
Simulation time 1282738872 ps
CPU time 21.77 seconds
Started Jun 11 02:14:26 PM PDT 24
Finished Jun 11 02:14:49 PM PDT 24
Peak memory 251324 kb
Host smart-71620af3-17a0-41db-92fd-664bcab39d82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581857610 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_failure.2581857610
Directory /workspace/39.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_post_trans.10074625
Short name T510
Test name
Test status
Simulation time 458640931 ps
CPU time 13.35 seconds
Started Jun 11 02:14:22 PM PDT 24
Finished Jun 11 02:14:37 PM PDT 24
Peak memory 251360 kb
Host smart-43af498b-e12a-4557-b9e5-3c2f4f2223d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10074625 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_post_trans.10074625
Directory /workspace/39.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all.2743500871
Short name T809
Test name
Test status
Simulation time 6755371703 ps
CPU time 244.23 seconds
Started Jun 11 02:14:25 PM PDT 24
Finished Jun 11 02:18:31 PM PDT 24
Peak memory 251364 kb
Host smart-67ee5b4a-de19-4dde-9f83-4b8fff5cd4d5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743500871 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.lc_ctrl_stress_all.2743500871
Directory /workspace/39.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.lc_ctrl_volatile_unlock_smoke.2261997913
Short name T279
Test name
Test status
Simulation time 46183765 ps
CPU time 0.79 seconds
Started Jun 11 02:14:22 PM PDT 24
Finished Jun 11 02:14:24 PM PDT 24
Peak memory 209288 kb
Host smart-b0f3fe03-e792-40d8-814f-e8765e6f6038
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261997913 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_c
trl_volatile_unlock_smoke.2261997913
Directory /workspace/39.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_alert_test.2774482162
Short name T488
Test name
Test status
Simulation time 26635962 ps
CPU time 0.98 seconds
Started Jun 11 02:12:46 PM PDT 24
Finished Jun 11 02:12:49 PM PDT 24
Peak memory 209508 kb
Host smart-a8f639e0-8fb7-49b9-907d-53c7f1b47097
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774482162 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_alert_test.2774482162
Directory /workspace/4.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.lc_ctrl_errors.1895431782
Short name T304
Test name
Test status
Simulation time 263089321 ps
CPU time 9.08 seconds
Started Jun 11 02:12:42 PM PDT 24
Finished Jun 11 02:12:53 PM PDT 24
Peak memory 218716 kb
Host smart-0049ee7d-9411-4ea4-bc1a-a31e7f370508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895431782 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_errors.1895431782
Directory /workspace/4.lc_ctrl_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_access.3955336987
Short name T783
Test name
Test status
Simulation time 599319052 ps
CPU time 6.9 seconds
Started Jun 11 02:12:42 PM PDT 24
Finished Jun 11 02:12:50 PM PDT 24
Peak memory 217872 kb
Host smart-7d7f8504-77cd-4cd3-8e20-18271d5fe16a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955336987 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_access.3955336987
Directory /workspace/4.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_errors.1881953294
Short name T591
Test name
Test status
Simulation time 7703365953 ps
CPU time 46.79 seconds
Started Jun 11 02:12:44 PM PDT 24
Finished Jun 11 02:13:32 PM PDT 24
Peak memory 226556 kb
Host smart-82a3ae3b-6080-4710-ab81-af6c7b4f33a9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881953294 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_er
rors.1881953294
Directory /workspace/4.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_priority.2767042115
Short name T814
Test name
Test status
Simulation time 170924172 ps
CPU time 2.35 seconds
Started Jun 11 02:12:43 PM PDT 24
Finished Jun 11 02:12:47 PM PDT 24
Peak memory 217992 kb
Host smart-ffac9662-6541-477f-ad4d-8299a1c8c4e7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767042115 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_priority.2
767042115
Directory /workspace/4.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_prog_failure.223197764
Short name T831
Test name
Test status
Simulation time 1030376523 ps
CPU time 9.25 seconds
Started Jun 11 02:12:44 PM PDT 24
Finished Jun 11 02:12:55 PM PDT 24
Peak memory 224468 kb
Host smart-b9cca609-28f2-4f18-a7d8-c0c5d85f6808
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223197764 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_
prog_failure.223197764
Directory /workspace/4.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_regwen_during_op.1492993384
Short name T787
Test name
Test status
Simulation time 1506047782 ps
CPU time 23.82 seconds
Started Jun 11 02:12:46 PM PDT 24
Finished Jun 11 02:13:12 PM PDT 24
Peak memory 218212 kb
Host smart-27e2c240-ed2d-40fd-af50-c0cb163e2be7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492993384 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_regwen_during_op.1492993384
Directory /workspace/4.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_smoke.2737872265
Short name T609
Test name
Test status
Simulation time 643894073 ps
CPU time 3.17 seconds
Started Jun 11 02:12:42 PM PDT 24
Finished Jun 11 02:12:47 PM PDT 24
Peak memory 218216 kb
Host smart-3c87ae07-c98b-42ae-a470-3cbf86510fd3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737872265 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_smoke.
2737872265
Directory /workspace/4.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_failure.4065460419
Short name T529
Test name
Test status
Simulation time 3268844747 ps
CPU time 32.02 seconds
Started Jun 11 02:12:43 PM PDT 24
Finished Jun 11 02:13:17 PM PDT 24
Peak memory 251512 kb
Host smart-e7913c05-7097-4353-b6a8-508529afe15c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065460419 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jta
g_state_failure.4065460419
Directory /workspace/4.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_post_trans.863047079
Short name T520
Test name
Test status
Simulation time 1616170321 ps
CPU time 8.12 seconds
Started Jun 11 02:12:42 PM PDT 24
Finished Jun 11 02:12:51 PM PDT 24
Peak memory 226800 kb
Host smart-2ffea4a8-8fba-49b9-bfb7-09f64d65fce5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863047079 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_j
tag_state_post_trans.863047079
Directory /workspace/4.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_prog_failure.4082862354
Short name T476
Test name
Test status
Simulation time 351544002 ps
CPU time 1.98 seconds
Started Jun 11 02:12:42 PM PDT 24
Finished Jun 11 02:12:45 PM PDT 24
Peak memory 218620 kb
Host smart-e27896d0-d545-465c-b1d4-cbb52de6fe98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082862354 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_prog_failure.4082862354
Directory /workspace/4.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_regwen_during_op.3394052680
Short name T387
Test name
Test status
Simulation time 251091744 ps
CPU time 9.81 seconds
Started Jun 11 02:12:43 PM PDT 24
Finished Jun 11 02:12:54 PM PDT 24
Peak memory 218256 kb
Host smart-04e29f5f-1dcd-4202-88e2-18caeabdfeae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394052680 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_regwen_during_op.3394052680
Directory /workspace/4.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_cm.78694865
Short name T54
Test name
Test status
Simulation time 2615580924 ps
CPU time 39.97 seconds
Started Jun 11 02:12:43 PM PDT 24
Finished Jun 11 02:13:25 PM PDT 24
Peak memory 271664 kb
Host smart-ba1bfa41-bd42-477f-b27f-bc9c7058a4b6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78694865 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_cm.78694865
Directory /workspace/4.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_mubi.2681950881
Short name T807
Test name
Test status
Simulation time 564594912 ps
CPU time 16.73 seconds
Started Jun 11 02:12:46 PM PDT 24
Finished Jun 11 02:13:05 PM PDT 24
Peak memory 219408 kb
Host smart-8c50457a-20c2-4a54-9ea3-7c837341e3a2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681950881 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_mubi.2681950881
Directory /workspace/4.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_digest.1453249767
Short name T819
Test name
Test status
Simulation time 1223742583 ps
CPU time 12.37 seconds
Started Jun 11 02:12:44 PM PDT 24
Finished Jun 11 02:12:58 PM PDT 24
Peak memory 218728 kb
Host smart-59fdcf94-17ab-43c5-b07d-2e5f88d6ae0a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453249767 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_di
gest.1453249767
Directory /workspace/4.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_mux.2512674756
Short name T386
Test name
Test status
Simulation time 939395688 ps
CPU time 9.4 seconds
Started Jun 11 02:12:45 PM PDT 24
Finished Jun 11 02:12:56 PM PDT 24
Peak memory 218616 kb
Host smart-20d87558-618b-4eb8-b0e8-b1718fd70210
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512674756 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_mux.2
512674756
Directory /workspace/4.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/4.lc_ctrl_security_escalation.1696246813
Short name T271
Test name
Test status
Simulation time 1420343045 ps
CPU time 10.26 seconds
Started Jun 11 02:12:43 PM PDT 24
Finished Jun 11 02:12:55 PM PDT 24
Peak memory 226492 kb
Host smart-c2c04fd6-8222-4b3d-b31e-73b04ff519f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696246813 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_security_escalation.1696246813
Directory /workspace/4.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/4.lc_ctrl_smoke.923416572
Short name T173
Test name
Test status
Simulation time 180542523 ps
CPU time 3.84 seconds
Started Jun 11 02:12:41 PM PDT 24
Finished Jun 11 02:12:46 PM PDT 24
Peak memory 218212 kb
Host smart-d4f68349-928f-43f8-91e0-59f62ba8bb8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923416572 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_smoke.923416572
Directory /workspace/4.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_failure.1226467314
Short name T351
Test name
Test status
Simulation time 808614637 ps
CPU time 21.39 seconds
Started Jun 11 02:12:40 PM PDT 24
Finished Jun 11 02:13:02 PM PDT 24
Peak memory 251400 kb
Host smart-35c5a92b-9e6a-48df-9a6e-f0032d8948eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226467314 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_failure.1226467314
Directory /workspace/4.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_post_trans.1525204547
Short name T295
Test name
Test status
Simulation time 152828227 ps
CPU time 2.8 seconds
Started Jun 11 02:12:42 PM PDT 24
Finished Jun 11 02:12:47 PM PDT 24
Peak memory 226812 kb
Host smart-93c606cf-015f-4d13-b2ef-1700c4d89fb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525204547 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_post_trans.1525204547
Directory /workspace/4.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/40.lc_ctrl_alert_test.934337006
Short name T834
Test name
Test status
Simulation time 21884863 ps
CPU time 1.06 seconds
Started Jun 11 02:14:26 PM PDT 24
Finished Jun 11 02:14:28 PM PDT 24
Peak memory 209492 kb
Host smart-660a474f-3619-4d5b-8e6d-13da1c54aa23
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934337006 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_alert_test.934337006
Directory /workspace/40.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.lc_ctrl_errors.3374963661
Short name T840
Test name
Test status
Simulation time 2526871365 ps
CPU time 11.86 seconds
Started Jun 11 02:14:24 PM PDT 24
Finished Jun 11 02:14:38 PM PDT 24
Peak memory 219496 kb
Host smart-0485c871-b2b0-464a-9508-cd1e7b09d543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3374963661 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_errors.3374963661
Directory /workspace/40.lc_ctrl_errors/latest

Test location /workspace/coverage/default/40.lc_ctrl_jtag_access.3154818645
Short name T598
Test name
Test status
Simulation time 2025054072 ps
CPU time 7.14 seconds
Started Jun 11 02:14:25 PM PDT 24
Finished Jun 11 02:14:33 PM PDT 24
Peak memory 217576 kb
Host smart-e7e33fee-0a0b-469e-ba6b-ef3b1c58bf7a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154818645 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_jtag_access.3154818645
Directory /workspace/40.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/40.lc_ctrl_prog_failure.3189648072
Short name T635
Test name
Test status
Simulation time 86176013 ps
CPU time 4.34 seconds
Started Jun 11 02:14:23 PM PDT 24
Finished Jun 11 02:14:28 PM PDT 24
Peak memory 218672 kb
Host smart-d42822f3-9001-4727-af59-eb6d59e4e603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189648072 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_prog_failure.3189648072
Directory /workspace/40.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_mubi.2545198804
Short name T249
Test name
Test status
Simulation time 4362278541 ps
CPU time 13.98 seconds
Started Jun 11 02:14:28 PM PDT 24
Finished Jun 11 02:14:42 PM PDT 24
Peak memory 220496 kb
Host smart-e590cf5d-bf61-46f3-a5c5-0e345536449d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545198804 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_mubi.2545198804
Directory /workspace/40.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_digest.506178655
Short name T404
Test name
Test status
Simulation time 1994119570 ps
CPU time 17.18 seconds
Started Jun 11 02:14:24 PM PDT 24
Finished Jun 11 02:14:43 PM PDT 24
Peak memory 218700 kb
Host smart-192ecbda-9290-4f7d-97ad-6fc93358b629
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506178655 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_di
gest.506178655
Directory /workspace/40.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_mux.3885639992
Short name T550
Test name
Test status
Simulation time 442600294 ps
CPU time 11.88 seconds
Started Jun 11 02:14:24 PM PDT 24
Finished Jun 11 02:14:37 PM PDT 24
Peak memory 226528 kb
Host smart-0b819b30-cddc-43b3-a2db-131e0a0146c1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885639992 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_mux.
3885639992
Directory /workspace/40.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/40.lc_ctrl_security_escalation.1887051550
Short name T454
Test name
Test status
Simulation time 1764262071 ps
CPU time 13.78 seconds
Started Jun 11 02:14:24 PM PDT 24
Finished Jun 11 02:14:40 PM PDT 24
Peak memory 218780 kb
Host smart-4281a77c-1379-4eb8-86ca-f5ee7f2e9dd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887051550 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_security_escalation.1887051550
Directory /workspace/40.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/40.lc_ctrl_smoke.3373700040
Short name T678
Test name
Test status
Simulation time 71455526 ps
CPU time 3.79 seconds
Started Jun 11 02:14:23 PM PDT 24
Finished Jun 11 02:14:28 PM PDT 24
Peak memory 218232 kb
Host smart-02131de4-4deb-4b12-bd9d-420a327a7965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373700040 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_smoke.3373700040
Directory /workspace/40.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_failure.305917093
Short name T362
Test name
Test status
Simulation time 1057415957 ps
CPU time 27.99 seconds
Started Jun 11 02:14:30 PM PDT 24
Finished Jun 11 02:14:59 PM PDT 24
Peak memory 251424 kb
Host smart-c4a1c606-4a3a-4bc0-93d7-8d7368430b26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305917093 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_failure.305917093
Directory /workspace/40.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_post_trans.3148087471
Short name T636
Test name
Test status
Simulation time 118541478 ps
CPU time 7.18 seconds
Started Jun 11 02:14:25 PM PDT 24
Finished Jun 11 02:14:34 PM PDT 24
Peak memory 250968 kb
Host smart-5f0cd8a3-4cb1-4780-9915-3cbf42428251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148087471 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_post_trans.3148087471
Directory /workspace/40.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/40.lc_ctrl_stress_all.4213056988
Short name T177
Test name
Test status
Simulation time 11035974509 ps
CPU time 109.04 seconds
Started Jun 11 02:14:21 PM PDT 24
Finished Jun 11 02:16:11 PM PDT 24
Peak memory 251444 kb
Host smart-0a98c67c-2b66-4988-8978-841c124d4a92
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213056988 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.lc_ctrl_stress_all.4213056988
Directory /workspace/40.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.lc_ctrl_stress_all_with_rand_reset.1581189668
Short name T792
Test name
Test status
Simulation time 254730065082 ps
CPU time 511.65 seconds
Started Jun 11 02:14:23 PM PDT 24
Finished Jun 11 02:22:56 PM PDT 24
Peak memory 333584 kb
Host smart-874cd7eb-6a92-4187-9864-b5613c505ab0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1581189668 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_stress_all_with_rand_reset.1581189668
Directory /workspace/40.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.lc_ctrl_volatile_unlock_smoke.1566483369
Short name T316
Test name
Test status
Simulation time 51652232 ps
CPU time 0.82 seconds
Started Jun 11 02:14:31 PM PDT 24
Finished Jun 11 02:14:33 PM PDT 24
Peak memory 209320 kb
Host smart-1c835abe-8cdd-4304-a3a0-47e098a064eb
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566483369 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_c
trl_volatile_unlock_smoke.1566483369
Directory /workspace/40.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_alert_test.2236459178
Short name T81
Test name
Test status
Simulation time 167406810 ps
CPU time 1.18 seconds
Started Jun 11 02:14:22 PM PDT 24
Finished Jun 11 02:14:24 PM PDT 24
Peak memory 209576 kb
Host smart-df8fca91-b038-4134-851e-c490b7d27344
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236459178 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_alert_test.2236459178
Directory /workspace/41.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.lc_ctrl_errors.2040654461
Short name T232
Test name
Test status
Simulation time 866156272 ps
CPU time 16.64 seconds
Started Jun 11 02:14:24 PM PDT 24
Finished Jun 11 02:14:43 PM PDT 24
Peak memory 218604 kb
Host smart-0be26a64-1006-4191-aaea-6e1439358a5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040654461 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_errors.2040654461
Directory /workspace/41.lc_ctrl_errors/latest

Test location /workspace/coverage/default/41.lc_ctrl_jtag_access.3629194303
Short name T7
Test name
Test status
Simulation time 110294781 ps
CPU time 3.66 seconds
Started Jun 11 02:14:23 PM PDT 24
Finished Jun 11 02:14:28 PM PDT 24
Peak memory 217672 kb
Host smart-a0827bdf-0239-4a8e-b5a1-2e49b1a1c009
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629194303 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_jtag_access.3629194303
Directory /workspace/41.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/41.lc_ctrl_prog_failure.1368376666
Short name T462
Test name
Test status
Simulation time 136154355 ps
CPU time 1.67 seconds
Started Jun 11 02:14:23 PM PDT 24
Finished Jun 11 02:14:27 PM PDT 24
Peak memory 218648 kb
Host smart-ef1ef8d4-28f3-41dc-ad3e-8ca00d038ed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368376666 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_prog_failure.1368376666
Directory /workspace/41.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_mubi.279948561
Short name T530
Test name
Test status
Simulation time 975669369 ps
CPU time 17.8 seconds
Started Jun 11 02:14:31 PM PDT 24
Finished Jun 11 02:14:49 PM PDT 24
Peak memory 218740 kb
Host smart-72902a84-ce8d-418b-9ef9-cb393ba4e67f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279948561 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_mubi.279948561
Directory /workspace/41.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_digest.544672492
Short name T311
Test name
Test status
Simulation time 1502729939 ps
CPU time 11.4 seconds
Started Jun 11 02:14:27 PM PDT 24
Finished Jun 11 02:14:39 PM PDT 24
Peak memory 218744 kb
Host smart-a3284d9c-0eb1-46d0-aeeb-3ba735ab43e6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544672492 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_di
gest.544672492
Directory /workspace/41.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_mux.2800010034
Short name T342
Test name
Test status
Simulation time 344961746 ps
CPU time 8.84 seconds
Started Jun 11 02:14:21 PM PDT 24
Finished Jun 11 02:14:30 PM PDT 24
Peak memory 218728 kb
Host smart-45299781-ffe8-462e-8442-74f364c669f9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800010034 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_mux.
2800010034
Directory /workspace/41.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/41.lc_ctrl_security_escalation.1872663163
Short name T418
Test name
Test status
Simulation time 399632180 ps
CPU time 14.86 seconds
Started Jun 11 02:14:27 PM PDT 24
Finished Jun 11 02:14:43 PM PDT 24
Peak memory 225884 kb
Host smart-3dda4707-aa4e-49b5-8dec-5b5e2cf4e4a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872663163 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_security_escalation.1872663163
Directory /workspace/41.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/41.lc_ctrl_smoke.628785560
Short name T597
Test name
Test status
Simulation time 44897299 ps
CPU time 2.82 seconds
Started Jun 11 02:14:30 PM PDT 24
Finished Jun 11 02:14:34 PM PDT 24
Peak memory 215248 kb
Host smart-b0a904df-01d9-466c-8e2c-46a3e315164a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628785560 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_smoke.628785560
Directory /workspace/41.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_failure.3382122816
Short name T555
Test name
Test status
Simulation time 447513523 ps
CPU time 27.71 seconds
Started Jun 11 02:14:23 PM PDT 24
Finished Jun 11 02:14:53 PM PDT 24
Peak memory 251408 kb
Host smart-8dad10c3-b947-4c8f-9054-89a3fd5111a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382122816 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_failure.3382122816
Directory /workspace/41.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_post_trans.116029128
Short name T240
Test name
Test status
Simulation time 72992533 ps
CPU time 8.23 seconds
Started Jun 11 02:14:25 PM PDT 24
Finished Jun 11 02:14:34 PM PDT 24
Peak memory 251440 kb
Host smart-f8529239-e007-48a4-b92d-16e73f777beb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116029128 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_post_trans.116029128
Directory /workspace/41.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all.1362147723
Short name T841
Test name
Test status
Simulation time 9191997628 ps
CPU time 98.46 seconds
Started Jun 11 02:14:25 PM PDT 24
Finished Jun 11 02:16:05 PM PDT 24
Peak memory 268148 kb
Host smart-36b40db4-7c62-46ce-8dd5-195a1e399f36
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362147723 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.lc_ctrl_stress_all.1362147723
Directory /workspace/41.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.lc_ctrl_volatile_unlock_smoke.2683910601
Short name T567
Test name
Test status
Simulation time 16484787 ps
CPU time 0.79 seconds
Started Jun 11 02:14:31 PM PDT 24
Finished Jun 11 02:14:32 PM PDT 24
Peak memory 208908 kb
Host smart-3a16622e-2052-460b-88b2-f6cf158c648a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683910601 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_c
trl_volatile_unlock_smoke.2683910601
Directory /workspace/41.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_alert_test.2286243923
Short name T512
Test name
Test status
Simulation time 35397531 ps
CPU time 0.93 seconds
Started Jun 11 02:14:32 PM PDT 24
Finished Jun 11 02:14:34 PM PDT 24
Peak memory 209276 kb
Host smart-2a1e9fa2-1f70-41ec-acfe-e9b56188211e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286243923 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_alert_test.2286243923
Directory /workspace/42.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.lc_ctrl_errors.927268490
Short name T608
Test name
Test status
Simulation time 1412935821 ps
CPU time 12.55 seconds
Started Jun 11 02:14:35 PM PDT 24
Finished Jun 11 02:14:49 PM PDT 24
Peak memory 218692 kb
Host smart-d45dbbc4-50fe-4d03-8016-38d8d72ca786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927268490 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_errors.927268490
Directory /workspace/42.lc_ctrl_errors/latest

Test location /workspace/coverage/default/42.lc_ctrl_jtag_access.902266999
Short name T839
Test name
Test status
Simulation time 2674689224 ps
CPU time 15.63 seconds
Started Jun 11 02:14:32 PM PDT 24
Finished Jun 11 02:14:50 PM PDT 24
Peak memory 218076 kb
Host smart-87bef59a-f67f-4343-ba20-5b2b5249f51f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902266999 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_jtag_access.902266999
Directory /workspace/42.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/42.lc_ctrl_prog_failure.885628616
Short name T439
Test name
Test status
Simulation time 90476995 ps
CPU time 3.14 seconds
Started Jun 11 02:14:32 PM PDT 24
Finished Jun 11 02:14:36 PM PDT 24
Peak memory 222936 kb
Host smart-0c59de0c-d7a7-4d77-abdd-a5d0abcf96f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885628616 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_prog_failure.885628616
Directory /workspace/42.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_mubi.691377553
Short name T754
Test name
Test status
Simulation time 1055654026 ps
CPU time 12.89 seconds
Started Jun 11 02:14:31 PM PDT 24
Finished Jun 11 02:14:46 PM PDT 24
Peak memory 218760 kb
Host smart-caa0b3c9-6086-4043-9b4a-5a322b580a83
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691377553 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_mubi.691377553
Directory /workspace/42.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_digest.1639167274
Short name T487
Test name
Test status
Simulation time 328842158 ps
CPU time 9.39 seconds
Started Jun 11 02:14:31 PM PDT 24
Finished Jun 11 02:14:42 PM PDT 24
Peak memory 218712 kb
Host smart-743f9ea0-97ff-4eb2-a3ab-3eb892a31e17
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639167274 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_d
igest.1639167274
Directory /workspace/42.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_mux.4089986205
Short name T281
Test name
Test status
Simulation time 430776673 ps
CPU time 10.75 seconds
Started Jun 11 02:14:32 PM PDT 24
Finished Jun 11 02:14:44 PM PDT 24
Peak memory 218668 kb
Host smart-1d00303d-e917-4a3a-b298-bd80a7fb3031
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089986205 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_mux.
4089986205
Directory /workspace/42.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/42.lc_ctrl_security_escalation.2159975465
Short name T590
Test name
Test status
Simulation time 373598070 ps
CPU time 9.07 seconds
Started Jun 11 02:14:32 PM PDT 24
Finished Jun 11 02:14:43 PM PDT 24
Peak memory 218672 kb
Host smart-55f153fd-3b87-4595-99ac-6c9fa1c8ae4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159975465 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_security_escalation.2159975465
Directory /workspace/42.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/42.lc_ctrl_smoke.3689932706
Short name T714
Test name
Test status
Simulation time 48628889 ps
CPU time 1.79 seconds
Started Jun 11 02:14:23 PM PDT 24
Finished Jun 11 02:14:27 PM PDT 24
Peak memory 218168 kb
Host smart-a9b04c9c-c570-4cb7-8f72-529ff4182c27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689932706 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_smoke.3689932706
Directory /workspace/42.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_failure.1680397525
Short name T472
Test name
Test status
Simulation time 1245085186 ps
CPU time 26.09 seconds
Started Jun 11 02:14:31 PM PDT 24
Finished Jun 11 02:14:59 PM PDT 24
Peak memory 251428 kb
Host smart-57c456c5-92b4-49f6-a58e-3ae21f4b2a6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680397525 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_failure.1680397525
Directory /workspace/42.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_post_trans.103035600
Short name T369
Test name
Test status
Simulation time 167069187 ps
CPU time 6.6 seconds
Started Jun 11 02:14:32 PM PDT 24
Finished Jun 11 02:14:40 PM PDT 24
Peak memory 251236 kb
Host smart-88cb3235-7a0d-4bce-bb52-e3588a489fae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103035600 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_post_trans.103035600
Directory /workspace/42.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/42.lc_ctrl_stress_all.751921599
Short name T837
Test name
Test status
Simulation time 8459811186 ps
CPU time 73.63 seconds
Started Jun 11 02:14:31 PM PDT 24
Finished Jun 11 02:15:46 PM PDT 24
Peak memory 270588 kb
Host smart-56205412-63e6-499c-9488-0dc600b665a3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751921599 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.lc_ctrl_stress_all.751921599
Directory /workspace/42.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.lc_ctrl_volatile_unlock_smoke.2768189569
Short name T96
Test name
Test status
Simulation time 18812118 ps
CPU time 0.92 seconds
Started Jun 11 02:14:34 PM PDT 24
Finished Jun 11 02:14:36 PM PDT 24
Peak memory 209592 kb
Host smart-dce991e7-435b-4e41-bdaa-466f9bea20b3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768189569 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_c
trl_volatile_unlock_smoke.2768189569
Directory /workspace/42.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_alert_test.2832377564
Short name T596
Test name
Test status
Simulation time 73565006 ps
CPU time 0.97 seconds
Started Jun 11 02:14:37 PM PDT 24
Finished Jun 11 02:14:39 PM PDT 24
Peak memory 209412 kb
Host smart-0ffbd1ea-bfe1-4607-bc57-bef7209e1e33
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832377564 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_alert_test.2832377564
Directory /workspace/43.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.lc_ctrl_errors.469799118
Short name T34
Test name
Test status
Simulation time 294537729 ps
CPU time 12.57 seconds
Started Jun 11 02:14:31 PM PDT 24
Finished Jun 11 02:14:45 PM PDT 24
Peak memory 218732 kb
Host smart-743957cd-0f77-41ec-9859-cdad09f3e508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469799118 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_errors.469799118
Directory /workspace/43.lc_ctrl_errors/latest

Test location /workspace/coverage/default/43.lc_ctrl_jtag_access.3695427917
Short name T453
Test name
Test status
Simulation time 2132563646 ps
CPU time 3.01 seconds
Started Jun 11 02:14:32 PM PDT 24
Finished Jun 11 02:14:37 PM PDT 24
Peak memory 217680 kb
Host smart-79a40bdb-f4ee-46e4-a703-de5c9af49428
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695427917 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_jtag_access.3695427917
Directory /workspace/43.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/43.lc_ctrl_prog_failure.1590286216
Short name T338
Test name
Test status
Simulation time 215127438 ps
CPU time 2.64 seconds
Started Jun 11 02:14:31 PM PDT 24
Finished Jun 11 02:14:34 PM PDT 24
Peak memory 218584 kb
Host smart-1d52fb3e-7094-45cf-a3ff-28881b5840ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590286216 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_prog_failure.1590286216
Directory /workspace/43.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_mubi.2054240
Short name T776
Test name
Test status
Simulation time 420397041 ps
CPU time 11.07 seconds
Started Jun 11 02:14:31 PM PDT 24
Finished Jun 11 02:14:43 PM PDT 24
Peak memory 218752 kb
Host smart-35a77edc-f978-4ec6-be2f-dd18021e50ad
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054240 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_mubi.2054240
Directory /workspace/43.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_digest.1911222529
Short name T690
Test name
Test status
Simulation time 283231147 ps
CPU time 10.74 seconds
Started Jun 11 02:14:31 PM PDT 24
Finished Jun 11 02:14:44 PM PDT 24
Peak memory 218712 kb
Host smart-a7dacfed-f15a-4081-81c1-94c7942aafc6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911222529 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_d
igest.1911222529
Directory /workspace/43.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_mux.1076176742
Short name T685
Test name
Test status
Simulation time 507500823 ps
CPU time 7.76 seconds
Started Jun 11 02:14:31 PM PDT 24
Finished Jun 11 02:14:41 PM PDT 24
Peak memory 218600 kb
Host smart-0a8a6b36-3664-47d8-8664-9b4633f2be1c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076176742 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_mux.
1076176742
Directory /workspace/43.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/43.lc_ctrl_security_escalation.1576386635
Short name T473
Test name
Test status
Simulation time 919112300 ps
CPU time 11.48 seconds
Started Jun 11 02:14:33 PM PDT 24
Finished Jun 11 02:14:46 PM PDT 24
Peak memory 226516 kb
Host smart-0cae5115-89cf-478d-8c4a-5221bbbf00c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576386635 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_security_escalation.1576386635
Directory /workspace/43.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/43.lc_ctrl_smoke.2458079933
Short name T391
Test name
Test status
Simulation time 32458761 ps
CPU time 1.15 seconds
Started Jun 11 02:14:33 PM PDT 24
Finished Jun 11 02:14:36 PM PDT 24
Peak memory 218208 kb
Host smart-65e9a716-49fd-4506-912b-31506d9769f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458079933 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_smoke.2458079933
Directory /workspace/43.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_failure.1219821511
Short name T447
Test name
Test status
Simulation time 234273580 ps
CPU time 27.86 seconds
Started Jun 11 02:14:36 PM PDT 24
Finished Jun 11 02:15:05 PM PDT 24
Peak memory 251444 kb
Host smart-3a530a07-87a1-42a1-91ef-11edb7ab4291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219821511 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_failure.1219821511
Directory /workspace/43.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_post_trans.2738727189
Short name T601
Test name
Test status
Simulation time 398050564 ps
CPU time 8.9 seconds
Started Jun 11 02:14:34 PM PDT 24
Finished Jun 11 02:14:44 PM PDT 24
Peak memory 251412 kb
Host smart-9ba7d670-4580-476f-9861-fa311e6e4ffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738727189 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_post_trans.2738727189
Directory /workspace/43.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all.142657754
Short name T683
Test name
Test status
Simulation time 11338855811 ps
CPU time 142.17 seconds
Started Jun 11 02:14:30 PM PDT 24
Finished Jun 11 02:16:53 PM PDT 24
Peak memory 278724 kb
Host smart-d376522a-1b20-45a0-9b59-3a88fe0128c0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142657754 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.lc_ctrl_stress_all.142657754
Directory /workspace/43.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.lc_ctrl_volatile_unlock_smoke.1620390359
Short name T856
Test name
Test status
Simulation time 15148885 ps
CPU time 1.04 seconds
Started Jun 11 02:14:38 PM PDT 24
Finished Jun 11 02:14:40 PM PDT 24
Peak memory 212340 kb
Host smart-c44a4a1e-8dd2-4f79-a30d-43253977bd77
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620390359 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_c
trl_volatile_unlock_smoke.1620390359
Directory /workspace/43.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_alert_test.1882255520
Short name T676
Test name
Test status
Simulation time 28169418 ps
CPU time 0.83 seconds
Started Jun 11 02:14:32 PM PDT 24
Finished Jun 11 02:14:34 PM PDT 24
Peak memory 209264 kb
Host smart-1fbb13c5-6e01-463f-8e66-cace7d38a99d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882255520 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_alert_test.1882255520
Directory /workspace/44.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.lc_ctrl_errors.2082615201
Short name T164
Test name
Test status
Simulation time 252604263 ps
CPU time 9.79 seconds
Started Jun 11 02:14:31 PM PDT 24
Finished Jun 11 02:14:41 PM PDT 24
Peak memory 218708 kb
Host smart-e2770050-69d7-4a72-a7e7-d48d8caaaab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082615201 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_errors.2082615201
Directory /workspace/44.lc_ctrl_errors/latest

Test location /workspace/coverage/default/44.lc_ctrl_jtag_access.3223044014
Short name T376
Test name
Test status
Simulation time 1966843826 ps
CPU time 9.08 seconds
Started Jun 11 02:14:29 PM PDT 24
Finished Jun 11 02:14:39 PM PDT 24
Peak memory 217616 kb
Host smart-e4b2d140-9b67-4691-8cef-e51c7395a070
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223044014 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_jtag_access.3223044014
Directory /workspace/44.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/44.lc_ctrl_prog_failure.1079017003
Short name T167
Test name
Test status
Simulation time 70921374 ps
CPU time 3.07 seconds
Started Jun 11 02:14:32 PM PDT 24
Finished Jun 11 02:14:36 PM PDT 24
Peak memory 218668 kb
Host smart-ad5448d2-672d-4974-894a-8f458390d450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079017003 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_prog_failure.1079017003
Directory /workspace/44.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_mubi.1989611458
Short name T638
Test name
Test status
Simulation time 513360710 ps
CPU time 11.39 seconds
Started Jun 11 02:14:32 PM PDT 24
Finished Jun 11 02:14:46 PM PDT 24
Peak memory 226496 kb
Host smart-b5109fdc-72bc-45ef-a469-3b187203793c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989611458 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_mubi.1989611458
Directory /workspace/44.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_digest.2317988934
Short name T230
Test name
Test status
Simulation time 1450924927 ps
CPU time 10.25 seconds
Started Jun 11 02:14:32 PM PDT 24
Finished Jun 11 02:14:44 PM PDT 24
Peak memory 226416 kb
Host smart-53234c16-2e22-4ecd-8ae5-00a2a6cd11d9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317988934 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_d
igest.2317988934
Directory /workspace/44.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_mux.423460889
Short name T525
Test name
Test status
Simulation time 841196737 ps
CPU time 7.75 seconds
Started Jun 11 02:14:32 PM PDT 24
Finished Jun 11 02:14:42 PM PDT 24
Peak memory 225660 kb
Host smart-63afde32-6405-48e0-9ab9-9e0beae24fe0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423460889 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_mux.423460889
Directory /workspace/44.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/44.lc_ctrl_security_escalation.3021649981
Short name T174
Test name
Test status
Simulation time 3210956849 ps
CPU time 9.36 seconds
Started Jun 11 02:14:31 PM PDT 24
Finished Jun 11 02:14:42 PM PDT 24
Peak memory 225912 kb
Host smart-58461195-d120-443a-af64-b4d2c257f563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021649981 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_security_escalation.3021649981
Directory /workspace/44.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/44.lc_ctrl_smoke.3079994504
Short name T553
Test name
Test status
Simulation time 117409810 ps
CPU time 1.64 seconds
Started Jun 11 02:14:32 PM PDT 24
Finished Jun 11 02:14:35 PM PDT 24
Peak memory 218212 kb
Host smart-56da2494-afd5-49aa-9c98-9f57bbd995ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079994504 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_smoke.3079994504
Directory /workspace/44.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_failure.1468065790
Short name T729
Test name
Test status
Simulation time 188584101 ps
CPU time 25.04 seconds
Started Jun 11 02:14:34 PM PDT 24
Finished Jun 11 02:15:00 PM PDT 24
Peak memory 251408 kb
Host smart-847abd2c-c041-4275-a053-b9206ac250e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468065790 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_failure.1468065790
Directory /workspace/44.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_post_trans.1536765718
Short name T822
Test name
Test status
Simulation time 1592169381 ps
CPU time 7.87 seconds
Started Jun 11 02:14:32 PM PDT 24
Finished Jun 11 02:14:42 PM PDT 24
Peak memory 251352 kb
Host smart-dc7d545f-ab95-43fc-a00b-235eec11c749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536765718 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_post_trans.1536765718
Directory /workspace/44.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/44.lc_ctrl_stress_all.2195223893
Short name T845
Test name
Test status
Simulation time 7106059227 ps
CPU time 142.51 seconds
Started Jun 11 02:14:32 PM PDT 24
Finished Jun 11 02:16:56 PM PDT 24
Peak memory 251744 kb
Host smart-4d2d6f78-0284-4383-87a9-dd3d1f0455fe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195223893 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.lc_ctrl_stress_all.2195223893
Directory /workspace/44.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.lc_ctrl_volatile_unlock_smoke.3660591972
Short name T91
Test name
Test status
Simulation time 109925538 ps
CPU time 0.99 seconds
Started Jun 11 02:14:32 PM PDT 24
Finished Jun 11 02:14:34 PM PDT 24
Peak memory 212332 kb
Host smart-a49f3d9c-27e7-42c2-b028-ae5c5b232fc8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660591972 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_c
trl_volatile_unlock_smoke.3660591972
Directory /workspace/44.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_alert_test.2690472973
Short name T495
Test name
Test status
Simulation time 20998526 ps
CPU time 1.14 seconds
Started Jun 11 02:14:34 PM PDT 24
Finished Jun 11 02:14:37 PM PDT 24
Peak memory 209432 kb
Host smart-71cdbdab-49c9-4834-9a98-c0269fbbcc81
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690472973 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_alert_test.2690472973
Directory /workspace/45.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.lc_ctrl_errors.817228836
Short name T820
Test name
Test status
Simulation time 314612758 ps
CPU time 14.73 seconds
Started Jun 11 02:14:31 PM PDT 24
Finished Jun 11 02:14:47 PM PDT 24
Peak memory 226572 kb
Host smart-7a1381d1-073f-4252-b27a-1a4b9f77e31d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817228836 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_errors.817228836
Directory /workspace/45.lc_ctrl_errors/latest

Test location /workspace/coverage/default/45.lc_ctrl_jtag_access.1862834910
Short name T710
Test name
Test status
Simulation time 456988332 ps
CPU time 12.23 seconds
Started Jun 11 02:14:34 PM PDT 24
Finished Jun 11 02:14:48 PM PDT 24
Peak memory 217696 kb
Host smart-2972c068-91d7-483c-92af-e91f10826131
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862834910 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_jtag_access.1862834910
Directory /workspace/45.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/45.lc_ctrl_prog_failure.400555468
Short name T333
Test name
Test status
Simulation time 97379498 ps
CPU time 3.38 seconds
Started Jun 11 02:14:34 PM PDT 24
Finished Jun 11 02:14:39 PM PDT 24
Peak memory 218688 kb
Host smart-e170c865-37a1-487c-ae4b-59701daafc71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400555468 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_prog_failure.400555468
Directory /workspace/45.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_mubi.3837564455
Short name T782
Test name
Test status
Simulation time 2745231498 ps
CPU time 17.77 seconds
Started Jun 11 02:14:32 PM PDT 24
Finished Jun 11 02:14:51 PM PDT 24
Peak memory 226608 kb
Host smart-7d57110b-5406-438c-bcca-53196aeac1ae
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837564455 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_mubi.3837564455
Directory /workspace/45.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_digest.575832134
Short name T467
Test name
Test status
Simulation time 218813390 ps
CPU time 10.12 seconds
Started Jun 11 02:14:34 PM PDT 24
Finished Jun 11 02:14:46 PM PDT 24
Peak memory 226540 kb
Host smart-d1391706-b55e-4c2e-95ce-1a2b6971aec1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575832134 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_di
gest.575832134
Directory /workspace/45.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_mux.4147013234
Short name T61
Test name
Test status
Simulation time 219133601 ps
CPU time 7.39 seconds
Started Jun 11 02:14:34 PM PDT 24
Finished Jun 11 02:14:42 PM PDT 24
Peak memory 218784 kb
Host smart-468533cf-66e8-416f-a956-fad3f8bb8ed4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147013234 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_mux.
4147013234
Directory /workspace/45.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/45.lc_ctrl_smoke.3919717794
Short name T405
Test name
Test status
Simulation time 428361385 ps
CPU time 2.03 seconds
Started Jun 11 02:14:32 PM PDT 24
Finished Jun 11 02:14:36 PM PDT 24
Peak memory 218252 kb
Host smart-eafd9f72-c315-4bc7-9d29-4994ba5dfc51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919717794 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_smoke.3919717794
Directory /workspace/45.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_failure.3219105327
Short name T370
Test name
Test status
Simulation time 912658928 ps
CPU time 26.3 seconds
Started Jun 11 02:14:34 PM PDT 24
Finished Jun 11 02:15:02 PM PDT 24
Peak memory 251432 kb
Host smart-742ee441-2b90-441f-a379-ce610005fb15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219105327 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_failure.3219105327
Directory /workspace/45.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_post_trans.2553690534
Short name T256
Test name
Test status
Simulation time 1261443097 ps
CPU time 9.01 seconds
Started Jun 11 02:14:31 PM PDT 24
Finished Jun 11 02:14:41 PM PDT 24
Peak memory 251392 kb
Host smart-835501a3-8cdb-4fe3-9d5b-8950ab20e4a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553690534 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_post_trans.2553690534
Directory /workspace/45.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/45.lc_ctrl_stress_all.2910504485
Short name T712
Test name
Test status
Simulation time 3834360521 ps
CPU time 99.38 seconds
Started Jun 11 02:14:35 PM PDT 24
Finished Jun 11 02:16:16 PM PDT 24
Peak memory 268916 kb
Host smart-cdc4c1f7-d09a-4975-85b5-feecc3e60f9e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910504485 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.lc_ctrl_stress_all.2910504485
Directory /workspace/45.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.lc_ctrl_stress_all_with_rand_reset.4214186055
Short name T99
Test name
Test status
Simulation time 21169874869 ps
CPU time 279.31 seconds
Started Jun 11 02:14:35 PM PDT 24
Finished Jun 11 02:19:15 PM PDT 24
Peak memory 284236 kb
Host smart-485a6741-ad47-4067-8e24-dd1c03473c68
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4214186055 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_stress_all_with_rand_reset.4214186055
Directory /workspace/45.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.lc_ctrl_volatile_unlock_smoke.3950360835
Short name T573
Test name
Test status
Simulation time 12011713 ps
CPU time 1.06 seconds
Started Jun 11 02:14:32 PM PDT 24
Finished Jun 11 02:14:35 PM PDT 24
Peak memory 212460 kb
Host smart-f81039ab-8d59-4750-ae71-b23d35f0f8eb
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950360835 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_c
trl_volatile_unlock_smoke.3950360835
Directory /workspace/45.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_alert_test.2967351175
Short name T612
Test name
Test status
Simulation time 30141825 ps
CPU time 0.89 seconds
Started Jun 11 02:14:43 PM PDT 24
Finished Jun 11 02:14:46 PM PDT 24
Peak memory 209176 kb
Host smart-277c7b9b-dc1e-45a9-908c-6a2918e059ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967351175 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_alert_test.2967351175
Directory /workspace/46.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.lc_ctrl_errors.3084688580
Short name T262
Test name
Test status
Simulation time 940176499 ps
CPU time 10.03 seconds
Started Jun 11 02:14:42 PM PDT 24
Finished Jun 11 02:14:54 PM PDT 24
Peak memory 218756 kb
Host smart-8024c1ad-cb57-4727-becc-f2c47aaf76d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084688580 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_errors.3084688580
Directory /workspace/46.lc_ctrl_errors/latest

Test location /workspace/coverage/default/46.lc_ctrl_jtag_access.3090741178
Short name T672
Test name
Test status
Simulation time 888782427 ps
CPU time 2.05 seconds
Started Jun 11 02:14:45 PM PDT 24
Finished Jun 11 02:14:49 PM PDT 24
Peak memory 217420 kb
Host smart-990224fd-b358-4813-acfb-de9a3c6fd32f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090741178 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_jtag_access.3090741178
Directory /workspace/46.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/46.lc_ctrl_prog_failure.305658855
Short name T622
Test name
Test status
Simulation time 59002504 ps
CPU time 3.14 seconds
Started Jun 11 02:14:42 PM PDT 24
Finished Jun 11 02:14:47 PM PDT 24
Peak memory 222616 kb
Host smart-4d7d05c0-4b50-41c1-b565-6b79bcb5a144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305658855 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_prog_failure.305658855
Directory /workspace/46.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_mubi.1383797807
Short name T633
Test name
Test status
Simulation time 1179620435 ps
CPU time 12.4 seconds
Started Jun 11 02:14:43 PM PDT 24
Finished Jun 11 02:14:57 PM PDT 24
Peak memory 219452 kb
Host smart-c0a6eae4-d7c4-4df7-b293-b231e3c95606
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383797807 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_mubi.1383797807
Directory /workspace/46.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_digest.2047350117
Short name T797
Test name
Test status
Simulation time 900454864 ps
CPU time 14.02 seconds
Started Jun 11 02:14:41 PM PDT 24
Finished Jun 11 02:14:57 PM PDT 24
Peak memory 218632 kb
Host smart-9d88b578-046d-4cb9-a618-cc900cb32b72
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047350117 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_d
igest.2047350117
Directory /workspace/46.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_mux.4218888428
Short name T798
Test name
Test status
Simulation time 3339403971 ps
CPU time 8.23 seconds
Started Jun 11 02:14:43 PM PDT 24
Finished Jun 11 02:14:53 PM PDT 24
Peak memory 218732 kb
Host smart-770dfd8f-f255-476e-8f77-ecee9d15fa4b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218888428 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_mux.
4218888428
Directory /workspace/46.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/46.lc_ctrl_security_escalation.2775681909
Short name T314
Test name
Test status
Simulation time 388704407 ps
CPU time 11.44 seconds
Started Jun 11 02:14:44 PM PDT 24
Finished Jun 11 02:14:57 PM PDT 24
Peak memory 226200 kb
Host smart-9fef9a96-5699-4c10-bd76-6aa25e240d61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775681909 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_security_escalation.2775681909
Directory /workspace/46.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/46.lc_ctrl_smoke.1132560806
Short name T549
Test name
Test status
Simulation time 93033566 ps
CPU time 3.39 seconds
Started Jun 11 02:14:34 PM PDT 24
Finished Jun 11 02:14:38 PM PDT 24
Peak memory 215420 kb
Host smart-e21564ab-2acf-47f2-9829-fe6a7e4d5ec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132560806 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_smoke.1132560806
Directory /workspace/46.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_failure.3071756127
Short name T739
Test name
Test status
Simulation time 482679454 ps
CPU time 29.24 seconds
Started Jun 11 02:14:41 PM PDT 24
Finished Jun 11 02:15:12 PM PDT 24
Peak memory 251432 kb
Host smart-d6c4e940-7a2f-4817-99e2-daa267c7da16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071756127 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_failure.3071756127
Directory /workspace/46.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_post_trans.2992190432
Short name T292
Test name
Test status
Simulation time 374497081 ps
CPU time 6.42 seconds
Started Jun 11 02:14:45 PM PDT 24
Finished Jun 11 02:14:54 PM PDT 24
Peak memory 246912 kb
Host smart-07ebf9e1-fa9e-4476-a52e-173d02996897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992190432 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_post_trans.2992190432
Directory /workspace/46.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all.1602849489
Short name T366
Test name
Test status
Simulation time 15864789321 ps
CPU time 118.46 seconds
Started Jun 11 02:14:39 PM PDT 24
Finished Jun 11 02:16:38 PM PDT 24
Peak memory 276880 kb
Host smart-d5353a20-0c1e-443a-b3e5-0ff9711fb83c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602849489 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.lc_ctrl_stress_all.1602849489
Directory /workspace/46.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.lc_ctrl_volatile_unlock_smoke.3198237246
Short name T677
Test name
Test status
Simulation time 36146967 ps
CPU time 0.72 seconds
Started Jun 11 02:14:40 PM PDT 24
Finished Jun 11 02:14:42 PM PDT 24
Peak memory 209168 kb
Host smart-5de9bfbd-1250-4488-936c-2d4cb4802fda
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198237246 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_c
trl_volatile_unlock_smoke.3198237246
Directory /workspace/46.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_alert_test.2298955932
Short name T572
Test name
Test status
Simulation time 35374267 ps
CPU time 1.41 seconds
Started Jun 11 02:14:42 PM PDT 24
Finished Jun 11 02:14:45 PM PDT 24
Peak memory 209404 kb
Host smart-d204a5a6-2033-473c-b309-75b1b0953e27
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298955932 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_alert_test.2298955932
Directory /workspace/47.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.lc_ctrl_errors.1048041524
Short name T216
Test name
Test status
Simulation time 220638100 ps
CPU time 11.92 seconds
Started Jun 11 02:14:49 PM PDT 24
Finished Jun 11 02:15:02 PM PDT 24
Peak memory 218672 kb
Host smart-40db1910-2fe4-4f5e-9357-7274f5d0d386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048041524 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_errors.1048041524
Directory /workspace/47.lc_ctrl_errors/latest

Test location /workspace/coverage/default/47.lc_ctrl_jtag_access.3242013124
Short name T556
Test name
Test status
Simulation time 246035991 ps
CPU time 2.65 seconds
Started Jun 11 02:14:45 PM PDT 24
Finished Jun 11 02:14:50 PM PDT 24
Peak memory 217576 kb
Host smart-6ed1c944-f150-42ce-afce-adb12b24156a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242013124 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_jtag_access.3242013124
Directory /workspace/47.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/47.lc_ctrl_prog_failure.3846396084
Short name T571
Test name
Test status
Simulation time 424449145 ps
CPU time 4.11 seconds
Started Jun 11 02:14:45 PM PDT 24
Finished Jun 11 02:14:52 PM PDT 24
Peak memory 218688 kb
Host smart-bc5e0e3f-74a0-4e71-985e-2c93f2b31253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846396084 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_prog_failure.3846396084
Directory /workspace/47.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_mubi.1311006368
Short name T524
Test name
Test status
Simulation time 874753253 ps
CPU time 10.51 seconds
Started Jun 11 02:14:47 PM PDT 24
Finished Jun 11 02:14:59 PM PDT 24
Peak memory 218724 kb
Host smart-1e496159-1e7d-4358-a693-d34b86e6d310
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311006368 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_mubi.1311006368
Directory /workspace/47.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_digest.26285906
Short name T465
Test name
Test status
Simulation time 2038332709 ps
CPU time 10.49 seconds
Started Jun 11 02:14:42 PM PDT 24
Finished Jun 11 02:14:54 PM PDT 24
Peak memory 226728 kb
Host smart-4ebc9ac6-5e71-4215-8b7e-e834c386487e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26285906 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_dig
est_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_dig
est.26285906
Directory /workspace/47.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_mux.3025520709
Short name T736
Test name
Test status
Simulation time 1146844192 ps
CPU time 7.31 seconds
Started Jun 11 02:14:41 PM PDT 24
Finished Jun 11 02:14:49 PM PDT 24
Peak memory 218768 kb
Host smart-21ad83c0-73ae-456c-ba72-47b4183a0622
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025520709 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_mux.
3025520709
Directory /workspace/47.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/47.lc_ctrl_security_escalation.36129910
Short name T211
Test name
Test status
Simulation time 965535065 ps
CPU time 6.85 seconds
Started Jun 11 02:14:42 PM PDT 24
Finished Jun 11 02:14:51 PM PDT 24
Peak memory 218720 kb
Host smart-331b4798-f26b-46b8-8efd-61e1886283a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36129910 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_security_escalation.36129910
Directory /workspace/47.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/47.lc_ctrl_smoke.3157502325
Short name T162
Test name
Test status
Simulation time 44099509 ps
CPU time 2.69 seconds
Started Jun 11 02:14:41 PM PDT 24
Finished Jun 11 02:14:44 PM PDT 24
Peak memory 214860 kb
Host smart-2dc3207b-60d7-43ce-ba1c-4bf093760e8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157502325 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_smoke.3157502325
Directory /workspace/47.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_failure.684161935
Short name T294
Test name
Test status
Simulation time 2158641443 ps
CPU time 30.72 seconds
Started Jun 11 02:14:43 PM PDT 24
Finished Jun 11 02:15:16 PM PDT 24
Peak memory 251540 kb
Host smart-d52b2774-54a0-405c-ad8c-79a25092d54e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684161935 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_failure.684161935
Directory /workspace/47.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_post_trans.2341977491
Short name T563
Test name
Test status
Simulation time 254175976 ps
CPU time 7.74 seconds
Started Jun 11 02:14:45 PM PDT 24
Finished Jun 11 02:14:55 PM PDT 24
Peak memory 251460 kb
Host smart-34d92eae-1860-4c81-ba29-41c0a1eb0d82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341977491 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_post_trans.2341977491
Directory /workspace/47.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/47.lc_ctrl_stress_all.953744507
Short name T836
Test name
Test status
Simulation time 14041313561 ps
CPU time 111.26 seconds
Started Jun 11 02:14:41 PM PDT 24
Finished Jun 11 02:16:34 PM PDT 24
Peak memory 220060 kb
Host smart-fb26b33e-daec-471f-b5a9-1ab7a637658e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953744507 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.lc_ctrl_stress_all.953744507
Directory /workspace/47.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.lc_ctrl_stress_all_with_rand_reset.895394163
Short name T88
Test name
Test status
Simulation time 66291297663 ps
CPU time 769.81 seconds
Started Jun 11 02:14:42 PM PDT 24
Finished Jun 11 02:27:33 PM PDT 24
Peak memory 422544 kb
Host smart-832ee576-ecea-491f-ba94-2b501e303bec
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=895394163 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_stress_all_with_rand_reset.895394163
Directory /workspace/47.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.lc_ctrl_volatile_unlock_smoke.3733441699
Short name T33
Test name
Test status
Simulation time 13309583 ps
CPU time 0.99 seconds
Started Jun 11 02:14:46 PM PDT 24
Finished Jun 11 02:14:49 PM PDT 24
Peak memory 209332 kb
Host smart-5424216d-ad7e-45f1-b70d-ae4fddedb606
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733441699 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_c
trl_volatile_unlock_smoke.3733441699
Directory /workspace/47.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_alert_test.565930485
Short name T288
Test name
Test status
Simulation time 63354319 ps
CPU time 1.22 seconds
Started Jun 11 02:14:43 PM PDT 24
Finished Jun 11 02:14:46 PM PDT 24
Peak memory 209488 kb
Host smart-363e2912-1b58-44a9-8e47-fcea181507e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565930485 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_alert_test.565930485
Directory /workspace/48.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.lc_ctrl_errors.2115473422
Short name T535
Test name
Test status
Simulation time 391507455 ps
CPU time 15.77 seconds
Started Jun 11 02:14:45 PM PDT 24
Finished Jun 11 02:15:02 PM PDT 24
Peak memory 218552 kb
Host smart-aa96b017-c972-49ee-b2d4-507d0d711eb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115473422 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_errors.2115473422
Directory /workspace/48.lc_ctrl_errors/latest

Test location /workspace/coverage/default/48.lc_ctrl_jtag_access.2568982438
Short name T449
Test name
Test status
Simulation time 473884245 ps
CPU time 6.32 seconds
Started Jun 11 02:14:44 PM PDT 24
Finished Jun 11 02:14:52 PM PDT 24
Peak memory 217800 kb
Host smart-89fad940-e3d0-4424-a1da-71a2c2848125
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568982438 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_jtag_access.2568982438
Directory /workspace/48.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/48.lc_ctrl_prog_failure.3565041483
Short name T527
Test name
Test status
Simulation time 204184565 ps
CPU time 2.73 seconds
Started Jun 11 02:14:45 PM PDT 24
Finished Jun 11 02:14:50 PM PDT 24
Peak memory 218632 kb
Host smart-96e05494-41d8-4484-9cca-6c81d444c077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565041483 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_prog_failure.3565041483
Directory /workspace/48.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_mubi.2666309140
Short name T368
Test name
Test status
Simulation time 619726485 ps
CPU time 9.34 seconds
Started Jun 11 02:14:44 PM PDT 24
Finished Jun 11 02:14:55 PM PDT 24
Peak memory 218736 kb
Host smart-28f781ee-cef9-4f22-b053-e05ca43950f3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666309140 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_mubi.2666309140
Directory /workspace/48.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_digest.1871578090
Short name T218
Test name
Test status
Simulation time 704098647 ps
CPU time 18.32 seconds
Started Jun 11 02:14:41 PM PDT 24
Finished Jun 11 02:15:01 PM PDT 24
Peak memory 218716 kb
Host smart-1d9dbe83-3dc8-4499-8db5-7683ded14636
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871578090 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_d
igest.1871578090
Directory /workspace/48.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_mux.556172476
Short name T711
Test name
Test status
Simulation time 268165359 ps
CPU time 7.69 seconds
Started Jun 11 02:14:44 PM PDT 24
Finished Jun 11 02:14:53 PM PDT 24
Peak memory 218660 kb
Host smart-f6a7166e-91d9-4447-af7b-dda33b5e5857
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556172476 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_mux.556172476
Directory /workspace/48.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/48.lc_ctrl_security_escalation.3270437797
Short name T52
Test name
Test status
Simulation time 1538148914 ps
CPU time 9.04 seconds
Started Jun 11 02:14:42 PM PDT 24
Finished Jun 11 02:14:52 PM PDT 24
Peak memory 225608 kb
Host smart-b822c0dc-7d84-4503-b100-311ef392013f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270437797 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_security_escalation.3270437797
Directory /workspace/48.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/48.lc_ctrl_smoke.2374940093
Short name T16
Test name
Test status
Simulation time 49616475 ps
CPU time 2.64 seconds
Started Jun 11 02:14:45 PM PDT 24
Finished Jun 11 02:14:50 PM PDT 24
Peak memory 218240 kb
Host smart-e1ea95e0-3ae0-4f50-96e9-8f21801a66e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374940093 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_smoke.2374940093
Directory /workspace/48.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_failure.3752091361
Short name T221
Test name
Test status
Simulation time 773284787 ps
CPU time 31.1 seconds
Started Jun 11 02:14:43 PM PDT 24
Finished Jun 11 02:15:15 PM PDT 24
Peak memory 251432 kb
Host smart-28a6ce64-5de2-45d8-981f-b5b46d79e6f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752091361 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_failure.3752091361
Directory /workspace/48.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_post_trans.2036620267
Short name T213
Test name
Test status
Simulation time 250151088 ps
CPU time 6.24 seconds
Started Jun 11 02:14:43 PM PDT 24
Finished Jun 11 02:14:51 PM PDT 24
Peak memory 247372 kb
Host smart-d0e8a41a-3f65-4cb4-8ea3-2b24e51b7155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036620267 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_post_trans.2036620267
Directory /workspace/48.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all.3855307043
Short name T766
Test name
Test status
Simulation time 53702552619 ps
CPU time 402.66 seconds
Started Jun 11 02:14:44 PM PDT 24
Finished Jun 11 02:21:29 PM PDT 24
Peak memory 317012 kb
Host smart-6c0dc14a-4ea1-47a1-bf63-f49af7b237ca
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855307043 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.lc_ctrl_stress_all.3855307043
Directory /workspace/48.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.lc_ctrl_volatile_unlock_smoke.3080583588
Short name T745
Test name
Test status
Simulation time 34795647 ps
CPU time 0.87 seconds
Started Jun 11 02:14:44 PM PDT 24
Finished Jun 11 02:14:46 PM PDT 24
Peak memory 209332 kb
Host smart-98b693d8-c3a5-45b3-8fc4-3f2150628374
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080583588 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_c
trl_volatile_unlock_smoke.3080583588
Directory /workspace/48.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_alert_test.341420505
Short name T825
Test name
Test status
Simulation time 31115043 ps
CPU time 1.13 seconds
Started Jun 11 02:14:55 PM PDT 24
Finished Jun 11 02:14:58 PM PDT 24
Peak memory 209552 kb
Host smart-31370838-890d-4c2f-99ab-7ffe3a3af496
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341420505 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_alert_test.341420505
Directory /workspace/49.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.lc_ctrl_errors.2632890559
Short name T682
Test name
Test status
Simulation time 1989440431 ps
CPU time 15.13 seconds
Started Jun 11 02:14:44 PM PDT 24
Finished Jun 11 02:15:01 PM PDT 24
Peak memory 218640 kb
Host smart-43261aaf-c0c6-4807-b8bd-81e1f462234d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632890559 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_errors.2632890559
Directory /workspace/49.lc_ctrl_errors/latest

Test location /workspace/coverage/default/49.lc_ctrl_jtag_access.604526475
Short name T781
Test name
Test status
Simulation time 670313818 ps
CPU time 7.41 seconds
Started Jun 11 02:14:44 PM PDT 24
Finished Jun 11 02:14:53 PM PDT 24
Peak memory 217724 kb
Host smart-4001c4cc-61a6-4952-a9c5-366bad26032c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604526475 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_jtag_access.604526475
Directory /workspace/49.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/49.lc_ctrl_prog_failure.611149789
Short name T443
Test name
Test status
Simulation time 64263163 ps
CPU time 3.14 seconds
Started Jun 11 02:14:42 PM PDT 24
Finished Jun 11 02:14:47 PM PDT 24
Peak memory 222844 kb
Host smart-98ab9555-bf98-45d9-833a-60cbdc95c328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611149789 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_prog_failure.611149789
Directory /workspace/49.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_mubi.3868900717
Short name T401
Test name
Test status
Simulation time 769691158 ps
CPU time 12.27 seconds
Started Jun 11 02:14:47 PM PDT 24
Finished Jun 11 02:15:01 PM PDT 24
Peak memory 226564 kb
Host smart-f6254e46-2fd6-45cd-960f-931bc37cd97e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868900717 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_mubi.3868900717
Directory /workspace/49.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_digest.1323201633
Short name T441
Test name
Test status
Simulation time 1520533607 ps
CPU time 16.81 seconds
Started Jun 11 02:14:42 PM PDT 24
Finished Jun 11 02:15:01 PM PDT 24
Peak memory 218744 kb
Host smart-4b78bc72-b7c5-4cc8-8d7a-6243e67b8b7a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323201633 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_d
igest.1323201633
Directory /workspace/49.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_mux.3955243773
Short name T865
Test name
Test status
Simulation time 738934448 ps
CPU time 5.9 seconds
Started Jun 11 02:14:43 PM PDT 24
Finished Jun 11 02:14:51 PM PDT 24
Peak memory 218716 kb
Host smart-0a1db318-c214-43ca-9c88-d98d1c722a83
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955243773 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_mux.
3955243773
Directory /workspace/49.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/49.lc_ctrl_security_escalation.1431142783
Short name T796
Test name
Test status
Simulation time 366082434 ps
CPU time 8.99 seconds
Started Jun 11 02:14:41 PM PDT 24
Finished Jun 11 02:14:52 PM PDT 24
Peak memory 218828 kb
Host smart-81144be3-27a7-463d-9b30-4c5adf117029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431142783 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_security_escalation.1431142783
Directory /workspace/49.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/49.lc_ctrl_smoke.2075892804
Short name T243
Test name
Test status
Simulation time 59945311 ps
CPU time 1.04 seconds
Started Jun 11 02:14:44 PM PDT 24
Finished Jun 11 02:14:47 PM PDT 24
Peak memory 212684 kb
Host smart-1b828574-6d57-44ca-ac56-06c6de3ddf9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075892804 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_smoke.2075892804
Directory /workspace/49.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_failure.1059078270
Short name T720
Test name
Test status
Simulation time 634848403 ps
CPU time 27.06 seconds
Started Jun 11 02:14:45 PM PDT 24
Finished Jun 11 02:15:14 PM PDT 24
Peak memory 251428 kb
Host smart-747e8cd3-2aa8-4d0c-b9af-abedaa6e5865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059078270 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_failure.1059078270
Directory /workspace/49.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_post_trans.805470339
Short name T168
Test name
Test status
Simulation time 393828439 ps
CPU time 9.28 seconds
Started Jun 11 02:14:46 PM PDT 24
Finished Jun 11 02:14:57 PM PDT 24
Peak memory 251408 kb
Host smart-9b49f6bf-02e3-44cc-af44-f8557373f0f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805470339 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_post_trans.805470339
Directory /workspace/49.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/49.lc_ctrl_stress_all.4018516917
Short name T605
Test name
Test status
Simulation time 6474474064 ps
CPU time 171 seconds
Started Jun 11 02:14:43 PM PDT 24
Finished Jun 11 02:17:35 PM PDT 24
Peak memory 422416 kb
Host smart-fa238cd2-33f9-4e03-9887-34e166762103
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018516917 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.lc_ctrl_stress_all.4018516917
Directory /workspace/49.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.lc_ctrl_volatile_unlock_smoke.1844075221
Short name T322
Test name
Test status
Simulation time 16201613 ps
CPU time 0.93 seconds
Started Jun 11 02:14:44 PM PDT 24
Finished Jun 11 02:14:47 PM PDT 24
Peak memory 209420 kb
Host smart-6b40dcf9-8b83-4771-8bdc-44291115ed9c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844075221 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_c
trl_volatile_unlock_smoke.1844075221
Directory /workspace/49.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_alert_test.804701308
Short name T607
Test name
Test status
Simulation time 31560850 ps
CPU time 1.11 seconds
Started Jun 11 02:12:55 PM PDT 24
Finished Jun 11 02:12:59 PM PDT 24
Peak memory 209348 kb
Host smart-964dabe7-767d-4284-8c05-7624e085ef35
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804701308 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_alert_test.804701308
Directory /workspace/5.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.lc_ctrl_claim_transition_if.75747948
Short name T698
Test name
Test status
Simulation time 27869706 ps
CPU time 0.83 seconds
Started Jun 11 02:12:48 PM PDT 24
Finished Jun 11 02:12:50 PM PDT 24
Peak memory 209236 kb
Host smart-852ff1c4-befa-4e94-8849-9f31b5bf5f36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75747948 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_claim_transition_if.75747948
Directory /workspace/5.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/5.lc_ctrl_errors.1048497674
Short name T660
Test name
Test status
Simulation time 526487420 ps
CPU time 13.52 seconds
Started Jun 11 02:12:45 PM PDT 24
Finished Jun 11 02:13:00 PM PDT 24
Peak memory 218676 kb
Host smart-adb6fbee-91a9-4c4e-9808-74a76c7cd0b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048497674 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_errors.1048497674
Directory /workspace/5.lc_ctrl_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_access.1508650803
Short name T8
Test name
Test status
Simulation time 1431249326 ps
CPU time 12.88 seconds
Started Jun 11 02:12:55 PM PDT 24
Finished Jun 11 02:13:11 PM PDT 24
Peak memory 217980 kb
Host smart-71ca383a-f8a4-4af5-bb77-fdbcb38a2e0e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508650803 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_access.1508650803
Directory /workspace/5.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_errors.845189576
Short name T508
Test name
Test status
Simulation time 3023005910 ps
CPU time 79.45 seconds
Started Jun 11 02:12:44 PM PDT 24
Finished Jun 11 02:14:05 PM PDT 24
Peak memory 218768 kb
Host smart-76804451-77ed-44b1-b191-62347456d1c6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845189576 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_err
ors.845189576
Directory /workspace/5.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_priority.3682828410
Short name T497
Test name
Test status
Simulation time 258799665 ps
CPU time 3.53 seconds
Started Jun 11 02:12:56 PM PDT 24
Finished Jun 11 02:13:02 PM PDT 24
Peak memory 217928 kb
Host smart-b703483a-e0f3-45a5-bf84-452aba9abef8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682828410 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_priority.3
682828410
Directory /workspace/5.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_prog_failure.28479079
Short name T687
Test name
Test status
Simulation time 1086490836 ps
CPU time 6.4 seconds
Started Jun 11 02:12:45 PM PDT 24
Finished Jun 11 02:12:53 PM PDT 24
Peak memory 218716 kb
Host smart-7c2f9243-4b55-47a9-809c-a1408b65ed4f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28479079 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_p
rog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_p
rog_failure.28479079
Directory /workspace/5.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_regwen_during_op.1466628775
Short name T452
Test name
Test status
Simulation time 1063874663 ps
CPU time 17.34 seconds
Started Jun 11 02:12:52 PM PDT 24
Finished Jun 11 02:13:11 PM PDT 24
Peak memory 218224 kb
Host smart-b8c769fa-a8d7-40c2-9392-f4cd76b499bf
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466628775 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_regwen_during_op.1466628775
Directory /workspace/5.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_smoke.1380915825
Short name T388
Test name
Test status
Simulation time 1443218328 ps
CPU time 3.2 seconds
Started Jun 11 02:12:43 PM PDT 24
Finished Jun 11 02:12:48 PM PDT 24
Peak memory 218212 kb
Host smart-aa72f811-d740-483e-9c36-1cb6e72a0e3a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380915825 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_smoke.
1380915825
Directory /workspace/5.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_failure.1788156275
Short name T276
Test name
Test status
Simulation time 2059752842 ps
CPU time 39.28 seconds
Started Jun 11 02:12:44 PM PDT 24
Finished Jun 11 02:13:25 PM PDT 24
Peak memory 274508 kb
Host smart-3c02ccf4-7b27-4b5c-b8ec-ece387f256b6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788156275 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jta
g_state_failure.1788156275
Directory /workspace/5.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_post_trans.4293734243
Short name T172
Test name
Test status
Simulation time 941486860 ps
CPU time 18.46 seconds
Started Jun 11 02:12:46 PM PDT 24
Finished Jun 11 02:13:06 PM PDT 24
Peak memory 251200 kb
Host smart-27c0cb01-9170-403b-ae2c-326331e15429
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293734243 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_state_post_trans.4293734243
Directory /workspace/5.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_prog_failure.1100761862
Short name T559
Test name
Test status
Simulation time 106457435 ps
CPU time 2.27 seconds
Started Jun 11 02:12:43 PM PDT 24
Finished Jun 11 02:12:47 PM PDT 24
Peak memory 218660 kb
Host smart-864044ec-e2e1-4e20-be95-b807020582a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100761862 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_prog_failure.1100761862
Directory /workspace/5.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_regwen_during_op.4211918140
Short name T735
Test name
Test status
Simulation time 3540378833 ps
CPU time 11.2 seconds
Started Jun 11 02:12:46 PM PDT 24
Finished Jun 11 02:12:59 PM PDT 24
Peak memory 218284 kb
Host smart-7ba5660f-1bfa-4a94-bff3-7b780c5d6515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211918140 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_regwen_during_op.4211918140
Directory /workspace/5.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_mubi.2091490971
Short name T45
Test name
Test status
Simulation time 705863853 ps
CPU time 9.83 seconds
Started Jun 11 02:12:56 PM PDT 24
Finished Jun 11 02:13:09 PM PDT 24
Peak memory 218820 kb
Host smart-46c9fc90-5045-472d-b192-49a7f6760287
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091490971 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_mubi.2091490971
Directory /workspace/5.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_digest.3728231146
Short name T864
Test name
Test status
Simulation time 546528506 ps
CPU time 10.81 seconds
Started Jun 11 02:12:52 PM PDT 24
Finished Jun 11 02:13:05 PM PDT 24
Peak memory 226540 kb
Host smart-0d158164-782e-42da-b62d-839666eda284
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728231146 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_di
gest.3728231146
Directory /workspace/5.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_mux.2924829817
Short name T390
Test name
Test status
Simulation time 1709012645 ps
CPU time 8.91 seconds
Started Jun 11 02:12:53 PM PDT 24
Finished Jun 11 02:13:04 PM PDT 24
Peak memory 218740 kb
Host smart-a147ea46-b24e-4d8f-93eb-d1617d0e330f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924829817 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_mux.2
924829817
Directory /workspace/5.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/5.lc_ctrl_security_escalation.2701342467
Short name T50
Test name
Test status
Simulation time 573416897 ps
CPU time 11.85 seconds
Started Jun 11 02:12:43 PM PDT 24
Finished Jun 11 02:12:57 PM PDT 24
Peak memory 226448 kb
Host smart-d43616f0-0355-4ad8-890d-5d86eac9170b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701342467 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_security_escalation.2701342467
Directory /workspace/5.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/5.lc_ctrl_smoke.2932624954
Short name T627
Test name
Test status
Simulation time 370541241 ps
CPU time 1.88 seconds
Started Jun 11 02:12:46 PM PDT 24
Finished Jun 11 02:12:49 PM PDT 24
Peak memory 223952 kb
Host smart-a1b66963-12d0-4677-8a03-eb9de98c6ddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932624954 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_smoke.2932624954
Directory /workspace/5.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_failure.3858767854
Short name T577
Test name
Test status
Simulation time 762541449 ps
CPU time 26.75 seconds
Started Jun 11 02:12:48 PM PDT 24
Finished Jun 11 02:13:16 PM PDT 24
Peak memory 251420 kb
Host smart-25b205c6-59db-4bf2-92f4-519092eaca00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858767854 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_failure.3858767854
Directory /workspace/5.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_post_trans.2691617533
Short name T317
Test name
Test status
Simulation time 178395019 ps
CPU time 7.09 seconds
Started Jun 11 02:12:46 PM PDT 24
Finished Jun 11 02:12:54 PM PDT 24
Peak memory 251408 kb
Host smart-d2f8a280-14ed-4ec9-8539-af5100db00b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691617533 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_post_trans.2691617533
Directory /workspace/5.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_volatile_unlock_smoke.1732181765
Short name T753
Test name
Test status
Simulation time 14786976 ps
CPU time 0.98 seconds
Started Jun 11 02:12:41 PM PDT 24
Finished Jun 11 02:12:43 PM PDT 24
Peak memory 209436 kb
Host smart-9374d300-59b2-4d93-ac1d-20651a9425a4
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732181765 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ct
rl_volatile_unlock_smoke.1732181765
Directory /workspace/5.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_alert_test.2832673258
Short name T436
Test name
Test status
Simulation time 13885403 ps
CPU time 0.83 seconds
Started Jun 11 02:12:59 PM PDT 24
Finished Jun 11 02:13:03 PM PDT 24
Peak memory 209280 kb
Host smart-5a430a9d-3a65-479c-b174-2b6c256a55a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832673258 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_alert_test.2832673258
Directory /workspace/6.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.lc_ctrl_claim_transition_if.3682702689
Short name T207
Test name
Test status
Simulation time 51809006 ps
CPU time 0.79 seconds
Started Jun 11 02:12:53 PM PDT 24
Finished Jun 11 02:12:57 PM PDT 24
Peak memory 209460 kb
Host smart-b2e08837-d9a7-42ee-895a-1454854fbfd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682702689 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_claim_transition_if.3682702689
Directory /workspace/6.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/6.lc_ctrl_errors.2053132625
Short name T812
Test name
Test status
Simulation time 2482842148 ps
CPU time 13.67 seconds
Started Jun 11 02:12:52 PM PDT 24
Finished Jun 11 02:13:06 PM PDT 24
Peak memory 218740 kb
Host smart-5b07640e-86db-4169-80d0-42f60ac46eed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053132625 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_errors.2053132625
Directory /workspace/6.lc_ctrl_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_access.4277439027
Short name T824
Test name
Test status
Simulation time 527920605 ps
CPU time 6.85 seconds
Started Jun 11 02:12:53 PM PDT 24
Finished Jun 11 02:13:03 PM PDT 24
Peak memory 217820 kb
Host smart-38b6e9b5-081c-4709-8776-03146b762fb3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277439027 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_access.4277439027
Directory /workspace/6.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_errors.114529156
Short name T432
Test name
Test status
Simulation time 3189958439 ps
CPU time 33.99 seconds
Started Jun 11 02:13:04 PM PDT 24
Finished Jun 11 02:13:41 PM PDT 24
Peak memory 219500 kb
Host smart-60fddcf1-354f-454a-9874-92ee32f98b4d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114529156 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_err
ors.114529156
Directory /workspace/6.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_priority.3215612902
Short name T21
Test name
Test status
Simulation time 896956432 ps
CPU time 3.15 seconds
Started Jun 11 02:12:54 PM PDT 24
Finished Jun 11 02:13:00 PM PDT 24
Peak memory 218300 kb
Host smart-9bf57422-b3a9-43e7-8935-e291f08039d1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215612902 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_priority.3
215612902
Directory /workspace/6.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_prog_failure.399128349
Short name T538
Test name
Test status
Simulation time 690632145 ps
CPU time 6.79 seconds
Started Jun 11 02:12:54 PM PDT 24
Finished Jun 11 02:13:04 PM PDT 24
Peak memory 218712 kb
Host smart-08437081-066c-47db-8272-e6ed335ea499
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399128349 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_
prog_failure.399128349
Directory /workspace/6.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_regwen_during_op.950933665
Short name T656
Test name
Test status
Simulation time 938376963 ps
CPU time 22.81 seconds
Started Jun 11 02:12:54 PM PDT 24
Finished Jun 11 02:13:20 PM PDT 24
Peak memory 218224 kb
Host smart-4a39ac90-2aa9-4c11-a3aa-964445b20d98
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950933665 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_j
tag_regwen_during_op.950933665
Directory /workspace/6.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_smoke.3134432951
Short name T541
Test name
Test status
Simulation time 866905988 ps
CPU time 4.25 seconds
Started Jun 11 02:12:51 PM PDT 24
Finished Jun 11 02:12:56 PM PDT 24
Peak memory 218224 kb
Host smart-327a8e7f-6ba2-485b-840c-fe46ac859a38
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134432951 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_smoke.
3134432951
Directory /workspace/6.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_failure.1615644416
Short name T499
Test name
Test status
Simulation time 1305294467 ps
CPU time 34.2 seconds
Started Jun 11 02:12:53 PM PDT 24
Finished Jun 11 02:13:29 PM PDT 24
Peak memory 251520 kb
Host smart-844b55e4-8c4a-40ea-9ba8-49fd6a34513c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615644416 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jta
g_state_failure.1615644416
Directory /workspace/6.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_post_trans.2489015940
Short name T17
Test name
Test status
Simulation time 846892082 ps
CPU time 18.67 seconds
Started Jun 11 02:12:53 PM PDT 24
Finished Jun 11 02:13:14 PM PDT 24
Peak memory 251420 kb
Host smart-5791ba42-a8e9-450a-8a58-34fc47e5b677
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489015940 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_state_post_trans.2489015940
Directory /workspace/6.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_prog_failure.4186663525
Short name T426
Test name
Test status
Simulation time 270342612 ps
CPU time 3.47 seconds
Started Jun 11 02:12:52 PM PDT 24
Finished Jun 11 02:12:56 PM PDT 24
Peak memory 218664 kb
Host smart-faedd146-9aea-4cef-acf4-02a9b42503ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186663525 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_prog_failure.4186663525
Directory /workspace/6.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_regwen_during_op.345378185
Short name T483
Test name
Test status
Simulation time 1342209982 ps
CPU time 9.66 seconds
Started Jun 11 02:12:52 PM PDT 24
Finished Jun 11 02:13:03 PM PDT 24
Peak memory 215152 kb
Host smart-a6c74a63-2a01-4b9a-994f-83336dfbc3e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345378185 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_regwen_during_op.345378185
Directory /workspace/6.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_mubi.2982028418
Short name T384
Test name
Test status
Simulation time 587963127 ps
CPU time 15.19 seconds
Started Jun 11 02:12:55 PM PDT 24
Finished Jun 11 02:13:13 PM PDT 24
Peak memory 219312 kb
Host smart-c36100c7-00c9-473b-9f39-c13921984c45
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982028418 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_mubi.2982028418
Directory /workspace/6.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_digest.188016354
Short name T320
Test name
Test status
Simulation time 1035149198 ps
CPU time 21.79 seconds
Started Jun 11 02:12:57 PM PDT 24
Finished Jun 11 02:13:23 PM PDT 24
Peak memory 218768 kb
Host smart-f17920c1-a491-4a55-a235-dd9b489d9c70
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188016354 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_dig
est.188016354
Directory /workspace/6.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_mux.3845161425
Short name T496
Test name
Test status
Simulation time 2084552978 ps
CPU time 9.27 seconds
Started Jun 11 02:12:52 PM PDT 24
Finished Jun 11 02:13:02 PM PDT 24
Peak memory 218668 kb
Host smart-65e6a666-fd2f-4de4-b490-8ce0473f6a67
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845161425 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_mux.3
845161425
Directory /workspace/6.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/6.lc_ctrl_security_escalation.2917435607
Short name T56
Test name
Test status
Simulation time 741125164 ps
CPU time 7.63 seconds
Started Jun 11 02:12:56 PM PDT 24
Finished Jun 11 02:13:07 PM PDT 24
Peak memory 225484 kb
Host smart-95741355-30f0-4fae-a975-6fc8d88b112e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917435607 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_security_escalation.2917435607
Directory /workspace/6.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/6.lc_ctrl_smoke.2331947378
Short name T502
Test name
Test status
Simulation time 40685819 ps
CPU time 3.1 seconds
Started Jun 11 02:12:57 PM PDT 24
Finished Jun 11 02:13:03 PM PDT 24
Peak memory 215208 kb
Host smart-9a88a454-1e30-41e5-b44a-21f560739b0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331947378 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_smoke.2331947378
Directory /workspace/6.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_failure.109921262
Short name T248
Test name
Test status
Simulation time 266519316 ps
CPU time 36.92 seconds
Started Jun 11 02:12:54 PM PDT 24
Finished Jun 11 02:13:33 PM PDT 24
Peak memory 251432 kb
Host smart-7a2f0ce6-f21c-41ee-9717-c6fefed4c101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109921262 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_failure.109921262
Directory /workspace/6.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_post_trans.3732698268
Short name T684
Test name
Test status
Simulation time 353805963 ps
CPU time 9.03 seconds
Started Jun 11 02:12:56 PM PDT 24
Finished Jun 11 02:13:09 PM PDT 24
Peak memory 251368 kb
Host smart-132d52cc-e6bf-46af-9e4b-3950cca954ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732698268 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_post_trans.3732698268
Directory /workspace/6.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all.3392952791
Short name T85
Test name
Test status
Simulation time 10474104414 ps
CPU time 70.73 seconds
Started Jun 11 02:13:04 PM PDT 24
Finished Jun 11 02:14:18 PM PDT 24
Peak memory 277576 kb
Host smart-ab4c30f0-baa7-4e98-9a6d-3e673ad3df97
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392952791 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.lc_ctrl_stress_all.3392952791
Directory /workspace/6.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all_with_rand_reset.2992976421
Short name T140
Test name
Test status
Simulation time 226716701120 ps
CPU time 1059.58 seconds
Started Jun 11 02:12:57 PM PDT 24
Finished Jun 11 02:30:39 PM PDT 24
Peak memory 284328 kb
Host smart-7480ea26-9f88-4216-a6d6-2522c3f63904
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2992976421 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_stress_all_with_rand_reset.2992976421
Directory /workspace/6.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.lc_ctrl_volatile_unlock_smoke.1959101781
Short name T852
Test name
Test status
Simulation time 81654193 ps
CPU time 0.87 seconds
Started Jun 11 02:12:51 PM PDT 24
Finished Jun 11 02:12:53 PM PDT 24
Peak memory 212348 kb
Host smart-6f453e5e-42b0-43a2-b894-c03c989a8ded
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959101781 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ct
rl_volatile_unlock_smoke.1959101781
Directory /workspace/6.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_alert_test.1003989168
Short name T568
Test name
Test status
Simulation time 52074524 ps
CPU time 1.02 seconds
Started Jun 11 02:12:53 PM PDT 24
Finished Jun 11 02:12:56 PM PDT 24
Peak memory 209420 kb
Host smart-be545ae3-7a31-4caa-9826-5fe20b69556b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003989168 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_alert_test.1003989168
Directory /workspace/7.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.lc_ctrl_errors.1441962183
Short name T44
Test name
Test status
Simulation time 602450403 ps
CPU time 10.85 seconds
Started Jun 11 02:12:55 PM PDT 24
Finished Jun 11 02:13:09 PM PDT 24
Peak memory 218780 kb
Host smart-cc6940a3-75b4-4064-8457-56c6b9d86433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441962183 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_errors.1441962183
Directory /workspace/7.lc_ctrl_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_access.4040458654
Short name T769
Test name
Test status
Simulation time 206348259 ps
CPU time 5.92 seconds
Started Jun 11 02:12:54 PM PDT 24
Finished Jun 11 02:13:02 PM PDT 24
Peak memory 217728 kb
Host smart-574efdd5-284f-4668-9635-2db94dc4c886
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040458654 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_access.4040458654
Directory /workspace/7.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_errors.1767849270
Short name T150
Test name
Test status
Simulation time 9372495409 ps
CPU time 32.42 seconds
Started Jun 11 02:12:59 PM PDT 24
Finished Jun 11 02:13:35 PM PDT 24
Peak memory 219452 kb
Host smart-2d9cd00d-d170-418d-8192-75252c85e6b1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767849270 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_er
rors.1767849270
Directory /workspace/7.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_priority.1139955041
Short name T722
Test name
Test status
Simulation time 318135756 ps
CPU time 4.75 seconds
Started Jun 11 02:12:55 PM PDT 24
Finished Jun 11 02:13:03 PM PDT 24
Peak memory 218268 kb
Host smart-74c6636e-fa8b-4d33-9485-89906bb2c22a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139955041 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_priority.1
139955041
Directory /workspace/7.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_prog_failure.2214260182
Short name T266
Test name
Test status
Simulation time 1113045834 ps
CPU time 5.08 seconds
Started Jun 11 02:12:52 PM PDT 24
Finished Jun 11 02:12:58 PM PDT 24
Peak memory 218720 kb
Host smart-8b716a8a-2f46-4116-9c45-97f00024b878
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214260182 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag
_prog_failure.2214260182
Directory /workspace/7.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_regwen_during_op.403723880
Short name T287
Test name
Test status
Simulation time 1044519727 ps
CPU time 30.62 seconds
Started Jun 11 02:12:56 PM PDT 24
Finished Jun 11 02:13:29 PM PDT 24
Peak memory 218216 kb
Host smart-671853aa-1d16-4673-9e12-5de84e04fec5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403723880 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_j
tag_regwen_during_op.403723880
Directory /workspace/7.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_smoke.1039454481
Short name T399
Test name
Test status
Simulation time 1612950542 ps
CPU time 7.33 seconds
Started Jun 11 02:12:53 PM PDT 24
Finished Jun 11 02:13:03 PM PDT 24
Peak memory 218236 kb
Host smart-9caa568e-2443-4d2b-a968-7f5d04713957
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039454481 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_smoke.
1039454481
Directory /workspace/7.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_failure.2488738414
Short name T763
Test name
Test status
Simulation time 1862679859 ps
CPU time 45.46 seconds
Started Jun 11 02:12:56 PM PDT 24
Finished Jun 11 02:13:45 PM PDT 24
Peak memory 275964 kb
Host smart-7f3acffa-90be-4572-88df-35385c10b920
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488738414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jta
g_state_failure.2488738414
Directory /workspace/7.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_post_trans.3671127243
Short name T283
Test name
Test status
Simulation time 1994026961 ps
CPU time 12.71 seconds
Started Jun 11 02:12:57 PM PDT 24
Finished Jun 11 02:13:14 PM PDT 24
Peak memory 250976 kb
Host smart-c15ececf-a55f-49f5-a5d2-76b1d32c7f2b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671127243 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_state_post_trans.3671127243
Directory /workspace/7.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_prog_failure.1768673026
Short name T318
Test name
Test status
Simulation time 750644194 ps
CPU time 2.55 seconds
Started Jun 11 02:12:53 PM PDT 24
Finished Jun 11 02:12:58 PM PDT 24
Peak memory 218704 kb
Host smart-18f59ae4-b1a5-4f05-a528-09994bcbbeeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768673026 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_prog_failure.1768673026
Directory /workspace/7.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_regwen_during_op.3674444771
Short name T201
Test name
Test status
Simulation time 983274255 ps
CPU time 6.9 seconds
Started Jun 11 02:13:04 PM PDT 24
Finished Jun 11 02:13:14 PM PDT 24
Peak memory 215088 kb
Host smart-2e70dceb-91bf-40e8-8db4-0c81631c22de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674444771 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_regwen_during_op.3674444771
Directory /workspace/7.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_mubi.468008433
Short name T617
Test name
Test status
Simulation time 224735650 ps
CPU time 9.16 seconds
Started Jun 11 02:12:56 PM PDT 24
Finished Jun 11 02:13:08 PM PDT 24
Peak memory 219432 kb
Host smart-9fd4510c-2de6-406d-9aca-249a07e1977d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468008433 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_mubi.468008433
Directory /workspace/7.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_digest.2391802664
Short name T284
Test name
Test status
Simulation time 3976541790 ps
CPU time 24.15 seconds
Started Jun 11 02:13:00 PM PDT 24
Finished Jun 11 02:13:28 PM PDT 24
Peak memory 226616 kb
Host smart-fdb81909-c019-48ba-ae61-a9e33370d8cb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391802664 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_di
gest.2391802664
Directory /workspace/7.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_mux.2330748890
Short name T543
Test name
Test status
Simulation time 2711224655 ps
CPU time 11.46 seconds
Started Jun 11 02:12:56 PM PDT 24
Finished Jun 11 02:13:10 PM PDT 24
Peak memory 218800 kb
Host smart-705de957-cd40-44ad-88a0-4ec588eaa88f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330748890 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_mux.2
330748890
Directory /workspace/7.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/7.lc_ctrl_security_escalation.722826880
Short name T542
Test name
Test status
Simulation time 1020375593 ps
CPU time 7.13 seconds
Started Jun 11 02:13:04 PM PDT 24
Finished Jun 11 02:13:15 PM PDT 24
Peak memory 225320 kb
Host smart-01e442fd-6777-4fee-a60b-f20691764da1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722826880 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_security_escalation.722826880
Directory /workspace/7.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/7.lc_ctrl_smoke.3069486001
Short name T800
Test name
Test status
Simulation time 70542231 ps
CPU time 2.27 seconds
Started Jun 11 02:12:52 PM PDT 24
Finished Jun 11 02:12:55 PM PDT 24
Peak memory 214852 kb
Host smart-a37e870b-4bb1-4058-8792-cf14a4971326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069486001 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_smoke.3069486001
Directory /workspace/7.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_failure.1703507535
Short name T828
Test name
Test status
Simulation time 194068913 ps
CPU time 18.59 seconds
Started Jun 11 02:12:52 PM PDT 24
Finished Jun 11 02:13:13 PM PDT 24
Peak memory 251464 kb
Host smart-2e055496-4dfc-49fc-a523-c8f211789cf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1703507535 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_failure.1703507535
Directory /workspace/7.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_post_trans.1497848502
Short name T842
Test name
Test status
Simulation time 131426726 ps
CPU time 7.1 seconds
Started Jun 11 02:12:53 PM PDT 24
Finished Jun 11 02:13:03 PM PDT 24
Peak memory 250876 kb
Host smart-09766e46-34cd-4930-a2e4-33caad596cb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497848502 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_post_trans.1497848502
Directory /workspace/7.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_stress_all.2027815779
Short name T382
Test name
Test status
Simulation time 13179273038 ps
CPU time 132.97 seconds
Started Jun 11 02:13:00 PM PDT 24
Finished Jun 11 02:15:17 PM PDT 24
Peak memory 284180 kb
Host smart-2ac6c873-c7aa-4b03-a9bf-2cc6e679fd85
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027815779 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.lc_ctrl_stress_all.2027815779
Directory /workspace/7.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.lc_ctrl_volatile_unlock_smoke.332860586
Short name T515
Test name
Test status
Simulation time 38187054 ps
CPU time 0.75 seconds
Started Jun 11 02:12:54 PM PDT 24
Finished Jun 11 02:12:57 PM PDT 24
Peak memory 209188 kb
Host smart-d956d80c-fe7a-45db-9192-c7e1fa591be9
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332860586 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctr
l_volatile_unlock_smoke.332860586
Directory /workspace/7.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_alert_test.4265656960
Short name T69
Test name
Test status
Simulation time 16418497 ps
CPU time 0.9 seconds
Started Jun 11 02:13:05 PM PDT 24
Finished Jun 11 02:13:09 PM PDT 24
Peak memory 209416 kb
Host smart-64cb4e6d-5c74-4c45-a8e4-bdafbfa5cec1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265656960 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_alert_test.4265656960
Directory /workspace/8.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.lc_ctrl_errors.2584802477
Short name T821
Test name
Test status
Simulation time 5095720192 ps
CPU time 13.46 seconds
Started Jun 11 02:12:57 PM PDT 24
Finished Jun 11 02:13:13 PM PDT 24
Peak memory 219372 kb
Host smart-b9392935-bd13-49ad-be0a-31ae235a0ed6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584802477 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_errors.2584802477
Directory /workspace/8.lc_ctrl_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_access.518580539
Short name T500
Test name
Test status
Simulation time 716400867 ps
CPU time 16.91 seconds
Started Jun 11 02:12:54 PM PDT 24
Finished Jun 11 02:13:14 PM PDT 24
Peak memory 217792 kb
Host smart-8a509211-e47b-43e7-8843-8cb983d1b204
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518580539 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_access.518580539
Directory /workspace/8.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_errors.2541467585
Short name T506
Test name
Test status
Simulation time 5272922502 ps
CPU time 43.18 seconds
Started Jun 11 02:12:57 PM PDT 24
Finished Jun 11 02:13:43 PM PDT 24
Peak memory 219516 kb
Host smart-656c6641-e71f-49b0-bc25-33552fed1153
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541467585 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_er
rors.2541467585
Directory /workspace/8.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_priority.2469444984
Short name T65
Test name
Test status
Simulation time 247057743 ps
CPU time 3.26 seconds
Started Jun 11 02:12:54 PM PDT 24
Finished Jun 11 02:13:00 PM PDT 24
Peak memory 218000 kb
Host smart-f779b3d8-6028-4664-bf58-4500fd3b8658
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469444984 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_priority.2
469444984
Directory /workspace/8.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_prog_failure.3362261365
Short name T758
Test name
Test status
Simulation time 195824695 ps
CPU time 3.76 seconds
Started Jun 11 02:12:54 PM PDT 24
Finished Jun 11 02:13:01 PM PDT 24
Peak memory 223324 kb
Host smart-e2826766-3764-4f6d-b72e-339d53ddfcf2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362261365 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag
_prog_failure.3362261365
Directory /workspace/8.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_regwen_during_op.4021708294
Short name T582
Test name
Test status
Simulation time 1194233609 ps
CPU time 15.59 seconds
Started Jun 11 02:12:56 PM PDT 24
Finished Jun 11 02:13:15 PM PDT 24
Peak memory 218228 kb
Host smart-6c7f4706-4b4a-4e4e-8904-6897d25eba65
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021708294 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_regwen_during_op.4021708294
Directory /workspace/8.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_smoke.4171152675
Short name T489
Test name
Test status
Simulation time 391618298 ps
CPU time 3.01 seconds
Started Jun 11 02:12:55 PM PDT 24
Finished Jun 11 02:13:01 PM PDT 24
Peak memory 218208 kb
Host smart-443b327a-c800-4ac0-b228-cac0f449a995
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171152675 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_smoke.
4171152675
Directory /workspace/8.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_failure.2362388957
Short name T829
Test name
Test status
Simulation time 4591529049 ps
CPU time 48.05 seconds
Started Jun 11 02:13:04 PM PDT 24
Finished Jun 11 02:13:55 PM PDT 24
Peak memory 251436 kb
Host smart-de7e86cc-1a1e-401a-b257-678520d3cb91
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362388957 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jta
g_state_failure.2362388957
Directory /workspace/8.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_post_trans.3696052061
Short name T795
Test name
Test status
Simulation time 400124794 ps
CPU time 16.08 seconds
Started Jun 11 02:12:54 PM PDT 24
Finished Jun 11 02:13:13 PM PDT 24
Peak memory 247068 kb
Host smart-d8a001f3-db34-4e50-b2dd-0fb53e08dc4f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696052061 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_state_post_trans.3696052061
Directory /workspace/8.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_prog_failure.77094988
Short name T392
Test name
Test status
Simulation time 37476239 ps
CPU time 2.16 seconds
Started Jun 11 02:12:52 PM PDT 24
Finished Jun 11 02:12:55 PM PDT 24
Peak memory 222728 kb
Host smart-04590c15-9e9f-4c04-8029-6f60db017132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77094988 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_prog_failure.77094988
Directory /workspace/8.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_regwen_during_op.1017549796
Short name T551
Test name
Test status
Simulation time 3477609072 ps
CPU time 12.77 seconds
Started Jun 11 02:12:55 PM PDT 24
Finished Jun 11 02:13:11 PM PDT 24
Peak memory 218276 kb
Host smart-1cc7f849-fddf-4dc1-b986-e55cb47715d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017549796 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_regwen_during_op.1017549796
Directory /workspace/8.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_mubi.1091956543
Short name T340
Test name
Test status
Simulation time 1024800214 ps
CPU time 11.96 seconds
Started Jun 11 02:12:54 PM PDT 24
Finished Jun 11 02:13:08 PM PDT 24
Peak memory 226540 kb
Host smart-0b97a506-b302-4ef7-b483-0f1e4bbc03df
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091956543 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_mubi.1091956543
Directory /workspace/8.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_digest.814290416
Short name T522
Test name
Test status
Simulation time 1285938980 ps
CPU time 8.31 seconds
Started Jun 11 02:13:03 PM PDT 24
Finished Jun 11 02:13:15 PM PDT 24
Peak memory 218644 kb
Host smart-563d24ec-06dd-4ae8-bdc1-726956a24c58
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814290416 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_dig
est.814290416
Directory /workspace/8.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_mux.663081317
Short name T651
Test name
Test status
Simulation time 383945083 ps
CPU time 11.33 seconds
Started Jun 11 02:13:04 PM PDT 24
Finished Jun 11 02:13:18 PM PDT 24
Peak memory 218732 kb
Host smart-8f7ac0d9-c285-4716-9d12-b9da10f21c59
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663081317 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_mux.663081317
Directory /workspace/8.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/8.lc_ctrl_smoke.71777560
Short name T731
Test name
Test status
Simulation time 247300858 ps
CPU time 4.39 seconds
Started Jun 11 02:12:57 PM PDT 24
Finished Jun 11 02:13:05 PM PDT 24
Peak memory 218256 kb
Host smart-6f5a1fd0-7264-4593-86a3-354c0627c730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71777560 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_smoke.71777560
Directory /workspace/8.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_failure.3600831457
Short name T477
Test name
Test status
Simulation time 909100800 ps
CPU time 21.17 seconds
Started Jun 11 02:12:54 PM PDT 24
Finished Jun 11 02:13:18 PM PDT 24
Peak memory 251428 kb
Host smart-ce8b3542-1aa1-41ce-ae95-29a164a08a5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600831457 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_failure.3600831457
Directory /workspace/8.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_post_trans.3231656834
Short name T485
Test name
Test status
Simulation time 368029839 ps
CPU time 7.8 seconds
Started Jun 11 02:12:54 PM PDT 24
Finished Jun 11 02:13:04 PM PDT 24
Peak memory 250980 kb
Host smart-598577d0-e8dc-4f97-9882-dfccdf868780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231656834 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_post_trans.3231656834
Directory /workspace/8.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all.2452563499
Short name T350
Test name
Test status
Simulation time 1099141901 ps
CPU time 21.26 seconds
Started Jun 11 02:13:02 PM PDT 24
Finished Jun 11 02:13:28 PM PDT 24
Peak memory 251396 kb
Host smart-b43601b1-a7d5-444e-9500-98ad71dc7016
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452563499 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.lc_ctrl_stress_all.2452563499
Directory /workspace/8.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.lc_ctrl_volatile_unlock_smoke.55199680
Short name T319
Test name
Test status
Simulation time 16726968 ps
CPU time 1.09 seconds
Started Jun 11 02:12:57 PM PDT 24
Finished Jun 11 02:13:02 PM PDT 24
Peak memory 209496 kb
Host smart-b3b1d94d-eadf-4e29-90ea-510540c7fb14
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55199680 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vol
atile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl
_volatile_unlock_smoke.55199680
Directory /workspace/8.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_alert_test.2973179100
Short name T671
Test name
Test status
Simulation time 228798170 ps
CPU time 1.04 seconds
Started Jun 11 02:13:06 PM PDT 24
Finished Jun 11 02:13:09 PM PDT 24
Peak memory 209412 kb
Host smart-67c4ed45-32e7-460e-b3f2-fed85df1961f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973179100 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_alert_test.2973179100
Directory /workspace/9.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.lc_ctrl_claim_transition_if.3207281464
Short name T204
Test name
Test status
Simulation time 27519892 ps
CPU time 0.79 seconds
Started Jun 11 02:13:01 PM PDT 24
Finished Jun 11 02:13:06 PM PDT 24
Peak memory 209424 kb
Host smart-c5a56580-5946-48f7-8a21-1a92f412b3d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207281464 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_claim_transition_if.3207281464
Directory /workspace/9.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/9.lc_ctrl_errors.655067542
Short name T455
Test name
Test status
Simulation time 2045346735 ps
CPU time 12.41 seconds
Started Jun 11 02:13:02 PM PDT 24
Finished Jun 11 02:13:18 PM PDT 24
Peak memory 218748 kb
Host smart-79646469-acf6-457f-8388-71ea7fd77849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=655067542 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_errors.655067542
Directory /workspace/9.lc_ctrl_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_access.584347628
Short name T789
Test name
Test status
Simulation time 917261301 ps
CPU time 5.6 seconds
Started Jun 11 02:13:02 PM PDT 24
Finished Jun 11 02:13:12 PM PDT 24
Peak memory 217648 kb
Host smart-867d8f9c-ac2c-44fc-a9d0-6d69a7a9fad1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584347628 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_access.584347628
Directory /workspace/9.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_errors.3349006114
Short name T46
Test name
Test status
Simulation time 47098022346 ps
CPU time 43.15 seconds
Started Jun 11 02:13:02 PM PDT 24
Finished Jun 11 02:13:49 PM PDT 24
Peak memory 226504 kb
Host smart-2943dabc-a2b6-4919-a684-2406b5ddd33a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349006114 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_er
rors.3349006114
Directory /workspace/9.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_priority.2783907974
Short name T327
Test name
Test status
Simulation time 147887127 ps
CPU time 2.82 seconds
Started Jun 11 02:13:08 PM PDT 24
Finished Jun 11 02:13:13 PM PDT 24
Peak memory 217948 kb
Host smart-b60d0cb8-ad0f-4d4c-8c16-8cca3e87d872
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783907974 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_priority.2
783907974
Directory /workspace/9.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_prog_failure.2603996211
Short name T498
Test name
Test status
Simulation time 278627695 ps
CPU time 5.77 seconds
Started Jun 11 02:13:07 PM PDT 24
Finished Jun 11 02:13:15 PM PDT 24
Peak memory 218764 kb
Host smart-8ae42856-7a1c-421f-bede-28e5909570c2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603996211 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag
_prog_failure.2603996211
Directory /workspace/9.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_regwen_during_op.1780598127
Short name T624
Test name
Test status
Simulation time 762943931 ps
CPU time 22.37 seconds
Started Jun 11 02:13:13 PM PDT 24
Finished Jun 11 02:13:37 PM PDT 24
Peak memory 218252 kb
Host smart-6686826e-f73f-45d9-8a74-ee5451ee410f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780598127 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_regwen_during_op.1780598127
Directory /workspace/9.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_smoke.3728958056
Short name T862
Test name
Test status
Simulation time 78474268 ps
CPU time 2.9 seconds
Started Jun 11 02:13:13 PM PDT 24
Finished Jun 11 02:13:17 PM PDT 24
Peak memory 218276 kb
Host smart-14a345e8-9239-4476-8ddb-bb141ff97dba
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728958056 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_smoke.
3728958056
Directory /workspace/9.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_failure.2364756657
Short name T224
Test name
Test status
Simulation time 2600860800 ps
CPU time 53.17 seconds
Started Jun 11 02:13:01 PM PDT 24
Finished Jun 11 02:13:58 PM PDT 24
Peak memory 276364 kb
Host smart-28740d19-1eae-4ee9-93ed-db8faf32a0ef
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364756657 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jta
g_state_failure.2364756657
Directory /workspace/9.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_post_trans.2565643641
Short name T619
Test name
Test status
Simulation time 4276563468 ps
CPU time 18.08 seconds
Started Jun 11 02:13:13 PM PDT 24
Finished Jun 11 02:13:33 PM PDT 24
Peak memory 251472 kb
Host smart-7b02b06c-30b9-4a66-b87e-f45f804fbebb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565643641 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_state_post_trans.2565643641
Directory /workspace/9.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_prog_failure.1334691645
Short name T507
Test name
Test status
Simulation time 45534991 ps
CPU time 2.41 seconds
Started Jun 11 02:13:07 PM PDT 24
Finished Jun 11 02:13:12 PM PDT 24
Peak memory 222668 kb
Host smart-f43fdc74-6222-439a-b7ff-d7a657b744c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334691645 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_prog_failure.1334691645
Directory /workspace/9.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_regwen_during_op.806221476
Short name T296
Test name
Test status
Simulation time 312297226 ps
CPU time 5.87 seconds
Started Jun 11 02:13:05 PM PDT 24
Finished Jun 11 02:13:14 PM PDT 24
Peak memory 218304 kb
Host smart-878fcad0-44e5-486a-8630-7189bb0928d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806221476 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_regwen_during_op.806221476
Directory /workspace/9.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_mubi.1541040954
Short name T779
Test name
Test status
Simulation time 314672953 ps
CPU time 12.34 seconds
Started Jun 11 02:13:05 PM PDT 24
Finished Jun 11 02:13:20 PM PDT 24
Peak memory 226300 kb
Host smart-cd1a6c21-97e7-4a39-a7aa-f0d17639e40f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541040954 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_mubi.1541040954
Directory /workspace/9.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_digest.1287475884
Short name T747
Test name
Test status
Simulation time 1289037660 ps
CPU time 12.34 seconds
Started Jun 11 02:13:02 PM PDT 24
Finished Jun 11 02:13:19 PM PDT 24
Peak memory 218660 kb
Host smart-0c1e1a8a-0c5f-450c-a3c6-bb02d47c5c5d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287475884 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_di
gest.1287475884
Directory /workspace/9.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_mux.2106983979
Short name T853
Test name
Test status
Simulation time 2063178855 ps
CPU time 9.89 seconds
Started Jun 11 02:13:02 PM PDT 24
Finished Jun 11 02:13:15 PM PDT 24
Peak memory 218720 kb
Host smart-fd3eea57-b3d2-452a-b0c7-6b290edbb13d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106983979 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_mux.2
106983979
Directory /workspace/9.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/9.lc_ctrl_security_escalation.2871098511
Short name T494
Test name
Test status
Simulation time 1194563223 ps
CPU time 10.82 seconds
Started Jun 11 02:13:03 PM PDT 24
Finished Jun 11 02:13:17 PM PDT 24
Peak memory 218848 kb
Host smart-fac96fca-543f-4ae8-9898-cfdee20dd025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871098511 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_security_escalation.2871098511
Directory /workspace/9.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/9.lc_ctrl_smoke.2245462253
Short name T576
Test name
Test status
Simulation time 24894508 ps
CPU time 1.34 seconds
Started Jun 11 02:13:06 PM PDT 24
Finished Jun 11 02:13:10 PM PDT 24
Peak memory 214164 kb
Host smart-a52aa50f-046a-4ed5-8c70-d06ac5d0de98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2245462253 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_smoke.2245462253
Directory /workspace/9.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_failure.1523733543
Short name T847
Test name
Test status
Simulation time 367048794 ps
CPU time 21.2 seconds
Started Jun 11 02:13:12 PM PDT 24
Finished Jun 11 02:13:35 PM PDT 24
Peak memory 251428 kb
Host smart-df1212bd-b8a3-4b80-880e-91eee31e6d30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523733543 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_failure.1523733543
Directory /workspace/9.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_post_trans.3093896167
Short name T772
Test name
Test status
Simulation time 143832623 ps
CPU time 9.22 seconds
Started Jun 11 02:13:06 PM PDT 24
Finished Jun 11 02:13:18 PM PDT 24
Peak memory 246124 kb
Host smart-232749d8-35ef-47ef-8488-444660203a24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093896167 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_post_trans.3093896167
Directory /workspace/9.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_stress_all.1609903964
Short name T43
Test name
Test status
Simulation time 5902458491 ps
CPU time 94.13 seconds
Started Jun 11 02:13:07 PM PDT 24
Finished Jun 11 02:14:44 PM PDT 24
Peak memory 270140 kb
Host smart-89f6b5ce-f702-48eb-93c6-ba6235d6f15e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609903964 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.lc_ctrl_stress_all.1609903964
Directory /workspace/9.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.lc_ctrl_volatile_unlock_smoke.3190883352
Short name T616
Test name
Test status
Simulation time 21170675 ps
CPU time 1.12 seconds
Started Jun 11 02:13:03 PM PDT 24
Finished Jun 11 02:13:08 PM PDT 24
Peak memory 213420 kb
Host smart-0b3e2c69-6571-4050-bc76-5cc5845d0bb7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190883352 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ct
rl_volatile_unlock_smoke.3190883352
Directory /workspace/9.lc_ctrl_volatile_unlock_smoke/latest
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