Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

93579283

1

T1

14158

T2

12860

T3

50434

auto[1]

1495575

1

T1

1683

T2

2079

T4

14273

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

93598287

1

T1

13366

T2

12761

T3

50434

auto[1]

1476571

1

T1

2475

T2

2178

T4

12800

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	7685311	1			T1	6203		T2	5059		T3	98
auto[IdleSt]	18918606	1			T1	990		T2	1044		T3	50336
auto[ClkMuxSt]	33531	1			T4	76		T9	62		T10	15
auto[CntIncrSt]	33287	1			T4	74		T9	62		T10	15
auto[CntProgSt]	1454170	1			T4	10164		T9	4321		T10	30
auto[TransCheckSt]	25761	1			T4	41		T9	49		T10	15
auto[TokenHashSt]	36688139	1			T4	781		T9	2968		T10	9261
auto[FlashRmaSt]	26931	1			T4	78		T9	39		T10	56
auto[TokenCheck0St]	12100	1			T4	34		T9	39		T10	15
auto[TokenCheck1St]	8895	1			T4	34		T9	23		T10	15
auto[TransProgSt]	370624	1			T4	450		T9	1840		T10	30
auto[PostTransSt]	10568595	1			T4	3		T9	8267		T10	4722
auto[ScrapSt]	292663	1			T4	6		T10	413		T11	3
auto[EscalateSt]	6927920	1			T1	5411		T2	5611		T4	19406
auto[InvalidSt]	12026189	1			T1	3228		T2	3220		T9	1450

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	2136	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	12026189	1			T1	3228		T2	3220		T9	1450
EscalateSt	6927920	1			T1	5411		T2	5611		T4	19406
ScrapSt	292663	1			T4	6		T10	413		T11	3
PostTransSt	10568595	1			T4	3		T9	8267		T10	4722
TransProgSt	370624	1			T4	450		T9	1840		T10	30
TokenCheck1St	8895	1			T4	34		T9	23		T10	15
TokenCheck0St	12100	1			T4	34		T9	39		T10	15
FlashRmaSt	26931	1			T4	78		T9	39		T10	56
TokenHashSt	36688139	1			T4	781		T9	2968		T10	9261
TransCheckSt	25761	1			T4	41		T9	49		T10	15
CntProgSt	1454170	1			T4	10164		T9	4321		T10	30
CntIncrSt	33287	1			T4	74		T9	62		T10	15
ClkMuxSt	33531	1			T4	76		T9	62		T10	15
IdleSt	18918606	1			T1	990		T2	1044		T3	50336
ResetSt	7685311	1			T1	6203		T2	5059		T3	98
arcs[ResetSt=>IdleSt]	53490	1			T1	50		T2	50		T3	1
arcs[IdleSt=>ScrapSt]	267	1			T4	2		T10	1		T11	1
arcs[IdleSt=>ClkMuxSt]	33340	1			T4	76		T9	62		T10	15
arcs[ClkMuxSt=>CntIncrSt]	33287	1			T4	74		T9	62		T10	15
arcs[CntIncrSt=>PostTransSt]	1648	1			T13	9		T31	10		T32	8
arcs[CntIncrSt=>CntProgSt]	31570	1			T4	73		T9	62		T10	15
arcs[CntProgSt=>PostTransSt]	4615	1			T9	13		T12	10		T13	6
arcs[CntProgSt=>TransCheckSt]	25761	1			T4	41		T9	49		T10	15
arcs[TransCheckSt=>PostTransSt]	3477	1			T13	14		T16	48		T35	35
arcs[TransCheckSt=>TokenHashSt]	22182	1			T4	41		T9	49		T10	15
arcs[TokenHashSt=>PostTransSt]	9335	1			T9	10		T12	10		T13	38
arcs[TokenHashSt=>FlashRmaSt]	12210	1			T4	34		T9	39		T10	15
arcs[FlashRmaSt=>TokenCheck0St]	12100	1			T4	34		T9	39		T10	15
arcs[TokenCheck0St=>PostTransSt]	3174	1			T9	16		T12	10		T13	10
arcs[TokenCheck0St=>TokenCheck1St]	8895	1			T4	34		T9	23		T10	15
arcs[TokenCheck1St=>PostTransSt]	616	1			T12	1		T16	6		T42	1
arcs[TransProgSt=>PostTransSt]	7350	1			T4	1		T9	23		T10	15
arcs[IdleSt=>EscalateSt]	257	1			T4	10		T48	6		T50	5
arcs[ClkMuxSt=>EscalateSt]	53	1			T4	2		T11	1		T48	1
arcs[CntIncrSt=>EscalateSt]	69	1			T4	1		T11	1		T49	3
arcs[CntProgSt=>EscalateSt]	1194	1			T4	32		T11	38		T49	25
arcs[TransCheckSt=>EscalateSt]	102	1			T48	7		T56	12		T54	3
arcs[TokenHashSt=>EscalateSt]	637	1			T4	7		T11	16		T49	14
arcs[FlashRmaSt=>EscalateSt]	110	1			T11	5		T49	1		T48	1
arcs[TokenCheck0St=>EscalateSt]	31	1			T11	2		T54	1		T55	3
arcs[TokenCheck1St=>EscalateSt]	142	1			T4	7		T11	6		T49	1
arcs[TransProgSt=>EscalateSt]	787	1			T4	26		T11	16		T49	10
arcs[PostTransSt=>EscalateSt]	4840	1			T4	1		T9	13		T11	6
arcs[InvalidSt=>EscalateSt]	15263	1			T1	42		T2	43		T9	19

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7685128	1			T1	6203		T2	5059		T3	98
auto[0]	auto[IdleSt]	18918438	1			T1	990		T2	1044		T3	50336
auto[0]	auto[ClkMuxSt]	33495	1			T4	75		T9	62		T10	15
auto[0]	auto[CntIncrSt]	33235	1			T4	73		T9	62		T10	15
auto[0]	auto[CntProgSt]	1453367	1			T4	10145		T9	4321		T10	30
auto[0]	auto[TransCheckSt]	25690	1			T4	41		T9	49		T10	15
auto[0]	auto[TokenHashSt]	36687714	1			T4	777		T9	2968		T10	9261
auto[0]	auto[FlashRmaSt]	26853	1			T4	78		T9	39		T10	56
auto[0]	auto[TokenCheck0St]	12081	1			T4	34		T9	39		T10	15
auto[0]	auto[TokenCheck1St]	8793	1			T4	28		T9	23		T10	15
auto[0]	auto[TransProgSt]	370088	1			T4	427		T9	1840		T10	30
auto[0]	auto[PostTransSt]	10566163	1			T4	2		T9	8261		T10	4722
auto[0]	auto[ScrapSt]	292613	1			T4	4		T10	413		T11	3
auto[0]	auto[EscalateSt]	5445017	1			T1	3745		T2	3553		T4	5202
auto[0]	auto[InvalidSt]	12018472	1			T1	3211		T2	3199		T9	1446
auto[1]	auto[ResetSt]	183	1			T4	3		T11	2		T49	5
auto[1]	auto[IdleSt]	168	1			T4	9		T48	6		T50	5
auto[1]	auto[ClkMuxSt]	36	1			T4	1		T11	1		T48	1
auto[1]	auto[CntIncrSt]	52	1			T4	1		T11	1		T49	3
auto[1]	auto[CntProgSt]	803	1			T4	19		T11	23		T49	15
auto[1]	auto[TransCheckSt]	71	1			T48	5		T56	9		T54	1
auto[1]	auto[TokenHashSt]	425	1			T4	4		T11	11		T49	11
auto[1]	auto[FlashRmaSt]	78	1			T11	3		T48	1		T56	5
auto[1]	auto[TokenCheck0St]	19	1			T11	2		T54	1		T55	2
auto[1]	auto[TokenCheck1St]	102	1			T4	6		T11	4		T49	1
auto[1]	auto[TransProgSt]	536	1			T4	23		T11	11		T49	7
auto[1]	auto[PostTransSt]	2432	1			T4	1		T9	6		T11	5
auto[1]	auto[ScrapSt]	50	1			T4	2		T48	4		T56	1
auto[1]	auto[EscalateSt]	1482903	1			T1	1666		T2	2058		T4	14204
auto[1]	auto[InvalidSt]	7717	1			T1	17		T2	21		T9	4

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7685115	1			T1	6203		T2	5059		T3	98
auto[0]	auto[IdleSt]	18918431	1			T1	990		T2	1044		T3	50336
auto[0]	auto[ClkMuxSt]	33497	1			T4	74		T9	62		T10	15
auto[0]	auto[CntIncrSt]	33246	1			T4	74		T9	62		T10	15
auto[0]	auto[CntProgSt]	1453368	1			T4	10142		T9	4321		T10	30
auto[0]	auto[TransCheckSt]	25695	1			T4	41		T9	49		T10	15
auto[0]	auto[TokenHashSt]	36687706	1			T4	776		T9	2968		T10	9261
auto[0]	auto[FlashRmaSt]	26869	1			T4	78		T9	39		T10	56
auto[0]	auto[TokenCheck0St]	12079	1			T4	34		T9	39		T10	15
auto[0]	auto[TokenCheck1St]	8803	1			T4	30		T9	23		T10	15
auto[0]	auto[TransProgSt]	370121	1			T4	433		T9	1840		T10	30
auto[0]	auto[PostTransSt]	10566115	1			T4	3		T9	8260		T10	4722
auto[0]	auto[ScrapSt]	292631	1			T4	4		T10	413		T11	2
auto[0]	auto[EscalateSt]	5463832	1			T1	2961		T2	3455		T4	6667
auto[0]	auto[InvalidSt]	12018643	1			T1	3203		T2	3198		T9	1435
auto[1]	auto[ResetSt]	196	1			T4	4		T11	1		T49	7
auto[1]	auto[IdleSt]	175	1			T4	5		T48	3		T50	3
auto[1]	auto[ClkMuxSt]	34	1			T4	2		T48	1		T56	2
auto[1]	auto[CntIncrSt]	41	1			T49	1		T56	1		T54	2
auto[1]	auto[CntProgSt]	802	1			T4	22		T11	27		T49	17
auto[1]	auto[TransCheckSt]	66	1			T48	6		T56	9		T54	2
auto[1]	auto[TokenHashSt]	433	1			T4	5		T11	8		T49	9
auto[1]	auto[FlashRmaSt]	62	1			T11	2		T49	1		T48	1
auto[1]	auto[TokenCheck0St]	21	1			T54	1		T55	3		T203	1
auto[1]	auto[TokenCheck1St]	92	1			T4	4		T11	5		T48	1
auto[1]	auto[TransProgSt]	503	1			T4	17		T11	11		T49	8
auto[1]	auto[PostTransSt]	2480	1			T9	7		T11	4		T12	6
auto[1]	auto[ScrapSt]	32	1			T4	2		T11	1		T48	1
auto[1]	auto[EscalateSt]	1464088	1			T1	2450		T2	2156		T4	12739
auto[1]	auto[InvalidSt]	7546	1			T1	25		T2	22		T9	15