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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.24 97.99 95.95 93.38 100.00 98.55 98.51 96.29


Total test records in report: 995
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T814 /workspace/coverage/default/36.lc_ctrl_state_post_trans.3201364562 Jun 13 01:45:21 PM PDT 24 Jun 13 01:45:28 PM PDT 24 215187092 ps
T815 /workspace/coverage/default/49.lc_ctrl_smoke.1927125002 Jun 13 01:46:12 PM PDT 24 Jun 13 01:46:16 PM PDT 24 42348632 ps
T816 /workspace/coverage/default/12.lc_ctrl_jtag_state_failure.3214235633 Jun 13 01:43:15 PM PDT 24 Jun 13 01:44:11 PM PDT 24 10745822627 ps
T817 /workspace/coverage/default/29.lc_ctrl_security_escalation.3978365155 Jun 13 01:44:45 PM PDT 24 Jun 13 01:45:04 PM PDT 24 2459487036 ps
T818 /workspace/coverage/default/10.lc_ctrl_jtag_smoke.420923665 Jun 13 01:42:54 PM PDT 24 Jun 13 01:43:00 PM PDT 24 481179833 ps
T819 /workspace/coverage/default/49.lc_ctrl_state_post_trans.1073622300 Jun 13 01:46:19 PM PDT 24 Jun 13 01:46:28 PM PDT 24 294188353 ps
T820 /workspace/coverage/default/12.lc_ctrl_prog_failure.3503025919 Jun 13 01:43:13 PM PDT 24 Jun 13 01:43:15 PM PDT 24 61046442 ps
T821 /workspace/coverage/default/7.lc_ctrl_sec_mubi.3988254854 Jun 13 01:42:36 PM PDT 24 Jun 13 01:42:50 PM PDT 24 904159956 ps
T822 /workspace/coverage/default/38.lc_ctrl_volatile_unlock_smoke.2566510317 Jun 13 01:45:33 PM PDT 24 Jun 13 01:45:35 PM PDT 24 10910302 ps
T823 /workspace/coverage/default/46.lc_ctrl_sec_token_mux.3174082524 Jun 13 01:46:05 PM PDT 24 Jun 13 01:46:18 PM PDT 24 279589645 ps
T824 /workspace/coverage/default/3.lc_ctrl_sec_token_mux.887846725 Jun 13 01:41:55 PM PDT 24 Jun 13 01:42:07 PM PDT 24 1414390658 ps
T825 /workspace/coverage/default/2.lc_ctrl_jtag_priority.1744380771 Jun 13 01:41:45 PM PDT 24 Jun 13 01:41:58 PM PDT 24 1245927345 ps
T826 /workspace/coverage/default/48.lc_ctrl_errors.3633540735 Jun 13 01:46:13 PM PDT 24 Jun 13 01:46:40 PM PDT 24 3788530845 ps
T827 /workspace/coverage/default/33.lc_ctrl_sec_token_mux.1750827134 Jun 13 01:45:06 PM PDT 24 Jun 13 01:45:17 PM PDT 24 2390876212 ps
T828 /workspace/coverage/default/22.lc_ctrl_state_failure.3858498697 Jun 13 01:44:16 PM PDT 24 Jun 13 01:44:47 PM PDT 24 337219604 ps
T829 /workspace/coverage/default/4.lc_ctrl_smoke.853264173 Jun 13 01:41:56 PM PDT 24 Jun 13 01:41:59 PM PDT 24 26598098 ps
T830 /workspace/coverage/default/30.lc_ctrl_sec_mubi.1694281243 Jun 13 01:44:54 PM PDT 24 Jun 13 01:45:11 PM PDT 24 363642765 ps
T831 /workspace/coverage/default/0.lc_ctrl_jtag_errors.3920299072 Jun 13 01:41:20 PM PDT 24 Jun 13 01:41:49 PM PDT 24 5134123859 ps
T832 /workspace/coverage/default/22.lc_ctrl_prog_failure.1138675993 Jun 13 01:44:15 PM PDT 24 Jun 13 01:44:19 PM PDT 24 49994669 ps
T833 /workspace/coverage/default/0.lc_ctrl_state_post_trans.1646603057 Jun 13 01:41:17 PM PDT 24 Jun 13 01:41:22 PM PDT 24 149867665 ps
T834 /workspace/coverage/default/9.lc_ctrl_sec_mubi.1167870714 Jun 13 01:42:49 PM PDT 24 Jun 13 01:43:02 PM PDT 24 739594546 ps
T835 /workspace/coverage/default/17.lc_ctrl_stress_all.156908157 Jun 13 01:43:51 PM PDT 24 Jun 13 01:46:58 PM PDT 24 42580556010 ps
T836 /workspace/coverage/default/8.lc_ctrl_jtag_smoke.3599228247 Jun 13 01:42:35 PM PDT 24 Jun 13 01:42:40 PM PDT 24 729939687 ps
T837 /workspace/coverage/default/33.lc_ctrl_smoke.968965711 Jun 13 01:45:09 PM PDT 24 Jun 13 01:45:12 PM PDT 24 89886460 ps
T838 /workspace/coverage/default/2.lc_ctrl_stress_all.1141324007 Jun 13 01:41:47 PM PDT 24 Jun 13 01:42:26 PM PDT 24 2185212818 ps
T839 /workspace/coverage/default/16.lc_ctrl_prog_failure.2885744288 Jun 13 01:43:38 PM PDT 24 Jun 13 01:43:41 PM PDT 24 80874529 ps
T840 /workspace/coverage/default/2.lc_ctrl_jtag_smoke.2731439702 Jun 13 01:41:43 PM PDT 24 Jun 13 01:41:48 PM PDT 24 207038290 ps
T841 /workspace/coverage/default/3.lc_ctrl_jtag_state_failure.849551938 Jun 13 01:41:47 PM PDT 24 Jun 13 01:42:26 PM PDT 24 2294347195 ps
T842 /workspace/coverage/default/9.lc_ctrl_alert_test.1262604571 Jun 13 01:42:47 PM PDT 24 Jun 13 01:42:50 PM PDT 24 47170367 ps
T843 /workspace/coverage/default/30.lc_ctrl_stress_all_with_rand_reset.2874932071 Jun 13 01:45:04 PM PDT 24 Jun 13 01:50:28 PM PDT 24 107134135734 ps
T844 /workspace/coverage/default/4.lc_ctrl_jtag_errors.2873487196 Jun 13 01:41:53 PM PDT 24 Jun 13 01:42:37 PM PDT 24 1662118905 ps
T845 /workspace/coverage/default/38.lc_ctrl_alert_test.3455814803 Jun 13 01:45:42 PM PDT 24 Jun 13 01:45:44 PM PDT 24 20789376 ps
T846 /workspace/coverage/default/14.lc_ctrl_jtag_smoke.1360166080 Jun 13 01:43:25 PM PDT 24 Jun 13 01:43:32 PM PDT 24 846722820 ps
T847 /workspace/coverage/default/36.lc_ctrl_alert_test.3458772654 Jun 13 01:45:26 PM PDT 24 Jun 13 01:45:27 PM PDT 24 14869651 ps
T848 /workspace/coverage/default/39.lc_ctrl_sec_mubi.3117866470 Jun 13 01:45:37 PM PDT 24 Jun 13 01:45:48 PM PDT 24 661015779 ps
T101 /workspace/coverage/default/27.lc_ctrl_stress_all_with_rand_reset.1698182752 Jun 13 01:44:42 PM PDT 24 Jun 13 02:12:28 PM PDT 24 904540360972 ps
T849 /workspace/coverage/default/12.lc_ctrl_sec_token_digest.2500934727 Jun 13 01:43:13 PM PDT 24 Jun 13 01:43:23 PM PDT 24 928302423 ps
T850 /workspace/coverage/default/3.lc_ctrl_sec_token_digest.2213626638 Jun 13 01:41:54 PM PDT 24 Jun 13 01:42:06 PM PDT 24 338148047 ps
T851 /workspace/coverage/default/47.lc_ctrl_jtag_access.2636906672 Jun 13 01:46:13 PM PDT 24 Jun 13 01:46:19 PM PDT 24 1724992302 ps
T852 /workspace/coverage/default/28.lc_ctrl_prog_failure.447284177 Jun 13 01:44:49 PM PDT 24 Jun 13 01:44:52 PM PDT 24 60252470 ps
T853 /workspace/coverage/default/39.lc_ctrl_prog_failure.2621570180 Jun 13 01:45:30 PM PDT 24 Jun 13 01:45:32 PM PDT 24 99056249 ps
T854 /workspace/coverage/default/7.lc_ctrl_volatile_unlock_smoke.93338662 Jun 13 01:42:24 PM PDT 24 Jun 13 01:42:25 PM PDT 24 13714555 ps
T855 /workspace/coverage/default/38.lc_ctrl_security_escalation.2574069918 Jun 13 01:45:28 PM PDT 24 Jun 13 01:45:35 PM PDT 24 253956987 ps
T856 /workspace/coverage/default/6.lc_ctrl_jtag_state_post_trans.1522554066 Jun 13 01:42:21 PM PDT 24 Jun 13 01:42:38 PM PDT 24 2632209563 ps
T857 /workspace/coverage/default/20.lc_ctrl_state_failure.3821278780 Jun 13 01:44:04 PM PDT 24 Jun 13 01:44:25 PM PDT 24 616357589 ps
T858 /workspace/coverage/default/42.lc_ctrl_sec_token_mux.2083454121 Jun 13 01:45:53 PM PDT 24 Jun 13 01:46:07 PM PDT 24 731233554 ps
T859 /workspace/coverage/default/28.lc_ctrl_smoke.1532172755 Jun 13 01:44:41 PM PDT 24 Jun 13 01:44:44 PM PDT 24 112404635 ps
T860 /workspace/coverage/default/46.lc_ctrl_sec_token_digest.3983365897 Jun 13 01:46:02 PM PDT 24 Jun 13 01:46:15 PM PDT 24 241958463 ps
T861 /workspace/coverage/default/37.lc_ctrl_stress_all.4254997907 Jun 13 01:45:25 PM PDT 24 Jun 13 01:46:23 PM PDT 24 1767079506 ps
T862 /workspace/coverage/default/24.lc_ctrl_alert_test.4263941354 Jun 13 01:44:26 PM PDT 24 Jun 13 01:44:28 PM PDT 24 60535334 ps
T863 /workspace/coverage/default/24.lc_ctrl_prog_failure.2031890326 Jun 13 01:44:21 PM PDT 24 Jun 13 01:44:25 PM PDT 24 155150549 ps
T864 /workspace/coverage/default/38.lc_ctrl_jtag_access.749914481 Jun 13 01:45:34 PM PDT 24 Jun 13 01:45:37 PM PDT 24 86071044 ps
T865 /workspace/coverage/default/15.lc_ctrl_jtag_prog_failure.156101918 Jun 13 01:43:31 PM PDT 24 Jun 13 01:43:40 PM PDT 24 3408214075 ps
T866 /workspace/coverage/default/6.lc_ctrl_sec_mubi.802391261 Jun 13 01:42:27 PM PDT 24 Jun 13 01:42:45 PM PDT 24 566376586 ps
T867 /workspace/coverage/default/17.lc_ctrl_volatile_unlock_smoke.3019849319 Jun 13 01:43:45 PM PDT 24 Jun 13 01:43:47 PM PDT 24 67202375 ps
T868 /workspace/coverage/default/43.lc_ctrl_errors.1317994650 Jun 13 01:45:52 PM PDT 24 Jun 13 01:46:01 PM PDT 24 456687693 ps
T869 /workspace/coverage/default/0.lc_ctrl_smoke.2694200264 Jun 13 01:41:16 PM PDT 24 Jun 13 01:41:27 PM PDT 24 490019001 ps
T870 /workspace/coverage/default/49.lc_ctrl_errors.1999547875 Jun 13 01:46:21 PM PDT 24 Jun 13 01:46:40 PM PDT 24 664697309 ps
T102 /workspace/coverage/default/23.lc_ctrl_stress_all_with_rand_reset.3589551703 Jun 13 01:44:23 PM PDT 24 Jun 13 01:48:54 PM PDT 24 48325744683 ps
T871 /workspace/coverage/default/26.lc_ctrl_jtag_access.1153040794 Jun 13 01:44:34 PM PDT 24 Jun 13 01:44:39 PM PDT 24 304697678 ps
T106 /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.219567092 Jun 13 01:33:23 PM PDT 24 Jun 13 01:33:25 PM PDT 24 26253282 ps
T98 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.3616466295 Jun 13 01:34:13 PM PDT 24 Jun 13 01:34:16 PM PDT 24 123060340 ps
T107 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.2871895573 Jun 13 01:33:55 PM PDT 24 Jun 13 01:33:57 PM PDT 24 17390264 ps
T99 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.2741546968 Jun 13 01:34:35 PM PDT 24 Jun 13 01:34:38 PM PDT 24 209589161 ps
T190 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.1796996 Jun 13 01:34:30 PM PDT 24 Jun 13 01:34:32 PM PDT 24 45198045 ps
T132 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.563223482 Jun 13 01:33:20 PM PDT 24 Jun 13 01:33:26 PM PDT 24 373191902 ps
T100 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.909953128 Jun 13 01:34:28 PM PDT 24 Jun 13 01:34:31 PM PDT 24 27856566 ps
T150 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.4285286616 Jun 13 01:34:28 PM PDT 24 Jun 13 01:34:29 PM PDT 24 51927831 ps
T136 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.3763919460 Jun 13 01:34:16 PM PDT 24 Jun 13 01:34:29 PM PDT 24 2476835020 ps
T872 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.687493316 Jun 13 01:34:08 PM PDT 24 Jun 13 01:34:11 PM PDT 24 15137706 ps
T103 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.34400776 Jun 13 01:34:39 PM PDT 24 Jun 13 01:34:42 PM PDT 24 30592552 ps
T133 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.650528987 Jun 13 01:33:46 PM PDT 24 Jun 13 01:33:50 PM PDT 24 3017195735 ps
T135 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2352969272 Jun 13 01:33:20 PM PDT 24 Jun 13 01:33:23 PM PDT 24 315541486 ps
T873 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.4273416051 Jun 13 01:34:15 PM PDT 24 Jun 13 01:34:17 PM PDT 24 72349867 ps
T134 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.292901470 Jun 13 01:34:06 PM PDT 24 Jun 13 01:34:08 PM PDT 24 526578877 ps
T104 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.2690049113 Jun 13 01:33:30 PM PDT 24 Jun 13 01:33:33 PM PDT 24 574975062 ps
T874 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.3808228398 Jun 13 01:33:50 PM PDT 24 Jun 13 01:33:57 PM PDT 24 1928499988 ps
T175 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.2422856953 Jun 13 01:33:20 PM PDT 24 Jun 13 01:33:22 PM PDT 24 36480627 ps
T875 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.4155514103 Jun 13 01:33:48 PM PDT 24 Jun 13 01:33:51 PM PDT 24 175601255 ps
T191 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.317064492 Jun 13 01:33:30 PM PDT 24 Jun 13 01:33:33 PM PDT 24 37760442 ps
T192 /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.4208043005 Jun 13 01:34:06 PM PDT 24 Jun 13 01:34:08 PM PDT 24 26444346 ps
T123 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.2559610363 Jun 13 01:33:34 PM PDT 24 Jun 13 01:33:36 PM PDT 24 22870619 ps
T113 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.3734842954 Jun 13 01:33:53 PM PDT 24 Jun 13 01:33:57 PM PDT 24 117794522 ps
T171 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3500087416 Jun 13 01:34:01 PM PDT 24 Jun 13 01:34:04 PM PDT 24 49410671 ps
T876 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.2504611688 Jun 13 01:32:57 PM PDT 24 Jun 13 01:32:59 PM PDT 24 228443628 ps
T877 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.1367349869 Jun 13 01:33:22 PM PDT 24 Jun 13 01:33:25 PM PDT 24 292908339 ps
T108 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.4060163449 Jun 13 01:34:34 PM PDT 24 Jun 13 01:34:36 PM PDT 24 76188394 ps
T125 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.4035286400 Jun 13 01:33:50 PM PDT 24 Jun 13 01:33:52 PM PDT 24 25711121 ps
T105 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.1130077566 Jun 13 01:34:01 PM PDT 24 Jun 13 01:34:04 PM PDT 24 112344310 ps
T119 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.419825214 Jun 13 01:34:08 PM PDT 24 Jun 13 01:34:11 PM PDT 24 27181261 ps
T109 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.339852850 Jun 13 01:34:18 PM PDT 24 Jun 13 01:34:21 PM PDT 24 374317402 ps
T110 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.1149798396 Jun 13 01:33:46 PM PDT 24 Jun 13 01:33:50 PM PDT 24 199055533 ps
T126 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.1783356582 Jun 13 01:34:22 PM PDT 24 Jun 13 01:34:25 PM PDT 24 497863991 ps
T131 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.2292630962 Jun 13 01:34:26 PM PDT 24 Jun 13 01:34:29 PM PDT 24 106828164 ps
T193 /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.662107845 Jun 13 01:33:37 PM PDT 24 Jun 13 01:33:40 PM PDT 24 41172848 ps
T878 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.3427650733 Jun 13 01:34:28 PM PDT 24 Jun 13 01:34:31 PM PDT 24 95476772 ps
T879 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.2332129627 Jun 13 01:34:32 PM PDT 24 Jun 13 01:34:34 PM PDT 24 228831868 ps
T880 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.1181928930 Jun 13 01:33:22 PM PDT 24 Jun 13 01:33:24 PM PDT 24 17907664 ps
T194 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.998219438 Jun 13 01:32:56 PM PDT 24 Jun 13 01:32:58 PM PDT 24 38806553 ps
T195 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.2167125089 Jun 13 01:34:06 PM PDT 24 Jun 13 01:34:08 PM PDT 24 161861453 ps
T881 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.3302162423 Jun 13 01:33:40 PM PDT 24 Jun 13 01:33:42 PM PDT 24 104441218 ps
T176 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.1010876925 Jun 13 01:34:40 PM PDT 24 Jun 13 01:34:42 PM PDT 24 23950909 ps
T882 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.1545410259 Jun 13 01:33:22 PM PDT 24 Jun 13 01:33:24 PM PDT 24 63640544 ps
T196 /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.3156968802 Jun 13 01:34:32 PM PDT 24 Jun 13 01:34:34 PM PDT 24 26892912 ps
T177 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.719707223 Jun 13 01:34:31 PM PDT 24 Jun 13 01:34:32 PM PDT 24 30358505 ps
T883 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.2980786645 Jun 13 01:33:24 PM PDT 24 Jun 13 01:33:25 PM PDT 24 21649141 ps
T117 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.3784198626 Jun 13 01:33:10 PM PDT 24 Jun 13 01:33:13 PM PDT 24 214590940 ps
T884 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.593780230 Jun 13 01:33:31 PM PDT 24 Jun 13 01:33:33 PM PDT 24 89905449 ps
T178 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.3445798612 Jun 13 01:34:26 PM PDT 24 Jun 13 01:34:28 PM PDT 24 14780945 ps
T885 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.3904986136 Jun 13 01:34:41 PM PDT 24 Jun 13 01:34:44 PM PDT 24 29270593 ps
T116 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.3257883287 Jun 13 01:34:32 PM PDT 24 Jun 13 01:34:36 PM PDT 24 75273888 ps
T886 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.797400818 Jun 13 01:34:20 PM PDT 24 Jun 13 01:34:22 PM PDT 24 50924900 ps
T887 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.2082358805 Jun 13 01:32:50 PM PDT 24 Jun 13 01:32:52 PM PDT 24 74347761 ps
T888 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4197629753 Jun 13 01:33:22 PM PDT 24 Jun 13 01:33:27 PM PDT 24 1848273687 ps
T889 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.100413038 Jun 13 01:33:31 PM PDT 24 Jun 13 01:33:51 PM PDT 24 862926285 ps
T890 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.1740034883 Jun 13 01:34:32 PM PDT 24 Jun 13 01:34:34 PM PDT 24 106275229 ps
T891 /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.3856242530 Jun 13 01:34:13 PM PDT 24 Jun 13 01:34:15 PM PDT 24 18898539 ps
T892 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.646966516 Jun 13 01:34:03 PM PDT 24 Jun 13 01:34:07 PM PDT 24 905051795 ps
T893 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.3425851654 Jun 13 01:33:56 PM PDT 24 Jun 13 01:33:59 PM PDT 24 35112349 ps
T894 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.260716309 Jun 13 01:34:04 PM PDT 24 Jun 13 01:34:06 PM PDT 24 17402369 ps
T895 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.1726668180 Jun 13 01:33:55 PM PDT 24 Jun 13 01:34:16 PM PDT 24 946251346 ps
T179 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.3167059321 Jun 13 01:32:58 PM PDT 24 Jun 13 01:32:59 PM PDT 24 26126228 ps
T896 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.2650793139 Jun 13 01:34:07 PM PDT 24 Jun 13 01:34:10 PM PDT 24 102809940 ps
T897 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.1456339228 Jun 13 01:32:51 PM PDT 24 Jun 13 01:32:53 PM PDT 24 282669334 ps
T898 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.283297153 Jun 13 01:32:58 PM PDT 24 Jun 13 01:33:02 PM PDT 24 294242012 ps
T899 /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.2227309317 Jun 13 01:34:28 PM PDT 24 Jun 13 01:34:30 PM PDT 24 90401562 ps
T900 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.1590273671 Jun 13 01:34:14 PM PDT 24 Jun 13 01:34:20 PM PDT 24 190405105 ps
T901 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.734863230 Jun 13 01:34:02 PM PDT 24 Jun 13 01:34:13 PM PDT 24 969270156 ps
T128 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.3647002290 Jun 13 01:34:30 PM PDT 24 Jun 13 01:34:33 PM PDT 24 336859171 ps
T902 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.338977500 Jun 13 01:34:01 PM PDT 24 Jun 13 01:34:07 PM PDT 24 142961488 ps
T903 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.1726265079 Jun 13 01:33:40 PM PDT 24 Jun 13 01:33:42 PM PDT 24 125097608 ps
T904 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2880002346 Jun 13 01:34:00 PM PDT 24 Jun 13 01:34:06 PM PDT 24 279433167 ps
T118 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.3357937404 Jun 13 01:34:32 PM PDT 24 Jun 13 01:34:35 PM PDT 24 267926894 ps
T905 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.997890018 Jun 13 01:33:46 PM PDT 24 Jun 13 01:33:48 PM PDT 24 72902070 ps
T906 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.2732860480 Jun 13 01:32:50 PM PDT 24 Jun 13 01:33:21 PM PDT 24 5518694059 ps
T907 /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.840035106 Jun 13 01:34:28 PM PDT 24 Jun 13 01:34:31 PM PDT 24 38358228 ps
T908 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.4259968334 Jun 13 01:33:29 PM PDT 24 Jun 13 01:33:32 PM PDT 24 178545301 ps
T909 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.352243327 Jun 13 01:33:47 PM PDT 24 Jun 13 01:33:59 PM PDT 24 1773466526 ps
T910 /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.2141149641 Jun 13 01:33:48 PM PDT 24 Jun 13 01:33:51 PM PDT 24 135778860 ps
T911 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.869502318 Jun 13 01:34:27 PM PDT 24 Jun 13 01:34:30 PM PDT 24 34038934 ps
T912 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.647105825 Jun 13 01:34:40 PM PDT 24 Jun 13 01:34:46 PM PDT 24 555540605 ps
T913 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.436187556 Jun 13 01:32:58 PM PDT 24 Jun 13 01:33:00 PM PDT 24 449792819 ps
T914 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.693592878 Jun 13 01:34:02 PM PDT 24 Jun 13 01:34:14 PM PDT 24 1961113410 ps
T915 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.2486214033 Jun 13 01:32:58 PM PDT 24 Jun 13 01:33:00 PM PDT 24 42705257 ps
T916 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.3550735768 Jun 13 01:34:07 PM PDT 24 Jun 13 01:34:09 PM PDT 24 121814629 ps
T917 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.3855627946 Jun 13 01:33:29 PM PDT 24 Jun 13 01:33:30 PM PDT 24 118982587 ps
T918 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.309767345 Jun 13 01:34:09 PM PDT 24 Jun 13 01:34:20 PM PDT 24 4875842125 ps
T919 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.2458922286 Jun 13 01:33:30 PM PDT 24 Jun 13 01:33:33 PM PDT 24 75733698 ps
T920 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.211611496 Jun 13 01:34:05 PM PDT 24 Jun 13 01:34:08 PM PDT 24 1703731545 ps
T180 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.2277919783 Jun 13 01:34:40 PM PDT 24 Jun 13 01:34:41 PM PDT 24 290350914 ps
T127 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.3738332153 Jun 13 01:33:56 PM PDT 24 Jun 13 01:33:59 PM PDT 24 60051808 ps
T921 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.2530791929 Jun 13 01:34:29 PM PDT 24 Jun 13 01:34:30 PM PDT 24 31050138 ps
T922 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.1428486853 Jun 13 01:33:11 PM PDT 24 Jun 13 01:33:13 PM PDT 24 32180246 ps
T923 /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.2767654015 Jun 13 01:34:39 PM PDT 24 Jun 13 01:34:41 PM PDT 24 26629231 ps
T924 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.3380975688 Jun 13 01:33:31 PM PDT 24 Jun 13 01:33:38 PM PDT 24 5376889583 ps
T925 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4007578178 Jun 13 01:33:55 PM PDT 24 Jun 13 01:33:59 PM PDT 24 103830782 ps
T926 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.3145718670 Jun 13 01:34:42 PM PDT 24 Jun 13 01:34:44 PM PDT 24 75540860 ps
T181 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.3523004168 Jun 13 01:33:37 PM PDT 24 Jun 13 01:33:40 PM PDT 24 22805202 ps
T182 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.3165594594 Jun 13 01:34:14 PM PDT 24 Jun 13 01:34:16 PM PDT 24 16030752 ps
T927 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.274992319 Jun 13 01:34:32 PM PDT 24 Jun 13 01:34:34 PM PDT 24 42917140 ps
T928 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.3724764623 Jun 13 01:34:02 PM PDT 24 Jun 13 01:34:04 PM PDT 24 35531715 ps
T929 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.2652874412 Jun 13 01:34:27 PM PDT 24 Jun 13 01:34:29 PM PDT 24 74685014 ps
T930 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.3567681317 Jun 13 01:34:01 PM PDT 24 Jun 13 01:34:04 PM PDT 24 45746061 ps
T114 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.446631642 Jun 13 01:33:42 PM PDT 24 Jun 13 01:33:46 PM PDT 24 522510897 ps
T931 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.908534692 Jun 13 01:34:21 PM PDT 24 Jun 13 01:34:23 PM PDT 24 15036933 ps
T932 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.1953539407 Jun 13 01:33:35 PM PDT 24 Jun 13 01:33:38 PM PDT 24 24565566 ps
T124 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.2680570469 Jun 13 01:34:39 PM PDT 24 Jun 13 01:34:42 PM PDT 24 58146248 ps
T933 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.2337927469 Jun 13 01:33:30 PM PDT 24 Jun 13 01:33:32 PM PDT 24 25389100 ps
T934 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1909041742 Jun 13 01:33:42 PM PDT 24 Jun 13 01:33:45 PM PDT 24 361419743 ps
T935 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.1659325283 Jun 13 01:32:51 PM PDT 24 Jun 13 01:32:57 PM PDT 24 1921687654 ps
T129 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.1145371956 Jun 13 01:33:36 PM PDT 24 Jun 13 01:33:40 PM PDT 24 373107255 ps
T936 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.3032469987 Jun 13 01:33:11 PM PDT 24 Jun 13 01:33:15 PM PDT 24 64020718 ps
T937 /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.400603316 Jun 13 01:34:42 PM PDT 24 Jun 13 01:34:44 PM PDT 24 24208098 ps
T938 /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.2498478412 Jun 13 01:34:00 PM PDT 24 Jun 13 01:34:02 PM PDT 24 196728925 ps
T188 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.1325463432 Jun 13 01:33:35 PM PDT 24 Jun 13 01:33:36 PM PDT 24 101411627 ps
T939 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.854000769 Jun 13 01:34:00 PM PDT 24 Jun 13 01:34:06 PM PDT 24 4463706778 ps
T183 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.2833650863 Jun 13 01:33:03 PM PDT 24 Jun 13 01:33:05 PM PDT 24 163195547 ps
T940 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.3948710636 Jun 13 01:33:23 PM PDT 24 Jun 13 01:33:34 PM PDT 24 1803040142 ps
T941 /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.358725 Jun 13 01:33:02 PM PDT 24 Jun 13 01:33:04 PM PDT 24 42357290 ps
T942 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.1806565898 Jun 13 01:33:23 PM PDT 24 Jun 13 01:33:25 PM PDT 24 49093310 ps
T943 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.595522547 Jun 13 01:34:30 PM PDT 24 Jun 13 01:34:31 PM PDT 24 21390997 ps
T944 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.3480184693 Jun 13 01:34:07 PM PDT 24 Jun 13 01:34:14 PM PDT 24 707426971 ps
T945 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.425864317 Jun 13 01:33:20 PM PDT 24 Jun 13 01:33:22 PM PDT 24 74670596 ps
T946 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3927846109 Jun 13 01:34:19 PM PDT 24 Jun 13 01:34:22 PM PDT 24 726674131 ps
T947 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.1383201046 Jun 13 01:33:22 PM PDT 24 Jun 13 01:33:25 PM PDT 24 20250203 ps
T948 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.1802504000 Jun 13 01:34:26 PM PDT 24 Jun 13 01:34:30 PM PDT 24 101466590 ps
T949 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.814943948 Jun 13 01:33:56 PM PDT 24 Jun 13 01:33:58 PM PDT 24 886928657 ps
T111 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.3838748856 Jun 13 01:34:06 PM PDT 24 Jun 13 01:34:12 PM PDT 24 409907950 ps
T950 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.1322738335 Jun 13 01:34:26 PM PDT 24 Jun 13 01:34:28 PM PDT 24 54913512 ps
T951 /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.1661783632 Jun 13 01:34:35 PM PDT 24 Jun 13 01:34:37 PM PDT 24 67955308 ps
T952 /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.1376645848 Jun 13 01:34:28 PM PDT 24 Jun 13 01:34:30 PM PDT 24 118944456 ps
T953 /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.1761055384 Jun 13 01:34:19 PM PDT 24 Jun 13 01:34:20 PM PDT 24 125448640 ps
T954 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.1726134985 Jun 13 01:33:42 PM PDT 24 Jun 13 01:33:46 PM PDT 24 420675056 ps
T955 /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.2903645313 Jun 13 01:33:57 PM PDT 24 Jun 13 01:34:00 PM PDT 24 49178948 ps
T189 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.1707625635 Jun 13 01:33:41 PM PDT 24 Jun 13 01:33:42 PM PDT 24 20733324 ps
T956 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.66545908 Jun 13 01:34:12 PM PDT 24 Jun 13 01:34:16 PM PDT 24 36138835 ps
T957 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.2273329512 Jun 13 01:33:43 PM PDT 24 Jun 13 01:33:45 PM PDT 24 24896319 ps
T958 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.974180815 Jun 13 01:34:15 PM PDT 24 Jun 13 01:34:24 PM PDT 24 2759679995 ps
T130 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.3260716215 Jun 13 01:34:21 PM PDT 24 Jun 13 01:34:25 PM PDT 24 63924406 ps
T959 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.2391879611 Jun 13 01:33:30 PM PDT 24 Jun 13 01:33:33 PM PDT 24 36503805 ps
T184 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.3431204159 Jun 13 01:34:34 PM PDT 24 Jun 13 01:34:35 PM PDT 24 37375068 ps
T960 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.414210202 Jun 13 01:34:22 PM PDT 24 Jun 13 01:34:23 PM PDT 24 34347118 ps
T961 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1761095982 Jun 13 01:32:59 PM PDT 24 Jun 13 01:33:02 PM PDT 24 55910117 ps
T962 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.9094508 Jun 13 01:34:17 PM PDT 24 Jun 13 01:34:19 PM PDT 24 14366755 ps
T963 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.2836279016 Jun 13 01:33:04 PM PDT 24 Jun 13 01:33:07 PM PDT 24 235417482 ps
T964 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.3595684877 Jun 13 01:34:33 PM PDT 24 Jun 13 01:34:35 PM PDT 24 26906847 ps
T965 /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.1855749688 Jun 13 01:33:18 PM PDT 24 Jun 13 01:33:20 PM PDT 24 108092891 ps
T112 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.2272626487 Jun 13 01:34:31 PM PDT 24 Jun 13 01:34:35 PM PDT 24 399272754 ps
T966 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.765445159 Jun 13 01:34:26 PM PDT 24 Jun 13 01:34:29 PM PDT 24 46811395 ps
T967 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.4107940624 Jun 13 01:33:56 PM PDT 24 Jun 13 01:33:57 PM PDT 24 242473064 ps
T968 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.4067790948 Jun 13 01:34:29 PM PDT 24 Jun 13 01:34:33 PM PDT 24 255840509 ps
T969 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.148572767 Jun 13 01:34:15 PM PDT 24 Jun 13 01:34:18 PM PDT 24 218044323 ps
T970 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.1675858523 Jun 13 01:34:02 PM PDT 24 Jun 13 01:34:05 PM PDT 24 66734150 ps
T971 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.2794937398 Jun 13 01:34:02 PM PDT 24 Jun 13 01:34:07 PM PDT 24 1690425005 ps
T185 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.1665665308 Jun 13 01:33:22 PM PDT 24 Jun 13 01:33:25 PM PDT 24 165038752 ps
T972 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.3224684250 Jun 13 01:34:14 PM PDT 24 Jun 13 01:34:16 PM PDT 24 371132587 ps
T973 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.893708082 Jun 13 01:33:36 PM PDT 24 Jun 13 01:33:39 PM PDT 24 186929412 ps
T974 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.1445906356 Jun 13 01:34:03 PM PDT 24 Jun 13 01:34:04 PM PDT 24 16089370 ps
T975 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.4290200051 Jun 13 01:33:20 PM PDT 24 Jun 13 01:33:33 PM PDT 24 3563125525 ps
T976 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.3749074653 Jun 13 01:33:11 PM PDT 24 Jun 13 01:33:14 PM PDT 24 2466087688 ps
T977 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.850114034 Jun 13 01:33:48 PM PDT 24 Jun 13 01:33:50 PM PDT 24 308525918 ps
T978 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.3816967097 Jun 13 01:33:05 PM PDT 24 Jun 13 01:33:08 PM PDT 24 154630450 ps
T979 /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.1000633592 Jun 13 01:34:40 PM PDT 24 Jun 13 01:34:42 PM PDT 24 95145171 ps
T980 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.3794690789 Jun 13 01:33:05 PM PDT 24 Jun 13 01:33:07 PM PDT 24 42944799 ps
T186 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.726232226 Jun 13 01:33:41 PM PDT 24 Jun 13 01:33:43 PM PDT 24 76302795 ps
T122 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.2426863118 Jun 13 01:32:59 PM PDT 24 Jun 13 01:33:03 PM PDT 24 141894744 ps
T981 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.1843287218 Jun 13 01:34:20 PM PDT 24 Jun 13 01:34:22 PM PDT 24 353707378 ps
T982 /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.3467987547 Jun 13 01:34:25 PM PDT 24 Jun 13 01:34:27 PM PDT 24 39851413 ps
T115 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.3914002543 Jun 13 01:34:33 PM PDT 24 Jun 13 01:34:37 PM PDT 24 84999688 ps
T983 /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.3471616501 Jun 13 01:34:20 PM PDT 24 Jun 13 01:34:22 PM PDT 24 18080301 ps
T984 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.1732376418 Jun 13 01:33:23 PM PDT 24 Jun 13 01:33:24 PM PDT 24 85153518 ps
T985 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.4197015412 Jun 13 01:34:41 PM PDT 24 Jun 13 01:34:44 PM PDT 24 43599254 ps
T986 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.1300679716 Jun 13 01:33:31 PM PDT 24 Jun 13 01:33:35 PM PDT 24 2450930784 ps
T987 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.1247269823 Jun 13 01:33:19 PM PDT 24 Jun 13 01:33:21 PM PDT 24 21634547 ps
T988 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.228960390 Jun 13 01:34:33 PM PDT 24 Jun 13 01:34:36 PM PDT 24 79403315 ps
T989 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.1500883668 Jun 13 01:34:08 PM PDT 24 Jun 13 01:34:11 PM PDT 24 79288603 ps
T120 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.787695753 Jun 13 01:34:32 PM PDT 24 Jun 13 01:34:35 PM PDT 24 48993542 ps
T990 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.3585092306 Jun 13 01:33:46 PM PDT 24 Jun 13 01:33:48 PM PDT 24 82550640 ps
T121 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.2505793674 Jun 13 01:34:20 PM PDT 24 Jun 13 01:34:25 PM PDT 24 227356139 ps
T991 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.3702450388 Jun 13 01:34:04 PM PDT 24 Jun 13 01:34:05 PM PDT 24 164204168 ps
T992 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.40076187 Jun 13 01:34:01 PM PDT 24 Jun 13 01:34:03 PM PDT 24 45449983 ps
T993 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.1776281536 Jun 13 01:34:41 PM PDT 24 Jun 13 01:34:43 PM PDT 24 21333265 ps
T187 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.1962554155 Jun 13 01:33:26 PM PDT 24 Jun 13 01:33:28 PM PDT 24 14947210 ps
T994 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.795263187 Jun 13 01:33:20 PM PDT 24 Jun 13 01:33:22 PM PDT 24 27180924 ps
T995 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.3365518419 Jun 13 01:33:21 PM PDT 24 Jun 13 01:33:23 PM PDT 24 34393972 ps

Test location /workspace/coverage/default/49.lc_ctrl_sec_mubi.96567256
Short name T9
Test name
Test status
Simulation time 1432833960 ps
CPU time 12.67 seconds
Started Jun 13 01:46:20 PM PDT 24
Finished Jun 13 01:46:34 PM PDT 24
Peak memory 225804 kb
Host smart-23db842b-ae48-4de5-a579-d9bdf54f0ac8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96567256 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_mubi.96567256
Directory /workspace/49.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/14.lc_ctrl_stress_all.3257160443
Short name T18
Test name
Test status
Simulation time 8954310071 ps
CPU time 82.17 seconds
Started Jun 13 01:43:28 PM PDT 24
Finished Jun 13 01:44:51 PM PDT 24
Peak memory 253588 kb
Host smart-b4fb3f68-d198-44a1-9988-09cbffe7009f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257160443 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.lc_ctrl_stress_all.3257160443
Directory /workspace/14.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.lc_ctrl_security_escalation.3221105400
Short name T11
Test name
Test status
Simulation time 1228365628 ps
CPU time 9.26 seconds
Started Jun 13 01:45:51 PM PDT 24
Finished Jun 13 01:46:02 PM PDT 24
Peak memory 218280 kb
Host smart-8b13b04d-2e50-4260-a70b-54f1c3c59225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221105400 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_security_escalation.3221105400
Directory /workspace/43.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all_with_rand_reset.2384969263
Short name T32
Test name
Test status
Simulation time 16359716840 ps
CPU time 508.89 seconds
Started Jun 13 01:45:24 PM PDT 24
Finished Jun 13 01:53:53 PM PDT 24
Peak memory 280324 kb
Host smart-47253675-fc2f-4e4d-8834-b9f1fd2cb87f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2384969263 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_stress_all_with_rand_reset.2384969263
Directory /workspace/36.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.909953128
Short name T100
Test name
Test status
Simulation time 27856566 ps
CPU time 2.09 seconds
Started Jun 13 01:34:28 PM PDT 24
Finished Jun 13 01:34:31 PM PDT 24
Peak memory 218292 kb
Host smart-9a2a8b89-75d8-419b-8649-8b281486c45b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909953128 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 14.lc_ctrl_csr_mem_rw_with_rand_reset.909953128
Directory /workspace/14.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_mux.1972263686
Short name T16
Test name
Test status
Simulation time 618211530 ps
CPU time 11.16 seconds
Started Jun 13 01:43:25 PM PDT 24
Finished Jun 13 01:43:37 PM PDT 24
Peak memory 218248 kb
Host smart-ecdb47e7-2945-4873-a131-9a62c09a15a6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972263686 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_mux.
1972263686
Directory /workspace/14.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/21.lc_ctrl_security_escalation.2982526076
Short name T263
Test name
Test status
Simulation time 1656194960 ps
CPU time 9.06 seconds
Started Jun 13 01:44:08 PM PDT 24
Finished Jun 13 01:44:19 PM PDT 24
Peak memory 226080 kb
Host smart-bebec83e-62bd-4d4d-a923-6510ce7d3a13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982526076 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_security_escalation.2982526076
Directory /workspace/21.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/3.lc_ctrl_volatile_unlock_smoke.297612475
Short name T28
Test name
Test status
Simulation time 13710988 ps
CPU time 0.81 seconds
Started Jun 13 01:41:46 PM PDT 24
Finished Jun 13 01:41:48 PM PDT 24
Peak memory 208936 kb
Host smart-c1ef192b-1f88-4cbc-8e5f-36e3e4572996
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297612475 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctr
l_volatile_unlock_smoke.297612475
Directory /workspace/3.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_cm.4241873436
Short name T53
Test name
Test status
Simulation time 3676628765 ps
CPU time 38.77 seconds
Started Jun 13 01:41:28 PM PDT 24
Finished Jun 13 01:42:08 PM PDT 24
Peak memory 282436 kb
Host smart-935ec220-5e2a-489e-8be6-c6b682f8e5d5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241873436 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_cm.4241873436
Directory /workspace/0.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all.2061699874
Short name T151
Test name
Test status
Simulation time 13771580729 ps
CPU time 180.99 seconds
Started Jun 13 01:44:36 PM PDT 24
Finished Jun 13 01:47:37 PM PDT 24
Peak memory 421924 kb
Host smart-91d6ea73-05af-4c75-87fd-7701c042e4ce
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061699874 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.lc_ctrl_stress_all.2061699874
Directory /workspace/26.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_access.857409530
Short name T6
Test name
Test status
Simulation time 349065171 ps
CPU time 4.15 seconds
Started Jun 13 01:43:23 PM PDT 24
Finished Jun 13 01:43:28 PM PDT 24
Peak memory 217236 kb
Host smart-66aaa35f-5266-4fd3-9ddc-ea515a4d64a7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857409530 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_access.857409530
Directory /workspace/14.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all_with_rand_reset.4054431813
Short name T137
Test name
Test status
Simulation time 141226409047 ps
CPU time 1963.75 seconds
Started Jun 13 01:45:26 PM PDT 24
Finished Jun 13 02:18:10 PM PDT 24
Peak memory 1537204 kb
Host smart-c5b3a80f-7007-479e-b9c3-cc9a8e0585e2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4054431813 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_stress_all_with_rand_reset.4054431813
Directory /workspace/37.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.lc_ctrl_alert_test.2931648657
Short name T79
Test name
Test status
Simulation time 44073506 ps
CPU time 0.96 seconds
Started Jun 13 01:44:09 PM PDT 24
Finished Jun 13 01:44:11 PM PDT 24
Peak memory 209020 kb
Host smart-dfc4c298-8e2d-49fa-a76f-6455e8a8cbe0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931648657 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_alert_test.2931648657
Directory /workspace/20.lc_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.3784198626
Short name T117
Test name
Test status
Simulation time 214590940 ps
CPU time 2.85 seconds
Started Jun 13 01:33:10 PM PDT 24
Finished Jun 13 01:33:13 PM PDT 24
Peak memory 222396 kb
Host smart-bb479de6-9a11-4c3a-972d-67ca827b8a73
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784198626 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_intg_
err.3784198626
Directory /workspace/1.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/47.lc_ctrl_stress_all_with_rand_reset.1344115801
Short name T82
Test name
Test status
Simulation time 18804098153 ps
CPU time 376.7 seconds
Started Jun 13 01:46:13 PM PDT 24
Finished Jun 13 01:52:32 PM PDT 24
Peak memory 281356 kb
Host smart-94f59813-4d75-4fb6-8bf2-294ba4676589
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1344115801 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_stress_all_with_rand_reset.1344115801
Directory /workspace/47.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.719707223
Short name T177
Test name
Test status
Simulation time 30358505 ps
CPU time 1.09 seconds
Started Jun 13 01:34:31 PM PDT 24
Finished Jun 13 01:34:32 PM PDT 24
Peak memory 209952 kb
Host smart-046edcdb-70a6-4bc9-85b1-23b4c7ab7084
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719707223 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_csr_rw.719707223
Directory /workspace/11.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.563223482
Short name T132
Test name
Test status
Simulation time 373191902 ps
CPU time 4.6 seconds
Started Jun 13 01:33:20 PM PDT 24
Finished Jun 13 01:33:26 PM PDT 24
Peak memory 209892 kb
Host smart-76b13d25-a2b3-4775-a4f2-3437b3ef5347
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563223482 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 2.lc_ctrl_jtag_csr_aliasing.563223482
Directory /workspace/2.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/default/9.lc_ctrl_stress_all_with_rand_reset.1064812016
Short name T140
Test name
Test status
Simulation time 46375438029 ps
CPU time 1077.1 seconds
Started Jun 13 01:42:48 PM PDT 24
Finished Jun 13 02:00:48 PM PDT 24
Peak memory 496796 kb
Host smart-cd465b1f-2bf9-40eb-bdf8-cdecbded9cbf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1064812016 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_stress_all_with_rand_reset.1064812016
Directory /workspace/9.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_failure.2846509330
Short name T2
Test name
Test status
Simulation time 298793714 ps
CPU time 25.01 seconds
Started Jun 13 01:46:05 PM PDT 24
Finished Jun 13 01:46:32 PM PDT 24
Peak memory 250904 kb
Host smart-59134baa-eaeb-4e5f-8a08-ba3479cf758a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846509330 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_failure.2846509330
Directory /workspace/45.lc_ctrl_state_failure/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.2741546968
Short name T99
Test name
Test status
Simulation time 209589161 ps
CPU time 3.14 seconds
Started Jun 13 01:34:35 PM PDT 24
Finished Jun 13 01:34:38 PM PDT 24
Peak memory 218236 kb
Host smart-66633a5b-177d-4ba9-8c61-b5ec5ebcf736
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741546968 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_errors.2741546968
Directory /workspace/17.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.3914002543
Short name T115
Test name
Test status
Simulation time 84999688 ps
CPU time 2.71 seconds
Started Jun 13 01:34:33 PM PDT 24
Finished Jun 13 01:34:37 PM PDT 24
Peak memory 222604 kb
Host smart-3304475d-0795-477e-9d26-60ae19f9f987
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914002543 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_intg
_err.3914002543
Directory /workspace/15.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.2292630962
Short name T131
Test name
Test status
Simulation time 106828164 ps
CPU time 2.83 seconds
Started Jun 13 01:34:26 PM PDT 24
Finished Jun 13 01:34:29 PM PDT 24
Peak memory 222600 kb
Host smart-6b9b7b5a-b61d-4198-9899-1184e99debfd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292630962 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_intg
_err.2292630962
Directory /workspace/14.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all_with_rand_reset.2229908767
Short name T47
Test name
Test status
Simulation time 233874275805 ps
CPU time 855.67 seconds
Started Jun 13 01:43:19 PM PDT 24
Finished Jun 13 01:57:35 PM PDT 24
Peak memory 464068 kb
Host smart-91c44a70-6179-4674-81fa-d557661fd371
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2229908767 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_stress_all_with_rand_reset.2229908767
Directory /workspace/13.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.lc_ctrl_smoke.3891238471
Short name T34
Test name
Test status
Simulation time 119812136 ps
CPU time 2.35 seconds
Started Jun 13 01:43:55 PM PDT 24
Finished Jun 13 01:43:58 PM PDT 24
Peak memory 217772 kb
Host smart-7862871d-8fcf-469c-85d0-103a78e35884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891238471 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_smoke.3891238471
Directory /workspace/19.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_security_escalation.3044979558
Short name T54
Test name
Test status
Simulation time 203543591 ps
CPU time 9.13 seconds
Started Jun 13 01:41:20 PM PDT 24
Finished Jun 13 01:41:31 PM PDT 24
Peak memory 225024 kb
Host smart-e6e78002-fc5d-4207-8396-f20f302ed75b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044979558 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_security_escalation.3044979558
Directory /workspace/0.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.219567092
Short name T106
Test name
Test status
Simulation time 26253282 ps
CPU time 1.02 seconds
Started Jun 13 01:33:23 PM PDT 24
Finished Jun 13 01:33:25 PM PDT 24
Peak memory 209996 kb
Host smart-b40c0466-b54e-40ee-ba5a-121448469622
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219567092 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
same_csr_outstanding.219567092
Directory /workspace/2.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.446631642
Short name T114
Test name
Test status
Simulation time 522510897 ps
CPU time 4.13 seconds
Started Jun 13 01:33:42 PM PDT 24
Finished Jun 13 01:33:46 PM PDT 24
Peak memory 218180 kb
Host smart-5626a29a-af88-49b6-8b24-2e93c9a874ef
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446631642 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_intg_e
rr.446631642
Directory /workspace/4.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_mubi.3118312807
Short name T42
Test name
Test status
Simulation time 426904919 ps
CPU time 14.18 seconds
Started Jun 13 01:44:41 PM PDT 24
Finished Jun 13 01:44:55 PM PDT 24
Peak memory 226076 kb
Host smart-cbd69210-7dd7-4ce8-b2a9-da2443eb1f60
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118312807 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_mubi.3118312807
Directory /workspace/27.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.2426863118
Short name T122
Test name
Test status
Simulation time 141894744 ps
CPU time 4.03 seconds
Started Jun 13 01:32:59 PM PDT 24
Finished Jun 13 01:33:03 PM PDT 24
Peak memory 218192 kb
Host smart-6de35cf7-8634-4bd3-b02e-6485b557b80a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426863118 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_intg_
err.2426863118
Directory /workspace/0.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.3357937404
Short name T118
Test name
Test status
Simulation time 267926894 ps
CPU time 2.88 seconds
Started Jun 13 01:34:32 PM PDT 24
Finished Jun 13 01:34:35 PM PDT 24
Peak memory 218140 kb
Host smart-5c45e81c-4c71-4e9f-b14b-9a6e58abc709
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357937404 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_intg
_err.3357937404
Directory /workspace/12.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.3838748856
Short name T111
Test name
Test status
Simulation time 409907950 ps
CPU time 4.07 seconds
Started Jun 13 01:34:06 PM PDT 24
Finished Jun 13 01:34:12 PM PDT 24
Peak memory 218200 kb
Host smart-35ba4665-8d92-45d5-9d41-0277581e76e0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838748856 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_intg_
err.3838748856
Directory /workspace/7.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_claim_transition_if.8304756
Short name T202
Test name
Test status
Simulation time 96686841 ps
CPU time 0.93 seconds
Started Jun 13 01:41:21 PM PDT 24
Finished Jun 13 01:41:24 PM PDT 24
Peak memory 208948 kb
Host smart-1843210a-05f1-4da2-81e2-205717673054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8304756 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_claim_transition_if.8304756
Directory /workspace/0.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/3.lc_ctrl_claim_transition_if.4138108212
Short name T198
Test name
Test status
Simulation time 12684615 ps
CPU time 0.94 seconds
Started Jun 13 01:41:47 PM PDT 24
Finished Jun 13 01:41:49 PM PDT 24
Peak memory 209020 kb
Host smart-de5ef7d1-99ae-41cc-b3a0-6e0af6bc6b17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138108212 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_claim_transition_if.4138108212
Directory /workspace/3.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/4.lc_ctrl_claim_transition_if.3095384128
Short name T91
Test name
Test status
Simulation time 32540761 ps
CPU time 0.77 seconds
Started Jun 13 01:41:56 PM PDT 24
Finished Jun 13 01:41:57 PM PDT 24
Peak memory 208996 kb
Host smart-03df4480-67ba-4e59-a52f-7e132fbfae73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3095384128 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_claim_transition_if.3095384128
Directory /workspace/4.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/7.lc_ctrl_claim_transition_if.1774413285
Short name T200
Test name
Test status
Simulation time 24248638 ps
CPU time 0.94 seconds
Started Jun 13 01:42:28 PM PDT 24
Finished Jun 13 01:42:29 PM PDT 24
Peak memory 209004 kb
Host smart-56ef6cde-f1cf-4007-993d-b697da7c5883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774413285 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_claim_transition_if.1774413285
Directory /workspace/7.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.3794690789
Short name T980
Test name
Test status
Simulation time 42944799 ps
CPU time 1.52 seconds
Started Jun 13 01:33:05 PM PDT 24
Finished Jun 13 01:33:07 PM PDT 24
Peak memory 218300 kb
Host smart-c44deed0-eacf-4e7e-9337-34013209003b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794690789 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 0.lc_ctrl_csr_mem_rw_with_rand_reset.3794690789
Directory /workspace/0.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.3647002290
Short name T128
Test name
Test status
Simulation time 336859171 ps
CPU time 1.88 seconds
Started Jun 13 01:34:30 PM PDT 24
Finished Jun 13 01:34:33 PM PDT 24
Peak memory 222236 kb
Host smart-02306862-d762-483f-822c-c71c17da6ed7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647002290 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_intg
_err.3647002290
Directory /workspace/13.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.2680570469
Short name T124
Test name
Test status
Simulation time 58146248 ps
CPU time 2.75 seconds
Started Jun 13 01:34:39 PM PDT 24
Finished Jun 13 01:34:42 PM PDT 24
Peak memory 218160 kb
Host smart-25e6db68-5a8d-4360-847d-00df98647435
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680570469 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_intg
_err.2680570469
Directory /workspace/19.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.1145371956
Short name T129
Test name
Test status
Simulation time 373107255 ps
CPU time 2.99 seconds
Started Jun 13 01:33:36 PM PDT 24
Finished Jun 13 01:33:40 PM PDT 24
Peak memory 222940 kb
Host smart-0e537313-6955-43b6-84ca-c7888e53fe9e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145371956 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_intg_
err.1145371956
Directory /workspace/3.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.3260716215
Short name T130
Test name
Test status
Simulation time 63924406 ps
CPU time 2.86 seconds
Started Jun 13 01:34:21 PM PDT 24
Finished Jun 13 01:34:25 PM PDT 24
Peak memory 218224 kb
Host smart-1adc6ef0-8b6b-4c9c-9a1e-e68d3ebd2d94
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260716215 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_intg_
err.3260716215
Directory /workspace/9.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/30.lc_ctrl_errors.995876563
Short name T46
Test name
Test status
Simulation time 327652626 ps
CPU time 10.01 seconds
Started Jun 13 01:44:53 PM PDT 24
Finished Jun 13 01:45:04 PM PDT 24
Peak memory 218296 kb
Host smart-422daf38-a160-4867-9423-93b7ba5595a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995876563 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_errors.995876563
Directory /workspace/30.lc_ctrl_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_failure.2872199269
Short name T281
Test name
Test status
Simulation time 267653208 ps
CPU time 16.6 seconds
Started Jun 13 01:43:06 PM PDT 24
Finished Jun 13 01:43:23 PM PDT 24
Peak memory 250904 kb
Host smart-c735cef4-2148-4d67-a69f-f220fded26cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872199269 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_failure.2872199269
Directory /workspace/12.lc_ctrl_state_failure/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.2833650863
Short name T183
Test name
Test status
Simulation time 163195547 ps
CPU time 1.32 seconds
Started Jun 13 01:33:03 PM PDT 24
Finished Jun 13 01:33:05 PM PDT 24
Peak memory 217832 kb
Host smart-0cc1c4db-91e1-4335-ae44-1668b3308c9b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833650863 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_aliasin
g.2833650863
Directory /workspace/0.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.436187556
Short name T913
Test name
Test status
Simulation time 449792819 ps
CPU time 1.89 seconds
Started Jun 13 01:32:58 PM PDT 24
Finished Jun 13 01:33:00 PM PDT 24
Peak memory 209976 kb
Host smart-e720cd1c-0cd3-452b-844f-081f63ed6b06
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436187556 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_bit_bash
.436187556
Directory /workspace/0.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.2486214033
Short name T915
Test name
Test status
Simulation time 42705257 ps
CPU time 1.07 seconds
Started Jun 13 01:32:58 PM PDT 24
Finished Jun 13 01:33:00 PM PDT 24
Peak memory 210540 kb
Host smart-18e9bb3a-4bea-4462-bb60-0eaf9cc6d151
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486214033 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_hw_rese
t.2486214033
Directory /workspace/0.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.3167059321
Short name T179
Test name
Test status
Simulation time 26126228 ps
CPU time 0.9 seconds
Started Jun 13 01:32:58 PM PDT 24
Finished Jun 13 01:32:59 PM PDT 24
Peak memory 209704 kb
Host smart-f8d04491-12cc-42b7-89d5-9348529ebf46
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167059321 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_rw.3167059321
Directory /workspace/0.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.2504611688
Short name T876
Test name
Test status
Simulation time 228443628 ps
CPU time 1.2 seconds
Started Jun 13 01:32:57 PM PDT 24
Finished Jun 13 01:32:59 PM PDT 24
Peak memory 209064 kb
Host smart-e049e07b-ee56-44e5-9b88-f6c0de34a184
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504611688 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.lc_ctrl_jtag_alert_test.2504611688
Directory /workspace/0.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.1659325283
Short name T935
Test name
Test status
Simulation time 1921687654 ps
CPU time 4.68 seconds
Started Jun 13 01:32:51 PM PDT 24
Finished Jun 13 01:32:57 PM PDT 24
Peak memory 209392 kb
Host smart-fea2f779-8666-436b-b455-a34f529c1901
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659325283 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_aliasing.1659325283
Directory /workspace/0.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.2732860480
Short name T906
Test name
Test status
Simulation time 5518694059 ps
CPU time 29.66 seconds
Started Jun 13 01:32:50 PM PDT 24
Finished Jun 13 01:33:21 PM PDT 24
Peak memory 217916 kb
Host smart-09aeb233-36a8-46a5-a907-be3112868e3e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732860480 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_bit_bash.2732860480
Directory /workspace/0.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.2082358805
Short name T887
Test name
Test status
Simulation time 74347761 ps
CPU time 1.53 seconds
Started Jun 13 01:32:50 PM PDT 24
Finished Jun 13 01:32:52 PM PDT 24
Peak memory 210912 kb
Host smart-95882bba-2adb-439f-a99f-4b563dac8807
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082358805 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_hw_reset.2082358805
Directory /workspace/0.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1761095982
Short name T961
Test name
Test status
Simulation time 55910117 ps
CPU time 2.25 seconds
Started Jun 13 01:32:59 PM PDT 24
Finished Jun 13 01:33:02 PM PDT 24
Peak memory 218256 kb
Host smart-2848209a-1cb6-4ce3-96e1-b1b18e6b6d26
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176109
5982 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1761095982
Directory /workspace/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.1456339228
Short name T897
Test name
Test status
Simulation time 282669334 ps
CPU time 1.98 seconds
Started Jun 13 01:32:51 PM PDT 24
Finished Jun 13 01:32:53 PM PDT 24
Peak memory 209904 kb
Host smart-ce895c0a-ae9d-41a2-80e8-aca11dd8372b
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456339228 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.lc_ctrl_jtag_csr_rw.1456339228
Directory /workspace/0.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.998219438
Short name T194
Test name
Test status
Simulation time 38806553 ps
CPU time 1.23 seconds
Started Jun 13 01:32:56 PM PDT 24
Finished Jun 13 01:32:58 PM PDT 24
Peak memory 218228 kb
Host smart-1ca79974-8603-46a4-b3e5-4761c9d234ac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998219438 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.lc_ctrl_jtag_same_csr_outstanding.998219438
Directory /workspace/0.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.358725
Short name T941
Test name
Test status
Simulation time 42357290 ps
CPU time 1.04 seconds
Started Jun 13 01:33:02 PM PDT 24
Finished Jun 13 01:33:04 PM PDT 24
Peak memory 209276 kb
Host smart-daeac777-dcf4-47b6-964e-ee88968f1c5b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358725 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sam
e_csr_outstanding.358725
Directory /workspace/0.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.283297153
Short name T898
Test name
Test status
Simulation time 294242012 ps
CPU time 3.11 seconds
Started Jun 13 01:32:58 PM PDT 24
Finished Jun 13 01:33:02 PM PDT 24
Peak memory 218228 kb
Host smart-ac62bd42-ff15-45c6-8f76-dc47112234e1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283297153 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_errors.283297153
Directory /workspace/0.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.2422856953
Short name T175
Test name
Test status
Simulation time 36480627 ps
CPU time 0.96 seconds
Started Jun 13 01:33:20 PM PDT 24
Finished Jun 13 01:33:22 PM PDT 24
Peak memory 209960 kb
Host smart-5ea9f10a-0228-46b7-805e-c30392f8d1fe
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422856953 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_aliasin
g.2422856953
Directory /workspace/1.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.795263187
Short name T994
Test name
Test status
Simulation time 27180924 ps
CPU time 1.62 seconds
Started Jun 13 01:33:20 PM PDT 24
Finished Jun 13 01:33:22 PM PDT 24
Peak memory 209948 kb
Host smart-07dae65a-526a-475f-836a-cef5f045d480
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795263187 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_bit_bash
.795263187
Directory /workspace/1.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.1181928930
Short name T880
Test name
Test status
Simulation time 17907664 ps
CPU time 0.93 seconds
Started Jun 13 01:33:22 PM PDT 24
Finished Jun 13 01:33:24 PM PDT 24
Peak memory 210376 kb
Host smart-24fff527-e4fc-4fb3-a046-df3e541a2efd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181928930 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_hw_rese
t.1181928930
Directory /workspace/1.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.425864317
Short name T945
Test name
Test status
Simulation time 74670596 ps
CPU time 1.75 seconds
Started Jun 13 01:33:20 PM PDT 24
Finished Jun 13 01:33:22 PM PDT 24
Peak memory 219372 kb
Host smart-89483f78-8f2a-47ca-ba22-1e9eb60a7fdf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425864317 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 1.lc_ctrl_csr_mem_rw_with_rand_reset.425864317
Directory /workspace/1.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.2980786645
Short name T883
Test name
Test status
Simulation time 21649141 ps
CPU time 0.96 seconds
Started Jun 13 01:33:24 PM PDT 24
Finished Jun 13 01:33:25 PM PDT 24
Peak memory 209284 kb
Host smart-98716370-11ab-4b8e-b4b1-ab4322ab74eb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980786645 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_rw.2980786645
Directory /workspace/1.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.1428486853
Short name T922
Test name
Test status
Simulation time 32180246 ps
CPU time 1.11 seconds
Started Jun 13 01:33:11 PM PDT 24
Finished Jun 13 01:33:13 PM PDT 24
Peak memory 209808 kb
Host smart-47af049f-fadd-4d5b-b012-d5f5e1fb25c5
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428486853 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.lc_ctrl_jtag_alert_test.1428486853
Directory /workspace/1.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.3749074653
Short name T976
Test name
Test status
Simulation time 2466087688 ps
CPU time 2.98 seconds
Started Jun 13 01:33:11 PM PDT 24
Finished Jun 13 01:33:14 PM PDT 24
Peak memory 209824 kb
Host smart-23b58d76-e816-49e6-b091-419dab39e9f0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749074653 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_aliasing.3749074653
Directory /workspace/1.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.4290200051
Short name T975
Test name
Test status
Simulation time 3563125525 ps
CPU time 11.69 seconds
Started Jun 13 01:33:20 PM PDT 24
Finished Jun 13 01:33:33 PM PDT 24
Peak memory 209884 kb
Host smart-620cad17-fcd3-4a64-b53b-a17f3884c14d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290200051 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_bit_bash.4290200051
Directory /workspace/1.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.3816967097
Short name T978
Test name
Test status
Simulation time 154630450 ps
CPU time 3.07 seconds
Started Jun 13 01:33:05 PM PDT 24
Finished Jun 13 01:33:08 PM PDT 24
Peak memory 218080 kb
Host smart-620d8473-4874-4474-8d72-8cb194057b5a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816967097 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_hw_reset.3816967097
Directory /workspace/1.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2352969272
Short name T135
Test name
Test status
Simulation time 315541486 ps
CPU time 2.5 seconds
Started Jun 13 01:33:20 PM PDT 24
Finished Jun 13 01:33:23 PM PDT 24
Peak memory 219232 kb
Host smart-c2b48839-ed19-4a2a-8710-73afccd2bdd8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235296
9272 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2352969272
Directory /workspace/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.2836279016
Short name T963
Test name
Test status
Simulation time 235417482 ps
CPU time 2 seconds
Started Jun 13 01:33:04 PM PDT 24
Finished Jun 13 01:33:07 PM PDT 24
Peak memory 217412 kb
Host smart-632444a3-8c3b-4a40-8bf2-e73e8a1a994f
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836279016 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.lc_ctrl_jtag_csr_rw.2836279016
Directory /workspace/1.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.1247269823
Short name T987
Test name
Test status
Simulation time 21634547 ps
CPU time 1.2 seconds
Started Jun 13 01:33:19 PM PDT 24
Finished Jun 13 01:33:21 PM PDT 24
Peak memory 217968 kb
Host smart-d1e2ce3c-0d4a-458a-9f0b-253ea1af655c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247269823 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.lc_ctrl_jtag_same_csr_outstanding.1247269823
Directory /workspace/1.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.1855749688
Short name T965
Test name
Test status
Simulation time 108092891 ps
CPU time 1.13 seconds
Started Jun 13 01:33:18 PM PDT 24
Finished Jun 13 01:33:20 PM PDT 24
Peak memory 210044 kb
Host smart-daf8ce6e-7818-4b83-96cc-62ab3fe67c2d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855749688 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl
_same_csr_outstanding.1855749688
Directory /workspace/1.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.3032469987
Short name T936
Test name
Test status
Simulation time 64020718 ps
CPU time 2.95 seconds
Started Jun 13 01:33:11 PM PDT 24
Finished Jun 13 01:33:15 PM PDT 24
Peak memory 218172 kb
Host smart-0b984ad9-7714-4263-bd9e-8c6f3720b86c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032469987 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_errors.3032469987
Directory /workspace/1.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.765445159
Short name T966
Test name
Test status
Simulation time 46811395 ps
CPU time 1.62 seconds
Started Jun 13 01:34:26 PM PDT 24
Finished Jun 13 01:34:29 PM PDT 24
Peak memory 218348 kb
Host smart-18ca85b9-2154-4b84-b7d2-4427ee8af61d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765445159 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 10.lc_ctrl_csr_mem_rw_with_rand_reset.765445159
Directory /workspace/10.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.2530791929
Short name T921
Test name
Test status
Simulation time 31050138 ps
CPU time 0.94 seconds
Started Jun 13 01:34:29 PM PDT 24
Finished Jun 13 01:34:30 PM PDT 24
Peak memory 209984 kb
Host smart-d3993f5c-8da6-4050-8b87-d85f7658c9c3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530791929 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_csr_rw.2530791929
Directory /workspace/10.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.3471616501
Short name T983
Test name
Test status
Simulation time 18080301 ps
CPU time 1.02 seconds
Started Jun 13 01:34:20 PM PDT 24
Finished Jun 13 01:34:22 PM PDT 24
Peak memory 209180 kb
Host smart-6a706c71-993c-4547-8848-94c35ee605d8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471616501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctr
l_same_csr_outstanding.3471616501
Directory /workspace/10.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.1783356582
Short name T126
Test name
Test status
Simulation time 497863991 ps
CPU time 3.06 seconds
Started Jun 13 01:34:22 PM PDT 24
Finished Jun 13 01:34:25 PM PDT 24
Peak memory 218212 kb
Host smart-ade2d01b-26d9-436d-984d-41ad8557e374
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783356582 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_errors.1783356582
Directory /workspace/10.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.2505793674
Short name T121
Test name
Test status
Simulation time 227356139 ps
CPU time 4.23 seconds
Started Jun 13 01:34:20 PM PDT 24
Finished Jun 13 01:34:25 PM PDT 24
Peak memory 218196 kb
Host smart-7b249b00-e7ce-41b6-ba5a-3cf77dfc071c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505793674 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_intg
_err.2505793674
Directory /workspace/10.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.595522547
Short name T943
Test name
Test status
Simulation time 21390997 ps
CPU time 1.38 seconds
Started Jun 13 01:34:30 PM PDT 24
Finished Jun 13 01:34:31 PM PDT 24
Peak memory 219624 kb
Host smart-c0f8902d-5bfb-4dd1-ba8b-0925908e93c4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595522547 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 11.lc_ctrl_csr_mem_rw_with_rand_reset.595522547
Directory /workspace/11.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.840035106
Short name T907
Test name
Test status
Simulation time 38358228 ps
CPU time 1.89 seconds
Started Jun 13 01:34:28 PM PDT 24
Finished Jun 13 01:34:31 PM PDT 24
Peak memory 212076 kb
Host smart-5b1ab431-81e0-4f5f-a0e2-04719f1a4ed0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840035106 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl
_same_csr_outstanding.840035106
Directory /workspace/11.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.1802504000
Short name T948
Test name
Test status
Simulation time 101466590 ps
CPU time 3.36 seconds
Started Jun 13 01:34:26 PM PDT 24
Finished Jun 13 01:34:30 PM PDT 24
Peak memory 218192 kb
Host smart-3e08e17b-9510-4122-92f8-bde3f6f742d7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802504000 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_errors.1802504000
Directory /workspace/11.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.2272626487
Short name T112
Test name
Test status
Simulation time 399272754 ps
CPU time 4.13 seconds
Started Jun 13 01:34:31 PM PDT 24
Finished Jun 13 01:34:35 PM PDT 24
Peak memory 218148 kb
Host smart-9d5c3fa6-e7ca-4787-acd6-a3795581bc8e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272626487 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_intg
_err.2272626487
Directory /workspace/11.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.2652874412
Short name T929
Test name
Test status
Simulation time 74685014 ps
CPU time 1.39 seconds
Started Jun 13 01:34:27 PM PDT 24
Finished Jun 13 01:34:29 PM PDT 24
Peak memory 218596 kb
Host smart-1bd0a12d-a52f-46de-bfc0-923929ed5f3e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652874412 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 12.lc_ctrl_csr_mem_rw_with_rand_reset.2652874412
Directory /workspace/12.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.1796996
Short name T190
Test name
Test status
Simulation time 45198045 ps
CPU time 0.88 seconds
Started Jun 13 01:34:30 PM PDT 24
Finished Jun 13 01:34:32 PM PDT 24
Peak memory 209800 kb
Host smart-7dfb50ff-9225-4ad0-951e-6cb2b81ab796
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796996 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_csr_rw.1796996
Directory /workspace/12.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.3467987547
Short name T982
Test name
Test status
Simulation time 39851413 ps
CPU time 1.26 seconds
Started Jun 13 01:34:25 PM PDT 24
Finished Jun 13 01:34:27 PM PDT 24
Peak memory 209968 kb
Host smart-4ff15732-bc4c-49a5-bc3d-3ca7df7774e8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467987547 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctr
l_same_csr_outstanding.3467987547
Directory /workspace/12.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.4067790948
Short name T968
Test name
Test status
Simulation time 255840509 ps
CPU time 3.13 seconds
Started Jun 13 01:34:29 PM PDT 24
Finished Jun 13 01:34:33 PM PDT 24
Peak memory 218184 kb
Host smart-5ef35ae4-5baf-4151-b04a-dc1f195c794d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067790948 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_errors.4067790948
Directory /workspace/12.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.3427650733
Short name T878
Test name
Test status
Simulation time 95476772 ps
CPU time 1.75 seconds
Started Jun 13 01:34:28 PM PDT 24
Finished Jun 13 01:34:31 PM PDT 24
Peak memory 218516 kb
Host smart-4bacfb41-8873-40ae-a08e-337fc4c5ded5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427650733 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 13.lc_ctrl_csr_mem_rw_with_rand_reset.3427650733
Directory /workspace/13.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.4285286616
Short name T150
Test name
Test status
Simulation time 51927831 ps
CPU time 0.84 seconds
Started Jun 13 01:34:28 PM PDT 24
Finished Jun 13 01:34:29 PM PDT 24
Peak memory 209140 kb
Host smart-5420d6ea-b71d-4aa0-bd7c-1375e4ca43fd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285286616 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_csr_rw.4285286616
Directory /workspace/13.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.2227309317
Short name T899
Test name
Test status
Simulation time 90401562 ps
CPU time 1.13 seconds
Started Jun 13 01:34:28 PM PDT 24
Finished Jun 13 01:34:30 PM PDT 24
Peak memory 217792 kb
Host smart-472ce305-95fb-4ff8-a21b-61ef224eaa61
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227309317 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctr
l_same_csr_outstanding.2227309317
Directory /workspace/13.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.869502318
Short name T911
Test name
Test status
Simulation time 34038934 ps
CPU time 2.02 seconds
Started Jun 13 01:34:27 PM PDT 24
Finished Jun 13 01:34:30 PM PDT 24
Peak memory 218220 kb
Host smart-88bead2e-41b9-47b1-ad58-5e9beb0b0a26
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869502318 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_errors.869502318
Directory /workspace/13.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.3445798612
Short name T178
Test name
Test status
Simulation time 14780945 ps
CPU time 0.89 seconds
Started Jun 13 01:34:26 PM PDT 24
Finished Jun 13 01:34:28 PM PDT 24
Peak memory 209840 kb
Host smart-47b4c9f3-045b-4163-b2cf-f11c9c11cbf4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445798612 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_csr_rw.3445798612
Directory /workspace/14.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.1376645848
Short name T952
Test name
Test status
Simulation time 118944456 ps
CPU time 0.96 seconds
Started Jun 13 01:34:28 PM PDT 24
Finished Jun 13 01:34:30 PM PDT 24
Peak memory 209540 kb
Host smart-aca32bac-7058-46c9-b423-5bdfcfc089b2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376645848 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctr
l_same_csr_outstanding.1376645848
Directory /workspace/14.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.1322738335
Short name T950
Test name
Test status
Simulation time 54913512 ps
CPU time 1.9 seconds
Started Jun 13 01:34:26 PM PDT 24
Finished Jun 13 01:34:28 PM PDT 24
Peak memory 218184 kb
Host smart-c88696b0-c1d6-4026-9a75-23313e5ea168
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322738335 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_errors.1322738335
Directory /workspace/14.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.2332129627
Short name T879
Test name
Test status
Simulation time 228831868 ps
CPU time 1.24 seconds
Started Jun 13 01:34:32 PM PDT 24
Finished Jun 13 01:34:34 PM PDT 24
Peak memory 219492 kb
Host smart-d59a2331-f6dc-4a35-aafd-3d77d19a5141
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332129627 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 15.lc_ctrl_csr_mem_rw_with_rand_reset.2332129627
Directory /workspace/15.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.3595684877
Short name T964
Test name
Test status
Simulation time 26906847 ps
CPU time 0.96 seconds
Started Jun 13 01:34:33 PM PDT 24
Finished Jun 13 01:34:35 PM PDT 24
Peak memory 209948 kb
Host smart-d5c10e6b-4284-4eeb-acb9-8841667562de
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595684877 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_csr_rw.3595684877
Directory /workspace/15.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.1661783632
Short name T951
Test name
Test status
Simulation time 67955308 ps
CPU time 1.74 seconds
Started Jun 13 01:34:35 PM PDT 24
Finished Jun 13 01:34:37 PM PDT 24
Peak memory 211924 kb
Host smart-118130bf-566e-4672-bd9e-0c1c064024eb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661783632 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctr
l_same_csr_outstanding.1661783632
Directory /workspace/15.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.4060163449
Short name T108
Test name
Test status
Simulation time 76188394 ps
CPU time 1.43 seconds
Started Jun 13 01:34:34 PM PDT 24
Finished Jun 13 01:34:36 PM PDT 24
Peak memory 218308 kb
Host smart-8bd4ce08-56c9-4c4b-8acb-4eb98a1506c5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060163449 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_errors.4060163449
Directory /workspace/15.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.1740034883
Short name T890
Test name
Test status
Simulation time 106275229 ps
CPU time 1.32 seconds
Started Jun 13 01:34:32 PM PDT 24
Finished Jun 13 01:34:34 PM PDT 24
Peak memory 219200 kb
Host smart-f07def35-0178-48fa-a518-5e1f226f80f1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740034883 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 16.lc_ctrl_csr_mem_rw_with_rand_reset.1740034883
Directory /workspace/16.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.274992319
Short name T927
Test name
Test status
Simulation time 42917140 ps
CPU time 0.86 seconds
Started Jun 13 01:34:32 PM PDT 24
Finished Jun 13 01:34:34 PM PDT 24
Peak memory 209816 kb
Host smart-26be919d-13d7-4f8a-a890-d66972fa9fc5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274992319 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_csr_rw.274992319
Directory /workspace/16.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.3156968802
Short name T196
Test name
Test status
Simulation time 26892912 ps
CPU time 1.46 seconds
Started Jun 13 01:34:32 PM PDT 24
Finished Jun 13 01:34:34 PM PDT 24
Peak memory 210052 kb
Host smart-41cdb9a7-fb2c-4840-819b-b0c83a3738cb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156968802 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctr
l_same_csr_outstanding.3156968802
Directory /workspace/16.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.228960390
Short name T988
Test name
Test status
Simulation time 79403315 ps
CPU time 2.53 seconds
Started Jun 13 01:34:33 PM PDT 24
Finished Jun 13 01:34:36 PM PDT 24
Peak memory 218256 kb
Host smart-68b6a3eb-4903-43ed-b2fc-90ab3cba18fe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228960390 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_errors.228960390
Directory /workspace/16.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.787695753
Short name T120
Test name
Test status
Simulation time 48993542 ps
CPU time 2.38 seconds
Started Jun 13 01:34:32 PM PDT 24
Finished Jun 13 01:34:35 PM PDT 24
Peak memory 222388 kb
Host smart-0fa166d3-8a22-4ecc-ae8f-e9ba4d3a5379
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787695753 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_intg_
err.787695753
Directory /workspace/16.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.3145718670
Short name T926
Test name
Test status
Simulation time 75540860 ps
CPU time 1.19 seconds
Started Jun 13 01:34:42 PM PDT 24
Finished Jun 13 01:34:44 PM PDT 24
Peak memory 222616 kb
Host smart-ac92d66e-eb1e-434e-a716-fa998a8efd2a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145718670 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 17.lc_ctrl_csr_mem_rw_with_rand_reset.3145718670
Directory /workspace/17.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.3431204159
Short name T184
Test name
Test status
Simulation time 37375068 ps
CPU time 0.9 seconds
Started Jun 13 01:34:34 PM PDT 24
Finished Jun 13 01:34:35 PM PDT 24
Peak memory 209560 kb
Host smart-6c0c5917-4a98-4319-b1b0-9f4557831df8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431204159 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_csr_rw.3431204159
Directory /workspace/17.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.2767654015
Short name T923
Test name
Test status
Simulation time 26629231 ps
CPU time 1.48 seconds
Started Jun 13 01:34:39 PM PDT 24
Finished Jun 13 01:34:41 PM PDT 24
Peak memory 209964 kb
Host smart-8bd596d9-5656-4aaf-91a4-0b689b6276f5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767654015 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctr
l_same_csr_outstanding.2767654015
Directory /workspace/17.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.3257883287
Short name T116
Test name
Test status
Simulation time 75273888 ps
CPU time 2.57 seconds
Started Jun 13 01:34:32 PM PDT 24
Finished Jun 13 01:34:36 PM PDT 24
Peak memory 222504 kb
Host smart-0e360b51-6859-4367-aad3-bb6ffe3a54e0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257883287 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_intg
_err.3257883287
Directory /workspace/17.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.1776281536
Short name T993
Test name
Test status
Simulation time 21333265 ps
CPU time 1.26 seconds
Started Jun 13 01:34:41 PM PDT 24
Finished Jun 13 01:34:43 PM PDT 24
Peak memory 220308 kb
Host smart-4187d3fe-0b02-4872-bb39-04257c59ffea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776281536 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 18.lc_ctrl_csr_mem_rw_with_rand_reset.1776281536
Directory /workspace/18.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.1010876925
Short name T176
Test name
Test status
Simulation time 23950909 ps
CPU time 1.03 seconds
Started Jun 13 01:34:40 PM PDT 24
Finished Jun 13 01:34:42 PM PDT 24
Peak memory 209988 kb
Host smart-b208a44f-6c14-4edc-a93f-857b3fab5344
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010876925 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_csr_rw.1010876925
Directory /workspace/18.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.1000633592
Short name T979
Test name
Test status
Simulation time 95145171 ps
CPU time 1.48 seconds
Started Jun 13 01:34:40 PM PDT 24
Finished Jun 13 01:34:42 PM PDT 24
Peak memory 210076 kb
Host smart-36d90734-cb9b-46d7-bef9-f6ae4548c990
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000633592 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctr
l_same_csr_outstanding.1000633592
Directory /workspace/18.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.647105825
Short name T912
Test name
Test status
Simulation time 555540605 ps
CPU time 5.68 seconds
Started Jun 13 01:34:40 PM PDT 24
Finished Jun 13 01:34:46 PM PDT 24
Peak memory 218200 kb
Host smart-7b4b2578-f8ab-4a4a-97e7-fd65082a1f98
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647105825 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_errors.647105825
Directory /workspace/18.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.4197015412
Short name T985
Test name
Test status
Simulation time 43599254 ps
CPU time 2.34 seconds
Started Jun 13 01:34:41 PM PDT 24
Finished Jun 13 01:34:44 PM PDT 24
Peak memory 222560 kb
Host smart-8726a38a-2960-4f68-a815-ca905b4c716f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197015412 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_intg
_err.4197015412
Directory /workspace/18.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.34400776
Short name T103
Test name
Test status
Simulation time 30592552 ps
CPU time 2.25 seconds
Started Jun 13 01:34:39 PM PDT 24
Finished Jun 13 01:34:42 PM PDT 24
Peak memory 219936 kb
Host smart-8861b61c-9aa7-4d63-a9dd-6e97822eda70
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34400776 -assert nopostproc +UVM_TESTNAME=l
c_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.lc_ctrl_csr_mem_rw_with_rand_reset.34400776
Directory /workspace/19.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.2277919783
Short name T180
Test name
Test status
Simulation time 290350914 ps
CPU time 0.89 seconds
Started Jun 13 01:34:40 PM PDT 24
Finished Jun 13 01:34:41 PM PDT 24
Peak memory 209980 kb
Host smart-2c1abf15-c0fe-40b4-bc8f-77e7f1e7bed9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277919783 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_csr_rw.2277919783
Directory /workspace/19.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.400603316
Short name T937
Test name
Test status
Simulation time 24208098 ps
CPU time 1.12 seconds
Started Jun 13 01:34:42 PM PDT 24
Finished Jun 13 01:34:44 PM PDT 24
Peak memory 209976 kb
Host smart-a83d9f63-9d37-4a5d-8d07-fd6edb26c172
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400603316 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl
_same_csr_outstanding.400603316
Directory /workspace/19.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.3904986136
Short name T885
Test name
Test status
Simulation time 29270593 ps
CPU time 1.76 seconds
Started Jun 13 01:34:41 PM PDT 24
Finished Jun 13 01:34:44 PM PDT 24
Peak memory 218128 kb
Host smart-bcd48213-9c18-4dc3-ac85-33e16eb67268
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904986136 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_errors.3904986136
Directory /workspace/19.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.1665665308
Short name T185
Test name
Test status
Simulation time 165038752 ps
CPU time 1.78 seconds
Started Jun 13 01:33:22 PM PDT 24
Finished Jun 13 01:33:25 PM PDT 24
Peak memory 217788 kb
Host smart-97edc79a-a233-4891-9703-c50d05bef278
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665665308 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_aliasin
g.1665665308
Directory /workspace/2.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.2337927469
Short name T933
Test name
Test status
Simulation time 25389100 ps
CPU time 1.53 seconds
Started Jun 13 01:33:30 PM PDT 24
Finished Jun 13 01:33:32 PM PDT 24
Peak memory 209180 kb
Host smart-f9dc5b4e-cfdd-4d2c-bbbd-fa25b589924e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337927469 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_bit_bas
h.2337927469
Directory /workspace/2.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.1545410259
Short name T882
Test name
Test status
Simulation time 63640544 ps
CPU time 1.04 seconds
Started Jun 13 01:33:22 PM PDT 24
Finished Jun 13 01:33:24 PM PDT 24
Peak memory 212140 kb
Host smart-ffef4bf4-0ad1-4169-b48f-9259ebe7ed3b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545410259 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_hw_rese
t.1545410259
Directory /workspace/2.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.1383201046
Short name T947
Test name
Test status
Simulation time 20250203 ps
CPU time 1.85 seconds
Started Jun 13 01:33:22 PM PDT 24
Finished Jun 13 01:33:25 PM PDT 24
Peak memory 220204 kb
Host smart-a25a619d-1862-42e4-86ac-aba4eb5f6561
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383201046 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 2.lc_ctrl_csr_mem_rw_with_rand_reset.1383201046
Directory /workspace/2.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.1962554155
Short name T187
Test name
Test status
Simulation time 14947210 ps
CPU time 1.08 seconds
Started Jun 13 01:33:26 PM PDT 24
Finished Jun 13 01:33:28 PM PDT 24
Peak memory 209964 kb
Host smart-008b1554-b99a-4678-8ddf-ae1bf3f926df
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962554155 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_rw.1962554155
Directory /workspace/2.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.1806565898
Short name T942
Test name
Test status
Simulation time 49093310 ps
CPU time 1.27 seconds
Started Jun 13 01:33:23 PM PDT 24
Finished Jun 13 01:33:25 PM PDT 24
Peak memory 209128 kb
Host smart-9f19dc08-2562-499d-8013-4a41ac13ad57
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806565898 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.lc_ctrl_jtag_alert_test.1806565898
Directory /workspace/2.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.3948710636
Short name T940
Test name
Test status
Simulation time 1803040142 ps
CPU time 9.92 seconds
Started Jun 13 01:33:23 PM PDT 24
Finished Jun 13 01:33:34 PM PDT 24
Peak memory 209828 kb
Host smart-fddd9369-6f7b-4506-82e4-b232c0bd1d31
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948710636 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_bit_bash.3948710636
Directory /workspace/2.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.1367349869
Short name T877
Test name
Test status
Simulation time 292908339 ps
CPU time 2.58 seconds
Started Jun 13 01:33:22 PM PDT 24
Finished Jun 13 01:33:25 PM PDT 24
Peak memory 218104 kb
Host smart-78adc762-8848-4488-82c5-9e92089fe7ed
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367349869 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_hw_reset.1367349869
Directory /workspace/2.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4197629753
Short name T888
Test name
Test status
Simulation time 1848273687 ps
CPU time 3.96 seconds
Started Jun 13 01:33:22 PM PDT 24
Finished Jun 13 01:33:27 PM PDT 24
Peak memory 218528 kb
Host smart-b73bb41b-a453-4dd4-8f49-ae83de1d7ba3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419762
9753 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4197629753
Directory /workspace/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.3365518419
Short name T995
Test name
Test status
Simulation time 34393972 ps
CPU time 1.53 seconds
Started Jun 13 01:33:21 PM PDT 24
Finished Jun 13 01:33:23 PM PDT 24
Peak memory 209872 kb
Host smart-10dfbea4-6b6b-4c4d-8982-89356ad9c8ae
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365518419 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.lc_ctrl_jtag_csr_rw.3365518419
Directory /workspace/2.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.1732376418
Short name T984
Test name
Test status
Simulation time 85153518 ps
CPU time 1.04 seconds
Started Jun 13 01:33:23 PM PDT 24
Finished Jun 13 01:33:24 PM PDT 24
Peak memory 209992 kb
Host smart-789f0320-c175-4fd7-af38-e56de00cff35
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732376418 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.lc_ctrl_jtag_same_csr_outstanding.1732376418
Directory /workspace/2.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.2391879611
Short name T959
Test name
Test status
Simulation time 36503805 ps
CPU time 2.27 seconds
Started Jun 13 01:33:30 PM PDT 24
Finished Jun 13 01:33:33 PM PDT 24
Peak memory 218216 kb
Host smart-168ae7e8-6fd9-4815-b550-4ff40ff9f602
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391879611 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_errors.2391879611
Directory /workspace/2.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.2690049113
Short name T104
Test name
Test status
Simulation time 574975062 ps
CPU time 3.13 seconds
Started Jun 13 01:33:30 PM PDT 24
Finished Jun 13 01:33:33 PM PDT 24
Peak memory 222440 kb
Host smart-fc34ed53-7a68-46da-87da-c724d963dee6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690049113 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_intg_
err.2690049113
Directory /workspace/2.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.1953539407
Short name T932
Test name
Test status
Simulation time 24565566 ps
CPU time 0.99 seconds
Started Jun 13 01:33:35 PM PDT 24
Finished Jun 13 01:33:38 PM PDT 24
Peak memory 210008 kb
Host smart-93d5da44-dd07-4516-95b0-ecc4a650748c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953539407 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_aliasin
g.1953539407
Directory /workspace/3.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.893708082
Short name T973
Test name
Test status
Simulation time 186929412 ps
CPU time 1.22 seconds
Started Jun 13 01:33:36 PM PDT 24
Finished Jun 13 01:33:39 PM PDT 24
Peak memory 209168 kb
Host smart-f79034d6-d4d6-473c-822b-ec3c4c5497c7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893708082 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_bit_bash
.893708082
Directory /workspace/3.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.3523004168
Short name T181
Test name
Test status
Simulation time 22805202 ps
CPU time 1.4 seconds
Started Jun 13 01:33:37 PM PDT 24
Finished Jun 13 01:33:40 PM PDT 24
Peak memory 218720 kb
Host smart-d9c7626c-f791-4b03-bdbf-1246431a258c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523004168 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_hw_rese
t.3523004168
Directory /workspace/3.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.2559610363
Short name T123
Test name
Test status
Simulation time 22870619 ps
CPU time 1.74 seconds
Started Jun 13 01:33:34 PM PDT 24
Finished Jun 13 01:33:36 PM PDT 24
Peak memory 223020 kb
Host smart-b4b0676b-ced5-42d7-8987-7370a9a29790
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559610363 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 3.lc_ctrl_csr_mem_rw_with_rand_reset.2559610363
Directory /workspace/3.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.1325463432
Short name T188
Test name
Test status
Simulation time 101411627 ps
CPU time 0.8 seconds
Started Jun 13 01:33:35 PM PDT 24
Finished Jun 13 01:33:36 PM PDT 24
Peak memory 209816 kb
Host smart-7bba7135-6183-436b-9ec9-9f7b7fded7e5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325463432 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_rw.1325463432
Directory /workspace/3.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.3855627946
Short name T917
Test name
Test status
Simulation time 118982587 ps
CPU time 1.35 seconds
Started Jun 13 01:33:29 PM PDT 24
Finished Jun 13 01:33:30 PM PDT 24
Peak memory 209796 kb
Host smart-571419ea-a09a-4239-a4eb-125e43896d0a
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855627946 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.lc_ctrl_jtag_alert_test.3855627946
Directory /workspace/3.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.100413038
Short name T889
Test name
Test status
Simulation time 862926285 ps
CPU time 19.2 seconds
Started Jun 13 01:33:31 PM PDT 24
Finished Jun 13 01:33:51 PM PDT 24
Peak memory 209896 kb
Host smart-c95f1a7b-492b-4779-9396-dc6420d01ed7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100413038 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 3.lc_ctrl_jtag_csr_aliasing.100413038
Directory /workspace/3.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.3380975688
Short name T924
Test name
Test status
Simulation time 5376889583 ps
CPU time 6.3 seconds
Started Jun 13 01:33:31 PM PDT 24
Finished Jun 13 01:33:38 PM PDT 24
Peak memory 209900 kb
Host smart-25a9c2cc-c54d-4180-b1d4-598f1dbc62aa
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380975688 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_bit_bash.3380975688
Directory /workspace/3.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.1300679716
Short name T986
Test name
Test status
Simulation time 2450930784 ps
CPU time 3.03 seconds
Started Jun 13 01:33:31 PM PDT 24
Finished Jun 13 01:33:35 PM PDT 24
Peak memory 211464 kb
Host smart-7413be0f-ca5a-4a38-9417-031592884a55
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300679716 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_hw_reset.1300679716
Directory /workspace/3.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.593780230
Short name T884
Test name
Test status
Simulation time 89905449 ps
CPU time 2.15 seconds
Started Jun 13 01:33:31 PM PDT 24
Finished Jun 13 01:33:33 PM PDT 24
Peak memory 218224 kb
Host smart-5fd02e71-c137-4ef0-bd1a-efa40dab8510
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593780
230 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.593780230
Directory /workspace/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.2458922286
Short name T919
Test name
Test status
Simulation time 75733698 ps
CPU time 2.43 seconds
Started Jun 13 01:33:30 PM PDT 24
Finished Jun 13 01:33:33 PM PDT 24
Peak memory 217360 kb
Host smart-1e4d311d-9b80-4d02-875c-b59a3da2a6fa
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458922286 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.lc_ctrl_jtag_csr_rw.2458922286
Directory /workspace/3.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.317064492
Short name T191
Test name
Test status
Simulation time 37760442 ps
CPU time 1.78 seconds
Started Jun 13 01:33:30 PM PDT 24
Finished Jun 13 01:33:33 PM PDT 24
Peak memory 218172 kb
Host smart-bd95fa85-1e02-4fee-965f-ad2e09bb291a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317064492 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.lc_ctrl_jtag_same_csr_outstanding.317064492
Directory /workspace/3.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.662107845
Short name T193
Test name
Test status
Simulation time 41172848 ps
CPU time 1.84 seconds
Started Jun 13 01:33:37 PM PDT 24
Finished Jun 13 01:33:40 PM PDT 24
Peak memory 209996 kb
Host smart-6ab404a8-5b45-4361-a1ab-298021ddd89a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662107845 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
same_csr_outstanding.662107845
Directory /workspace/3.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.4259968334
Short name T908
Test name
Test status
Simulation time 178545301 ps
CPU time 2.7 seconds
Started Jun 13 01:33:29 PM PDT 24
Finished Jun 13 01:33:32 PM PDT 24
Peak memory 219844 kb
Host smart-fc96849c-321f-4db7-8a0d-be330ad5f430
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259968334 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_errors.4259968334
Directory /workspace/3.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.726232226
Short name T186
Test name
Test status
Simulation time 76302795 ps
CPU time 1.41 seconds
Started Jun 13 01:33:41 PM PDT 24
Finished Jun 13 01:33:43 PM PDT 24
Peak memory 209952 kb
Host smart-188ebfa1-6ed0-4e13-9b07-318505567317
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726232226 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_aliasing
.726232226
Directory /workspace/4.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.2273329512
Short name T957
Test name
Test status
Simulation time 24896319 ps
CPU time 1.44 seconds
Started Jun 13 01:33:43 PM PDT 24
Finished Jun 13 01:33:45 PM PDT 24
Peak memory 209864 kb
Host smart-2a0ed9d7-1c1d-4f11-826a-980bad503515
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273329512 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_bit_bas
h.2273329512
Directory /workspace/4.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.3585092306
Short name T990
Test name
Test status
Simulation time 82550640 ps
CPU time 1.07 seconds
Started Jun 13 01:33:46 PM PDT 24
Finished Jun 13 01:33:48 PM PDT 24
Peak memory 210932 kb
Host smart-82b4b821-b57a-474a-b774-f2dd8365758c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585092306 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_hw_rese
t.3585092306
Directory /workspace/4.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.4035286400
Short name T125
Test name
Test status
Simulation time 25711121 ps
CPU time 1.34 seconds
Started Jun 13 01:33:50 PM PDT 24
Finished Jun 13 01:33:52 PM PDT 24
Peak memory 218220 kb
Host smart-f12ed639-5319-4bb1-840a-a969ba8f6b53
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035286400 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 4.lc_ctrl_csr_mem_rw_with_rand_reset.4035286400
Directory /workspace/4.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.1707625635
Short name T189
Test name
Test status
Simulation time 20733324 ps
CPU time 0.81 seconds
Started Jun 13 01:33:41 PM PDT 24
Finished Jun 13 01:33:42 PM PDT 24
Peak memory 209812 kb
Host smart-4938ed84-6d55-4b14-8461-0f03ee730afe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707625635 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_rw.1707625635
Directory /workspace/4.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.997890018
Short name T905
Test name
Test status
Simulation time 72902070 ps
CPU time 1.34 seconds
Started Jun 13 01:33:46 PM PDT 24
Finished Jun 13 01:33:48 PM PDT 24
Peak memory 209872 kb
Host smart-3052940e-ef6d-47dc-9361-d4210f993322
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997890018 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 4.lc_ctrl_jtag_alert_test.997890018
Directory /workspace/4.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.1726134985
Short name T954
Test name
Test status
Simulation time 420675056 ps
CPU time 3.26 seconds
Started Jun 13 01:33:42 PM PDT 24
Finished Jun 13 01:33:46 PM PDT 24
Peak memory 209544 kb
Host smart-3c1a3eb5-53ae-43bb-8370-873c543c75f7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726134985 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_aliasing.1726134985
Directory /workspace/4.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.352243327
Short name T909
Test name
Test status
Simulation time 1773466526 ps
CPU time 11.4 seconds
Started Jun 13 01:33:47 PM PDT 24
Finished Jun 13 01:33:59 PM PDT 24
Peak memory 209876 kb
Host smart-3c9f0ebd-5b6a-4781-8814-badb3c0b9b5e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352243327 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 4.lc_ctrl_jtag_csr_bit_bash.352243327
Directory /workspace/4.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.3302162423
Short name T881
Test name
Test status
Simulation time 104441218 ps
CPU time 1.86 seconds
Started Jun 13 01:33:40 PM PDT 24
Finished Jun 13 01:33:42 PM PDT 24
Peak memory 209928 kb
Host smart-a6b2ca9c-91a1-4406-8661-e15a5a45a58c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302162423 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_hw_reset.3302162423
Directory /workspace/4.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1909041742
Short name T934
Test name
Test status
Simulation time 361419743 ps
CPU time 1.94 seconds
Started Jun 13 01:33:42 PM PDT 24
Finished Jun 13 01:33:45 PM PDT 24
Peak memory 218440 kb
Host smart-fcb83b53-da69-4701-ac19-d7857ecaf174
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190904
1742 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1909041742
Directory /workspace/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.650528987
Short name T133
Test name
Test status
Simulation time 3017195735 ps
CPU time 2.38 seconds
Started Jun 13 01:33:46 PM PDT 24
Finished Jun 13 01:33:50 PM PDT 24
Peak memory 217448 kb
Host smart-9ce81436-7817-4650-8c0f-ab764b452478
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650528987 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.lc_ctrl_jtag_csr_rw.650528987
Directory /workspace/4.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.1726265079
Short name T903
Test name
Test status
Simulation time 125097608 ps
CPU time 1.46 seconds
Started Jun 13 01:33:40 PM PDT 24
Finished Jun 13 01:33:42 PM PDT 24
Peak memory 210000 kb
Host smart-a8a0743e-db83-4a46-8f57-382d93b7492a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726265079 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.lc_ctrl_jtag_same_csr_outstanding.1726265079
Directory /workspace/4.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.2141149641
Short name T910
Test name
Test status
Simulation time 135778860 ps
CPU time 1.69 seconds
Started Jun 13 01:33:48 PM PDT 24
Finished Jun 13 01:33:51 PM PDT 24
Peak memory 209952 kb
Host smart-21bb088e-6de8-467a-a0e4-a22d85a2f78e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141149641 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl
_same_csr_outstanding.2141149641
Directory /workspace/4.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.1149798396
Short name T110
Test name
Test status
Simulation time 199055533 ps
CPU time 3.12 seconds
Started Jun 13 01:33:46 PM PDT 24
Finished Jun 13 01:33:50 PM PDT 24
Peak memory 219212 kb
Host smart-59e465ae-e722-43b2-a40d-a6ff98f35ebc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149798396 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_errors.1149798396
Directory /workspace/4.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.3425851654
Short name T893
Test name
Test status
Simulation time 35112349 ps
CPU time 1.73 seconds
Started Jun 13 01:33:56 PM PDT 24
Finished Jun 13 01:33:59 PM PDT 24
Peak memory 219104 kb
Host smart-de0c8b6a-d71f-47af-bfda-3221d6cdf95d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425851654 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 5.lc_ctrl_csr_mem_rw_with_rand_reset.3425851654
Directory /workspace/5.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.2871895573
Short name T107
Test name
Test status
Simulation time 17390264 ps
CPU time 0.91 seconds
Started Jun 13 01:33:55 PM PDT 24
Finished Jun 13 01:33:57 PM PDT 24
Peak memory 209884 kb
Host smart-53a24434-4b7b-4ea2-9045-c306dabe8423
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871895573 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_csr_rw.2871895573
Directory /workspace/5.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.814943948
Short name T949
Test name
Test status
Simulation time 886928657 ps
CPU time 1.17 seconds
Started Jun 13 01:33:56 PM PDT 24
Finished Jun 13 01:33:58 PM PDT 24
Peak memory 209052 kb
Host smart-2f6f46ec-6180-46e4-908e-369223f015f3
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814943948 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 5.lc_ctrl_jtag_alert_test.814943948
Directory /workspace/5.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.1726668180
Short name T895
Test name
Test status
Simulation time 946251346 ps
CPU time 20.58 seconds
Started Jun 13 01:33:55 PM PDT 24
Finished Jun 13 01:34:16 PM PDT 24
Peak memory 217296 kb
Host smart-e9b8deac-71d4-4ff3-bac5-009e7cd630dc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726668180 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_aliasing.1726668180
Directory /workspace/5.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.3808228398
Short name T874
Test name
Test status
Simulation time 1928499988 ps
CPU time 6.72 seconds
Started Jun 13 01:33:50 PM PDT 24
Finished Jun 13 01:33:57 PM PDT 24
Peak memory 209836 kb
Host smart-43444f8b-b5fb-47ef-8a45-c4ec4de9dd55
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808228398 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_bit_bash.3808228398
Directory /workspace/5.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.4155514103
Short name T875
Test name
Test status
Simulation time 175601255 ps
CPU time 1.34 seconds
Started Jun 13 01:33:48 PM PDT 24
Finished Jun 13 01:33:51 PM PDT 24
Peak memory 211232 kb
Host smart-515400e8-e9e8-4de4-b017-ebed0d12e3a3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155514103 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_hw_reset.4155514103
Directory /workspace/5.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4007578178
Short name T925
Test name
Test status
Simulation time 103830782 ps
CPU time 3.44 seconds
Started Jun 13 01:33:55 PM PDT 24
Finished Jun 13 01:33:59 PM PDT 24
Peak memory 218260 kb
Host smart-abab8534-e824-42e4-8d9d-46b4b8e1879d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400757
8178 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4007578178
Directory /workspace/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.850114034
Short name T977
Test name
Test status
Simulation time 308525918 ps
CPU time 1.39 seconds
Started Jun 13 01:33:48 PM PDT 24
Finished Jun 13 01:33:50 PM PDT 24
Peak memory 217312 kb
Host smart-54e14469-3952-4b12-aca5-b773624366df
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850114034 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.lc_ctrl_jtag_csr_rw.850114034
Directory /workspace/5.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.4107940624
Short name T967
Test name
Test status
Simulation time 242473064 ps
CPU time 1.08 seconds
Started Jun 13 01:33:56 PM PDT 24
Finished Jun 13 01:33:57 PM PDT 24
Peak memory 209944 kb
Host smart-4dfad564-ae92-47fb-9043-7c3156000b00
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107940624 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.lc_ctrl_jtag_same_csr_outstanding.4107940624
Directory /workspace/5.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.2903645313
Short name T955
Test name
Test status
Simulation time 49178948 ps
CPU time 1.88 seconds
Started Jun 13 01:33:57 PM PDT 24
Finished Jun 13 01:34:00 PM PDT 24
Peak memory 209960 kb
Host smart-25aad413-43a5-4771-b834-aa6fbc604a1e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903645313 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl
_same_csr_outstanding.2903645313
Directory /workspace/5.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.3734842954
Short name T113
Test name
Test status
Simulation time 117794522 ps
CPU time 3.11 seconds
Started Jun 13 01:33:53 PM PDT 24
Finished Jun 13 01:33:57 PM PDT 24
Peak memory 218184 kb
Host smart-0b382fea-5292-49be-ba0f-03db294bde5f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734842954 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_errors.3734842954
Directory /workspace/5.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.3738332153
Short name T127
Test name
Test status
Simulation time 60051808 ps
CPU time 2.17 seconds
Started Jun 13 01:33:56 PM PDT 24
Finished Jun 13 01:33:59 PM PDT 24
Peak memory 221832 kb
Host smart-5c97db90-fd15-4cf2-9b24-a0397d61f5cb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738332153 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_intg_
err.3738332153
Directory /workspace/5.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.3702450388
Short name T991
Test name
Test status
Simulation time 164204168 ps
CPU time 1.28 seconds
Started Jun 13 01:34:04 PM PDT 24
Finished Jun 13 01:34:05 PM PDT 24
Peak memory 218240 kb
Host smart-0f8602cd-d198-4690-91e5-886f60873e8c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702450388 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 6.lc_ctrl_csr_mem_rw_with_rand_reset.3702450388
Directory /workspace/6.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.1445906356
Short name T974
Test name
Test status
Simulation time 16089370 ps
CPU time 0.84 seconds
Started Jun 13 01:34:03 PM PDT 24
Finished Jun 13 01:34:04 PM PDT 24
Peak memory 209940 kb
Host smart-98143f28-25fa-449b-93ff-eb73027a875b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445906356 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_csr_rw.1445906356
Directory /workspace/6.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.3724764623
Short name T928
Test name
Test status
Simulation time 35531715 ps
CPU time 1.45 seconds
Started Jun 13 01:34:02 PM PDT 24
Finished Jun 13 01:34:04 PM PDT 24
Peak memory 209836 kb
Host smart-e5c9e0a0-dd66-4a4c-8f2f-f7a3b2a5d55c
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724764623 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.lc_ctrl_jtag_alert_test.3724764623
Directory /workspace/6.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.693592878
Short name T914
Test name
Test status
Simulation time 1961113410 ps
CPU time 10.87 seconds
Started Jun 13 01:34:02 PM PDT 24
Finished Jun 13 01:34:14 PM PDT 24
Peak memory 209552 kb
Host smart-1e21e5e3-1a1c-49e3-83a7-fd6313e4b388
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693592878 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 6.lc_ctrl_jtag_csr_aliasing.693592878
Directory /workspace/6.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.854000769
Short name T939
Test name
Test status
Simulation time 4463706778 ps
CPU time 5.63 seconds
Started Jun 13 01:34:00 PM PDT 24
Finished Jun 13 01:34:06 PM PDT 24
Peak memory 217944 kb
Host smart-43625475-f116-4d8a-8c87-1a0612ca21dc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854000769 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 6.lc_ctrl_jtag_csr_bit_bash.854000769
Directory /workspace/6.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.646966516
Short name T892
Test name
Test status
Simulation time 905051795 ps
CPU time 3.64 seconds
Started Jun 13 01:34:03 PM PDT 24
Finished Jun 13 01:34:07 PM PDT 24
Peak memory 218116 kb
Host smart-87a0787f-f5ef-49c9-bea2-b1e823f885bd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646966516 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 6.lc_ctrl_jtag_csr_hw_reset.646966516
Directory /workspace/6.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2880002346
Short name T904
Test name
Test status
Simulation time 279433167 ps
CPU time 5.75 seconds
Started Jun 13 01:34:00 PM PDT 24
Finished Jun 13 01:34:06 PM PDT 24
Peak memory 219728 kb
Host smart-67dcee4c-a840-4d36-abdc-fbabab139fda
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288000
2346 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2880002346
Directory /workspace/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.1675858523
Short name T970
Test name
Test status
Simulation time 66734150 ps
CPU time 1.86 seconds
Started Jun 13 01:34:02 PM PDT 24
Finished Jun 13 01:34:05 PM PDT 24
Peak memory 209860 kb
Host smart-8ea0e049-9f98-4c2b-80ad-21d49c63c3c0
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675858523 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.lc_ctrl_jtag_csr_rw.1675858523
Directory /workspace/6.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.40076187
Short name T992
Test name
Test status
Simulation time 45449983 ps
CPU time 1.58 seconds
Started Jun 13 01:34:01 PM PDT 24
Finished Jun 13 01:34:03 PM PDT 24
Peak memory 212072 kb
Host smart-308fa51f-175a-48ff-81ed-8fb8c7cac1db
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40076187 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 6.lc_ctrl_jtag_same_csr_outstanding.40076187
Directory /workspace/6.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.2498478412
Short name T938
Test name
Test status
Simulation time 196728925 ps
CPU time 1.5 seconds
Started Jun 13 01:34:00 PM PDT 24
Finished Jun 13 01:34:02 PM PDT 24
Peak memory 211828 kb
Host smart-2f1d36a5-ed5d-4b74-a28f-0149594b1a95
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498478412 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl
_same_csr_outstanding.2498478412
Directory /workspace/6.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.338977500
Short name T902
Test name
Test status
Simulation time 142961488 ps
CPU time 5.21 seconds
Started Jun 13 01:34:01 PM PDT 24
Finished Jun 13 01:34:07 PM PDT 24
Peak memory 218076 kb
Host smart-8852aadd-4433-48d1-a72d-26992d8f6158
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338977500 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_errors.338977500
Directory /workspace/6.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.1130077566
Short name T105
Test name
Test status
Simulation time 112344310 ps
CPU time 2.07 seconds
Started Jun 13 01:34:01 PM PDT 24
Finished Jun 13 01:34:04 PM PDT 24
Peak memory 222400 kb
Host smart-2330f866-ad22-4eee-8b1a-08501b13de58
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130077566 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_intg_
err.1130077566
Directory /workspace/6.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.419825214
Short name T119
Test name
Test status
Simulation time 27181261 ps
CPU time 1.6 seconds
Started Jun 13 01:34:08 PM PDT 24
Finished Jun 13 01:34:11 PM PDT 24
Peak memory 219068 kb
Host smart-6c36dcbe-b87f-4dbb-aebe-6515b71ee74a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419825214 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 7.lc_ctrl_csr_mem_rw_with_rand_reset.419825214
Directory /workspace/7.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.687493316
Short name T872
Test name
Test status
Simulation time 15137706 ps
CPU time 1.03 seconds
Started Jun 13 01:34:08 PM PDT 24
Finished Jun 13 01:34:11 PM PDT 24
Peak memory 209564 kb
Host smart-ef923812-8e9d-47c6-8eeb-df70ac3ed8e8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687493316 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_csr_rw.687493316
Directory /workspace/7.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.2650793139
Short name T896
Test name
Test status
Simulation time 102809940 ps
CPU time 1.22 seconds
Started Jun 13 01:34:07 PM PDT 24
Finished Jun 13 01:34:10 PM PDT 24
Peak memory 209748 kb
Host smart-c19c63b1-ddfb-4b7a-ae6b-1ebdc9ada11e
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650793139 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.lc_ctrl_jtag_alert_test.2650793139
Directory /workspace/7.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.2794937398
Short name T971
Test name
Test status
Simulation time 1690425005 ps
CPU time 4.86 seconds
Started Jun 13 01:34:02 PM PDT 24
Finished Jun 13 01:34:07 PM PDT 24
Peak memory 209804 kb
Host smart-1034f2b5-daea-451f-8f9b-cef2849a9e46
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794937398 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_aliasing.2794937398
Directory /workspace/7.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.734863230
Short name T901
Test name
Test status
Simulation time 969270156 ps
CPU time 9.52 seconds
Started Jun 13 01:34:02 PM PDT 24
Finished Jun 13 01:34:13 PM PDT 24
Peak memory 209552 kb
Host smart-2fd6815e-38de-4746-9650-e2bff5a447fd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734863230 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 7.lc_ctrl_jtag_csr_bit_bash.734863230
Directory /workspace/7.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.3567681317
Short name T930
Test name
Test status
Simulation time 45746061 ps
CPU time 1.89 seconds
Started Jun 13 01:34:01 PM PDT 24
Finished Jun 13 01:34:04 PM PDT 24
Peak memory 210976 kb
Host smart-bfb37177-7f0b-400b-9b45-80cc8be8415f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567681317 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_hw_reset.3567681317
Directory /workspace/7.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3500087416
Short name T171
Test name
Test status
Simulation time 49410671 ps
CPU time 1.53 seconds
Started Jun 13 01:34:01 PM PDT 24
Finished Jun 13 01:34:04 PM PDT 24
Peak memory 219256 kb
Host smart-0555108a-9a62-4504-8379-312e8ceab84a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350008
7416 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3500087416
Directory /workspace/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.211611496
Short name T920
Test name
Test status
Simulation time 1703731545 ps
CPU time 1.67 seconds
Started Jun 13 01:34:05 PM PDT 24
Finished Jun 13 01:34:08 PM PDT 24
Peak memory 209868 kb
Host smart-ea732a8a-bbfb-44c9-8991-33f72bdbbd82
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211611496 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.lc_ctrl_jtag_csr_rw.211611496
Directory /workspace/7.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.260716309
Short name T894
Test name
Test status
Simulation time 17402369 ps
CPU time 1.21 seconds
Started Jun 13 01:34:04 PM PDT 24
Finished Jun 13 01:34:06 PM PDT 24
Peak memory 209936 kb
Host smart-c2e58e84-4350-4967-aae7-347c643409b6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260716309 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.lc_ctrl_jtag_same_csr_outstanding.260716309
Directory /workspace/7.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.4208043005
Short name T192
Test name
Test status
Simulation time 26444346 ps
CPU time 1.12 seconds
Started Jun 13 01:34:06 PM PDT 24
Finished Jun 13 01:34:08 PM PDT 24
Peak memory 209960 kb
Host smart-1200143d-3aa6-4dd3-b363-6aad86b52344
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208043005 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl
_same_csr_outstanding.4208043005
Directory /workspace/7.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.1500883668
Short name T989
Test name
Test status
Simulation time 79288603 ps
CPU time 2.41 seconds
Started Jun 13 01:34:08 PM PDT 24
Finished Jun 13 01:34:11 PM PDT 24
Peak memory 218216 kb
Host smart-05f6103c-009f-493a-b5c8-07a2c35d01d3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500883668 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_errors.1500883668
Directory /workspace/7.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.9094508
Short name T962
Test name
Test status
Simulation time 14366755 ps
CPU time 1.01 seconds
Started Jun 13 01:34:17 PM PDT 24
Finished Jun 13 01:34:19 PM PDT 24
Peak memory 220384 kb
Host smart-4d24cf42-ceca-43a4-8e8c-3a67d0d591c8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9094508 -assert nopostproc +UVM_TESTNAME=lc
_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 8.lc_ctrl_csr_mem_rw_with_rand_reset.9094508
Directory /workspace/8.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.3165594594
Short name T182
Test name
Test status
Simulation time 16030752 ps
CPU time 0.86 seconds
Started Jun 13 01:34:14 PM PDT 24
Finished Jun 13 01:34:16 PM PDT 24
Peak memory 209952 kb
Host smart-257cfe0a-b624-4b1b-8a54-d15f3d765320
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165594594 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_csr_rw.3165594594
Directory /workspace/8.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.4273416051
Short name T873
Test name
Test status
Simulation time 72349867 ps
CPU time 1.39 seconds
Started Jun 13 01:34:15 PM PDT 24
Finished Jun 13 01:34:17 PM PDT 24
Peak memory 209836 kb
Host smart-38f1a507-3e06-41f0-963b-d8e7f0a76972
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273416051 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.lc_ctrl_jtag_alert_test.4273416051
Directory /workspace/8.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.3480184693
Short name T944
Test name
Test status
Simulation time 707426971 ps
CPU time 5.92 seconds
Started Jun 13 01:34:07 PM PDT 24
Finished Jun 13 01:34:14 PM PDT 24
Peak memory 209504 kb
Host smart-6a100e0c-59b2-431a-82f7-bcbb3e3620ef
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480184693 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_aliasing.3480184693
Directory /workspace/8.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.309767345
Short name T918
Test name
Test status
Simulation time 4875842125 ps
CPU time 10.52 seconds
Started Jun 13 01:34:09 PM PDT 24
Finished Jun 13 01:34:20 PM PDT 24
Peak memory 209912 kb
Host smart-344af3f4-335f-43f6-8df3-e2e6e9cdaef5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309767345 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 8.lc_ctrl_jtag_csr_bit_bash.309767345
Directory /workspace/8.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.292901470
Short name T134
Test name
Test status
Simulation time 526578877 ps
CPU time 1.86 seconds
Started Jun 13 01:34:06 PM PDT 24
Finished Jun 13 01:34:08 PM PDT 24
Peak memory 211472 kb
Host smart-80ed8174-57af-458c-84bc-2420ee18f959
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292901470 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 8.lc_ctrl_jtag_csr_hw_reset.292901470
Directory /workspace/8.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.148572767
Short name T969
Test name
Test status
Simulation time 218044323 ps
CPU time 2.41 seconds
Started Jun 13 01:34:15 PM PDT 24
Finished Jun 13 01:34:18 PM PDT 24
Peak memory 219636 kb
Host smart-62de3a43-8d5f-4695-9107-f038c4a7e00d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148572
767 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.148572767
Directory /workspace/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.3550735768
Short name T916
Test name
Test status
Simulation time 121814629 ps
CPU time 1.12 seconds
Started Jun 13 01:34:07 PM PDT 24
Finished Jun 13 01:34:09 PM PDT 24
Peak memory 217380 kb
Host smart-089f74ca-0fb7-48a6-8743-8738c20c3f3c
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550735768 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.lc_ctrl_jtag_csr_rw.3550735768
Directory /workspace/8.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.2167125089
Short name T195
Test name
Test status
Simulation time 161861453 ps
CPU time 1.35 seconds
Started Jun 13 01:34:06 PM PDT 24
Finished Jun 13 01:34:08 PM PDT 24
Peak memory 210012 kb
Host smart-ed155311-7329-4c99-b842-3d794554eeb8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167125089 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.lc_ctrl_jtag_same_csr_outstanding.2167125089
Directory /workspace/8.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.3856242530
Short name T891
Test name
Test status
Simulation time 18898539 ps
CPU time 1.29 seconds
Started Jun 13 01:34:13 PM PDT 24
Finished Jun 13 01:34:15 PM PDT 24
Peak memory 209968 kb
Host smart-2e6e7451-375b-442e-b4e6-ba4486168eb8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856242530 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl
_same_csr_outstanding.3856242530
Directory /workspace/8.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.66545908
Short name T956
Test name
Test status
Simulation time 36138835 ps
CPU time 2.89 seconds
Started Jun 13 01:34:12 PM PDT 24
Finished Jun 13 01:34:16 PM PDT 24
Peak memory 218500 kb
Host smart-d639f909-d109-497f-8b46-2440a1599fe0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66545908 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_errors.66545908
Directory /workspace/8.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.3616466295
Short name T98
Test name
Test status
Simulation time 123060340 ps
CPU time 1.9 seconds
Started Jun 13 01:34:13 PM PDT 24
Finished Jun 13 01:34:16 PM PDT 24
Peak memory 222604 kb
Host smart-c648e098-9c6c-44f8-934f-4879238c3503
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616466295 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_intg_
err.3616466295
Directory /workspace/8.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.797400818
Short name T886
Test name
Test status
Simulation time 50924900 ps
CPU time 1.3 seconds
Started Jun 13 01:34:20 PM PDT 24
Finished Jun 13 01:34:22 PM PDT 24
Peak memory 218228 kb
Host smart-ce0245a3-f0f3-4b4e-a349-441245a93c07
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797400818 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 9.lc_ctrl_csr_mem_rw_with_rand_reset.797400818
Directory /workspace/9.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.414210202
Short name T960
Test name
Test status
Simulation time 34347118 ps
CPU time 0.81 seconds
Started Jun 13 01:34:22 PM PDT 24
Finished Jun 13 01:34:23 PM PDT 24
Peak memory 209836 kb
Host smart-a56a45fa-c3f4-44eb-92ba-c4753f37f08a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414210202 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_csr_rw.414210202
Directory /workspace/9.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.1843287218
Short name T981
Test name
Test status
Simulation time 353707378 ps
CPU time 1.67 seconds
Started Jun 13 01:34:20 PM PDT 24
Finished Jun 13 01:34:22 PM PDT 24
Peak memory 209836 kb
Host smart-f61ca0fc-c594-42a4-be51-632993ff8f2c
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843287218 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.lc_ctrl_jtag_alert_test.1843287218
Directory /workspace/9.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.974180815
Short name T958
Test name
Test status
Simulation time 2759679995 ps
CPU time 8.8 seconds
Started Jun 13 01:34:15 PM PDT 24
Finished Jun 13 01:34:24 PM PDT 24
Peak memory 217332 kb
Host smart-d9cc8ad8-b5cc-444f-9e5e-4253d799d735
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974180815 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 9.lc_ctrl_jtag_csr_aliasing.974180815
Directory /workspace/9.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.3763919460
Short name T136
Test name
Test status
Simulation time 2476835020 ps
CPU time 11.74 seconds
Started Jun 13 01:34:16 PM PDT 24
Finished Jun 13 01:34:29 PM PDT 24
Peak memory 209924 kb
Host smart-1264cfc0-9c51-41da-a3d8-b3d3cbcea8f6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763919460 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_bit_bash.3763919460
Directory /workspace/9.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.1590273671
Short name T900
Test name
Test status
Simulation time 190405105 ps
CPU time 5.23 seconds
Started Jun 13 01:34:14 PM PDT 24
Finished Jun 13 01:34:20 PM PDT 24
Peak memory 211608 kb
Host smart-92feb693-940a-43a7-ad95-7af3904dfa47
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590273671 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_hw_reset.1590273671
Directory /workspace/9.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3927846109
Short name T946
Test name
Test status
Simulation time 726674131 ps
CPU time 2.06 seconds
Started Jun 13 01:34:19 PM PDT 24
Finished Jun 13 01:34:22 PM PDT 24
Peak memory 219352 kb
Host smart-57d20661-2921-4425-bbf4-4c31d95c151e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392784
6109 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3927846109
Directory /workspace/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.3224684250
Short name T972
Test name
Test status
Simulation time 371132587 ps
CPU time 1.64 seconds
Started Jun 13 01:34:14 PM PDT 24
Finished Jun 13 01:34:16 PM PDT 24
Peak memory 217340 kb
Host smart-1c3d4bf9-2709-4bd8-98a8-da3c7eb44925
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224684250 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.lc_ctrl_jtag_csr_rw.3224684250
Directory /workspace/9.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.908534692
Short name T931
Test name
Test status
Simulation time 15036933 ps
CPU time 0.99 seconds
Started Jun 13 01:34:21 PM PDT 24
Finished Jun 13 01:34:23 PM PDT 24
Peak memory 209976 kb
Host smart-446e4bd6-e456-4701-b1ee-578474f3c1a2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908534692 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.lc_ctrl_jtag_same_csr_outstanding.908534692
Directory /workspace/9.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.1761055384
Short name T953
Test name
Test status
Simulation time 125448640 ps
CPU time 1.21 seconds
Started Jun 13 01:34:19 PM PDT 24
Finished Jun 13 01:34:20 PM PDT 24
Peak memory 210020 kb
Host smart-6001f6fc-6c71-45f3-8c3d-38879710a789
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761055384 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl
_same_csr_outstanding.1761055384
Directory /workspace/9.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.339852850
Short name T109
Test name
Test status
Simulation time 374317402 ps
CPU time 2.63 seconds
Started Jun 13 01:34:18 PM PDT 24
Finished Jun 13 01:34:21 PM PDT 24
Peak memory 218240 kb
Host smart-141318ec-6d64-4760-b334-7d0925738080
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339852850 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_errors.339852850
Directory /workspace/9.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_alert_test.1618666850
Short name T330
Test name
Test status
Simulation time 17911567 ps
CPU time 1.11 seconds
Started Jun 13 01:41:26 PM PDT 24
Finished Jun 13 01:41:28 PM PDT 24
Peak memory 209028 kb
Host smart-40c12d7f-f50f-4fc7-9837-0d353f75e5df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618666850 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_alert_test.1618666850
Directory /workspace/0.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.lc_ctrl_errors.3119723929
Short name T671
Test name
Test status
Simulation time 318495596 ps
CPU time 9.81 seconds
Started Jun 13 01:41:15 PM PDT 24
Finished Jun 13 01:41:28 PM PDT 24
Peak memory 218220 kb
Host smart-cf1b7299-19de-4fa9-bc56-b8f69c439945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119723929 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_errors.3119723929
Directory /workspace/0.lc_ctrl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_access.2694646256
Short name T791
Test name
Test status
Simulation time 1700499798 ps
CPU time 6.29 seconds
Started Jun 13 01:41:20 PM PDT 24
Finished Jun 13 01:41:28 PM PDT 24
Peak memory 217312 kb
Host smart-8304c730-518d-40de-9e1c-e96ab7ad0619
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694646256 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_access.2694646256
Directory /workspace/0.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_errors.3920299072
Short name T831
Test name
Test status
Simulation time 5134123859 ps
CPU time 27 seconds
Started Jun 13 01:41:20 PM PDT 24
Finished Jun 13 01:41:49 PM PDT 24
Peak memory 226060 kb
Host smart-51359c1d-f3f7-419c-b9e7-3daf1855b585
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920299072 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_er
rors.3920299072
Directory /workspace/0.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_priority.428393369
Short name T209
Test name
Test status
Simulation time 15921454358 ps
CPU time 18.01 seconds
Started Jun 13 01:41:27 PM PDT 24
Finished Jun 13 01:41:46 PM PDT 24
Peak memory 217860 kb
Host smart-17f207b7-633d-41fa-890a-adbb8846679f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428393369 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_priority.428393369
Directory /workspace/0.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_prog_failure.738094205
Short name T582
Test name
Test status
Simulation time 7476190210 ps
CPU time 8.99 seconds
Started Jun 13 01:41:21 PM PDT 24
Finished Jun 13 01:41:32 PM PDT 24
Peak memory 218260 kb
Host smart-87cd64cd-b4e3-4013-a2fe-f263c50b5985
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738094205 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_
prog_failure.738094205
Directory /workspace/0.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_regwen_during_op.2966999183
Short name T444
Test name
Test status
Simulation time 2015261268 ps
CPU time 12.28 seconds
Started Jun 13 01:41:30 PM PDT 24
Finished Jun 13 01:41:43 PM PDT 24
Peak memory 217712 kb
Host smart-bdbe2944-e524-43a2-9dde-1c0430b352a9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966999183 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_regwen_during_op.2966999183
Directory /workspace/0.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_smoke.2202306707
Short name T416
Test name
Test status
Simulation time 1793198563 ps
CPU time 12.48 seconds
Started Jun 13 01:41:21 PM PDT 24
Finished Jun 13 01:41:35 PM PDT 24
Peak memory 217692 kb
Host smart-154cd9a0-f41d-4151-9707-d1ca0ac5b3c3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202306707 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_smoke.
2202306707
Directory /workspace/0.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_failure.3936679128
Short name T748
Test name
Test status
Simulation time 2532230295 ps
CPU time 69.05 seconds
Started Jun 13 01:41:21 PM PDT 24
Finished Jun 13 01:42:32 PM PDT 24
Peak memory 283520 kb
Host smart-e5caefa0-27a7-494b-a93b-fc1c74f81caf
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936679128 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jta
g_state_failure.3936679128
Directory /workspace/0.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_post_trans.1854980215
Short name T17
Test name
Test status
Simulation time 1993073430 ps
CPU time 10 seconds
Started Jun 13 01:41:19 PM PDT 24
Finished Jun 13 01:41:31 PM PDT 24
Peak memory 224708 kb
Host smart-521942c6-f3d8-4fb5-b749-f62b7d614219
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854980215 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_state_post_trans.1854980215
Directory /workspace/0.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_prog_failure.2734017483
Short name T237
Test name
Test status
Simulation time 577595459 ps
CPU time 4.43 seconds
Started Jun 13 01:41:15 PM PDT 24
Finished Jun 13 01:41:22 PM PDT 24
Peak memory 218204 kb
Host smart-bbc4eb14-9a4a-4b6e-a9ed-3c4858045043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734017483 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_prog_failure.2734017483
Directory /workspace/0.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_regwen_during_op.3380592919
Short name T571
Test name
Test status
Simulation time 277546484 ps
CPU time 7.69 seconds
Started Jun 13 01:41:22 PM PDT 24
Finished Jun 13 01:41:31 PM PDT 24
Peak memory 217748 kb
Host smart-e8329c31-4cf8-4924-ae99-098104683849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380592919 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_regwen_during_op.3380592919
Directory /workspace/0.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_mubi.2435238123
Short name T558
Test name
Test status
Simulation time 848471003 ps
CPU time 16.65 seconds
Started Jun 13 01:41:26 PM PDT 24
Finished Jun 13 01:41:44 PM PDT 24
Peak memory 218916 kb
Host smart-60fed1e9-fda3-423e-9196-6e9a5f79ab37
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435238123 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_mubi.2435238123
Directory /workspace/0.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_digest.3894865784
Short name T449
Test name
Test status
Simulation time 380416801 ps
CPU time 16.58 seconds
Started Jun 13 01:41:28 PM PDT 24
Finished Jun 13 01:41:45 PM PDT 24
Peak memory 218260 kb
Host smart-cb073cac-5c34-47ff-afd6-6c5bf3f0df82
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894865784 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_di
gest.3894865784
Directory /workspace/0.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_mux.2164240381
Short name T574
Test name
Test status
Simulation time 2396351815 ps
CPU time 11.42 seconds
Started Jun 13 01:41:29 PM PDT 24
Finished Jun 13 01:41:42 PM PDT 24
Peak memory 218312 kb
Host smart-c57b41de-b149-42e2-a2df-3bff5bb74c0e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164240381 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_mux.2
164240381
Directory /workspace/0.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/0.lc_ctrl_smoke.2694200264
Short name T869
Test name
Test status
Simulation time 490019001 ps
CPU time 8.21 seconds
Started Jun 13 01:41:16 PM PDT 24
Finished Jun 13 01:41:27 PM PDT 24
Peak memory 217768 kb
Host smart-62313592-71b3-4f23-850a-4f2caf6e0abe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694200264 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_smoke.2694200264
Directory /workspace/0.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_failure.3914193554
Short name T211
Test name
Test status
Simulation time 621304516 ps
CPU time 19.89 seconds
Started Jun 13 01:41:15 PM PDT 24
Finished Jun 13 01:41:38 PM PDT 24
Peak memory 250908 kb
Host smart-f68c5eab-44f9-44a3-914d-300e5ced1af3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914193554 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_failure.3914193554
Directory /workspace/0.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_post_trans.1646603057
Short name T833
Test name
Test status
Simulation time 149867665 ps
CPU time 2.96 seconds
Started Jun 13 01:41:17 PM PDT 24
Finished Jun 13 01:41:22 PM PDT 24
Peak memory 222472 kb
Host smart-5df39a2e-f7d8-49d8-a474-3a81e5236a98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646603057 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_post_trans.1646603057
Directory /workspace/0.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all.353643591
Short name T783
Test name
Test status
Simulation time 6340675838 ps
CPU time 160.83 seconds
Started Jun 13 01:41:27 PM PDT 24
Finished Jun 13 01:44:09 PM PDT 24
Peak memory 273112 kb
Host smart-69c6a8dd-9e9c-4706-8b00-25aba32af9c8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353643591 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.lc_ctrl_stress_all.353643591
Directory /workspace/0.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.lc_ctrl_volatile_unlock_smoke.1408125197
Short name T685
Test name
Test status
Simulation time 35632188 ps
CPU time 0.8 seconds
Started Jun 13 01:41:15 PM PDT 24
Finished Jun 13 01:41:19 PM PDT 24
Peak memory 208784 kb
Host smart-a480ffd8-d14d-48de-a8c8-b5dc360304a9
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408125197 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ct
rl_volatile_unlock_smoke.1408125197
Directory /workspace/0.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_alert_test.3398305019
Short name T612
Test name
Test status
Simulation time 13092779 ps
CPU time 0.87 seconds
Started Jun 13 01:41:43 PM PDT 24
Finished Jun 13 01:41:44 PM PDT 24
Peak memory 208820 kb
Host smart-027e4629-2477-460f-92e9-d4badb0891d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398305019 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_alert_test.3398305019
Directory /workspace/1.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.lc_ctrl_claim_transition_if.3016802610
Short name T265
Test name
Test status
Simulation time 41376935 ps
CPU time 0.95 seconds
Started Jun 13 01:41:33 PM PDT 24
Finished Jun 13 01:41:36 PM PDT 24
Peak memory 208924 kb
Host smart-9372cb34-8f06-4234-ab10-727efad92b63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3016802610 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_claim_transition_if.3016802610
Directory /workspace/1.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_access.3356437287
Short name T638
Test name
Test status
Simulation time 386004344 ps
CPU time 4.75 seconds
Started Jun 13 01:41:34 PM PDT 24
Finished Jun 13 01:41:40 PM PDT 24
Peak memory 217096 kb
Host smart-22050f80-392a-449d-9e3b-a00f17da738b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356437287 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_access.3356437287
Directory /workspace/1.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_errors.3259387629
Short name T493
Test name
Test status
Simulation time 1070444702 ps
CPU time 31.5 seconds
Started Jun 13 01:41:33 PM PDT 24
Finished Jun 13 01:42:05 PM PDT 24
Peak memory 218220 kb
Host smart-f86a7d3b-0255-471e-888d-f75a340f8eeb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259387629 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_er
rors.3259387629
Directory /workspace/1.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_priority.3143297984
Short name T596
Test name
Test status
Simulation time 2909059342 ps
CPU time 34.12 seconds
Started Jun 13 01:41:46 PM PDT 24
Finished Jun 13 01:42:22 PM PDT 24
Peak memory 217696 kb
Host smart-8d131aa6-5f92-4c10-b225-0dd39fa6cd2f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143297984 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_priority.3
143297984
Directory /workspace/1.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_prog_failure.3837269124
Short name T390
Test name
Test status
Simulation time 1453606552 ps
CPU time 7.11 seconds
Started Jun 13 01:41:33 PM PDT 24
Finished Jun 13 01:41:42 PM PDT 24
Peak memory 218188 kb
Host smart-4ef0926f-e473-4d0b-aac3-6dc3dd82435f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837269124 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag
_prog_failure.3837269124
Directory /workspace/1.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_regwen_during_op.3375891299
Short name T451
Test name
Test status
Simulation time 3993800847 ps
CPU time 9.81 seconds
Started Jun 13 01:41:42 PM PDT 24
Finished Jun 13 01:41:53 PM PDT 24
Peak memory 217732 kb
Host smart-99d673f3-51ad-4712-8813-2487e5f9c27c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375891299 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_regwen_during_op.3375891299
Directory /workspace/1.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_smoke.3944636681
Short name T326
Test name
Test status
Simulation time 4482308477 ps
CPU time 5.21 seconds
Started Jun 13 01:41:34 PM PDT 24
Finished Jun 13 01:41:40 PM PDT 24
Peak memory 217792 kb
Host smart-a6f03b6c-4376-42c7-a56e-f1a11178d8ee
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944636681 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_smoke.
3944636681
Directory /workspace/1.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_failure.699477730
Short name T350
Test name
Test status
Simulation time 8247941079 ps
CPU time 73.5 seconds
Started Jun 13 01:41:34 PM PDT 24
Finished Jun 13 01:42:49 PM PDT 24
Peak memory 283644 kb
Host smart-c8d77af0-415f-4dff-ab18-dbe5efbc10b6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699477730 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag
_state_failure.699477730
Directory /workspace/1.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_post_trans.2954515498
Short name T254
Test name
Test status
Simulation time 693983034 ps
CPU time 21.42 seconds
Started Jun 13 01:41:34 PM PDT 24
Finished Jun 13 01:41:57 PM PDT 24
Peak memory 250872 kb
Host smart-fb177488-b272-433b-8dc2-df5f9a3cba80
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954515498 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_state_post_trans.2954515498
Directory /workspace/1.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_prog_failure.1485624981
Short name T461
Test name
Test status
Simulation time 78354004 ps
CPU time 3.05 seconds
Started Jun 13 01:41:38 PM PDT 24
Finished Jun 13 01:41:42 PM PDT 24
Peak memory 222548 kb
Host smart-db2fd449-86ba-471b-9180-dc7db838657a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485624981 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_prog_failure.1485624981
Directory /workspace/1.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_regwen_during_op.3312549012
Short name T173
Test name
Test status
Simulation time 245018143 ps
CPU time 9.59 seconds
Started Jun 13 01:41:32 PM PDT 24
Finished Jun 13 01:41:43 PM PDT 24
Peak memory 217720 kb
Host smart-0ba87ba7-4fd3-4f8e-9371-6eaaaf929d8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312549012 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_regwen_during_op.3312549012
Directory /workspace/1.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_cm.3781751585
Short name T78
Test name
Test status
Simulation time 110869904 ps
CPU time 23.96 seconds
Started Jun 13 01:41:42 PM PDT 24
Finished Jun 13 01:42:07 PM PDT 24
Peak memory 269332 kb
Host smart-2944de98-9daf-4426-be30-a66a6f8956b1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781751585 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_cm.3781751585
Directory /workspace/1.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_mubi.2317282607
Short name T408
Test name
Test status
Simulation time 469261606 ps
CPU time 10.97 seconds
Started Jun 13 01:41:41 PM PDT 24
Finished Jun 13 01:41:52 PM PDT 24
Peak memory 218932 kb
Host smart-884cfb1d-82f4-4eff-a0ba-324bf244bdc6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317282607 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_mubi.2317282607
Directory /workspace/1.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_digest.4208521092
Short name T212
Test name
Test status
Simulation time 1876195031 ps
CPU time 10.06 seconds
Started Jun 13 01:41:41 PM PDT 24
Finished Jun 13 01:41:51 PM PDT 24
Peak memory 226080 kb
Host smart-d073f6bf-ae30-4d6b-9c5c-a55192eb8c1c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208521092 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_di
gest.4208521092
Directory /workspace/1.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_mux.3117621335
Short name T567
Test name
Test status
Simulation time 336980417 ps
CPU time 8.61 seconds
Started Jun 13 01:41:40 PM PDT 24
Finished Jun 13 01:41:50 PM PDT 24
Peak memory 218264 kb
Host smart-71f15a60-9085-419d-8ceb-8570b1d20379
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117621335 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_mux.3
117621335
Directory /workspace/1.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/1.lc_ctrl_security_escalation.3590235981
Short name T634
Test name
Test status
Simulation time 938285080 ps
CPU time 9.69 seconds
Started Jun 13 01:41:37 PM PDT 24
Finished Jun 13 01:41:47 PM PDT 24
Peak memory 225520 kb
Host smart-2fb4381a-7d7b-4062-84be-990731832bf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590235981 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_security_escalation.3590235981
Directory /workspace/1.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/1.lc_ctrl_smoke.3099482884
Short name T480
Test name
Test status
Simulation time 51340031 ps
CPU time 3.27 seconds
Started Jun 13 01:41:28 PM PDT 24
Finished Jun 13 01:41:33 PM PDT 24
Peak memory 214752 kb
Host smart-f4c64db4-22d1-45db-8d8f-73704012cb3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099482884 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_smoke.3099482884
Directory /workspace/1.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_failure.2956126617
Short name T465
Test name
Test status
Simulation time 269292721 ps
CPU time 22.31 seconds
Started Jun 13 01:41:26 PM PDT 24
Finished Jun 13 01:41:50 PM PDT 24
Peak memory 250920 kb
Host smart-6b6633a0-cfce-4f21-998c-bec2388fda53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956126617 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_failure.2956126617
Directory /workspace/1.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_post_trans.1571980598
Short name T38
Test name
Test status
Simulation time 473406695 ps
CPU time 3.95 seconds
Started Jun 13 01:41:37 PM PDT 24
Finished Jun 13 01:41:41 PM PDT 24
Peak memory 222368 kb
Host smart-a7f9812a-57aa-46f5-af05-084307ea5a5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571980598 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_post_trans.1571980598
Directory /workspace/1.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_stress_all.4198993449
Short name T704
Test name
Test status
Simulation time 10814299456 ps
CPU time 210.85 seconds
Started Jun 13 01:41:41 PM PDT 24
Finished Jun 13 01:45:12 PM PDT 24
Peak memory 250784 kb
Host smart-7b772ce7-923d-4285-ac39-76e86d3ffbd8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198993449 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.lc_ctrl_stress_all.4198993449
Directory /workspace/1.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.lc_ctrl_volatile_unlock_smoke.3605310254
Short name T576
Test name
Test status
Simulation time 14058720 ps
CPU time 1.03 seconds
Started Jun 13 01:41:29 PM PDT 24
Finished Jun 13 01:41:31 PM PDT 24
Peak memory 212064 kb
Host smart-1b2beaa7-8fdb-4d25-9e11-45a45f58d49c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605310254 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ct
rl_volatile_unlock_smoke.3605310254
Directory /workspace/1.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_alert_test.3727864028
Short name T308
Test name
Test status
Simulation time 74986437 ps
CPU time 1.4 seconds
Started Jun 13 01:43:01 PM PDT 24
Finished Jun 13 01:43:04 PM PDT 24
Peak memory 209032 kb
Host smart-d99d0227-87ed-4b62-9421-8532a969f4b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727864028 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_alert_test.3727864028
Directory /workspace/10.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.lc_ctrl_errors.1017007951
Short name T258
Test name
Test status
Simulation time 308064204 ps
CPU time 12.63 seconds
Started Jun 13 01:42:55 PM PDT 24
Finished Jun 13 01:43:10 PM PDT 24
Peak memory 218304 kb
Host smart-43e0b9f2-c0af-4c13-8b42-e0c0ac07a001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017007951 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_errors.1017007951
Directory /workspace/10.lc_ctrl_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_access.739319372
Short name T15
Test name
Test status
Simulation time 2090477481 ps
CPU time 11.17 seconds
Started Jun 13 01:42:55 PM PDT 24
Finished Jun 13 01:43:09 PM PDT 24
Peak memory 217128 kb
Host smart-db74d882-50eb-4748-8372-d94c01d46402
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739319372 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_access.739319372
Directory /workspace/10.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_errors.1068639397
Short name T711
Test name
Test status
Simulation time 2153430936 ps
CPU time 66.44 seconds
Started Jun 13 01:42:54 PM PDT 24
Finished Jun 13 01:44:01 PM PDT 24
Peak memory 218296 kb
Host smart-a2a6f38e-d8e9-43ec-8c0f-a03b95c29e6e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068639397 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_e
rrors.1068639397
Directory /workspace/10.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_prog_failure.1492067425
Short name T740
Test name
Test status
Simulation time 299085996 ps
CPU time 6.22 seconds
Started Jun 13 01:42:54 PM PDT 24
Finished Jun 13 01:43:01 PM PDT 24
Peak memory 218184 kb
Host smart-1c17c2de-01e0-46b3-8cc7-42818e2df11f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492067425 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jta
g_prog_failure.1492067425
Directory /workspace/10.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_smoke.420923665
Short name T818
Test name
Test status
Simulation time 481179833 ps
CPU time 3.6 seconds
Started Jun 13 01:42:54 PM PDT 24
Finished Jun 13 01:43:00 PM PDT 24
Peak memory 217688 kb
Host smart-753b704a-82fe-41a6-9781-1d3869242406
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420923665 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_smoke.
420923665
Directory /workspace/10.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_failure.885175076
Short name T400
Test name
Test status
Simulation time 3582657669 ps
CPU time 55.48 seconds
Started Jun 13 01:42:57 PM PDT 24
Finished Jun 13 01:43:53 PM PDT 24
Peak memory 250888 kb
Host smart-13dfa7dc-42ae-454b-86df-85a1160d11b7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885175076 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jta
g_state_failure.885175076
Directory /workspace/10.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_post_trans.2679271046
Short name T266
Test name
Test status
Simulation time 344433314 ps
CPU time 11.52 seconds
Started Jun 13 01:42:55 PM PDT 24
Finished Jun 13 01:43:08 PM PDT 24
Peak memory 221820 kb
Host smart-d3204d2b-59e7-40de-bb04-8af380437384
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679271046 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl
_jtag_state_post_trans.2679271046
Directory /workspace/10.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_prog_failure.3924928328
Short name T157
Test name
Test status
Simulation time 99222554 ps
CPU time 3.24 seconds
Started Jun 13 01:42:56 PM PDT 24
Finished Jun 13 01:43:01 PM PDT 24
Peak memory 222540 kb
Host smart-0cd13a0c-7b34-47a3-8844-650189deec2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924928328 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_prog_failure.3924928328
Directory /workspace/10.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_mubi.3309100428
Short name T771
Test name
Test status
Simulation time 5404152972 ps
CPU time 15.39 seconds
Started Jun 13 01:43:03 PM PDT 24
Finished Jun 13 01:43:20 PM PDT 24
Peak memory 219520 kb
Host smart-d7e6e85b-acfa-4231-bf7c-a68d7592db24
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309100428 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_mubi.3309100428
Directory /workspace/10.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_digest.1519342552
Short name T551
Test name
Test status
Simulation time 1317065367 ps
CPU time 14.27 seconds
Started Jun 13 01:43:03 PM PDT 24
Finished Jun 13 01:43:18 PM PDT 24
Peak memory 218268 kb
Host smart-2bb024d7-2d9b-49e0-bf17-e65369a1354d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519342552 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_d
igest.1519342552
Directory /workspace/10.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_mux.3142332334
Short name T519
Test name
Test status
Simulation time 175705677 ps
CPU time 7.57 seconds
Started Jun 13 01:43:01 PM PDT 24
Finished Jun 13 01:43:10 PM PDT 24
Peak memory 218260 kb
Host smart-80133dd3-2395-4773-adf3-c864457234c1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142332334 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_mux.
3142332334
Directory /workspace/10.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/10.lc_ctrl_security_escalation.660482559
Short name T311
Test name
Test status
Simulation time 1035567814 ps
CPU time 10.22 seconds
Started Jun 13 01:42:57 PM PDT 24
Finished Jun 13 01:43:08 PM PDT 24
Peak memory 226080 kb
Host smart-15d3a3bc-5d5a-43b0-8583-a3437055aedb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660482559 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_security_escalation.660482559
Directory /workspace/10.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/10.lc_ctrl_smoke.854765529
Short name T543
Test name
Test status
Simulation time 56757134 ps
CPU time 3.31 seconds
Started Jun 13 01:42:51 PM PDT 24
Finished Jun 13 01:42:56 PM PDT 24
Peak memory 215168 kb
Host smart-5c6da804-ca86-4aed-a927-0e368e40e9ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854765529 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_smoke.854765529
Directory /workspace/10.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_failure.449714626
Short name T719
Test name
Test status
Simulation time 542715751 ps
CPU time 31.18 seconds
Started Jun 13 01:42:48 PM PDT 24
Finished Jun 13 01:43:22 PM PDT 24
Peak memory 251000 kb
Host smart-039062de-e168-4e8a-a296-9f9db20aa134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449714626 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_failure.449714626
Directory /workspace/10.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_post_trans.986554785
Short name T410
Test name
Test status
Simulation time 236680668 ps
CPU time 7.6 seconds
Started Jun 13 01:42:48 PM PDT 24
Finished Jun 13 01:42:58 PM PDT 24
Peak memory 250332 kb
Host smart-1716be61-dac1-4232-9c56-15147c485391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986554785 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_post_trans.986554785
Directory /workspace/10.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all.2794373360
Short name T462
Test name
Test status
Simulation time 51954043693 ps
CPU time 234.99 seconds
Started Jun 13 01:43:02 PM PDT 24
Finished Jun 13 01:46:57 PM PDT 24
Peak memory 279232 kb
Host smart-b9350ca4-4745-4747-9a73-12bea6075420
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794373360 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.lc_ctrl_stress_all.2794373360
Directory /workspace/10.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.lc_ctrl_volatile_unlock_smoke.1607535679
Short name T155
Test name
Test status
Simulation time 20222271 ps
CPU time 1.46 seconds
Started Jun 13 01:42:49 PM PDT 24
Finished Jun 13 01:42:53 PM PDT 24
Peak memory 213028 kb
Host smart-963b711c-1dd6-422a-b388-fcd9dfb2723f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607535679 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_c
trl_volatile_unlock_smoke.1607535679
Directory /workspace/10.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_alert_test.3653893332
Short name T470
Test name
Test status
Simulation time 16777368 ps
CPU time 1.1 seconds
Started Jun 13 01:43:08 PM PDT 24
Finished Jun 13 01:43:10 PM PDT 24
Peak memory 209032 kb
Host smart-507645bb-bef5-4f19-87ad-5da040359731
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653893332 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_alert_test.3653893332
Directory /workspace/11.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.lc_ctrl_errors.367855694
Short name T490
Test name
Test status
Simulation time 1575006264 ps
CPU time 15.54 seconds
Started Jun 13 01:43:05 PM PDT 24
Finished Jun 13 01:43:22 PM PDT 24
Peak memory 218332 kb
Host smart-0720106c-8faf-44e7-abdb-cab4e5d2a91e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367855694 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_errors.367855694
Directory /workspace/11.lc_ctrl_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_access.229667918
Short name T431
Test name
Test status
Simulation time 461941231 ps
CPU time 11.58 seconds
Started Jun 13 01:43:08 PM PDT 24
Finished Jun 13 01:43:21 PM PDT 24
Peak memory 217252 kb
Host smart-90709dd4-915e-4659-80f7-8a6d22920d16
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229667918 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_access.229667918
Directory /workspace/11.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_errors.1138514548
Short name T467
Test name
Test status
Simulation time 1000367629 ps
CPU time 20.44 seconds
Started Jun 13 01:43:07 PM PDT 24
Finished Jun 13 01:43:28 PM PDT 24
Peak memory 225976 kb
Host smart-a16e7abb-fd6b-484b-8453-de9f2109f376
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138514548 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_e
rrors.1138514548
Directory /workspace/11.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_prog_failure.3766172161
Short name T795
Test name
Test status
Simulation time 1218162280 ps
CPU time 9.66 seconds
Started Jun 13 01:43:07 PM PDT 24
Finished Jun 13 01:43:18 PM PDT 24
Peak memory 218188 kb
Host smart-580876e6-37cb-495c-8afa-4a2d1ef3660c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766172161 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jta
g_prog_failure.3766172161
Directory /workspace/11.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_smoke.2294669461
Short name T370
Test name
Test status
Simulation time 2889063283 ps
CPU time 15.23 seconds
Started Jun 13 01:43:05 PM PDT 24
Finished Jun 13 01:43:21 PM PDT 24
Peak memory 217720 kb
Host smart-f97651bf-c8f3-4b11-b654-d5a310b73468
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294669461 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_smoke
.2294669461
Directory /workspace/11.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_failure.981683805
Short name T537
Test name
Test status
Simulation time 12670235905 ps
CPU time 92.48 seconds
Started Jun 13 01:43:03 PM PDT 24
Finished Jun 13 01:44:37 PM PDT 24
Peak memory 278824 kb
Host smart-28f69a6a-408a-4cf0-8df0-7865618fcee5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981683805 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jta
g_state_failure.981683805
Directory /workspace/11.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_post_trans.3282529546
Short name T752
Test name
Test status
Simulation time 349083573 ps
CPU time 6.36 seconds
Started Jun 13 01:43:00 PM PDT 24
Finished Jun 13 01:43:07 PM PDT 24
Peak memory 224796 kb
Host smart-50259dfa-0924-424f-89fa-48a6afe440c3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282529546 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl
_jtag_state_post_trans.3282529546
Directory /workspace/11.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_prog_failure.2975295353
Short name T676
Test name
Test status
Simulation time 205544095 ps
CPU time 4.53 seconds
Started Jun 13 01:43:03 PM PDT 24
Finished Jun 13 01:43:09 PM PDT 24
Peak memory 222112 kb
Host smart-59d6cfb0-def4-4d6a-8426-afc51e8ec795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975295353 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_prog_failure.2975295353
Directory /workspace/11.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_mubi.940903842
Short name T233
Test name
Test status
Simulation time 837980145 ps
CPU time 19.41 seconds
Started Jun 13 01:43:06 PM PDT 24
Finished Jun 13 01:43:26 PM PDT 24
Peak memory 218932 kb
Host smart-dba6d6c3-4859-448e-963e-aa17986ca94f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940903842 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_mubi.940903842
Directory /workspace/11.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_digest.1823729632
Short name T300
Test name
Test status
Simulation time 2995940215 ps
CPU time 11.4 seconds
Started Jun 13 01:43:07 PM PDT 24
Finished Jun 13 01:43:19 PM PDT 24
Peak memory 226132 kb
Host smart-eaddda0b-6abd-44fb-aeca-dc0d103a11e8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823729632 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_d
igest.1823729632
Directory /workspace/11.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_mux.724359188
Short name T305
Test name
Test status
Simulation time 348554387 ps
CPU time 8.1 seconds
Started Jun 13 01:43:09 PM PDT 24
Finished Jun 13 01:43:18 PM PDT 24
Peak memory 218272 kb
Host smart-716ce517-1280-4e46-93b9-d18559237450
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724359188 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_mux.724359188
Directory /workspace/11.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/11.lc_ctrl_security_escalation.2619929836
Short name T260
Test name
Test status
Simulation time 358706213 ps
CPU time 7.46 seconds
Started Jun 13 01:43:05 PM PDT 24
Finished Jun 13 01:43:13 PM PDT 24
Peak memory 218320 kb
Host smart-64ce715c-9c45-417b-9bad-a51f680b845f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619929836 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_security_escalation.2619929836
Directory /workspace/11.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/11.lc_ctrl_smoke.738217291
Short name T62
Test name
Test status
Simulation time 22230918 ps
CPU time 2.1 seconds
Started Jun 13 01:43:04 PM PDT 24
Finished Jun 13 01:43:07 PM PDT 24
Peak memory 214160 kb
Host smart-9744e42e-33b2-4b02-8e9c-b6bdac0023ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738217291 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_smoke.738217291
Directory /workspace/11.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_failure.3156174491
Short name T336
Test name
Test status
Simulation time 3847927287 ps
CPU time 21.51 seconds
Started Jun 13 01:43:03 PM PDT 24
Finished Jun 13 01:43:26 PM PDT 24
Peak memory 250968 kb
Host smart-55f79341-9344-4058-8ddb-1378fa64287c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156174491 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_failure.3156174491
Directory /workspace/11.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_post_trans.4290936688
Short name T659
Test name
Test status
Simulation time 168079187 ps
CPU time 10.3 seconds
Started Jun 13 01:43:02 PM PDT 24
Finished Jun 13 01:43:13 PM PDT 24
Peak memory 250916 kb
Host smart-8616df92-a989-4b0b-8c6a-b76cc4f8b39c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290936688 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_post_trans.4290936688
Directory /workspace/11.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_stress_all.707478966
Short name T143
Test name
Test status
Simulation time 12551160991 ps
CPU time 149.3 seconds
Started Jun 13 01:43:06 PM PDT 24
Finished Jun 13 01:45:36 PM PDT 24
Peak memory 250956 kb
Host smart-f84eb041-6f71-4894-b54d-f757f0a5a750
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707478966 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.lc_ctrl_stress_all.707478966
Directory /workspace/11.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.lc_ctrl_volatile_unlock_smoke.2682834175
Short name T471
Test name
Test status
Simulation time 22573206 ps
CPU time 0.81 seconds
Started Jun 13 01:43:01 PM PDT 24
Finished Jun 13 01:43:03 PM PDT 24
Peak memory 209100 kb
Host smart-8cc695d5-751f-4207-8980-02b8d84f049d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682834175 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_c
trl_volatile_unlock_smoke.2682834175
Directory /workspace/11.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_alert_test.2532997596
Short name T779
Test name
Test status
Simulation time 136126365 ps
CPU time 1.15 seconds
Started Jun 13 01:43:14 PM PDT 24
Finished Jun 13 01:43:16 PM PDT 24
Peak memory 209044 kb
Host smart-35c45b66-5cac-467c-b64c-fd0166769a91
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532997596 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_alert_test.2532997596
Directory /workspace/12.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.lc_ctrl_errors.778479951
Short name T562
Test name
Test status
Simulation time 584886706 ps
CPU time 13.99 seconds
Started Jun 13 01:43:09 PM PDT 24
Finished Jun 13 01:43:23 PM PDT 24
Peak memory 218264 kb
Host smart-2e590e99-8ca3-4c13-b822-38d729527237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778479951 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_errors.778479951
Directory /workspace/12.lc_ctrl_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_access.2875126451
Short name T21
Test name
Test status
Simulation time 421962114 ps
CPU time 5.28 seconds
Started Jun 13 01:43:11 PM PDT 24
Finished Jun 13 01:43:17 PM PDT 24
Peak memory 217148 kb
Host smart-2b753b07-1ef9-4ec7-8b88-e2d8c9118f5e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875126451 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_access.2875126451
Directory /workspace/12.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_errors.737082398
Short name T161
Test name
Test status
Simulation time 9280049652 ps
CPU time 64.78 seconds
Started Jun 13 01:43:14 PM PDT 24
Finished Jun 13 01:44:20 PM PDT 24
Peak memory 218248 kb
Host smart-a43ab4e2-d1a9-4c5c-88f1-0f154862c595
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737082398 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_er
rors.737082398
Directory /workspace/12.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_prog_failure.1455503361
Short name T623
Test name
Test status
Simulation time 638640581 ps
CPU time 12.92 seconds
Started Jun 13 01:43:14 PM PDT 24
Finished Jun 13 01:43:28 PM PDT 24
Peak memory 224108 kb
Host smart-ec09fe69-52ba-40c9-9613-4d1356099cb7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455503361 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jta
g_prog_failure.1455503361
Directory /workspace/12.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_smoke.2263449896
Short name T271
Test name
Test status
Simulation time 136746180 ps
CPU time 3.1 seconds
Started Jun 13 01:43:13 PM PDT 24
Finished Jun 13 01:43:17 PM PDT 24
Peak memory 217656 kb
Host smart-f307f6c0-bf4d-454b-84d2-3785ea9d0578
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263449896 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_smoke
.2263449896
Directory /workspace/12.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_failure.3214235633
Short name T816
Test name
Test status
Simulation time 10745822627 ps
CPU time 54.8 seconds
Started Jun 13 01:43:15 PM PDT 24
Finished Jun 13 01:44:11 PM PDT 24
Peak memory 268608 kb
Host smart-3d4092cc-2d3f-4b8d-8a09-8a7fec3dfa9c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214235633 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jt
ag_state_failure.3214235633
Directory /workspace/12.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_post_trans.3377896832
Short name T433
Test name
Test status
Simulation time 3436458972 ps
CPU time 25.04 seconds
Started Jun 13 01:43:14 PM PDT 24
Finished Jun 13 01:43:40 PM PDT 24
Peak memory 226356 kb
Host smart-82a8bca9-1a63-4c65-b518-29f010e7fe4c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377896832 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl
_jtag_state_post_trans.3377896832
Directory /workspace/12.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_prog_failure.3503025919
Short name T820
Test name
Test status
Simulation time 61046442 ps
CPU time 1.57 seconds
Started Jun 13 01:43:13 PM PDT 24
Finished Jun 13 01:43:15 PM PDT 24
Peak memory 221700 kb
Host smart-81aa4ad9-2ff0-4a32-9345-9e6177b149f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503025919 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_prog_failure.3503025919
Directory /workspace/12.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_mubi.2548098935
Short name T162
Test name
Test status
Simulation time 1170925449 ps
CPU time 13.32 seconds
Started Jun 13 01:43:13 PM PDT 24
Finished Jun 13 01:43:27 PM PDT 24
Peak memory 218260 kb
Host smart-68aaeb0f-0ef2-416f-9ff7-f8f39537e7a0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548098935 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_mubi.2548098935
Directory /workspace/12.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_digest.2500934727
Short name T849
Test name
Test status
Simulation time 928302423 ps
CPU time 9.74 seconds
Started Jun 13 01:43:13 PM PDT 24
Finished Jun 13 01:43:23 PM PDT 24
Peak memory 218264 kb
Host smart-a8ef32a2-583a-48fc-8341-bd209b353abd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500934727 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_d
igest.2500934727
Directory /workspace/12.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_mux.3555367903
Short name T236
Test name
Test status
Simulation time 289749914 ps
CPU time 9.42 seconds
Started Jun 13 01:43:14 PM PDT 24
Finished Jun 13 01:43:24 PM PDT 24
Peak memory 226112 kb
Host smart-8196205b-6b94-4416-bc07-8e6f70107067
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555367903 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_mux.
3555367903
Directory /workspace/12.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/12.lc_ctrl_security_escalation.3850838610
Short name T735
Test name
Test status
Simulation time 439131425 ps
CPU time 9.36 seconds
Started Jun 13 01:43:08 PM PDT 24
Finished Jun 13 01:43:18 PM PDT 24
Peak memory 225156 kb
Host smart-921863a8-d59d-4cd6-a1b5-236a46cbf36b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850838610 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_security_escalation.3850838610
Directory /workspace/12.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/12.lc_ctrl_smoke.3713460690
Short name T773
Test name
Test status
Simulation time 82064268 ps
CPU time 4.2 seconds
Started Jun 13 01:43:10 PM PDT 24
Finished Jun 13 01:43:15 PM PDT 24
Peak memory 217776 kb
Host smart-8c5ae39e-51b1-4600-bdf7-568300f6ba96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713460690 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_smoke.3713460690
Directory /workspace/12.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_post_trans.2976793196
Short name T251
Test name
Test status
Simulation time 106084457 ps
CPU time 8.32 seconds
Started Jun 13 01:43:08 PM PDT 24
Finished Jun 13 01:43:17 PM PDT 24
Peak memory 250912 kb
Host smart-fe5d6797-bf9a-47a2-b584-dd34d3940344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976793196 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_post_trans.2976793196
Directory /workspace/12.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_stress_all.336518143
Short name T460
Test name
Test status
Simulation time 6664126421 ps
CPU time 211.27 seconds
Started Jun 13 01:43:14 PM PDT 24
Finished Jun 13 01:46:46 PM PDT 24
Peak memory 259164 kb
Host smart-e05bdf75-1936-45f2-b926-b302f64eafb0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336518143 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.lc_ctrl_stress_all.336518143
Directory /workspace/12.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.lc_ctrl_volatile_unlock_smoke.3826387632
Short name T447
Test name
Test status
Simulation time 43528247 ps
CPU time 1.04 seconds
Started Jun 13 01:43:06 PM PDT 24
Finished Jun 13 01:43:08 PM PDT 24
Peak memory 209188 kb
Host smart-c3e91255-a486-4c3e-97b4-b0fa7cc29f35
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826387632 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_c
trl_volatile_unlock_smoke.3826387632
Directory /workspace/12.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_alert_test.757872029
Short name T385
Test name
Test status
Simulation time 41919264 ps
CPU time 1.04 seconds
Started Jun 13 01:43:26 PM PDT 24
Finished Jun 13 01:43:27 PM PDT 24
Peak memory 209048 kb
Host smart-160e7553-e72f-4f9d-a26e-3876d9c06f0f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757872029 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_alert_test.757872029
Directory /workspace/13.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.lc_ctrl_errors.3848393659
Short name T606
Test name
Test status
Simulation time 422401042 ps
CPU time 20.53 seconds
Started Jun 13 01:43:20 PM PDT 24
Finished Jun 13 01:43:41 PM PDT 24
Peak memory 218212 kb
Host smart-d8c67666-e049-4694-8794-9a234bda8308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848393659 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_errors.3848393659
Directory /workspace/13.lc_ctrl_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_access.1394986288
Short name T7
Test name
Test status
Simulation time 83191003 ps
CPU time 2.8 seconds
Started Jun 13 01:43:19 PM PDT 24
Finished Jun 13 01:43:22 PM PDT 24
Peak memory 217072 kb
Host smart-5d3b1d83-9ff4-494a-a8b5-d0a768e4f39c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394986288 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_access.1394986288
Directory /workspace/13.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_errors.1335911832
Short name T273
Test name
Test status
Simulation time 5910282404 ps
CPU time 43.86 seconds
Started Jun 13 01:43:21 PM PDT 24
Finished Jun 13 01:44:05 PM PDT 24
Peak memory 226076 kb
Host smart-c7b37bb2-5f15-4cd1-90f7-49321ed6d018
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335911832 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_e
rrors.1335911832
Directory /workspace/13.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_prog_failure.2818430736
Short name T501
Test name
Test status
Simulation time 302753865 ps
CPU time 8.85 seconds
Started Jun 13 01:43:20 PM PDT 24
Finished Jun 13 01:43:29 PM PDT 24
Peak memory 218188 kb
Host smart-9dcf939c-0c3b-4435-8344-35dabd9ab3e1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818430736 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jta
g_prog_failure.2818430736
Directory /workspace/13.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_smoke.1175432998
Short name T64
Test name
Test status
Simulation time 40257451 ps
CPU time 1.21 seconds
Started Jun 13 01:43:18 PM PDT 24
Finished Jun 13 01:43:21 PM PDT 24
Peak memory 217188 kb
Host smart-439bf6fd-82a0-4458-bcf8-f1cc88d85eb2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175432998 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_smoke
.1175432998
Directory /workspace/13.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_failure.3273615918
Short name T731
Test name
Test status
Simulation time 851148767 ps
CPU time 26.93 seconds
Started Jun 13 01:43:18 PM PDT 24
Finished Jun 13 01:43:45 PM PDT 24
Peak memory 250820 kb
Host smart-2b25ad1d-cb53-4456-a3da-1c57f6f9f220
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273615918 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jt
ag_state_failure.3273615918
Directory /workspace/13.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_post_trans.608903045
Short name T159
Test name
Test status
Simulation time 1143856027 ps
CPU time 13.41 seconds
Started Jun 13 01:43:19 PM PDT 24
Finished Jun 13 01:43:34 PM PDT 24
Peak memory 226284 kb
Host smart-0630c277-780e-4c56-a5d5-0fe6738e7d8c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608903045 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_
jtag_state_post_trans.608903045
Directory /workspace/13.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_prog_failure.1276128881
Short name T620
Test name
Test status
Simulation time 86570187 ps
CPU time 2.32 seconds
Started Jun 13 01:43:22 PM PDT 24
Finished Jun 13 01:43:25 PM PDT 24
Peak memory 218276 kb
Host smart-eb832a32-2e8d-43ea-83ee-d7b0257ce8f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276128881 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_prog_failure.1276128881
Directory /workspace/13.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_mubi.440884601
Short name T226
Test name
Test status
Simulation time 628275901 ps
CPU time 14.42 seconds
Started Jun 13 01:43:19 PM PDT 24
Finished Jun 13 01:43:34 PM PDT 24
Peak memory 226080 kb
Host smart-e45df59b-c41d-4c69-a3e3-f5fdf5f5a722
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440884601 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_mubi.440884601
Directory /workspace/13.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_digest.3719993174
Short name T658
Test name
Test status
Simulation time 704910103 ps
CPU time 8 seconds
Started Jun 13 01:43:18 PM PDT 24
Finished Jun 13 01:43:27 PM PDT 24
Peak memory 218260 kb
Host smart-61a7ba16-d33d-4de3-8921-847e00c85e27
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719993174 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_d
igest.3719993174
Directory /workspace/13.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_mux.799869979
Short name T363
Test name
Test status
Simulation time 1008982652 ps
CPU time 6.72 seconds
Started Jun 13 01:43:21 PM PDT 24
Finished Jun 13 01:43:28 PM PDT 24
Peak memory 218372 kb
Host smart-1df7f444-69e9-4623-a827-f7858855b09c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799869979 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_mux.799869979
Directory /workspace/13.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/13.lc_ctrl_security_escalation.2206398896
Short name T373
Test name
Test status
Simulation time 761569744 ps
CPU time 14.23 seconds
Started Jun 13 01:43:19 PM PDT 24
Finished Jun 13 01:43:34 PM PDT 24
Peak memory 226076 kb
Host smart-c4259c3d-4efe-4e79-b95f-00611ceb2952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206398896 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_security_escalation.2206398896
Directory /workspace/13.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/13.lc_ctrl_smoke.1203384585
Short name T230
Test name
Test status
Simulation time 283473723 ps
CPU time 3.11 seconds
Started Jun 13 01:43:13 PM PDT 24
Finished Jun 13 01:43:17 PM PDT 24
Peak memory 217740 kb
Host smart-3ea941ac-b8d6-45ca-a105-4f2d0b6f5816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203384585 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_smoke.1203384585
Directory /workspace/13.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_failure.2051007684
Short name T1
Test name
Test status
Simulation time 316846612 ps
CPU time 21.49 seconds
Started Jun 13 01:43:22 PM PDT 24
Finished Jun 13 01:43:44 PM PDT 24
Peak memory 250928 kb
Host smart-7a1aff1d-7a49-46a0-8616-e3c47743add5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051007684 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_failure.2051007684
Directory /workspace/13.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_post_trans.3917080268
Short name T268
Test name
Test status
Simulation time 156980317 ps
CPU time 8.78 seconds
Started Jun 13 01:43:18 PM PDT 24
Finished Jun 13 01:43:28 PM PDT 24
Peak memory 250892 kb
Host smart-18157f9b-a5d2-42c0-b407-422b47d891c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917080268 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_post_trans.3917080268
Directory /workspace/13.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all.3025853662
Short name T172
Test name
Test status
Simulation time 4340260451 ps
CPU time 172.43 seconds
Started Jun 13 01:43:19 PM PDT 24
Finished Jun 13 01:46:12 PM PDT 24
Peak memory 267356 kb
Host smart-32d4457e-ce31-49a7-bd07-bd528b75c04a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025853662 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.lc_ctrl_stress_all.3025853662
Directory /workspace/13.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.lc_ctrl_volatile_unlock_smoke.2418004656
Short name T588
Test name
Test status
Simulation time 12295150 ps
CPU time 0.83 seconds
Started Jun 13 01:43:22 PM PDT 24
Finished Jun 13 01:43:24 PM PDT 24
Peak memory 209124 kb
Host smart-a6fd8bfd-dc23-4c94-ad6e-51b3536af088
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418004656 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_c
trl_volatile_unlock_smoke.2418004656
Directory /workspace/13.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_alert_test.753733864
Short name T80
Test name
Test status
Simulation time 40748785 ps
CPU time 0.99 seconds
Started Jun 13 01:43:25 PM PDT 24
Finished Jun 13 01:43:26 PM PDT 24
Peak memory 209096 kb
Host smart-27e0e2d0-7763-4ef0-b755-dee0329d4a1f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753733864 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_alert_test.753733864
Directory /workspace/14.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.lc_ctrl_errors.3932769
Short name T464
Test name
Test status
Simulation time 326151480 ps
CPU time 13.7 seconds
Started Jun 13 01:43:26 PM PDT 24
Finished Jun 13 01:43:40 PM PDT 24
Peak memory 218252 kb
Host smart-4f9560cf-5c47-476d-9fdd-48535339f6f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932769 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_errors.3932769
Directory /workspace/14.lc_ctrl_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_errors.1310301049
Short name T448
Test name
Test status
Simulation time 37001300214 ps
CPU time 62.07 seconds
Started Jun 13 01:43:30 PM PDT 24
Finished Jun 13 01:44:32 PM PDT 24
Peak memory 226064 kb
Host smart-5c2e95cf-75cc-4bd7-a22e-220f54de9c14
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310301049 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_e
rrors.1310301049
Directory /workspace/14.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_prog_failure.1558267814
Short name T706
Test name
Test status
Simulation time 2391231695 ps
CPU time 4.95 seconds
Started Jun 13 01:43:27 PM PDT 24
Finished Jun 13 01:43:32 PM PDT 24
Peak memory 223160 kb
Host smart-2c452fca-be0f-4891-99b5-3b40bb861912
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558267814 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jta
g_prog_failure.1558267814
Directory /workspace/14.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_smoke.1360166080
Short name T846
Test name
Test status
Simulation time 846722820 ps
CPU time 6.66 seconds
Started Jun 13 01:43:25 PM PDT 24
Finished Jun 13 01:43:32 PM PDT 24
Peak memory 217688 kb
Host smart-ab1efea9-9720-4438-91cd-2b45fbe0da36
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360166080 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_smoke
.1360166080
Directory /workspace/14.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_failure.3239527544
Short name T729
Test name
Test status
Simulation time 1894734285 ps
CPU time 43.76 seconds
Started Jun 13 01:43:26 PM PDT 24
Finished Jun 13 01:44:10 PM PDT 24
Peak memory 249496 kb
Host smart-ed0d92c6-b649-4931-b428-b2480d596646
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239527544 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jt
ag_state_failure.3239527544
Directory /workspace/14.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_post_trans.790164623
Short name T292
Test name
Test status
Simulation time 428956392 ps
CPU time 14.27 seconds
Started Jun 13 01:43:26 PM PDT 24
Finished Jun 13 01:43:41 PM PDT 24
Peak memory 222980 kb
Host smart-f92d32fd-85cb-4e60-ac6d-f49e64309cdf
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790164623 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_
jtag_state_post_trans.790164623
Directory /workspace/14.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_prog_failure.3566371625
Short name T210
Test name
Test status
Simulation time 241867369 ps
CPU time 2.7 seconds
Started Jun 13 01:43:24 PM PDT 24
Finished Jun 13 01:43:27 PM PDT 24
Peak memory 222336 kb
Host smart-3a3f7723-79c7-41d2-a9ac-a07fe5ef3aa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566371625 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_prog_failure.3566371625
Directory /workspace/14.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_mubi.3999836254
Short name T774
Test name
Test status
Simulation time 397802557 ps
CPU time 13.2 seconds
Started Jun 13 01:43:27 PM PDT 24
Finished Jun 13 01:43:40 PM PDT 24
Peak memory 218944 kb
Host smart-51e9f00e-66f7-4682-822d-ca927b1b0f8b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999836254 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_mubi.3999836254
Directory /workspace/14.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_digest.1456170271
Short name T396
Test name
Test status
Simulation time 317217912 ps
CPU time 12.62 seconds
Started Jun 13 01:43:25 PM PDT 24
Finished Jun 13 01:43:39 PM PDT 24
Peak memory 218260 kb
Host smart-846dcd80-77ec-4a66-ab9a-14fcfe3ebdd5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456170271 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_d
igest.1456170271
Directory /workspace/14.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/14.lc_ctrl_security_escalation.3437190463
Short name T696
Test name
Test status
Simulation time 393122945 ps
CPU time 9.54 seconds
Started Jun 13 01:43:23 PM PDT 24
Finished Jun 13 01:43:33 PM PDT 24
Peak memory 226056 kb
Host smart-9ff17f0b-6d05-4627-9f37-41ee550f7b45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437190463 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_security_escalation.3437190463
Directory /workspace/14.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/14.lc_ctrl_smoke.1779892102
Short name T570
Test name
Test status
Simulation time 106807841 ps
CPU time 2.54 seconds
Started Jun 13 01:43:25 PM PDT 24
Finished Jun 13 01:43:28 PM PDT 24
Peak memory 214604 kb
Host smart-ee559cfb-eb6d-441b-b19b-3d6c188f3b2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779892102 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_smoke.1779892102
Directory /workspace/14.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_failure.2105782800
Short name T217
Test name
Test status
Simulation time 3467609497 ps
CPU time 26.91 seconds
Started Jun 13 01:43:25 PM PDT 24
Finished Jun 13 01:43:53 PM PDT 24
Peak memory 250928 kb
Host smart-7f4772f3-eb1d-49b7-82a4-bd9d0c57da42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105782800 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_failure.2105782800
Directory /workspace/14.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_post_trans.1973003727
Short name T368
Test name
Test status
Simulation time 93645772 ps
CPU time 8.82 seconds
Started Jun 13 01:43:32 PM PDT 24
Finished Jun 13 01:43:42 PM PDT 24
Peak memory 250908 kb
Host smart-5f26a851-6714-47d9-9aa7-e91b8e8386d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973003727 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_post_trans.1973003727
Directory /workspace/14.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_volatile_unlock_smoke.3075829719
Short name T380
Test name
Test status
Simulation time 42883308 ps
CPU time 0.79 seconds
Started Jun 13 01:43:25 PM PDT 24
Finished Jun 13 01:43:26 PM PDT 24
Peak memory 208928 kb
Host smart-017e54bc-ac1b-4368-9503-7f2e74e5c301
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075829719 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_c
trl_volatile_unlock_smoke.3075829719
Directory /workspace/14.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_alert_test.3819834877
Short name T523
Test name
Test status
Simulation time 25004733 ps
CPU time 1.04 seconds
Started Jun 13 01:43:46 PM PDT 24
Finished Jun 13 01:43:49 PM PDT 24
Peak memory 209120 kb
Host smart-25cc3ede-f7a2-4ed7-b8e6-a612529c8dee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819834877 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_alert_test.3819834877
Directory /workspace/15.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.lc_ctrl_errors.3612423897
Short name T238
Test name
Test status
Simulation time 805906817 ps
CPU time 22.85 seconds
Started Jun 13 01:43:33 PM PDT 24
Finished Jun 13 01:43:57 PM PDT 24
Peak memory 218284 kb
Host smart-df80558d-65fa-4cae-a600-5965f2efc5e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612423897 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_errors.3612423897
Directory /workspace/15.lc_ctrl_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_access.1546698372
Short name T686
Test name
Test status
Simulation time 234340008 ps
CPU time 2.27 seconds
Started Jun 13 01:43:33 PM PDT 24
Finished Jun 13 01:43:36 PM PDT 24
Peak memory 217084 kb
Host smart-9a4d9f36-dd3f-4ee0-83af-1c5f945b3df2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546698372 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_access.1546698372
Directory /workspace/15.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_errors.3853845076
Short name T789
Test name
Test status
Simulation time 7850994078 ps
CPU time 34.94 seconds
Started Jun 13 01:43:31 PM PDT 24
Finished Jun 13 01:44:07 PM PDT 24
Peak memory 218924 kb
Host smart-05d1da97-941f-4771-93a5-09ad621eaf9b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853845076 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_e
rrors.3853845076
Directory /workspace/15.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_prog_failure.156101918
Short name T865
Test name
Test status
Simulation time 3408214075 ps
CPU time 7.78 seconds
Started Jun 13 01:43:31 PM PDT 24
Finished Jun 13 01:43:40 PM PDT 24
Peak memory 223488 kb
Host smart-ee948a7c-0bbf-425a-98c7-2a7577ae2c34
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156101918 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag
_prog_failure.156101918
Directory /workspace/15.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_smoke.1592022073
Short name T459
Test name
Test status
Simulation time 236825233 ps
CPU time 5.4 seconds
Started Jun 13 01:43:31 PM PDT 24
Finished Jun 13 01:43:38 PM PDT 24
Peak memory 217692 kb
Host smart-ddcf20b2-3565-4db5-bb7b-9abc8c280531
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592022073 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_smoke
.1592022073
Directory /workspace/15.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_failure.1991749776
Short name T664
Test name
Test status
Simulation time 1078411617 ps
CPU time 47.24 seconds
Started Jun 13 01:43:35 PM PDT 24
Finished Jun 13 01:44:23 PM PDT 24
Peak memory 250848 kb
Host smart-b02cf254-5112-4567-ba95-ac11a9d9dc4a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991749776 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jt
ag_state_failure.1991749776
Directory /workspace/15.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_post_trans.4228091650
Short name T540
Test name
Test status
Simulation time 694653530 ps
CPU time 21.95 seconds
Started Jun 13 01:43:32 PM PDT 24
Finished Jun 13 01:43:55 PM PDT 24
Peak memory 244120 kb
Host smart-23100405-2f2a-40f4-a3cf-5d140709859e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228091650 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl
_jtag_state_post_trans.4228091650
Directory /workspace/15.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_prog_failure.2688043988
Short name T58
Test name
Test status
Simulation time 26083211 ps
CPU time 1.64 seconds
Started Jun 13 01:43:32 PM PDT 24
Finished Jun 13 01:43:34 PM PDT 24
Peak memory 218216 kb
Host smart-9383f30a-5aef-42da-9b58-9f58eab6b4a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688043988 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_prog_failure.2688043988
Directory /workspace/15.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_mubi.287311941
Short name T88
Test name
Test status
Simulation time 1094580431 ps
CPU time 11.5 seconds
Started Jun 13 01:43:32 PM PDT 24
Finished Jun 13 01:43:45 PM PDT 24
Peak memory 218288 kb
Host smart-4c6d12e1-5d16-47fc-ad52-7a0fb51135ab
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287311941 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_mubi.287311941
Directory /workspace/15.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_digest.242740626
Short name T577
Test name
Test status
Simulation time 256723098 ps
CPU time 11.31 seconds
Started Jun 13 01:43:31 PM PDT 24
Finished Jun 13 01:43:43 PM PDT 24
Peak memory 226096 kb
Host smart-7ed29c15-cd4b-49f5-bb67-b327c52d954f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242740626 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_di
gest.242740626
Directory /workspace/15.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_mux.2698111180
Short name T36
Test name
Test status
Simulation time 1330327797 ps
CPU time 10.88 seconds
Started Jun 13 01:43:32 PM PDT 24
Finished Jun 13 01:43:44 PM PDT 24
Peak memory 218260 kb
Host smart-e9f0c31a-a3e1-44dc-aaaa-312c4d6061b8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698111180 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_mux.
2698111180
Directory /workspace/15.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/15.lc_ctrl_security_escalation.2310883330
Short name T56
Test name
Test status
Simulation time 919900398 ps
CPU time 10.14 seconds
Started Jun 13 01:43:32 PM PDT 24
Finished Jun 13 01:43:43 PM PDT 24
Peak memory 218276 kb
Host smart-5ecb35d7-682e-4f91-bc70-682af481694b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310883330 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_security_escalation.2310883330
Directory /workspace/15.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/15.lc_ctrl_smoke.849714682
Short name T57
Test name
Test status
Simulation time 35657668 ps
CPU time 2.34 seconds
Started Jun 13 01:43:27 PM PDT 24
Finished Jun 13 01:43:30 PM PDT 24
Peak memory 214356 kb
Host smart-382caf01-fd6a-4d8a-b0c9-83263be1055d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849714682 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_smoke.849714682
Directory /workspace/15.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_failure.3811085009
Short name T733
Test name
Test status
Simulation time 169937184 ps
CPU time 21.17 seconds
Started Jun 13 01:43:34 PM PDT 24
Finished Jun 13 01:43:56 PM PDT 24
Peak memory 250912 kb
Host smart-e83fa17e-2b12-42e8-8cd2-70b7bf8ba1c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811085009 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_failure.3811085009
Directory /workspace/15.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_post_trans.1508830192
Short name T515
Test name
Test status
Simulation time 148976587 ps
CPU time 6.45 seconds
Started Jun 13 01:43:30 PM PDT 24
Finished Jun 13 01:43:37 PM PDT 24
Peak memory 246528 kb
Host smart-2b716075-96dd-45ca-8df7-6b72e4d7c2b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508830192 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_post_trans.1508830192
Directory /workspace/15.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all.772667049
Short name T755
Test name
Test status
Simulation time 21256363725 ps
CPU time 179.9 seconds
Started Jun 13 01:43:32 PM PDT 24
Finished Jun 13 01:46:33 PM PDT 24
Peak memory 283724 kb
Host smart-2cfe85cc-a67d-4226-bb54-20e5e695b235
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772667049 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.lc_ctrl_stress_all.772667049
Directory /workspace/15.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all_with_rand_reset.3771097852
Short name T153
Test name
Test status
Simulation time 21502526323 ps
CPU time 434.42 seconds
Started Jun 13 01:43:46 PM PDT 24
Finished Jun 13 01:51:02 PM PDT 24
Peak memory 356648 kb
Host smart-60d9a78a-9b13-401d-9d44-a9694123aa98
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3771097852 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_stress_all_with_rand_reset.3771097852
Directory /workspace/15.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.lc_ctrl_volatile_unlock_smoke.240674277
Short name T68
Test name
Test status
Simulation time 45034611 ps
CPU time 1.08 seconds
Started Jun 13 01:43:25 PM PDT 24
Finished Jun 13 01:43:27 PM PDT 24
Peak memory 212016 kb
Host smart-dd280873-3660-40d5-9348-74c990d7a64c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240674277 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ct
rl_volatile_unlock_smoke.240674277
Directory /workspace/15.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_alert_test.3997272207
Short name T243
Test name
Test status
Simulation time 25220466 ps
CPU time 0.98 seconds
Started Jun 13 01:43:40 PM PDT 24
Finished Jun 13 01:43:42 PM PDT 24
Peak memory 209100 kb
Host smart-269cda69-de98-49d1-bac4-840dd0a3e17f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997272207 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_alert_test.3997272207
Directory /workspace/16.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.lc_ctrl_errors.1272405404
Short name T682
Test name
Test status
Simulation time 355721688 ps
CPU time 8.78 seconds
Started Jun 13 01:43:39 PM PDT 24
Finished Jun 13 01:43:49 PM PDT 24
Peak memory 218304 kb
Host smart-2101f036-3d56-4983-909e-4b0e86539bed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272405404 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_errors.1272405404
Directory /workspace/16.lc_ctrl_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_access.2972585933
Short name T24
Test name
Test status
Simulation time 3024021076 ps
CPU time 17.96 seconds
Started Jun 13 01:43:39 PM PDT 24
Finished Jun 13 01:43:57 PM PDT 24
Peak memory 217600 kb
Host smart-fc871a37-be11-45c6-8018-9bdc6f7871a5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972585933 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_access.2972585933
Directory /workspace/16.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_errors.4045433973
Short name T169
Test name
Test status
Simulation time 2042273063 ps
CPU time 31.6 seconds
Started Jun 13 01:43:38 PM PDT 24
Finished Jun 13 01:44:11 PM PDT 24
Peak memory 226040 kb
Host smart-b5f32eed-7f07-44c6-bf5c-3774c9134ea4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045433973 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_e
rrors.4045433973
Directory /workspace/16.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_prog_failure.1392288294
Short name T354
Test name
Test status
Simulation time 653924436 ps
CPU time 10.29 seconds
Started Jun 13 01:43:39 PM PDT 24
Finished Jun 13 01:43:50 PM PDT 24
Peak memory 218188 kb
Host smart-9cd58dc1-5367-4765-a887-8e71ffdd1e11
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392288294 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jta
g_prog_failure.1392288294
Directory /workspace/16.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_smoke.3259963165
Short name T485
Test name
Test status
Simulation time 308568321 ps
CPU time 4.15 seconds
Started Jun 13 01:43:38 PM PDT 24
Finished Jun 13 01:43:43 PM PDT 24
Peak memory 217732 kb
Host smart-a45a37e2-0dfe-4ada-9ccd-76d85f797c84
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259963165 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_smoke
.3259963165
Directory /workspace/16.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_failure.1207318294
Short name T282
Test name
Test status
Simulation time 2224757496 ps
CPU time 81.46 seconds
Started Jun 13 01:43:38 PM PDT 24
Finished Jun 13 01:45:00 PM PDT 24
Peak memory 275476 kb
Host smart-2d531932-a4d3-4261-aa47-b569ff537e39
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207318294 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jt
ag_state_failure.1207318294
Directory /workspace/16.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_post_trans.997723434
Short name T787
Test name
Test status
Simulation time 783673572 ps
CPU time 25.43 seconds
Started Jun 13 01:43:39 PM PDT 24
Finished Jun 13 01:44:06 PM PDT 24
Peak memory 242640 kb
Host smart-ec39078f-a453-45e5-adc2-fb7d732d70f4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997723434 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_
jtag_state_post_trans.997723434
Directory /workspace/16.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_prog_failure.2885744288
Short name T839
Test name
Test status
Simulation time 80874529 ps
CPU time 1.61 seconds
Started Jun 13 01:43:38 PM PDT 24
Finished Jun 13 01:43:41 PM PDT 24
Peak memory 218224 kb
Host smart-1a6009fd-ccc1-4e12-a8d9-228ce5533abc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885744288 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_prog_failure.2885744288
Directory /workspace/16.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_mubi.3538512176
Short name T382
Test name
Test status
Simulation time 626336488 ps
CPU time 12.57 seconds
Started Jun 13 01:43:40 PM PDT 24
Finished Jun 13 01:43:53 PM PDT 24
Peak memory 218932 kb
Host smart-e4a1909f-9dbb-4dbb-86da-dcf6e0ba3d16
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538512176 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_mubi.3538512176
Directory /workspace/16.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_digest.2580002767
Short name T809
Test name
Test status
Simulation time 676041973 ps
CPU time 19.11 seconds
Started Jun 13 01:43:37 PM PDT 24
Finished Jun 13 01:43:57 PM PDT 24
Peak memory 226072 kb
Host smart-94bee2e4-2884-4572-b643-d2f0086ca506
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580002767 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_d
igest.2580002767
Directory /workspace/16.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_mux.2954784481
Short name T321
Test name
Test status
Simulation time 1167769826 ps
CPU time 9.18 seconds
Started Jun 13 01:43:39 PM PDT 24
Finished Jun 13 01:43:49 PM PDT 24
Peak memory 218288 kb
Host smart-7f21461d-bf8e-42cf-9fe5-a553307e8437
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954784481 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_mux.
2954784481
Directory /workspace/16.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/16.lc_ctrl_security_escalation.966698768
Short name T407
Test name
Test status
Simulation time 284442790 ps
CPU time 11.43 seconds
Started Jun 13 01:43:46 PM PDT 24
Finished Jun 13 01:43:59 PM PDT 24
Peak memory 226060 kb
Host smart-e34c3a23-9c85-4c45-9ff6-508805828cac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966698768 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_security_escalation.966698768
Directory /workspace/16.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/16.lc_ctrl_smoke.2690347214
Short name T441
Test name
Test status
Simulation time 86148436 ps
CPU time 2.07 seconds
Started Jun 13 01:43:39 PM PDT 24
Finished Jun 13 01:43:42 PM PDT 24
Peak memory 214380 kb
Host smart-fbdeda1a-a8e7-4289-8d81-a5a25d481d38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690347214 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_smoke.2690347214
Directory /workspace/16.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_failure.4105028392
Short name T662
Test name
Test status
Simulation time 428716228 ps
CPU time 21.98 seconds
Started Jun 13 01:43:40 PM PDT 24
Finished Jun 13 01:44:03 PM PDT 24
Peak memory 250900 kb
Host smart-80233682-b62c-4270-9894-6dfc681aceda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105028392 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_failure.4105028392
Directory /workspace/16.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_post_trans.4156184023
Short name T60
Test name
Test status
Simulation time 70842681 ps
CPU time 5.98 seconds
Started Jun 13 01:43:41 PM PDT 24
Finished Jun 13 01:43:47 PM PDT 24
Peak memory 242724 kb
Host smart-c186903c-22ab-4538-931a-c43369899288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156184023 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_post_trans.4156184023
Directory /workspace/16.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_stress_all.2748468145
Short name T253
Test name
Test status
Simulation time 75143273912 ps
CPU time 134.09 seconds
Started Jun 13 01:43:37 PM PDT 24
Finished Jun 13 01:45:52 PM PDT 24
Peak memory 277456 kb
Host smart-4c2e38e3-ff15-4c33-aa41-dc946bc2269e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748468145 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.lc_ctrl_stress_all.2748468145
Directory /workspace/16.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.lc_ctrl_volatile_unlock_smoke.3323013160
Short name T586
Test name
Test status
Simulation time 14449219 ps
CPU time 1.19 seconds
Started Jun 13 01:43:40 PM PDT 24
Finished Jun 13 01:43:42 PM PDT 24
Peak memory 211948 kb
Host smart-865dee2d-4d53-40da-997a-357758295c46
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323013160 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_c
trl_volatile_unlock_smoke.3323013160
Directory /workspace/16.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_alert_test.2364840378
Short name T361
Test name
Test status
Simulation time 52161606 ps
CPU time 0.89 seconds
Started Jun 13 01:43:50 PM PDT 24
Finished Jun 13 01:43:52 PM PDT 24
Peak memory 209004 kb
Host smart-4c44cdd8-7d95-4217-9711-c495af92a05d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364840378 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_alert_test.2364840378
Directory /workspace/17.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.lc_ctrl_errors.155926809
Short name T356
Test name
Test status
Simulation time 1095707464 ps
CPU time 13.16 seconds
Started Jun 13 01:43:44 PM PDT 24
Finished Jun 13 01:43:58 PM PDT 24
Peak memory 218220 kb
Host smart-d229d5cd-ea7e-4c76-b3ee-f93d5e038bf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=155926809 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_errors.155926809
Directory /workspace/17.lc_ctrl_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_access.1903874304
Short name T402
Test name
Test status
Simulation time 727199357 ps
CPU time 5.24 seconds
Started Jun 13 01:43:44 PM PDT 24
Finished Jun 13 01:43:51 PM PDT 24
Peak memory 217292 kb
Host smart-aa2a55f1-cbf7-4053-a438-9d32650e37f3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903874304 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_access.1903874304
Directory /workspace/17.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_errors.3777675097
Short name T669
Test name
Test status
Simulation time 4864266019 ps
CPU time 37.98 seconds
Started Jun 13 01:43:45 PM PDT 24
Finished Jun 13 01:44:24 PM PDT 24
Peak memory 218968 kb
Host smart-59a651fb-0cb2-433e-afa6-c72f13fbbfb4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777675097 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_e
rrors.3777675097
Directory /workspace/17.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_prog_failure.161459708
Short name T746
Test name
Test status
Simulation time 2247713799 ps
CPU time 6.74 seconds
Started Jun 13 01:43:47 PM PDT 24
Finished Jun 13 01:43:55 PM PDT 24
Peak memory 218160 kb
Host smart-10294609-b687-43bb-a530-d51cd3cd9ad8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161459708 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag
_prog_failure.161459708
Directory /workspace/17.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_smoke.1111760045
Short name T221
Test name
Test status
Simulation time 112185795 ps
CPU time 3.26 seconds
Started Jun 13 01:43:46 PM PDT 24
Finished Jun 13 01:43:51 PM PDT 24
Peak memory 217692 kb
Host smart-3cfffb37-ffbe-470f-8767-4fb86ade1c3e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111760045 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_smoke
.1111760045
Directory /workspace/17.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_failure.2276145963
Short name T234
Test name
Test status
Simulation time 1913156632 ps
CPU time 49.41 seconds
Started Jun 13 01:43:45 PM PDT 24
Finished Jun 13 01:44:36 PM PDT 24
Peak memory 267316 kb
Host smart-de93ca7d-d152-4c2c-a82a-2f999248224c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276145963 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jt
ag_state_failure.2276145963
Directory /workspace/17.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_post_trans.39475764
Short name T692
Test name
Test status
Simulation time 1574492604 ps
CPU time 25.78 seconds
Started Jun 13 01:43:43 PM PDT 24
Finished Jun 13 01:44:11 PM PDT 24
Peak memory 248744 kb
Host smart-39725e99-2343-42aa-b07a-97496ceb0ca0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39475764 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_s
tate_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_j
tag_state_post_trans.39475764
Directory /workspace/17.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_prog_failure.3525801254
Short name T777
Test name
Test status
Simulation time 69362597 ps
CPU time 3.58 seconds
Started Jun 13 01:43:44 PM PDT 24
Finished Jun 13 01:43:49 PM PDT 24
Peak memory 218188 kb
Host smart-b7be822c-7d12-400a-b284-7e3ddee6e665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525801254 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_prog_failure.3525801254
Directory /workspace/17.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_mubi.1379111647
Short name T167
Test name
Test status
Simulation time 216899405 ps
CPU time 9.11 seconds
Started Jun 13 01:43:46 PM PDT 24
Finished Jun 13 01:43:57 PM PDT 24
Peak memory 218332 kb
Host smart-def52c92-2641-4b61-9d3e-bf678510ac54
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379111647 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_mubi.1379111647
Directory /workspace/17.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_digest.2817178202
Short name T439
Test name
Test status
Simulation time 2963447240 ps
CPU time 13.03 seconds
Started Jun 13 01:43:50 PM PDT 24
Finished Jun 13 01:44:03 PM PDT 24
Peak memory 218312 kb
Host smart-46009912-8dae-4f70-8a2e-3171eef8a18b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817178202 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_d
igest.2817178202
Directory /workspace/17.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_mux.4048891676
Short name T405
Test name
Test status
Simulation time 2327404387 ps
CPU time 16.23 seconds
Started Jun 13 01:43:48 PM PDT 24
Finished Jun 13 01:44:05 PM PDT 24
Peak memory 218324 kb
Host smart-5c21ce12-c949-488c-9668-2b85f813200d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048891676 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_mux.
4048891676
Directory /workspace/17.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/17.lc_ctrl_security_escalation.2162781829
Short name T700
Test name
Test status
Simulation time 383231308 ps
CPU time 10.99 seconds
Started Jun 13 01:43:44 PM PDT 24
Finished Jun 13 01:43:56 PM PDT 24
Peak memory 226052 kb
Host smart-b60ed12c-b750-4ad2-8bde-b15f3aeb4b8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162781829 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_security_escalation.2162781829
Directory /workspace/17.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/17.lc_ctrl_smoke.412526022
Short name T808
Test name
Test status
Simulation time 28175934 ps
CPU time 1.71 seconds
Started Jun 13 01:43:45 PM PDT 24
Finished Jun 13 01:43:49 PM PDT 24
Peak memory 217768 kb
Host smart-e005eadc-82a8-4ea2-b35d-84ee7f4081f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412526022 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_smoke.412526022
Directory /workspace/17.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_failure.676349269
Short name T772
Test name
Test status
Simulation time 942715744 ps
CPU time 25.76 seconds
Started Jun 13 01:43:45 PM PDT 24
Finished Jun 13 01:44:13 PM PDT 24
Peak memory 250904 kb
Host smart-018e3c96-b024-46ed-ac63-c338c423b318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676349269 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_failure.676349269
Directory /workspace/17.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_post_trans.3190254547
Short name T77
Test name
Test status
Simulation time 155355790 ps
CPU time 7.11 seconds
Started Jun 13 01:43:45 PM PDT 24
Finished Jun 13 01:43:54 PM PDT 24
Peak memory 250924 kb
Host smart-0ff490ee-df27-4b15-bb5c-14eaae05ed4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190254547 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_post_trans.3190254547
Directory /workspace/17.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all.156908157
Short name T835
Test name
Test status
Simulation time 42580556010 ps
CPU time 186.2 seconds
Started Jun 13 01:43:51 PM PDT 24
Finished Jun 13 01:46:58 PM PDT 24
Peak memory 283712 kb
Host smart-c0d4ba16-ef6e-48f5-901a-2a47037ec0fb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156908157 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.lc_ctrl_stress_all.156908157
Directory /workspace/17.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.lc_ctrl_volatile_unlock_smoke.3019849319
Short name T867
Test name
Test status
Simulation time 67202375 ps
CPU time 1.04 seconds
Started Jun 13 01:43:45 PM PDT 24
Finished Jun 13 01:43:47 PM PDT 24
Peak memory 212960 kb
Host smart-d74ef98c-4fdd-432f-89e2-b1dd844075b7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019849319 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_c
trl_volatile_unlock_smoke.3019849319
Directory /workspace/17.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_alert_test.3475342509
Short name T532
Test name
Test status
Simulation time 34145143 ps
CPU time 0.89 seconds
Started Jun 13 01:44:16 PM PDT 24
Finished Jun 13 01:44:18 PM PDT 24
Peak memory 208972 kb
Host smart-1066ac5c-6146-4f92-8ea7-5d12395ccf80
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475342509 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_alert_test.3475342509
Directory /workspace/18.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.lc_ctrl_errors.2357390360
Short name T475
Test name
Test status
Simulation time 977276953 ps
CPU time 13.7 seconds
Started Jun 13 01:43:51 PM PDT 24
Finished Jun 13 01:44:05 PM PDT 24
Peak memory 218272 kb
Host smart-b21fc167-ab49-4037-b322-dc413b405494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357390360 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_errors.2357390360
Directory /workspace/18.lc_ctrl_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_access.2110240598
Short name T8
Test name
Test status
Simulation time 2727005308 ps
CPU time 7.54 seconds
Started Jun 13 01:43:56 PM PDT 24
Finished Jun 13 01:44:04 PM PDT 24
Peak memory 217656 kb
Host smart-08e62a25-1906-4ab7-80db-d9caf75f3482
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110240598 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_access.2110240598
Directory /workspace/18.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_errors.2309335974
Short name T792
Test name
Test status
Simulation time 8545788115 ps
CPU time 54.93 seconds
Started Jun 13 01:43:59 PM PDT 24
Finished Jun 13 01:44:54 PM PDT 24
Peak memory 226092 kb
Host smart-25613cf1-7480-4b7c-856e-c83d4de60359
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309335974 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_e
rrors.2309335974
Directory /workspace/18.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_prog_failure.3067709257
Short name T805
Test name
Test status
Simulation time 1456555243 ps
CPU time 20.66 seconds
Started Jun 13 01:43:53 PM PDT 24
Finished Jun 13 01:44:14 PM PDT 24
Peak memory 218188 kb
Host smart-05f6e6a5-b4f6-4ee9-8cb1-18d373b064f1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067709257 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jta
g_prog_failure.3067709257
Directory /workspace/18.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_smoke.1016997317
Short name T67
Test name
Test status
Simulation time 2270331205 ps
CPU time 8.22 seconds
Started Jun 13 01:43:51 PM PDT 24
Finished Jun 13 01:43:59 PM PDT 24
Peak memory 217744 kb
Host smart-499778cc-263d-4e50-906e-522400d5e54f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016997317 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_smoke
.1016997317
Directory /workspace/18.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_failure.3409476332
Short name T572
Test name
Test status
Simulation time 1367172563 ps
CPU time 42.76 seconds
Started Jun 13 01:43:52 PM PDT 24
Finished Jun 13 01:44:36 PM PDT 24
Peak memory 267212 kb
Host smart-7d60a113-4c5e-497b-8656-7b2f00215142
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409476332 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jt
ag_state_failure.3409476332
Directory /workspace/18.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_post_trans.1712386903
Short name T661
Test name
Test status
Simulation time 2265806177 ps
CPU time 12.83 seconds
Started Jun 13 01:43:49 PM PDT 24
Finished Jun 13 01:44:02 PM PDT 24
Peak memory 250708 kb
Host smart-f392b751-b477-486e-972d-930af7a8b7cc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712386903 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl
_jtag_state_post_trans.1712386903
Directory /workspace/18.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_prog_failure.2367201553
Short name T222
Test name
Test status
Simulation time 481735392 ps
CPU time 3.7 seconds
Started Jun 13 01:43:53 PM PDT 24
Finished Jun 13 01:43:57 PM PDT 24
Peak memory 222704 kb
Host smart-de5d2f7e-2ed2-4ff8-ac9a-68bee4026df1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367201553 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_prog_failure.2367201553
Directory /workspace/18.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_mubi.2935414313
Short name T391
Test name
Test status
Simulation time 224559148 ps
CPU time 9.95 seconds
Started Jun 13 01:43:56 PM PDT 24
Finished Jun 13 01:44:07 PM PDT 24
Peak memory 226080 kb
Host smart-49b19fac-042f-4dbe-94dd-1b9cfc288130
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935414313 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_mubi.2935414313
Directory /workspace/18.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_digest.912752097
Short name T299
Test name
Test status
Simulation time 321737333 ps
CPU time 9.84 seconds
Started Jun 13 01:43:56 PM PDT 24
Finished Jun 13 01:44:07 PM PDT 24
Peak memory 218300 kb
Host smart-736a28e1-eb49-4c43-9205-a8e91ab5081a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912752097 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_di
gest.912752097
Directory /workspace/18.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_mux.3005808274
Short name T274
Test name
Test status
Simulation time 899441308 ps
CPU time 8.66 seconds
Started Jun 13 01:43:57 PM PDT 24
Finished Jun 13 01:44:06 PM PDT 24
Peak memory 218256 kb
Host smart-082e98fe-6575-476d-9b0e-48ff6fdc4d78
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005808274 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_mux.
3005808274
Directory /workspace/18.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/18.lc_ctrl_security_escalation.3535207336
Short name T152
Test name
Test status
Simulation time 1090828041 ps
CPU time 8.14 seconds
Started Jun 13 01:43:51 PM PDT 24
Finished Jun 13 01:44:01 PM PDT 24
Peak memory 226060 kb
Host smart-5a482344-2cff-4db2-94d9-c3398499090b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535207336 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_security_escalation.3535207336
Directory /workspace/18.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/18.lc_ctrl_smoke.456238552
Short name T564
Test name
Test status
Simulation time 41354597 ps
CPU time 2.74 seconds
Started Jun 13 01:43:52 PM PDT 24
Finished Jun 13 01:43:56 PM PDT 24
Peak memory 214872 kb
Host smart-659d7b98-7e32-4eae-95c5-0e28d7c86633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456238552 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_smoke.456238552
Directory /workspace/18.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_failure.484147237
Short name T286
Test name
Test status
Simulation time 711370385 ps
CPU time 35.94 seconds
Started Jun 13 01:43:51 PM PDT 24
Finished Jun 13 01:44:28 PM PDT 24
Peak memory 246300 kb
Host smart-e3059f83-0a8e-4ea1-9687-a800bc1c76fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484147237 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_failure.484147237
Directory /workspace/18.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_post_trans.1057080756
Short name T76
Test name
Test status
Simulation time 882808009 ps
CPU time 9.3 seconds
Started Jun 13 01:43:49 PM PDT 24
Finished Jun 13 01:43:59 PM PDT 24
Peak memory 250900 kb
Host smart-fa9242bd-b62b-48f1-bbb7-b56f12be6bde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057080756 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_post_trans.1057080756
Directory /workspace/18.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all.2424423710
Short name T660
Test name
Test status
Simulation time 1300824318 ps
CPU time 31.06 seconds
Started Jun 13 01:43:57 PM PDT 24
Finished Jun 13 01:44:29 PM PDT 24
Peak memory 250888 kb
Host smart-e53acfe6-7919-478b-831c-ecba1f13022a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424423710 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.lc_ctrl_stress_all.2424423710
Directory /workspace/18.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.lc_ctrl_volatile_unlock_smoke.3502817229
Short name T259
Test name
Test status
Simulation time 32981782 ps
CPU time 1.19 seconds
Started Jun 13 01:43:51 PM PDT 24
Finished Jun 13 01:43:54 PM PDT 24
Peak memory 213008 kb
Host smart-4908845d-4e7b-4e00-ad5b-86d074950aad
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502817229 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_c
trl_volatile_unlock_smoke.3502817229
Directory /workspace/18.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_alert_test.29137560
Short name T617
Test name
Test status
Simulation time 23779469 ps
CPU time 1.21 seconds
Started Jun 13 01:44:02 PM PDT 24
Finished Jun 13 01:44:05 PM PDT 24
Peak memory 209132 kb
Host smart-665087e7-c4e9-4430-8829-33dcffd934d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29137560 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_alert_test.29137560
Directory /workspace/19.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.lc_ctrl_errors.2992246256
Short name T13
Test name
Test status
Simulation time 511443057 ps
CPU time 14.05 seconds
Started Jun 13 01:43:59 PM PDT 24
Finished Jun 13 01:44:13 PM PDT 24
Peak memory 218144 kb
Host smart-538d4fb6-4d53-4f10-bdfc-1bb01600ae45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992246256 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_errors.2992246256
Directory /workspace/19.lc_ctrl_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_access.2056873810
Short name T801
Test name
Test status
Simulation time 815378122 ps
CPU time 2.34 seconds
Started Jun 13 01:44:03 PM PDT 24
Finished Jun 13 01:44:06 PM PDT 24
Peak memory 217164 kb
Host smart-cc3a1f43-90de-4dac-9696-4b9b3d0d7815
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056873810 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_access.2056873810
Directory /workspace/19.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_errors.4081851980
Short name T277
Test name
Test status
Simulation time 15480425440 ps
CPU time 56.13 seconds
Started Jun 13 01:43:56 PM PDT 24
Finished Jun 13 01:44:53 PM PDT 24
Peak memory 219728 kb
Host smart-8f0a36d3-33f0-43e4-ac78-62a39b90074a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081851980 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_e
rrors.4081851980
Directory /workspace/19.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_prog_failure.102027204
Short name T611
Test name
Test status
Simulation time 184461440 ps
CPU time 4.69 seconds
Started Jun 13 01:43:57 PM PDT 24
Finished Jun 13 01:44:03 PM PDT 24
Peak memory 223016 kb
Host smart-7e1defc2-ffcb-4474-93ae-143b31763dea
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102027204 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag
_prog_failure.102027204
Directory /workspace/19.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_smoke.1550745101
Short name T61
Test name
Test status
Simulation time 802083318 ps
CPU time 3.31 seconds
Started Jun 13 01:43:56 PM PDT 24
Finished Jun 13 01:44:00 PM PDT 24
Peak memory 217652 kb
Host smart-ae4d658f-3666-456a-9cee-34cea2db1d17
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550745101 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_smoke
.1550745101
Directory /workspace/19.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_failure.3391699164
Short name T257
Test name
Test status
Simulation time 5592719619 ps
CPU time 47 seconds
Started Jun 13 01:44:00 PM PDT 24
Finished Jun 13 01:44:47 PM PDT 24
Peak memory 252300 kb
Host smart-7c0e9ae1-a26e-47b5-bd10-2b61b51117a6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391699164 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jt
ag_state_failure.3391699164
Directory /workspace/19.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_post_trans.3052002605
Short name T399
Test name
Test status
Simulation time 718940860 ps
CPU time 7.62 seconds
Started Jun 13 01:43:56 PM PDT 24
Finished Jun 13 01:44:04 PM PDT 24
Peak memory 225396 kb
Host smart-aad1fcd6-ec0f-4f78-b6d2-b16f9ba574d5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052002605 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl
_jtag_state_post_trans.3052002605
Directory /workspace/19.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_prog_failure.722349996
Short name T419
Test name
Test status
Simulation time 22003077 ps
CPU time 1.64 seconds
Started Jun 13 01:43:57 PM PDT 24
Finished Jun 13 01:43:59 PM PDT 24
Peak memory 222036 kb
Host smart-08abbbba-0c79-4a78-9bb0-d9fbbfd337e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722349996 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_prog_failure.722349996
Directory /workspace/19.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_mubi.995624031
Short name T468
Test name
Test status
Simulation time 1144104477 ps
CPU time 14.38 seconds
Started Jun 13 01:44:04 PM PDT 24
Finished Jun 13 01:44:20 PM PDT 24
Peak memory 226112 kb
Host smart-5833fb20-438b-4dd9-adc4-e73ce3c19444
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995624031 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_mubi.995624031
Directory /workspace/19.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_digest.1705264948
Short name T250
Test name
Test status
Simulation time 229423996 ps
CPU time 9.99 seconds
Started Jun 13 01:44:03 PM PDT 24
Finished Jun 13 01:44:15 PM PDT 24
Peak memory 218268 kb
Host smart-39599301-9385-4c9f-a5ac-afedd1fa4f44
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705264948 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_d
igest.1705264948
Directory /workspace/19.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_mux.1935560253
Short name T807
Test name
Test status
Simulation time 1596532513 ps
CPU time 9.38 seconds
Started Jun 13 01:44:04 PM PDT 24
Finished Jun 13 01:44:14 PM PDT 24
Peak memory 218252 kb
Host smart-46c75464-33b2-4fec-86be-d90d55c33f70
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935560253 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_mux.
1935560253
Directory /workspace/19.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/19.lc_ctrl_security_escalation.1957141918
Short name T649
Test name
Test status
Simulation time 1828094259 ps
CPU time 6.65 seconds
Started Jun 13 01:43:56 PM PDT 24
Finished Jun 13 01:44:04 PM PDT 24
Peak memory 218284 kb
Host smart-0b3e429c-ed46-46d2-8ffe-aa0ce67069a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957141918 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_security_escalation.1957141918
Directory /workspace/19.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_failure.1713247069
Short name T362
Test name
Test status
Simulation time 309970150 ps
CPU time 28.29 seconds
Started Jun 13 01:43:56 PM PDT 24
Finished Jun 13 01:44:25 PM PDT 24
Peak memory 250900 kb
Host smart-c44d9eb9-c111-4cd2-8d54-707ba9c49b8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713247069 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_failure.1713247069
Directory /workspace/19.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_post_trans.1055769663
Short name T435
Test name
Test status
Simulation time 264165352 ps
CPU time 6.27 seconds
Started Jun 13 01:43:59 PM PDT 24
Finished Jun 13 01:44:06 PM PDT 24
Peak memory 250252 kb
Host smart-c32b69b2-2d26-4a2b-89c9-2c3f335d77db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055769663 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_post_trans.1055769663
Directory /workspace/19.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all.1877226681
Short name T89
Test name
Test status
Simulation time 566423160 ps
CPU time 30.78 seconds
Started Jun 13 01:44:06 PM PDT 24
Finished Jun 13 01:44:38 PM PDT 24
Peak memory 250912 kb
Host smart-6875bfda-17dd-45e1-b69c-e4c8acd32a2a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877226681 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.lc_ctrl_stress_all.1877226681
Directory /workspace/19.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.lc_ctrl_volatile_unlock_smoke.3855845376
Short name T556
Test name
Test status
Simulation time 41410602 ps
CPU time 0.92 seconds
Started Jun 13 01:43:56 PM PDT 24
Finished Jun 13 01:43:58 PM PDT 24
Peak memory 212016 kb
Host smart-a94fa526-95a6-4cf6-8420-90b2a5caf910
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855845376 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_c
trl_volatile_unlock_smoke.3855845376
Directory /workspace/19.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_alert_test.497230607
Short name T442
Test name
Test status
Simulation time 83426958 ps
CPU time 0.99 seconds
Started Jun 13 01:41:46 PM PDT 24
Finished Jun 13 01:41:48 PM PDT 24
Peak memory 209032 kb
Host smart-917dc750-2984-4f52-a6e1-8d39e640f7c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497230607 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_alert_test.497230607
Directory /workspace/2.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.lc_ctrl_claim_transition_if.3808933720
Short name T630
Test name
Test status
Simulation time 49195205 ps
CPU time 0.86 seconds
Started Jun 13 01:41:46 PM PDT 24
Finished Jun 13 01:41:47 PM PDT 24
Peak memory 209032 kb
Host smart-19afd261-d03e-46a1-86f0-940828c64d43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808933720 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_claim_transition_if.3808933720
Directory /workspace/2.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/2.lc_ctrl_errors.1915230893
Short name T278
Test name
Test status
Simulation time 256265320 ps
CPU time 11.08 seconds
Started Jun 13 01:41:45 PM PDT 24
Finished Jun 13 01:41:57 PM PDT 24
Peak memory 218228 kb
Host smart-7b742d43-b309-4b50-8d93-8c1ce4864539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915230893 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_errors.1915230893
Directory /workspace/2.lc_ctrl_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_access.3114769143
Short name T538
Test name
Test status
Simulation time 2519566823 ps
CPU time 13.49 seconds
Started Jun 13 01:41:50 PM PDT 24
Finished Jun 13 01:42:04 PM PDT 24
Peak memory 217616 kb
Host smart-887de873-c269-4d21-9619-41f080390632
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114769143 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_access.3114769143
Directory /workspace/2.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_errors.1508394133
Short name T240
Test name
Test status
Simulation time 2289595478 ps
CPU time 66.87 seconds
Started Jun 13 01:41:45 PM PDT 24
Finished Jun 13 01:42:53 PM PDT 24
Peak memory 218208 kb
Host smart-8db01f76-caae-4841-aca0-41e80532dc0a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508394133 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_er
rors.1508394133
Directory /workspace/2.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_priority.1744380771
Short name T825
Test name
Test status
Simulation time 1245927345 ps
CPU time 12.67 seconds
Started Jun 13 01:41:45 PM PDT 24
Finished Jun 13 01:41:58 PM PDT 24
Peak memory 217852 kb
Host smart-7e3864d1-4226-439b-8bc0-e49b928ac3bb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744380771 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_priority.1
744380771
Directory /workspace/2.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_prog_failure.729968685
Short name T597
Test name
Test status
Simulation time 2406079285 ps
CPU time 3.23 seconds
Started Jun 13 01:41:47 PM PDT 24
Finished Jun 13 01:41:51 PM PDT 24
Peak memory 218256 kb
Host smart-600436ee-9c07-4e38-b429-3c78cff08be7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729968685 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_
prog_failure.729968685
Directory /workspace/2.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_regwen_during_op.3075823723
Short name T229
Test name
Test status
Simulation time 2891780958 ps
CPU time 19.44 seconds
Started Jun 13 01:41:47 PM PDT 24
Finished Jun 13 01:42:08 PM PDT 24
Peak memory 217728 kb
Host smart-100c4a19-a9f9-4e38-9003-cf850e57428e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075823723 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_regwen_during_op.3075823723
Directory /workspace/2.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_smoke.2731439702
Short name T840
Test name
Test status
Simulation time 207038290 ps
CPU time 3.55 seconds
Started Jun 13 01:41:43 PM PDT 24
Finished Jun 13 01:41:48 PM PDT 24
Peak memory 217720 kb
Host smart-30aa3924-508e-4951-955e-a1e6021e5560
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731439702 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_smoke.
2731439702
Directory /workspace/2.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_failure.2098266485
Short name T242
Test name
Test status
Simulation time 2553008715 ps
CPU time 37.93 seconds
Started Jun 13 01:41:45 PM PDT 24
Finished Jun 13 01:42:24 PM PDT 24
Peak memory 266604 kb
Host smart-aef31155-1044-4a36-a65c-aba299bf4e92
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098266485 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jta
g_state_failure.2098266485
Directory /workspace/2.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_post_trans.159248288
Short name T331
Test name
Test status
Simulation time 1617167549 ps
CPU time 16.72 seconds
Started Jun 13 01:41:41 PM PDT 24
Finished Jun 13 01:41:59 PM PDT 24
Peak memory 247436 kb
Host smart-833ae9c7-8f60-4b52-8172-1b45628c6750
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159248288 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_j
tag_state_post_trans.159248288
Directory /workspace/2.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_prog_failure.2095981618
Short name T144
Test name
Test status
Simulation time 119633368 ps
CPU time 1.73 seconds
Started Jun 13 01:41:40 PM PDT 24
Finished Jun 13 01:41:43 PM PDT 24
Peak memory 218220 kb
Host smart-bf70973d-a57a-46fa-bbb1-9beaa2414e8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095981618 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_prog_failure.2095981618
Directory /workspace/2.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_regwen_during_op.1015475986
Short name T415
Test name
Test status
Simulation time 798619480 ps
CPU time 11.31 seconds
Started Jun 13 01:41:42 PM PDT 24
Finished Jun 13 01:41:54 PM PDT 24
Peak memory 214560 kb
Host smart-82737c48-7017-405e-b0fd-15a5f735c6ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015475986 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_regwen_during_op.1015475986
Directory /workspace/2.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_cm.3801486857
Short name T87
Test name
Test status
Simulation time 214182202 ps
CPU time 37.82 seconds
Started Jun 13 01:41:46 PM PDT 24
Finished Jun 13 01:42:25 PM PDT 24
Peak memory 270056 kb
Host smart-42eabab7-429a-4062-bdc5-25f35e4203b8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801486857 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_cm.3801486857
Directory /workspace/2.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_mubi.4226760944
Short name T810
Test name
Test status
Simulation time 3137991400 ps
CPU time 11.19 seconds
Started Jun 13 01:41:47 PM PDT 24
Finished Jun 13 01:41:59 PM PDT 24
Peak memory 219268 kb
Host smart-1cd03242-b697-446c-8607-e60dff835739
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226760944 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_mubi.4226760944
Directory /workspace/2.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_digest.4225180078
Short name T291
Test name
Test status
Simulation time 255226059 ps
CPU time 11.69 seconds
Started Jun 13 01:41:48 PM PDT 24
Finished Jun 13 01:42:00 PM PDT 24
Peak memory 218252 kb
Host smart-dea33e10-0afd-4394-aab1-c88ddeaef00f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225180078 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_di
gest.4225180078
Directory /workspace/2.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_mux.3890373088
Short name T628
Test name
Test status
Simulation time 544558499 ps
CPU time 12.32 seconds
Started Jun 13 01:41:48 PM PDT 24
Finished Jun 13 01:42:01 PM PDT 24
Peak memory 218304 kb
Host smart-c49b76c0-b5e9-458a-b0d8-b0d50cc71c0b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890373088 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_mux.3
890373088
Directory /workspace/2.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/2.lc_ctrl_security_escalation.3867702151
Short name T422
Test name
Test status
Simulation time 3039453907 ps
CPU time 8.57 seconds
Started Jun 13 01:41:45 PM PDT 24
Finished Jun 13 01:41:54 PM PDT 24
Peak memory 218360 kb
Host smart-dec62a56-902e-48f1-9dc7-c1129092fd0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867702151 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_security_escalation.3867702151
Directory /workspace/2.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/2.lc_ctrl_smoke.1036650663
Short name T74
Test name
Test status
Simulation time 27900806 ps
CPU time 2.15 seconds
Started Jun 13 01:41:42 PM PDT 24
Finished Jun 13 01:41:45 PM PDT 24
Peak memory 214320 kb
Host smart-76f55480-3493-4890-be4c-7c2374bd2bce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036650663 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_smoke.1036650663
Directory /workspace/2.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_failure.3254952913
Short name T555
Test name
Test status
Simulation time 313901915 ps
CPU time 25.74 seconds
Started Jun 13 01:41:42 PM PDT 24
Finished Jun 13 01:42:09 PM PDT 24
Peak memory 250904 kb
Host smart-99dedb43-eeda-44ac-b230-21fdb5d8ee27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254952913 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_failure.3254952913
Directory /workspace/2.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_post_trans.695335328
Short name T309
Test name
Test status
Simulation time 321120713 ps
CPU time 3.91 seconds
Started Jun 13 01:41:41 PM PDT 24
Finished Jun 13 01:41:46 PM PDT 24
Peak memory 222156 kb
Host smart-b637cdc3-0f66-49c1-af6c-8396618c1f36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695335328 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_post_trans.695335328
Directory /workspace/2.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all.1141324007
Short name T838
Test name
Test status
Simulation time 2185212818 ps
CPU time 38.38 seconds
Started Jun 13 01:41:47 PM PDT 24
Finished Jun 13 01:42:26 PM PDT 24
Peak memory 246108 kb
Host smart-bace4073-58b4-4671-94e4-6fb60f8b5b0d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141324007 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.lc_ctrl_stress_all.1141324007
Directory /workspace/2.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all_with_rand_reset.550128339
Short name T83
Test name
Test status
Simulation time 95253853417 ps
CPU time 850.3 seconds
Started Jun 13 01:41:48 PM PDT 24
Finished Jun 13 01:55:59 PM PDT 24
Peak memory 316640 kb
Host smart-384d768b-2ce7-41a0-8e29-f823863a03aa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=550128339 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_stress_all_with_rand_reset.550128339
Directory /workspace/2.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.lc_ctrl_volatile_unlock_smoke.3829951626
Short name T453
Test name
Test status
Simulation time 99157566 ps
CPU time 1 seconds
Started Jun 13 01:41:44 PM PDT 24
Finished Jun 13 01:41:46 PM PDT 24
Peak memory 217844 kb
Host smart-ae9105b2-44e2-4fab-a467-b923b9f77f0f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829951626 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ct
rl_volatile_unlock_smoke.3829951626
Directory /workspace/2.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_errors.2003945702
Short name T625
Test name
Test status
Simulation time 2943018480 ps
CPU time 16.17 seconds
Started Jun 13 01:44:03 PM PDT 24
Finished Jun 13 01:44:20 PM PDT 24
Peak memory 218976 kb
Host smart-f356333f-f987-406c-be4e-808adbd14b73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003945702 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_errors.2003945702
Directory /workspace/20.lc_ctrl_errors/latest

Test location /workspace/coverage/default/20.lc_ctrl_jtag_access.3505120765
Short name T497
Test name
Test status
Simulation time 330382203 ps
CPU time 3.71 seconds
Started Jun 13 01:44:02 PM PDT 24
Finished Jun 13 01:44:07 PM PDT 24
Peak memory 217180 kb
Host smart-0ae50041-f547-42d2-943c-2acc23a0a7e0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505120765 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_jtag_access.3505120765
Directory /workspace/20.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/20.lc_ctrl_prog_failure.2907077531
Short name T208
Test name
Test status
Simulation time 645999634 ps
CPU time 3.7 seconds
Started Jun 13 01:44:02 PM PDT 24
Finished Jun 13 01:44:06 PM PDT 24
Peak memory 222736 kb
Host smart-04fc9593-a839-44a9-8df3-d5b63b0bcbb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907077531 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_prog_failure.2907077531
Directory /workspace/20.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_mubi.2277960378
Short name T624
Test name
Test status
Simulation time 5802566540 ps
CPU time 11.22 seconds
Started Jun 13 01:44:03 PM PDT 24
Finished Jun 13 01:44:16 PM PDT 24
Peak memory 218988 kb
Host smart-08b49534-1983-4b50-b7cc-3ca7aa1a6cc1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277960378 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_mubi.2277960378
Directory /workspace/20.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_digest.2294910118
Short name T335
Test name
Test status
Simulation time 436672570 ps
CPU time 11.81 seconds
Started Jun 13 01:44:08 PM PDT 24
Finished Jun 13 01:44:21 PM PDT 24
Peak memory 218252 kb
Host smart-708a0f1f-f987-4619-9614-3fa439248e98
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294910118 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_d
igest.2294910118
Directory /workspace/20.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_mux.1449655127
Short name T297
Test name
Test status
Simulation time 256687278 ps
CPU time 10.61 seconds
Started Jun 13 01:44:04 PM PDT 24
Finished Jun 13 01:44:16 PM PDT 24
Peak memory 218264 kb
Host smart-ed2a811d-ecad-49dd-a689-4789698998a2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449655127 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_mux.
1449655127
Directory /workspace/20.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/20.lc_ctrl_security_escalation.2279968817
Short name T695
Test name
Test status
Simulation time 1794926612 ps
CPU time 16.05 seconds
Started Jun 13 01:44:03 PM PDT 24
Finished Jun 13 01:44:20 PM PDT 24
Peak memory 226032 kb
Host smart-9992baf7-5087-49b0-bfad-e823d571daf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279968817 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_security_escalation.2279968817
Directory /workspace/20.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/20.lc_ctrl_smoke.1725851038
Short name T522
Test name
Test status
Simulation time 158963813 ps
CPU time 2.62 seconds
Started Jun 13 01:44:03 PM PDT 24
Finished Jun 13 01:44:07 PM PDT 24
Peak memory 214448 kb
Host smart-c4f3adfa-efb7-437b-9dde-9e7f550d6090
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725851038 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_smoke.1725851038
Directory /workspace/20.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_failure.3821278780
Short name T857
Test name
Test status
Simulation time 616357589 ps
CPU time 20.39 seconds
Started Jun 13 01:44:04 PM PDT 24
Finished Jun 13 01:44:25 PM PDT 24
Peak memory 250924 kb
Host smart-615c8ac1-e6ae-4fff-9026-cf745e30def5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821278780 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_failure.3821278780
Directory /workspace/20.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_post_trans.3317871657
Short name T145
Test name
Test status
Simulation time 90752981 ps
CPU time 3.62 seconds
Started Jun 13 01:44:04 PM PDT 24
Finished Jun 13 01:44:09 PM PDT 24
Peak memory 222668 kb
Host smart-89219c90-7c06-445c-9f72-44e0b4a5f244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317871657 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_post_trans.3317871657
Directory /workspace/20.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/20.lc_ctrl_stress_all.1985522645
Short name T63
Test name
Test status
Simulation time 62391332345 ps
CPU time 486.17 seconds
Started Jun 13 01:44:08 PM PDT 24
Finished Jun 13 01:52:16 PM PDT 24
Peak memory 252552 kb
Host smart-115a1058-6fc0-4df2-93bf-02924700c58e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985522645 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.lc_ctrl_stress_all.1985522645
Directory /workspace/20.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.lc_ctrl_volatile_unlock_smoke.1629081649
Short name T629
Test name
Test status
Simulation time 30599971 ps
CPU time 0.96 seconds
Started Jun 13 01:44:03 PM PDT 24
Finished Jun 13 01:44:06 PM PDT 24
Peak memory 211992 kb
Host smart-4d9f1c11-f51e-40d6-bdf0-88cbcae4b82f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629081649 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_c
trl_volatile_unlock_smoke.1629081649
Directory /workspace/20.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_alert_test.3921775628
Short name T353
Test name
Test status
Simulation time 36018271 ps
CPU time 1.14 seconds
Started Jun 13 01:44:15 PM PDT 24
Finished Jun 13 01:44:16 PM PDT 24
Peak memory 209100 kb
Host smart-e2b641f2-15c5-4f7b-9d1e-af139931ab2a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921775628 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_alert_test.3921775628
Directory /workspace/21.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.lc_ctrl_errors.2126199924
Short name T160
Test name
Test status
Simulation time 872930492 ps
CPU time 10.99 seconds
Started Jun 13 01:44:11 PM PDT 24
Finished Jun 13 01:44:23 PM PDT 24
Peak memory 218232 kb
Host smart-98aa9937-1fe6-4b7b-87c0-46d8728f72dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126199924 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_errors.2126199924
Directory /workspace/21.lc_ctrl_errors/latest

Test location /workspace/coverage/default/21.lc_ctrl_jtag_access.1070220834
Short name T751
Test name
Test status
Simulation time 164284155 ps
CPU time 4.89 seconds
Started Jun 13 01:44:07 PM PDT 24
Finished Jun 13 01:44:13 PM PDT 24
Peak memory 217056 kb
Host smart-96bddfe7-1c2e-42c6-b130-e0f741213eee
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070220834 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_jtag_access.1070220834
Directory /workspace/21.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/21.lc_ctrl_prog_failure.3630687139
Short name T534
Test name
Test status
Simulation time 107047162 ps
CPU time 2.87 seconds
Started Jun 13 01:44:09 PM PDT 24
Finished Jun 13 01:44:14 PM PDT 24
Peak memory 222480 kb
Host smart-9f3ed3f2-0f59-4b8c-b957-8aa0cae1afb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630687139 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_prog_failure.3630687139
Directory /workspace/21.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_mubi.912388825
Short name T241
Test name
Test status
Simulation time 573120048 ps
CPU time 14.77 seconds
Started Jun 13 01:44:07 PM PDT 24
Finished Jun 13 01:44:23 PM PDT 24
Peak memory 226060 kb
Host smart-88270e63-2b6a-4103-910e-504e23dd8a37
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912388825 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_mubi.912388825
Directory /workspace/21.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_digest.2431080471
Short name T678
Test name
Test status
Simulation time 1791133145 ps
CPU time 15.86 seconds
Started Jun 13 01:44:10 PM PDT 24
Finished Jun 13 01:44:27 PM PDT 24
Peak memory 218212 kb
Host smart-0a9b95cf-2432-45b4-ba4e-d53535fe8260
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431080471 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_d
igest.2431080471
Directory /workspace/21.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_mux.4093121165
Short name T750
Test name
Test status
Simulation time 1711233515 ps
CPU time 12.57 seconds
Started Jun 13 01:44:09 PM PDT 24
Finished Jun 13 01:44:23 PM PDT 24
Peak memory 218236 kb
Host smart-042a0148-4391-48f7-be17-c202b355ca32
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093121165 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_mux.
4093121165
Directory /workspace/21.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/21.lc_ctrl_smoke.369536522
Short name T223
Test name
Test status
Simulation time 107462248 ps
CPU time 2.37 seconds
Started Jun 13 01:44:09 PM PDT 24
Finished Jun 13 01:44:12 PM PDT 24
Peak memory 222736 kb
Host smart-cb18bf0a-3058-4bb1-b666-98f2c6b1bc91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369536522 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_smoke.369536522
Directory /workspace/21.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_failure.3249489966
Short name T295
Test name
Test status
Simulation time 753769882 ps
CPU time 35.73 seconds
Started Jun 13 01:44:07 PM PDT 24
Finished Jun 13 01:44:43 PM PDT 24
Peak memory 250880 kb
Host smart-b2ff8300-4caa-49a3-85b8-542c07aa53ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249489966 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_failure.3249489966
Directory /workspace/21.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_post_trans.3735831778
Short name T698
Test name
Test status
Simulation time 104792792 ps
CPU time 9.92 seconds
Started Jun 13 01:44:08 PM PDT 24
Finished Jun 13 01:44:20 PM PDT 24
Peak memory 250908 kb
Host smart-15adf552-ed75-4105-a16c-68ba2a2adf15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735831778 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_post_trans.3735831778
Directory /workspace/21.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/21.lc_ctrl_stress_all.3335920132
Short name T627
Test name
Test status
Simulation time 4801268338 ps
CPU time 78.77 seconds
Started Jun 13 01:44:11 PM PDT 24
Finished Jun 13 01:45:31 PM PDT 24
Peak memory 250960 kb
Host smart-0fe868fa-e6c3-4d77-938a-885d8b74855c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335920132 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.lc_ctrl_stress_all.3335920132
Directory /workspace/21.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.lc_ctrl_stress_all_with_rand_reset.894999865
Short name T138
Test name
Test status
Simulation time 41453160499 ps
CPU time 124.69 seconds
Started Jun 13 01:44:08 PM PDT 24
Finished Jun 13 01:46:14 PM PDT 24
Peak memory 267464 kb
Host smart-31d5d2b1-0429-4232-be91-992967c07cb4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=894999865 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_stress_all_with_rand_reset.894999865
Directory /workspace/21.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.lc_ctrl_volatile_unlock_smoke.1946130934
Short name T436
Test name
Test status
Simulation time 19233382 ps
CPU time 0.94 seconds
Started Jun 13 01:44:08 PM PDT 24
Finished Jun 13 01:44:10 PM PDT 24
Peak memory 211964 kb
Host smart-e87071f8-759b-4bdb-9bb3-c318258d6588
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946130934 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_c
trl_volatile_unlock_smoke.1946130934
Directory /workspace/21.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_alert_test.2155595660
Short name T526
Test name
Test status
Simulation time 150574128 ps
CPU time 0.93 seconds
Started Jun 13 01:44:22 PM PDT 24
Finished Jun 13 01:44:24 PM PDT 24
Peak memory 209092 kb
Host smart-7763e5b0-e958-428c-9429-f82f4bdccf48
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155595660 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_alert_test.2155595660
Directory /workspace/22.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.lc_ctrl_errors.1245822346
Short name T535
Test name
Test status
Simulation time 320028686 ps
CPU time 9.65 seconds
Started Jun 13 01:44:15 PM PDT 24
Finished Jun 13 01:44:25 PM PDT 24
Peak memory 218288 kb
Host smart-ad4ac169-581f-472d-a83c-5d55e2d158c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245822346 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_errors.1245822346
Directory /workspace/22.lc_ctrl_errors/latest

Test location /workspace/coverage/default/22.lc_ctrl_jtag_access.1034139730
Short name T3
Test name
Test status
Simulation time 2292607545 ps
CPU time 5.31 seconds
Started Jun 13 01:44:15 PM PDT 24
Finished Jun 13 01:44:22 PM PDT 24
Peak memory 217332 kb
Host smart-b635029d-c449-445b-8549-f8c58d27f6f6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034139730 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_jtag_access.1034139730
Directory /workspace/22.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/22.lc_ctrl_prog_failure.1138675993
Short name T832
Test name
Test status
Simulation time 49994669 ps
CPU time 1.82 seconds
Started Jun 13 01:44:15 PM PDT 24
Finished Jun 13 01:44:19 PM PDT 24
Peak memory 218216 kb
Host smart-da478ea6-2f25-43d0-846e-6cabcfc1a918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138675993 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_prog_failure.1138675993
Directory /workspace/22.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_mubi.2681589068
Short name T337
Test name
Test status
Simulation time 422042529 ps
CPU time 11.13 seconds
Started Jun 13 01:44:14 PM PDT 24
Finished Jun 13 01:44:26 PM PDT 24
Peak memory 218364 kb
Host smart-0deedd48-6753-4259-9131-29cdce5d0de4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681589068 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_mubi.2681589068
Directory /workspace/22.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_digest.1409269620
Short name T670
Test name
Test status
Simulation time 2595537033 ps
CPU time 16.13 seconds
Started Jun 13 01:44:17 PM PDT 24
Finished Jun 13 01:44:34 PM PDT 24
Peak memory 218320 kb
Host smart-21ed4a1c-5527-4b73-842c-8f5d9eab42d3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409269620 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_d
igest.1409269620
Directory /workspace/22.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_mux.2468973284
Short name T610
Test name
Test status
Simulation time 361236290 ps
CPU time 13.62 seconds
Started Jun 13 01:44:14 PM PDT 24
Finished Jun 13 01:44:28 PM PDT 24
Peak memory 226068 kb
Host smart-d4a5df82-6d4f-4024-9fc2-c1fbfd72f8c0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468973284 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_mux.
2468973284
Directory /workspace/22.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/22.lc_ctrl_security_escalation.241237881
Short name T681
Test name
Test status
Simulation time 371142175 ps
CPU time 8.77 seconds
Started Jun 13 01:44:16 PM PDT 24
Finished Jun 13 01:44:26 PM PDT 24
Peak memory 218232 kb
Host smart-ed3c9ca5-5abd-411c-b054-63a2e109aad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241237881 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_security_escalation.241237881
Directory /workspace/22.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/22.lc_ctrl_smoke.1909171293
Short name T272
Test name
Test status
Simulation time 125397101 ps
CPU time 1.45 seconds
Started Jun 13 01:44:16 PM PDT 24
Finished Jun 13 01:44:19 PM PDT 24
Peak memory 217796 kb
Host smart-f366947c-a604-40df-bd22-d81deac672b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909171293 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_smoke.1909171293
Directory /workspace/22.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_failure.3858498697
Short name T828
Test name
Test status
Simulation time 337219604 ps
CPU time 29.29 seconds
Started Jun 13 01:44:16 PM PDT 24
Finished Jun 13 01:44:47 PM PDT 24
Peak memory 250912 kb
Host smart-aa408f00-451d-4ff5-b806-5905751b5ea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858498697 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_failure.3858498697
Directory /workspace/22.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_post_trans.1328765409
Short name T673
Test name
Test status
Simulation time 225366438 ps
CPU time 6.17 seconds
Started Jun 13 01:44:16 PM PDT 24
Finished Jun 13 01:44:24 PM PDT 24
Peak memory 246476 kb
Host smart-c305e664-45ef-4c99-b5cb-971b7260aebc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328765409 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_post_trans.1328765409
Directory /workspace/22.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/22.lc_ctrl_stress_all.2642637030
Short name T578
Test name
Test status
Simulation time 5489320912 ps
CPU time 222.96 seconds
Started Jun 13 01:44:16 PM PDT 24
Finished Jun 13 01:48:00 PM PDT 24
Peak memory 282760 kb
Host smart-7b11d9cb-633a-487b-b3b4-0150470aaef0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642637030 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.lc_ctrl_stress_all.2642637030
Directory /workspace/22.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.lc_ctrl_volatile_unlock_smoke.2488277890
Short name T496
Test name
Test status
Simulation time 13553462 ps
CPU time 0.8 seconds
Started Jun 13 01:44:16 PM PDT 24
Finished Jun 13 01:44:18 PM PDT 24
Peak memory 208916 kb
Host smart-295322ec-57e2-44aa-a638-3697e163353a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488277890 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_c
trl_volatile_unlock_smoke.2488277890
Directory /workspace/22.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_alert_test.796368012
Short name T608
Test name
Test status
Simulation time 17975342 ps
CPU time 1.17 seconds
Started Jun 13 01:44:27 PM PDT 24
Finished Jun 13 01:44:29 PM PDT 24
Peak memory 209036 kb
Host smart-0c72fda6-69ff-4141-b18e-063b6f186b60
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796368012 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_alert_test.796368012
Directory /workspace/23.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.lc_ctrl_errors.1938428853
Short name T642
Test name
Test status
Simulation time 1683958107 ps
CPU time 17 seconds
Started Jun 13 01:44:20 PM PDT 24
Finished Jun 13 01:44:38 PM PDT 24
Peak memory 218228 kb
Host smart-73afd751-becb-4633-9030-0a487c1fb30b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1938428853 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_errors.1938428853
Directory /workspace/23.lc_ctrl_errors/latest

Test location /workspace/coverage/default/23.lc_ctrl_jtag_access.48057898
Short name T656
Test name
Test status
Simulation time 2308023991 ps
CPU time 6.47 seconds
Started Jun 13 01:44:21 PM PDT 24
Finished Jun 13 01:44:28 PM PDT 24
Peak memory 217472 kb
Host smart-4e4b5888-9619-4d00-b5d8-e7c82b926773
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48057898 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_jtag_access.48057898
Directory /workspace/23.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/23.lc_ctrl_prog_failure.3388929030
Short name T716
Test name
Test status
Simulation time 53354609 ps
CPU time 3.33 seconds
Started Jun 13 01:44:23 PM PDT 24
Finished Jun 13 01:44:28 PM PDT 24
Peak memory 218256 kb
Host smart-7b3ecbe6-1cd2-4379-8819-b97686d501bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388929030 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_prog_failure.3388929030
Directory /workspace/23.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_mubi.2401770434
Short name T575
Test name
Test status
Simulation time 5591325568 ps
CPU time 17.51 seconds
Started Jun 13 01:44:23 PM PDT 24
Finished Jun 13 01:44:42 PM PDT 24
Peak memory 226160 kb
Host smart-d0247793-fd87-44d2-ad23-5d60544fbc91
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401770434 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_mubi.2401770434
Directory /workspace/23.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_digest.3188270362
Short name T215
Test name
Test status
Simulation time 251083994 ps
CPU time 6.8 seconds
Started Jun 13 01:44:21 PM PDT 24
Finished Jun 13 01:44:28 PM PDT 24
Peak memory 218340 kb
Host smart-16fe2eb2-8fa8-44c7-9754-6d4ac8271c52
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188270362 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_d
igest.3188270362
Directory /workspace/23.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_mux.2588651566
Short name T481
Test name
Test status
Simulation time 325349111 ps
CPU time 8.88 seconds
Started Jun 13 01:44:20 PM PDT 24
Finished Jun 13 01:44:30 PM PDT 24
Peak memory 218256 kb
Host smart-f216066e-2937-4060-be75-5da329707e73
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588651566 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_mux.
2588651566
Directory /workspace/23.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/23.lc_ctrl_security_escalation.1266159068
Short name T427
Test name
Test status
Simulation time 513991702 ps
CPU time 11.9 seconds
Started Jun 13 01:44:28 PM PDT 24
Finished Jun 13 01:44:40 PM PDT 24
Peak memory 218280 kb
Host smart-ad2b012d-94aa-442d-9b22-4d1adbdb2b3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266159068 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_security_escalation.1266159068
Directory /workspace/23.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/23.lc_ctrl_smoke.2766690814
Short name T803
Test name
Test status
Simulation time 13690637 ps
CPU time 1.22 seconds
Started Jun 13 01:44:20 PM PDT 24
Finished Jun 13 01:44:22 PM PDT 24
Peak memory 212256 kb
Host smart-2c8a414b-6c3d-4396-a696-0f11da94d0e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766690814 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_smoke.2766690814
Directory /workspace/23.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_failure.523515410
Short name T414
Test name
Test status
Simulation time 412766335 ps
CPU time 31.23 seconds
Started Jun 13 01:44:26 PM PDT 24
Finished Jun 13 01:44:58 PM PDT 24
Peak memory 250900 kb
Host smart-40c79a0c-1007-4cfc-a04e-6f4c4cf5e2d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523515410 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_failure.523515410
Directory /workspace/23.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_post_trans.67424795
Short name T314
Test name
Test status
Simulation time 63903663 ps
CPU time 5.99 seconds
Started Jun 13 01:44:20 PM PDT 24
Finished Jun 13 01:44:27 PM PDT 24
Peak memory 246684 kb
Host smart-169378fb-6888-4529-ace6-74bfbccdcec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67424795 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_post_trans.67424795
Directory /workspace/23.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all.3184091930
Short name T799
Test name
Test status
Simulation time 4527128699 ps
CPU time 53.89 seconds
Started Jun 13 01:44:23 PM PDT 24
Finished Jun 13 01:45:18 PM PDT 24
Peak memory 251000 kb
Host smart-47520393-1914-4f08-9dfa-ee49475ddfdb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184091930 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.lc_ctrl_stress_all.3184091930
Directory /workspace/23.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all_with_rand_reset.3589551703
Short name T102
Test name
Test status
Simulation time 48325744683 ps
CPU time 270.75 seconds
Started Jun 13 01:44:23 PM PDT 24
Finished Jun 13 01:48:54 PM PDT 24
Peak memory 447432 kb
Host smart-440ffa02-3ab8-4375-b6e7-e95d9c94e902
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3589551703 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_stress_all_with_rand_reset.3589551703
Directory /workspace/23.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.lc_ctrl_volatile_unlock_smoke.2722816129
Short name T430
Test name
Test status
Simulation time 49072732 ps
CPU time 1.03 seconds
Started Jun 13 01:44:22 PM PDT 24
Finished Jun 13 01:44:24 PM PDT 24
Peak memory 211984 kb
Host smart-badb92b8-808e-4223-8710-2ca59fd28254
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722816129 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_c
trl_volatile_unlock_smoke.2722816129
Directory /workspace/23.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_alert_test.4263941354
Short name T862
Test name
Test status
Simulation time 60535334 ps
CPU time 1.07 seconds
Started Jun 13 01:44:26 PM PDT 24
Finished Jun 13 01:44:28 PM PDT 24
Peak memory 208980 kb
Host smart-f42dd02d-4e4e-4370-81d0-74b929324e89
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263941354 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_alert_test.4263941354
Directory /workspace/24.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.lc_ctrl_errors.3573530425
Short name T607
Test name
Test status
Simulation time 321257011 ps
CPU time 15.08 seconds
Started Jun 13 01:44:26 PM PDT 24
Finished Jun 13 01:44:42 PM PDT 24
Peak memory 218220 kb
Host smart-d7f21e10-b827-4094-8203-d2f1f751b896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573530425 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_errors.3573530425
Directory /workspace/24.lc_ctrl_errors/latest

Test location /workspace/coverage/default/24.lc_ctrl_jtag_access.673434150
Short name T22
Test name
Test status
Simulation time 959330776 ps
CPU time 12.5 seconds
Started Jun 13 01:44:21 PM PDT 24
Finished Jun 13 01:44:34 PM PDT 24
Peak memory 217524 kb
Host smart-39e4b7da-b572-4961-8364-d31e9b419690
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673434150 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_jtag_access.673434150
Directory /workspace/24.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/24.lc_ctrl_prog_failure.2031890326
Short name T863
Test name
Test status
Simulation time 155150549 ps
CPU time 2.63 seconds
Started Jun 13 01:44:21 PM PDT 24
Finished Jun 13 01:44:25 PM PDT 24
Peak memory 222300 kb
Host smart-b8a56b3c-3503-45fd-a421-a6eda4a5c317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031890326 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_prog_failure.2031890326
Directory /workspace/24.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_mubi.4183835769
Short name T684
Test name
Test status
Simulation time 610204169 ps
CPU time 15.9 seconds
Started Jun 13 01:44:28 PM PDT 24
Finished Jun 13 01:44:45 PM PDT 24
Peak memory 226084 kb
Host smart-e0b506b3-e316-442a-ae04-8748127510c2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183835769 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_mubi.4183835769
Directory /workspace/24.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_digest.829125643
Short name T648
Test name
Test status
Simulation time 1703969486 ps
CPU time 7.88 seconds
Started Jun 13 01:44:30 PM PDT 24
Finished Jun 13 01:44:38 PM PDT 24
Peak memory 226040 kb
Host smart-39e13ad2-4f44-491b-b5cf-e9f7ca04d07f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829125643 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_di
gest.829125643
Directory /workspace/24.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_mux.3412698552
Short name T245
Test name
Test status
Simulation time 400255331 ps
CPU time 7.86 seconds
Started Jun 13 01:44:27 PM PDT 24
Finished Jun 13 01:44:36 PM PDT 24
Peak memory 224992 kb
Host smart-82897f69-1d01-4305-b0d7-7013a85040fb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412698552 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_mux.
3412698552
Directory /workspace/24.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/24.lc_ctrl_security_escalation.727745592
Short name T631
Test name
Test status
Simulation time 1142630443 ps
CPU time 9.19 seconds
Started Jun 13 01:44:27 PM PDT 24
Finished Jun 13 01:44:37 PM PDT 24
Peak memory 225340 kb
Host smart-e7a6dc3c-d346-49b8-860a-7829464daa5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727745592 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_security_escalation.727745592
Directory /workspace/24.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/24.lc_ctrl_smoke.903901570
Short name T500
Test name
Test status
Simulation time 393926656 ps
CPU time 3.16 seconds
Started Jun 13 01:44:21 PM PDT 24
Finished Jun 13 01:44:25 PM PDT 24
Peak memory 217760 kb
Host smart-ff4965f8-4dd3-4036-b653-ef5e1771d17c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903901570 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_smoke.903901570
Directory /workspace/24.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_failure.2641134607
Short name T244
Test name
Test status
Simulation time 249635916 ps
CPU time 26.18 seconds
Started Jun 13 01:44:26 PM PDT 24
Finished Jun 13 01:44:53 PM PDT 24
Peak memory 250772 kb
Host smart-0fa56b08-f821-44a4-93f2-08b66be5a2e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641134607 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_failure.2641134607
Directory /workspace/24.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_post_trans.1324204722
Short name T455
Test name
Test status
Simulation time 85841429 ps
CPU time 7.29 seconds
Started Jun 13 01:44:27 PM PDT 24
Finished Jun 13 01:44:35 PM PDT 24
Peak memory 245972 kb
Host smart-3bf02ebc-73eb-46f8-9ccd-feabdfd8cd72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324204722 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_post_trans.1324204722
Directory /workspace/24.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all.387881017
Short name T379
Test name
Test status
Simulation time 15932521038 ps
CPU time 126.94 seconds
Started Jun 13 01:44:29 PM PDT 24
Finished Jun 13 01:46:36 PM PDT 24
Peak memory 250780 kb
Host smart-d5c74d0d-6e2f-4af9-b1a6-c269e81a7371
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387881017 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.lc_ctrl_stress_all.387881017
Directory /workspace/24.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.lc_ctrl_volatile_unlock_smoke.807570158
Short name T732
Test name
Test status
Simulation time 104375959 ps
CPU time 0.83 seconds
Started Jun 13 01:44:22 PM PDT 24
Finished Jun 13 01:44:23 PM PDT 24
Peak memory 208236 kb
Host smart-83fd99be-17c4-4ed6-a7b0-ec971e516253
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807570158 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ct
rl_volatile_unlock_smoke.807570158
Directory /workspace/24.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_alert_test.1601533314
Short name T329
Test name
Test status
Simulation time 55266427 ps
CPU time 1.09 seconds
Started Jun 13 01:44:33 PM PDT 24
Finished Jun 13 01:44:34 PM PDT 24
Peak memory 209040 kb
Host smart-7e446de8-c009-48be-a54c-027ad01fd3e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601533314 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_alert_test.1601533314
Directory /workspace/25.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.lc_ctrl_errors.445989598
Short name T813
Test name
Test status
Simulation time 535957431 ps
CPU time 10.76 seconds
Started Jun 13 01:44:34 PM PDT 24
Finished Jun 13 01:44:45 PM PDT 24
Peak memory 218200 kb
Host smart-115a5f1a-bd8f-4340-b192-4914144589a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445989598 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_errors.445989598
Directory /workspace/25.lc_ctrl_errors/latest

Test location /workspace/coverage/default/25.lc_ctrl_jtag_access.387577020
Short name T358
Test name
Test status
Simulation time 194914407 ps
CPU time 3.94 seconds
Started Jun 13 01:44:37 PM PDT 24
Finished Jun 13 01:44:41 PM PDT 24
Peak memory 217204 kb
Host smart-e2dfba98-0a24-4bdb-9533-a931b8a62a1f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387577020 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_jtag_access.387577020
Directory /workspace/25.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/25.lc_ctrl_prog_failure.806971314
Short name T542
Test name
Test status
Simulation time 182491530 ps
CPU time 1.88 seconds
Started Jun 13 01:44:34 PM PDT 24
Finished Jun 13 01:44:37 PM PDT 24
Peak memory 218220 kb
Host smart-0e811555-6644-4d09-bd1b-d028efaeff18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806971314 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_prog_failure.806971314
Directory /workspace/25.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_mubi.1694114189
Short name T652
Test name
Test status
Simulation time 826155612 ps
CPU time 18.78 seconds
Started Jun 13 01:44:34 PM PDT 24
Finished Jun 13 01:44:53 PM PDT 24
Peak memory 218932 kb
Host smart-55f696eb-3756-4c93-8b9f-d741ff641c78
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694114189 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_mubi.1694114189
Directory /workspace/25.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_digest.1521755290
Short name T613
Test name
Test status
Simulation time 632706081 ps
CPU time 16 seconds
Started Jun 13 01:44:33 PM PDT 24
Finished Jun 13 01:44:50 PM PDT 24
Peak memory 226060 kb
Host smart-119c1f80-d015-474b-ab0c-851514f84069
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521755290 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_d
igest.1521755290
Directory /workspace/25.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_mux.2790391031
Short name T573
Test name
Test status
Simulation time 786042416 ps
CPU time 10.99 seconds
Started Jun 13 01:44:33 PM PDT 24
Finished Jun 13 01:44:45 PM PDT 24
Peak memory 218244 kb
Host smart-d9050fd3-2356-4af7-b7cf-74b228dc4d97
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790391031 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_mux.
2790391031
Directory /workspace/25.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/25.lc_ctrl_security_escalation.3121084414
Short name T593
Test name
Test status
Simulation time 4413662078 ps
CPU time 11.03 seconds
Started Jun 13 01:44:36 PM PDT 24
Finished Jun 13 01:44:47 PM PDT 24
Peak memory 218360 kb
Host smart-e26a8b9d-478b-424b-a844-d0bd582204bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121084414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_security_escalation.3121084414
Directory /workspace/25.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/25.lc_ctrl_smoke.1184498908
Short name T413
Test name
Test status
Simulation time 35724007 ps
CPU time 1.86 seconds
Started Jun 13 01:44:26 PM PDT 24
Finished Jun 13 01:44:29 PM PDT 24
Peak memory 214220 kb
Host smart-45161d55-e6d8-4607-97b1-c5e907b09895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184498908 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_smoke.1184498908
Directory /workspace/25.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_failure.3577476036
Short name T701
Test name
Test status
Simulation time 704915942 ps
CPU time 16.46 seconds
Started Jun 13 01:44:26 PM PDT 24
Finished Jun 13 01:44:43 PM PDT 24
Peak memory 250980 kb
Host smart-c1040b46-3b1d-4f28-82c3-8a0b0e11edfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577476036 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_failure.3577476036
Directory /workspace/25.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_post_trans.3680327876
Short name T235
Test name
Test status
Simulation time 372114402 ps
CPU time 3.59 seconds
Started Jun 13 01:44:28 PM PDT 24
Finished Jun 13 01:44:32 PM PDT 24
Peak memory 221968 kb
Host smart-00e89697-8148-44c6-99ed-72752da3f898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680327876 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_post_trans.3680327876
Directory /workspace/25.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/25.lc_ctrl_stress_all.3746835299
Short name T675
Test name
Test status
Simulation time 5573817434 ps
CPU time 87.58 seconds
Started Jun 13 01:44:34 PM PDT 24
Finished Jun 13 01:46:02 PM PDT 24
Peak memory 272596 kb
Host smart-20776f49-06af-4e56-a00c-4789cd590942
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746835299 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.lc_ctrl_stress_all.3746835299
Directory /workspace/25.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.lc_ctrl_volatile_unlock_smoke.1835978076
Short name T289
Test name
Test status
Simulation time 14571952 ps
CPU time 0.81 seconds
Started Jun 13 01:44:47 PM PDT 24
Finished Jun 13 01:44:49 PM PDT 24
Peak memory 208924 kb
Host smart-0eaf85d3-61df-4db7-95d7-fce0c3fda54e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835978076 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_c
trl_volatile_unlock_smoke.1835978076
Directory /workspace/25.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_alert_test.1521671231
Short name T761
Test name
Test status
Simulation time 23014023 ps
CPU time 0.95 seconds
Started Jun 13 01:44:39 PM PDT 24
Finished Jun 13 01:44:41 PM PDT 24
Peak memory 208988 kb
Host smart-d448c68b-fbea-4a76-9658-73092fbcec39
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521671231 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_alert_test.1521671231
Directory /workspace/26.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.lc_ctrl_errors.717707832
Short name T643
Test name
Test status
Simulation time 158510141 ps
CPU time 8.27 seconds
Started Jun 13 01:44:39 PM PDT 24
Finished Jun 13 01:44:48 PM PDT 24
Peak memory 218224 kb
Host smart-67fd1da1-8845-4b57-9b30-cd8a66c59953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717707832 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_errors.717707832
Directory /workspace/26.lc_ctrl_errors/latest

Test location /workspace/coverage/default/26.lc_ctrl_jtag_access.1153040794
Short name T871
Test name
Test status
Simulation time 304697678 ps
CPU time 4.26 seconds
Started Jun 13 01:44:34 PM PDT 24
Finished Jun 13 01:44:39 PM PDT 24
Peak memory 217464 kb
Host smart-771c205a-7ca6-4206-9cab-ffe139e8831f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153040794 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_jtag_access.1153040794
Directory /workspace/26.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/26.lc_ctrl_prog_failure.4183755079
Short name T641
Test name
Test status
Simulation time 483848708 ps
CPU time 5.46 seconds
Started Jun 13 01:44:34 PM PDT 24
Finished Jun 13 01:44:40 PM PDT 24
Peak memory 218196 kb
Host smart-7958d45e-99dc-4fb4-9e84-2b6bcaf60f1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183755079 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_prog_failure.4183755079
Directory /workspace/26.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_mubi.2829917619
Short name T341
Test name
Test status
Simulation time 5716730121 ps
CPU time 18.49 seconds
Started Jun 13 01:44:34 PM PDT 24
Finished Jun 13 01:44:53 PM PDT 24
Peak memory 226160 kb
Host smart-83b877ad-b45d-4dd4-946e-c005e10692c9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829917619 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_mubi.2829917619
Directory /workspace/26.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_digest.487985402
Short name T508
Test name
Test status
Simulation time 290999051 ps
CPU time 7.89 seconds
Started Jun 13 01:44:41 PM PDT 24
Finished Jun 13 01:44:50 PM PDT 24
Peak memory 218256 kb
Host smart-17c2118e-974a-4e2f-8865-55cde75a38e3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487985402 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_di
gest.487985402
Directory /workspace/26.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_mux.1132979664
Short name T595
Test name
Test status
Simulation time 316272866 ps
CPU time 7.26 seconds
Started Jun 13 01:44:32 PM PDT 24
Finished Jun 13 01:44:39 PM PDT 24
Peak memory 218256 kb
Host smart-eb12edfb-ab88-4f37-8522-08e3385941ac
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132979664 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_mux.
1132979664
Directory /workspace/26.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/26.lc_ctrl_security_escalation.2476957600
Short name T4
Test name
Test status
Simulation time 497290626 ps
CPU time 17.94 seconds
Started Jun 13 01:44:33 PM PDT 24
Finished Jun 13 01:44:51 PM PDT 24
Peak memory 225196 kb
Host smart-ffc7fdd9-6838-40e0-9b95-634c38b07a97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476957600 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_security_escalation.2476957600
Directory /workspace/26.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/26.lc_ctrl_smoke.3953016654
Short name T225
Test name
Test status
Simulation time 169899367 ps
CPU time 1.33 seconds
Started Jun 13 01:44:34 PM PDT 24
Finished Jun 13 01:44:36 PM PDT 24
Peak memory 217760 kb
Host smart-b082fbe6-6a8e-4103-8c96-c8b48af375f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953016654 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_smoke.3953016654
Directory /workspace/26.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_failure.1362503605
Short name T206
Test name
Test status
Simulation time 2712284354 ps
CPU time 22.28 seconds
Started Jun 13 01:44:35 PM PDT 24
Finished Jun 13 01:44:58 PM PDT 24
Peak memory 250956 kb
Host smart-592aa569-ba47-4ced-b732-818e8f7c6cd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362503605 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_failure.1362503605
Directory /workspace/26.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_post_trans.3903456507
Short name T318
Test name
Test status
Simulation time 78696725 ps
CPU time 6.59 seconds
Started Jun 13 01:44:33 PM PDT 24
Finished Jun 13 01:44:41 PM PDT 24
Peak memory 250924 kb
Host smart-5bd8c0d6-bbc7-4df5-9abe-c3698a99577f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903456507 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_post_trans.3903456507
Directory /workspace/26.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/26.lc_ctrl_volatile_unlock_smoke.3395608072
Short name T784
Test name
Test status
Simulation time 13832450 ps
CPU time 1.15 seconds
Started Jun 13 01:44:34 PM PDT 24
Finished Jun 13 01:44:36 PM PDT 24
Peak memory 212048 kb
Host smart-1162e644-8bc1-4fbe-bed3-bca1964479e2
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395608072 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_c
trl_volatile_unlock_smoke.3395608072
Directory /workspace/26.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_alert_test.684509622
Short name T158
Test name
Test status
Simulation time 23316874 ps
CPU time 0.98 seconds
Started Jun 13 01:44:42 PM PDT 24
Finished Jun 13 01:44:43 PM PDT 24
Peak memory 209036 kb
Host smart-cda692ce-1e7e-4a55-9785-af507d4181e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684509622 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_alert_test.684509622
Directory /workspace/27.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.lc_ctrl_errors.2889939189
Short name T371
Test name
Test status
Simulation time 2465834760 ps
CPU time 23.31 seconds
Started Jun 13 01:44:43 PM PDT 24
Finished Jun 13 01:45:07 PM PDT 24
Peak memory 218980 kb
Host smart-09142825-ad22-48f3-9615-38213a71f7eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889939189 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_errors.2889939189
Directory /workspace/27.lc_ctrl_errors/latest

Test location /workspace/coverage/default/27.lc_ctrl_jtag_access.1774505778
Short name T424
Test name
Test status
Simulation time 1758853538 ps
CPU time 23.39 seconds
Started Jun 13 01:44:39 PM PDT 24
Finished Jun 13 01:45:03 PM PDT 24
Peak memory 217312 kb
Host smart-9ce9f551-9b71-4b82-bbbe-0cc48d68f6a3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774505778 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_jtag_access.1774505778
Directory /workspace/27.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/27.lc_ctrl_prog_failure.1189106279
Short name T323
Test name
Test status
Simulation time 101694582 ps
CPU time 2.12 seconds
Started Jun 13 01:44:39 PM PDT 24
Finished Jun 13 01:44:42 PM PDT 24
Peak memory 218236 kb
Host smart-f87c153a-93c8-4375-8fbc-ed7e0a03e733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189106279 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_prog_failure.1189106279
Directory /workspace/27.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_digest.1980684466
Short name T327
Test name
Test status
Simulation time 565086895 ps
CPU time 22.98 seconds
Started Jun 13 01:44:42 PM PDT 24
Finished Jun 13 01:45:06 PM PDT 24
Peak memory 218264 kb
Host smart-8a93b648-af67-46b1-8888-c32c63e4db1f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980684466 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_d
igest.1980684466
Directory /workspace/27.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_mux.2023798049
Short name T736
Test name
Test status
Simulation time 2155150737 ps
CPU time 11.57 seconds
Started Jun 13 01:44:43 PM PDT 24
Finished Jun 13 01:44:55 PM PDT 24
Peak memory 218320 kb
Host smart-e875e3b2-c7bb-4f7b-bfcf-6eedaa291256
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023798049 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_mux.
2023798049
Directory /workspace/27.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/27.lc_ctrl_security_escalation.1263764648
Short name T563
Test name
Test status
Simulation time 1605896602 ps
CPU time 8.61 seconds
Started Jun 13 01:44:40 PM PDT 24
Finished Jun 13 01:44:49 PM PDT 24
Peak memory 224784 kb
Host smart-f7c14874-5df1-4a7b-b04b-1ebfa0432c2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263764648 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_security_escalation.1263764648
Directory /workspace/27.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/27.lc_ctrl_smoke.3876803135
Short name T14
Test name
Test status
Simulation time 43286015 ps
CPU time 1.1 seconds
Started Jun 13 01:44:38 PM PDT 24
Finished Jun 13 01:44:40 PM PDT 24
Peak memory 212284 kb
Host smart-3c0feff1-2fae-4d0e-9dd5-8ac5189560f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876803135 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_smoke.3876803135
Directory /workspace/27.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_failure.2123429504
Short name T601
Test name
Test status
Simulation time 587814462 ps
CPU time 29.96 seconds
Started Jun 13 01:44:42 PM PDT 24
Finished Jun 13 01:45:12 PM PDT 24
Peak memory 250944 kb
Host smart-268d32d2-d72f-48c0-a1e5-d5f074594afa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123429504 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_failure.2123429504
Directory /workspace/27.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_post_trans.2505620306
Short name T383
Test name
Test status
Simulation time 289161988 ps
CPU time 7.46 seconds
Started Jun 13 01:44:39 PM PDT 24
Finished Jun 13 01:44:47 PM PDT 24
Peak memory 250476 kb
Host smart-f31c6a77-fad6-4831-8e15-1d92efcfe77d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505620306 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_post_trans.2505620306
Directory /workspace/27.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all.3825630101
Short name T512
Test name
Test status
Simulation time 35767414744 ps
CPU time 661.43 seconds
Started Jun 13 01:44:39 PM PDT 24
Finished Jun 13 01:55:41 PM PDT 24
Peak memory 272856 kb
Host smart-dba4e4e3-293c-4a6c-834a-9e0af54afb79
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825630101 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.lc_ctrl_stress_all.3825630101
Directory /workspace/27.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all_with_rand_reset.1698182752
Short name T101
Test name
Test status
Simulation time 904540360972 ps
CPU time 1665.91 seconds
Started Jun 13 01:44:42 PM PDT 24
Finished Jun 13 02:12:28 PM PDT 24
Peak memory 791824 kb
Host smart-998cc590-8265-45a6-ba20-e296ee6e2566
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1698182752 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_stress_all_with_rand_reset.1698182752
Directory /workspace/27.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.lc_ctrl_volatile_unlock_smoke.2088138887
Short name T469
Test name
Test status
Simulation time 29927542 ps
CPU time 0.83 seconds
Started Jun 13 01:44:40 PM PDT 24
Finished Jun 13 01:44:42 PM PDT 24
Peak memory 208292 kb
Host smart-2a497321-c2b2-40da-ab4d-0482dca048df
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088138887 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_c
trl_volatile_unlock_smoke.2088138887
Directory /workspace/27.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_alert_test.1698877129
Short name T378
Test name
Test status
Simulation time 31419238 ps
CPU time 1.11 seconds
Started Jun 13 01:44:45 PM PDT 24
Finished Jun 13 01:44:47 PM PDT 24
Peak memory 209032 kb
Host smart-2246cdc8-b5e0-4e3a-9ddf-740fcace7eee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698877129 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_alert_test.1698877129
Directory /workspace/28.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.lc_ctrl_errors.2985429665
Short name T147
Test name
Test status
Simulation time 328460313 ps
CPU time 16.16 seconds
Started Jun 13 01:44:47 PM PDT 24
Finished Jun 13 01:45:04 PM PDT 24
Peak memory 218132 kb
Host smart-8ea4535d-3514-418f-9621-8bfa7a14fffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985429665 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_errors.2985429665
Directory /workspace/28.lc_ctrl_errors/latest

Test location /workspace/coverage/default/28.lc_ctrl_jtag_access.4002801856
Short name T5
Test name
Test status
Simulation time 369197956 ps
CPU time 5.66 seconds
Started Jun 13 01:44:48 PM PDT 24
Finished Jun 13 01:44:54 PM PDT 24
Peak memory 217424 kb
Host smart-ed32b05c-9568-4b1d-8c76-83ca31ba20ee
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002801856 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_jtag_access.4002801856
Directory /workspace/28.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/28.lc_ctrl_prog_failure.447284177
Short name T852
Test name
Test status
Simulation time 60252470 ps
CPU time 2.71 seconds
Started Jun 13 01:44:49 PM PDT 24
Finished Jun 13 01:44:52 PM PDT 24
Peak memory 218220 kb
Host smart-cb6a9415-dadc-45fa-9145-63293c059057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447284177 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_prog_failure.447284177
Directory /workspace/28.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_mubi.1566925862
Short name T646
Test name
Test status
Simulation time 960122130 ps
CPU time 14.04 seconds
Started Jun 13 01:44:46 PM PDT 24
Finished Jun 13 01:45:01 PM PDT 24
Peak memory 218964 kb
Host smart-f104800c-58d6-4bec-b66b-4fffcdbd1bb6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566925862 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_mubi.1566925862
Directory /workspace/28.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_digest.3018027577
Short name T218
Test name
Test status
Simulation time 1789436673 ps
CPU time 17.77 seconds
Started Jun 13 01:44:51 PM PDT 24
Finished Jun 13 01:45:10 PM PDT 24
Peak memory 218256 kb
Host smart-227aa9ea-31c6-4b8a-875d-dd72b9c0e4e5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018027577 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_d
igest.3018027577
Directory /workspace/28.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_mux.244271661
Short name T734
Test name
Test status
Simulation time 333422253 ps
CPU time 13.37 seconds
Started Jun 13 01:44:46 PM PDT 24
Finished Jun 13 01:45:00 PM PDT 24
Peak memory 226072 kb
Host smart-7b7b0174-d632-4e99-8685-709941096a57
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244271661 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_mux.244271661
Directory /workspace/28.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/28.lc_ctrl_security_escalation.1305558370
Short name T770
Test name
Test status
Simulation time 300579436 ps
CPU time 9.64 seconds
Started Jun 13 01:44:47 PM PDT 24
Finished Jun 13 01:44:57 PM PDT 24
Peak memory 218264 kb
Host smart-0954959a-6677-4b02-95a6-24b8ebb10fb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305558370 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_security_escalation.1305558370
Directory /workspace/28.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/28.lc_ctrl_smoke.1532172755
Short name T859
Test name
Test status
Simulation time 112404635 ps
CPU time 2.85 seconds
Started Jun 13 01:44:41 PM PDT 24
Finished Jun 13 01:44:44 PM PDT 24
Peak memory 214588 kb
Host smart-eae81679-fb20-412c-b0f6-8cef01462b78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532172755 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_smoke.1532172755
Directory /workspace/28.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_failure.3269539404
Short name T418
Test name
Test status
Simulation time 917349744 ps
CPU time 30.21 seconds
Started Jun 13 01:44:37 PM PDT 24
Finished Jun 13 01:45:08 PM PDT 24
Peak memory 250880 kb
Host smart-8778f13e-825d-4f84-9bf3-4e9c15a477c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269539404 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_failure.3269539404
Directory /workspace/28.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_post_trans.1701223795
Short name T476
Test name
Test status
Simulation time 107047875 ps
CPU time 6.98 seconds
Started Jun 13 01:44:49 PM PDT 24
Finished Jun 13 01:44:56 PM PDT 24
Peak memory 250912 kb
Host smart-5fada3f8-084f-4dcf-8167-665a43814d41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701223795 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_post_trans.1701223795
Directory /workspace/28.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/28.lc_ctrl_stress_all.3989060385
Short name T717
Test name
Test status
Simulation time 1664793515 ps
CPU time 64.4 seconds
Started Jun 13 01:44:46 PM PDT 24
Finished Jun 13 01:45:51 PM PDT 24
Peak memory 250900 kb
Host smart-a14cd9f9-cef1-4be3-a71a-902001dbb51a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989060385 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.lc_ctrl_stress_all.3989060385
Directory /workspace/28.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.lc_ctrl_volatile_unlock_smoke.2773635339
Short name T71
Test name
Test status
Simulation time 12722178 ps
CPU time 1.13 seconds
Started Jun 13 01:44:38 PM PDT 24
Finished Jun 13 01:44:39 PM PDT 24
Peak memory 212080 kb
Host smart-7bea4604-f8d4-496e-985d-158f16fa4d68
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773635339 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_c
trl_volatile_unlock_smoke.2773635339
Directory /workspace/28.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_alert_test.1279587256
Short name T621
Test name
Test status
Simulation time 40514311 ps
CPU time 0.98 seconds
Started Jun 13 01:44:51 PM PDT 24
Finished Jun 13 01:44:53 PM PDT 24
Peak memory 209028 kb
Host smart-69ef03e6-011d-446b-8948-9176dd368448
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279587256 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_alert_test.1279587256
Directory /workspace/29.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.lc_ctrl_errors.1078205859
Short name T781
Test name
Test status
Simulation time 6852674596 ps
CPU time 11.9 seconds
Started Jun 13 01:44:47 PM PDT 24
Finished Jun 13 01:44:59 PM PDT 24
Peak memory 218576 kb
Host smart-b35a21a1-ffd4-4ff8-8dc5-b2445510b2ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078205859 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_errors.1078205859
Directory /workspace/29.lc_ctrl_errors/latest

Test location /workspace/coverage/default/29.lc_ctrl_jtag_access.421244433
Short name T653
Test name
Test status
Simulation time 178561674 ps
CPU time 2.92 seconds
Started Jun 13 01:44:51 PM PDT 24
Finished Jun 13 01:44:55 PM PDT 24
Peak memory 217160 kb
Host smart-4c7afa3a-76c0-49fe-807a-fe43db33afdf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421244433 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_jtag_access.421244433
Directory /workspace/29.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/29.lc_ctrl_prog_failure.739057007
Short name T149
Test name
Test status
Simulation time 81019828 ps
CPU time 3.59 seconds
Started Jun 13 01:44:46 PM PDT 24
Finished Jun 13 01:44:50 PM PDT 24
Peak memory 218220 kb
Host smart-0f93ccb4-90d1-4369-a987-9464a3a21517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739057007 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_prog_failure.739057007
Directory /workspace/29.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_mubi.690444226
Short name T744
Test name
Test status
Simulation time 468990597 ps
CPU time 13.99 seconds
Started Jun 13 01:44:47 PM PDT 24
Finished Jun 13 01:45:01 PM PDT 24
Peak memory 218280 kb
Host smart-327066d6-369d-4668-8d9b-442f83f3301a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690444226 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_mubi.690444226
Directory /workspace/29.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_digest.3663079980
Short name T348
Test name
Test status
Simulation time 436443894 ps
CPU time 16.6 seconds
Started Jun 13 01:44:45 PM PDT 24
Finished Jun 13 01:45:02 PM PDT 24
Peak memory 218300 kb
Host smart-c7975e0c-508b-4503-8261-379032a0a729
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663079980 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_d
igest.3663079980
Directory /workspace/29.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_mux.1560501126
Short name T267
Test name
Test status
Simulation time 822855933 ps
CPU time 6.13 seconds
Started Jun 13 01:44:45 PM PDT 24
Finished Jun 13 01:44:51 PM PDT 24
Peak memory 224732 kb
Host smart-b21feda5-5c93-4097-9d67-2590066e2740
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560501126 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_mux.
1560501126
Directory /workspace/29.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/29.lc_ctrl_security_escalation.3978365155
Short name T817
Test name
Test status
Simulation time 2459487036 ps
CPU time 18.51 seconds
Started Jun 13 01:44:45 PM PDT 24
Finished Jun 13 01:45:04 PM PDT 24
Peak memory 226096 kb
Host smart-2672b9d3-14a4-44d1-a8a1-6a5d0407f20e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978365155 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_security_escalation.3978365155
Directory /workspace/29.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/29.lc_ctrl_smoke.3646988344
Short name T70
Test name
Test status
Simulation time 391337718 ps
CPU time 3.16 seconds
Started Jun 13 01:44:46 PM PDT 24
Finished Jun 13 01:44:50 PM PDT 24
Peak memory 217736 kb
Host smart-7a58aea5-53af-4a9a-bb17-db7b21b3e1bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646988344 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_smoke.3646988344
Directory /workspace/29.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_failure.1864997982
Short name T785
Test name
Test status
Simulation time 282395392 ps
CPU time 31.75 seconds
Started Jun 13 01:44:48 PM PDT 24
Finished Jun 13 01:45:20 PM PDT 24
Peak memory 250908 kb
Host smart-ef869284-4dec-475b-a91e-8b793933c03f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864997982 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_failure.1864997982
Directory /workspace/29.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_post_trans.1579937146
Short name T581
Test name
Test status
Simulation time 63720955 ps
CPU time 6.98 seconds
Started Jun 13 01:44:48 PM PDT 24
Finished Jun 13 01:44:55 PM PDT 24
Peak memory 246276 kb
Host smart-bb03b291-5e3e-45c9-b9b2-c27b0d37cac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579937146 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_post_trans.1579937146
Directory /workspace/29.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/29.lc_ctrl_stress_all.711959329
Short name T548
Test name
Test status
Simulation time 9819034300 ps
CPU time 153.58 seconds
Started Jun 13 01:44:45 PM PDT 24
Finished Jun 13 01:47:20 PM PDT 24
Peak memory 283784 kb
Host smart-02b6e157-5254-4468-8836-a1c3ef320597
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711959329 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.lc_ctrl_stress_all.711959329
Directory /workspace/29.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.lc_ctrl_volatile_unlock_smoke.3438835226
Short name T618
Test name
Test status
Simulation time 14065255 ps
CPU time 0.78 seconds
Started Jun 13 01:44:48 PM PDT 24
Finished Jun 13 01:44:49 PM PDT 24
Peak memory 208920 kb
Host smart-f8a5c507-666b-4e14-a643-1705f2db2d88
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438835226 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_c
trl_volatile_unlock_smoke.3438835226
Directory /workspace/29.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_alert_test.3768111512
Short name T432
Test name
Test status
Simulation time 17938922 ps
CPU time 0.88 seconds
Started Jun 13 01:41:50 PM PDT 24
Finished Jun 13 01:41:52 PM PDT 24
Peak memory 208964 kb
Host smart-7e894a32-e672-4e8a-9e14-523834e8ae6b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768111512 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_alert_test.3768111512
Directory /workspace/3.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.lc_ctrl_errors.2221201072
Short name T395
Test name
Test status
Simulation time 1374150556 ps
CPU time 11.34 seconds
Started Jun 13 01:41:50 PM PDT 24
Finished Jun 13 01:42:03 PM PDT 24
Peak memory 218232 kb
Host smart-8ec7396f-0015-4da2-9de3-dc41de8ce5e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221201072 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_errors.2221201072
Directory /workspace/3.lc_ctrl_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_access.1849522895
Short name T23
Test name
Test status
Simulation time 1668162497 ps
CPU time 5.47 seconds
Started Jun 13 01:41:54 PM PDT 24
Finished Jun 13 01:42:00 PM PDT 24
Peak memory 217400 kb
Host smart-4be2e1c8-f633-454a-998e-1e4854d43a7d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849522895 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_access.1849522895
Directory /workspace/3.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_errors.1462423987
Short name T288
Test name
Test status
Simulation time 2297415402 ps
CPU time 62.44 seconds
Started Jun 13 01:41:51 PM PDT 24
Finished Jun 13 01:42:55 PM PDT 24
Peak memory 218240 kb
Host smart-de051f3c-ee52-4627-ab69-d7160224d0c5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462423987 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_er
rors.1462423987
Directory /workspace/3.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_priority.3613253526
Short name T790
Test name
Test status
Simulation time 93594064 ps
CPU time 1.9 seconds
Started Jun 13 01:41:51 PM PDT 24
Finished Jun 13 01:41:54 PM PDT 24
Peak memory 217436 kb
Host smart-563ea153-6e19-4892-804f-cb730ad255d9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613253526 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_priority.3
613253526
Directory /workspace/3.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_prog_failure.2920225143
Short name T765
Test name
Test status
Simulation time 145887969 ps
CPU time 3.25 seconds
Started Jun 13 01:41:51 PM PDT 24
Finished Jun 13 01:41:56 PM PDT 24
Peak memory 218192 kb
Host smart-910bb703-0ea3-4a62-9add-f34663170c74
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920225143 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag
_prog_failure.2920225143
Directory /workspace/3.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_regwen_during_op.2824805525
Short name T605
Test name
Test status
Simulation time 3341515696 ps
CPU time 21.39 seconds
Started Jun 13 01:41:52 PM PDT 24
Finished Jun 13 01:42:14 PM PDT 24
Peak memory 217744 kb
Host smart-fcd21c91-894c-46b4-bde8-705467794552
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824805525 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_regwen_during_op.2824805525
Directory /workspace/3.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_smoke.2781966419
Short name T262
Test name
Test status
Simulation time 1156296742 ps
CPU time 4.19 seconds
Started Jun 13 01:41:50 PM PDT 24
Finished Jun 13 01:41:56 PM PDT 24
Peak memory 217688 kb
Host smart-0115d886-439a-4df8-9c63-0836e298b52b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781966419 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_smoke.
2781966419
Directory /workspace/3.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_failure.849551938
Short name T841
Test name
Test status
Simulation time 2294347195 ps
CPU time 37.98 seconds
Started Jun 13 01:41:47 PM PDT 24
Finished Jun 13 01:42:26 PM PDT 24
Peak memory 275472 kb
Host smart-19d173bd-6985-40ff-884b-150316dd76d5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849551938 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag
_state_failure.849551938
Directory /workspace/3.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_post_trans.1750782689
Short name T256
Test name
Test status
Simulation time 356422761 ps
CPU time 16.51 seconds
Started Jun 13 01:41:45 PM PDT 24
Finished Jun 13 01:42:02 PM PDT 24
Peak memory 250848 kb
Host smart-74dc623d-e9c2-4c6a-9d9b-542e07848f3b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750782689 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_state_post_trans.1750782689
Directory /workspace/3.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_prog_failure.341647681
Short name T454
Test name
Test status
Simulation time 22549598 ps
CPU time 1.77 seconds
Started Jun 13 01:41:48 PM PDT 24
Finished Jun 13 01:41:50 PM PDT 24
Peak memory 221756 kb
Host smart-c6cf2530-0e40-4ae3-a751-535e4e1d3276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341647681 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_prog_failure.341647681
Directory /workspace/3.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_regwen_during_op.4092899670
Short name T688
Test name
Test status
Simulation time 1253378040 ps
CPU time 18.31 seconds
Started Jun 13 01:41:47 PM PDT 24
Finished Jun 13 01:42:06 PM PDT 24
Peak memory 217732 kb
Host smart-6689f62e-a7d0-4e3e-b637-ed0767c71de2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092899670 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_regwen_during_op.4092899670
Directory /workspace/3.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_cm.3323537883
Short name T52
Test name
Test status
Simulation time 350807700 ps
CPU time 37.69 seconds
Started Jun 13 01:41:51 PM PDT 24
Finished Jun 13 01:42:30 PM PDT 24
Peak memory 284328 kb
Host smart-7674fe7a-536b-4661-afaf-39cf1e6c650a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323537883 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_cm.3323537883
Directory /workspace/3.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_mubi.3598059747
Short name T521
Test name
Test status
Simulation time 1286446919 ps
CPU time 10.48 seconds
Started Jun 13 01:41:55 PM PDT 24
Finished Jun 13 01:42:07 PM PDT 24
Peak memory 218932 kb
Host smart-c774ea51-adaa-4170-a555-848c530402e9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598059747 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_mubi.3598059747
Directory /workspace/3.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_digest.2213626638
Short name T850
Test name
Test status
Simulation time 338148047 ps
CPU time 12.05 seconds
Started Jun 13 01:41:54 PM PDT 24
Finished Jun 13 01:42:06 PM PDT 24
Peak memory 218252 kb
Host smart-c5005e39-8eaf-4b71-996e-1c9712c3fc26
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213626638 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_di
gest.2213626638
Directory /workspace/3.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_mux.887846725
Short name T824
Test name
Test status
Simulation time 1414390658 ps
CPU time 10.58 seconds
Started Jun 13 01:41:55 PM PDT 24
Finished Jun 13 01:42:07 PM PDT 24
Peak memory 218236 kb
Host smart-12903c37-138b-41fb-94e2-fa39bb1cf60a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887846725 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_mux.887846725
Directory /workspace/3.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/3.lc_ctrl_security_escalation.3667018351
Short name T579
Test name
Test status
Simulation time 394332351 ps
CPU time 13.35 seconds
Started Jun 13 01:41:46 PM PDT 24
Finished Jun 13 01:42:00 PM PDT 24
Peak memory 225828 kb
Host smart-281283dc-a3da-48da-bfe3-51f07e60b7e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667018351 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_security_escalation.3667018351
Directory /workspace/3.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/3.lc_ctrl_smoke.702075639
Short name T507
Test name
Test status
Simulation time 103740498 ps
CPU time 2.85 seconds
Started Jun 13 01:41:50 PM PDT 24
Finished Jun 13 01:41:54 PM PDT 24
Peak memory 217756 kb
Host smart-34dfc208-6606-4b41-8f72-62d934f3f6c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=702075639 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_smoke.702075639
Directory /workspace/3.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_failure.943709713
Short name T504
Test name
Test status
Simulation time 1370141169 ps
CPU time 26.95 seconds
Started Jun 13 01:41:48 PM PDT 24
Finished Jun 13 01:42:15 PM PDT 24
Peak memory 250940 kb
Host smart-e362a646-274d-4540-ac12-2aa56666eacc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943709713 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_failure.943709713
Directory /workspace/3.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_post_trans.3666924410
Short name T550
Test name
Test status
Simulation time 320672349 ps
CPU time 8.67 seconds
Started Jun 13 01:41:48 PM PDT 24
Finished Jun 13 01:41:58 PM PDT 24
Peak memory 250968 kb
Host smart-e8ab02fd-9ed6-436c-aff5-dbce028e816e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666924410 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_post_trans.3666924410
Directory /workspace/3.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_stress_all.3855109746
Short name T75
Test name
Test status
Simulation time 2652401067 ps
CPU time 95.22 seconds
Started Jun 13 01:41:52 PM PDT 24
Finished Jun 13 01:43:28 PM PDT 24
Peak memory 267936 kb
Host smart-94e190e9-dd31-4895-ac8d-4f3b7a513f6b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855109746 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.lc_ctrl_stress_all.3855109746
Directory /workspace/3.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.lc_ctrl_alert_test.1908839227
Short name T531
Test name
Test status
Simulation time 16383572 ps
CPU time 0.89 seconds
Started Jun 13 01:44:59 PM PDT 24
Finished Jun 13 01:45:01 PM PDT 24
Peak memory 209024 kb
Host smart-ce49c492-05e9-4a0e-b2fc-13cb1bb5a14d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908839227 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_alert_test.1908839227
Directory /workspace/30.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.lc_ctrl_jtag_access.453092218
Short name T347
Test name
Test status
Simulation time 1286426808 ps
CPU time 9.49 seconds
Started Jun 13 01:44:52 PM PDT 24
Finished Jun 13 01:45:02 PM PDT 24
Peak memory 217344 kb
Host smart-4c4833e1-4b56-449d-9efc-9445070ec8b8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453092218 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_jtag_access.453092218
Directory /workspace/30.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/30.lc_ctrl_prog_failure.409544297
Short name T536
Test name
Test status
Simulation time 877907141 ps
CPU time 3.04 seconds
Started Jun 13 01:44:53 PM PDT 24
Finished Jun 13 01:44:57 PM PDT 24
Peak memory 218220 kb
Host smart-aaf203fc-9f50-4cda-bccf-56780d145305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409544297 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_prog_failure.409544297
Directory /workspace/30.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_mubi.1694281243
Short name T830
Test name
Test status
Simulation time 363642765 ps
CPU time 16.13 seconds
Started Jun 13 01:44:54 PM PDT 24
Finished Jun 13 01:45:11 PM PDT 24
Peak memory 218932 kb
Host smart-5e50c22a-c488-42aa-b4ee-c60f062991d2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694281243 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_mubi.1694281243
Directory /workspace/30.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_digest.1627532060
Short name T386
Test name
Test status
Simulation time 167858275 ps
CPU time 7.98 seconds
Started Jun 13 01:44:53 PM PDT 24
Finished Jun 13 01:45:02 PM PDT 24
Peak memory 218268 kb
Host smart-99fc662b-885f-4520-abfe-e758c4b169fa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627532060 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_d
igest.1627532060
Directory /workspace/30.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_mux.3430294609
Short name T674
Test name
Test status
Simulation time 573330046 ps
CPU time 11.03 seconds
Started Jun 13 01:45:02 PM PDT 24
Finished Jun 13 01:45:14 PM PDT 24
Peak memory 218392 kb
Host smart-e304029a-2318-4b01-a9d5-b45c96c0c43a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430294609 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_mux.
3430294609
Directory /workspace/30.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/30.lc_ctrl_security_escalation.509258256
Short name T619
Test name
Test status
Simulation time 2030873505 ps
CPU time 11.52 seconds
Started Jun 13 01:44:53 PM PDT 24
Finished Jun 13 01:45:05 PM PDT 24
Peak memory 218276 kb
Host smart-b44cfd5a-adad-49d3-a6a0-cf77b37bf66d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509258256 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_security_escalation.509258256
Directory /workspace/30.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/30.lc_ctrl_smoke.673478407
Short name T553
Test name
Test status
Simulation time 143267299 ps
CPU time 3.06 seconds
Started Jun 13 01:44:52 PM PDT 24
Finished Jun 13 01:44:56 PM PDT 24
Peak memory 214516 kb
Host smart-46a60028-4e11-456c-b8df-774ce10aca53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673478407 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_smoke.673478407
Directory /workspace/30.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_failure.1816132062
Short name T762
Test name
Test status
Simulation time 580920401 ps
CPU time 15.98 seconds
Started Jun 13 01:44:54 PM PDT 24
Finished Jun 13 01:45:10 PM PDT 24
Peak memory 245636 kb
Host smart-499e478e-1772-497e-b64a-ce92d335e2da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816132062 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_failure.1816132062
Directory /workspace/30.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_post_trans.3980560072
Short name T146
Test name
Test status
Simulation time 113839869 ps
CPU time 6.78 seconds
Started Jun 13 01:44:53 PM PDT 24
Finished Jun 13 01:45:00 PM PDT 24
Peak memory 250936 kb
Host smart-77b86259-b1a0-49a8-833d-9caefe7de33f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980560072 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_post_trans.3980560072
Directory /workspace/30.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all.1994542574
Short name T310
Test name
Test status
Simulation time 3021856000 ps
CPU time 45.88 seconds
Started Jun 13 01:44:57 PM PDT 24
Finished Jun 13 01:45:44 PM PDT 24
Peak memory 250948 kb
Host smart-99ac74e2-03c3-428d-b8a9-300f5bf0be9c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994542574 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.lc_ctrl_stress_all.1994542574
Directory /workspace/30.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all_with_rand_reset.2874932071
Short name T843
Test name
Test status
Simulation time 107134135734 ps
CPU time 324.12 seconds
Started Jun 13 01:45:04 PM PDT 24
Finished Jun 13 01:50:28 PM PDT 24
Peak memory 422132 kb
Host smart-81a34e46-25c8-40e2-88be-b2d6de77d586
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2874932071 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_stress_all_with_rand_reset.2874932071
Directory /workspace/30.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.lc_ctrl_volatile_unlock_smoke.1593866703
Short name T26
Test name
Test status
Simulation time 17216647 ps
CPU time 1.21 seconds
Started Jun 13 01:44:52 PM PDT 24
Finished Jun 13 01:44:54 PM PDT 24
Peak memory 211936 kb
Host smart-8c165768-95dd-4f5e-92b2-3a2b7613e341
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593866703 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_c
trl_volatile_unlock_smoke.1593866703
Directory /workspace/30.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_alert_test.505545841
Short name T492
Test name
Test status
Simulation time 33399217 ps
CPU time 1.23 seconds
Started Jun 13 01:44:59 PM PDT 24
Finished Jun 13 01:45:01 PM PDT 24
Peak memory 209048 kb
Host smart-1fc46c1c-4da0-4d62-a6ee-899fed3af8c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505545841 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_alert_test.505545841
Directory /workspace/31.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.lc_ctrl_errors.3330339498
Short name T166
Test name
Test status
Simulation time 4007924022 ps
CPU time 15.89 seconds
Started Jun 13 01:44:59 PM PDT 24
Finished Jun 13 01:45:16 PM PDT 24
Peak memory 218976 kb
Host smart-6d6baa67-f20e-4483-82b2-99f96eb292ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330339498 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_errors.3330339498
Directory /workspace/31.lc_ctrl_errors/latest

Test location /workspace/coverage/default/31.lc_ctrl_jtag_access.3418927150
Short name T25
Test name
Test status
Simulation time 1842639237 ps
CPU time 12.28 seconds
Started Jun 13 01:45:02 PM PDT 24
Finished Jun 13 01:45:14 PM PDT 24
Peak memory 217352 kb
Host smart-9052481f-490b-4f57-aa0b-bd2c6b7624d4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418927150 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_jtag_access.3418927150
Directory /workspace/31.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/31.lc_ctrl_prog_failure.1647603617
Short name T754
Test name
Test status
Simulation time 121278292 ps
CPU time 1.7 seconds
Started Jun 13 01:45:00 PM PDT 24
Finished Jun 13 01:45:02 PM PDT 24
Peak memory 218260 kb
Host smart-382fc55c-bbf4-45e7-8cc8-91becacb2f5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647603617 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_prog_failure.1647603617
Directory /workspace/31.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_mubi.2018946290
Short name T317
Test name
Test status
Simulation time 476446768 ps
CPU time 14.25 seconds
Started Jun 13 01:44:58 PM PDT 24
Finished Jun 13 01:45:13 PM PDT 24
Peak memory 218724 kb
Host smart-a70a67dd-d7f4-4da2-8285-6d2a18e85e6b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018946290 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_mubi.2018946290
Directory /workspace/31.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_digest.3938064860
Short name T284
Test name
Test status
Simulation time 379994739 ps
CPU time 11.66 seconds
Started Jun 13 01:44:58 PM PDT 24
Finished Jun 13 01:45:10 PM PDT 24
Peak memory 226100 kb
Host smart-769562ec-b91e-43c4-a027-c2238ba99723
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938064860 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_d
igest.3938064860
Directory /workspace/31.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_mux.4281511145
Short name T403
Test name
Test status
Simulation time 334772597 ps
CPU time 9.05 seconds
Started Jun 13 01:44:59 PM PDT 24
Finished Jun 13 01:45:09 PM PDT 24
Peak memory 218260 kb
Host smart-14bd3a0e-dee7-4970-a255-ecac60df9d9d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281511145 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_mux.
4281511145
Directory /workspace/31.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/31.lc_ctrl_security_escalation.3598505068
Short name T364
Test name
Test status
Simulation time 871168422 ps
CPU time 9.34 seconds
Started Jun 13 01:44:58 PM PDT 24
Finished Jun 13 01:45:08 PM PDT 24
Peak memory 218364 kb
Host smart-6547510a-442f-44e1-9fd2-112b3c4d1083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3598505068 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_security_escalation.3598505068
Directory /workspace/31.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/31.lc_ctrl_smoke.209706434
Short name T397
Test name
Test status
Simulation time 105640029 ps
CPU time 0.91 seconds
Started Jun 13 01:44:59 PM PDT 24
Finished Jun 13 01:45:00 PM PDT 24
Peak memory 212124 kb
Host smart-6f518f97-1c02-4403-9b8b-15349c33d006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209706434 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_smoke.209706434
Directory /workspace/31.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_failure.67896986
Short name T650
Test name
Test status
Simulation time 1059620018 ps
CPU time 25.32 seconds
Started Jun 13 01:45:03 PM PDT 24
Finished Jun 13 01:45:28 PM PDT 24
Peak memory 251028 kb
Host smart-41d43f9e-95de-44dd-bd36-c86bb679e70a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67896986 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_failure.67896986
Directory /workspace/31.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_post_trans.4136101007
Short name T346
Test name
Test status
Simulation time 177608514 ps
CPU time 3.55 seconds
Started Jun 13 01:44:58 PM PDT 24
Finished Jun 13 01:45:02 PM PDT 24
Peak memory 226408 kb
Host smart-05cad7a9-80df-4443-9c54-80f1c7c8049e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136101007 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_post_trans.4136101007
Directory /workspace/31.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/31.lc_ctrl_stress_all.1749483805
Short name T635
Test name
Test status
Simulation time 14152352817 ps
CPU time 214.04 seconds
Started Jun 13 01:45:00 PM PDT 24
Finished Jun 13 01:48:35 PM PDT 24
Peak memory 496764 kb
Host smart-329e318b-1abf-4f87-8255-c5e644b12e01
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749483805 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.lc_ctrl_stress_all.1749483805
Directory /workspace/31.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.lc_ctrl_volatile_unlock_smoke.1112668880
Short name T580
Test name
Test status
Simulation time 19908121 ps
CPU time 0.9 seconds
Started Jun 13 01:44:59 PM PDT 24
Finished Jun 13 01:45:00 PM PDT 24
Peak memory 209044 kb
Host smart-cbc44d98-99d1-4556-85c1-83dff34d316d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112668880 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_c
trl_volatile_unlock_smoke.1112668880
Directory /workspace/31.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_alert_test.1747310456
Short name T81
Test name
Test status
Simulation time 56419250 ps
CPU time 0.83 seconds
Started Jun 13 01:45:05 PM PDT 24
Finished Jun 13 01:45:07 PM PDT 24
Peak memory 208844 kb
Host smart-425808e9-3450-4cb0-9c3d-174241d14371
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747310456 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_alert_test.1747310456
Directory /workspace/32.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.lc_ctrl_errors.1222141035
Short name T247
Test name
Test status
Simulation time 498301062 ps
CPU time 14.02 seconds
Started Jun 13 01:45:07 PM PDT 24
Finished Jun 13 01:45:22 PM PDT 24
Peak memory 218148 kb
Host smart-a2f7cf50-a909-4a4a-b751-21ce1ba1f450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222141035 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_errors.1222141035
Directory /workspace/32.lc_ctrl_errors/latest

Test location /workspace/coverage/default/32.lc_ctrl_jtag_access.173937671
Short name T737
Test name
Test status
Simulation time 169539121 ps
CPU time 2.43 seconds
Started Jun 13 01:45:05 PM PDT 24
Finished Jun 13 01:45:08 PM PDT 24
Peak memory 217164 kb
Host smart-36371598-8185-4e18-98b6-5b260f01ca57
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173937671 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_jtag_access.173937671
Directory /workspace/32.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/32.lc_ctrl_prog_failure.3138088660
Short name T280
Test name
Test status
Simulation time 171538139 ps
CPU time 2.66 seconds
Started Jun 13 01:45:07 PM PDT 24
Finished Jun 13 01:45:10 PM PDT 24
Peak memory 218256 kb
Host smart-a26956bf-cfb3-42f5-aa2a-6aa74fa0706c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138088660 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_prog_failure.3138088660
Directory /workspace/32.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_mubi.3461054477
Short name T767
Test name
Test status
Simulation time 319738887 ps
CPU time 14.27 seconds
Started Jun 13 01:45:06 PM PDT 24
Finished Jun 13 01:45:21 PM PDT 24
Peak memory 218956 kb
Host smart-f6343d7a-99a4-4f20-9fd6-6ce9b96ac25c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461054477 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_mubi.3461054477
Directory /workspace/32.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_digest.1117394268
Short name T639
Test name
Test status
Simulation time 820632336 ps
CPU time 15.17 seconds
Started Jun 13 01:45:06 PM PDT 24
Finished Jun 13 01:45:22 PM PDT 24
Peak memory 226052 kb
Host smart-429ca0f7-5ec7-48bb-b1b1-429a5e004662
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117394268 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_d
igest.1117394268
Directory /workspace/32.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_mux.635072337
Short name T703
Test name
Test status
Simulation time 3084231177 ps
CPU time 10.26 seconds
Started Jun 13 01:45:07 PM PDT 24
Finished Jun 13 01:45:19 PM PDT 24
Peak memory 218316 kb
Host smart-b5437974-03b0-4d1e-9b90-8a5951101b26
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635072337 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_mux.635072337
Directory /workspace/32.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/32.lc_ctrl_security_escalation.2316981140
Short name T591
Test name
Test status
Simulation time 1417061344 ps
CPU time 14.21 seconds
Started Jun 13 01:45:04 PM PDT 24
Finished Jun 13 01:45:19 PM PDT 24
Peak memory 218308 kb
Host smart-da1245ac-666b-4462-9440-89d9b54d0725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316981140 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_security_escalation.2316981140
Directory /workspace/32.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/32.lc_ctrl_smoke.1579678349
Short name T797
Test name
Test status
Simulation time 37106386 ps
CPU time 2.94 seconds
Started Jun 13 01:45:00 PM PDT 24
Finished Jun 13 01:45:04 PM PDT 24
Peak memory 214832 kb
Host smart-fa5ae3bc-3286-4ee1-b612-0b9c62b5ca01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579678349 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_smoke.1579678349
Directory /workspace/32.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_failure.286681418
Short name T738
Test name
Test status
Simulation time 1363877365 ps
CPU time 33.08 seconds
Started Jun 13 01:45:09 PM PDT 24
Finished Jun 13 01:45:42 PM PDT 24
Peak memory 250944 kb
Host smart-8164cb84-6aa5-4b52-8577-a4c418f30f74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=286681418 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_failure.286681418
Directory /workspace/32.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_post_trans.326993705
Short name T505
Test name
Test status
Simulation time 1070547482 ps
CPU time 7.7 seconds
Started Jun 13 01:45:06 PM PDT 24
Finished Jun 13 01:45:15 PM PDT 24
Peak memory 250848 kb
Host smart-1badfed7-0b1c-4d58-8db3-017897258806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326993705 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_post_trans.326993705
Directory /workspace/32.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all.3744305920
Short name T486
Test name
Test status
Simulation time 7978592218 ps
CPU time 121.15 seconds
Started Jun 13 01:45:04 PM PDT 24
Finished Jun 13 01:47:06 PM PDT 24
Peak memory 249260 kb
Host smart-91ef55ca-6266-4ea7-97d9-75216c1e852f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744305920 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.lc_ctrl_stress_all.3744305920
Directory /workspace/32.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.lc_ctrl_volatile_unlock_smoke.692220897
Short name T20
Test name
Test status
Simulation time 31473632 ps
CPU time 0.98 seconds
Started Jun 13 01:44:57 PM PDT 24
Finished Jun 13 01:44:58 PM PDT 24
Peak memory 211956 kb
Host smart-b0daf338-218e-45c6-a890-94036d5cbd8f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692220897 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ct
rl_volatile_unlock_smoke.692220897
Directory /workspace/32.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_alert_test.3764472846
Short name T796
Test name
Test status
Simulation time 64308041 ps
CPU time 1.22 seconds
Started Jun 13 01:45:07 PM PDT 24
Finished Jun 13 01:45:10 PM PDT 24
Peak memory 209060 kb
Host smart-a1f15579-c73e-404e-a539-7d657b2e1f15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764472846 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_alert_test.3764472846
Directory /workspace/33.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.lc_ctrl_errors.1867450370
Short name T411
Test name
Test status
Simulation time 2122813827 ps
CPU time 17.28 seconds
Started Jun 13 01:45:05 PM PDT 24
Finished Jun 13 01:45:23 PM PDT 24
Peak memory 218300 kb
Host smart-c61fff39-4018-41ca-a8ec-ec05526cb3d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867450370 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_errors.1867450370
Directory /workspace/33.lc_ctrl_errors/latest

Test location /workspace/coverage/default/33.lc_ctrl_jtag_access.3818049252
Short name T604
Test name
Test status
Simulation time 2438432910 ps
CPU time 8.24 seconds
Started Jun 13 01:45:06 PM PDT 24
Finished Jun 13 01:45:15 PM PDT 24
Peak memory 217644 kb
Host smart-b041d742-ffa5-4106-9935-c5e30f51f9d8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818049252 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_jtag_access.3818049252
Directory /workspace/33.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/33.lc_ctrl_prog_failure.1726505636
Short name T616
Test name
Test status
Simulation time 33471079 ps
CPU time 1.44 seconds
Started Jun 13 01:45:06 PM PDT 24
Finished Jun 13 01:45:09 PM PDT 24
Peak memory 221688 kb
Host smart-71b8af70-5d80-4569-851d-1923c74f94ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726505636 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_prog_failure.1726505636
Directory /workspace/33.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_mubi.1996889438
Short name T214
Test name
Test status
Simulation time 232722429 ps
CPU time 11.74 seconds
Started Jun 13 01:45:04 PM PDT 24
Finished Jun 13 01:45:17 PM PDT 24
Peak memory 218908 kb
Host smart-083c1e7b-d378-4c0b-b4c3-c41868d43971
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996889438 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_mubi.1996889438
Directory /workspace/33.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_digest.3186246151
Short name T165
Test name
Test status
Simulation time 681213340 ps
CPU time 17.48 seconds
Started Jun 13 01:45:08 PM PDT 24
Finished Jun 13 01:45:26 PM PDT 24
Peak memory 218268 kb
Host smart-171c344b-4686-4327-9627-e1195dae2b14
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186246151 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_d
igest.3186246151
Directory /workspace/33.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_mux.1750827134
Short name T827
Test name
Test status
Simulation time 2390876212 ps
CPU time 10.73 seconds
Started Jun 13 01:45:06 PM PDT 24
Finished Jun 13 01:45:17 PM PDT 24
Peak memory 218312 kb
Host smart-b1148def-f541-4ca8-90dc-68ab07c23389
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750827134 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_mux.
1750827134
Directory /workspace/33.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/33.lc_ctrl_security_escalation.3737042033
Short name T49
Test name
Test status
Simulation time 879848252 ps
CPU time 6.9 seconds
Started Jun 13 01:45:06 PM PDT 24
Finished Jun 13 01:45:14 PM PDT 24
Peak memory 225120 kb
Host smart-22124376-7634-4fa8-99db-36417e30fc28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737042033 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_security_escalation.3737042033
Directory /workspace/33.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/33.lc_ctrl_smoke.968965711
Short name T837
Test name
Test status
Simulation time 89886460 ps
CPU time 2.34 seconds
Started Jun 13 01:45:09 PM PDT 24
Finished Jun 13 01:45:12 PM PDT 24
Peak memory 214568 kb
Host smart-fba9715b-a304-40c6-ab76-b5061979521c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968965711 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_smoke.968965711
Directory /workspace/33.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_failure.828152987
Short name T283
Test name
Test status
Simulation time 836600866 ps
CPU time 19.87 seconds
Started Jun 13 01:45:05 PM PDT 24
Finished Jun 13 01:45:26 PM PDT 24
Peak memory 250904 kb
Host smart-aa2cf50c-9a44-43c8-bd6a-de134ecc806c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828152987 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_failure.828152987
Directory /workspace/33.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_post_trans.2738712924
Short name T479
Test name
Test status
Simulation time 597765332 ps
CPU time 6.32 seconds
Started Jun 13 01:45:07 PM PDT 24
Finished Jun 13 01:45:14 PM PDT 24
Peak memory 246544 kb
Host smart-3cfbe9c9-9ce9-4421-979c-d683a1fedbe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738712924 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_post_trans.2738712924
Directory /workspace/33.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all.475729324
Short name T691
Test name
Test status
Simulation time 5765944810 ps
CPU time 103.66 seconds
Started Jun 13 01:45:07 PM PDT 24
Finished Jun 13 01:46:52 PM PDT 24
Peak memory 309680 kb
Host smart-f5585a65-5736-4ed1-9ee8-ff8c6da92fe5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475729324 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.lc_ctrl_stress_all.475729324
Directory /workspace/33.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.lc_ctrl_volatile_unlock_smoke.884349478
Short name T313
Test name
Test status
Simulation time 17719105 ps
CPU time 0.74 seconds
Started Jun 13 01:45:06 PM PDT 24
Finished Jun 13 01:45:08 PM PDT 24
Peak memory 207136 kb
Host smart-99107eed-c9d4-46af-939d-698183ee1c68
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884349478 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ct
rl_volatile_unlock_smoke.884349478
Directory /workspace/33.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_alert_test.1804123653
Short name T584
Test name
Test status
Simulation time 29137121 ps
CPU time 0.87 seconds
Started Jun 13 01:45:20 PM PDT 24
Finished Jun 13 01:45:22 PM PDT 24
Peak memory 208968 kb
Host smart-2ff6d234-a8f5-4527-8e05-5c4819f9e565
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804123653 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_alert_test.1804123653
Directory /workspace/34.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.lc_ctrl_errors.2311858904
Short name T477
Test name
Test status
Simulation time 1257168665 ps
CPU time 14.87 seconds
Started Jun 13 01:45:12 PM PDT 24
Finished Jun 13 01:45:28 PM PDT 24
Peak memory 218256 kb
Host smart-33b4c39c-504d-42bc-b294-a5431ec521c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311858904 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_errors.2311858904
Directory /workspace/34.lc_ctrl_errors/latest

Test location /workspace/coverage/default/34.lc_ctrl_jtag_access.1293422769
Short name T730
Test name
Test status
Simulation time 61091240 ps
CPU time 1.32 seconds
Started Jun 13 01:45:11 PM PDT 24
Finished Jun 13 01:45:13 PM PDT 24
Peak memory 217092 kb
Host smart-fca06da9-ec17-4a50-8fb2-639259d341de
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293422769 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_jtag_access.1293422769
Directory /workspace/34.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/34.lc_ctrl_prog_failure.673797419
Short name T156
Test name
Test status
Simulation time 40566978 ps
CPU time 2.19 seconds
Started Jun 13 01:45:10 PM PDT 24
Finished Jun 13 01:45:12 PM PDT 24
Peak memory 218216 kb
Host smart-5a8e5c13-0610-4019-aa70-39edee9ba73e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673797419 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_prog_failure.673797419
Directory /workspace/34.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_mubi.4217554350
Short name T312
Test name
Test status
Simulation time 395010917 ps
CPU time 14.45 seconds
Started Jun 13 01:45:21 PM PDT 24
Finished Jun 13 01:45:36 PM PDT 24
Peak memory 219104 kb
Host smart-e12486b6-96c5-4c58-abe9-671a0fc9f23d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217554350 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_mubi.4217554350
Directory /workspace/34.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_digest.267175523
Short name T665
Test name
Test status
Simulation time 609334164 ps
CPU time 11.56 seconds
Started Jun 13 01:45:10 PM PDT 24
Finished Jun 13 01:45:22 PM PDT 24
Peak memory 226064 kb
Host smart-7dae2ef8-efdc-4afa-9b52-94603ab516e9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267175523 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_di
gest.267175523
Directory /workspace/34.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_mux.750299004
Short name T366
Test name
Test status
Simulation time 1250488787 ps
CPU time 8.16 seconds
Started Jun 13 01:45:12 PM PDT 24
Finished Jun 13 01:45:21 PM PDT 24
Peak memory 218216 kb
Host smart-3ecdaef0-cc24-4ab8-9f25-6f3ba09956f7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750299004 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_mux.750299004
Directory /workspace/34.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/34.lc_ctrl_security_escalation.1079241131
Short name T707
Test name
Test status
Simulation time 1163483606 ps
CPU time 12.05 seconds
Started Jun 13 01:45:19 PM PDT 24
Finished Jun 13 01:45:32 PM PDT 24
Peak memory 218412 kb
Host smart-e45bd9cc-0513-47a0-b624-691a7e774539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079241131 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_security_escalation.1079241131
Directory /workspace/34.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/34.lc_ctrl_smoke.61031142
Short name T367
Test name
Test status
Simulation time 76821262 ps
CPU time 3.52 seconds
Started Jun 13 01:45:12 PM PDT 24
Finished Jun 13 01:45:17 PM PDT 24
Peak memory 214452 kb
Host smart-ddeaffbe-3088-48c9-b6cf-1cd359b51670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61031142 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_smoke.61031142
Directory /workspace/34.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_failure.1280124299
Short name T690
Test name
Test status
Simulation time 772294670 ps
CPU time 18.21 seconds
Started Jun 13 01:45:19 PM PDT 24
Finished Jun 13 01:45:39 PM PDT 24
Peak memory 251020 kb
Host smart-c44acaaa-362b-4ba0-b901-c908e0859611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280124299 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_failure.1280124299
Directory /workspace/34.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_post_trans.2295760996
Short name T204
Test name
Test status
Simulation time 162428469 ps
CPU time 9.76 seconds
Started Jun 13 01:45:11 PM PDT 24
Finished Jun 13 01:45:22 PM PDT 24
Peak memory 250908 kb
Host smart-57c322be-c75c-407f-bbed-755ee66bd38a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295760996 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_post_trans.2295760996
Directory /workspace/34.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all.842224720
Short name T778
Test name
Test status
Simulation time 4187448969 ps
CPU time 80.75 seconds
Started Jun 13 01:45:12 PM PDT 24
Finished Jun 13 01:46:33 PM PDT 24
Peak memory 270844 kb
Host smart-08aeac14-343d-486d-9376-84f042ca56d5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842224720 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.lc_ctrl_stress_all.842224720
Directory /workspace/34.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all_with_rand_reset.3757278505
Short name T41
Test name
Test status
Simulation time 16112493024 ps
CPU time 361.72 seconds
Started Jun 13 01:45:12 PM PDT 24
Finished Jun 13 01:51:15 PM PDT 24
Peak memory 447600 kb
Host smart-0b5b8ec7-6084-4960-9901-26b98e2e5b29
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3757278505 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_stress_all_with_rand_reset.3757278505
Directory /workspace/34.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.lc_ctrl_volatile_unlock_smoke.2152944752
Short name T270
Test name
Test status
Simulation time 23925090 ps
CPU time 1.05 seconds
Started Jun 13 01:45:11 PM PDT 24
Finished Jun 13 01:45:13 PM PDT 24
Peak memory 212068 kb
Host smart-b1ce96ae-7af3-418f-8361-49e6860d5cc0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152944752 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_c
trl_volatile_unlock_smoke.2152944752
Directory /workspace/34.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_alert_test.2638890539
Short name T369
Test name
Test status
Simulation time 128787271 ps
CPU time 0.83 seconds
Started Jun 13 01:45:17 PM PDT 24
Finished Jun 13 01:45:19 PM PDT 24
Peak memory 208792 kb
Host smart-057565f4-b02f-4539-8a36-2453e9d1957c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638890539 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_alert_test.2638890539
Directory /workspace/35.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.lc_ctrl_errors.4186602549
Short name T560
Test name
Test status
Simulation time 297468446 ps
CPU time 15.21 seconds
Started Jun 13 01:45:17 PM PDT 24
Finished Jun 13 01:45:33 PM PDT 24
Peak memory 218316 kb
Host smart-eda0bc7e-18cd-4245-a621-1ac300baeb78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186602549 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_errors.4186602549
Directory /workspace/35.lc_ctrl_errors/latest

Test location /workspace/coverage/default/35.lc_ctrl_jtag_access.3616492369
Short name T344
Test name
Test status
Simulation time 1179699532 ps
CPU time 4.22 seconds
Started Jun 13 01:45:19 PM PDT 24
Finished Jun 13 01:45:25 PM PDT 24
Peak memory 217224 kb
Host smart-3bf21b1f-5538-433a-9fbc-a8ae221dab4d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616492369 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_jtag_access.3616492369
Directory /workspace/35.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/35.lc_ctrl_prog_failure.2941915339
Short name T769
Test name
Test status
Simulation time 86968323 ps
CPU time 2.01 seconds
Started Jun 13 01:45:20 PM PDT 24
Finished Jun 13 01:45:23 PM PDT 24
Peak memory 222024 kb
Host smart-1b942f7d-5947-41ff-b3b3-56b537a28073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941915339 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_prog_failure.2941915339
Directory /workspace/35.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_mubi.2364238599
Short name T445
Test name
Test status
Simulation time 1472723907 ps
CPU time 14.53 seconds
Started Jun 13 01:45:17 PM PDT 24
Finished Jun 13 01:45:33 PM PDT 24
Peak memory 218924 kb
Host smart-3f64cc1f-55e5-4f84-a35c-3c19e768a865
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364238599 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_mubi.2364238599
Directory /workspace/35.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_digest.789336046
Short name T93
Test name
Test status
Simulation time 262266864 ps
CPU time 8.72 seconds
Started Jun 13 01:45:20 PM PDT 24
Finished Jun 13 01:45:30 PM PDT 24
Peak memory 218268 kb
Host smart-4bdab4a1-c435-4ece-9df1-e9f042b1092a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789336046 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_di
gest.789336046
Directory /workspace/35.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_mux.2858734855
Short name T275
Test name
Test status
Simulation time 820565698 ps
CPU time 8.14 seconds
Started Jun 13 01:45:19 PM PDT 24
Finished Jun 13 01:45:28 PM PDT 24
Peak memory 218256 kb
Host smart-d5bfb1c0-03ee-4205-aa63-c3e29fe002fb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858734855 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_mux.
2858734855
Directory /workspace/35.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/35.lc_ctrl_security_escalation.2369957765
Short name T50
Test name
Test status
Simulation time 263626710 ps
CPU time 9.92 seconds
Started Jun 13 01:45:19 PM PDT 24
Finished Jun 13 01:45:30 PM PDT 24
Peak memory 218296 kb
Host smart-9fdb1628-f86e-40b3-9d0b-1858c382355d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369957765 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_security_escalation.2369957765
Directory /workspace/35.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/35.lc_ctrl_smoke.2836544380
Short name T802
Test name
Test status
Simulation time 149470609 ps
CPU time 3.16 seconds
Started Jun 13 01:45:21 PM PDT 24
Finished Jun 13 01:45:25 PM PDT 24
Peak memory 217772 kb
Host smart-33042f76-695a-4ed2-8be4-2c31cb2a3efe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836544380 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_smoke.2836544380
Directory /workspace/35.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_failure.1834290334
Short name T342
Test name
Test status
Simulation time 204318853 ps
CPU time 19.82 seconds
Started Jun 13 01:45:19 PM PDT 24
Finished Jun 13 01:45:40 PM PDT 24
Peak memory 250880 kb
Host smart-a1be3c99-8746-4867-aae6-67a226a1963f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834290334 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_failure.1834290334
Directory /workspace/35.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_post_trans.1985961252
Short name T699
Test name
Test status
Simulation time 349168734 ps
CPU time 4.37 seconds
Started Jun 13 01:45:18 PM PDT 24
Finished Jun 13 01:45:23 PM PDT 24
Peak memory 218160 kb
Host smart-2b67bccd-be92-4cb1-a8a2-72949f0b0e05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985961252 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_post_trans.1985961252
Directory /workspace/35.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all.508689232
Short name T66
Test name
Test status
Simulation time 9716468072 ps
CPU time 231.5 seconds
Started Jun 13 01:45:18 PM PDT 24
Finished Jun 13 01:49:10 PM PDT 24
Peak memory 495580 kb
Host smart-99c9cae9-d320-45bf-b378-34298eb097ee
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508689232 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.lc_ctrl_stress_all.508689232
Directory /workspace/35.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.lc_ctrl_volatile_unlock_smoke.2496006286
Short name T663
Test name
Test status
Simulation time 43428276 ps
CPU time 0.81 seconds
Started Jun 13 01:45:20 PM PDT 24
Finished Jun 13 01:45:22 PM PDT 24
Peak memory 208912 kb
Host smart-e808bd5f-1b94-4ef9-888b-7496b78c1815
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496006286 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_c
trl_volatile_unlock_smoke.2496006286
Directory /workspace/35.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_alert_test.3458772654
Short name T847
Test name
Test status
Simulation time 14869651 ps
CPU time 0.89 seconds
Started Jun 13 01:45:26 PM PDT 24
Finished Jun 13 01:45:27 PM PDT 24
Peak memory 208820 kb
Host smart-84fdfe70-85be-4e5b-b1d8-c019b7b10593
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458772654 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_alert_test.3458772654
Directory /workspace/36.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.lc_ctrl_errors.2334933676
Short name T672
Test name
Test status
Simulation time 292447273 ps
CPU time 15.8 seconds
Started Jun 13 01:45:19 PM PDT 24
Finished Jun 13 01:45:36 PM PDT 24
Peak memory 226092 kb
Host smart-167013a9-b2d4-41cc-bf8e-5fbca39db26c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334933676 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_errors.2334933676
Directory /workspace/36.lc_ctrl_errors/latest

Test location /workspace/coverage/default/36.lc_ctrl_jtag_access.3023415915
Short name T687
Test name
Test status
Simulation time 486808748 ps
CPU time 6.58 seconds
Started Jun 13 01:45:23 PM PDT 24
Finished Jun 13 01:45:30 PM PDT 24
Peak memory 217220 kb
Host smart-9a3fb7b7-3215-437b-9de4-b372cbda56a6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023415915 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_jtag_access.3023415915
Directory /workspace/36.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/36.lc_ctrl_prog_failure.3973809986
Short name T723
Test name
Test status
Simulation time 19746098 ps
CPU time 1.71 seconds
Started Jun 13 01:45:19 PM PDT 24
Finished Jun 13 01:45:21 PM PDT 24
Peak memory 218216 kb
Host smart-59e6974a-7274-4446-a279-1b757706fe94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973809986 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_prog_failure.3973809986
Directory /workspace/36.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_mubi.3780556727
Short name T443
Test name
Test status
Simulation time 339014405 ps
CPU time 18.15 seconds
Started Jun 13 01:45:19 PM PDT 24
Finished Jun 13 01:45:38 PM PDT 24
Peak memory 226088 kb
Host smart-70cb96d3-efe5-4e21-bfaf-eea31e161267
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780556727 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_mubi.3780556727
Directory /workspace/36.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_digest.2707535918
Short name T376
Test name
Test status
Simulation time 557093940 ps
CPU time 11.46 seconds
Started Jun 13 01:46:43 PM PDT 24
Finished Jun 13 01:46:56 PM PDT 24
Peak memory 218240 kb
Host smart-6d96f0e6-297d-4df8-9bbe-33ad7d4524db
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707535918 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_d
igest.2707535918
Directory /workspace/36.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_mux.3338614962
Short name T667
Test name
Test status
Simulation time 196408727 ps
CPU time 6.5 seconds
Started Jun 13 01:45:19 PM PDT 24
Finished Jun 13 01:45:26 PM PDT 24
Peak memory 218256 kb
Host smart-9bbc7f6b-f598-4e9e-82b2-50382e0c55ff
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338614962 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_mux.
3338614962
Directory /workspace/36.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/36.lc_ctrl_security_escalation.2489006505
Short name T599
Test name
Test status
Simulation time 552752995 ps
CPU time 12.66 seconds
Started Jun 13 01:45:20 PM PDT 24
Finished Jun 13 01:45:34 PM PDT 24
Peak memory 218348 kb
Host smart-9ff547e0-46f3-4988-9975-96934567c8a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489006505 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_security_escalation.2489006505
Directory /workspace/36.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/36.lc_ctrl_smoke.1341748659
Short name T565
Test name
Test status
Simulation time 90870319 ps
CPU time 1.31 seconds
Started Jun 13 01:45:19 PM PDT 24
Finished Jun 13 01:45:21 PM PDT 24
Peak memory 217768 kb
Host smart-8711646b-9a87-4f68-8697-794daf5cad33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341748659 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_smoke.1341748659
Directory /workspace/36.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_failure.2125238868
Short name T615
Test name
Test status
Simulation time 3379732159 ps
CPU time 25.92 seconds
Started Jun 13 01:45:18 PM PDT 24
Finished Jun 13 01:45:45 PM PDT 24
Peak memory 250960 kb
Host smart-183f5bd4-f07f-40dc-b940-209da39c1f2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125238868 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_failure.2125238868
Directory /workspace/36.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_post_trans.3201364562
Short name T814
Test name
Test status
Simulation time 215187092 ps
CPU time 5.98 seconds
Started Jun 13 01:45:21 PM PDT 24
Finished Jun 13 01:45:28 PM PDT 24
Peak memory 248936 kb
Host smart-aa340ad4-d6d2-4577-9cf4-e4a60a3db20a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201364562 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_post_trans.3201364562
Directory /workspace/36.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all.3211670814
Short name T452
Test name
Test status
Simulation time 4203358532 ps
CPU time 97.33 seconds
Started Jun 13 01:45:18 PM PDT 24
Finished Jun 13 01:46:57 PM PDT 24
Peak memory 251604 kb
Host smart-08f952c3-b6ca-4754-9008-4b4aad5ec99f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211670814 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.lc_ctrl_stress_all.3211670814
Directory /workspace/36.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.lc_ctrl_volatile_unlock_smoke.547428375
Short name T589
Test name
Test status
Simulation time 13743785 ps
CPU time 1 seconds
Started Jun 13 01:45:21 PM PDT 24
Finished Jun 13 01:45:23 PM PDT 24
Peak memory 209052 kb
Host smart-d8b1cd98-2ddc-460d-88e4-b88c00f07a46
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547428375 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ct
rl_volatile_unlock_smoke.547428375
Directory /workspace/36.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_alert_test.780661649
Short name T569
Test name
Test status
Simulation time 30428264 ps
CPU time 0.92 seconds
Started Jun 13 01:45:34 PM PDT 24
Finished Jun 13 01:45:36 PM PDT 24
Peak memory 208888 kb
Host smart-46fac779-eec1-40a9-9ee0-eec98d1208a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780661649 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_alert_test.780661649
Directory /workspace/37.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.lc_ctrl_errors.201578959
Short name T602
Test name
Test status
Simulation time 446099993 ps
CPU time 11.65 seconds
Started Jun 13 01:45:26 PM PDT 24
Finished Jun 13 01:45:39 PM PDT 24
Peak memory 218224 kb
Host smart-7964ef1f-374b-463c-b25f-6f9fce7969b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201578959 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_errors.201578959
Directory /workspace/37.lc_ctrl_errors/latest

Test location /workspace/coverage/default/37.lc_ctrl_jtag_access.2772092060
Short name T351
Test name
Test status
Simulation time 1733485235 ps
CPU time 3.16 seconds
Started Jun 13 01:45:24 PM PDT 24
Finished Jun 13 01:45:28 PM PDT 24
Peak memory 217056 kb
Host smart-379cf323-6705-431d-9ee5-d97feace26ba
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772092060 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_jtag_access.2772092060
Directory /workspace/37.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/37.lc_ctrl_prog_failure.4224109122
Short name T720
Test name
Test status
Simulation time 100978560 ps
CPU time 4.11 seconds
Started Jun 13 01:45:23 PM PDT 24
Finished Jun 13 01:45:28 PM PDT 24
Peak memory 218256 kb
Host smart-bd96803e-7656-48f9-88ba-b798586de58f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224109122 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_prog_failure.4224109122
Directory /workspace/37.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_mubi.827193534
Short name T603
Test name
Test status
Simulation time 163128742 ps
CPU time 8.97 seconds
Started Jun 13 01:45:22 PM PDT 24
Finished Jun 13 01:45:32 PM PDT 24
Peak memory 218328 kb
Host smart-0b0a0a44-3d72-4780-ac51-cc563b7d7da1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827193534 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_mubi.827193534
Directory /workspace/37.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_digest.4083493838
Short name T450
Test name
Test status
Simulation time 1597418036 ps
CPU time 12.07 seconds
Started Jun 13 01:45:25 PM PDT 24
Finished Jun 13 01:45:38 PM PDT 24
Peak memory 218272 kb
Host smart-eb997c5e-13ec-4720-931f-1f733f9c8637
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083493838 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_d
igest.4083493838
Directory /workspace/37.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_mux.2108877689
Short name T227
Test name
Test status
Simulation time 323395938 ps
CPU time 7.05 seconds
Started Jun 13 01:45:25 PM PDT 24
Finished Jun 13 01:45:33 PM PDT 24
Peak memory 218272 kb
Host smart-d5b34c21-e4e7-41f7-a1d3-dc8db37fcffe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108877689 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_mux.
2108877689
Directory /workspace/37.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/37.lc_ctrl_security_escalation.1814058864
Short name T645
Test name
Test status
Simulation time 318571048 ps
CPU time 9.56 seconds
Started Jun 13 01:45:25 PM PDT 24
Finished Jun 13 01:45:35 PM PDT 24
Peak memory 218276 kb
Host smart-0858a5e9-6ca0-441d-a72d-a6b85416e324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814058864 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_security_escalation.1814058864
Directory /workspace/37.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/37.lc_ctrl_smoke.2921888585
Short name T255
Test name
Test status
Simulation time 109074610 ps
CPU time 1.89 seconds
Started Jun 13 01:45:27 PM PDT 24
Finished Jun 13 01:45:29 PM PDT 24
Peak memory 217776 kb
Host smart-99f06a76-00ab-4693-af96-d372535442d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921888585 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_smoke.2921888585
Directory /workspace/37.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_failure.1564606863
Short name T793
Test name
Test status
Simulation time 303299852 ps
CPU time 25.32 seconds
Started Jun 13 01:45:25 PM PDT 24
Finished Jun 13 01:45:51 PM PDT 24
Peak memory 250968 kb
Host smart-8e3f6df4-2677-448c-87de-88482abd7e7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1564606863 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_failure.1564606863
Directory /workspace/37.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_post_trans.1599926396
Short name T96
Test name
Test status
Simulation time 362287551 ps
CPU time 7.15 seconds
Started Jun 13 01:45:24 PM PDT 24
Finished Jun 13 01:45:32 PM PDT 24
Peak memory 250932 kb
Host smart-56865cdb-1073-4b39-a111-9fe88fde3208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599926396 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_post_trans.1599926396
Directory /workspace/37.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all.4254997907
Short name T861
Test name
Test status
Simulation time 1767079506 ps
CPU time 57.62 seconds
Started Jun 13 01:45:25 PM PDT 24
Finished Jun 13 01:46:23 PM PDT 24
Peak memory 250872 kb
Host smart-cbb22b33-e38d-4610-998e-cab66d5e8ea1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254997907 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.lc_ctrl_stress_all.4254997907
Directory /workspace/37.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.lc_ctrl_volatile_unlock_smoke.874092949
Short name T776
Test name
Test status
Simulation time 14026651 ps
CPU time 0.97 seconds
Started Jun 13 01:45:25 PM PDT 24
Finished Jun 13 01:45:26 PM PDT 24
Peak memory 209072 kb
Host smart-f68cba13-3075-45b8-8ced-1622dec01e5b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874092949 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ct
rl_volatile_unlock_smoke.874092949
Directory /workspace/37.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_alert_test.3455814803
Short name T845
Test name
Test status
Simulation time 20789376 ps
CPU time 0.93 seconds
Started Jun 13 01:45:42 PM PDT 24
Finished Jun 13 01:45:44 PM PDT 24
Peak memory 209032 kb
Host smart-f5b9fa8a-6ffa-4f85-b2fb-034ecaecb620
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455814803 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_alert_test.3455814803
Directory /workspace/38.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.lc_ctrl_errors.2661513965
Short name T514
Test name
Test status
Simulation time 1945727194 ps
CPU time 13.31 seconds
Started Jun 13 01:45:31 PM PDT 24
Finished Jun 13 01:45:45 PM PDT 24
Peak memory 218284 kb
Host smart-423d1649-72e3-4e4a-ab7f-669feba2e879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661513965 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_errors.2661513965
Directory /workspace/38.lc_ctrl_errors/latest

Test location /workspace/coverage/default/38.lc_ctrl_jtag_access.749914481
Short name T864
Test name
Test status
Simulation time 86071044 ps
CPU time 1.8 seconds
Started Jun 13 01:45:34 PM PDT 24
Finished Jun 13 01:45:37 PM PDT 24
Peak memory 217172 kb
Host smart-f256901e-8a41-4edf-be04-18351d326cd3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749914481 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_jtag_access.749914481
Directory /workspace/38.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/38.lc_ctrl_prog_failure.3783737878
Short name T715
Test name
Test status
Simulation time 458352331 ps
CPU time 4.53 seconds
Started Jun 13 01:45:30 PM PDT 24
Finished Jun 13 01:45:35 PM PDT 24
Peak memory 218216 kb
Host smart-73544018-f511-44c9-be4f-4951c72a2e7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783737878 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_prog_failure.3783737878
Directory /workspace/38.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_mubi.57230747
Short name T764
Test name
Test status
Simulation time 2482319754 ps
CPU time 9.25 seconds
Started Jun 13 01:45:33 PM PDT 24
Finished Jun 13 01:45:42 PM PDT 24
Peak memory 219052 kb
Host smart-f0d76759-1200-4b15-a804-dc388a2d7db5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57230747 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_mubi.57230747
Directory /workspace/38.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_digest.2194085144
Short name T811
Test name
Test status
Simulation time 482763072 ps
CPU time 12.95 seconds
Started Jun 13 01:45:31 PM PDT 24
Finished Jun 13 01:45:44 PM PDT 24
Peak memory 218256 kb
Host smart-3bef7bfa-7a18-4714-9b87-a9af62d48ce1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194085144 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_d
igest.2194085144
Directory /workspace/38.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_mux.694990449
Short name T463
Test name
Test status
Simulation time 383967418 ps
CPU time 12.67 seconds
Started Jun 13 01:45:30 PM PDT 24
Finished Jun 13 01:45:44 PM PDT 24
Peak memory 218260 kb
Host smart-b89a878c-0ca6-4b5b-b744-a8cd690df0b1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694990449 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_mux.694990449
Directory /workspace/38.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/38.lc_ctrl_security_escalation.2574069918
Short name T855
Test name
Test status
Simulation time 253956987 ps
CPU time 6.2 seconds
Started Jun 13 01:45:28 PM PDT 24
Finished Jun 13 01:45:35 PM PDT 24
Peak memory 224536 kb
Host smart-0f55b4c9-1122-4fe8-934f-2dbcb6638984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574069918 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_security_escalation.2574069918
Directory /workspace/38.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/38.lc_ctrl_smoke.776089703
Short name T487
Test name
Test status
Simulation time 16887257 ps
CPU time 1.53 seconds
Started Jun 13 01:45:30 PM PDT 24
Finished Jun 13 01:45:32 PM PDT 24
Peak memory 213892 kb
Host smart-ff8afa92-e674-411b-9b2f-2b1b4017557b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776089703 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_smoke.776089703
Directory /workspace/38.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_failure.2963562999
Short name T457
Test name
Test status
Simulation time 229929524 ps
CPU time 21.76 seconds
Started Jun 13 01:45:31 PM PDT 24
Finished Jun 13 01:45:53 PM PDT 24
Peak memory 250900 kb
Host smart-528ddd34-7b06-4681-b2ef-a2cb5296f4fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963562999 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_failure.2963562999
Directory /workspace/38.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_post_trans.14215353
Short name T655
Test name
Test status
Simulation time 122050786 ps
CPU time 7.76 seconds
Started Jun 13 01:45:32 PM PDT 24
Finished Jun 13 01:45:40 PM PDT 24
Peak memory 250888 kb
Host smart-fcd6d7ef-9453-4004-a98a-235d09c94d79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14215353 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_post_trans.14215353
Directory /workspace/38.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all.851551868
Short name T636
Test name
Test status
Simulation time 8337365014 ps
CPU time 71.95 seconds
Started Jun 13 01:45:34 PM PDT 24
Finished Jun 13 01:46:46 PM PDT 24
Peak memory 250964 kb
Host smart-0cc91930-d157-4169-83ff-4d7ce59bafc4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851551868 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.lc_ctrl_stress_all.851551868
Directory /workspace/38.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.lc_ctrl_volatile_unlock_smoke.2566510317
Short name T822
Test name
Test status
Simulation time 10910302 ps
CPU time 0.82 seconds
Started Jun 13 01:45:33 PM PDT 24
Finished Jun 13 01:45:35 PM PDT 24
Peak memory 208952 kb
Host smart-7e40fa96-a1ed-48cc-8585-045e866675df
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566510317 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_c
trl_volatile_unlock_smoke.2566510317
Directory /workspace/38.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_alert_test.1802609159
Short name T394
Test name
Test status
Simulation time 68320609 ps
CPU time 0.93 seconds
Started Jun 13 01:45:38 PM PDT 24
Finished Jun 13 01:45:40 PM PDT 24
Peak memory 208964 kb
Host smart-a8ba38ca-1774-4c6e-a03f-c23b620303fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802609159 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_alert_test.1802609159
Directory /workspace/39.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.lc_ctrl_errors.3950989216
Short name T622
Test name
Test status
Simulation time 1032044592 ps
CPU time 10.58 seconds
Started Jun 13 01:45:30 PM PDT 24
Finished Jun 13 01:45:42 PM PDT 24
Peak memory 218236 kb
Host smart-1baea7d3-4318-416c-be1b-23f13b6889a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950989216 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_errors.3950989216
Directory /workspace/39.lc_ctrl_errors/latest

Test location /workspace/coverage/default/39.lc_ctrl_jtag_access.3874286120
Short name T420
Test name
Test status
Simulation time 366347016 ps
CPU time 6.03 seconds
Started Jun 13 01:45:47 PM PDT 24
Finished Jun 13 01:45:53 PM PDT 24
Peak memory 217416 kb
Host smart-68b7f3f7-ae12-4407-916f-e4529d32c156
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874286120 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_jtag_access.3874286120
Directory /workspace/39.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/39.lc_ctrl_prog_failure.2621570180
Short name T853
Test name
Test status
Simulation time 99056249 ps
CPU time 2 seconds
Started Jun 13 01:45:30 PM PDT 24
Finished Jun 13 01:45:32 PM PDT 24
Peak memory 218208 kb
Host smart-b9cccbd9-5b21-4331-adf8-bfbf76e1867a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621570180 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_prog_failure.2621570180
Directory /workspace/39.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_mubi.3117866470
Short name T848
Test name
Test status
Simulation time 661015779 ps
CPU time 10.31 seconds
Started Jun 13 01:45:37 PM PDT 24
Finished Jun 13 01:45:48 PM PDT 24
Peak memory 218336 kb
Host smart-835b78f4-8823-4e12-a370-cdf91bfc55ba
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117866470 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_mubi.3117866470
Directory /workspace/39.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_digest.134515778
Short name T293
Test name
Test status
Simulation time 354927172 ps
CPU time 10.56 seconds
Started Jun 13 01:45:36 PM PDT 24
Finished Jun 13 01:45:48 PM PDT 24
Peak memory 226056 kb
Host smart-e9616a4a-b8d1-4179-b785-5fed046a53e9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134515778 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_di
gest.134515778
Directory /workspace/39.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_mux.2872921502
Short name T37
Test name
Test status
Simulation time 1458508671 ps
CPU time 13.98 seconds
Started Jun 13 01:45:45 PM PDT 24
Finished Jun 13 01:46:00 PM PDT 24
Peak memory 218260 kb
Host smart-5d8c4297-72b6-4bdb-9d2d-eb2d45762c26
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872921502 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_mux.
2872921502
Directory /workspace/39.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/39.lc_ctrl_security_escalation.3385598843
Short name T428
Test name
Test status
Simulation time 365718802 ps
CPU time 14.1 seconds
Started Jun 13 01:45:30 PM PDT 24
Finished Jun 13 01:45:45 PM PDT 24
Peak memory 225916 kb
Host smart-e2ef5353-f554-41bf-bef6-15e3d814451a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385598843 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_security_escalation.3385598843
Directory /workspace/39.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/39.lc_ctrl_smoke.3819308209
Short name T248
Test name
Test status
Simulation time 97509749 ps
CPU time 1.91 seconds
Started Jun 13 01:45:33 PM PDT 24
Finished Jun 13 01:45:36 PM PDT 24
Peak memory 217760 kb
Host smart-3a360207-ee1e-4c5a-b803-1b47d0e74601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819308209 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_smoke.3819308209
Directory /workspace/39.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_failure.1481687273
Short name T264
Test name
Test status
Simulation time 482318427 ps
CPU time 32.22 seconds
Started Jun 13 01:45:31 PM PDT 24
Finished Jun 13 01:46:04 PM PDT 24
Peak memory 250860 kb
Host smart-8157415f-f8b0-4a88-a406-6640cab8488e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1481687273 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_failure.1481687273
Directory /workspace/39.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_post_trans.1049770726
Short name T306
Test name
Test status
Simulation time 73177382 ps
CPU time 6.71 seconds
Started Jun 13 01:45:31 PM PDT 24
Finished Jun 13 01:45:38 PM PDT 24
Peak memory 250476 kb
Host smart-57fd0c5b-7a02-4eed-a5bd-49e65d0d455a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049770726 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_post_trans.1049770726
Directory /workspace/39.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all.3435434699
Short name T759
Test name
Test status
Simulation time 3335439882 ps
CPU time 133.66 seconds
Started Jun 13 01:45:46 PM PDT 24
Finished Jun 13 01:48:01 PM PDT 24
Peak memory 267328 kb
Host smart-9cd8f8a2-a521-4365-8c6e-955c1d3e6e6c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435434699 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.lc_ctrl_stress_all.3435434699
Directory /workspace/39.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all_with_rand_reset.1253764984
Short name T742
Test name
Test status
Simulation time 89564612506 ps
CPU time 938.28 seconds
Started Jun 13 01:45:40 PM PDT 24
Finished Jun 13 02:01:19 PM PDT 24
Peak memory 496836 kb
Host smart-958cfe25-a4be-45db-ba6b-26802abe110a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1253764984 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_stress_all_with_rand_reset.1253764984
Directory /workspace/39.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.lc_ctrl_volatile_unlock_smoke.1565340769
Short name T632
Test name
Test status
Simulation time 43607003 ps
CPU time 0.75 seconds
Started Jun 13 01:45:30 PM PDT 24
Finished Jun 13 01:45:32 PM PDT 24
Peak memory 209004 kb
Host smart-8aef3ba4-3008-45ea-9111-693cae14c4d8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565340769 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_c
trl_volatile_unlock_smoke.1565340769
Directory /workspace/39.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_alert_test.2996106872
Short name T231
Test name
Test status
Simulation time 50684489 ps
CPU time 0.93 seconds
Started Jun 13 01:41:58 PM PDT 24
Finished Jun 13 01:41:59 PM PDT 24
Peak memory 209012 kb
Host smart-6dc351b9-f498-4c79-a41c-8a0f54b53292
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996106872 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_alert_test.2996106872
Directory /workspace/4.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.lc_ctrl_errors.1469592550
Short name T168
Test name
Test status
Simulation time 272718912 ps
CPU time 9.73 seconds
Started Jun 13 01:41:55 PM PDT 24
Finished Jun 13 01:42:06 PM PDT 24
Peak memory 218296 kb
Host smart-cf4bf70b-5c47-4f23-8113-c89b3398ba01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469592550 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_errors.1469592550
Directory /workspace/4.lc_ctrl_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_access.138202978
Short name T517
Test name
Test status
Simulation time 1978206835 ps
CPU time 9.81 seconds
Started Jun 13 01:41:55 PM PDT 24
Finished Jun 13 01:42:05 PM PDT 24
Peak memory 217376 kb
Host smart-321de465-6bcb-48cb-a751-2473831cc1dc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138202978 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_access.138202978
Directory /workspace/4.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_errors.2873487196
Short name T844
Test name
Test status
Simulation time 1662118905 ps
CPU time 42.38 seconds
Started Jun 13 01:41:53 PM PDT 24
Finished Jun 13 01:42:37 PM PDT 24
Peak memory 218196 kb
Host smart-968804b7-6dc0-4b8e-804e-8b9be81eb217
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873487196 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_er
rors.2873487196
Directory /workspace/4.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_priority.325467347
Short name T557
Test name
Test status
Simulation time 762121419 ps
CPU time 6.06 seconds
Started Jun 13 01:41:52 PM PDT 24
Finished Jun 13 01:41:59 PM PDT 24
Peak memory 217820 kb
Host smart-00e76f1b-c83d-49a6-aa51-0bcd7e6b1e01
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325467347 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_priority.325467347
Directory /workspace/4.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_prog_failure.1495566084
Short name T680
Test name
Test status
Simulation time 320489209 ps
CPU time 10.57 seconds
Started Jun 13 01:41:53 PM PDT 24
Finished Jun 13 01:42:05 PM PDT 24
Peak memory 218220 kb
Host smart-94c52bcf-ae44-4bd7-b2b7-061487d845fa
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495566084 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag
_prog_failure.1495566084
Directory /workspace/4.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_regwen_during_op.538769716
Short name T513
Test name
Test status
Simulation time 2773769241 ps
CPU time 20.23 seconds
Started Jun 13 01:41:54 PM PDT 24
Finished Jun 13 01:42:15 PM PDT 24
Peak memory 217744 kb
Host smart-63ce7081-7537-466f-9453-744ce44b82eb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538769716 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_j
tag_regwen_during_op.538769716
Directory /workspace/4.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_smoke.2657112409
Short name T279
Test name
Test status
Simulation time 632002359 ps
CPU time 5.18 seconds
Started Jun 13 01:41:55 PM PDT 24
Finished Jun 13 01:42:01 PM PDT 24
Peak memory 217688 kb
Host smart-6e201de8-e3d5-4e1f-bc11-faf700f80dbc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657112409 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_smoke.
2657112409
Directory /workspace/4.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_failure.925898095
Short name T524
Test name
Test status
Simulation time 8544697097 ps
CPU time 53.43 seconds
Started Jun 13 01:41:51 PM PDT 24
Finished Jun 13 01:42:46 PM PDT 24
Peak memory 283660 kb
Host smart-2484ad87-63c0-4ac5-8d08-bea5efe0c0a3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925898095 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag
_state_failure.925898095
Directory /workspace/4.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_post_trans.1109126988
Short name T332
Test name
Test status
Simulation time 986550387 ps
CPU time 15.55 seconds
Started Jun 13 01:41:55 PM PDT 24
Finished Jun 13 01:42:12 PM PDT 24
Peak memory 226264 kb
Host smart-8a60b839-4211-49bc-be50-af265ad7e97b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109126988 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_state_post_trans.1109126988
Directory /workspace/4.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_prog_failure.3714840241
Short name T325
Test name
Test status
Simulation time 74142620 ps
CPU time 3.44 seconds
Started Jun 13 01:41:51 PM PDT 24
Finished Jun 13 01:41:56 PM PDT 24
Peak memory 218216 kb
Host smart-a6c3412f-bb0a-4538-870a-1c62a50b192b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714840241 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_prog_failure.3714840241
Directory /workspace/4.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_regwen_during_op.2734865625
Short name T714
Test name
Test status
Simulation time 572077442 ps
CPU time 15.82 seconds
Started Jun 13 01:41:53 PM PDT 24
Finished Jun 13 01:42:09 PM PDT 24
Peak memory 214620 kb
Host smart-76072442-4ed3-4ed0-8bb7-849ec9036d1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734865625 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_regwen_during_op.2734865625
Directory /workspace/4.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_cm.281367475
Short name T51
Test name
Test status
Simulation time 198252684 ps
CPU time 24.84 seconds
Started Jun 13 01:42:00 PM PDT 24
Finished Jun 13 01:42:27 PM PDT 24
Peak memory 269504 kb
Host smart-9bef6326-9ee3-4c76-b6ed-754dc06aebd4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281367475 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_cm.281367475
Directory /workspace/4.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_mubi.3728269661
Short name T389
Test name
Test status
Simulation time 624461636 ps
CPU time 16.39 seconds
Started Jun 13 01:41:55 PM PDT 24
Finished Jun 13 01:42:12 PM PDT 24
Peak memory 219000 kb
Host smart-6b28eb9e-267a-4ab4-b503-5badf8b11e69
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728269661 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_mubi.3728269661
Directory /workspace/4.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_digest.305066292
Short name T518
Test name
Test status
Simulation time 1331587897 ps
CPU time 10.13 seconds
Started Jun 13 01:42:00 PM PDT 24
Finished Jun 13 01:42:12 PM PDT 24
Peak memory 226060 kb
Host smart-821a521c-5517-4dd4-ae4d-050c1e592c2f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305066292 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_dig
est.305066292
Directory /workspace/4.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_mux.3141878149
Short name T739
Test name
Test status
Simulation time 202147874 ps
CPU time 6.04 seconds
Started Jun 13 01:41:53 PM PDT 24
Finished Jun 13 01:42:00 PM PDT 24
Peak memory 225040 kb
Host smart-37e169e5-37ef-4ecb-a698-ce010a48d7e2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141878149 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_mux.3
141878149
Directory /workspace/4.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/4.lc_ctrl_security_escalation.77155815
Short name T728
Test name
Test status
Simulation time 1325239659 ps
CPU time 7.57 seconds
Started Jun 13 01:41:56 PM PDT 24
Finished Jun 13 01:42:04 PM PDT 24
Peak memory 218256 kb
Host smart-7424f57f-a056-4349-be98-f35a2970246b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77155815 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_security_escalation.77155815
Directory /workspace/4.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/4.lc_ctrl_smoke.853264173
Short name T829
Test name
Test status
Simulation time 26598098 ps
CPU time 1.86 seconds
Started Jun 13 01:41:56 PM PDT 24
Finished Jun 13 01:41:59 PM PDT 24
Peak memory 213880 kb
Host smart-5ca15dfe-7dbc-41da-bae2-87cd8a230963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853264173 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_smoke.853264173
Directory /workspace/4.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_failure.1306441370
Short name T425
Test name
Test status
Simulation time 917388171 ps
CPU time 27.09 seconds
Started Jun 13 01:41:55 PM PDT 24
Finished Jun 13 01:42:23 PM PDT 24
Peak memory 250900 kb
Host smart-639f545f-b641-4740-a907-cf8171a0c491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306441370 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_failure.1306441370
Directory /workspace/4.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_post_trans.2469209124
Short name T766
Test name
Test status
Simulation time 157415914 ps
CPU time 8.01 seconds
Started Jun 13 01:41:51 PM PDT 24
Finished Jun 13 01:42:00 PM PDT 24
Peak memory 246544 kb
Host smart-b100668a-ac1e-4bdd-b0a8-f90a3d14368d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469209124 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_post_trans.2469209124
Directory /workspace/4.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_stress_all.2104975416
Short name T44
Test name
Test status
Simulation time 13817525838 ps
CPU time 47.42 seconds
Started Jun 13 01:42:00 PM PDT 24
Finished Jun 13 01:42:49 PM PDT 24
Peak memory 226128 kb
Host smart-a6f2d622-33f9-4628-b8ad-12e89d788c24
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104975416 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.lc_ctrl_stress_all.2104975416
Directory /workspace/4.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.lc_ctrl_volatile_unlock_smoke.2593174022
Short name T713
Test name
Test status
Simulation time 33038491 ps
CPU time 0.76 seconds
Started Jun 13 01:41:53 PM PDT 24
Finished Jun 13 01:41:55 PM PDT 24
Peak memory 208740 kb
Host smart-bfdace16-e282-477b-a263-2f7eed00b21f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593174022 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ct
rl_volatile_unlock_smoke.2593174022
Directory /workspace/4.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_alert_test.1757132740
Short name T753
Test name
Test status
Simulation time 206083756 ps
CPU time 0.94 seconds
Started Jun 13 01:45:44 PM PDT 24
Finished Jun 13 01:45:46 PM PDT 24
Peak memory 209016 kb
Host smart-764283d5-c756-477a-a611-6f6afbeec4fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757132740 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_alert_test.1757132740
Directory /workspace/40.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.lc_ctrl_errors.2707096715
Short name T529
Test name
Test status
Simulation time 1060221525 ps
CPU time 10.77 seconds
Started Jun 13 01:45:38 PM PDT 24
Finished Jun 13 01:45:50 PM PDT 24
Peak memory 218284 kb
Host smart-e8df0a79-7c19-4f99-ae46-1d7ae377ff60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707096715 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_errors.2707096715
Directory /workspace/40.lc_ctrl_errors/latest

Test location /workspace/coverage/default/40.lc_ctrl_jtag_access.1778482123
Short name T174
Test name
Test status
Simulation time 610598411 ps
CPU time 5.39 seconds
Started Jun 13 01:45:39 PM PDT 24
Finished Jun 13 01:45:45 PM PDT 24
Peak memory 217232 kb
Host smart-85c12a51-8196-4650-b20c-c7b2408515b2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778482123 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_jtag_access.1778482123
Directory /workspace/40.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/40.lc_ctrl_prog_failure.1993348684
Short name T224
Test name
Test status
Simulation time 258494973 ps
CPU time 3.04 seconds
Started Jun 13 01:45:46 PM PDT 24
Finished Jun 13 01:45:50 PM PDT 24
Peak memory 218216 kb
Host smart-edc44c63-9985-4cd5-9a19-38c59c17522e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993348684 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_prog_failure.1993348684
Directory /workspace/40.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_mubi.3361518433
Short name T170
Test name
Test status
Simulation time 1303359588 ps
CPU time 26.81 seconds
Started Jun 13 01:45:38 PM PDT 24
Finished Jun 13 01:46:05 PM PDT 24
Peak memory 218960 kb
Host smart-6da12aa1-0f63-46e7-811c-52407e496029
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361518433 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_mubi.3361518433
Directory /workspace/40.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_digest.1419781746
Short name T249
Test name
Test status
Simulation time 1110818515 ps
CPU time 9.15 seconds
Started Jun 13 01:45:42 PM PDT 24
Finished Jun 13 01:45:53 PM PDT 24
Peak memory 225816 kb
Host smart-163ec25b-7eed-4608-bd50-09e367966853
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419781746 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_d
igest.1419781746
Directory /workspace/40.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_mux.409983630
Short name T804
Test name
Test status
Simulation time 3333257776 ps
CPU time 11.63 seconds
Started Jun 13 01:45:37 PM PDT 24
Finished Jun 13 01:45:49 PM PDT 24
Peak memory 218316 kb
Host smart-181de445-5348-441a-9a51-a3784fcfd9a0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409983630 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_mux.409983630
Directory /workspace/40.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/40.lc_ctrl_security_escalation.3495566613
Short name T520
Test name
Test status
Simulation time 1782348094 ps
CPU time 10.11 seconds
Started Jun 13 01:45:38 PM PDT 24
Finished Jun 13 01:45:48 PM PDT 24
Peak memory 218280 kb
Host smart-3592e4e0-1c18-4c63-880e-3e99ce2d8de2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495566613 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_security_escalation.3495566613
Directory /workspace/40.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/40.lc_ctrl_smoke.527563603
Short name T705
Test name
Test status
Simulation time 197925665 ps
CPU time 2.58 seconds
Started Jun 13 01:45:37 PM PDT 24
Finished Jun 13 01:45:40 PM PDT 24
Peak memory 214548 kb
Host smart-556a6fe4-b7da-46ba-8a31-6b1728e37afa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=527563603 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_smoke.527563603
Directory /workspace/40.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_failure.1513807289
Short name T207
Test name
Test status
Simulation time 501373450 ps
CPU time 25.25 seconds
Started Jun 13 01:45:38 PM PDT 24
Finished Jun 13 01:46:04 PM PDT 24
Peak memory 250912 kb
Host smart-748014f1-0a8f-4ddc-a7b0-60e14a0c938a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513807289 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_failure.1513807289
Directory /workspace/40.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_post_trans.672963159
Short name T320
Test name
Test status
Simulation time 201833804 ps
CPU time 3.08 seconds
Started Jun 13 01:45:36 PM PDT 24
Finished Jun 13 01:45:40 PM PDT 24
Peak memory 218144 kb
Host smart-3754a9ed-fd02-424e-ab8f-395fc9bc68f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672963159 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_post_trans.672963159
Directory /workspace/40.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/40.lc_ctrl_stress_all.2333745260
Short name T458
Test name
Test status
Simulation time 164185135757 ps
CPU time 250.65 seconds
Started Jun 13 01:45:43 PM PDT 24
Finished Jun 13 01:49:54 PM PDT 24
Peak memory 281992 kb
Host smart-bc07c2e1-968e-4210-8af0-90b2d7cf0993
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333745260 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.lc_ctrl_stress_all.2333745260
Directory /workspace/40.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.lc_ctrl_volatile_unlock_smoke.4254447640
Short name T721
Test name
Test status
Simulation time 14221535 ps
CPU time 0.89 seconds
Started Jun 13 01:45:40 PM PDT 24
Finished Jun 13 01:45:41 PM PDT 24
Peak memory 208924 kb
Host smart-4d845276-5397-45b8-86cb-b61f48ea8c80
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254447640 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_c
trl_volatile_unlock_smoke.4254447640
Directory /workspace/40.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_alert_test.231010772
Short name T590
Test name
Test status
Simulation time 51394118 ps
CPU time 0.9 seconds
Started Jun 13 01:45:54 PM PDT 24
Finished Jun 13 01:45:56 PM PDT 24
Peak memory 209032 kb
Host smart-755ca002-15d1-41e6-88d5-61c3b8b4cde9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231010772 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_alert_test.231010772
Directory /workspace/41.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.lc_ctrl_errors.3248883488
Short name T473
Test name
Test status
Simulation time 1417906520 ps
CPU time 10.76 seconds
Started Jun 13 01:45:41 PM PDT 24
Finished Jun 13 01:45:52 PM PDT 24
Peak memory 218208 kb
Host smart-f9ddd911-6e82-4bd7-b326-d7297d6d297b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248883488 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_errors.3248883488
Directory /workspace/41.lc_ctrl_errors/latest

Test location /workspace/coverage/default/41.lc_ctrl_jtag_access.4140483565
Short name T90
Test name
Test status
Simulation time 49381109 ps
CPU time 1.24 seconds
Started Jun 13 01:45:45 PM PDT 24
Finished Jun 13 01:45:48 PM PDT 24
Peak memory 217140 kb
Host smart-402c874f-e125-43ca-bacc-8cdafac96809
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140483565 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_jtag_access.4140483565
Directory /workspace/41.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/41.lc_ctrl_prog_failure.3992410498
Short name T709
Test name
Test status
Simulation time 379321936 ps
CPU time 3.42 seconds
Started Jun 13 01:45:47 PM PDT 24
Finished Jun 13 01:45:51 PM PDT 24
Peak memory 218216 kb
Host smart-3418b0ae-8969-4552-9459-f79c17ace6dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992410498 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_prog_failure.3992410498
Directory /workspace/41.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_mubi.1380100606
Short name T552
Test name
Test status
Simulation time 214317973 ps
CPU time 9.94 seconds
Started Jun 13 01:45:42 PM PDT 24
Finished Jun 13 01:45:53 PM PDT 24
Peak memory 226048 kb
Host smart-c05b9557-73da-4816-87fb-890ad6ba0db0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380100606 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_mubi.1380100606
Directory /workspace/41.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_digest.550678548
Short name T232
Test name
Test status
Simulation time 478626381 ps
CPU time 12.43 seconds
Started Jun 13 01:45:42 PM PDT 24
Finished Jun 13 01:45:56 PM PDT 24
Peak memory 218260 kb
Host smart-22f8ab66-3b7a-4e26-abdd-0d3843d10682
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550678548 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_di
gest.550678548
Directory /workspace/41.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_mux.806164483
Short name T328
Test name
Test status
Simulation time 479445903 ps
CPU time 7.74 seconds
Started Jun 13 01:45:41 PM PDT 24
Finished Jun 13 01:45:50 PM PDT 24
Peak memory 218288 kb
Host smart-25ca1ba4-33d5-423b-948d-3ce9783403db
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806164483 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_mux.806164483
Directory /workspace/41.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/41.lc_ctrl_security_escalation.367973823
Short name T203
Test name
Test status
Simulation time 957495038 ps
CPU time 7.97 seconds
Started Jun 13 01:45:45 PM PDT 24
Finished Jun 13 01:45:54 PM PDT 24
Peak memory 218372 kb
Host smart-b7bd5adf-596f-42e9-8033-e81ca2207f97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367973823 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_security_escalation.367973823
Directory /workspace/41.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/41.lc_ctrl_smoke.629415718
Short name T592
Test name
Test status
Simulation time 108774318 ps
CPU time 2.81 seconds
Started Jun 13 01:45:42 PM PDT 24
Finished Jun 13 01:45:46 PM PDT 24
Peak memory 214656 kb
Host smart-70d9d7b5-e73c-4d37-ab8b-d40191e505fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629415718 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_smoke.629415718
Directory /workspace/41.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_failure.4091899083
Short name T491
Test name
Test status
Simulation time 1067491188 ps
CPU time 28.71 seconds
Started Jun 13 01:45:42 PM PDT 24
Finished Jun 13 01:46:11 PM PDT 24
Peak memory 250972 kb
Host smart-31d8448b-1803-4823-b6ea-c9f53cc1a808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091899083 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_failure.4091899083
Directory /workspace/41.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_post_trans.3142105735
Short name T239
Test name
Test status
Simulation time 90221931 ps
CPU time 8 seconds
Started Jun 13 01:45:44 PM PDT 24
Finished Jun 13 01:45:54 PM PDT 24
Peak memory 250912 kb
Host smart-bd285920-ae86-4344-867e-2a3a931e190f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142105735 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_post_trans.3142105735
Directory /workspace/41.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all.28938523
Short name T483
Test name
Test status
Simulation time 19360946080 ps
CPU time 156.61 seconds
Started Jun 13 01:45:53 PM PDT 24
Finished Jun 13 01:48:31 PM PDT 24
Peak memory 275468 kb
Host smart-420c4415-2028-4c6a-997d-18279ddf4701
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28938523 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_T
EST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
1.lc_ctrl_stress_all.28938523
Directory /workspace/41.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.lc_ctrl_volatile_unlock_smoke.4222181051
Short name T27
Test name
Test status
Simulation time 14015816 ps
CPU time 1.13 seconds
Started Jun 13 01:45:42 PM PDT 24
Finished Jun 13 01:45:45 PM PDT 24
Peak memory 212028 kb
Host smart-a887bfe9-429f-451c-824a-f4c382f8ac6d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222181051 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_c
trl_volatile_unlock_smoke.4222181051
Directory /workspace/41.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_alert_test.2268327267
Short name T509
Test name
Test status
Simulation time 28173972 ps
CPU time 1.38 seconds
Started Jun 13 01:45:53 PM PDT 24
Finished Jun 13 01:45:56 PM PDT 24
Peak memory 209068 kb
Host smart-f2786568-efc6-45c5-85a4-679c47149d2e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268327267 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_alert_test.2268327267
Directory /workspace/42.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.lc_ctrl_errors.3971906060
Short name T788
Test name
Test status
Simulation time 2433396389 ps
CPU time 17.61 seconds
Started Jun 13 01:45:55 PM PDT 24
Finished Jun 13 01:46:13 PM PDT 24
Peak memory 219108 kb
Host smart-f32bc6ab-e1b5-4b8b-b132-3a3b999e1a32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971906060 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_errors.3971906060
Directory /workspace/42.lc_ctrl_errors/latest

Test location /workspace/coverage/default/42.lc_ctrl_jtag_access.3133692050
Short name T782
Test name
Test status
Simulation time 247070905 ps
CPU time 6.72 seconds
Started Jun 13 01:45:54 PM PDT 24
Finished Jun 13 01:46:02 PM PDT 24
Peak memory 217448 kb
Host smart-116b1112-1922-4698-8278-7aac08551c6d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133692050 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_jtag_access.3133692050
Directory /workspace/42.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/42.lc_ctrl_prog_failure.3129379236
Short name T59
Test name
Test status
Simulation time 143073145 ps
CPU time 3.39 seconds
Started Jun 13 01:45:52 PM PDT 24
Finished Jun 13 01:45:57 PM PDT 24
Peak memory 218188 kb
Host smart-4bb23254-c889-43d6-9a56-75ba694143b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129379236 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_prog_failure.3129379236
Directory /workspace/42.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_mubi.2161498468
Short name T633
Test name
Test status
Simulation time 1129662149 ps
CPU time 13.18 seconds
Started Jun 13 01:45:54 PM PDT 24
Finished Jun 13 01:46:09 PM PDT 24
Peak memory 218912 kb
Host smart-a698a7d0-9a85-4b06-a166-c95528b8e350
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161498468 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_mubi.2161498468
Directory /workspace/42.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_digest.4253442177
Short name T554
Test name
Test status
Simulation time 979001641 ps
CPU time 11.07 seconds
Started Jun 13 01:45:51 PM PDT 24
Finished Jun 13 01:46:03 PM PDT 24
Peak memory 218228 kb
Host smart-0e8b6e26-8df0-43b1-b06b-4c6393bfaad1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253442177 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_d
igest.4253442177
Directory /workspace/42.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_mux.2083454121
Short name T858
Test name
Test status
Simulation time 731233554 ps
CPU time 12.02 seconds
Started Jun 13 01:45:53 PM PDT 24
Finished Jun 13 01:46:07 PM PDT 24
Peak memory 218284 kb
Host smart-66c05c2d-99e3-4a6b-9cf7-727c37d6a7c3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083454121 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_mux.
2083454121
Directory /workspace/42.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/42.lc_ctrl_security_escalation.2014630140
Short name T392
Test name
Test status
Simulation time 398279173 ps
CPU time 9.89 seconds
Started Jun 13 01:45:56 PM PDT 24
Finished Jun 13 01:46:07 PM PDT 24
Peak memory 226068 kb
Host smart-2df80b50-81dc-443f-99bb-4eaddb03cf40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014630140 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_security_escalation.2014630140
Directory /workspace/42.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/42.lc_ctrl_smoke.1335498153
Short name T72
Test name
Test status
Simulation time 116360919 ps
CPU time 2.69 seconds
Started Jun 13 01:45:59 PM PDT 24
Finished Jun 13 01:46:03 PM PDT 24
Peak memory 214772 kb
Host smart-85cc003a-0fe8-41e6-bb65-a6e1ce2693d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335498153 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_smoke.1335498153
Directory /workspace/42.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_failure.3552559487
Short name T549
Test name
Test status
Simulation time 354242681 ps
CPU time 32.56 seconds
Started Jun 13 01:45:54 PM PDT 24
Finished Jun 13 01:46:27 PM PDT 24
Peak memory 250916 kb
Host smart-dda21dd7-e626-4836-87a9-67db5318437a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552559487 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_failure.3552559487
Directory /workspace/42.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_post_trans.53975795
Short name T741
Test name
Test status
Simulation time 50262874 ps
CPU time 6.79 seconds
Started Jun 13 01:45:54 PM PDT 24
Finished Jun 13 01:46:02 PM PDT 24
Peak memory 250440 kb
Host smart-c131641f-0626-4097-96a6-a7acfd1c4c46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53975795 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_post_trans.53975795
Directory /workspace/42.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/42.lc_ctrl_stress_all.2918862671
Short name T647
Test name
Test status
Simulation time 16972518349 ps
CPU time 56.09 seconds
Started Jun 13 01:45:52 PM PDT 24
Finished Jun 13 01:46:49 PM PDT 24
Peak memory 250940 kb
Host smart-745df6c0-b1ab-4e24-afe5-1df3ca85193f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918862671 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.lc_ctrl_stress_all.2918862671
Directory /workspace/42.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.lc_ctrl_volatile_unlock_smoke.104328812
Short name T29
Test name
Test status
Simulation time 26155035 ps
CPU time 0.87 seconds
Started Jun 13 01:45:51 PM PDT 24
Finished Jun 13 01:45:53 PM PDT 24
Peak memory 209124 kb
Host smart-567c8b20-d14c-43ca-9cd5-f5461c338263
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104328812 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ct
rl_volatile_unlock_smoke.104328812
Directory /workspace/42.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_alert_test.769639405
Short name T349
Test name
Test status
Simulation time 40575496 ps
CPU time 1.29 seconds
Started Jun 13 01:45:57 PM PDT 24
Finished Jun 13 01:45:58 PM PDT 24
Peak memory 209052 kb
Host smart-97dc20bc-8ae0-4ce9-be8c-01f73024e00a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769639405 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_alert_test.769639405
Directory /workspace/43.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.lc_ctrl_errors.1317994650
Short name T868
Test name
Test status
Simulation time 456687693 ps
CPU time 7.84 seconds
Started Jun 13 01:45:52 PM PDT 24
Finished Jun 13 01:46:01 PM PDT 24
Peak memory 218224 kb
Host smart-88918f1e-ec6b-4309-854d-ea74a42d785c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317994650 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_errors.1317994650
Directory /workspace/43.lc_ctrl_errors/latest

Test location /workspace/coverage/default/43.lc_ctrl_jtag_access.1476343805
Short name T352
Test name
Test status
Simulation time 332713577 ps
CPU time 2.22 seconds
Started Jun 13 01:45:51 PM PDT 24
Finished Jun 13 01:45:53 PM PDT 24
Peak memory 217048 kb
Host smart-55cba87a-de3a-46a5-81a0-030028264258
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476343805 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_jtag_access.1476343805
Directory /workspace/43.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/43.lc_ctrl_prog_failure.4126502407
Short name T812
Test name
Test status
Simulation time 47899099 ps
CPU time 3.19 seconds
Started Jun 13 01:45:51 PM PDT 24
Finished Jun 13 01:45:55 PM PDT 24
Peak memory 218180 kb
Host smart-fd7ee877-3048-490c-88e4-923a3ed0223b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126502407 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_prog_failure.4126502407
Directory /workspace/43.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_mubi.826069267
Short name T679
Test name
Test status
Simulation time 348682962 ps
CPU time 14.55 seconds
Started Jun 13 01:45:51 PM PDT 24
Finished Jun 13 01:46:06 PM PDT 24
Peak memory 218916 kb
Host smart-73ab3cce-fa33-4303-b5a2-30b44e51a0b1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826069267 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_mubi.826069267
Directory /workspace/43.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_digest.2704260350
Short name T252
Test name
Test status
Simulation time 447713655 ps
CPU time 10.71 seconds
Started Jun 13 01:45:54 PM PDT 24
Finished Jun 13 01:46:06 PM PDT 24
Peak memory 218264 kb
Host smart-48d4f25e-b878-40ef-b3a3-47cc53c3ba51
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704260350 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_d
igest.2704260350
Directory /workspace/43.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_mux.2078930482
Short name T35
Test name
Test status
Simulation time 2059655517 ps
CPU time 14.11 seconds
Started Jun 13 01:45:52 PM PDT 24
Finished Jun 13 01:46:08 PM PDT 24
Peak memory 218144 kb
Host smart-d48b0671-e14b-44ba-8dd5-e52cfff82d49
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078930482 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_mux.
2078930482
Directory /workspace/43.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/43.lc_ctrl_smoke.3883340597
Short name T322
Test name
Test status
Simulation time 127703726 ps
CPU time 2.11 seconds
Started Jun 13 01:45:56 PM PDT 24
Finished Jun 13 01:45:58 PM PDT 24
Peak memory 217760 kb
Host smart-e98f515e-4fa6-4acf-8da9-43d8305e4b7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883340597 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_smoke.3883340597
Directory /workspace/43.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_failure.2413405612
Short name T97
Test name
Test status
Simulation time 1593747426 ps
CPU time 29.56 seconds
Started Jun 13 01:45:53 PM PDT 24
Finished Jun 13 01:46:24 PM PDT 24
Peak memory 250900 kb
Host smart-deaf9ee7-4d03-42f6-96f2-a7a6d0464fda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413405612 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_failure.2413405612
Directory /workspace/43.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_post_trans.2128611088
Short name T756
Test name
Test status
Simulation time 46977859 ps
CPU time 6.57 seconds
Started Jun 13 01:45:56 PM PDT 24
Finished Jun 13 01:46:03 PM PDT 24
Peak memory 250216 kb
Host smart-1cd98461-7383-41a5-a407-dae5b567e923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128611088 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_post_trans.2128611088
Directory /workspace/43.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/43.lc_ctrl_volatile_unlock_smoke.1515636924
Short name T285
Test name
Test status
Simulation time 20080063 ps
CPU time 0.91 seconds
Started Jun 13 01:45:52 PM PDT 24
Finished Jun 13 01:45:54 PM PDT 24
Peak memory 213012 kb
Host smart-8f1724b2-a0d9-42ff-98d2-3427817717ae
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515636924 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_c
trl_volatile_unlock_smoke.1515636924
Directory /workspace/43.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_alert_test.2767666176
Short name T404
Test name
Test status
Simulation time 19584183 ps
CPU time 1.16 seconds
Started Jun 13 01:45:59 PM PDT 24
Finished Jun 13 01:46:01 PM PDT 24
Peak memory 209036 kb
Host smart-302cd4c6-f07e-457c-9d2e-d5a5e848b6be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767666176 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_alert_test.2767666176
Directory /workspace/44.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.lc_ctrl_errors.2201660285
Short name T324
Test name
Test status
Simulation time 292264712 ps
CPU time 12.32 seconds
Started Jun 13 01:46:01 PM PDT 24
Finished Jun 13 01:46:14 PM PDT 24
Peak memory 218144 kb
Host smart-9d908c32-f3b7-40fa-9b64-de15228aa6b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201660285 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_errors.2201660285
Directory /workspace/44.lc_ctrl_errors/latest

Test location /workspace/coverage/default/44.lc_ctrl_jtag_access.2938812045
Short name T689
Test name
Test status
Simulation time 683489489 ps
CPU time 2.06 seconds
Started Jun 13 01:45:58 PM PDT 24
Finished Jun 13 01:46:01 PM PDT 24
Peak memory 217168 kb
Host smart-d4243ed5-273f-4ae4-b70c-a8c89829fe9d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938812045 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_jtag_access.2938812045
Directory /workspace/44.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/44.lc_ctrl_prog_failure.682937555
Short name T546
Test name
Test status
Simulation time 46731886 ps
CPU time 2 seconds
Started Jun 13 01:45:59 PM PDT 24
Finished Jun 13 01:46:02 PM PDT 24
Peak memory 218220 kb
Host smart-6ef6d19d-dfb1-4a9b-9acf-becd664fbbae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682937555 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_prog_failure.682937555
Directory /workspace/44.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_mubi.2774673194
Short name T566
Test name
Test status
Simulation time 221772686 ps
CPU time 9.09 seconds
Started Jun 13 01:46:01 PM PDT 24
Finished Jun 13 01:46:11 PM PDT 24
Peak memory 226168 kb
Host smart-557047e2-dce6-442b-ac85-da163ef66724
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774673194 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_mubi.2774673194
Directory /workspace/44.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_digest.889577228
Short name T438
Test name
Test status
Simulation time 240127749 ps
CPU time 9.93 seconds
Started Jun 13 01:46:00 PM PDT 24
Finished Jun 13 01:46:10 PM PDT 24
Peak memory 218252 kb
Host smart-a826a4dc-fed1-4c61-b659-db1512e8553b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889577228 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_di
gest.889577228
Directory /workspace/44.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_mux.3441621427
Short name T304
Test name
Test status
Simulation time 465482555 ps
CPU time 9.13 seconds
Started Jun 13 01:46:06 PM PDT 24
Finished Jun 13 01:46:16 PM PDT 24
Peak memory 218152 kb
Host smart-8fc02021-c76a-4a42-8398-81dc63c70726
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441621427 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_mux.
3441621427
Directory /workspace/44.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/44.lc_ctrl_security_escalation.2624951981
Short name T345
Test name
Test status
Simulation time 2415033524 ps
CPU time 9.78 seconds
Started Jun 13 01:45:57 PM PDT 24
Finished Jun 13 01:46:07 PM PDT 24
Peak memory 218220 kb
Host smart-a7b5eb87-e8f0-4418-92e8-7579c3df0d46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624951981 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_security_escalation.2624951981
Directory /workspace/44.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/44.lc_ctrl_smoke.3794484181
Short name T798
Test name
Test status
Simulation time 162717101 ps
CPU time 2.36 seconds
Started Jun 13 01:46:01 PM PDT 24
Finished Jun 13 01:46:04 PM PDT 24
Peak memory 214184 kb
Host smart-c4a0a58d-c058-4f55-8877-7c4141104a7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794484181 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_smoke.3794484181
Directory /workspace/44.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_failure.844716478
Short name T768
Test name
Test status
Simulation time 341542599 ps
CPU time 28.83 seconds
Started Jun 13 01:45:59 PM PDT 24
Finished Jun 13 01:46:28 PM PDT 24
Peak memory 251012 kb
Host smart-2ed852f4-a550-4130-b51e-a8e351b77452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844716478 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_failure.844716478
Directory /workspace/44.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_post_trans.442430323
Short name T594
Test name
Test status
Simulation time 81066139 ps
CPU time 7.64 seconds
Started Jun 13 01:46:01 PM PDT 24
Finished Jun 13 01:46:10 PM PDT 24
Peak memory 250588 kb
Host smart-905975b4-d9da-447c-a7e4-ecf41293d972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442430323 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_post_trans.442430323
Directory /workspace/44.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/44.lc_ctrl_stress_all.1961626692
Short name T219
Test name
Test status
Simulation time 11288471369 ps
CPU time 109.21 seconds
Started Jun 13 01:45:57 PM PDT 24
Finished Jun 13 01:47:47 PM PDT 24
Peak memory 282380 kb
Host smart-2902c1f5-fa7c-4d06-86a2-141c1e8e5e2a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961626692 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.lc_ctrl_stress_all.1961626692
Directory /workspace/44.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.lc_ctrl_volatile_unlock_smoke.2910980187
Short name T360
Test name
Test status
Simulation time 47540002 ps
CPU time 0.91 seconds
Started Jun 13 01:45:58 PM PDT 24
Finished Jun 13 01:46:00 PM PDT 24
Peak memory 217808 kb
Host smart-7b8731ce-ed53-47a4-924f-fc1ee859a6c3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910980187 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_c
trl_volatile_unlock_smoke.2910980187
Directory /workspace/44.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_alert_test.3823633543
Short name T287
Test name
Test status
Simulation time 14916419 ps
CPU time 1.09 seconds
Started Jun 13 01:46:08 PM PDT 24
Finished Jun 13 01:46:10 PM PDT 24
Peak memory 209108 kb
Host smart-e8f83e33-c87a-4488-912d-ede518b23b12
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823633543 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_alert_test.3823633543
Directory /workspace/45.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.lc_ctrl_errors.3057849659
Short name T294
Test name
Test status
Simulation time 1602259952 ps
CPU time 17.69 seconds
Started Jun 13 01:45:58 PM PDT 24
Finished Jun 13 01:46:17 PM PDT 24
Peak memory 218244 kb
Host smart-9201432a-2102-4d70-9875-bea6f0286a1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057849659 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_errors.3057849659
Directory /workspace/45.lc_ctrl_errors/latest

Test location /workspace/coverage/default/45.lc_ctrl_jtag_access.1977847323
Short name T355
Test name
Test status
Simulation time 34430693 ps
CPU time 1.15 seconds
Started Jun 13 01:46:06 PM PDT 24
Finished Jun 13 01:46:09 PM PDT 24
Peak memory 217004 kb
Host smart-44f9bb7d-4eee-4a9a-b083-c8f8b8888800
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977847323 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_jtag_access.1977847323
Directory /workspace/45.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/45.lc_ctrl_prog_failure.1242592787
Short name T702
Test name
Test status
Simulation time 78108038 ps
CPU time 2.63 seconds
Started Jun 13 01:45:59 PM PDT 24
Finished Jun 13 01:46:03 PM PDT 24
Peak memory 222188 kb
Host smart-305b3910-075f-4b09-97a3-55352f9d2a1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242592787 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_prog_failure.1242592787
Directory /workspace/45.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_mubi.272419513
Short name T12
Test name
Test status
Simulation time 1649244855 ps
CPU time 10.4 seconds
Started Jun 13 01:46:05 PM PDT 24
Finished Jun 13 01:46:17 PM PDT 24
Peak memory 218284 kb
Host smart-ed809056-6d1c-4457-969f-2e5ec9a8e572
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272419513 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_mubi.272419513
Directory /workspace/45.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_digest.148051452
Short name T92
Test name
Test status
Simulation time 1113995185 ps
CPU time 11.12 seconds
Started Jun 13 01:46:05 PM PDT 24
Finished Jun 13 01:46:19 PM PDT 24
Peak memory 218192 kb
Host smart-989c2489-2deb-494e-834d-bcbcc974b0f3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148051452 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_di
gest.148051452
Directory /workspace/45.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_mux.1956527421
Short name T511
Test name
Test status
Simulation time 723015979 ps
CPU time 9.55 seconds
Started Jun 13 01:45:58 PM PDT 24
Finished Jun 13 01:46:07 PM PDT 24
Peak memory 224956 kb
Host smart-40903f8b-cade-4f97-b923-e0f75f6e2cd4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956527421 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_mux.
1956527421
Directory /workspace/45.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/45.lc_ctrl_security_escalation.565988153
Short name T745
Test name
Test status
Simulation time 753939362 ps
CPU time 9.39 seconds
Started Jun 13 01:45:59 PM PDT 24
Finished Jun 13 01:46:09 PM PDT 24
Peak memory 226056 kb
Host smart-50dff2f7-6ff5-472c-9fa1-6ebd679a563f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565988153 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_security_escalation.565988153
Directory /workspace/45.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/45.lc_ctrl_smoke.1915277364
Short name T296
Test name
Test status
Simulation time 104311645 ps
CPU time 2.02 seconds
Started Jun 13 01:46:06 PM PDT 24
Finished Jun 13 01:46:10 PM PDT 24
Peak memory 217760 kb
Host smart-af91d265-2a7a-4d90-a205-3651156fc4cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915277364 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_smoke.1915277364
Directory /workspace/45.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_post_trans.3181794610
Short name T708
Test name
Test status
Simulation time 207303046 ps
CPU time 3.3 seconds
Started Jun 13 01:45:58 PM PDT 24
Finished Jun 13 01:46:01 PM PDT 24
Peak memory 218252 kb
Host smart-292d4874-675b-490c-975f-5726c962e2c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181794610 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_post_trans.3181794610
Directory /workspace/45.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/45.lc_ctrl_stress_all.3947944720
Short name T644
Test name
Test status
Simulation time 6828818241 ps
CPU time 127.61 seconds
Started Jun 13 01:46:04 PM PDT 24
Finished Jun 13 01:48:12 PM PDT 24
Peak memory 283748 kb
Host smart-4d6def10-ce6a-4b2b-bd1f-b6f7b7f9f576
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947944720 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.lc_ctrl_stress_all.3947944720
Directory /workspace/45.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.lc_ctrl_stress_all_with_rand_reset.4232704196
Short name T139
Test name
Test status
Simulation time 27113176498 ps
CPU time 2127.04 seconds
Started Jun 13 01:46:05 PM PDT 24
Finished Jun 13 02:21:34 PM PDT 24
Peak memory 934384 kb
Host smart-10db7992-1d20-4423-b785-5d3ec7cc33ee
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4232704196 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_stress_all_with_rand_reset.4232704196
Directory /workspace/45.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.lc_ctrl_volatile_unlock_smoke.1188998308
Short name T220
Test name
Test status
Simulation time 19537212 ps
CPU time 1.46 seconds
Started Jun 13 01:45:58 PM PDT 24
Finished Jun 13 01:46:00 PM PDT 24
Peak memory 217916 kb
Host smart-7f6e8dd6-7c45-437a-b937-ce7d334706b7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188998308 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_c
trl_volatile_unlock_smoke.1188998308
Directory /workspace/45.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_alert_test.2383132813
Short name T786
Test name
Test status
Simulation time 66735589 ps
CPU time 0.95 seconds
Started Jun 13 01:46:04 PM PDT 24
Finished Jun 13 01:46:06 PM PDT 24
Peak memory 209052 kb
Host smart-c36fc9ef-70e0-46f4-a2b4-e95cc961c1f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383132813 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_alert_test.2383132813
Directory /workspace/46.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.lc_ctrl_errors.2747599999
Short name T39
Test name
Test status
Simulation time 1343608147 ps
CPU time 12.34 seconds
Started Jun 13 01:46:05 PM PDT 24
Finished Jun 13 01:46:18 PM PDT 24
Peak memory 218216 kb
Host smart-d2fb5d58-1eba-4af6-b92f-0944044faac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747599999 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_errors.2747599999
Directory /workspace/46.lc_ctrl_errors/latest

Test location /workspace/coverage/default/46.lc_ctrl_jtag_access.1802578037
Short name T794
Test name
Test status
Simulation time 2888079353 ps
CPU time 7.97 seconds
Started Jun 13 01:46:04 PM PDT 24
Finished Jun 13 01:46:13 PM PDT 24
Peak memory 217424 kb
Host smart-eff76331-a527-4d96-b25e-d069e14e4e06
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802578037 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_jtag_access.1802578037
Directory /workspace/46.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/46.lc_ctrl_prog_failure.940814401
Short name T710
Test name
Test status
Simulation time 221339934 ps
CPU time 3.28 seconds
Started Jun 13 01:46:03 PM PDT 24
Finished Jun 13 01:46:08 PM PDT 24
Peak memory 218220 kb
Host smart-7a257e88-bb20-488b-9722-cec026b797bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940814401 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_prog_failure.940814401
Directory /workspace/46.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_mubi.1099459964
Short name T503
Test name
Test status
Simulation time 339620845 ps
CPU time 15.32 seconds
Started Jun 13 01:46:05 PM PDT 24
Finished Jun 13 01:46:23 PM PDT 24
Peak memory 218268 kb
Host smart-c36abd72-6bb5-4f2a-8553-c3c1bc48e2cc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099459964 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_mubi.1099459964
Directory /workspace/46.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_digest.3983365897
Short name T860
Test name
Test status
Simulation time 241958463 ps
CPU time 11 seconds
Started Jun 13 01:46:02 PM PDT 24
Finished Jun 13 01:46:15 PM PDT 24
Peak memory 225704 kb
Host smart-99ffcfa1-00e3-4961-b415-d42df7d936e4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983365897 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_d
igest.3983365897
Directory /workspace/46.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_mux.3174082524
Short name T823
Test name
Test status
Simulation time 279589645 ps
CPU time 10.86 seconds
Started Jun 13 01:46:05 PM PDT 24
Finished Jun 13 01:46:18 PM PDT 24
Peak memory 226120 kb
Host smart-ce3b5120-da6f-4dec-ba07-20e01a509a85
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174082524 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_mux.
3174082524
Directory /workspace/46.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/46.lc_ctrl_security_escalation.2478346151
Short name T561
Test name
Test status
Simulation time 4799855646 ps
CPU time 10.55 seconds
Started Jun 13 01:46:06 PM PDT 24
Finished Jun 13 01:46:19 PM PDT 24
Peak memory 218336 kb
Host smart-c94a0aa3-4121-451e-b031-d227cad9f80d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478346151 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_security_escalation.2478346151
Directory /workspace/46.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/46.lc_ctrl_smoke.3554603836
Short name T484
Test name
Test status
Simulation time 16604388 ps
CPU time 1.4 seconds
Started Jun 13 01:46:04 PM PDT 24
Finished Jun 13 01:46:06 PM PDT 24
Peak memory 217832 kb
Host smart-40667789-abcd-4284-a10d-0f267def5210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554603836 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_smoke.3554603836
Directory /workspace/46.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_failure.3669090293
Short name T85
Test name
Test status
Simulation time 255753692 ps
CPU time 34.26 seconds
Started Jun 13 01:46:06 PM PDT 24
Finished Jun 13 01:46:42 PM PDT 24
Peak memory 250900 kb
Host smart-5f3ce7d7-0e78-40a6-b478-c8af34fddf75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669090293 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_failure.3669090293
Directory /workspace/46.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_post_trans.1223447271
Short name T693
Test name
Test status
Simulation time 87622042 ps
CPU time 9.52 seconds
Started Jun 13 01:46:04 PM PDT 24
Finished Jun 13 01:46:15 PM PDT 24
Peak memory 250900 kb
Host smart-4f1cd08b-a84f-41fa-a2b1-a03acbe189a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223447271 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_post_trans.1223447271
Directory /workspace/46.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all.625302087
Short name T417
Test name
Test status
Simulation time 50108283614 ps
CPU time 836.59 seconds
Started Jun 13 01:46:04 PM PDT 24
Finished Jun 13 02:00:02 PM PDT 24
Peak memory 316132 kb
Host smart-b3d27d83-2996-48da-8628-14c0d77c07ad
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625302087 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.lc_ctrl_stress_all.625302087
Directory /workspace/46.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all_with_rand_reset.1895467039
Short name T154
Test name
Test status
Simulation time 5076699734 ps
CPU time 108.85 seconds
Started Jun 13 01:46:06 PM PDT 24
Finished Jun 13 01:47:57 PM PDT 24
Peak memory 269160 kb
Host smart-f831a2f1-fe3b-4539-90c0-41052b5956de
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1895467039 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_stress_all_with_rand_reset.1895467039
Directory /workspace/46.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.lc_ctrl_volatile_unlock_smoke.1482838212
Short name T666
Test name
Test status
Simulation time 18974274 ps
CPU time 0.92 seconds
Started Jun 13 01:46:13 PM PDT 24
Finished Jun 13 01:46:16 PM PDT 24
Peak memory 211924 kb
Host smart-b664c023-3cfd-42c0-9b3c-f92f09ed0f2e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482838212 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_c
trl_volatile_unlock_smoke.1482838212
Directory /workspace/46.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_alert_test.1903944871
Short name T434
Test name
Test status
Simulation time 70514183 ps
CPU time 0.91 seconds
Started Jun 13 01:46:14 PM PDT 24
Finished Jun 13 01:46:17 PM PDT 24
Peak memory 209032 kb
Host smart-9552d755-88fd-4d90-8f0b-b202d52ea05f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903944871 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_alert_test.1903944871
Directory /workspace/47.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.lc_ctrl_errors.1765599307
Short name T544
Test name
Test status
Simulation time 930706589 ps
CPU time 13.57 seconds
Started Jun 13 01:46:05 PM PDT 24
Finished Jun 13 01:46:21 PM PDT 24
Peak memory 218244 kb
Host smart-9df01c36-cf7b-4182-8438-34376cf7a8c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765599307 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_errors.1765599307
Directory /workspace/47.lc_ctrl_errors/latest

Test location /workspace/coverage/default/47.lc_ctrl_jtag_access.2636906672
Short name T851
Test name
Test status
Simulation time 1724992302 ps
CPU time 4.5 seconds
Started Jun 13 01:46:13 PM PDT 24
Finished Jun 13 01:46:19 PM PDT 24
Peak memory 217232 kb
Host smart-40499995-7587-40a1-ba2e-18a2f0fe4124
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636906672 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_jtag_access.2636906672
Directory /workspace/47.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/47.lc_ctrl_prog_failure.3429084020
Short name T474
Test name
Test status
Simulation time 458659610 ps
CPU time 4.24 seconds
Started Jun 13 01:46:06 PM PDT 24
Finished Jun 13 01:46:13 PM PDT 24
Peak memory 218264 kb
Host smart-c1c0cb2c-4f06-4a20-976d-710f1006705c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429084020 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_prog_failure.3429084020
Directory /workspace/47.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_mubi.1183949507
Short name T506
Test name
Test status
Simulation time 2288279547 ps
CPU time 16.62 seconds
Started Jun 13 01:46:15 PM PDT 24
Finished Jun 13 01:46:33 PM PDT 24
Peak memory 218728 kb
Host smart-d2855bfc-dd2c-40bc-88d0-c0ce9a7c2fff
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183949507 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_mubi.1183949507
Directory /workspace/47.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_digest.1502274942
Short name T568
Test name
Test status
Simulation time 1511103234 ps
CPU time 10.88 seconds
Started Jun 13 01:46:11 PM PDT 24
Finished Jun 13 01:46:23 PM PDT 24
Peak memory 218288 kb
Host smart-0cb459b3-ebf5-4633-b952-f54e845cc9e5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502274942 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_d
igest.1502274942
Directory /workspace/47.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_mux.3282612749
Short name T727
Test name
Test status
Simulation time 255332474 ps
CPU time 6.73 seconds
Started Jun 13 01:46:13 PM PDT 24
Finished Jun 13 01:46:22 PM PDT 24
Peak memory 218280 kb
Host smart-6159be6a-8c5d-4b9c-ba1b-282b5616097f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282612749 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_mux.
3282612749
Directory /workspace/47.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/47.lc_ctrl_security_escalation.3052959305
Short name T547
Test name
Test status
Simulation time 1977012569 ps
CPU time 8.5 seconds
Started Jun 13 01:46:05 PM PDT 24
Finished Jun 13 01:46:15 PM PDT 24
Peak memory 218292 kb
Host smart-76378a89-945e-4019-b33c-f9a3ff000df1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052959305 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_security_escalation.3052959305
Directory /workspace/47.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/47.lc_ctrl_smoke.784070202
Short name T164
Test name
Test status
Simulation time 101152879 ps
CPU time 2.41 seconds
Started Jun 13 01:46:07 PM PDT 24
Finished Jun 13 01:46:11 PM PDT 24
Peak memory 214440 kb
Host smart-cad96acd-3083-4e3f-872f-6c921da1e074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784070202 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_smoke.784070202
Directory /workspace/47.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_failure.1401824390
Short name T724
Test name
Test status
Simulation time 4070583390 ps
CPU time 28.35 seconds
Started Jun 13 01:46:02 PM PDT 24
Finished Jun 13 01:46:31 PM PDT 24
Peak memory 250956 kb
Host smart-7483ffb9-d141-4051-b453-d1f8f2e45d74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401824390 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_failure.1401824390
Directory /workspace/47.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_post_trans.2655735870
Short name T722
Test name
Test status
Simulation time 69314784 ps
CPU time 8.12 seconds
Started Jun 13 01:46:05 PM PDT 24
Finished Jun 13 01:46:15 PM PDT 24
Peak memory 250884 kb
Host smart-0a0606cd-4cb1-48b4-aba9-85bdc0192832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655735870 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_post_trans.2655735870
Directory /workspace/47.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/47.lc_ctrl_stress_all.901848435
Short name T614
Test name
Test status
Simulation time 529877009 ps
CPU time 39.65 seconds
Started Jun 13 01:46:13 PM PDT 24
Finished Jun 13 01:46:55 PM PDT 24
Peak memory 267288 kb
Host smart-454c8586-4978-48bb-8b1c-94f629dffdaa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901848435 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.lc_ctrl_stress_all.901848435
Directory /workspace/47.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.lc_ctrl_volatile_unlock_smoke.2832764405
Short name T398
Test name
Test status
Simulation time 26948285 ps
CPU time 0.99 seconds
Started Jun 13 01:46:03 PM PDT 24
Finished Jun 13 01:46:05 PM PDT 24
Peak memory 209056 kb
Host smart-b6014da1-d7db-47be-b50d-db531c9eaafe
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832764405 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_c
trl_volatile_unlock_smoke.2832764405
Directory /workspace/47.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_alert_test.1690659525
Short name T495
Test name
Test status
Simulation time 25100717 ps
CPU time 0.86 seconds
Started Jun 13 01:46:12 PM PDT 24
Finished Jun 13 01:46:15 PM PDT 24
Peak memory 208816 kb
Host smart-61ddbdab-1bef-49bb-96c6-1df91d84e689
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690659525 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_alert_test.1690659525
Directory /workspace/48.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.lc_ctrl_errors.3633540735
Short name T826
Test name
Test status
Simulation time 3788530845 ps
CPU time 24.55 seconds
Started Jun 13 01:46:13 PM PDT 24
Finished Jun 13 01:46:40 PM PDT 24
Peak memory 218340 kb
Host smart-28445643-3610-451a-bdba-6fb69edde7ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633540735 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_errors.3633540735
Directory /workspace/48.lc_ctrl_errors/latest

Test location /workspace/coverage/default/48.lc_ctrl_jtag_access.2184066143
Short name T384
Test name
Test status
Simulation time 413903450 ps
CPU time 5.78 seconds
Started Jun 13 01:46:14 PM PDT 24
Finished Jun 13 01:46:22 PM PDT 24
Peak memory 217248 kb
Host smart-6cb62055-ec52-44ec-bffe-c74351d0f5df
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184066143 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_jtag_access.2184066143
Directory /workspace/48.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/48.lc_ctrl_prog_failure.69484898
Short name T533
Test name
Test status
Simulation time 156099759 ps
CPU time 2.11 seconds
Started Jun 13 01:46:13 PM PDT 24
Finished Jun 13 01:46:18 PM PDT 24
Peak memory 222184 kb
Host smart-7e9e277b-c8e7-4be1-933e-c994dfb6a46a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69484898 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_prog_failure.69484898
Directory /workspace/48.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_mubi.4140790623
Short name T374
Test name
Test status
Simulation time 387867181 ps
CPU time 13.83 seconds
Started Jun 13 01:46:13 PM PDT 24
Finished Jun 13 01:46:29 PM PDT 24
Peak memory 218936 kb
Host smart-ab3cca8d-f975-4e09-9cb9-c7f042ccbb8e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140790623 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_mubi.4140790623
Directory /workspace/48.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_digest.326185990
Short name T488
Test name
Test status
Simulation time 426094553 ps
CPU time 11.99 seconds
Started Jun 13 01:46:17 PM PDT 24
Finished Jun 13 01:46:30 PM PDT 24
Peak memory 218384 kb
Host smart-5472b4fa-5e06-4f9a-96f8-9c9ef1e41fe8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326185990 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_di
gest.326185990
Directory /workspace/48.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_mux.2575469963
Short name T290
Test name
Test status
Simulation time 1498624069 ps
CPU time 6.04 seconds
Started Jun 13 01:46:13 PM PDT 24
Finished Jun 13 01:46:21 PM PDT 24
Peak memory 218256 kb
Host smart-64978d3c-345d-41bf-ae3a-921e5b774679
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575469963 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_mux.
2575469963
Directory /workspace/48.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/48.lc_ctrl_security_escalation.1306828091
Short name T478
Test name
Test status
Simulation time 1994207557 ps
CPU time 15.9 seconds
Started Jun 13 01:46:11 PM PDT 24
Finished Jun 13 01:46:27 PM PDT 24
Peak memory 225732 kb
Host smart-c4fd97e2-84f6-4d97-a221-db4ef1192898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306828091 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_security_escalation.1306828091
Directory /workspace/48.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/48.lc_ctrl_smoke.2443398162
Short name T213
Test name
Test status
Simulation time 14992395 ps
CPU time 1.07 seconds
Started Jun 13 01:46:12 PM PDT 24
Finished Jun 13 01:46:15 PM PDT 24
Peak memory 217752 kb
Host smart-a022d828-a988-4cd9-bc3d-29389279b106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2443398162 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_smoke.2443398162
Directory /workspace/48.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_failure.3672547749
Short name T587
Test name
Test status
Simulation time 521734311 ps
CPU time 17.52 seconds
Started Jun 13 01:46:12 PM PDT 24
Finished Jun 13 01:46:32 PM PDT 24
Peak memory 250896 kb
Host smart-f95cac92-0e32-4567-a4a7-0ed6b9c5d8fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672547749 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_failure.3672547749
Directory /workspace/48.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_post_trans.3752645742
Short name T298
Test name
Test status
Simulation time 155015891 ps
CPU time 10.72 seconds
Started Jun 13 01:46:12 PM PDT 24
Finished Jun 13 01:46:25 PM PDT 24
Peak memory 250908 kb
Host smart-366ef81b-19d1-419d-afd3-82f8aac6e01c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752645742 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_post_trans.3752645742
Directory /workspace/48.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all.1475818471
Short name T301
Test name
Test status
Simulation time 7315229013 ps
CPU time 244.18 seconds
Started Jun 13 01:46:14 PM PDT 24
Finished Jun 13 01:50:20 PM PDT 24
Peak memory 270820 kb
Host smart-e64a1f27-4d6a-49c3-a347-750c8e336c53
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475818471 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.lc_ctrl_stress_all.1475818471
Directory /workspace/48.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.lc_ctrl_volatile_unlock_smoke.3613498903
Short name T683
Test name
Test status
Simulation time 39297124 ps
CPU time 0.97 seconds
Started Jun 13 01:46:11 PM PDT 24
Finished Jun 13 01:46:14 PM PDT 24
Peak memory 213040 kb
Host smart-73eb817e-1026-4b11-9cc8-88e7a25ad358
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613498903 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_c
trl_volatile_unlock_smoke.3613498903
Directory /workspace/48.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_alert_test.2339086546
Short name T343
Test name
Test status
Simulation time 39051333 ps
CPU time 0.91 seconds
Started Jun 13 01:46:20 PM PDT 24
Finished Jun 13 01:46:22 PM PDT 24
Peak memory 208844 kb
Host smart-56668c7c-f1af-425f-9f99-62b441738419
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339086546 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_alert_test.2339086546
Directory /workspace/49.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.lc_ctrl_errors.1999547875
Short name T870
Test name
Test status
Simulation time 664697309 ps
CPU time 17.4 seconds
Started Jun 13 01:46:21 PM PDT 24
Finished Jun 13 01:46:40 PM PDT 24
Peak memory 218284 kb
Host smart-4d45abe1-2d3f-4969-bdb2-3936c3fe8842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999547875 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_errors.1999547875
Directory /workspace/49.lc_ctrl_errors/latest

Test location /workspace/coverage/default/49.lc_ctrl_jtag_access.2646466803
Short name T530
Test name
Test status
Simulation time 307223268 ps
CPU time 8.78 seconds
Started Jun 13 01:46:18 PM PDT 24
Finished Jun 13 01:46:27 PM PDT 24
Peak memory 217588 kb
Host smart-c496086e-09ad-4c73-ae70-a1eed09fe4a7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646466803 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_jtag_access.2646466803
Directory /workspace/49.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/49.lc_ctrl_prog_failure.3807092191
Short name T640
Test name
Test status
Simulation time 28410391 ps
CPU time 2.15 seconds
Started Jun 13 01:46:20 PM PDT 24
Finished Jun 13 01:46:23 PM PDT 24
Peak memory 222068 kb
Host smart-c0a69c53-b8b9-413e-85f4-77966c919505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807092191 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_prog_failure.3807092191
Directory /workspace/49.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_digest.1863799877
Short name T498
Test name
Test status
Simulation time 522890646 ps
CPU time 10.6 seconds
Started Jun 13 01:46:20 PM PDT 24
Finished Jun 13 01:46:31 PM PDT 24
Peak memory 226068 kb
Host smart-303d8e1c-727f-4a05-9175-bf85dfabb5e7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863799877 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_d
igest.1863799877
Directory /workspace/49.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_mux.3618504688
Short name T387
Test name
Test status
Simulation time 6343338208 ps
CPU time 13.23 seconds
Started Jun 13 01:46:20 PM PDT 24
Finished Jun 13 01:46:34 PM PDT 24
Peak memory 218300 kb
Host smart-f25749cb-3812-4aca-b119-bfd472d330c3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618504688 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_mux.
3618504688
Directory /workspace/49.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/49.lc_ctrl_security_escalation.1409382540
Short name T55
Test name
Test status
Simulation time 468627341 ps
CPU time 9.78 seconds
Started Jun 13 01:46:18 PM PDT 24
Finished Jun 13 01:46:28 PM PDT 24
Peak memory 226068 kb
Host smart-1aee558b-648a-405c-90aa-c3fd305b2a65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409382540 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_security_escalation.1409382540
Directory /workspace/49.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/49.lc_ctrl_smoke.1927125002
Short name T815
Test name
Test status
Simulation time 42348632 ps
CPU time 1.62 seconds
Started Jun 13 01:46:12 PM PDT 24
Finished Jun 13 01:46:16 PM PDT 24
Peak memory 214216 kb
Host smart-ab6a10bc-1318-4000-89d0-60f70e1dc5ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927125002 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_smoke.1927125002
Directory /workspace/49.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_failure.2687052652
Short name T316
Test name
Test status
Simulation time 281570487 ps
CPU time 26.37 seconds
Started Jun 13 01:46:20 PM PDT 24
Finished Jun 13 01:46:47 PM PDT 24
Peak memory 250912 kb
Host smart-207086d3-9aff-4311-afdf-54995f38711a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687052652 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_failure.2687052652
Directory /workspace/49.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_post_trans.1073622300
Short name T819
Test name
Test status
Simulation time 294188353 ps
CPU time 8.14 seconds
Started Jun 13 01:46:19 PM PDT 24
Finished Jun 13 01:46:28 PM PDT 24
Peak memory 244468 kb
Host smart-f356033e-c15b-4f1c-bc03-e51f570a6af3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073622300 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_post_trans.1073622300
Directory /workspace/49.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/49.lc_ctrl_stress_all.1625626978
Short name T319
Test name
Test status
Simulation time 5830093468 ps
CPU time 50.83 seconds
Started Jun 13 01:46:20 PM PDT 24
Finished Jun 13 01:47:12 PM PDT 24
Peak memory 226120 kb
Host smart-cf38a198-da25-481f-9ccc-c49a31435515
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625626978 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.lc_ctrl_stress_all.1625626978
Directory /workspace/49.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.lc_ctrl_volatile_unlock_smoke.2498758414
Short name T30
Test name
Test status
Simulation time 12831083 ps
CPU time 0.82 seconds
Started Jun 13 01:46:15 PM PDT 24
Finished Jun 13 01:46:17 PM PDT 24
Peak memory 208668 kb
Host smart-e6d75ce2-033f-4a0f-8b05-ac2f0bc66df4
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498758414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_c
trl_volatile_unlock_smoke.2498758414
Directory /workspace/49.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_alert_test.684972299
Short name T760
Test name
Test status
Simulation time 34783535 ps
CPU time 0.83 seconds
Started Jun 13 01:42:20 PM PDT 24
Finished Jun 13 01:42:21 PM PDT 24
Peak memory 209036 kb
Host smart-34ecad8e-665c-480d-ac5f-bb4cab8fe31d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684972299 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_alert_test.684972299
Directory /workspace/5.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.lc_ctrl_claim_transition_if.2572073259
Short name T466
Test name
Test status
Simulation time 33503930 ps
CPU time 0.8 seconds
Started Jun 13 01:42:04 PM PDT 24
Finished Jun 13 01:42:07 PM PDT 24
Peak memory 209004 kb
Host smart-2f79df4d-4661-48d0-8dec-e5758bda8aa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572073259 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_claim_transition_if.2572073259
Directory /workspace/5.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/5.lc_ctrl_errors.427469411
Short name T747
Test name
Test status
Simulation time 2281142477 ps
CPU time 13.39 seconds
Started Jun 13 01:41:58 PM PDT 24
Finished Jun 13 01:42:13 PM PDT 24
Peak memory 218328 kb
Host smart-cfb418b7-94a6-44ee-a5e3-97f65c3a6516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427469411 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_errors.427469411
Directory /workspace/5.lc_ctrl_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_access.2764848767
Short name T502
Test name
Test status
Simulation time 1883280093 ps
CPU time 11.12 seconds
Started Jun 13 01:42:15 PM PDT 24
Finished Jun 13 01:42:28 PM PDT 24
Peak memory 217108 kb
Host smart-a4d76e8f-7ac6-44b1-bfe1-54f2f5083d0b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764848767 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_access.2764848767
Directory /workspace/5.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_errors.2085551642
Short name T494
Test name
Test status
Simulation time 6238778792 ps
CPU time 23.63 seconds
Started Jun 13 01:42:15 PM PDT 24
Finished Jun 13 01:42:39 PM PDT 24
Peak memory 226060 kb
Host smart-505fd93d-add6-429c-afe0-964757234f22
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085551642 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_er
rors.2085551642
Directory /workspace/5.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_priority.1798236390
Short name T19
Test name
Test status
Simulation time 1910534963 ps
CPU time 32.29 seconds
Started Jun 13 01:42:14 PM PDT 24
Finished Jun 13 01:42:47 PM PDT 24
Peak memory 217812 kb
Host smart-7a8c9356-15da-4e4a-8aa5-4ef6c9fef6e2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798236390 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_priority.1
798236390
Directory /workspace/5.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_prog_failure.1538513547
Short name T440
Test name
Test status
Simulation time 1378208659 ps
CPU time 6.53 seconds
Started Jun 13 01:42:16 PM PDT 24
Finished Jun 13 01:42:23 PM PDT 24
Peak memory 218212 kb
Host smart-a58c803a-89f9-43dd-9597-d2ded1011c77
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538513547 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag
_prog_failure.1538513547
Directory /workspace/5.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_regwen_during_op.2654635295
Short name T583
Test name
Test status
Simulation time 1426198160 ps
CPU time 22.41 seconds
Started Jun 13 01:42:16 PM PDT 24
Finished Jun 13 01:42:40 PM PDT 24
Peak memory 217724 kb
Host smart-68a9c5fb-4352-4f08-a66b-b3e8e35b3946
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654635295 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_regwen_during_op.2654635295
Directory /workspace/5.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_smoke.1466991639
Short name T10
Test name
Test status
Simulation time 1303821677 ps
CPU time 6.48 seconds
Started Jun 13 01:42:06 PM PDT 24
Finished Jun 13 01:42:14 PM PDT 24
Peak memory 217692 kb
Host smart-3cc87bec-e656-44aa-bf65-cf49328cccf6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466991639 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_smoke.
1466991639
Directory /workspace/5.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_failure.1151348299
Short name T377
Test name
Test status
Simulation time 2118127589 ps
CPU time 73.6 seconds
Started Jun 13 01:42:05 PM PDT 24
Finished Jun 13 01:43:20 PM PDT 24
Peak memory 268852 kb
Host smart-d6b854bb-fd5c-457a-902b-5038cb4d6ea0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151348299 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jta
g_state_failure.1151348299
Directory /workspace/5.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_post_trans.2809146611
Short name T525
Test name
Test status
Simulation time 366677578 ps
CPU time 14.45 seconds
Started Jun 13 01:42:05 PM PDT 24
Finished Jun 13 01:42:21 PM PDT 24
Peak memory 250920 kb
Host smart-fb0f5f97-8de6-411f-8354-56ff371c48db
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809146611 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_state_post_trans.2809146611
Directory /workspace/5.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_prog_failure.1837646549
Short name T718
Test name
Test status
Simulation time 32791806 ps
CPU time 2.01 seconds
Started Jun 13 01:42:02 PM PDT 24
Finished Jun 13 01:42:05 PM PDT 24
Peak memory 218220 kb
Host smart-9a896eee-a9ef-4840-939b-10a07e604c21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837646549 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_prog_failure.1837646549
Directory /workspace/5.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_regwen_during_op.1594034696
Short name T65
Test name
Test status
Simulation time 246327911 ps
CPU time 7.43 seconds
Started Jun 13 01:42:06 PM PDT 24
Finished Jun 13 01:42:15 PM PDT 24
Peak memory 217740 kb
Host smart-1636da9e-d808-4187-b9a6-7a0b8f7cf99d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594034696 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_regwen_during_op.1594034696
Directory /workspace/5.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_mubi.3251246087
Short name T33
Test name
Test status
Simulation time 857285703 ps
CPU time 16.3 seconds
Started Jun 13 01:42:15 PM PDT 24
Finished Jun 13 01:42:32 PM PDT 24
Peak memory 226068 kb
Host smart-223801fc-e0bb-446f-aea5-d3555f13958b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251246087 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_mubi.3251246087
Directory /workspace/5.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_digest.2177590082
Short name T216
Test name
Test status
Simulation time 519946932 ps
CPU time 11.39 seconds
Started Jun 13 01:42:16 PM PDT 24
Finished Jun 13 01:42:28 PM PDT 24
Peak memory 218184 kb
Host smart-3493603a-2a37-4ea2-9288-6b6dc2a7cdd5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177590082 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_di
gest.2177590082
Directory /workspace/5.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_mux.2507946507
Short name T163
Test name
Test status
Simulation time 966074408 ps
CPU time 8.62 seconds
Started Jun 13 01:42:16 PM PDT 24
Finished Jun 13 01:42:26 PM PDT 24
Peak memory 226068 kb
Host smart-c2efaccb-f5c7-4ac8-9a4f-b8e0a0464e62
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507946507 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_mux.2
507946507
Directory /workspace/5.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/5.lc_ctrl_security_escalation.3064540379
Short name T406
Test name
Test status
Simulation time 8390973222 ps
CPU time 15.69 seconds
Started Jun 13 01:42:06 PM PDT 24
Finished Jun 13 01:42:23 PM PDT 24
Peak memory 218324 kb
Host smart-ea7d150f-b307-42f4-b389-c20642879967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064540379 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_security_escalation.3064540379
Directory /workspace/5.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/5.lc_ctrl_smoke.1437468836
Short name T302
Test name
Test status
Simulation time 278013847 ps
CPU time 4.62 seconds
Started Jun 13 01:42:03 PM PDT 24
Finished Jun 13 01:42:09 PM PDT 24
Peak memory 217760 kb
Host smart-d05d3a7d-41e7-42ad-a221-1b1e5b548237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437468836 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_smoke.1437468836
Directory /workspace/5.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_failure.340779983
Short name T401
Test name
Test status
Simulation time 200372154 ps
CPU time 22.4 seconds
Started Jun 13 01:41:58 PM PDT 24
Finished Jun 13 01:42:21 PM PDT 24
Peak memory 250876 kb
Host smart-ff23a0ab-82c4-4d27-af8c-bb6c9ae0b81f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340779983 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_failure.340779983
Directory /workspace/5.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_post_trans.2403154428
Short name T359
Test name
Test status
Simulation time 102120564 ps
CPU time 3.75 seconds
Started Jun 13 01:41:58 PM PDT 24
Finished Jun 13 01:42:03 PM PDT 24
Peak memory 222872 kb
Host smart-8a3104bf-d8e2-421f-9c62-7739361ad710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403154428 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_post_trans.2403154428
Directory /workspace/5.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_stress_all.3544600567
Short name T45
Test name
Test status
Simulation time 54546848602 ps
CPU time 302.89 seconds
Started Jun 13 01:42:15 PM PDT 24
Finished Jun 13 01:47:18 PM PDT 24
Peak memory 283656 kb
Host smart-f4ac0f03-c255-4e80-8c61-e39dfa4323ad
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544600567 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.lc_ctrl_stress_all.3544600567
Directory /workspace/5.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.lc_ctrl_stress_all_with_rand_reset.3865837825
Short name T142
Test name
Test status
Simulation time 104842424205 ps
CPU time 503.2 seconds
Started Jun 13 01:42:15 PM PDT 24
Finished Jun 13 01:50:39 PM PDT 24
Peak memory 283900 kb
Host smart-639a2ce8-ffc5-4796-ba1e-8a9910a63d7a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3865837825 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_stress_all_with_rand_reset.3865837825
Directory /workspace/5.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.lc_ctrl_volatile_unlock_smoke.2200058055
Short name T340
Test name
Test status
Simulation time 50767073 ps
CPU time 0.98 seconds
Started Jun 13 01:42:02 PM PDT 24
Finished Jun 13 01:42:04 PM PDT 24
Peak memory 212980 kb
Host smart-0d9c385e-eba0-40ef-a93c-c25cc68bfe64
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200058055 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ct
rl_volatile_unlock_smoke.2200058055
Directory /workspace/5.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_alert_test.233123759
Short name T539
Test name
Test status
Simulation time 18626743 ps
CPU time 1.18 seconds
Started Jun 13 01:42:30 PM PDT 24
Finished Jun 13 01:42:32 PM PDT 24
Peak memory 209100 kb
Host smart-7d2157d5-3c43-4d80-a510-6be67b0d5737
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233123759 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_alert_test.233123759
Directory /workspace/6.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.lc_ctrl_claim_transition_if.1176531972
Short name T199
Test name
Test status
Simulation time 13645751 ps
CPU time 0.96 seconds
Started Jun 13 01:42:21 PM PDT 24
Finished Jun 13 01:42:23 PM PDT 24
Peak memory 209012 kb
Host smart-afd3ec9c-23c6-4af8-89f1-4db1207143f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176531972 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_claim_transition_if.1176531972
Directory /workspace/6.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/6.lc_ctrl_errors.2828283316
Short name T31
Test name
Test status
Simulation time 289652116 ps
CPU time 10.2 seconds
Started Jun 13 01:42:20 PM PDT 24
Finished Jun 13 01:42:31 PM PDT 24
Peak memory 218312 kb
Host smart-babe4562-a5b3-4538-a592-b14345331fad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828283316 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_errors.2828283316
Directory /workspace/6.lc_ctrl_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_access.4148449936
Short name T246
Test name
Test status
Simulation time 63859698 ps
CPU time 1.5 seconds
Started Jun 13 01:42:23 PM PDT 24
Finished Jun 13 01:42:25 PM PDT 24
Peak memory 217248 kb
Host smart-ab051108-a347-481c-97e4-2b32050abccf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148449936 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_access.4148449936
Directory /workspace/6.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_errors.1711084183
Short name T429
Test name
Test status
Simulation time 1133742665 ps
CPU time 18.76 seconds
Started Jun 13 01:42:16 PM PDT 24
Finished Jun 13 01:42:36 PM PDT 24
Peak memory 218204 kb
Host smart-a8225941-0b0c-4b50-b320-6e95cdd86935
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711084183 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_er
rors.1711084183
Directory /workspace/6.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_priority.597398617
Short name T148
Test name
Test status
Simulation time 167686058 ps
CPU time 2.68 seconds
Started Jun 13 01:42:22 PM PDT 24
Finished Jun 13 01:42:25 PM PDT 24
Peak memory 217760 kb
Host smart-97bae4d8-76b6-4732-a02f-da171e1916dc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597398617 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_priority.597398617
Directory /workspace/6.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_prog_failure.3688924724
Short name T626
Test name
Test status
Simulation time 1351438057 ps
CPU time 8.33 seconds
Started Jun 13 01:42:21 PM PDT 24
Finished Jun 13 01:42:30 PM PDT 24
Peak memory 218236 kb
Host smart-aba810f9-6096-46c5-8ab4-ebdfa88fbd51
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688924724 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag
_prog_failure.3688924724
Directory /workspace/6.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_regwen_during_op.3641811692
Short name T228
Test name
Test status
Simulation time 1134072898 ps
CPU time 9.24 seconds
Started Jun 13 01:42:29 PM PDT 24
Finished Jun 13 01:42:39 PM PDT 24
Peak memory 217720 kb
Host smart-ba62e36f-8b6a-4c61-892e-39fd95f58bb3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641811692 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_regwen_during_op.3641811692
Directory /workspace/6.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_smoke.3121204851
Short name T339
Test name
Test status
Simulation time 129794440 ps
CPU time 2.22 seconds
Started Jun 13 01:42:21 PM PDT 24
Finished Jun 13 01:42:25 PM PDT 24
Peak memory 217708 kb
Host smart-1bf36192-c77c-4456-a6b0-de6f1159c0e6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121204851 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_smoke.
3121204851
Directory /workspace/6.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_failure.967842518
Short name T600
Test name
Test status
Simulation time 4758906807 ps
CPU time 84.29 seconds
Started Jun 13 01:42:19 PM PDT 24
Finished Jun 13 01:43:44 PM PDT 24
Peak memory 283668 kb
Host smart-f0767c78-fea0-4fde-a9fc-631f361f6649
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967842518 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag
_state_failure.967842518
Directory /workspace/6.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_post_trans.1522554066
Short name T856
Test name
Test status
Simulation time 2632209563 ps
CPU time 15.86 seconds
Started Jun 13 01:42:21 PM PDT 24
Finished Jun 13 01:42:38 PM PDT 24
Peak memory 250912 kb
Host smart-4c61b4ce-ab23-4e17-ac95-b56b6d63e49a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522554066 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_state_post_trans.1522554066
Directory /workspace/6.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_prog_failure.240492597
Short name T516
Test name
Test status
Simulation time 33895543 ps
CPU time 1.93 seconds
Started Jun 13 01:42:15 PM PDT 24
Finished Jun 13 01:42:18 PM PDT 24
Peak memory 222224 kb
Host smart-d84ff39a-acb0-4aa4-be58-0a2e10418469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240492597 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_prog_failure.240492597
Directory /workspace/6.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_regwen_during_op.1583327064
Short name T559
Test name
Test status
Simulation time 202381232 ps
CPU time 11.66 seconds
Started Jun 13 01:42:17 PM PDT 24
Finished Jun 13 01:42:30 PM PDT 24
Peak memory 217840 kb
Host smart-d24ed3af-f89e-4d7e-8adf-147f74f2cf7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583327064 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_regwen_during_op.1583327064
Directory /workspace/6.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_mubi.802391261
Short name T866
Test name
Test status
Simulation time 566376586 ps
CPU time 16.44 seconds
Started Jun 13 01:42:27 PM PDT 24
Finished Jun 13 01:42:45 PM PDT 24
Peak memory 226112 kb
Host smart-f24d476f-33e1-4c9b-be48-5cbd3348be3d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802391261 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_mubi.802391261
Directory /workspace/6.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_digest.563490423
Short name T489
Test name
Test status
Simulation time 771431119 ps
CPU time 11.69 seconds
Started Jun 13 01:42:23 PM PDT 24
Finished Jun 13 01:42:35 PM PDT 24
Peak memory 218184 kb
Host smart-72f830f5-f52b-441b-a728-d46d31e85883
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563490423 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_dig
est.563490423
Directory /workspace/6.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_mux.4294661654
Short name T806
Test name
Test status
Simulation time 1483335299 ps
CPU time 9.2 seconds
Started Jun 13 01:42:23 PM PDT 24
Finished Jun 13 01:42:33 PM PDT 24
Peak memory 226048 kb
Host smart-45130888-0184-423a-b964-4c360763c963
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294661654 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_mux.4
294661654
Directory /workspace/6.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/6.lc_ctrl_security_escalation.513855987
Short name T585
Test name
Test status
Simulation time 1445772231 ps
CPU time 12.66 seconds
Started Jun 13 01:42:22 PM PDT 24
Finished Jun 13 01:42:36 PM PDT 24
Peak memory 226052 kb
Host smart-e010092a-4502-472f-9562-26798b41db1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513855987 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_security_escalation.513855987
Directory /workspace/6.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/6.lc_ctrl_smoke.2217834172
Short name T763
Test name
Test status
Simulation time 31714316 ps
CPU time 0.98 seconds
Started Jun 13 01:42:18 PM PDT 24
Finished Jun 13 01:42:20 PM PDT 24
Peak memory 212200 kb
Host smart-6f7eec27-0ca4-4948-85ad-f94c41db00fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217834172 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_smoke.2217834172
Directory /workspace/6.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_failure.3676657483
Short name T757
Test name
Test status
Simulation time 2084792080 ps
CPU time 38.45 seconds
Started Jun 13 01:42:16 PM PDT 24
Finished Jun 13 01:42:55 PM PDT 24
Peak memory 250928 kb
Host smart-18abd191-cff8-4699-807a-25785900cabf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676657483 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_failure.3676657483
Directory /workspace/6.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_post_trans.4077714885
Short name T654
Test name
Test status
Simulation time 98423711 ps
CPU time 9.29 seconds
Started Jun 13 01:42:16 PM PDT 24
Finished Jun 13 01:42:27 PM PDT 24
Peak memory 250596 kb
Host smart-fb2d6497-da63-4f0b-b27b-8f06427490ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077714885 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_post_trans.4077714885
Directory /workspace/6.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all.627914723
Short name T694
Test name
Test status
Simulation time 8310247558 ps
CPU time 17.92 seconds
Started Jun 13 01:42:22 PM PDT 24
Finished Jun 13 01:42:41 PM PDT 24
Peak memory 217884 kb
Host smart-6d6ca378-dd56-446e-8aa8-68503c34cdbf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627914723 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.lc_ctrl_stress_all.627914723
Directory /workspace/6.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.lc_ctrl_volatile_unlock_smoke.1433509569
Short name T412
Test name
Test status
Simulation time 22434350 ps
CPU time 0.96 seconds
Started Jun 13 01:42:16 PM PDT 24
Finished Jun 13 01:42:18 PM PDT 24
Peak memory 211952 kb
Host smart-69b0b857-5803-485a-8975-6ae5fd641153
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433509569 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ct
rl_volatile_unlock_smoke.1433509569
Directory /workspace/6.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_alert_test.4053002060
Short name T527
Test name
Test status
Simulation time 20430350 ps
CPU time 1.02 seconds
Started Jun 13 01:42:35 PM PDT 24
Finished Jun 13 01:42:37 PM PDT 24
Peak memory 208968 kb
Host smart-0a44247b-e6e5-495c-97cf-721852e3e55b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053002060 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_alert_test.4053002060
Directory /workspace/7.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.lc_ctrl_errors.1861393779
Short name T456
Test name
Test status
Simulation time 287974050 ps
CPU time 10.02 seconds
Started Jun 13 01:42:30 PM PDT 24
Finished Jun 13 01:42:41 PM PDT 24
Peak memory 226084 kb
Host smart-10228f66-d75a-4c08-af5b-e532889df6f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861393779 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_errors.1861393779
Directory /workspace/7.lc_ctrl_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_access.4152757087
Short name T472
Test name
Test status
Simulation time 1770808814 ps
CPU time 4.32 seconds
Started Jun 13 01:42:35 PM PDT 24
Finished Jun 13 01:42:40 PM PDT 24
Peak memory 217220 kb
Host smart-79009d10-ed48-4ccd-96d6-b2967f335038
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152757087 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_access.4152757087
Directory /workspace/7.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_errors.1654459433
Short name T333
Test name
Test status
Simulation time 1586456326 ps
CPU time 24.95 seconds
Started Jun 13 01:42:35 PM PDT 24
Finished Jun 13 01:43:01 PM PDT 24
Peak memory 225732 kb
Host smart-d1cff920-d990-4698-99e1-8be3ea951e07
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654459433 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_er
rors.1654459433
Directory /workspace/7.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_priority.325380686
Short name T528
Test name
Test status
Simulation time 538607456 ps
CPU time 5.71 seconds
Started Jun 13 01:42:35 PM PDT 24
Finished Jun 13 01:42:41 PM PDT 24
Peak memory 217808 kb
Host smart-f19a183d-eeff-4ac7-a96d-9f31ab875779
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325380686 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_priority.325380686
Directory /workspace/7.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_prog_failure.1286854366
Short name T482
Test name
Test status
Simulation time 602824594 ps
CPU time 4.35 seconds
Started Jun 13 01:42:33 PM PDT 24
Finished Jun 13 01:42:38 PM PDT 24
Peak memory 221420 kb
Host smart-652c16c4-6dd5-4431-b460-d27e04bc493b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286854366 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag
_prog_failure.1286854366
Directory /workspace/7.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_regwen_during_op.2741440599
Short name T95
Test name
Test status
Simulation time 4981379517 ps
CPU time 38.33 seconds
Started Jun 13 01:42:35 PM PDT 24
Finished Jun 13 01:43:15 PM PDT 24
Peak memory 217744 kb
Host smart-80dd566f-6bc4-49f0-9699-24e31a0569ae
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741440599 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_regwen_during_op.2741440599
Directory /workspace/7.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_smoke.1065964838
Short name T375
Test name
Test status
Simulation time 677165486 ps
CPU time 9.44 seconds
Started Jun 13 01:42:30 PM PDT 24
Finished Jun 13 01:42:40 PM PDT 24
Peak memory 217684 kb
Host smart-fc9a7db5-b234-4cbf-95ac-c5d4eaf1e840
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065964838 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_smoke.
1065964838
Directory /workspace/7.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_failure.1290637553
Short name T86
Test name
Test status
Simulation time 2500517993 ps
CPU time 85.52 seconds
Started Jun 13 01:42:33 PM PDT 24
Finished Jun 13 01:43:59 PM PDT 24
Peak memory 283652 kb
Host smart-92196417-be30-46b5-994c-365a2ea669e9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290637553 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jta
g_state_failure.1290637553
Directory /workspace/7.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_post_trans.589467649
Short name T499
Test name
Test status
Simulation time 878703686 ps
CPU time 12.08 seconds
Started Jun 13 01:42:31 PM PDT 24
Finished Jun 13 01:42:44 PM PDT 24
Peak memory 250832 kb
Host smart-977a4384-c232-435c-853e-78648b2c6e5c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589467649 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_j
tag_state_post_trans.589467649
Directory /workspace/7.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_prog_failure.1474357432
Short name T94
Test name
Test status
Simulation time 54071304 ps
CPU time 3.31 seconds
Started Jun 13 01:42:29 PM PDT 24
Finished Jun 13 01:42:33 PM PDT 24
Peak memory 222312 kb
Host smart-a0a150ed-8242-4d47-b608-e2bd0f7cb8b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474357432 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_prog_failure.1474357432
Directory /workspace/7.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_regwen_during_op.69935839
Short name T725
Test name
Test status
Simulation time 208080902 ps
CPU time 11.57 seconds
Started Jun 13 01:42:30 PM PDT 24
Finished Jun 13 01:42:43 PM PDT 24
Peak memory 214012 kb
Host smart-33d027be-3227-45b0-baaf-7541acc18dc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69935839 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_regwen_during_op.69935839
Directory /workspace/7.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_mubi.3988254854
Short name T821
Test name
Test status
Simulation time 904159956 ps
CPU time 12.77 seconds
Started Jun 13 01:42:36 PM PDT 24
Finished Jun 13 01:42:50 PM PDT 24
Peak memory 218932 kb
Host smart-6e182804-0931-41e6-858a-a7c519e73916
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988254854 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_mubi.3988254854
Directory /workspace/7.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_digest.2358913044
Short name T743
Test name
Test status
Simulation time 1006928526 ps
CPU time 9.37 seconds
Started Jun 13 01:42:34 PM PDT 24
Finished Jun 13 01:42:44 PM PDT 24
Peak memory 225820 kb
Host smart-7f48ae2d-17f5-474f-b7e0-921449e92e1f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358913044 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_di
gest.2358913044
Directory /workspace/7.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_mux.1900318105
Short name T446
Test name
Test status
Simulation time 4300245253 ps
CPU time 8.18 seconds
Started Jun 13 01:42:35 PM PDT 24
Finished Jun 13 01:42:44 PM PDT 24
Peak memory 226132 kb
Host smart-87bb5ac5-3590-46af-9889-c14a40b4e1b5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900318105 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_mux.1
900318105
Directory /workspace/7.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/7.lc_ctrl_security_escalation.2394415380
Short name T598
Test name
Test status
Simulation time 423192637 ps
CPU time 15.16 seconds
Started Jun 13 01:42:28 PM PDT 24
Finished Jun 13 01:42:44 PM PDT 24
Peak memory 225672 kb
Host smart-2bc78d96-318a-47c4-8fd6-6e333559f5d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394415380 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_security_escalation.2394415380
Directory /workspace/7.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/7.lc_ctrl_smoke.2614548810
Short name T388
Test name
Test status
Simulation time 51438100 ps
CPU time 1.63 seconds
Started Jun 13 01:42:27 PM PDT 24
Finished Jun 13 01:42:29 PM PDT 24
Peak memory 213916 kb
Host smart-2f4fdb20-92aa-4842-b263-c336c4d1f2f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2614548810 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_smoke.2614548810
Directory /workspace/7.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_failure.2505700374
Short name T668
Test name
Test status
Simulation time 1572207050 ps
CPU time 21.03 seconds
Started Jun 13 01:42:23 PM PDT 24
Finished Jun 13 01:42:44 PM PDT 24
Peak memory 250856 kb
Host smart-3fd1c390-e20b-4b2d-a33d-8a3b71505a66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505700374 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_failure.2505700374
Directory /workspace/7.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_post_trans.2342999076
Short name T315
Test name
Test status
Simulation time 81620076 ps
CPU time 9.58 seconds
Started Jun 13 01:42:21 PM PDT 24
Finished Jun 13 01:42:32 PM PDT 24
Peak memory 250852 kb
Host smart-adb4a71a-e885-43aa-9bf6-16d38a3e03d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342999076 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_post_trans.2342999076
Directory /workspace/7.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_stress_all.1531442944
Short name T800
Test name
Test status
Simulation time 6960301061 ps
CPU time 49.15 seconds
Started Jun 13 01:42:35 PM PDT 24
Finished Jun 13 01:43:25 PM PDT 24
Peak memory 226128 kb
Host smart-5283ece8-cc21-411a-b796-5cc8399b80f2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531442944 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.lc_ctrl_stress_all.1531442944
Directory /workspace/7.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.lc_ctrl_volatile_unlock_smoke.93338662
Short name T854
Test name
Test status
Simulation time 13714555 ps
CPU time 0.94 seconds
Started Jun 13 01:42:24 PM PDT 24
Finished Jun 13 01:42:25 PM PDT 24
Peak memory 209056 kb
Host smart-0f0604fa-66b0-4e3e-9db1-06cba26be314
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93338662 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vol
atile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl
_volatile_unlock_smoke.93338662
Directory /workspace/7.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_alert_test.3126258483
Short name T510
Test name
Test status
Simulation time 14729786 ps
CPU time 1.06 seconds
Started Jun 13 01:42:42 PM PDT 24
Finished Jun 13 01:42:44 PM PDT 24
Peak memory 208972 kb
Host smart-359d8568-589d-44f2-ba6a-35989bb12435
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126258483 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_alert_test.3126258483
Directory /workspace/8.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.lc_ctrl_claim_transition_if.238386197
Short name T712
Test name
Test status
Simulation time 13764989 ps
CPU time 0.89 seconds
Started Jun 13 01:42:37 PM PDT 24
Finished Jun 13 01:42:39 PM PDT 24
Peak memory 208964 kb
Host smart-74f88b95-9cae-4a93-a1ac-adff9777f7b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238386197 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_claim_transition_if.238386197
Directory /workspace/8.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/8.lc_ctrl_errors.597738989
Short name T40
Test name
Test status
Simulation time 629854574 ps
CPU time 15.81 seconds
Started Jun 13 01:42:39 PM PDT 24
Finished Jun 13 01:42:56 PM PDT 24
Peak memory 218292 kb
Host smart-cc3421a8-ae70-4250-83b8-9c10609339ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597738989 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_errors.597738989
Directory /workspace/8.lc_ctrl_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_access.2634568025
Short name T749
Test name
Test status
Simulation time 1211574972 ps
CPU time 15.86 seconds
Started Jun 13 01:42:43 PM PDT 24
Finished Jun 13 01:43:00 PM PDT 24
Peak memory 217480 kb
Host smart-a2c62728-4cc5-4bac-a911-3a2eebb64f8f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634568025 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_access.2634568025
Directory /workspace/8.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_errors.1784168600
Short name T43
Test name
Test status
Simulation time 11296758364 ps
CPU time 40.17 seconds
Started Jun 13 01:42:44 PM PDT 24
Finished Jun 13 01:43:25 PM PDT 24
Peak memory 219400 kb
Host smart-4b15129a-6a6b-43d3-a0c4-6a5ab4f2c8d7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784168600 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_er
rors.1784168600
Directory /workspace/8.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_priority.436179511
Short name T197
Test name
Test status
Simulation time 6663081422 ps
CPU time 45.82 seconds
Started Jun 13 01:42:42 PM PDT 24
Finished Jun 13 01:43:29 PM PDT 24
Peak memory 217844 kb
Host smart-85d102c4-0006-47c1-b25d-16ac43c4ccab
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436179511 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_priority.436179511
Directory /workspace/8.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_prog_failure.2376086638
Short name T726
Test name
Test status
Simulation time 1658289360 ps
CPU time 12.61 seconds
Started Jun 13 01:42:41 PM PDT 24
Finished Jun 13 01:42:55 PM PDT 24
Peak memory 218204 kb
Host smart-d07ff586-94ec-4e9c-8b82-fee08d609d78
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376086638 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag
_prog_failure.2376086638
Directory /workspace/8.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_regwen_during_op.180056029
Short name T303
Test name
Test status
Simulation time 1391844491 ps
CPU time 12.08 seconds
Started Jun 13 01:42:40 PM PDT 24
Finished Jun 13 01:42:54 PM PDT 24
Peak memory 217684 kb
Host smart-92c42472-e010-4477-9a09-81eff46fb024
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180056029 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_j
tag_regwen_during_op.180056029
Directory /workspace/8.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_smoke.3599228247
Short name T836
Test name
Test status
Simulation time 729939687 ps
CPU time 3.56 seconds
Started Jun 13 01:42:35 PM PDT 24
Finished Jun 13 01:42:40 PM PDT 24
Peak memory 217724 kb
Host smart-5eb1a513-ab2a-4baf-8cbc-816c99fea88b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599228247 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_smoke.
3599228247
Directory /workspace/8.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_failure.3625550893
Short name T677
Test name
Test status
Simulation time 1178556542 ps
CPU time 39.15 seconds
Started Jun 13 01:42:40 PM PDT 24
Finished Jun 13 01:43:20 PM PDT 24
Peak memory 267260 kb
Host smart-031a578c-b0a1-4afa-b5a3-058d6111db58
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625550893 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jta
g_state_failure.3625550893
Directory /workspace/8.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_post_trans.2250636821
Short name T423
Test name
Test status
Simulation time 499345490 ps
CPU time 8.92 seconds
Started Jun 13 01:42:46 PM PDT 24
Finished Jun 13 01:42:57 PM PDT 24
Peak memory 223876 kb
Host smart-10125a3e-e543-442f-b750-ee6876314e88
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250636821 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_state_post_trans.2250636821
Directory /workspace/8.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_prog_failure.3946987384
Short name T393
Test name
Test status
Simulation time 67724362 ps
CPU time 1.58 seconds
Started Jun 13 01:42:41 PM PDT 24
Finished Jun 13 01:42:43 PM PDT 24
Peak memory 218224 kb
Host smart-44150a0c-c677-4f46-a83e-8f680645e3d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946987384 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_prog_failure.3946987384
Directory /workspace/8.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_regwen_during_op.100387858
Short name T357
Test name
Test status
Simulation time 1506943141 ps
CPU time 10.02 seconds
Started Jun 13 01:42:35 PM PDT 24
Finished Jun 13 01:42:45 PM PDT 24
Peak memory 217832 kb
Host smart-6deeacc4-0906-448b-b5a2-b46445993118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100387858 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_regwen_during_op.100387858
Directory /workspace/8.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_mubi.4267847570
Short name T409
Test name
Test status
Simulation time 4145824129 ps
CPU time 19.49 seconds
Started Jun 13 01:42:40 PM PDT 24
Finished Jun 13 01:43:01 PM PDT 24
Peak memory 226012 kb
Host smart-2017bc69-6b60-41d1-a676-4bdac272bbb0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267847570 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_mubi.4267847570
Directory /workspace/8.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_digest.1350714593
Short name T609
Test name
Test status
Simulation time 1142791393 ps
CPU time 12.13 seconds
Started Jun 13 01:42:43 PM PDT 24
Finished Jun 13 01:42:56 PM PDT 24
Peak memory 218252 kb
Host smart-aa220290-53ca-4e61-b834-62095ec3fb47
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350714593 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_di
gest.1350714593
Directory /workspace/8.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_mux.487501018
Short name T426
Test name
Test status
Simulation time 1493025860 ps
CPU time 14.55 seconds
Started Jun 13 01:42:39 PM PDT 24
Finished Jun 13 01:42:55 PM PDT 24
Peak memory 218284 kb
Host smart-c608666e-daf5-43ce-a713-2e249e314959
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487501018 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_mux.487501018
Directory /workspace/8.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/8.lc_ctrl_security_escalation.1102318806
Short name T48
Test name
Test status
Simulation time 516727081 ps
CPU time 9.69 seconds
Started Jun 13 01:42:40 PM PDT 24
Finished Jun 13 01:42:51 PM PDT 24
Peak memory 224980 kb
Host smart-03e44563-576d-4146-b77a-1cff4ef3b992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102318806 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_security_escalation.1102318806
Directory /workspace/8.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/8.lc_ctrl_smoke.3388606198
Short name T261
Test name
Test status
Simulation time 17645296 ps
CPU time 1.38 seconds
Started Jun 13 01:42:35 PM PDT 24
Finished Jun 13 01:42:38 PM PDT 24
Peak memory 213804 kb
Host smart-b68c0d71-8f8a-4add-93eb-5a343de2be86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388606198 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_smoke.3388606198
Directory /workspace/8.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_failure.3532906425
Short name T365
Test name
Test status
Simulation time 894856752 ps
CPU time 30.23 seconds
Started Jun 13 01:42:35 PM PDT 24
Finished Jun 13 01:43:05 PM PDT 24
Peak memory 250872 kb
Host smart-080c1ee8-afe0-468d-90d6-bc718705776c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532906425 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_failure.3532906425
Directory /workspace/8.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_post_trans.210444263
Short name T437
Test name
Test status
Simulation time 795851183 ps
CPU time 7.89 seconds
Started Jun 13 01:42:34 PM PDT 24
Finished Jun 13 01:42:42 PM PDT 24
Peak memory 250792 kb
Host smart-a3c3850a-cfa2-4906-9133-a1136c5db9d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210444263 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_post_trans.210444263
Directory /workspace/8.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all.4092350423
Short name T69
Test name
Test status
Simulation time 16741197128 ps
CPU time 87.54 seconds
Started Jun 13 01:42:41 PM PDT 24
Finished Jun 13 01:44:09 PM PDT 24
Peak memory 273356 kb
Host smart-933f788f-4a22-4ef0-b67a-2d70ff0ba91f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092350423 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.lc_ctrl_stress_all.4092350423
Directory /workspace/8.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all_with_rand_reset.542777274
Short name T141
Test name
Test status
Simulation time 120711420644 ps
CPU time 988.26 seconds
Started Jun 13 01:42:41 PM PDT 24
Finished Jun 13 01:59:11 PM PDT 24
Peak memory 496896 kb
Host smart-019818bb-0e2a-4f09-a254-d5693a1a715b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=542777274 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_stress_all_with_rand_reset.542777274
Directory /workspace/8.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.lc_ctrl_volatile_unlock_smoke.2511964056
Short name T307
Test name
Test status
Simulation time 63119808 ps
CPU time 0.88 seconds
Started Jun 13 01:42:40 PM PDT 24
Finished Jun 13 01:42:42 PM PDT 24
Peak memory 217820 kb
Host smart-cb3fb032-e85e-4178-8ea8-aa8f55ba8bbf
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511964056 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ct
rl_volatile_unlock_smoke.2511964056
Directory /workspace/8.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_alert_test.1262604571
Short name T842
Test name
Test status
Simulation time 47170367 ps
CPU time 0.93 seconds
Started Jun 13 01:42:47 PM PDT 24
Finished Jun 13 01:42:50 PM PDT 24
Peak memory 209040 kb
Host smart-378d8ec3-ad20-4d77-9b49-c40d6a040767
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262604571 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_alert_test.1262604571
Directory /workspace/9.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.lc_ctrl_claim_transition_if.509755514
Short name T201
Test name
Test status
Simulation time 41009437 ps
CPU time 0.9 seconds
Started Jun 13 01:42:44 PM PDT 24
Finished Jun 13 01:42:46 PM PDT 24
Peak memory 208936 kb
Host smart-be7d093b-0bf7-42c7-9e96-c58d713d6f3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509755514 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_claim_transition_if.509755514
Directory /workspace/9.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/9.lc_ctrl_errors.3034332492
Short name T372
Test name
Test status
Simulation time 1162845414 ps
CPU time 13.13 seconds
Started Jun 13 01:42:43 PM PDT 24
Finished Jun 13 01:42:57 PM PDT 24
Peak memory 218232 kb
Host smart-9285ccbb-075b-42bc-9c25-c6b71d1bc593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3034332492 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_errors.3034332492
Directory /workspace/9.lc_ctrl_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_access.822744612
Short name T541
Test name
Test status
Simulation time 212634340 ps
CPU time 3.33 seconds
Started Jun 13 01:42:48 PM PDT 24
Finished Jun 13 01:42:54 PM PDT 24
Peak memory 217312 kb
Host smart-87728901-41fe-495f-aa3c-acffb81a0c13
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822744612 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_access.822744612
Directory /workspace/9.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_errors.875062150
Short name T269
Test name
Test status
Simulation time 7570162559 ps
CPU time 35.07 seconds
Started Jun 13 01:42:47 PM PDT 24
Finished Jun 13 01:43:24 PM PDT 24
Peak memory 218724 kb
Host smart-70149bd6-d9b5-455c-83b8-23d82ef550a7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875062150 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_err
ors.875062150
Directory /workspace/9.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_priority.2632716262
Short name T758
Test name
Test status
Simulation time 262631817 ps
CPU time 7.91 seconds
Started Jun 13 01:42:48 PM PDT 24
Finished Jun 13 01:42:59 PM PDT 24
Peak memory 217584 kb
Host smart-8d2d567e-6ba9-4595-870d-a9886a22bcf2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632716262 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_priority.2
632716262
Directory /workspace/9.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_prog_failure.3151260754
Short name T657
Test name
Test status
Simulation time 392903615 ps
CPU time 2.7 seconds
Started Jun 13 01:42:48 PM PDT 24
Finished Jun 13 01:42:53 PM PDT 24
Peak memory 218188 kb
Host smart-17a5d31a-b467-462f-a0f7-33ba2614bcc2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151260754 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag
_prog_failure.3151260754
Directory /workspace/9.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_regwen_during_op.2378775583
Short name T637
Test name
Test status
Simulation time 8261127771 ps
CPU time 11.52 seconds
Started Jun 13 01:42:51 PM PDT 24
Finished Jun 13 01:43:04 PM PDT 24
Peak memory 217724 kb
Host smart-06b866fe-8e61-499c-a467-dbd6ea5ae16d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378775583 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_regwen_during_op.2378775583
Directory /workspace/9.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_smoke.3235342664
Short name T775
Test name
Test status
Simulation time 204567639 ps
CPU time 1.9 seconds
Started Jun 13 01:42:43 PM PDT 24
Finished Jun 13 01:42:45 PM PDT 24
Peak memory 217712 kb
Host smart-d16993ef-4ad8-4e11-bb65-938cd0a335b1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235342664 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_smoke.
3235342664
Directory /workspace/9.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_failure.2540835019
Short name T334
Test name
Test status
Simulation time 2870171693 ps
CPU time 72.41 seconds
Started Jun 13 01:42:48 PM PDT 24
Finished Jun 13 01:44:03 PM PDT 24
Peak memory 283656 kb
Host smart-4b4afac8-be9b-4afc-91e7-19eb8c3e30b6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540835019 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jta
g_state_failure.2540835019
Directory /workspace/9.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_post_trans.3065738069
Short name T780
Test name
Test status
Simulation time 419808817 ps
CPU time 14.54 seconds
Started Jun 13 01:42:47 PM PDT 24
Finished Jun 13 01:43:04 PM PDT 24
Peak memory 250868 kb
Host smart-2e26a914-782b-4ffb-8b53-47aa9c222e39
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065738069 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_state_post_trans.3065738069
Directory /workspace/9.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_prog_failure.3426202421
Short name T697
Test name
Test status
Simulation time 69276538 ps
CPU time 1.6 seconds
Started Jun 13 01:42:44 PM PDT 24
Finished Jun 13 01:42:47 PM PDT 24
Peak memory 221560 kb
Host smart-22e01dc8-e20d-46d8-8d17-f2c9b4e697f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426202421 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_prog_failure.3426202421
Directory /workspace/9.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_regwen_during_op.1250750829
Short name T276
Test name
Test status
Simulation time 207634490 ps
CPU time 8.27 seconds
Started Jun 13 01:42:42 PM PDT 24
Finished Jun 13 01:42:51 PM PDT 24
Peak memory 214004 kb
Host smart-0d9ea8ca-345c-4708-80b8-48b7d1c59d1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250750829 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_regwen_during_op.1250750829
Directory /workspace/9.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_mubi.1167870714
Short name T834
Test name
Test status
Simulation time 739594546 ps
CPU time 10.87 seconds
Started Jun 13 01:42:49 PM PDT 24
Finished Jun 13 01:43:02 PM PDT 24
Peak memory 226072 kb
Host smart-52eb8cda-18ab-4a82-9404-3dbef92dfbe8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167870714 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_mubi.1167870714
Directory /workspace/9.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_digest.3852967146
Short name T421
Test name
Test status
Simulation time 270915455 ps
CPU time 11.63 seconds
Started Jun 13 01:42:50 PM PDT 24
Finished Jun 13 01:43:04 PM PDT 24
Peak memory 226064 kb
Host smart-8ebaaf01-d76a-4bfb-8058-c1eb37050426
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852967146 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_di
gest.3852967146
Directory /workspace/9.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_mux.2705453935
Short name T381
Test name
Test status
Simulation time 718181626 ps
CPU time 12.83 seconds
Started Jun 13 01:42:47 PM PDT 24
Finished Jun 13 01:43:01 PM PDT 24
Peak memory 226076 kb
Host smart-f71f3ee4-26e3-4bb1-bee2-4ba62d964e56
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705453935 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_mux.2
705453935
Directory /workspace/9.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/9.lc_ctrl_security_escalation.3602484314
Short name T338
Test name
Test status
Simulation time 1539785773 ps
CPU time 11.38 seconds
Started Jun 13 01:42:44 PM PDT 24
Finished Jun 13 01:42:57 PM PDT 24
Peak memory 218344 kb
Host smart-321b6272-83b7-4cfc-8fcb-e13d8b9f1ad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602484314 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_security_escalation.3602484314
Directory /workspace/9.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/9.lc_ctrl_smoke.105561362
Short name T73
Test name
Test status
Simulation time 100396955 ps
CPU time 1.73 seconds
Started Jun 13 01:42:40 PM PDT 24
Finished Jun 13 01:42:43 PM PDT 24
Peak memory 217768 kb
Host smart-2065dce9-f99a-4b1b-add7-d9e5f5f907ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105561362 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_smoke.105561362
Directory /workspace/9.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_failure.2571887844
Short name T84
Test name
Test status
Simulation time 1499693393 ps
CPU time 18.3 seconds
Started Jun 13 01:42:41 PM PDT 24
Finished Jun 13 01:43:00 PM PDT 24
Peak memory 250904 kb
Host smart-c145287d-01d2-4644-aff9-b82398f5bc29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571887844 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_failure.2571887844
Directory /workspace/9.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_post_trans.2702814317
Short name T205
Test name
Test status
Simulation time 224309173 ps
CPU time 7.89 seconds
Started Jun 13 01:42:42 PM PDT 24
Finished Jun 13 01:42:51 PM PDT 24
Peak memory 250916 kb
Host smart-ea137b1a-4186-4e11-a07c-ac2a1282c09c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702814317 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_post_trans.2702814317
Directory /workspace/9.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_stress_all.131026609
Short name T651
Test name
Test status
Simulation time 814936801 ps
CPU time 13.49 seconds
Started Jun 13 01:42:47 PM PDT 24
Finished Jun 13 01:43:02 PM PDT 24
Peak memory 226096 kb
Host smart-3e5f4643-2a52-4af3-b3b4-6eeee719a4d5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131026609 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.lc_ctrl_stress_all.131026609
Directory /workspace/9.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.lc_ctrl_volatile_unlock_smoke.1609850007
Short name T545
Test name
Test status
Simulation time 23510081 ps
CPU time 1 seconds
Started Jun 13 01:42:42 PM PDT 24
Finished Jun 13 01:42:44 PM PDT 24
Peak memory 209028 kb
Host smart-4b87a148-cacc-4a28-b935-1d31d7420424
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609850007 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ct
rl_volatile_unlock_smoke.1609850007
Directory /workspace/9.lc_ctrl_volatile_unlock_smoke/latest
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