Summary for Variable clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53100 |
1 |
|
|
T2 |
9 |
|
T3 |
16 |
|
T4 |
10 |
auto[1] |
2122 |
1 |
|
|
T16 |
17 |
|
T17 |
9 |
|
T32 |
8 |
Summary for Variable clk_byp_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54488 |
1 |
|
|
T2 |
9 |
|
T3 |
16 |
|
T4 |
10 |
auto[1] |
734 |
1 |
|
|
T40 |
22 |
|
T64 |
9 |
|
T44 |
17 |
Summary for Variable count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53428 |
1 |
|
|
T2 |
9 |
|
T3 |
16 |
|
T4 |
10 |
auto[1] |
1794 |
1 |
|
|
T28 |
2 |
|
T37 |
15 |
|
T16 |
28 |
Summary for Variable count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53295 |
1 |
|
|
T2 |
9 |
|
T3 |
16 |
|
T4 |
10 |
auto[1] |
1927 |
1 |
|
|
T13 |
2 |
|
T28 |
1 |
|
T37 |
8 |
Summary for Variable count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53358 |
1 |
|
|
T2 |
9 |
|
T3 |
16 |
|
T4 |
10 |
auto[1] |
1864 |
1 |
|
|
T28 |
1 |
|
T37 |
7 |
|
T16 |
17 |
Summary for Variable err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for err_inj_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
err_inj |
50696 |
1 |
|
|
T2 |
9 |
|
T5 |
4 |
|
T9 |
4 |
no_err_inj |
4526 |
1 |
|
|
T3 |
16 |
|
T4 |
10 |
|
T13 |
30 |
Summary for Variable flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53126 |
1 |
|
|
T2 |
9 |
|
T3 |
16 |
|
T4 |
10 |
auto[1] |
2096 |
1 |
|
|
T16 |
23 |
|
T17 |
5 |
|
T32 |
10 |
Summary for Variable flash_rma_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54444 |
1 |
|
|
T2 |
9 |
|
T3 |
16 |
|
T4 |
10 |
auto[1] |
778 |
1 |
|
|
T40 |
16 |
|
T64 |
12 |
|
T44 |
11 |
Summary for Variable jtag_csr_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for jtag_csr_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
37082 |
1 |
|
|
T2 |
9 |
|
T9 |
4 |
|
T10 |
16 |
auto[1] |
18140 |
1 |
|
|
T3 |
16 |
|
T4 |
10 |
|
T5 |
4 |
Summary for Variable kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for kmac_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53471 |
1 |
|
|
T2 |
9 |
|
T3 |
16 |
|
T4 |
10 |
auto[1] |
1751 |
1 |
|
|
T37 |
9 |
|
T16 |
20 |
|
T17 |
9 |
Summary for Variable lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for lc_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53431 |
1 |
|
|
T2 |
9 |
|
T3 |
16 |
|
T4 |
10 |
auto[1] |
1791 |
1 |
|
|
T13 |
1 |
|
T37 |
10 |
|
T16 |
16 |
Summary for Variable otp_lc_data_i_valid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_lc_data_i_valid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53432 |
1 |
|
|
T2 |
9 |
|
T3 |
16 |
|
T4 |
10 |
auto[1] |
1790 |
1 |
|
|
T37 |
16 |
|
T16 |
18 |
|
T17 |
10 |
Summary for Variable otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_partition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53071 |
1 |
|
|
T2 |
9 |
|
T3 |
16 |
|
T4 |
10 |
auto[1] |
2151 |
1 |
|
|
T16 |
19 |
|
T17 |
5 |
|
T32 |
10 |
Summary for Variable otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_prog_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52965 |
1 |
|
|
T3 |
16 |
|
T4 |
10 |
|
T13 |
35 |
auto[1] |
2257 |
1 |
|
|
T2 |
9 |
|
T5 |
4 |
|
T9 |
4 |
Summary for Variable otp_rma_token_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_rma_token_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54461 |
1 |
|
|
T2 |
9 |
|
T3 |
16 |
|
T4 |
10 |
auto[1] |
761 |
1 |
|
|
T40 |
14 |
|
T64 |
8 |
|
T44 |
14 |
Summary for Variable otp_secrets_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_secrets_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54421 |
1 |
|
|
T2 |
9 |
|
T3 |
16 |
|
T4 |
10 |
auto[1] |
801 |
1 |
|
|
T40 |
10 |
|
T64 |
11 |
|
T44 |
24 |
Summary for Variable otp_test_tokens_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_test_tokens_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54466 |
1 |
|
|
T2 |
9 |
|
T3 |
16 |
|
T4 |
10 |
auto[1] |
756 |
1 |
|
|
T40 |
20 |
|
T64 |
12 |
|
T44 |
19 |
Summary for Variable post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for post_trans_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52579 |
1 |
|
|
T2 |
9 |
|
T3 |
16 |
|
T4 |
10 |
auto[1] |
2643 |
1 |
|
|
T13 |
12 |
|
T28 |
10 |
|
T16 |
23 |
Summary for Variable security_escalation_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for security_escalation_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51467 |
1 |
|
|
T2 |
9 |
|
T3 |
16 |
|
T4 |
10 |
auto[1] |
3755 |
1 |
|
|
T51 |
51 |
|
T48 |
93 |
|
T49 |
83 |
Summary for Variable state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53427 |
1 |
|
|
T2 |
9 |
|
T3 |
16 |
|
T4 |
10 |
auto[1] |
1795 |
1 |
|
|
T13 |
1 |
|
T28 |
1 |
|
T37 |
8 |
Summary for Variable state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53418 |
1 |
|
|
T2 |
9 |
|
T3 |
16 |
|
T4 |
10 |
auto[1] |
1804 |
1 |
|
|
T13 |
1 |
|
T37 |
10 |
|
T16 |
25 |
Summary for Variable state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53415 |
1 |
|
|
T2 |
9 |
|
T3 |
16 |
|
T4 |
10 |
auto[1] |
1807 |
1 |
|
|
T28 |
1 |
|
T37 |
9 |
|
T16 |
21 |
Summary for Variable token_invalid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_invalid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53080 |
1 |
|
|
T2 |
9 |
|
T3 |
16 |
|
T4 |
10 |
auto[1] |
2142 |
1 |
|
|
T16 |
21 |
|
T17 |
10 |
|
T32 |
5 |
Summary for Variable token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mismatch_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49426 |
1 |
|
|
T2 |
9 |
|
T3 |
16 |
|
T4 |
10 |
auto[1] |
5796 |
1 |
|
|
T29 |
89 |
|
T16 |
22 |
|
T36 |
92 |
Summary for Variable token_mux_ctrl_redun_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mux_ctrl_redun_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51339 |
1 |
|
|
T2 |
9 |
|
T3 |
16 |
|
T4 |
10 |
auto[1] |
3883 |
1 |
|
|
T14 |
97 |
|
T62 |
79 |
|
T63 |
78 |
Summary for Variable token_mux_digest_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for token_mux_digest_err_cp
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
55222 |
1 |
|
|
T2 |
9 |
|
T3 |
16 |
|
T4 |
10 |
Summary for Variable token_response_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_response_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53177 |
1 |
|
|
T2 |
9 |
|
T3 |
16 |
|
T4 |
10 |
auto[1] |
2045 |
1 |
|
|
T16 |
11 |
|
T17 |
7 |
|
T32 |
10 |
Summary for Variable transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53053 |
1 |
|
|
T2 |
9 |
|
T3 |
16 |
|
T4 |
10 |
auto[1] |
2169 |
1 |
|
|
T16 |
19 |
|
T17 |
4 |
|
T32 |
9 |
Summary for Variable transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53095 |
1 |
|
|
T2 |
9 |
|
T3 |
16 |
|
T4 |
10 |
auto[1] |
2127 |
1 |
|
|
T16 |
12 |
|
T17 |
11 |
|
T32 |
7 |
Summary for Cross post_trans_err_inj_xp
Samples crossed: post_trans_err_cp err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_err_inj_xp
Bins
post_trans_err_cp | err_inj_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
err_inj |
49377 |
1 |
|
|
T2 |
9 |
|
T5 |
4 |
|
T9 |
4 |
auto[0] |
no_err_inj |
3202 |
1 |
|
|
T3 |
16 |
|
T4 |
10 |
|
T13 |
23 |
auto[1] |
err_inj |
1319 |
1 |
|
|
T13 |
5 |
|
T28 |
6 |
|
T16 |
8 |
auto[1] |
no_err_inj |
1324 |
1 |
|
|
T13 |
7 |
|
T28 |
4 |
|
T16 |
15 |
Summary for Cross post_trans_state_err_xp
Samples crossed: post_trans_err_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_err_xp
Bins
post_trans_err_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
50925 |
1 |
|
|
T2 |
9 |
|
T3 |
16 |
|
T4 |
10 |
auto[0] |
auto[1] |
1654 |
1 |
|
|
T37 |
10 |
|
T16 |
24 |
|
T17 |
14 |
auto[1] |
auto[0] |
2493 |
1 |
|
|
T13 |
11 |
|
T28 |
10 |
|
T16 |
22 |
auto[1] |
auto[1] |
150 |
1 |
|
|
T13 |
1 |
|
T16 |
1 |
|
T17 |
3 |
Summary for Cross post_trans_lc_fsm_backdoor_err_xp
Samples crossed: post_trans_err_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_lc_fsm_backdoor_err_xp
Bins
post_trans_err_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
50923 |
1 |
|
|
T2 |
9 |
|
T3 |
16 |
|
T4 |
10 |
auto[0] |
auto[1] |
1656 |
1 |
|
|
T37 |
10 |
|
T16 |
15 |
|
T17 |
7 |
auto[1] |
auto[0] |
2508 |
1 |
|
|
T13 |
11 |
|
T28 |
10 |
|
T16 |
22 |
auto[1] |
auto[1] |
135 |
1 |
|
|
T13 |
1 |
|
T16 |
1 |
|
T17 |
1 |
Summary for Cross post_trans_state_illegal_err_xp
Samples crossed: post_trans_err_cp state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_illegal_err_xp
Bins
post_trans_err_cp | state_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
50915 |
1 |
|
|
T2 |
9 |
|
T3 |
16 |
|
T4 |
10 |
auto[0] |
auto[1] |
1664 |
1 |
|
|
T37 |
9 |
|
T16 |
20 |
|
T17 |
8 |
auto[1] |
auto[0] |
2500 |
1 |
|
|
T13 |
12 |
|
T28 |
9 |
|
T16 |
22 |
auto[1] |
auto[1] |
143 |
1 |
|
|
T28 |
1 |
|
T16 |
1 |
|
T17 |
1 |
Summary for Cross post_trans_count_err_xp
Samples crossed: post_trans_err_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_err_xp
Bins
post_trans_err_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
50821 |
1 |
|
|
T2 |
9 |
|
T3 |
16 |
|
T4 |
10 |
auto[0] |
auto[1] |
1758 |
1 |
|
|
T37 |
8 |
|
T16 |
23 |
|
T17 |
16 |
auto[1] |
auto[0] |
2474 |
1 |
|
|
T13 |
10 |
|
T28 |
9 |
|
T16 |
22 |
auto[1] |
auto[1] |
169 |
1 |
|
|
T13 |
2 |
|
T28 |
1 |
|
T16 |
1 |
Summary for Cross post_trans_count_illegal_err_xp
Samples crossed: post_trans_err_cp count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_illegal_err_xp
Bins
post_trans_err_cp | count_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
50865 |
1 |
|
|
T2 |
9 |
|
T3 |
16 |
|
T4 |
10 |
auto[0] |
auto[1] |
1714 |
1 |
|
|
T37 |
7 |
|
T16 |
16 |
|
T17 |
7 |
auto[1] |
auto[0] |
2493 |
1 |
|
|
T13 |
12 |
|
T28 |
9 |
|
T16 |
22 |
auto[1] |
auto[1] |
150 |
1 |
|
|
T28 |
1 |
|
T16 |
1 |
|
T41 |
3 |
Summary for Cross post_trans_count_backdoor_err_xp
Samples crossed: post_trans_err_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_backdoor_err_xp
Bins
post_trans_err_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
50916 |
1 |
|
|
T2 |
9 |
|
T3 |
16 |
|
T4 |
10 |
auto[0] |
auto[1] |
1663 |
1 |
|
|
T37 |
15 |
|
T16 |
27 |
|
T17 |
8 |
auto[1] |
auto[0] |
2512 |
1 |
|
|
T13 |
12 |
|
T28 |
8 |
|
T16 |
22 |
auto[1] |
auto[1] |
131 |
1 |
|
|
T28 |
2 |
|
T16 |
1 |
|
T17 |
2 |
Summary for Cross jtag_clk_byp_error_rsp_xp
Samples crossed: jtag_csr_cp clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_clk_byp_error_rsp_xp
Bins
jtag_csr_cp | clk_byp_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35991 |
1 |
|
|
T2 |
9 |
|
T9 |
4 |
|
T10 |
16 |
auto[0] |
auto[1] |
1091 |
1 |
|
|
T16 |
8 |
|
T32 |
8 |
|
T33 |
8 |
auto[1] |
auto[0] |
17109 |
1 |
|
|
T3 |
16 |
|
T4 |
10 |
|
T5 |
4 |
auto[1] |
auto[1] |
1031 |
1 |
|
|
T16 |
9 |
|
T17 |
9 |
|
T86 |
8 |
Summary for Cross jtag_flash_rma_error_rsp_xp
Samples crossed: jtag_csr_cp flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_flash_rma_error_rsp_xp
Bins
jtag_csr_cp | flash_rma_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35979 |
1 |
|
|
T2 |
9 |
|
T9 |
4 |
|
T10 |
16 |
auto[0] |
auto[1] |
1103 |
1 |
|
|
T16 |
6 |
|
T32 |
10 |
|
T33 |
10 |
auto[1] |
auto[0] |
17147 |
1 |
|
|
T3 |
16 |
|
T4 |
10 |
|
T5 |
4 |
auto[1] |
auto[1] |
993 |
1 |
|
|
T16 |
17 |
|
T17 |
5 |
|
T86 |
7 |
Summary for Cross jtag_otp_prog_err_xp
Samples crossed: jtag_csr_cp otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_prog_err_xp
Bins
jtag_csr_cp | otp_prog_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35832 |
1 |
|
|
T14 |
97 |
|
T28 |
10 |
|
T29 |
89 |
auto[0] |
auto[1] |
1250 |
1 |
|
|
T2 |
9 |
|
T9 |
4 |
|
T10 |
16 |
auto[1] |
auto[0] |
17133 |
1 |
|
|
T3 |
16 |
|
T4 |
10 |
|
T13 |
35 |
auto[1] |
auto[1] |
1007 |
1 |
|
|
T5 |
4 |
|
T12 |
13 |
|
T16 |
4 |
Summary for Cross jtag_otp_partition_err_xp
Samples crossed: jtag_csr_cp otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_partition_err_xp
Bins
jtag_csr_cp | otp_partition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35956 |
1 |
|
|
T2 |
9 |
|
T9 |
4 |
|
T10 |
16 |
auto[0] |
auto[1] |
1126 |
1 |
|
|
T16 |
9 |
|
T32 |
10 |
|
T33 |
2 |
auto[1] |
auto[0] |
17115 |
1 |
|
|
T3 |
16 |
|
T4 |
10 |
|
T5 |
4 |
auto[1] |
auto[1] |
1025 |
1 |
|
|
T16 |
10 |
|
T17 |
5 |
|
T86 |
18 |
Summary for Cross jtag_token_mismatch_err_xp
Samples crossed: jtag_csr_cp token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_token_mismatch_err_xp
Bins
jtag_csr_cp | token_mismatch_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
32298 |
1 |
|
|
T2 |
9 |
|
T9 |
4 |
|
T10 |
16 |
auto[0] |
auto[1] |
4784 |
1 |
|
|
T29 |
89 |
|
T16 |
13 |
|
T36 |
92 |
auto[1] |
auto[0] |
17128 |
1 |
|
|
T3 |
16 |
|
T4 |
10 |
|
T5 |
4 |
auto[1] |
auto[1] |
1012 |
1 |
|
|
T16 |
9 |
|
T17 |
15 |
|
T86 |
9 |
Summary for Cross jtag_state_err_xp
Samples crossed: jtag_csr_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_err_xp
Bins
jtag_csr_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36067 |
1 |
|
|
T2 |
9 |
|
T9 |
4 |
|
T10 |
16 |
auto[0] |
auto[1] |
1015 |
1 |
|
|
T37 |
10 |
|
T16 |
1 |
|
T17 |
2 |
auto[1] |
auto[0] |
17351 |
1 |
|
|
T3 |
16 |
|
T4 |
10 |
|
T5 |
4 |
auto[1] |
auto[1] |
789 |
1 |
|
|
T13 |
1 |
|
T16 |
24 |
|
T17 |
15 |
Summary for Cross jtag_state_backdoor_err_xp
Samples crossed: jtag_csr_cp state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_backdoor_err_xp
Bins
jtag_csr_cp | state_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36076 |
1 |
|
|
T2 |
9 |
|
T9 |
4 |
|
T10 |
16 |
auto[0] |
auto[1] |
1006 |
1 |
|
|
T28 |
1 |
|
T37 |
8 |
|
T85 |
4 |
auto[1] |
auto[0] |
17351 |
1 |
|
|
T3 |
16 |
|
T4 |
10 |
|
T5 |
4 |
auto[1] |
auto[1] |
789 |
1 |
|
|
T13 |
1 |
|
T16 |
12 |
|
T17 |
12 |
Summary for Cross jtag_lc_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_lc_fsm_backdoor_err_xp
Bins
jtag_csr_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36060 |
1 |
|
|
T2 |
9 |
|
T9 |
4 |
|
T10 |
16 |
auto[0] |
auto[1] |
1022 |
1 |
|
|
T37 |
10 |
|
T16 |
1 |
|
T17 |
1 |
auto[1] |
auto[0] |
17371 |
1 |
|
|
T3 |
16 |
|
T4 |
10 |
|
T5 |
4 |
auto[1] |
auto[1] |
769 |
1 |
|
|
T13 |
1 |
|
T16 |
15 |
|
T17 |
7 |
Summary for Cross jtag_kmac_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_kmac_fsm_backdoor_err_xp
Bins
jtag_csr_cp | kmac_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36099 |
1 |
|
|
T2 |
9 |
|
T9 |
4 |
|
T10 |
16 |
auto[0] |
auto[1] |
983 |
1 |
|
|
T37 |
9 |
|
T16 |
1 |
|
T17 |
1 |
auto[1] |
auto[0] |
17372 |
1 |
|
|
T3 |
16 |
|
T4 |
10 |
|
T5 |
4 |
auto[1] |
auto[1] |
768 |
1 |
|
|
T16 |
19 |
|
T17 |
8 |
|
T18 |
8 |
Summary for Cross jtag_count_err_xp
Samples crossed: jtag_csr_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_err_xp
Bins
jtag_csr_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36027 |
1 |
|
|
T2 |
9 |
|
T9 |
4 |
|
T10 |
16 |
auto[0] |
auto[1] |
1055 |
1 |
|
|
T28 |
1 |
|
T37 |
8 |
|
T16 |
1 |
auto[1] |
auto[0] |
17268 |
1 |
|
|
T3 |
16 |
|
T4 |
10 |
|
T5 |
4 |
auto[1] |
auto[1] |
872 |
1 |
|
|
T13 |
2 |
|
T16 |
23 |
|
T17 |
17 |
Summary for Cross jtag_count_backdoor_err_xp
Samples crossed: jtag_csr_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_backdoor_err_xp
Bins
jtag_csr_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36061 |
1 |
|
|
T2 |
9 |
|
T9 |
4 |
|
T10 |
16 |
auto[0] |
auto[1] |
1021 |
1 |
|
|
T28 |
2 |
|
T37 |
15 |
|
T16 |
1 |
auto[1] |
auto[0] |
17367 |
1 |
|
|
T3 |
16 |
|
T4 |
10 |
|
T5 |
4 |
auto[1] |
auto[1] |
773 |
1 |
|
|
T16 |
27 |
|
T17 |
9 |
|
T18 |
7 |
Summary for Cross jtag_transition_err_xp
Samples crossed: jtag_csr_cp transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_err_xp
Bins
jtag_csr_cp | transition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35969 |
1 |
|
|
T2 |
9 |
|
T9 |
4 |
|
T10 |
16 |
auto[0] |
auto[1] |
1113 |
1 |
|
|
T16 |
5 |
|
T32 |
7 |
|
T33 |
10 |
auto[1] |
auto[0] |
17126 |
1 |
|
|
T3 |
16 |
|
T4 |
10 |
|
T5 |
4 |
auto[1] |
auto[1] |
1014 |
1 |
|
|
T16 |
7 |
|
T17 |
11 |
|
T86 |
13 |
Summary for Cross jtag_transition_count_err_xp
Samples crossed: jtag_csr_cp transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_count_err_xp
Bins
jtag_csr_cp | transition_count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35925 |
1 |
|
|
T2 |
9 |
|
T9 |
4 |
|
T10 |
16 |
auto[0] |
auto[1] |
1157 |
1 |
|
|
T16 |
9 |
|
T32 |
9 |
|
T33 |
14 |
auto[1] |
auto[0] |
17128 |
1 |
|
|
T3 |
16 |
|
T4 |
10 |
|
T5 |
4 |
auto[1] |
auto[1] |
1012 |
1 |
|
|
T16 |
10 |
|
T17 |
4 |
|
T86 |
6 |
Summary for Cross jtag_post_trans_err_xp
Samples crossed: jtag_csr_cp post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_post_trans_err_xp
Bins
jtag_csr_cp | post_trans_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35503 |
1 |
|
|
T2 |
9 |
|
T9 |
4 |
|
T10 |
16 |
auto[0] |
auto[1] |
1579 |
1 |
|
|
T28 |
10 |
|
T16 |
23 |
|
T17 |
15 |
auto[1] |
auto[0] |
17076 |
1 |
|
|
T3 |
16 |
|
T4 |
10 |
|
T5 |
4 |
auto[1] |
auto[1] |
1064 |
1 |
|
|
T13 |
12 |
|
T17 |
12 |
|
T208 |
12 |