Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

104285469

1

T1

3679

T2

3939

T3

52346

auto[1]

1395411

1

T2

495

T5

294

T9

198

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

104285236

1

T1

3679

T2

4038

T3

52346

auto[1]

1395644

1

T2

396

T5

98

T9

198

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	7501518	1			T1	130		T2	962		T3	1383
auto[IdleSt]	25895777	1			T1	3549		T2	1518		T3	33614
auto[ClkMuxSt]	37655	1			T2	9		T3	15		T4	9
auto[CntIncrSt]	37437	1			T2	9		T3	15		T4	9
auto[CntProgSt]	1489759	1			T2	18		T3	30		T4	210
auto[TransCheckSt]	29043	1			T3	15		T4	9		T13	30
auto[TokenHashSt]	35211543	1			T3	9987		T4	99868		T13	54306
auto[FlashRmaSt]	30027	1			T3	36		T4	24		T13	59
auto[TokenCheck0St]	13084	1			T3	15		T4	9		T13	30
auto[TokenCheck1St]	9563	1			T3	15		T4	9		T13	30
auto[TransProgSt]	366464	1			T3	30		T4	195		T13	5502
auto[PostTransSt]	15836517	1			T2	607		T3	6445		T4	3642
auto[ScrapSt]	93285	1			T3	746		T4	509		T17	249
auto[EscalateSt]	7045580	1			T2	1311		T5	3126		T9	581
auto[InvalidSt]	12081744	1			T13	9224		T28	619		T37	12288

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1884	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	12081744	1			T13	9224		T28	619		T37	12288
EscalateSt	7045580	1			T2	1311		T5	3126		T9	581
ScrapSt	93285	1			T3	746		T4	509		T17	249
PostTransSt	15836517	1			T2	607		T3	6445		T4	3642
TransProgSt	366464	1			T3	30		T4	195		T13	5502
TokenCheck1St	9563	1			T3	15		T4	9		T13	30
TokenCheck0St	13084	1			T3	15		T4	9		T13	30
FlashRmaSt	30027	1			T3	36		T4	24		T13	59
TokenHashSt	35211543	1			T3	9987		T4	99868		T13	54306
TransCheckSt	29043	1			T3	15		T4	9		T13	30
CntProgSt	1489759	1			T2	18		T3	30		T4	210
CntIncrSt	37437	1			T2	9		T3	15		T4	9
ClkMuxSt	37655	1			T2	9		T3	15		T4	9
IdleSt	25895777	1			T1	3549		T2	1518		T3	33614
ResetSt	7501518	1			T1	130		T2	962		T3	1383
arcs[ResetSt=>IdleSt]	55699	1			T1	1		T2	10		T3	16
arcs[IdleSt=>ScrapSt]	279	1			T3	1		T4	1		T17	2
arcs[IdleSt=>ClkMuxSt]	37499	1			T2	9		T3	15		T4	9
arcs[ClkMuxSt=>CntIncrSt]	37437	1			T2	9		T3	15		T4	9
arcs[CntIncrSt=>PostTransSt]	2172	1			T16	19		T17	4		T32	9
arcs[CntIncrSt=>CntProgSt]	35208	1			T2	9		T3	15		T4	9
arcs[CntProgSt=>PostTransSt]	5067	1			T2	9		T5	4		T9	4
arcs[CntProgSt=>TransCheckSt]	29043	1			T3	15		T4	9		T13	30
arcs[TransCheckSt=>PostTransSt]	4081	1			T14	54		T16	12		T17	11
arcs[TransCheckSt=>TokenHashSt]	24836	1			T3	15		T4	9		T13	30
arcs[TokenHashSt=>PostTransSt]	10976	1			T14	16		T29	89		T16	54
arcs[TokenHashSt=>FlashRmaSt]	13187	1			T3	15		T4	9		T13	30
arcs[FlashRmaSt=>TokenCheck0St]	13084	1			T3	15		T4	9		T13	30
arcs[TokenCheck0St=>PostTransSt]	3485	1			T14	18		T16	16		T17	4
arcs[TokenCheck0St=>TokenCheck1St]	9563	1			T3	15		T4	9		T13	30
arcs[TokenCheck1St=>PostTransSt]	743	1			T14	9		T16	5		T17	1
arcs[TransProgSt=>PostTransSt]	7942	1			T3	15		T4	9		T13	30
arcs[IdleSt=>EscalateSt]	207	1			T51	4		T49	7		T52	5
arcs[ClkMuxSt=>EscalateSt]	62	1			T48	1		T49	2		T50	6
arcs[CntIncrSt=>EscalateSt]	57	1			T51	1		T48	4		T52	1
arcs[CntProgSt=>EscalateSt]	1098	1			T51	17		T48	33		T49	39
arcs[TransCheckSt=>EscalateSt]	126	1			T52	2		T56	5		T57	8
arcs[TokenHashSt=>EscalateSt]	673	1			T51	9		T48	9		T49	11
arcs[FlashRmaSt=>EscalateSt]	103	1			T51	1		T49	3		T52	2
arcs[TokenCheck0St=>EscalateSt]	36	1			T51	1		T49	1		T52	1
arcs[TokenCheck1St=>EscalateSt]	158	1			T48	5		T52	5		T50	4
arcs[TransProgSt=>EscalateSt]	720	1			T51	13		T48	34		T49	13
arcs[PostTransSt=>EscalateSt]	5318	1			T2	9		T5	4		T9	4
arcs[InvalidSt=>EscalateSt]	13533	1			T13	5		T28	5		T37	67

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7501352	1			T1	130		T2	962		T3	1383
auto[0]	auto[IdleSt]	25895631	1			T1	3549		T2	1518		T3	33614
auto[0]	auto[ClkMuxSt]	37610	1			T2	9		T3	15		T4	9
auto[0]	auto[CntIncrSt]	37397	1			T2	9		T3	15		T4	9
auto[0]	auto[CntProgSt]	1489020	1			T2	18		T3	30		T4	210
auto[0]	auto[TransCheckSt]	28965	1			T3	15		T4	9		T13	30
auto[0]	auto[TokenHashSt]	35211100	1			T3	9987		T4	99868		T13	54306
auto[0]	auto[FlashRmaSt]	29962	1			T3	36		T4	24		T13	59
auto[0]	auto[TokenCheck0St]	13059	1			T3	15		T4	9		T13	30
auto[0]	auto[TokenCheck1St]	9450	1			T3	15		T4	9		T13	30
auto[0]	auto[TransProgSt]	365967	1			T3	30		T4	195		T13	5502
auto[0]	auto[PostTransSt]	15833856	1			T2	602		T3	6445		T4	3642
auto[0]	auto[ScrapSt]	93239	1			T3	746		T4	509		T17	249
auto[0]	auto[EscalateSt]	5661969	1			T2	821		T5	2835		T9	385
auto[0]	auto[InvalidSt]	12075008	1			T13	9222		T28	615		T37	12257
auto[1]	auto[ResetSt]	166	1			T51	1		T48	3		T49	2
auto[1]	auto[IdleSt]	146	1			T51	3		T49	3		T52	5
auto[1]	auto[ClkMuxSt]	45	1			T49	2		T50	4		T57	2
auto[1]	auto[CntIncrSt]	40	1			T51	1		T48	2		T52	1
auto[1]	auto[CntProgSt]	739	1			T51	11		T48	24		T49	25
auto[1]	auto[TransCheckSt]	78	1			T52	1		T56	2		T57	5
auto[1]	auto[TokenHashSt]	443	1			T51	7		T48	5		T49	7
auto[1]	auto[FlashRmaSt]	65	1			T51	1		T49	2		T52	2
auto[1]	auto[TokenCheck0St]	25	1			T49	1		T52	1		T207	1
auto[1]	auto[TokenCheck1St]	113	1			T48	4		T52	5		T50	3
auto[1]	auto[TransProgSt]	497	1			T51	10		T48	19		T49	12
auto[1]	auto[PostTransSt]	2661	1			T2	5		T5	3		T9	2
auto[1]	auto[ScrapSt]	46	1			T48	1		T49	2		T52	1
auto[1]	auto[EscalateSt]	1383611	1			T2	490		T5	291		T9	196
auto[1]	auto[InvalidSt]	6736	1			T13	2		T28	4		T37	31

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7501355	1			T1	130		T2	962		T3	1383
auto[0]	auto[IdleSt]	25895652	1			T1	3549		T2	1518		T3	33614
auto[0]	auto[ClkMuxSt]	37613	1			T2	9		T3	15		T4	9
auto[0]	auto[CntIncrSt]	37391	1			T2	9		T3	15		T4	9
auto[0]	auto[CntProgSt]	1489028	1			T2	18		T3	30		T4	210
auto[0]	auto[TransCheckSt]	28961	1			T3	15		T4	9		T13	30
auto[0]	auto[TokenHashSt]	35211105	1			T3	9987		T4	99868		T13	54306
auto[0]	auto[FlashRmaSt]	29956	1			T3	36		T4	24		T13	59
auto[0]	auto[TokenCheck0St]	13057	1			T3	15		T4	9		T13	30
auto[0]	auto[TokenCheck1St]	9461	1			T3	15		T4	9		T13	30
auto[0]	auto[TransProgSt]	366003	1			T3	30		T4	195		T13	5502
auto[0]	auto[PostTransSt]	15833789	1			T2	603		T3	6445		T4	3642
auto[0]	auto[ScrapSt]	93231	1			T3	746		T4	509		T17	249
auto[0]	auto[EscalateSt]	5661803	1			T2	919		T5	3029		T9	385
auto[0]	auto[InvalidSt]	12074947	1			T13	9221		T28	618		T37	12252
auto[1]	auto[ResetSt]	163	1			T51	2		T48	2		T49	1
auto[1]	auto[IdleSt]	125	1			T51	1		T49	7		T52	3
auto[1]	auto[ClkMuxSt]	42	1			T48	1		T49	1		T50	4
auto[1]	auto[CntIncrSt]	46	1			T51	1		T48	3		T52	1
auto[1]	auto[CntProgSt]	731	1			T51	10		T48	28		T49	29
auto[1]	auto[TransCheckSt]	82	1			T52	2		T56	3		T57	4
auto[1]	auto[TokenHashSt]	438	1			T51	6		T48	7		T49	8
auto[1]	auto[FlashRmaSt]	71	1			T51	1		T49	3		T52	1
auto[1]	auto[TokenCheck0St]	27	1			T51	1		T49	1		T52	1
auto[1]	auto[TokenCheck1St]	102	1			T48	3		T52	2		T50	1
auto[1]	auto[TransProgSt]	461	1			T51	8		T48	20		T49	5
auto[1]	auto[PostTransSt]	2728	1			T2	4		T5	1		T9	2
auto[1]	auto[ScrapSt]	54	1			T51	1		T48	1		T49	2
auto[1]	auto[EscalateSt]	1383777	1			T2	392		T5	97		T9	196
auto[1]	auto[InvalidSt]	6797	1			T13	3		T28	1		T37	36