Summary for Variable clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
55805 |
1 |
|
|
T1 |
13 |
|
T2 |
81 |
|
T3 |
63 |
auto[1] |
2031 |
1 |
|
|
T2 |
13 |
|
T3 |
16 |
|
T10 |
13 |
Summary for Variable clk_byp_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
57113 |
1 |
|
|
T1 |
13 |
|
T2 |
94 |
|
T3 |
79 |
auto[1] |
723 |
1 |
|
|
T61 |
12 |
|
T68 |
9 |
|
T48 |
16 |
Summary for Variable count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
55774 |
1 |
|
|
T1 |
13 |
|
T2 |
94 |
|
T3 |
79 |
auto[1] |
2062 |
1 |
|
|
T15 |
29 |
|
T16 |
41 |
|
T17 |
42 |
Summary for Variable count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
55764 |
1 |
|
|
T1 |
13 |
|
T2 |
94 |
|
T3 |
79 |
auto[1] |
2072 |
1 |
|
|
T15 |
13 |
|
T67 |
1 |
|
T16 |
35 |
Summary for Variable count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
55678 |
1 |
|
|
T1 |
11 |
|
T2 |
94 |
|
T3 |
79 |
auto[1] |
2158 |
1 |
|
|
T1 |
2 |
|
T14 |
1 |
|
T15 |
20 |
Summary for Variable err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for err_inj_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
err_inj |
52572 |
1 |
|
|
T1 |
8 |
|
T2 |
94 |
|
T3 |
79 |
no_err_inj |
5264 |
1 |
|
|
T1 |
5 |
|
T9 |
10 |
|
T13 |
18 |
Summary for Variable flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
55795 |
1 |
|
|
T1 |
13 |
|
T2 |
85 |
|
T3 |
69 |
auto[1] |
2041 |
1 |
|
|
T2 |
9 |
|
T3 |
10 |
|
T10 |
8 |
Summary for Variable flash_rma_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
57065 |
1 |
|
|
T1 |
13 |
|
T2 |
94 |
|
T3 |
79 |
auto[1] |
771 |
1 |
|
|
T61 |
12 |
|
T68 |
13 |
|
T48 |
22 |
Summary for Variable jtag_csr_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for jtag_csr_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
38760 |
1 |
|
|
T1 |
13 |
|
T9 |
10 |
|
T10 |
98 |
auto[1] |
19076 |
1 |
|
|
T2 |
94 |
|
T3 |
79 |
|
T4 |
78 |
Summary for Variable kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for kmac_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
55717 |
1 |
|
|
T1 |
12 |
|
T2 |
94 |
|
T3 |
79 |
auto[1] |
2119 |
1 |
|
|
T1 |
1 |
|
T14 |
1 |
|
T15 |
23 |
Summary for Variable lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for lc_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
55748 |
1 |
|
|
T1 |
13 |
|
T2 |
94 |
|
T3 |
79 |
auto[1] |
2088 |
1 |
|
|
T14 |
1 |
|
T15 |
21 |
|
T67 |
1 |
Summary for Variable otp_lc_data_i_valid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_lc_data_i_valid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
55755 |
1 |
|
|
T1 |
13 |
|
T2 |
94 |
|
T3 |
79 |
auto[1] |
2081 |
1 |
|
|
T14 |
2 |
|
T15 |
23 |
|
T43 |
1 |
Summary for Variable otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_partition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
55867 |
1 |
|
|
T1 |
13 |
|
T2 |
88 |
|
T3 |
73 |
auto[1] |
1969 |
1 |
|
|
T2 |
6 |
|
T3 |
6 |
|
T10 |
12 |
Summary for Variable otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_prog_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
55656 |
1 |
|
|
T1 |
13 |
|
T2 |
94 |
|
T3 |
79 |
auto[1] |
2180 |
1 |
|
|
T15 |
11 |
|
T64 |
7 |
|
T16 |
42 |
Summary for Variable otp_rma_token_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_rma_token_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
57074 |
1 |
|
|
T1 |
13 |
|
T2 |
94 |
|
T3 |
79 |
auto[1] |
762 |
1 |
|
|
T61 |
9 |
|
T68 |
13 |
|
T48 |
22 |
Summary for Variable otp_secrets_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_secrets_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
57100 |
1 |
|
|
T1 |
13 |
|
T2 |
94 |
|
T3 |
79 |
auto[1] |
736 |
1 |
|
|
T61 |
16 |
|
T68 |
14 |
|
T48 |
14 |
Summary for Variable otp_test_tokens_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_test_tokens_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
57088 |
1 |
|
|
T1 |
13 |
|
T2 |
94 |
|
T3 |
79 |
auto[1] |
748 |
1 |
|
|
T61 |
13 |
|
T68 |
9 |
|
T48 |
20 |
Summary for Variable post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for post_trans_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54809 |
1 |
|
|
T2 |
94 |
|
T3 |
79 |
|
T9 |
10 |
auto[1] |
3027 |
1 |
|
|
T1 |
13 |
|
T14 |
10 |
|
T43 |
14 |
Summary for Variable security_escalation_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for security_escalation_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54024 |
1 |
|
|
T1 |
13 |
|
T2 |
94 |
|
T3 |
79 |
auto[1] |
3812 |
1 |
|
|
T11 |
51 |
|
T41 |
97 |
|
T29 |
61 |
Summary for Variable state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
55758 |
1 |
|
|
T1 |
12 |
|
T2 |
94 |
|
T3 |
79 |
auto[1] |
2078 |
1 |
|
|
T1 |
1 |
|
T15 |
24 |
|
T43 |
2 |
Summary for Variable state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
55693 |
1 |
|
|
T1 |
13 |
|
T2 |
94 |
|
T3 |
79 |
auto[1] |
2143 |
1 |
|
|
T15 |
33 |
|
T43 |
1 |
|
T16 |
36 |
Summary for Variable state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
55712 |
1 |
|
|
T1 |
9 |
|
T2 |
94 |
|
T3 |
79 |
auto[1] |
2124 |
1 |
|
|
T1 |
4 |
|
T15 |
25 |
|
T43 |
1 |
Summary for Variable token_invalid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_invalid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
55768 |
1 |
|
|
T1 |
13 |
|
T2 |
82 |
|
T3 |
70 |
auto[1] |
2068 |
1 |
|
|
T2 |
12 |
|
T3 |
9 |
|
T10 |
13 |
Summary for Variable token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mismatch_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51936 |
1 |
|
|
T1 |
13 |
|
T2 |
83 |
|
T3 |
68 |
auto[1] |
5900 |
1 |
|
|
T2 |
11 |
|
T3 |
11 |
|
T10 |
16 |
Summary for Variable token_mux_ctrl_redun_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mux_ctrl_redun_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54093 |
1 |
|
|
T1 |
13 |
|
T2 |
94 |
|
T3 |
79 |
auto[1] |
3743 |
1 |
|
|
T42 |
54 |
|
T65 |
81 |
|
T66 |
64 |
Summary for Variable token_mux_digest_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for token_mux_digest_err_cp
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
57836 |
1 |
|
|
T1 |
13 |
|
T2 |
94 |
|
T3 |
79 |
Summary for Variable token_response_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_response_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
55791 |
1 |
|
|
T1 |
13 |
|
T2 |
77 |
|
T3 |
70 |
auto[1] |
2045 |
1 |
|
|
T2 |
17 |
|
T3 |
9 |
|
T10 |
11 |
Summary for Variable transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
55812 |
1 |
|
|
T1 |
13 |
|
T2 |
80 |
|
T3 |
69 |
auto[1] |
2024 |
1 |
|
|
T2 |
14 |
|
T3 |
10 |
|
T10 |
12 |
Summary for Variable transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
55742 |
1 |
|
|
T1 |
13 |
|
T2 |
82 |
|
T3 |
71 |
auto[1] |
2094 |
1 |
|
|
T2 |
12 |
|
T3 |
8 |
|
T10 |
13 |
Summary for Cross post_trans_err_inj_xp
Samples crossed: post_trans_err_cp err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_err_inj_xp
Bins
post_trans_err_cp | err_inj_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
err_inj |
51069 |
1 |
|
|
T2 |
94 |
|
T3 |
79 |
|
T10 |
98 |
auto[0] |
no_err_inj |
3740 |
1 |
|
|
T9 |
10 |
|
T13 |
18 |
|
T15 |
28 |
auto[1] |
err_inj |
1503 |
1 |
|
|
T1 |
8 |
|
T14 |
5 |
|
T43 |
7 |
auto[1] |
no_err_inj |
1524 |
1 |
|
|
T1 |
5 |
|
T14 |
5 |
|
T43 |
7 |
Summary for Cross post_trans_state_err_xp
Samples crossed: post_trans_err_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_err_xp
Bins
post_trans_err_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
52847 |
1 |
|
|
T2 |
94 |
|
T3 |
79 |
|
T9 |
10 |
auto[0] |
auto[1] |
1962 |
1 |
|
|
T15 |
33 |
|
T16 |
31 |
|
T17 |
34 |
auto[1] |
auto[0] |
2846 |
1 |
|
|
T1 |
13 |
|
T14 |
10 |
|
T43 |
13 |
auto[1] |
auto[1] |
181 |
1 |
|
|
T43 |
1 |
|
T16 |
5 |
|
T17 |
11 |
Summary for Cross post_trans_lc_fsm_backdoor_err_xp
Samples crossed: post_trans_err_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_lc_fsm_backdoor_err_xp
Bins
post_trans_err_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
52875 |
1 |
|
|
T2 |
94 |
|
T3 |
79 |
|
T9 |
10 |
auto[0] |
auto[1] |
1934 |
1 |
|
|
T15 |
21 |
|
T16 |
24 |
|
T17 |
44 |
auto[1] |
auto[0] |
2873 |
1 |
|
|
T1 |
13 |
|
T14 |
9 |
|
T43 |
14 |
auto[1] |
auto[1] |
154 |
1 |
|
|
T14 |
1 |
|
T67 |
1 |
|
T16 |
4 |
Summary for Cross post_trans_state_illegal_err_xp
Samples crossed: post_trans_err_cp state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_illegal_err_xp
Bins
post_trans_err_cp | state_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
52848 |
1 |
|
|
T2 |
94 |
|
T3 |
79 |
|
T9 |
10 |
auto[0] |
auto[1] |
1961 |
1 |
|
|
T15 |
25 |
|
T16 |
24 |
|
T17 |
34 |
auto[1] |
auto[0] |
2864 |
1 |
|
|
T1 |
9 |
|
T14 |
10 |
|
T43 |
13 |
auto[1] |
auto[1] |
163 |
1 |
|
|
T1 |
4 |
|
T43 |
1 |
|
T67 |
2 |
Summary for Cross post_trans_count_err_xp
Samples crossed: post_trans_err_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_err_xp
Bins
post_trans_err_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
52893 |
1 |
|
|
T2 |
94 |
|
T3 |
79 |
|
T9 |
10 |
auto[0] |
auto[1] |
1916 |
1 |
|
|
T15 |
13 |
|
T16 |
31 |
|
T17 |
37 |
auto[1] |
auto[0] |
2871 |
1 |
|
|
T1 |
13 |
|
T14 |
10 |
|
T43 |
14 |
auto[1] |
auto[1] |
156 |
1 |
|
|
T67 |
1 |
|
T16 |
4 |
|
T17 |
2 |
Summary for Cross post_trans_count_illegal_err_xp
Samples crossed: post_trans_err_cp count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_illegal_err_xp
Bins
post_trans_err_cp | count_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
52853 |
1 |
|
|
T2 |
94 |
|
T3 |
79 |
|
T9 |
10 |
auto[0] |
auto[1] |
1956 |
1 |
|
|
T15 |
20 |
|
T16 |
24 |
|
T17 |
36 |
auto[1] |
auto[0] |
2825 |
1 |
|
|
T1 |
11 |
|
T14 |
9 |
|
T43 |
14 |
auto[1] |
auto[1] |
202 |
1 |
|
|
T1 |
2 |
|
T14 |
1 |
|
T67 |
1 |
Summary for Cross post_trans_count_backdoor_err_xp
Samples crossed: post_trans_err_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_backdoor_err_xp
Bins
post_trans_err_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
52909 |
1 |
|
|
T2 |
94 |
|
T3 |
79 |
|
T9 |
10 |
auto[0] |
auto[1] |
1900 |
1 |
|
|
T15 |
29 |
|
T16 |
34 |
|
T17 |
34 |
auto[1] |
auto[0] |
2865 |
1 |
|
|
T1 |
13 |
|
T14 |
10 |
|
T43 |
14 |
auto[1] |
auto[1] |
162 |
1 |
|
|
T16 |
7 |
|
T17 |
8 |
|
T18 |
3 |
Summary for Cross jtag_clk_byp_error_rsp_xp
Samples crossed: jtag_csr_cp clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_clk_byp_error_rsp_xp
Bins
jtag_csr_cp | clk_byp_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37626 |
1 |
|
|
T1 |
13 |
|
T9 |
10 |
|
T10 |
85 |
auto[0] |
auto[1] |
1134 |
1 |
|
|
T10 |
13 |
|
T92 |
10 |
|
T228 |
6 |
auto[1] |
auto[0] |
18179 |
1 |
|
|
T2 |
81 |
|
T3 |
63 |
|
T4 |
70 |
auto[1] |
auto[1] |
897 |
1 |
|
|
T2 |
13 |
|
T3 |
16 |
|
T4 |
8 |
Summary for Cross jtag_flash_rma_error_rsp_xp
Samples crossed: jtag_csr_cp flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_flash_rma_error_rsp_xp
Bins
jtag_csr_cp | flash_rma_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37569 |
1 |
|
|
T1 |
13 |
|
T9 |
10 |
|
T10 |
90 |
auto[0] |
auto[1] |
1191 |
1 |
|
|
T10 |
8 |
|
T92 |
15 |
|
T228 |
11 |
auto[1] |
auto[0] |
18226 |
1 |
|
|
T2 |
85 |
|
T3 |
69 |
|
T4 |
67 |
auto[1] |
auto[1] |
850 |
1 |
|
|
T2 |
9 |
|
T3 |
10 |
|
T4 |
11 |
Summary for Cross jtag_otp_prog_err_xp
Samples crossed: jtag_csr_cp otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_prog_err_xp
Bins
jtag_csr_cp | otp_prog_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37532 |
1 |
|
|
T1 |
13 |
|
T9 |
10 |
|
T10 |
98 |
auto[0] |
auto[1] |
1228 |
1 |
|
|
T64 |
7 |
|
T16 |
20 |
|
T17 |
3 |
auto[1] |
auto[0] |
18124 |
1 |
|
|
T2 |
94 |
|
T3 |
79 |
|
T4 |
78 |
auto[1] |
auto[1] |
952 |
1 |
|
|
T15 |
11 |
|
T16 |
22 |
|
T17 |
33 |
Summary for Cross jtag_otp_partition_err_xp
Samples crossed: jtag_csr_cp otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_partition_err_xp
Bins
jtag_csr_cp | otp_partition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37578 |
1 |
|
|
T1 |
13 |
|
T9 |
10 |
|
T10 |
86 |
auto[0] |
auto[1] |
1182 |
1 |
|
|
T10 |
12 |
|
T92 |
8 |
|
T228 |
7 |
auto[1] |
auto[0] |
18289 |
1 |
|
|
T2 |
88 |
|
T3 |
73 |
|
T4 |
72 |
auto[1] |
auto[1] |
787 |
1 |
|
|
T2 |
6 |
|
T3 |
6 |
|
T4 |
6 |
Summary for Cross jtag_token_mismatch_err_xp
Samples crossed: jtag_csr_cp token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_token_mismatch_err_xp
Bins
jtag_csr_cp | token_mismatch_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
33717 |
1 |
|
|
T1 |
13 |
|
T9 |
10 |
|
T10 |
82 |
auto[0] |
auto[1] |
5043 |
1 |
|
|
T10 |
16 |
|
T92 |
9 |
|
T228 |
9 |
auto[1] |
auto[0] |
18219 |
1 |
|
|
T2 |
83 |
|
T3 |
68 |
|
T4 |
70 |
auto[1] |
auto[1] |
857 |
1 |
|
|
T2 |
11 |
|
T3 |
11 |
|
T4 |
8 |
Summary for Cross jtag_state_err_xp
Samples crossed: jtag_csr_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_err_xp
Bins
jtag_csr_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37607 |
1 |
|
|
T1 |
13 |
|
T9 |
10 |
|
T10 |
98 |
auto[0] |
auto[1] |
1153 |
1 |
|
|
T43 |
1 |
|
T16 |
13 |
|
T17 |
31 |
auto[1] |
auto[0] |
18086 |
1 |
|
|
T2 |
94 |
|
T3 |
79 |
|
T4 |
78 |
auto[1] |
auto[1] |
990 |
1 |
|
|
T15 |
33 |
|
T16 |
23 |
|
T17 |
14 |
Summary for Cross jtag_state_backdoor_err_xp
Samples crossed: jtag_csr_cp state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_backdoor_err_xp
Bins
jtag_csr_cp | state_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37601 |
1 |
|
|
T1 |
12 |
|
T9 |
10 |
|
T10 |
98 |
auto[0] |
auto[1] |
1159 |
1 |
|
|
T1 |
1 |
|
T43 |
2 |
|
T16 |
15 |
auto[1] |
auto[0] |
18157 |
1 |
|
|
T2 |
94 |
|
T3 |
79 |
|
T4 |
78 |
auto[1] |
auto[1] |
919 |
1 |
|
|
T15 |
24 |
|
T16 |
18 |
|
T17 |
16 |
Summary for Cross jtag_lc_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_lc_fsm_backdoor_err_xp
Bins
jtag_csr_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37595 |
1 |
|
|
T1 |
13 |
|
T9 |
10 |
|
T10 |
98 |
auto[0] |
auto[1] |
1165 |
1 |
|
|
T14 |
1 |
|
T67 |
1 |
|
T16 |
12 |
auto[1] |
auto[0] |
18153 |
1 |
|
|
T2 |
94 |
|
T3 |
79 |
|
T4 |
78 |
auto[1] |
auto[1] |
923 |
1 |
|
|
T15 |
21 |
|
T16 |
16 |
|
T17 |
14 |
Summary for Cross jtag_kmac_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_kmac_fsm_backdoor_err_xp
Bins
jtag_csr_cp | kmac_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37612 |
1 |
|
|
T1 |
12 |
|
T9 |
10 |
|
T10 |
98 |
auto[0] |
auto[1] |
1148 |
1 |
|
|
T1 |
1 |
|
T14 |
1 |
|
T43 |
2 |
auto[1] |
auto[0] |
18105 |
1 |
|
|
T2 |
94 |
|
T3 |
79 |
|
T4 |
78 |
auto[1] |
auto[1] |
971 |
1 |
|
|
T15 |
23 |
|
T16 |
22 |
|
T17 |
22 |
Summary for Cross jtag_count_err_xp
Samples crossed: jtag_csr_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_err_xp
Bins
jtag_csr_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37646 |
1 |
|
|
T1 |
13 |
|
T9 |
10 |
|
T10 |
98 |
auto[0] |
auto[1] |
1114 |
1 |
|
|
T67 |
1 |
|
T16 |
13 |
|
T17 |
19 |
auto[1] |
auto[0] |
18118 |
1 |
|
|
T2 |
94 |
|
T3 |
79 |
|
T4 |
78 |
auto[1] |
auto[1] |
958 |
1 |
|
|
T15 |
13 |
|
T16 |
22 |
|
T17 |
20 |
Summary for Cross jtag_count_backdoor_err_xp
Samples crossed: jtag_csr_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_backdoor_err_xp
Bins
jtag_csr_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37645 |
1 |
|
|
T1 |
13 |
|
T9 |
10 |
|
T10 |
98 |
auto[0] |
auto[1] |
1115 |
1 |
|
|
T16 |
16 |
|
T17 |
18 |
|
T18 |
3 |
auto[1] |
auto[0] |
18129 |
1 |
|
|
T2 |
94 |
|
T3 |
79 |
|
T4 |
78 |
auto[1] |
auto[1] |
947 |
1 |
|
|
T15 |
29 |
|
T16 |
25 |
|
T17 |
24 |
Summary for Cross jtag_transition_err_xp
Samples crossed: jtag_csr_cp transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_err_xp
Bins
jtag_csr_cp | transition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37576 |
1 |
|
|
T1 |
13 |
|
T9 |
10 |
|
T10 |
85 |
auto[0] |
auto[1] |
1184 |
1 |
|
|
T10 |
13 |
|
T92 |
16 |
|
T228 |
8 |
auto[1] |
auto[0] |
18166 |
1 |
|
|
T2 |
82 |
|
T3 |
71 |
|
T4 |
61 |
auto[1] |
auto[1] |
910 |
1 |
|
|
T2 |
12 |
|
T3 |
8 |
|
T4 |
17 |
Summary for Cross jtag_transition_count_err_xp
Samples crossed: jtag_csr_cp transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_count_err_xp
Bins
jtag_csr_cp | transition_count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37595 |
1 |
|
|
T1 |
13 |
|
T9 |
10 |
|
T10 |
86 |
auto[0] |
auto[1] |
1165 |
1 |
|
|
T10 |
12 |
|
T92 |
13 |
|
T228 |
6 |
auto[1] |
auto[0] |
18217 |
1 |
|
|
T2 |
80 |
|
T3 |
69 |
|
T4 |
68 |
auto[1] |
auto[1] |
859 |
1 |
|
|
T2 |
14 |
|
T3 |
10 |
|
T4 |
10 |
Summary for Cross jtag_post_trans_err_xp
Samples crossed: jtag_csr_cp post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_post_trans_err_xp
Bins
jtag_csr_cp | post_trans_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37296 |
1 |
|
|
T9 |
10 |
|
T10 |
98 |
|
T11 |
51 |
auto[0] |
auto[1] |
1464 |
1 |
|
|
T1 |
13 |
|
T14 |
10 |
|
T43 |
14 |
auto[1] |
auto[0] |
17513 |
1 |
|
|
T2 |
94 |
|
T3 |
79 |
|
T4 |
78 |
auto[1] |
auto[1] |
1563 |
1 |
|
|
T16 |
55 |
|
T17 |
63 |
|
T32 |
23 |