Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

119052728

1

T1

5756

T2

556695

T3

297837

auto[1]

1467646

1

T1

297

T2

792

T3

495

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

119028216

1

T1

5954

T2

556992

T3

297243

auto[1]

1492158

1

T1

99

T2

495

T3

1089

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	8141899	1			T1	1313		T2	8336		T3	7150
auto[IdleSt]	24149232	1			T1	1183		T2	263101		T3	152757
auto[ClkMuxSt]	37725	1			T1	5		T2	94		T3	79
auto[CntIncrSt]	37453	1			T1	5		T2	94		T3	79
auto[CntProgSt]	2117516	1			T1	141		T2	24057		T3	9179
auto[TransCheckSt]	29423	1			T1	5		T2	67		T3	53
auto[TokenHashSt]	47993837	1			T1	344		T2	43228		T3	3854
auto[FlashRmaSt]	30170	1			T1	28		T2	108		T3	16
auto[TokenCheck0St]	13540	1			T1	5		T2	15		T3	16
auto[TokenCheck1St]	10069	1			T1	5		T2	6		T3	6
auto[TransProgSt]	611737	1			T1	87		T2	1931		T3	863
auto[PostTransSt]	14919755	1			T1	1278		T2	203306		T3	112769
auto[ScrapSt]	161912	1			T9	27		T13	21		T15	3581
auto[EscalateSt]	7866002	1			T1	1044		T2	13144		T3	11511
auto[InvalidSt]	14397946	1			T1	610		T14	680		T15	278804

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	2158	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	14397946	1			T1	610		T14	680		T15	278804
EscalateSt	7866002	1			T1	1044		T2	13144		T3	11511
ScrapSt	161912	1			T9	27		T13	21		T15	3581
PostTransSt	14919755	1			T1	1278		T2	203306		T3	112769
TransProgSt	611737	1			T1	87		T2	1931		T3	863
TokenCheck1St	10069	1			T1	5		T2	6		T3	6
TokenCheck0St	13540	1			T1	5		T2	15		T3	16
FlashRmaSt	30170	1			T1	28		T2	108		T3	16
TokenHashSt	47993837	1			T1	344		T2	43228		T3	3854
TransCheckSt	29423	1			T1	5		T2	67		T3	53
CntProgSt	2117516	1			T1	141		T2	24057		T3	9179
CntIncrSt	37453	1			T1	5		T2	94		T3	79
ClkMuxSt	37725	1			T1	5		T2	94		T3	79
IdleSt	24149232	1			T1	1183		T2	263101		T3	152757
ResetSt	8141899	1			T1	1313		T2	8336		T3	7150
arcs[ResetSt=>IdleSt]	57965	1			T1	14		T2	95		T3	80
arcs[IdleSt=>ScrapSt]	310	1			T9	1		T13	1		T15	1
arcs[IdleSt=>ClkMuxSt]	37507	1			T1	5		T2	94		T3	79
arcs[ClkMuxSt=>CntIncrSt]	37453	1			T1	5		T2	94		T3	79
arcs[CntIncrSt=>PostTransSt]	2027	1			T2	14		T3	10		T10	12
arcs[CntIncrSt=>CntProgSt]	35360	1			T1	5		T2	80		T3	69
arcs[CntProgSt=>PostTransSt]	4865	1			T2	13		T3	16		T10	13
arcs[CntProgSt=>TransCheckSt]	29423	1			T1	5		T2	67		T3	53
arcs[TransCheckSt=>PostTransSt]	3935	1			T2	12		T3	8		T10	13
arcs[TransCheckSt=>TokenHashSt]	25344	1			T1	5		T2	55		T3	45
arcs[TokenHashSt=>PostTransSt]	10974	1			T2	40		T3	29		T10	40
arcs[TokenHashSt=>FlashRmaSt]	13656	1			T1	5		T2	15		T3	16
arcs[FlashRmaSt=>TokenCheck0St]	13540	1			T1	5		T2	15		T3	16
arcs[TokenCheck0St=>PostTransSt]	3444	1			T2	9		T3	10		T10	7
arcs[TokenCheck0St=>TokenCheck1St]	10069	1			T1	5		T2	6		T3	6
arcs[TokenCheck1St=>PostTransSt]	700	1			T15	1		T42	6		T61	1
arcs[TransProgSt=>PostTransSt]	8487	1			T1	5		T2	6		T3	6
arcs[IdleSt=>EscalateSt]	211	1			T11	7		T29	6		T55	5
arcs[ClkMuxSt=>EscalateSt]	54	1			T41	3		T55	1		T56	1
arcs[CntIncrSt=>EscalateSt]	66	1			T41	2		T29	1		T55	3
arcs[CntProgSt=>EscalateSt]	1072	1			T11	22		T41	19		T29	25
arcs[TransCheckSt=>EscalateSt]	144	1			T41	7		T29	1		T55	2
arcs[TokenHashSt=>EscalateSt]	714	1			T11	5		T41	22		T29	9
arcs[FlashRmaSt=>EscalateSt]	116	1			T41	3		T29	1		T47	1
arcs[TokenCheck0St=>EscalateSt]	27	1			T41	2		T55	1		T60	2
arcs[TokenCheck1St=>EscalateSt]	141	1			T11	2		T41	4		T29	3
arcs[TransProgSt=>EscalateSt]	741	1			T11	14		T41	18		T29	11
arcs[PostTransSt=>EscalateSt]	5110	1			T2	13		T3	16		T10	13
arcs[InvalidSt=>EscalateSt]	15473	1			T1	4		T14	3		T15	165

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	8141719	1			T1	1313		T2	8336		T3	7150
auto[0]	auto[IdleSt]	24149083	1			T1	1183		T2	263101		T3	152757
auto[0]	auto[ClkMuxSt]	37686	1			T1	5		T2	94		T3	79
auto[0]	auto[CntIncrSt]	37406	1			T1	5		T2	94		T3	79
auto[0]	auto[CntProgSt]	2116819	1			T1	141		T2	24057		T3	9179
auto[0]	auto[TransCheckSt]	29315	1			T1	5		T2	67		T3	53
auto[0]	auto[TokenHashSt]	47993363	1			T1	344		T2	43228		T3	3854
auto[0]	auto[FlashRmaSt]	30089	1			T1	28		T2	108		T3	16
auto[0]	auto[TokenCheck0St]	13521	1			T1	5		T2	15		T3	16
auto[0]	auto[TokenCheck1St]	9977	1			T1	5		T2	6		T3	6
auto[0]	auto[TransProgSt]	611260	1			T1	87		T2	1931		T3	863
auto[0]	auto[PostTransSt]	14917202	1			T1	1278		T2	203298		T3	112764
auto[0]	auto[ScrapSt]	161858	1			T9	27		T13	21		T15	3581
auto[0]	auto[EscalateSt]	6410977	1			T1	750		T2	12360		T3	11021
auto[0]	auto[InvalidSt]	14390295	1			T1	607		T14	679		T15	278705
auto[1]	auto[ResetSt]	180	1			T11	1		T41	5		T29	2
auto[1]	auto[IdleSt]	149	1			T11	3		T29	2		T55	5
auto[1]	auto[ClkMuxSt]	39	1			T41	2		T225	1		T226	1
auto[1]	auto[CntIncrSt]	47	1			T41	1		T29	1		T55	2
auto[1]	auto[CntProgSt]	697	1			T11	12		T41	11		T29	11
auto[1]	auto[TransCheckSt]	108	1			T41	4		T29	1		T55	2
auto[1]	auto[TokenHashSt]	474	1			T11	1		T41	17		T29	8
auto[1]	auto[FlashRmaSt]	81	1			T41	3		T29	1		T47	1
auto[1]	auto[TokenCheck0St]	19	1			T41	1		T55	1		T60	2
auto[1]	auto[TokenCheck1St]	92	1			T11	1		T41	2		T29	2
auto[1]	auto[TransProgSt]	477	1			T11	8		T41	10		T29	6
auto[1]	auto[PostTransSt]	2553	1			T2	8		T3	5		T10	3
auto[1]	auto[ScrapSt]	54	1			T41	1		T29	2		T60	5
auto[1]	auto[EscalateSt]	1455025	1			T1	294		T2	784		T3	490
auto[1]	auto[InvalidSt]	7651	1			T1	3		T14	1		T15	99

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	8141717	1			T1	1313		T2	8336		T3	7150
auto[0]	auto[IdleSt]	24149087	1			T1	1183		T2	263101		T3	152757
auto[0]	auto[ClkMuxSt]	37694	1			T1	5		T2	94		T3	79
auto[0]	auto[CntIncrSt]	37408	1			T1	5		T2	94		T3	79
auto[0]	auto[CntProgSt]	2116798	1			T1	141		T2	24057		T3	9179
auto[0]	auto[TransCheckSt]	29336	1			T1	5		T2	67		T3	53
auto[0]	auto[TokenHashSt]	47993362	1			T1	344		T2	43228		T3	3854
auto[0]	auto[FlashRmaSt]	30095	1			T1	28		T2	108		T3	16
auto[0]	auto[TokenCheck0St]	13522	1			T1	5		T2	15		T3	16
auto[0]	auto[TokenCheck1St]	9970	1			T1	5		T2	6		T3	6
auto[0]	auto[TransProgSt]	611242	1			T1	87		T2	1931		T3	863
auto[0]	auto[PostTransSt]	14917136	1			T1	1278		T2	203301		T3	112758
auto[0]	auto[ScrapSt]	161855	1			T9	27		T13	21		T15	3581
auto[0]	auto[EscalateSt]	6386712	1			T1	946		T2	12654		T3	10433
auto[0]	auto[InvalidSt]	14390124	1			T1	609		T14	678		T15	278738
auto[1]	auto[ResetSt]	182	1			T41	2		T29	2		T55	4
auto[1]	auto[IdleSt]	145	1			T11	4		T29	6		T55	1
auto[1]	auto[ClkMuxSt]	31	1			T41	1		T55	1		T56	1
auto[1]	auto[CntIncrSt]	45	1			T41	1		T55	3		T56	1
auto[1]	auto[CntProgSt]	718	1			T11	15		T41	14		T29	21
auto[1]	auto[TransCheckSt]	87	1			T41	4		T29	1		T55	2
auto[1]	auto[TokenHashSt]	475	1			T11	4		T41	12		T29	4
auto[1]	auto[FlashRmaSt]	75	1			T41	2		T29	1		T55	2
auto[1]	auto[TokenCheck0St]	18	1			T41	2		T60	1		T227	1
auto[1]	auto[TokenCheck1St]	99	1			T11	2		T41	4		T29	1
auto[1]	auto[TransProgSt]	495	1			T11	8		T41	14		T29	9
auto[1]	auto[PostTransSt]	2619	1			T2	5		T3	11		T10	10
auto[1]	auto[ScrapSt]	57	1			T41	2		T29	1		T56	2
auto[1]	auto[EscalateSt]	1479290	1			T1	98		T2	490		T3	1078
auto[1]	auto[InvalidSt]	7822	1			T1	1		T14	2		T15	66