Summary for Variable clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51595 |
1 |
|
|
T1 |
1 |
|
T3 |
19 |
|
T4 |
51 |
auto[1] |
1907 |
1 |
|
|
T13 |
13 |
|
T18 |
20 |
|
T19 |
21 |
Summary for Variable clk_byp_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52795 |
1 |
|
|
T1 |
1 |
|
T3 |
19 |
|
T4 |
51 |
auto[1] |
707 |
1 |
|
|
T15 |
9 |
|
T59 |
15 |
|
T37 |
12 |
Summary for Variable count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51683 |
1 |
|
|
T1 |
1 |
|
T3 |
19 |
|
T4 |
51 |
auto[1] |
1819 |
1 |
|
|
T6 |
12 |
|
T9 |
4 |
|
T10 |
11 |
Summary for Variable count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51699 |
1 |
|
|
T1 |
1 |
|
T3 |
19 |
|
T4 |
51 |
auto[1] |
1803 |
1 |
|
|
T6 |
6 |
|
T9 |
6 |
|
T10 |
10 |
Summary for Variable count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51743 |
1 |
|
|
T1 |
1 |
|
T3 |
19 |
|
T4 |
51 |
auto[1] |
1759 |
1 |
|
|
T6 |
10 |
|
T9 |
7 |
|
T10 |
5 |
Summary for Variable err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for err_inj_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
err_inj |
48450 |
1 |
|
|
T1 |
1 |
|
T3 |
19 |
|
T4 |
51 |
no_err_inj |
5052 |
1 |
|
|
T16 |
9 |
|
T17 |
8 |
|
T34 |
8 |
Summary for Variable flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51528 |
1 |
|
|
T1 |
1 |
|
T3 |
19 |
|
T4 |
51 |
auto[1] |
1974 |
1 |
|
|
T13 |
13 |
|
T18 |
23 |
|
T19 |
10 |
Summary for Variable flash_rma_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52736 |
1 |
|
|
T1 |
1 |
|
T3 |
19 |
|
T4 |
51 |
auto[1] |
766 |
1 |
|
|
T15 |
17 |
|
T59 |
12 |
|
T37 |
12 |
Summary for Variable jtag_csr_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for jtag_csr_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
37699 |
1 |
|
|
T1 |
1 |
|
T3 |
19 |
|
T4 |
51 |
auto[1] |
15803 |
1 |
|
|
T6 |
79 |
|
T9 |
54 |
|
T10 |
71 |
Summary for Variable kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for kmac_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51769 |
1 |
|
|
T1 |
1 |
|
T3 |
19 |
|
T4 |
51 |
auto[1] |
1733 |
1 |
|
|
T6 |
10 |
|
T9 |
6 |
|
T10 |
9 |
Summary for Variable lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for lc_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51751 |
1 |
|
|
T1 |
1 |
|
T3 |
19 |
|
T4 |
51 |
auto[1] |
1751 |
1 |
|
|
T6 |
9 |
|
T9 |
8 |
|
T10 |
5 |
Summary for Variable otp_lc_data_i_valid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_lc_data_i_valid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51662 |
1 |
|
|
T1 |
1 |
|
T3 |
19 |
|
T4 |
51 |
auto[1] |
1840 |
1 |
|
|
T6 |
8 |
|
T9 |
2 |
|
T10 |
9 |
Summary for Variable otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_partition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51619 |
1 |
|
|
T1 |
1 |
|
T3 |
19 |
|
T4 |
51 |
auto[1] |
1883 |
1 |
|
|
T13 |
13 |
|
T18 |
20 |
|
T19 |
8 |
Summary for Variable otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_prog_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51591 |
1 |
|
|
T4 |
51 |
|
T11 |
100 |
|
T12 |
92 |
auto[1] |
1911 |
1 |
|
|
T1 |
1 |
|
T3 |
19 |
|
T56 |
14 |
Summary for Variable otp_rma_token_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_rma_token_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52758 |
1 |
|
|
T1 |
1 |
|
T3 |
19 |
|
T4 |
51 |
auto[1] |
744 |
1 |
|
|
T15 |
9 |
|
T59 |
15 |
|
T37 |
12 |
Summary for Variable otp_secrets_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_secrets_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52762 |
1 |
|
|
T1 |
1 |
|
T3 |
19 |
|
T4 |
51 |
auto[1] |
740 |
1 |
|
|
T15 |
9 |
|
T59 |
20 |
|
T37 |
14 |
Summary for Variable otp_test_tokens_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_test_tokens_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52784 |
1 |
|
|
T1 |
1 |
|
T3 |
19 |
|
T4 |
51 |
auto[1] |
718 |
1 |
|
|
T15 |
13 |
|
T59 |
10 |
|
T37 |
4 |
Summary for Variable post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for post_trans_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50852 |
1 |
|
|
T1 |
1 |
|
T3 |
19 |
|
T4 |
51 |
auto[1] |
2650 |
1 |
|
|
T16 |
15 |
|
T17 |
14 |
|
T18 |
14 |
Summary for Variable security_escalation_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for security_escalation_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49631 |
1 |
|
|
T1 |
1 |
|
T3 |
19 |
|
T4 |
51 |
auto[1] |
3871 |
1 |
|
|
T11 |
100 |
|
T33 |
76 |
|
T43 |
88 |
Summary for Variable state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51596 |
1 |
|
|
T1 |
1 |
|
T3 |
19 |
|
T4 |
51 |
auto[1] |
1906 |
1 |
|
|
T6 |
12 |
|
T9 |
4 |
|
T10 |
5 |
Summary for Variable state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51674 |
1 |
|
|
T1 |
1 |
|
T3 |
19 |
|
T4 |
51 |
auto[1] |
1828 |
1 |
|
|
T6 |
8 |
|
T9 |
5 |
|
T10 |
7 |
Summary for Variable state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51727 |
1 |
|
|
T1 |
1 |
|
T3 |
19 |
|
T4 |
51 |
auto[1] |
1775 |
1 |
|
|
T6 |
4 |
|
T9 |
12 |
|
T10 |
10 |
Summary for Variable token_invalid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_invalid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51575 |
1 |
|
|
T1 |
1 |
|
T3 |
19 |
|
T4 |
51 |
auto[1] |
1927 |
1 |
|
|
T13 |
9 |
|
T18 |
17 |
|
T19 |
12 |
Summary for Variable token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mismatch_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
47766 |
1 |
|
|
T1 |
1 |
|
T3 |
19 |
|
T4 |
51 |
auto[1] |
5736 |
1 |
|
|
T12 |
92 |
|
T13 |
8 |
|
T32 |
83 |
Summary for Variable token_mux_ctrl_redun_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mux_ctrl_redun_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49800 |
1 |
|
|
T1 |
1 |
|
T3 |
19 |
|
T11 |
100 |
auto[1] |
3702 |
1 |
|
|
T4 |
51 |
|
T57 |
63 |
|
T58 |
75 |
Summary for Variable token_mux_digest_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for token_mux_digest_err_cp
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53502 |
1 |
|
|
T1 |
1 |
|
T3 |
19 |
|
T4 |
51 |
Summary for Variable token_response_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_response_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51643 |
1 |
|
|
T1 |
1 |
|
T3 |
19 |
|
T4 |
51 |
auto[1] |
1859 |
1 |
|
|
T13 |
12 |
|
T18 |
19 |
|
T19 |
9 |
Summary for Variable transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51645 |
1 |
|
|
T1 |
1 |
|
T3 |
19 |
|
T4 |
51 |
auto[1] |
1857 |
1 |
|
|
T13 |
19 |
|
T18 |
22 |
|
T19 |
9 |
Summary for Variable transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51568 |
1 |
|
|
T1 |
1 |
|
T3 |
19 |
|
T4 |
51 |
auto[1] |
1934 |
1 |
|
|
T13 |
10 |
|
T18 |
17 |
|
T19 |
17 |
Summary for Cross post_trans_err_inj_xp
Samples crossed: post_trans_err_cp err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_err_inj_xp
Bins
post_trans_err_cp | err_inj_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
err_inj |
47093 |
1 |
|
|
T1 |
1 |
|
T3 |
19 |
|
T4 |
51 |
auto[0] |
no_err_inj |
3759 |
1 |
|
|
T34 |
8 |
|
T53 |
3 |
|
T30 |
96 |
auto[1] |
err_inj |
1357 |
1 |
|
|
T16 |
6 |
|
T17 |
6 |
|
T18 |
7 |
auto[1] |
no_err_inj |
1293 |
1 |
|
|
T16 |
9 |
|
T17 |
8 |
|
T18 |
7 |
Summary for Cross post_trans_state_err_xp
Samples crossed: post_trans_err_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_err_xp
Bins
post_trans_err_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
49162 |
1 |
|
|
T1 |
1 |
|
T3 |
19 |
|
T4 |
51 |
auto[0] |
auto[1] |
1690 |
1 |
|
|
T6 |
8 |
|
T9 |
5 |
|
T10 |
7 |
auto[1] |
auto[0] |
2512 |
1 |
|
|
T16 |
13 |
|
T17 |
14 |
|
T18 |
14 |
auto[1] |
auto[1] |
138 |
1 |
|
|
T16 |
2 |
|
T30 |
4 |
|
T90 |
2 |
Summary for Cross post_trans_lc_fsm_backdoor_err_xp
Samples crossed: post_trans_err_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_lc_fsm_backdoor_err_xp
Bins
post_trans_err_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
49258 |
1 |
|
|
T1 |
1 |
|
T3 |
19 |
|
T4 |
51 |
auto[0] |
auto[1] |
1594 |
1 |
|
|
T6 |
9 |
|
T9 |
8 |
|
T10 |
5 |
auto[1] |
auto[0] |
2493 |
1 |
|
|
T16 |
14 |
|
T17 |
12 |
|
T18 |
14 |
auto[1] |
auto[1] |
157 |
1 |
|
|
T16 |
1 |
|
T17 |
2 |
|
T30 |
4 |
Summary for Cross post_trans_state_illegal_err_xp
Samples crossed: post_trans_err_cp state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_illegal_err_xp
Bins
post_trans_err_cp | state_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
49223 |
1 |
|
|
T1 |
1 |
|
T3 |
19 |
|
T4 |
51 |
auto[0] |
auto[1] |
1629 |
1 |
|
|
T6 |
4 |
|
T9 |
12 |
|
T10 |
10 |
auto[1] |
auto[0] |
2504 |
1 |
|
|
T16 |
15 |
|
T17 |
14 |
|
T18 |
12 |
auto[1] |
auto[1] |
146 |
1 |
|
|
T18 |
2 |
|
T30 |
1 |
|
T223 |
1 |
Summary for Cross post_trans_count_err_xp
Samples crossed: post_trans_err_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_err_xp
Bins
post_trans_err_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
49184 |
1 |
|
|
T1 |
1 |
|
T3 |
19 |
|
T4 |
51 |
auto[0] |
auto[1] |
1668 |
1 |
|
|
T6 |
6 |
|
T9 |
6 |
|
T10 |
10 |
auto[1] |
auto[0] |
2515 |
1 |
|
|
T16 |
14 |
|
T17 |
14 |
|
T18 |
14 |
auto[1] |
auto[1] |
135 |
1 |
|
|
T16 |
1 |
|
T30 |
6 |
|
T223 |
3 |
Summary for Cross post_trans_count_illegal_err_xp
Samples crossed: post_trans_err_cp count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_illegal_err_xp
Bins
post_trans_err_cp | count_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
49252 |
1 |
|
|
T1 |
1 |
|
T3 |
19 |
|
T4 |
51 |
auto[0] |
auto[1] |
1600 |
1 |
|
|
T6 |
10 |
|
T9 |
7 |
|
T10 |
5 |
auto[1] |
auto[0] |
2491 |
1 |
|
|
T16 |
15 |
|
T17 |
13 |
|
T18 |
13 |
auto[1] |
auto[1] |
159 |
1 |
|
|
T17 |
1 |
|
T18 |
1 |
|
T30 |
7 |
Summary for Cross post_trans_count_backdoor_err_xp
Samples crossed: post_trans_err_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_backdoor_err_xp
Bins
post_trans_err_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
49198 |
1 |
|
|
T1 |
1 |
|
T3 |
19 |
|
T4 |
51 |
auto[0] |
auto[1] |
1654 |
1 |
|
|
T6 |
12 |
|
T9 |
4 |
|
T10 |
11 |
auto[1] |
auto[0] |
2485 |
1 |
|
|
T16 |
15 |
|
T17 |
13 |
|
T18 |
12 |
auto[1] |
auto[1] |
165 |
1 |
|
|
T17 |
1 |
|
T18 |
2 |
|
T30 |
3 |
Summary for Cross jtag_clk_byp_error_rsp_xp
Samples crossed: jtag_csr_cp clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_clk_byp_error_rsp_xp
Bins
jtag_csr_cp | clk_byp_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36509 |
1 |
|
|
T1 |
1 |
|
T3 |
19 |
|
T4 |
51 |
auto[0] |
auto[1] |
1190 |
1 |
|
|
T13 |
13 |
|
T18 |
15 |
|
T30 |
19 |
auto[1] |
auto[0] |
15086 |
1 |
|
|
T6 |
79 |
|
T9 |
54 |
|
T10 |
71 |
auto[1] |
auto[1] |
717 |
1 |
|
|
T18 |
5 |
|
T19 |
21 |
|
T30 |
11 |
Summary for Cross jtag_flash_rma_error_rsp_xp
Samples crossed: jtag_csr_cp flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_flash_rma_error_rsp_xp
Bins
jtag_csr_cp | flash_rma_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36455 |
1 |
|
|
T1 |
1 |
|
T3 |
19 |
|
T4 |
51 |
auto[0] |
auto[1] |
1244 |
1 |
|
|
T13 |
13 |
|
T18 |
11 |
|
T30 |
18 |
auto[1] |
auto[0] |
15073 |
1 |
|
|
T6 |
79 |
|
T9 |
54 |
|
T10 |
71 |
auto[1] |
auto[1] |
730 |
1 |
|
|
T18 |
12 |
|
T19 |
10 |
|
T30 |
7 |
Summary for Cross jtag_otp_prog_err_xp
Samples crossed: jtag_csr_cp otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_prog_err_xp
Bins
jtag_csr_cp | otp_prog_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36507 |
1 |
|
|
T4 |
51 |
|
T11 |
100 |
|
T12 |
92 |
auto[0] |
auto[1] |
1192 |
1 |
|
|
T1 |
1 |
|
T3 |
19 |
|
T56 |
14 |
auto[1] |
auto[0] |
15084 |
1 |
|
|
T6 |
79 |
|
T9 |
54 |
|
T10 |
71 |
auto[1] |
auto[1] |
719 |
1 |
|
|
T30 |
33 |
|
T159 |
8 |
|
T90 |
5 |
Summary for Cross jtag_otp_partition_err_xp
Samples crossed: jtag_csr_cp otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_partition_err_xp
Bins
jtag_csr_cp | otp_partition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36513 |
1 |
|
|
T1 |
1 |
|
T3 |
19 |
|
T4 |
51 |
auto[0] |
auto[1] |
1186 |
1 |
|
|
T13 |
13 |
|
T18 |
12 |
|
T30 |
19 |
auto[1] |
auto[0] |
15106 |
1 |
|
|
T6 |
79 |
|
T9 |
54 |
|
T10 |
71 |
auto[1] |
auto[1] |
697 |
1 |
|
|
T18 |
8 |
|
T19 |
8 |
|
T30 |
6 |
Summary for Cross jtag_token_mismatch_err_xp
Samples crossed: jtag_csr_cp token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_token_mismatch_err_xp
Bins
jtag_csr_cp | token_mismatch_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
32658 |
1 |
|
|
T1 |
1 |
|
T3 |
19 |
|
T4 |
51 |
auto[0] |
auto[1] |
5041 |
1 |
|
|
T12 |
92 |
|
T13 |
8 |
|
T32 |
83 |
auto[1] |
auto[0] |
15108 |
1 |
|
|
T6 |
79 |
|
T9 |
54 |
|
T10 |
71 |
auto[1] |
auto[1] |
695 |
1 |
|
|
T18 |
8 |
|
T19 |
10 |
|
T30 |
12 |
Summary for Cross jtag_state_err_xp
Samples crossed: jtag_csr_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_err_xp
Bins
jtag_csr_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36701 |
1 |
|
|
T1 |
1 |
|
T3 |
19 |
|
T4 |
51 |
auto[0] |
auto[1] |
998 |
1 |
|
|
T67 |
7 |
|
T49 |
9 |
|
T224 |
11 |
auto[1] |
auto[0] |
14973 |
1 |
|
|
T6 |
71 |
|
T9 |
49 |
|
T10 |
64 |
auto[1] |
auto[1] |
830 |
1 |
|
|
T6 |
8 |
|
T9 |
5 |
|
T10 |
7 |
Summary for Cross jtag_state_backdoor_err_xp
Samples crossed: jtag_csr_cp state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_backdoor_err_xp
Bins
jtag_csr_cp | state_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36675 |
1 |
|
|
T1 |
1 |
|
T3 |
19 |
|
T4 |
51 |
auto[0] |
auto[1] |
1024 |
1 |
|
|
T67 |
11 |
|
T49 |
14 |
|
T224 |
4 |
auto[1] |
auto[0] |
14921 |
1 |
|
|
T6 |
67 |
|
T9 |
50 |
|
T10 |
66 |
auto[1] |
auto[1] |
882 |
1 |
|
|
T6 |
12 |
|
T9 |
4 |
|
T10 |
5 |
Summary for Cross jtag_lc_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_lc_fsm_backdoor_err_xp
Bins
jtag_csr_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36777 |
1 |
|
|
T1 |
1 |
|
T3 |
19 |
|
T4 |
51 |
auto[0] |
auto[1] |
922 |
1 |
|
|
T67 |
8 |
|
T49 |
8 |
|
T224 |
7 |
auto[1] |
auto[0] |
14974 |
1 |
|
|
T6 |
70 |
|
T9 |
46 |
|
T10 |
66 |
auto[1] |
auto[1] |
829 |
1 |
|
|
T6 |
9 |
|
T9 |
8 |
|
T10 |
5 |
Summary for Cross jtag_kmac_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_kmac_fsm_backdoor_err_xp
Bins
jtag_csr_cp | kmac_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36726 |
1 |
|
|
T1 |
1 |
|
T3 |
19 |
|
T4 |
51 |
auto[0] |
auto[1] |
973 |
1 |
|
|
T67 |
10 |
|
T18 |
1 |
|
T49 |
7 |
auto[1] |
auto[0] |
15043 |
1 |
|
|
T6 |
69 |
|
T9 |
48 |
|
T10 |
62 |
auto[1] |
auto[1] |
760 |
1 |
|
|
T6 |
10 |
|
T9 |
6 |
|
T10 |
9 |
Summary for Cross jtag_count_err_xp
Samples crossed: jtag_csr_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_err_xp
Bins
jtag_csr_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36683 |
1 |
|
|
T1 |
1 |
|
T3 |
19 |
|
T4 |
51 |
auto[0] |
auto[1] |
1016 |
1 |
|
|
T67 |
8 |
|
T49 |
18 |
|
T224 |
11 |
auto[1] |
auto[0] |
15016 |
1 |
|
|
T6 |
73 |
|
T9 |
48 |
|
T10 |
61 |
auto[1] |
auto[1] |
787 |
1 |
|
|
T6 |
6 |
|
T9 |
6 |
|
T10 |
10 |
Summary for Cross jtag_count_backdoor_err_xp
Samples crossed: jtag_csr_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_backdoor_err_xp
Bins
jtag_csr_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36716 |
1 |
|
|
T1 |
1 |
|
T3 |
19 |
|
T4 |
51 |
auto[0] |
auto[1] |
983 |
1 |
|
|
T67 |
8 |
|
T18 |
2 |
|
T49 |
10 |
auto[1] |
auto[0] |
14967 |
1 |
|
|
T6 |
67 |
|
T9 |
50 |
|
T10 |
60 |
auto[1] |
auto[1] |
836 |
1 |
|
|
T6 |
12 |
|
T9 |
4 |
|
T10 |
11 |
Summary for Cross jtag_transition_err_xp
Samples crossed: jtag_csr_cp transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_err_xp
Bins
jtag_csr_cp | transition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36499 |
1 |
|
|
T1 |
1 |
|
T3 |
19 |
|
T4 |
51 |
auto[0] |
auto[1] |
1200 |
1 |
|
|
T13 |
10 |
|
T18 |
9 |
|
T30 |
12 |
auto[1] |
auto[0] |
15069 |
1 |
|
|
T6 |
79 |
|
T9 |
54 |
|
T10 |
71 |
auto[1] |
auto[1] |
734 |
1 |
|
|
T18 |
8 |
|
T19 |
17 |
|
T30 |
14 |
Summary for Cross jtag_transition_count_err_xp
Samples crossed: jtag_csr_cp transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_count_err_xp
Bins
jtag_csr_cp | transition_count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36542 |
1 |
|
|
T1 |
1 |
|
T3 |
19 |
|
T4 |
51 |
auto[0] |
auto[1] |
1157 |
1 |
|
|
T13 |
19 |
|
T18 |
12 |
|
T30 |
23 |
auto[1] |
auto[0] |
15103 |
1 |
|
|
T6 |
79 |
|
T9 |
54 |
|
T10 |
71 |
auto[1] |
auto[1] |
700 |
1 |
|
|
T18 |
10 |
|
T19 |
9 |
|
T30 |
18 |
Summary for Cross jtag_post_trans_err_xp
Samples crossed: jtag_csr_cp post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_post_trans_err_xp
Bins
jtag_csr_cp | post_trans_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36032 |
1 |
|
|
T1 |
1 |
|
T3 |
19 |
|
T4 |
51 |
auto[0] |
auto[1] |
1667 |
1 |
|
|
T18 |
14 |
|
T30 |
33 |
|
T77 |
11 |
auto[1] |
auto[0] |
14820 |
1 |
|
|
T6 |
79 |
|
T9 |
54 |
|
T10 |
71 |
auto[1] |
auto[1] |
983 |
1 |
|
|
T16 |
15 |
|
T17 |
14 |
|
T30 |
29 |