Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

104738989

1

T1

1912

T2

63799

T3

8305

auto[1]

1358469

1

T3

594

T11

11927

T13

297

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

104730896

1

T1

1813

T2

63799

T3

7612

auto[1]

1366562

1

T1

99

T3

1287

T11

13137

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	7406291	1			T1	170		T2	77		T3	3725
auto[IdleSt]	21240306	1			T1	1504		T2	63722		T3	1489
auto[ClkMuxSt]	36137	1			T1	1		T3	19		T4	51
auto[CntIncrSt]	35845	1			T1	1		T3	19		T4	51
auto[CntProgSt]	1597724	1			T1	12		T3	90		T4	5632
auto[TransCheckSt]	28322	1			T4	51		T11	42		T12	92
auto[TokenHashSt]	43074962	1			T4	2646		T11	649		T12	1040
auto[FlashRmaSt]	30193	1			T4	46		T11	36		T13	72
auto[TokenCheck0St]	13257	1			T4	19		T11	27		T13	26
auto[TokenCheck1St]	9831	1			T4	6		T11	27		T13	14
auto[TransProgSt]	398430	1			T11	112		T13	47		T15	813
auto[PostTransSt]	12556848	1			T1	73		T3	1092		T4	7835
auto[ScrapSt]	128733	1			T11	3		T33	12		T34	15
auto[EscalateSt]	6823561	1			T1	151		T3	2465		T11	19406
auto[InvalidSt]	12715166	1			T6	268937		T9	116631		T15	1507

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1852	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	12715166	1			T6	268937		T9	116631		T15	1507
EscalateSt	6823561	1			T1	151		T3	2465		T11	19406
ScrapSt	128733	1			T11	3		T33	12		T34	15
PostTransSt	12556848	1			T1	73		T3	1092		T4	7835
TransProgSt	398430	1			T11	112		T13	47		T15	813
TokenCheck1St	9831	1			T4	6		T11	27		T13	14
TokenCheck0St	13257	1			T4	19		T11	27		T13	26
FlashRmaSt	30193	1			T4	46		T11	36		T13	72
TokenHashSt	43074962	1			T4	2646		T11	649		T12	1040
TransCheckSt	28322	1			T4	51		T11	42		T12	92
CntProgSt	1597724	1			T1	12		T3	90		T4	5632
CntIncrSt	35845	1			T1	1		T3	19		T4	51
ClkMuxSt	36137	1			T1	1		T3	19		T4	51
IdleSt	21240306	1			T1	1504		T2	63722		T3	1489
ResetSt	7406291	1			T1	170		T2	77		T3	3725
arcs[ResetSt=>IdleSt]	53925	1			T1	2		T2	1		T3	20
arcs[IdleSt=>ScrapSt]	304	1			T11	1		T33	4		T34	1
arcs[IdleSt=>ClkMuxSt]	35911	1			T1	1		T3	19		T4	51
arcs[ClkMuxSt=>CntIncrSt]	35845	1			T1	1		T3	19		T4	51
arcs[CntIncrSt=>PostTransSt]	1858	1			T13	19		T18	22		T19	9
arcs[CntIncrSt=>CntProgSt]	33909	1			T1	1		T3	19		T4	51
arcs[CntProgSt=>PostTransSt]	4481	1			T1	1		T3	19		T13	13
arcs[CntProgSt=>TransCheckSt]	28322	1			T4	51		T11	42		T12	92
arcs[TransCheckSt=>PostTransSt]	3781	1			T4	28		T13	10		T18	17
arcs[TransCheckSt=>TokenHashSt]	24408	1			T4	23		T11	41		T12	92
arcs[TokenHashSt=>PostTransSt]	10370	1			T4	4		T12	92		T13	29
arcs[TokenHashSt=>FlashRmaSt]	13360	1			T4	19		T11	28		T13	26
arcs[FlashRmaSt=>TokenCheck0St]	13257	1			T4	19		T11	27		T13	26
arcs[TokenCheck0St=>PostTransSt]	3398	1			T4	13		T13	12		T15	16
arcs[TokenCheck0St=>TokenCheck1St]	9831	1			T4	6		T11	27		T13	14
arcs[TokenCheck1St=>PostTransSt]	680	1			T4	6		T13	1		T18	2
arcs[TransProgSt=>PostTransSt]	8214	1			T11	1		T13	13		T15	17
arcs[IdleSt=>EscalateSt]	214	1			T11	13		T33	9		T43	8
arcs[ClkMuxSt=>EscalateSt]	66	1			T11	2		T33	2		T43	1
arcs[CntIncrSt=>EscalateSt]	78	1			T11	3		T33	2		T43	4
arcs[CntProgSt=>EscalateSt]	1106	1			T11	32		T33	26		T43	12
arcs[TransCheckSt=>EscalateSt]	133	1			T11	1		T43	8		T48	3
arcs[TokenHashSt=>EscalateSt]	678	1			T11	13		T33	7		T43	24
arcs[FlashRmaSt=>EscalateSt]	103	1			T11	1		T33	1		T43	1
arcs[TokenCheck0St=>EscalateSt]	28	1			T43	1		T46	1		T47	3
arcs[TokenCheck1St=>EscalateSt]	164	1			T11	3		T33	5		T43	4
arcs[TransProgSt=>EscalateSt]	773	1			T11	23		T33	17		T43	9
arcs[PostTransSt=>EscalateSt]	4734	1			T1	1		T3	19		T11	1
arcs[InvalidSt=>EscalateSt]	13358	1			T6	67		T9	40		T15	9

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7406124	1			T1	170		T2	77		T3	3725
auto[0]	auto[IdleSt]	21240168	1			T1	1504		T2	63722		T3	1489
auto[0]	auto[ClkMuxSt]	36091	1			T1	1		T3	19		T4	51
auto[0]	auto[CntIncrSt]	35796	1			T1	1		T3	19		T4	51
auto[0]	auto[CntProgSt]	1596988	1			T1	12		T3	90		T4	5632
auto[0]	auto[TransCheckSt]	28238	1			T4	51		T11	42		T12	92
auto[0]	auto[TokenHashSt]	43074535	1			T4	2646		T11	639		T12	1040
auto[0]	auto[FlashRmaSt]	30131	1			T4	46		T11	36		T13	72
auto[0]	auto[TokenCheck0St]	13235	1			T4	19		T11	27		T13	26
auto[0]	auto[TokenCheck1St]	9721	1			T4	6		T11	25		T13	14
auto[0]	auto[TransProgSt]	397927	1			T11	100		T13	47		T15	813
auto[0]	auto[PostTransSt]	12554420	1			T1	73		T3	1086		T4	7835
auto[0]	auto[ScrapSt]	128688	1			T11	3		T33	9		T34	15
auto[0]	auto[EscalateSt]	5476580	1			T1	151		T3	1877		T11	7539
auto[0]	auto[InvalidSt]	12708495	1			T6	268903		T9	116609		T15	1504
auto[1]	auto[ResetSt]	167	1			T11	4		T33	1		T43	5
auto[1]	auto[IdleSt]	138	1			T11	10		T33	9		T43	6
auto[1]	auto[ClkMuxSt]	46	1			T11	1		T43	1		T188	1
auto[1]	auto[CntIncrSt]	49	1			T33	1		T43	3		T188	1
auto[1]	auto[CntProgSt]	736	1			T11	20		T33	21		T43	6
auto[1]	auto[TransCheckSt]	84	1			T43	4		T221	4		T182	5
auto[1]	auto[TokenHashSt]	427	1			T11	10		T33	4		T43	13
auto[1]	auto[FlashRmaSt]	62	1			T33	1		T188	1		T83	1
auto[1]	auto[TokenCheck0St]	22	1			T47	3		T222	2		T184	1
auto[1]	auto[TokenCheck1St]	110	1			T11	2		T33	4		T188	1
auto[1]	auto[TransProgSt]	503	1			T11	12		T33	11		T43	7
auto[1]	auto[PostTransSt]	2428	1			T3	6		T11	1		T13	3
auto[1]	auto[ScrapSt]	45	1			T33	3		T43	1		T83	1
auto[1]	auto[EscalateSt]	1346981	1			T3	588		T11	11867		T13	294
auto[1]	auto[InvalidSt]	6671	1			T6	34		T9	22		T15	3

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7406120	1			T1	170		T2	77		T3	3725
auto[0]	auto[IdleSt]	21240161	1			T1	1504		T2	63722		T3	1489
auto[0]	auto[ClkMuxSt]	36096	1			T1	1		T3	19		T4	51
auto[0]	auto[CntIncrSt]	35794	1			T1	1		T3	19		T4	51
auto[0]	auto[CntProgSt]	1597000	1			T1	12		T3	90		T4	5632
auto[0]	auto[TransCheckSt]	28234	1			T4	51		T11	41		T12	92
auto[0]	auto[TokenHashSt]	43074501	1			T4	2646		T11	642		T12	1040
auto[0]	auto[FlashRmaSt]	30123	1			T4	46		T11	35		T13	72
auto[0]	auto[TokenCheck0St]	13244	1			T4	19		T11	27		T13	26
auto[0]	auto[TokenCheck1St]	9720	1			T4	6		T11	25		T13	14
auto[0]	auto[TransProgSt]	397889	1			T11	95		T13	47		T15	813
auto[0]	auto[PostTransSt]	12554470	1			T1	72		T3	1079		T4	7835
auto[0]	auto[ScrapSt]	128687	1			T11	2		T33	9		T34	15
auto[0]	auto[EscalateSt]	5468526	1			T1	53		T3	1191		T11	6337
auto[0]	auto[InvalidSt]	12708479	1			T6	268904		T9	116613		T15	1501
auto[1]	auto[ResetSt]	171	1			T11	5		T33	1		T43	3
auto[1]	auto[IdleSt]	145	1			T11	6		T33	5		T43	3
auto[1]	auto[ClkMuxSt]	41	1			T11	1		T33	2		T83	2
auto[1]	auto[CntIncrSt]	51	1			T11	3		T33	1		T43	3
auto[1]	auto[CntProgSt]	724	1			T11	24		T33	13		T43	11
auto[1]	auto[TransCheckSt]	88	1			T11	1		T43	5		T48	3
auto[1]	auto[TokenHashSt]	461	1			T11	7		T33	6		T43	17
auto[1]	auto[FlashRmaSt]	70	1			T11	1		T43	1		T83	3
auto[1]	auto[TokenCheck0St]	13	1			T43	1		T46	1		T47	1
auto[1]	auto[TokenCheck1St]	111	1			T11	2		T33	2		T43	4
auto[1]	auto[TransProgSt]	541	1			T11	17		T33	13		T43	6
auto[1]	auto[PostTransSt]	2378	1			T1	1		T3	13		T13	10
auto[1]	auto[ScrapSt]	46	1			T11	1		T33	3		T43	1
auto[1]	auto[EscalateSt]	1355035	1			T1	98		T3	1274		T11	13069
auto[1]	auto[InvalidSt]	6687	1			T6	33		T9	18		T15	6