Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.84 97.99 95.59 93.38 97.67 98.55 98.76 95.94


Total test records in report: 1001
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html
T1001 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.1961696816 Jun 23 05:02:42 PM PDT 24 Jun 23 05:02:43 PM PDT 24 15713022 ps

Test location /workspace/coverage/default/32.lc_ctrl_security_escalation.875480461
Short name T11
Test name
Test status
Simulation time 796491830 ps
CPU time 13.77 seconds
Started Jun 23 05:08:26 PM PDT 24
Finished Jun 23 05:08:40 PM PDT 24
Peak memory 226084 kb
Host smart-5a49abc1-1f35-4f95-925a-b92d3395861b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875480461 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_security_escalation.875480461
Directory /workspace/32.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all.2189293344
Short name T18
Test name
Test status
Simulation time 65763269918 ps
CPU time 114.63 seconds
Started Jun 23 05:06:45 PM PDT 24
Finished Jun 23 05:08:40 PM PDT 24
Peak memory 283608 kb
Host smart-cacc15f0-fcb8-4e4b-99ff-31689bcba447
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189293344 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.lc_ctrl_stress_all.2189293344
Directory /workspace/10.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all_with_rand_reset.3302785429
Short name T30
Test name
Test status
Simulation time 61181992803 ps
CPU time 548.02 seconds
Started Jun 23 05:07:13 PM PDT 24
Finished Jun 23 05:16:22 PM PDT 24
Peak memory 332864 kb
Host smart-134dd021-103e-40f8-b143-637f3dd22cfb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3302785429 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_stress_all_with_rand_reset.3302785429
Directory /workspace/15.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_mubi.1869454251
Short name T15
Test name
Test status
Simulation time 559675941 ps
CPU time 12.52 seconds
Started Jun 23 05:06:18 PM PDT 24
Finished Jun 23 05:06:32 PM PDT 24
Peak memory 226056 kb
Host smart-a0446be7-4c0e-4eda-b0b4-bb7fcb05e61b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869454251 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_mubi.1869454251
Directory /workspace/2.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.1609796004
Short name T115
Test name
Test status
Simulation time 27535936 ps
CPU time 1.76 seconds
Started Jun 23 05:02:19 PM PDT 24
Finished Jun 23 05:02:21 PM PDT 24
Peak memory 217888 kb
Host smart-f1cb4c70-7532-4642-a106-aa18dfee0232
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609796004 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_errors.1609796004
Directory /workspace/2.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/37.lc_ctrl_volatile_unlock_smoke.1780228036
Short name T14
Test name
Test status
Simulation time 12521230 ps
CPU time 0.96 seconds
Started Jun 23 05:08:48 PM PDT 24
Finished Jun 23 05:08:50 PM PDT 24
Peak memory 209028 kb
Host smart-385c7ec3-cbdb-446b-a990-1db81fc9e88d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780228036 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_c
trl_volatile_unlock_smoke.1780228036
Directory /workspace/37.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_stress_all.3514030613
Short name T109
Test name
Test status
Simulation time 23538486415 ps
CPU time 141.55 seconds
Started Jun 23 05:06:13 PM PDT 24
Finished Jun 23 05:08:36 PM PDT 24
Peak memory 222952 kb
Host smart-8fd2fee0-e671-43d5-b4c5-d85729e1aa42
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514030613 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.lc_ctrl_stress_all.3514030613
Directory /workspace/1.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_cm.3776087457
Short name T45
Test name
Test status
Simulation time 2507223011 ps
CPU time 39.22 seconds
Started Jun 23 05:06:18 PM PDT 24
Finished Jun 23 05:06:58 PM PDT 24
Peak memory 269540 kb
Host smart-f999d984-8957-48d8-81bd-280fe75a33f0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776087457 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_cm.3776087457
Directory /workspace/2.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_mux.3377630276
Short name T4
Test name
Test status
Simulation time 265556128 ps
CPU time 6.84 seconds
Started Jun 23 05:07:44 PM PDT 24
Finished Jun 23 05:07:52 PM PDT 24
Peak memory 218256 kb
Host smart-e28e1e55-aa17-4ae1-9d20-f0887658e848
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377630276 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_mux.
3377630276
Directory /workspace/24.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/42.lc_ctrl_security_escalation.1965554430
Short name T222
Test name
Test status
Simulation time 1320782868 ps
CPU time 11.79 seconds
Started Jun 23 05:09:22 PM PDT 24
Finished Jun 23 05:09:35 PM PDT 24
Peak memory 218284 kb
Host smart-70794a70-c97b-4663-84b9-b7d4151dda1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965554430 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_security_escalation.1965554430
Directory /workspace/42.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.3854933463
Short name T117
Test name
Test status
Simulation time 60601643 ps
CPU time 1.92 seconds
Started Jun 23 05:02:38 PM PDT 24
Finished Jun 23 05:02:41 PM PDT 24
Peak memory 221860 kb
Host smart-52a2f51b-22f7-4a12-99e9-ee9d8cb87a9d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854933463 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_intg
_err.3854933463
Directory /workspace/10.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_access.2206273382
Short name T22
Test name
Test status
Simulation time 1273678495 ps
CPU time 8.71 seconds
Started Jun 23 05:06:07 PM PDT 24
Finished Jun 23 05:06:16 PM PDT 24
Peak memory 217268 kb
Host smart-322dfe4d-6c4f-46b5-b6db-2e2bbb072b8d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206273382 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_access.2206273382
Directory /workspace/0.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/23.lc_ctrl_alert_test.420048696
Short name T76
Test name
Test status
Simulation time 65977390 ps
CPU time 0.94 seconds
Started Jun 23 05:07:44 PM PDT 24
Finished Jun 23 05:07:46 PM PDT 24
Peak memory 208928 kb
Host smart-d1d1870c-b19f-4d59-98c3-71b7de9aadd2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420048696 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_alert_test.420048696
Directory /workspace/23.lc_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.3572764549
Short name T199
Test name
Test status
Simulation time 58827524 ps
CPU time 1.34 seconds
Started Jun 23 05:02:16 PM PDT 24
Finished Jun 23 05:02:18 PM PDT 24
Peak memory 209344 kb
Host smart-0992e3ad-4f6a-4388-835e-164938cf4429
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572764549 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_aliasin
g.3572764549
Directory /workspace/0.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.2015729818
Short name T144
Test name
Test status
Simulation time 2027727936 ps
CPU time 14.71 seconds
Started Jun 23 05:02:16 PM PDT 24
Finished Jun 23 05:02:31 PM PDT 24
Peak memory 217076 kb
Host smart-90317ca3-7c7e-4acf-8daa-c4ced5600d77
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015729818 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_aliasing.2015729818
Directory /workspace/1.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/default/9.lc_ctrl_stress_all_with_rand_reset.957401997
Short name T147
Test name
Test status
Simulation time 63499973528 ps
CPU time 422.55 seconds
Started Jun 23 05:06:42 PM PDT 24
Finished Jun 23 05:13:45 PM PDT 24
Peak memory 316660 kb
Host smart-96b8229a-2531-404a-8129-2f3c1bc54682
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=957401997 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_stress_all_with_rand_reset.957401997
Directory /workspace/9.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.lc_ctrl_stress_all_with_rand_reset.2645848740
Short name T88
Test name
Test status
Simulation time 66478262171 ps
CPU time 1602.83 seconds
Started Jun 23 05:06:22 PM PDT 24
Finished Jun 23 05:33:05 PM PDT 24
Peak memory 513224 kb
Host smart-d94ee7cf-8910-446c-8025-7e4d1374b6d5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2645848740 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_stress_all_with_rand_reset.2645848740
Directory /workspace/3.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.3270096038
Short name T122
Test name
Test status
Simulation time 84901308 ps
CPU time 2.8 seconds
Started Jun 23 05:02:13 PM PDT 24
Finished Jun 23 05:02:16 PM PDT 24
Peak memory 222348 kb
Host smart-e78d1d07-1a93-49cd-86e2-af6880452398
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270096038 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_intg_
err.3270096038
Directory /workspace/0.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.2143792522
Short name T139
Test name
Test status
Simulation time 310166527 ps
CPU time 2.66 seconds
Started Jun 23 05:02:16 PM PDT 24
Finished Jun 23 05:02:19 PM PDT 24
Peak memory 221992 kb
Host smart-af7e60e6-e825-47d7-8ec1-e85e54ce43f0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143792522 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_intg_
err.2143792522
Directory /workspace/2.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_failure.1572423329
Short name T20
Test name
Test status
Simulation time 7222682763 ps
CPU time 37.6 seconds
Started Jun 23 05:06:08 PM PDT 24
Finished Jun 23 05:06:46 PM PDT 24
Peak memory 275528 kb
Host smart-4fc3fd18-1fc4-42a0-9658-895318d9b728
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572423329 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jta
g_state_failure.1572423329
Directory /workspace/0.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.3026712767
Short name T131
Test name
Test status
Simulation time 98241944 ps
CPU time 2.05 seconds
Started Jun 23 05:02:54 PM PDT 24
Finished Jun 23 05:02:56 PM PDT 24
Peak memory 221916 kb
Host smart-85de83da-488a-4a85-8a75-6f77a678b428
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026712767 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_intg
_err.3026712767
Directory /workspace/19.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/42.lc_ctrl_stress_all.833629681
Short name T36
Test name
Test status
Simulation time 6546701783 ps
CPU time 224.8 seconds
Started Jun 23 05:09:23 PM PDT 24
Finished Jun 23 05:13:08 PM PDT 24
Peak memory 283640 kb
Host smart-2f2511b2-d81b-4713-a89f-08ee63bb8c72
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833629681 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.lc_ctrl_stress_all.833629681
Directory /workspace/42.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_mubi.2668789531
Short name T59
Test name
Test status
Simulation time 634516523 ps
CPU time 13.81 seconds
Started Jun 23 05:09:23 PM PDT 24
Finished Jun 23 05:09:38 PM PDT 24
Peak memory 218936 kb
Host smart-275ff2b8-83c4-41a8-9fb4-fd108be0c7cf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668789531 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_mubi.2668789531
Directory /workspace/43.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.4150331300
Short name T124
Test name
Test status
Simulation time 45933417 ps
CPU time 2.35 seconds
Started Jun 23 05:02:41 PM PDT 24
Finished Jun 23 05:02:44 PM PDT 24
Peak memory 217576 kb
Host smart-6bf9b76f-aead-4504-9030-7ff85c2b2c3f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150331300 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_intg
_err.4150331300
Directory /workspace/12.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.3053020076
Short name T213
Test name
Test status
Simulation time 25908726 ps
CPU time 0.97 seconds
Started Jun 23 05:02:11 PM PDT 24
Finished Jun 23 05:02:12 PM PDT 24
Peak memory 209392 kb
Host smart-59c18443-2c7e-498b-9330-4552eef0c36d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053020076 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.lc_ctrl_jtag_same_csr_outstanding.3053020076
Directory /workspace/0.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.394523541
Short name T136
Test name
Test status
Simulation time 415695394 ps
CPU time 2 seconds
Started Jun 23 05:02:46 PM PDT 24
Finished Jun 23 05:02:48 PM PDT 24
Peak memory 221992 kb
Host smart-f3b3867f-e7ad-4ee0-bad5-ab75e3dfc89c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394523541 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_intg_
err.394523541
Directory /workspace/15.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.2917658210
Short name T126
Test name
Test status
Simulation time 117382442 ps
CPU time 2.88 seconds
Started Jun 23 05:02:23 PM PDT 24
Finished Jun 23 05:02:26 PM PDT 24
Peak memory 222304 kb
Host smart-cf4a8414-52d3-4d9a-9d90-660d59a08e76
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917658210 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_intg_
err.2917658210
Directory /workspace/3.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.3008312668
Short name T137
Test name
Test status
Simulation time 80457668 ps
CPU time 1.73 seconds
Started Jun 23 05:02:36 PM PDT 24
Finished Jun 23 05:02:38 PM PDT 24
Peak memory 221764 kb
Host smart-cfe6c357-f6d7-4a27-80a7-218de2846d38
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008312668 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_intg_
err.3008312668
Directory /workspace/9.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_claim_transition_if.3666221342
Short name T219
Test name
Test status
Simulation time 14070124 ps
CPU time 0.82 seconds
Started Jun 23 05:06:10 PM PDT 24
Finished Jun 23 05:06:11 PM PDT 24
Peak memory 208680 kb
Host smart-fededb89-385b-4e9d-ba52-e7c3eb2dc88c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666221342 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_claim_transition_if.3666221342
Directory /workspace/0.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/0.lc_ctrl_security_escalation.2988108128
Short name T435
Test name
Test status
Simulation time 1475961694 ps
CPU time 8.57 seconds
Started Jun 23 05:06:06 PM PDT 24
Finished Jun 23 05:06:15 PM PDT 24
Peak memory 225972 kb
Host smart-7f8b6524-3daa-4544-bf94-c12ee99ef7f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988108128 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_security_escalation.2988108128
Directory /workspace/0.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/2.lc_ctrl_claim_transition_if.828085772
Short name T217
Test name
Test status
Simulation time 37701389 ps
CPU time 0.94 seconds
Started Jun 23 05:06:17 PM PDT 24
Finished Jun 23 05:06:18 PM PDT 24
Peak memory 208944 kb
Host smart-3e82a844-e517-4b0a-9efb-282c9d898eb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828085772 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_claim_transition_if.828085772
Directory /workspace/2.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.31048511
Short name T141
Test name
Test status
Simulation time 60732210 ps
CPU time 2.59 seconds
Started Jun 23 05:02:41 PM PDT 24
Finished Jun 23 05:02:44 PM PDT 24
Peak memory 217748 kb
Host smart-4c0c02db-9741-422d-b760-ab217b70a995
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31048511 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_intg_e
rr.31048511
Directory /workspace/11.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.29031140
Short name T133
Test name
Test status
Simulation time 88891255 ps
CPU time 1.86 seconds
Started Jun 23 05:02:47 PM PDT 24
Finished Jun 23 05:02:49 PM PDT 24
Peak memory 222080 kb
Host smart-ac1bdec0-eae6-4a93-ade2-8cc3e3e630ab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29031140 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_intg_e
rr.29031140
Directory /workspace/17.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.2646043122
Short name T134
Test name
Test status
Simulation time 2076388363 ps
CPU time 3.12 seconds
Started Jun 23 05:02:49 PM PDT 24
Finished Jun 23 05:02:52 PM PDT 24
Peak memory 222412 kb
Host smart-5b1dc200-98c4-4cda-8858-80d9d5df28f0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646043122 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_intg
_err.2646043122
Directory /workspace/18.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/16.lc_ctrl_errors.2986247200
Short name T42
Test name
Test status
Simulation time 423114778 ps
CPU time 18.1 seconds
Started Jun 23 05:07:08 PM PDT 24
Finished Jun 23 05:07:26 PM PDT 24
Peak memory 218300 kb
Host smart-fa2f6d7a-84ef-428e-a5a2-c74e23c127fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986247200 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_errors.2986247200
Directory /workspace/16.lc_ctrl_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_post_trans.3474594843
Short name T16
Test name
Test status
Simulation time 399830540 ps
CPU time 12.35 seconds
Started Jun 23 05:06:15 PM PDT 24
Finished Jun 23 05:06:28 PM PDT 24
Peak memory 250720 kb
Host smart-b0325c84-637a-4e47-afcf-0ee59306b70c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474594843 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_state_post_trans.3474594843
Directory /workspace/1.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_regwen_during_op.652943140
Short name T34
Test name
Test status
Simulation time 1128731596 ps
CPU time 20.42 seconds
Started Jun 23 05:06:18 PM PDT 24
Finished Jun 23 05:06:39 PM PDT 24
Peak memory 217660 kb
Host smart-dc6c276d-4438-4844-8625-589ca590615f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652943140 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_regwen_during_op.652943140
Directory /workspace/2.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.3705952347
Short name T933
Test name
Test status
Simulation time 108866919 ps
CPU time 2.07 seconds
Started Jun 23 05:02:17 PM PDT 24
Finished Jun 23 05:02:20 PM PDT 24
Peak memory 209360 kb
Host smart-edd59177-b4cb-4285-a566-c8373cc70d89
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705952347 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_bit_bas
h.3705952347
Directory /workspace/0.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.1410372370
Short name T893
Test name
Test status
Simulation time 124735995 ps
CPU time 1.01 seconds
Started Jun 23 05:02:23 PM PDT 24
Finished Jun 23 05:02:25 PM PDT 24
Peak memory 209776 kb
Host smart-afb3655a-fc94-4d39-bd2d-82aafc9485e7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410372370 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_hw_rese
t.1410372370
Directory /workspace/0.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.3629828873
Short name T113
Test name
Test status
Simulation time 108968563 ps
CPU time 1.32 seconds
Started Jun 23 05:02:16 PM PDT 24
Finished Jun 23 05:02:18 PM PDT 24
Peak memory 218880 kb
Host smart-79006835-c74d-4788-9a41-ec49a8323780
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629828873 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 0.lc_ctrl_csr_mem_rw_with_rand_reset.3629828873
Directory /workspace/0.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.3041079551
Short name T909
Test name
Test status
Simulation time 49543942 ps
CPU time 1.03 seconds
Started Jun 23 05:02:16 PM PDT 24
Finished Jun 23 05:02:18 PM PDT 24
Peak memory 209372 kb
Host smart-6b7e7af4-5f31-4fad-a33c-650cbe195478
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041079551 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_rw.3041079551
Directory /workspace/0.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.245102862
Short name T889
Test name
Test status
Simulation time 169680220 ps
CPU time 1.13 seconds
Started Jun 23 05:02:13 PM PDT 24
Finished Jun 23 05:02:15 PM PDT 24
Peak memory 209264 kb
Host smart-33da0d29-cadd-446c-9e2b-1b16e590b236
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245102862 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 0.lc_ctrl_jtag_alert_test.245102862
Directory /workspace/0.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.3224380822
Short name T964
Test name
Test status
Simulation time 410681754 ps
CPU time 9.65 seconds
Started Jun 23 05:02:11 PM PDT 24
Finished Jun 23 05:02:21 PM PDT 24
Peak memory 217196 kb
Host smart-8ece377f-3697-4fc6-9fc7-88542b5585d0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224380822 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_aliasing.3224380822
Directory /workspace/0.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.3413555688
Short name T961
Test name
Test status
Simulation time 15604280769 ps
CPU time 43.68 seconds
Started Jun 23 05:02:09 PM PDT 24
Finished Jun 23 05:02:53 PM PDT 24
Peak memory 209156 kb
Host smart-471480ce-de9a-484e-92b2-831021916fbe
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413555688 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_bit_bash.3413555688
Directory /workspace/0.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.2836253634
Short name T877
Test name
Test status
Simulation time 61618642 ps
CPU time 2.17 seconds
Started Jun 23 05:02:13 PM PDT 24
Finished Jun 23 05:02:16 PM PDT 24
Peak memory 217516 kb
Host smart-a543ffa8-7591-4400-9c3d-7751b6665c2f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836253634 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_hw_reset.2836253634
Directory /workspace/0.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3402147286
Short name T167
Test name
Test status
Simulation time 152629229 ps
CPU time 5.18 seconds
Started Jun 23 05:02:12 PM PDT 24
Finished Jun 23 05:02:17 PM PDT 24
Peak memory 219384 kb
Host smart-1c1b9d27-4b17-4f06-ba33-4971527d30eb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340214
7286 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3402147286
Directory /workspace/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.2609990158
Short name T927
Test name
Test status
Simulation time 296583155 ps
CPU time 2.44 seconds
Started Jun 23 05:02:12 PM PDT 24
Finished Jun 23 05:02:15 PM PDT 24
Peak memory 209304 kb
Host smart-646d18fc-97ba-49b1-a70d-52f5bedb7629
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609990158 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.lc_ctrl_jtag_csr_rw.2609990158
Directory /workspace/0.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.2548777302
Short name T894
Test name
Test status
Simulation time 30682679 ps
CPU time 1 seconds
Started Jun 23 05:02:17 PM PDT 24
Finished Jun 23 05:02:18 PM PDT 24
Peak memory 209492 kb
Host smart-7cac474f-a623-4849-8318-d77ece6a5da5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548777302 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl
_same_csr_outstanding.2548777302
Directory /workspace/0.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.4256101469
Short name T906
Test name
Test status
Simulation time 129805819 ps
CPU time 4.63 seconds
Started Jun 23 05:02:11 PM PDT 24
Finished Jun 23 05:02:15 PM PDT 24
Peak memory 217688 kb
Host smart-1d2c5471-2d52-4806-80d3-8023a9773e60
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256101469 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_errors.4256101469
Directory /workspace/0.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.4058957044
Short name T985
Test name
Test status
Simulation time 78906895 ps
CPU time 0.99 seconds
Started Jun 23 05:02:17 PM PDT 24
Finished Jun 23 05:02:18 PM PDT 24
Peak memory 209420 kb
Host smart-1b2a7b87-2cc1-4ac3-ba4e-d25a7e2b9e78
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058957044 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_aliasin
g.4058957044
Directory /workspace/1.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.3113078337
Short name T954
Test name
Test status
Simulation time 66606997 ps
CPU time 2.65 seconds
Started Jun 23 05:02:16 PM PDT 24
Finished Jun 23 05:02:19 PM PDT 24
Peak memory 216840 kb
Host smart-7dc47657-0d2d-4cc9-ba32-4da875c3462a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113078337 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_bit_bas
h.3113078337
Directory /workspace/1.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.3509156688
Short name T946
Test name
Test status
Simulation time 49275533 ps
CPU time 0.91 seconds
Started Jun 23 05:02:18 PM PDT 24
Finished Jun 23 05:02:19 PM PDT 24
Peak memory 209712 kb
Host smart-e1f49d99-9983-43b7-b52a-75868b2bcb65
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509156688 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_hw_rese
t.3509156688
Directory /workspace/1.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.3475156825
Short name T165
Test name
Test status
Simulation time 71374821 ps
CPU time 1.4 seconds
Started Jun 23 05:02:17 PM PDT 24
Finished Jun 23 05:02:19 PM PDT 24
Peak memory 218748 kb
Host smart-23e4767c-971a-47e1-a262-1ce33bd9fc47
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475156825 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 1.lc_ctrl_csr_mem_rw_with_rand_reset.3475156825
Directory /workspace/1.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.1791194556
Short name T197
Test name
Test status
Simulation time 62260146 ps
CPU time 1.03 seconds
Started Jun 23 05:02:14 PM PDT 24
Finished Jun 23 05:02:15 PM PDT 24
Peak memory 209392 kb
Host smart-c259d885-50ff-41e2-a71a-7ff58903ccae
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791194556 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_rw.1791194556
Directory /workspace/1.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.2961061397
Short name T983
Test name
Test status
Simulation time 62582878 ps
CPU time 0.83 seconds
Started Jun 23 05:02:19 PM PDT 24
Finished Jun 23 05:02:20 PM PDT 24
Peak memory 209268 kb
Host smart-61f25e40-4753-4163-a48d-cdc6ec319ba0
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961061397 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.lc_ctrl_jtag_alert_test.2961061397
Directory /workspace/1.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.3500201926
Short name T882
Test name
Test status
Simulation time 834188862 ps
CPU time 7.08 seconds
Started Jun 23 05:02:20 PM PDT 24
Finished Jun 23 05:02:27 PM PDT 24
Peak memory 208792 kb
Host smart-61c1d573-6457-4132-aa9c-db20d7604d4f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500201926 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_bit_bash.3500201926
Directory /workspace/1.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.648426152
Short name T986
Test name
Test status
Simulation time 363435869 ps
CPU time 2.35 seconds
Started Jun 23 05:02:22 PM PDT 24
Finished Jun 23 05:02:25 PM PDT 24
Peak memory 217552 kb
Host smart-058d7c7a-bc4b-45fe-b5f2-d5dc1ff54f2f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648426152 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 1.lc_ctrl_jtag_csr_hw_reset.648426152
Directory /workspace/1.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3336165035
Short name T919
Test name
Test status
Simulation time 88272542 ps
CPU time 2.34 seconds
Started Jun 23 05:02:17 PM PDT 24
Finished Jun 23 05:02:19 PM PDT 24
Peak memory 218704 kb
Host smart-b95e249e-03c8-456d-aba3-97f870405f15
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333616
5035 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3336165035
Directory /workspace/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.769733234
Short name T942
Test name
Test status
Simulation time 117946914 ps
CPU time 1.79 seconds
Started Jun 23 05:02:16 PM PDT 24
Finished Jun 23 05:02:18 PM PDT 24
Peak memory 209360 kb
Host smart-08b39224-d5ba-4b6e-afbf-8e40d4eb2df2
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769733234 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.lc_ctrl_jtag_csr_rw.769733234
Directory /workspace/1.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.1984867870
Short name T123
Test name
Test status
Simulation time 260065631 ps
CPU time 1.06 seconds
Started Jun 23 05:02:16 PM PDT 24
Finished Jun 23 05:02:17 PM PDT 24
Peak memory 209408 kb
Host smart-ebb16e00-91bf-43d9-b3e8-a1b29625db7b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984867870 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.lc_ctrl_jtag_same_csr_outstanding.1984867870
Directory /workspace/1.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.3539629481
Short name T215
Test name
Test status
Simulation time 57571746 ps
CPU time 1.91 seconds
Started Jun 23 05:02:15 PM PDT 24
Finished Jun 23 05:02:18 PM PDT 24
Peak memory 211404 kb
Host smart-ad3eb63d-6593-4893-9fcf-1fd2fe20f269
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539629481 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl
_same_csr_outstanding.3539629481
Directory /workspace/1.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.1529452650
Short name T907
Test name
Test status
Simulation time 212623834 ps
CPU time 1.11 seconds
Started Jun 23 05:02:18 PM PDT 24
Finished Jun 23 05:02:20 PM PDT 24
Peak memory 217664 kb
Host smart-6bf2b420-f424-4a11-82f6-ce7d84e08590
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529452650 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_errors.1529452650
Directory /workspace/1.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.3923722075
Short name T125
Test name
Test status
Simulation time 160298481 ps
CPU time 2.82 seconds
Started Jun 23 05:02:17 PM PDT 24
Finished Jun 23 05:02:20 PM PDT 24
Peak memory 222300 kb
Host smart-92a06df7-e7d5-4f67-9477-37e530836ef9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923722075 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_intg_
err.3923722075
Directory /workspace/1.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.2324139974
Short name T973
Test name
Test status
Simulation time 21701147 ps
CPU time 1.42 seconds
Started Jun 23 05:02:38 PM PDT 24
Finished Jun 23 05:02:40 PM PDT 24
Peak memory 219644 kb
Host smart-6c154adc-bf1e-4c56-a602-67dc6667a3b5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324139974 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 10.lc_ctrl_csr_mem_rw_with_rand_reset.2324139974
Directory /workspace/10.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.1199494651
Short name T214
Test name
Test status
Simulation time 34816418 ps
CPU time 0.93 seconds
Started Jun 23 05:02:38 PM PDT 24
Finished Jun 23 05:02:39 PM PDT 24
Peak memory 208844 kb
Host smart-be921f36-e0de-47c3-8b35-bae70d9567ea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199494651 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_csr_rw.1199494651
Directory /workspace/10.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.62600024
Short name T966
Test name
Test status
Simulation time 68090917 ps
CPU time 1.11 seconds
Started Jun 23 05:02:37 PM PDT 24
Finished Jun 23 05:02:39 PM PDT 24
Peak memory 209496 kb
Host smart-b18ef084-03a3-4d69-b340-9618ee7b24ca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62600024 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_
same_csr_outstanding.62600024
Directory /workspace/10.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.284318470
Short name T132
Test name
Test status
Simulation time 104756636 ps
CPU time 2.62 seconds
Started Jun 23 05:02:40 PM PDT 24
Finished Jun 23 05:02:43 PM PDT 24
Peak memory 217736 kb
Host smart-2c5c9456-9d00-4d24-bd96-1fb224439b48
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284318470 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_errors.284318470
Directory /workspace/10.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.1961696816
Short name T1001
Test name
Test status
Simulation time 15713022 ps
CPU time 1.01 seconds
Started Jun 23 05:02:42 PM PDT 24
Finished Jun 23 05:02:43 PM PDT 24
Peak memory 217792 kb
Host smart-292fc6a0-6e29-4789-8423-10641f926530
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961696816 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 11.lc_ctrl_csr_mem_rw_with_rand_reset.1961696816
Directory /workspace/11.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.3389413046
Short name T969
Test name
Test status
Simulation time 19182647 ps
CPU time 1.21 seconds
Started Jun 23 05:02:42 PM PDT 24
Finished Jun 23 05:02:44 PM PDT 24
Peak memory 209476 kb
Host smart-7c7be3bd-0832-452a-b536-6730ba1bfe5c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389413046 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_csr_rw.3389413046
Directory /workspace/11.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.3187052490
Short name T911
Test name
Test status
Simulation time 96590678 ps
CPU time 2.03 seconds
Started Jun 23 05:02:41 PM PDT 24
Finished Jun 23 05:02:44 PM PDT 24
Peak memory 209352 kb
Host smart-20ed7c93-0e49-44d2-8393-d939ae7d3b0f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187052490 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctr
l_same_csr_outstanding.3187052490
Directory /workspace/11.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.968997642
Short name T975
Test name
Test status
Simulation time 407873835 ps
CPU time 3.33 seconds
Started Jun 23 05:02:36 PM PDT 24
Finished Jun 23 05:02:40 PM PDT 24
Peak memory 217676 kb
Host smart-4b5a6c5f-059d-4137-811c-029b081448c3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968997642 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_errors.968997642
Directory /workspace/11.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.2089644467
Short name T994
Test name
Test status
Simulation time 114957675 ps
CPU time 1.42 seconds
Started Jun 23 05:02:43 PM PDT 24
Finished Jun 23 05:02:45 PM PDT 24
Peak memory 219172 kb
Host smart-08db1d47-701b-43b5-8c86-301884c42d9a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089644467 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 12.lc_ctrl_csr_mem_rw_with_rand_reset.2089644467
Directory /workspace/12.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.711771555
Short name T200
Test name
Test status
Simulation time 52372100 ps
CPU time 0.89 seconds
Started Jun 23 05:02:42 PM PDT 24
Finished Jun 23 05:02:43 PM PDT 24
Peak memory 209460 kb
Host smart-1baea439-55f4-4f98-84de-bea0c68407ab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711771555 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_csr_rw.711771555
Directory /workspace/12.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.1724730642
Short name T935
Test name
Test status
Simulation time 23556600 ps
CPU time 1.51 seconds
Started Jun 23 05:02:41 PM PDT 24
Finished Jun 23 05:02:43 PM PDT 24
Peak memory 211400 kb
Host smart-0f4c3e07-c34d-4c5f-b8fa-ff4d40cbf9e8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724730642 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctr
l_same_csr_outstanding.1724730642
Directory /workspace/12.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.1106728869
Short name T940
Test name
Test status
Simulation time 176236871 ps
CPU time 1.66 seconds
Started Jun 23 05:02:42 PM PDT 24
Finished Jun 23 05:02:44 PM PDT 24
Peak memory 217740 kb
Host smart-72690177-8e7c-46c4-9913-103451a4beae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106728869 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_errors.1106728869
Directory /workspace/12.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.1915881205
Short name T186
Test name
Test status
Simulation time 25558021 ps
CPU time 1.19 seconds
Started Jun 23 05:02:40 PM PDT 24
Finished Jun 23 05:02:42 PM PDT 24
Peak memory 217720 kb
Host smart-41936a41-c433-4846-95a8-34a71495eff5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915881205 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 13.lc_ctrl_csr_mem_rw_with_rand_reset.1915881205
Directory /workspace/13.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.3609438288
Short name T925
Test name
Test status
Simulation time 45445933 ps
CPU time 0.85 seconds
Started Jun 23 05:02:43 PM PDT 24
Finished Jun 23 05:02:44 PM PDT 24
Peak memory 209208 kb
Host smart-68153ec7-c823-4282-a1e8-9cd28fab5819
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609438288 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_csr_rw.3609438288
Directory /workspace/13.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.1994482797
Short name T953
Test name
Test status
Simulation time 36422173 ps
CPU time 1.38 seconds
Started Jun 23 05:02:40 PM PDT 24
Finished Jun 23 05:02:42 PM PDT 24
Peak memory 217596 kb
Host smart-7b113300-5328-4057-8e85-7cb7a305b055
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994482797 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctr
l_same_csr_outstanding.1994482797
Directory /workspace/13.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.3411289652
Short name T988
Test name
Test status
Simulation time 95080346 ps
CPU time 1.84 seconds
Started Jun 23 05:02:42 PM PDT 24
Finished Jun 23 05:02:44 PM PDT 24
Peak memory 217764 kb
Host smart-2ca661c0-4432-428e-b687-9a6bdf81eebe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411289652 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_errors.3411289652
Directory /workspace/13.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.2604364301
Short name T138
Test name
Test status
Simulation time 92480841 ps
CPU time 1.79 seconds
Started Jun 23 05:02:42 PM PDT 24
Finished Jun 23 05:02:44 PM PDT 24
Peak memory 221476 kb
Host smart-5ccad3a9-1cb2-402e-a128-cfcbdff74516
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604364301 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_intg
_err.2604364301
Directory /workspace/13.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.1940655402
Short name T998
Test name
Test status
Simulation time 71336166 ps
CPU time 1.44 seconds
Started Jun 23 05:02:43 PM PDT 24
Finished Jun 23 05:02:45 PM PDT 24
Peak memory 218760 kb
Host smart-f5c7da8b-2f30-41bb-80f9-4812bd8cd116
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940655402 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 14.lc_ctrl_csr_mem_rw_with_rand_reset.1940655402
Directory /workspace/14.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.3570073724
Short name T201
Test name
Test status
Simulation time 34438853 ps
CPU time 0.95 seconds
Started Jun 23 05:02:41 PM PDT 24
Finished Jun 23 05:02:43 PM PDT 24
Peak memory 209664 kb
Host smart-365b73dd-fe33-47ec-999c-c7607c664d4c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570073724 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_csr_rw.3570073724
Directory /workspace/14.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.191280459
Short name T904
Test name
Test status
Simulation time 25418443 ps
CPU time 1.36 seconds
Started Jun 23 05:02:42 PM PDT 24
Finished Jun 23 05:02:44 PM PDT 24
Peak memory 217092 kb
Host smart-5fcc6689-56c6-4979-83da-a8a00e4cdb58
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191280459 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl
_same_csr_outstanding.191280459
Directory /workspace/14.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.2636181773
Short name T982
Test name
Test status
Simulation time 124510222 ps
CPU time 3.6 seconds
Started Jun 23 05:02:41 PM PDT 24
Finished Jun 23 05:02:45 PM PDT 24
Peak memory 217704 kb
Host smart-753c7d5e-ef71-4a54-939a-0b1bc145bc41
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636181773 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_errors.2636181773
Directory /workspace/14.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.1768705903
Short name T130
Test name
Test status
Simulation time 165471069 ps
CPU time 2.74 seconds
Started Jun 23 05:02:41 PM PDT 24
Finished Jun 23 05:02:45 PM PDT 24
Peak memory 222216 kb
Host smart-2214591b-1878-4b7e-a342-7d6c97df5f96
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768705903 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_intg
_err.1768705903
Directory /workspace/14.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.818118846
Short name T965
Test name
Test status
Simulation time 161548314 ps
CPU time 1.08 seconds
Started Jun 23 05:02:46 PM PDT 24
Finished Jun 23 05:02:48 PM PDT 24
Peak memory 218616 kb
Host smart-3585acae-e4f4-42fb-a875-cc1bb1bf5482
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818118846 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 15.lc_ctrl_csr_mem_rw_with_rand_reset.818118846
Directory /workspace/15.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.232224817
Short name T891
Test name
Test status
Simulation time 16738572 ps
CPU time 1.13 seconds
Started Jun 23 05:02:42 PM PDT 24
Finished Jun 23 05:02:44 PM PDT 24
Peak memory 217672 kb
Host smart-65a39760-a85d-4ddd-a0bb-214b6a451699
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232224817 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_csr_rw.232224817
Directory /workspace/15.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.3961062800
Short name T208
Test name
Test status
Simulation time 40919626 ps
CPU time 1.77 seconds
Started Jun 23 05:02:41 PM PDT 24
Finished Jun 23 05:02:44 PM PDT 24
Peak memory 211512 kb
Host smart-19252913-d8ac-4ccf-bee7-a77881e47845
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961062800 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctr
l_same_csr_outstanding.3961062800
Directory /workspace/15.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.1316740631
Short name T951
Test name
Test status
Simulation time 38465162 ps
CPU time 1.92 seconds
Started Jun 23 05:02:42 PM PDT 24
Finished Jun 23 05:02:45 PM PDT 24
Peak memory 217744 kb
Host smart-9949edac-691c-4b0b-b8f5-3e7b55c0f6a9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316740631 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_errors.1316740631
Directory /workspace/15.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.2145766277
Short name T902
Test name
Test status
Simulation time 22509853 ps
CPU time 1.49 seconds
Started Jun 23 05:02:46 PM PDT 24
Finished Jun 23 05:02:48 PM PDT 24
Peak memory 217820 kb
Host smart-e849dbe4-8c33-4c7f-a646-edbc6c6f4fa2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145766277 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 16.lc_ctrl_csr_mem_rw_with_rand_reset.2145766277
Directory /workspace/16.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.3029577627
Short name T119
Test name
Test status
Simulation time 43379881 ps
CPU time 0.98 seconds
Started Jun 23 05:02:46 PM PDT 24
Finished Jun 23 05:02:47 PM PDT 24
Peak memory 209132 kb
Host smart-a7a7328a-b6e2-4f23-bf0f-bc7a7ad4d6b3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029577627 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_csr_rw.3029577627
Directory /workspace/16.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.2482791560
Short name T898
Test name
Test status
Simulation time 203474375 ps
CPU time 1.22 seconds
Started Jun 23 05:02:46 PM PDT 24
Finished Jun 23 05:02:47 PM PDT 24
Peak memory 209444 kb
Host smart-e7c2f55c-69ac-44a7-8aa9-8e3f787f18db
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482791560 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctr
l_same_csr_outstanding.2482791560
Directory /workspace/16.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.273730182
Short name T936
Test name
Test status
Simulation time 38549719 ps
CPU time 2.47 seconds
Started Jun 23 05:02:45 PM PDT 24
Finished Jun 23 05:02:48 PM PDT 24
Peak memory 217644 kb
Host smart-dec9e745-2d75-4bea-8141-055433062b9f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273730182 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_errors.273730182
Directory /workspace/16.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.3735902359
Short name T135
Test name
Test status
Simulation time 269055769 ps
CPU time 2.17 seconds
Started Jun 23 05:02:47 PM PDT 24
Finished Jun 23 05:02:50 PM PDT 24
Peak memory 221448 kb
Host smart-7084403e-c55a-40c6-acde-469c007a10c9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735902359 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_intg
_err.3735902359
Directory /workspace/16.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.1435506270
Short name T166
Test name
Test status
Simulation time 51767880 ps
CPU time 1.14 seconds
Started Jun 23 05:02:46 PM PDT 24
Finished Jun 23 05:02:47 PM PDT 24
Peak memory 218072 kb
Host smart-600bd9be-9673-4dbe-aaea-5b7d21689c8a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435506270 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 17.lc_ctrl_csr_mem_rw_with_rand_reset.1435506270
Directory /workspace/17.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.3246827656
Short name T881
Test name
Test status
Simulation time 18297094 ps
CPU time 0.94 seconds
Started Jun 23 05:02:47 PM PDT 24
Finished Jun 23 05:02:48 PM PDT 24
Peak memory 209028 kb
Host smart-5cb21154-253a-43fe-85c2-504ed4f59ff6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246827656 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_csr_rw.3246827656
Directory /workspace/17.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.2529613093
Short name T912
Test name
Test status
Simulation time 20076463 ps
CPU time 1.39 seconds
Started Jun 23 05:02:49 PM PDT 24
Finished Jun 23 05:02:50 PM PDT 24
Peak memory 209364 kb
Host smart-4adb1c7a-50ad-4e54-98c0-83b0c8b49af9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529613093 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctr
l_same_csr_outstanding.2529613093
Directory /workspace/17.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.940525484
Short name T949
Test name
Test status
Simulation time 27969111 ps
CPU time 2.03 seconds
Started Jun 23 05:02:48 PM PDT 24
Finished Jun 23 05:02:50 PM PDT 24
Peak memory 217628 kb
Host smart-6594a426-8039-4918-b9da-ce03189de071
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940525484 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_errors.940525484
Directory /workspace/17.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.2730370208
Short name T913
Test name
Test status
Simulation time 85379257 ps
CPU time 1.93 seconds
Started Jun 23 05:02:47 PM PDT 24
Finished Jun 23 05:02:49 PM PDT 24
Peak memory 217912 kb
Host smart-30fc76fc-251e-40bd-b749-c05415165c7a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730370208 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 18.lc_ctrl_csr_mem_rw_with_rand_reset.2730370208
Directory /workspace/18.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.3792125003
Short name T205
Test name
Test status
Simulation time 54432486 ps
CPU time 0.96 seconds
Started Jun 23 05:02:50 PM PDT 24
Finished Jun 23 05:02:51 PM PDT 24
Peak memory 209392 kb
Host smart-436bef81-b050-4036-b740-8d151148faee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792125003 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_csr_rw.3792125003
Directory /workspace/18.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.4163944750
Short name T979
Test name
Test status
Simulation time 40780715 ps
CPU time 2.03 seconds
Started Jun 23 05:02:48 PM PDT 24
Finished Jun 23 05:02:50 PM PDT 24
Peak memory 217660 kb
Host smart-da8254c8-02fd-4994-a35e-bec1f62788c2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163944750 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctr
l_same_csr_outstanding.4163944750
Directory /workspace/18.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.3549678818
Short name T112
Test name
Test status
Simulation time 181423356 ps
CPU time 3.62 seconds
Started Jun 23 05:02:47 PM PDT 24
Finished Jun 23 05:02:51 PM PDT 24
Peak memory 218656 kb
Host smart-9fab47b5-d0b6-4a24-942f-8ff38ba9fb20
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549678818 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_errors.3549678818
Directory /workspace/18.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.2272257418
Short name T984
Test name
Test status
Simulation time 101029836 ps
CPU time 1.07 seconds
Started Jun 23 05:02:53 PM PDT 24
Finished Jun 23 05:02:54 PM PDT 24
Peak memory 217808 kb
Host smart-cd7edc6c-0777-44e3-85ea-2e901f02269e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272257418 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 19.lc_ctrl_csr_mem_rw_with_rand_reset.2272257418
Directory /workspace/19.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.476923225
Short name T204
Test name
Test status
Simulation time 83677951 ps
CPU time 0.88 seconds
Started Jun 23 05:02:54 PM PDT 24
Finished Jun 23 05:02:55 PM PDT 24
Peak memory 209468 kb
Host smart-c5d7dfff-a2c2-48ac-9b72-e3797763bc8a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476923225 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_csr_rw.476923225
Directory /workspace/19.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.3925488614
Short name T992
Test name
Test status
Simulation time 120684332 ps
CPU time 1.24 seconds
Started Jun 23 05:02:53 PM PDT 24
Finished Jun 23 05:02:55 PM PDT 24
Peak memory 209424 kb
Host smart-afe2ced2-b0c7-4bb2-87a8-b07a6c756eaf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925488614 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctr
l_same_csr_outstanding.3925488614
Directory /workspace/19.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.131555115
Short name T908
Test name
Test status
Simulation time 178260289 ps
CPU time 2.46 seconds
Started Jun 23 05:02:47 PM PDT 24
Finished Jun 23 05:02:49 PM PDT 24
Peak memory 217672 kb
Host smart-995e0c98-9c66-463e-81f0-2a1f864aea0c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131555115 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_errors.131555115
Directory /workspace/19.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.1928549229
Short name T196
Test name
Test status
Simulation time 31683660 ps
CPU time 1.21 seconds
Started Jun 23 05:02:23 PM PDT 24
Finished Jun 23 05:02:25 PM PDT 24
Peak memory 217616 kb
Host smart-fbf79f45-765a-42d2-bb1a-36adac731b93
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928549229 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_aliasin
g.1928549229
Directory /workspace/2.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.2770050373
Short name T886
Test name
Test status
Simulation time 50185840 ps
CPU time 1.63 seconds
Started Jun 23 05:02:22 PM PDT 24
Finished Jun 23 05:02:24 PM PDT 24
Peak memory 209356 kb
Host smart-d73312a7-ef59-4103-9970-aac0b256a3ae
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770050373 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_bit_bas
h.2770050373
Directory /workspace/2.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.727105193
Short name T203
Test name
Test status
Simulation time 76880059 ps
CPU time 1.02 seconds
Started Jun 23 05:02:19 PM PDT 24
Finished Jun 23 05:02:20 PM PDT 24
Peak memory 211476 kb
Host smart-300279dd-79cc-4e6d-bb93-23423ad98ea6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727105193 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_hw_reset
.727105193
Directory /workspace/2.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.1525290515
Short name T900
Test name
Test status
Simulation time 145947342 ps
CPU time 1.4 seconds
Started Jun 23 05:02:23 PM PDT 24
Finished Jun 23 05:02:25 PM PDT 24
Peak memory 219124 kb
Host smart-96d8efb7-7e4b-48e3-856b-87ec6fb20299
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525290515 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 2.lc_ctrl_csr_mem_rw_with_rand_reset.1525290515
Directory /workspace/2.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.179449865
Short name T958
Test name
Test status
Simulation time 16313375 ps
CPU time 1.1 seconds
Started Jun 23 05:02:22 PM PDT 24
Finished Jun 23 05:02:23 PM PDT 24
Peak memory 209384 kb
Host smart-a761d9b2-24f3-40e8-9fa4-ab9cf2bc5a0c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179449865 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_rw.179449865
Directory /workspace/2.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.1989173331
Short name T905
Test name
Test status
Simulation time 39692168 ps
CPU time 0.85 seconds
Started Jun 23 05:02:24 PM PDT 24
Finished Jun 23 05:02:25 PM PDT 24
Peak memory 209232 kb
Host smart-91fa1d57-83f8-400f-8901-633672e93c16
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989173331 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.lc_ctrl_jtag_alert_test.1989173331
Directory /workspace/2.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.1868284901
Short name T878
Test name
Test status
Simulation time 414847797 ps
CPU time 6.73 seconds
Started Jun 23 05:02:18 PM PDT 24
Finished Jun 23 05:02:25 PM PDT 24
Peak memory 209352 kb
Host smart-08181781-d9c1-4b8f-9968-a666b1364d5d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868284901 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_aliasing.1868284901
Directory /workspace/2.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.2464064882
Short name T981
Test name
Test status
Simulation time 1831179425 ps
CPU time 5.25 seconds
Started Jun 23 05:02:24 PM PDT 24
Finished Jun 23 05:02:29 PM PDT 24
Peak memory 209292 kb
Host smart-90c2f0ba-82b6-4ca8-84e5-5a253d73481c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464064882 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_bit_bash.2464064882
Directory /workspace/2.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.3247380413
Short name T121
Test name
Test status
Simulation time 139661977 ps
CPU time 1.49 seconds
Started Jun 23 05:02:17 PM PDT 24
Finished Jun 23 05:02:19 PM PDT 24
Peak memory 217520 kb
Host smart-ec752ba2-b893-4add-9896-b94d23516886
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247380413 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_hw_reset.3247380413
Directory /workspace/2.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1025771036
Short name T177
Test name
Test status
Simulation time 330961152 ps
CPU time 2.15 seconds
Started Jun 23 05:02:19 PM PDT 24
Finished Jun 23 05:02:21 PM PDT 24
Peak memory 218684 kb
Host smart-81102894-a206-4b96-aebb-456b592c0d8e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102577
1036 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1025771036
Directory /workspace/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.693702341
Short name T999
Test name
Test status
Simulation time 645449522 ps
CPU time 1.89 seconds
Started Jun 23 05:02:16 PM PDT 24
Finished Jun 23 05:02:18 PM PDT 24
Peak memory 209352 kb
Host smart-eb9b436c-c80b-4b89-8033-f7d39568b883
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693702341 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.lc_ctrl_jtag_csr_rw.693702341
Directory /workspace/2.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.1238368997
Short name T209
Test name
Test status
Simulation time 171624390 ps
CPU time 1.86 seconds
Started Jun 23 05:02:17 PM PDT 24
Finished Jun 23 05:02:20 PM PDT 24
Peak memory 211308 kb
Host smart-c1f1847f-bfd0-46a1-b3ac-80debe09bffb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238368997 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.lc_ctrl_jtag_same_csr_outstanding.1238368997
Directory /workspace/2.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.1885604312
Short name T977
Test name
Test status
Simulation time 21625057 ps
CPU time 1.61 seconds
Started Jun 23 05:02:21 PM PDT 24
Finished Jun 23 05:02:23 PM PDT 24
Peak memory 217872 kb
Host smart-99026ef9-87d3-4a10-879d-3601eeb60545
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885604312 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl
_same_csr_outstanding.1885604312
Directory /workspace/2.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.230106553
Short name T918
Test name
Test status
Simulation time 21690329 ps
CPU time 1.02 seconds
Started Jun 23 05:02:21 PM PDT 24
Finished Jun 23 05:02:22 PM PDT 24
Peak memory 209548 kb
Host smart-85d833ea-45ac-4e04-bad7-d1a67c612537
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230106553 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_aliasing
.230106553
Directory /workspace/3.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.136017683
Short name T931
Test name
Test status
Simulation time 18209478 ps
CPU time 1.16 seconds
Started Jun 23 05:02:23 PM PDT 24
Finished Jun 23 05:02:25 PM PDT 24
Peak memory 209236 kb
Host smart-fca4e9c2-4d06-43f8-867f-4719f9b4a97e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136017683 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_bit_bash
.136017683
Directory /workspace/3.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.2257423494
Short name T207
Test name
Test status
Simulation time 26868406 ps
CPU time 0.88 seconds
Started Jun 23 05:02:21 PM PDT 24
Finished Jun 23 05:02:22 PM PDT 24
Peak memory 209740 kb
Host smart-cb60e7f7-823d-4237-8884-4e8b067065bb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257423494 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_hw_rese
t.2257423494
Directory /workspace/3.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.263805858
Short name T944
Test name
Test status
Simulation time 23321272 ps
CPU time 1.41 seconds
Started Jun 23 05:02:21 PM PDT 24
Finished Jun 23 05:02:23 PM PDT 24
Peak memory 221760 kb
Host smart-71620065-d7c6-450e-80d1-812fcafe0857
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263805858 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 3.lc_ctrl_csr_mem_rw_with_rand_reset.263805858
Directory /workspace/3.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.2812553409
Short name T914
Test name
Test status
Simulation time 13070850 ps
CPU time 1 seconds
Started Jun 23 05:02:21 PM PDT 24
Finished Jun 23 05:02:23 PM PDT 24
Peak memory 209352 kb
Host smart-9c59dd1a-4ba9-42ae-9ca2-45e5fb8751e1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812553409 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_rw.2812553409
Directory /workspace/3.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.2606487214
Short name T990
Test name
Test status
Simulation time 215704369 ps
CPU time 1.04 seconds
Started Jun 23 05:02:21 PM PDT 24
Finished Jun 23 05:02:22 PM PDT 24
Peak memory 209252 kb
Host smart-df309449-5d92-4f05-8687-1b3b6ac5cac3
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606487214 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.lc_ctrl_jtag_alert_test.2606487214
Directory /workspace/3.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.3520438492
Short name T938
Test name
Test status
Simulation time 586326139 ps
CPU time 6.32 seconds
Started Jun 23 05:02:28 PM PDT 24
Finished Jun 23 05:02:34 PM PDT 24
Peak memory 217068 kb
Host smart-7147522f-cb17-4dfd-9576-90c3bfe34a3a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520438492 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_aliasing.3520438492
Directory /workspace/3.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.2425563822
Short name T885
Test name
Test status
Simulation time 694263518 ps
CPU time 8.14 seconds
Started Jun 23 05:02:28 PM PDT 24
Finished Jun 23 05:02:37 PM PDT 24
Peak memory 209060 kb
Host smart-8ccd3806-e088-43e8-aec9-21e4cd6f14af
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425563822 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_bit_bash.2425563822
Directory /workspace/3.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.2298511471
Short name T145
Test name
Test status
Simulation time 163498022 ps
CPU time 2.63 seconds
Started Jun 23 05:02:23 PM PDT 24
Finished Jun 23 05:02:26 PM PDT 24
Peak memory 211012 kb
Host smart-47d59b83-1427-4c2a-bbfb-36534b22d633
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298511471 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_hw_reset.2298511471
Directory /workspace/3.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3317333574
Short name T923
Test name
Test status
Simulation time 121208853 ps
CPU time 2.23 seconds
Started Jun 23 05:02:23 PM PDT 24
Finished Jun 23 05:02:26 PM PDT 24
Peak memory 218020 kb
Host smart-11d9689a-22a6-4234-bcc9-84cb422a8a58
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331733
3574 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3317333574
Directory /workspace/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.2185859101
Short name T963
Test name
Test status
Simulation time 963234836 ps
CPU time 1.26 seconds
Started Jun 23 05:02:19 PM PDT 24
Finished Jun 23 05:02:20 PM PDT 24
Peak memory 209148 kb
Host smart-786dbe31-c038-46d5-8390-30c4c134cfd3
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185859101 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.lc_ctrl_jtag_csr_rw.2185859101
Directory /workspace/3.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.125596411
Short name T970
Test name
Test status
Simulation time 45980321 ps
CPU time 1.95 seconds
Started Jun 23 05:02:23 PM PDT 24
Finished Jun 23 05:02:26 PM PDT 24
Peak memory 217656 kb
Host smart-98937619-e86c-4c8d-a6a4-05be912069a5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125596411 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.lc_ctrl_jtag_same_csr_outstanding.125596411
Directory /workspace/3.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.3636276809
Short name T211
Test name
Test status
Simulation time 189351711 ps
CPU time 1.99 seconds
Started Jun 23 05:02:20 PM PDT 24
Finished Jun 23 05:02:22 PM PDT 24
Peak memory 211548 kb
Host smart-f1c14a60-9baa-49ff-83ac-8ae1d9b4e24f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636276809 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl
_same_csr_outstanding.3636276809
Directory /workspace/3.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.260836671
Short name T921
Test name
Test status
Simulation time 80772964 ps
CPU time 3.09 seconds
Started Jun 23 05:02:20 PM PDT 24
Finished Jun 23 05:02:23 PM PDT 24
Peak memory 217708 kb
Host smart-8bae2bc6-db67-4f2f-b6c3-c4349003afee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260836671 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_errors.260836671
Directory /workspace/3.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.1881140981
Short name T976
Test name
Test status
Simulation time 83980539 ps
CPU time 1.28 seconds
Started Jun 23 05:02:26 PM PDT 24
Finished Jun 23 05:02:27 PM PDT 24
Peak memory 209468 kb
Host smart-ff40dfe5-7883-4b1d-aca3-89f0c898949b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881140981 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_aliasin
g.1881140981
Directory /workspace/4.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.1678175746
Short name T897
Test name
Test status
Simulation time 68260024 ps
CPU time 2.61 seconds
Started Jun 23 05:02:27 PM PDT 24
Finished Jun 23 05:02:30 PM PDT 24
Peak memory 209436 kb
Host smart-3946ddd2-004b-42e0-87ab-781056be9b38
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678175746 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_bit_bas
h.1678175746
Directory /workspace/4.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.1212850287
Short name T892
Test name
Test status
Simulation time 14747998 ps
CPU time 0.94 seconds
Started Jun 23 05:02:27 PM PDT 24
Finished Jun 23 05:02:28 PM PDT 24
Peak memory 209828 kb
Host smart-cb7ee76a-21f9-444b-b07a-484ee80d9d20
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212850287 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_hw_rese
t.1212850287
Directory /workspace/4.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.776859228
Short name T972
Test name
Test status
Simulation time 159726248 ps
CPU time 1.7 seconds
Started Jun 23 05:02:25 PM PDT 24
Finished Jun 23 05:02:27 PM PDT 24
Peak memory 217800 kb
Host smart-08f7af73-0139-4a2b-8ed4-30ced2ed83b6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776859228 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 4.lc_ctrl_csr_mem_rw_with_rand_reset.776859228
Directory /workspace/4.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.235882303
Short name T952
Test name
Test status
Simulation time 42024667 ps
CPU time 0.83 seconds
Started Jun 23 05:02:31 PM PDT 24
Finished Jun 23 05:02:32 PM PDT 24
Peak memory 208776 kb
Host smart-20f11a14-0a64-431b-96b1-766955fcffd9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235882303 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_rw.235882303
Directory /workspace/4.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.1399122899
Short name T896
Test name
Test status
Simulation time 50357357 ps
CPU time 1.9 seconds
Started Jun 23 05:02:28 PM PDT 24
Finished Jun 23 05:02:31 PM PDT 24
Peak memory 208804 kb
Host smart-427593de-1372-40e7-bdb1-8b6d4ed92637
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399122899 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.lc_ctrl_jtag_alert_test.1399122899
Directory /workspace/4.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.946060456
Short name T962
Test name
Test status
Simulation time 1164686006 ps
CPU time 12.98 seconds
Started Jun 23 05:02:23 PM PDT 24
Finished Jun 23 05:02:36 PM PDT 24
Peak memory 209152 kb
Host smart-3a0445c4-cb25-49f6-8818-4149bcdd684c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946060456 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 4.lc_ctrl_jtag_csr_aliasing.946060456
Directory /workspace/4.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.4112459945
Short name T928
Test name
Test status
Simulation time 3994263767 ps
CPU time 11.44 seconds
Started Jun 23 05:02:23 PM PDT 24
Finished Jun 23 05:02:35 PM PDT 24
Peak memory 209396 kb
Host smart-917a4070-b22d-4891-bf39-301ad78b4c62
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112459945 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_bit_bash.4112459945
Directory /workspace/4.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.2194208602
Short name T989
Test name
Test status
Simulation time 363796810 ps
CPU time 2.88 seconds
Started Jun 23 05:02:28 PM PDT 24
Finished Jun 23 05:02:32 PM PDT 24
Peak memory 217352 kb
Host smart-976cdeef-1de3-4136-8e0b-82fdfde4aeb8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194208602 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_hw_reset.2194208602
Directory /workspace/4.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.718196252
Short name T967
Test name
Test status
Simulation time 141058267 ps
CPU time 1.53 seconds
Started Jun 23 05:02:26 PM PDT 24
Finished Jun 23 05:02:28 PM PDT 24
Peak memory 219084 kb
Host smart-87694275-eae5-4fa8-a625-63b980e90a62
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718196
252 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.718196252
Directory /workspace/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.1475845819
Short name T937
Test name
Test status
Simulation time 181090520 ps
CPU time 1.75 seconds
Started Jun 23 05:02:28 PM PDT 24
Finished Jun 23 05:02:31 PM PDT 24
Peak memory 209188 kb
Host smart-328ef167-934a-4f23-b608-a30513f37dcd
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475845819 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.lc_ctrl_jtag_csr_rw.1475845819
Directory /workspace/4.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.4211101971
Short name T995
Test name
Test status
Simulation time 64496187 ps
CPU time 1.29 seconds
Started Jun 23 05:02:29 PM PDT 24
Finished Jun 23 05:02:30 PM PDT 24
Peak memory 217640 kb
Host smart-35922b69-02a3-4dc3-bde5-cc899dfea38c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211101971 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.lc_ctrl_jtag_same_csr_outstanding.4211101971
Directory /workspace/4.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.2375170125
Short name T997
Test name
Test status
Simulation time 59964759 ps
CPU time 1.27 seconds
Started Jun 23 05:02:27 PM PDT 24
Finished Jun 23 05:02:29 PM PDT 24
Peak memory 217668 kb
Host smart-3b2647e3-410f-4aef-8d77-b2dc58f15c1a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375170125 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl
_same_csr_outstanding.2375170125
Directory /workspace/4.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.48346631
Short name T971
Test name
Test status
Simulation time 88198464 ps
CPU time 2.87 seconds
Started Jun 23 05:02:26 PM PDT 24
Finished Jun 23 05:02:29 PM PDT 24
Peak memory 217840 kb
Host smart-31e30bca-6f33-476c-a353-d85f8060d467
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48346631 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_errors.48346631
Directory /workspace/4.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.916490913
Short name T140
Test name
Test status
Simulation time 254388805 ps
CPU time 2.23 seconds
Started Jun 23 05:02:26 PM PDT 24
Finished Jun 23 05:02:29 PM PDT 24
Peak memory 222000 kb
Host smart-9bf4dd2b-12ed-449d-8aef-ee33675e0f13
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916490913 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_intg_e
rr.916490913
Directory /workspace/4.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.3387025838
Short name T903
Test name
Test status
Simulation time 96228550 ps
CPU time 1.82 seconds
Started Jun 23 05:02:26 PM PDT 24
Finished Jun 23 05:02:28 PM PDT 24
Peak memory 217864 kb
Host smart-651270bb-152d-46ac-b80a-b06bd87c8dad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387025838 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 5.lc_ctrl_csr_mem_rw_with_rand_reset.3387025838
Directory /workspace/5.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.2669282599
Short name T202
Test name
Test status
Simulation time 14088735 ps
CPU time 0.83 seconds
Started Jun 23 05:02:26 PM PDT 24
Finished Jun 23 05:02:27 PM PDT 24
Peak memory 209196 kb
Host smart-274e12e2-fbe5-4058-a76c-d760e99c894f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669282599 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_csr_rw.2669282599
Directory /workspace/5.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.2674265614
Short name T956
Test name
Test status
Simulation time 102279042 ps
CPU time 1.2 seconds
Started Jun 23 05:02:29 PM PDT 24
Finished Jun 23 05:02:30 PM PDT 24
Peak memory 209284 kb
Host smart-590296b0-a458-4bd0-a3c2-505b0a2a30f0
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674265614 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.lc_ctrl_jtag_alert_test.2674265614
Directory /workspace/5.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.4181841546
Short name T974
Test name
Test status
Simulation time 690358070 ps
CPU time 8.41 seconds
Started Jun 23 05:02:28 PM PDT 24
Finished Jun 23 05:02:37 PM PDT 24
Peak memory 217144 kb
Host smart-ae1ca8fc-88df-42aa-b937-0b5937d09ebf
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181841546 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_aliasing.4181841546
Directory /workspace/5.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.4045331372
Short name T915
Test name
Test status
Simulation time 833485768 ps
CPU time 10.17 seconds
Started Jun 23 05:02:28 PM PDT 24
Finished Jun 23 05:02:38 PM PDT 24
Peak memory 209064 kb
Host smart-211303cf-4e73-48be-82a9-bf005e66f580
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045331372 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_bit_bash.4045331372
Directory /workspace/5.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.4154372571
Short name T899
Test name
Test status
Simulation time 47747131 ps
CPU time 1.18 seconds
Started Jun 23 05:02:28 PM PDT 24
Finished Jun 23 05:02:29 PM PDT 24
Peak memory 210784 kb
Host smart-12417c47-af7a-401c-b09d-20d54b916894
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154372571 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_hw_reset.4154372571
Directory /workspace/5.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.844815013
Short name T955
Test name
Test status
Simulation time 436432382 ps
CPU time 6.18 seconds
Started Jun 23 05:02:26 PM PDT 24
Finished Jun 23 05:02:33 PM PDT 24
Peak memory 218924 kb
Host smart-29d743c4-212b-4b6d-aa39-507855695364
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844815
013 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.844815013
Directory /workspace/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.2528545147
Short name T929
Test name
Test status
Simulation time 71283748 ps
CPU time 2.1 seconds
Started Jun 23 05:02:28 PM PDT 24
Finished Jun 23 05:02:31 PM PDT 24
Peak memory 209408 kb
Host smart-4c4cab4d-7142-4f8e-82ee-4d858c6a5064
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528545147 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.lc_ctrl_jtag_csr_rw.2528545147
Directory /workspace/5.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.2985799941
Short name T924
Test name
Test status
Simulation time 71347817 ps
CPU time 1.27 seconds
Started Jun 23 05:02:28 PM PDT 24
Finished Jun 23 05:02:30 PM PDT 24
Peak memory 209520 kb
Host smart-71b01641-4bcd-45c1-9bef-acda9154e603
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985799941 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.lc_ctrl_jtag_same_csr_outstanding.2985799941
Directory /workspace/5.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.1667390602
Short name T212
Test name
Test status
Simulation time 136021659 ps
CPU time 1.76 seconds
Started Jun 23 05:02:28 PM PDT 24
Finished Jun 23 05:02:30 PM PDT 24
Peak memory 217344 kb
Host smart-2a462372-1d67-4490-83d2-84610f1a688d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667390602 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl
_same_csr_outstanding.1667390602
Directory /workspace/5.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.570954488
Short name T114
Test name
Test status
Simulation time 213790941 ps
CPU time 2.58 seconds
Started Jun 23 05:02:26 PM PDT 24
Finished Jun 23 05:02:29 PM PDT 24
Peak memory 217728 kb
Host smart-a2a71017-5c29-4201-9675-6028531ac9fd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570954488 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_errors.570954488
Directory /workspace/5.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.4256858070
Short name T116
Test name
Test status
Simulation time 68729568 ps
CPU time 2.63 seconds
Started Jun 23 05:02:26 PM PDT 24
Finished Jun 23 05:02:29 PM PDT 24
Peak memory 217600 kb
Host smart-dbf12461-3755-40be-a3ef-b96b37446d60
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256858070 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_intg_
err.4256858070
Directory /workspace/5.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.1996336368
Short name T934
Test name
Test status
Simulation time 70791082 ps
CPU time 1.67 seconds
Started Jun 23 05:02:31 PM PDT 24
Finished Jun 23 05:02:33 PM PDT 24
Peak memory 218668 kb
Host smart-5cfea1e8-6330-4f37-aefd-2528bb9fc422
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996336368 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 6.lc_ctrl_csr_mem_rw_with_rand_reset.1996336368
Directory /workspace/6.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.2927959305
Short name T198
Test name
Test status
Simulation time 41940014 ps
CPU time 0.97 seconds
Started Jun 23 05:02:31 PM PDT 24
Finished Jun 23 05:02:33 PM PDT 24
Peak memory 209464 kb
Host smart-48f7fcdb-3235-4044-bae3-131a2135973b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927959305 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_csr_rw.2927959305
Directory /workspace/6.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.509238735
Short name T987
Test name
Test status
Simulation time 102138704 ps
CPU time 1.2 seconds
Started Jun 23 05:02:33 PM PDT 24
Finished Jun 23 05:02:35 PM PDT 24
Peak memory 209348 kb
Host smart-c2cf27c6-3699-434e-84ff-5dfe277e5d07
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509238735 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 6.lc_ctrl_jtag_alert_test.509238735
Directory /workspace/6.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.4200655390
Short name T959
Test name
Test status
Simulation time 1226236785 ps
CPU time 12.37 seconds
Started Jun 23 05:02:33 PM PDT 24
Finished Jun 23 05:02:45 PM PDT 24
Peak memory 217016 kb
Host smart-318db1eb-0c6f-4d30-bf00-50d5f19e8f96
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200655390 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_aliasing.4200655390
Directory /workspace/6.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.1158370523
Short name T917
Test name
Test status
Simulation time 703978983 ps
CPU time 4.47 seconds
Started Jun 23 05:02:25 PM PDT 24
Finished Jun 23 05:02:30 PM PDT 24
Peak memory 217056 kb
Host smart-1a0ef7a1-16f3-4fa5-950f-eeeef7aa6afb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158370523 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_bit_bash.1158370523
Directory /workspace/6.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.2423774244
Short name T1000
Test name
Test status
Simulation time 71892375 ps
CPU time 1.43 seconds
Started Jun 23 05:02:28 PM PDT 24
Finished Jun 23 05:02:30 PM PDT 24
Peak memory 210768 kb
Host smart-9b439868-f5a7-4743-b3bc-9900c1696346
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423774244 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_hw_reset.2423774244
Directory /workspace/6.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.180621713
Short name T926
Test name
Test status
Simulation time 133039042 ps
CPU time 2.81 seconds
Started Jun 23 05:02:31 PM PDT 24
Finished Jun 23 05:02:35 PM PDT 24
Peak memory 217628 kb
Host smart-a1e59007-cc75-4a86-b140-96ca658f2603
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180621
713 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.180621713
Directory /workspace/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.1908615203
Short name T890
Test name
Test status
Simulation time 128023047 ps
CPU time 1.5 seconds
Started Jun 23 05:02:28 PM PDT 24
Finished Jun 23 05:02:29 PM PDT 24
Peak memory 209204 kb
Host smart-5c5a2129-143a-4d76-a0cb-f6a94ad33904
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908615203 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.lc_ctrl_jtag_csr_rw.1908615203
Directory /workspace/6.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.430670633
Short name T895
Test name
Test status
Simulation time 60453515 ps
CPU time 1.18 seconds
Started Jun 23 05:02:30 PM PDT 24
Finished Jun 23 05:02:31 PM PDT 24
Peak memory 209516 kb
Host smart-7aa1f27d-a867-41cc-969b-925e4ada39c2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430670633 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.lc_ctrl_jtag_same_csr_outstanding.430670633
Directory /workspace/6.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.122524156
Short name T943
Test name
Test status
Simulation time 23984896 ps
CPU time 1.18 seconds
Started Jun 23 05:02:39 PM PDT 24
Finished Jun 23 05:02:40 PM PDT 24
Peak memory 209392 kb
Host smart-51e6fe77-d702-4bf2-9488-5a9361ca82f8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122524156 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
same_csr_outstanding.122524156
Directory /workspace/6.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.1342263271
Short name T922
Test name
Test status
Simulation time 210500977 ps
CPU time 3.99 seconds
Started Jun 23 05:02:32 PM PDT 24
Finished Jun 23 05:02:36 PM PDT 24
Peak memory 217816 kb
Host smart-c4b81b98-1576-4859-a93e-00095c818fe1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342263271 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_errors.1342263271
Directory /workspace/6.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.1192164386
Short name T142
Test name
Test status
Simulation time 41437107 ps
CPU time 2.27 seconds
Started Jun 23 05:02:31 PM PDT 24
Finished Jun 23 05:02:34 PM PDT 24
Peak memory 222100 kb
Host smart-be708034-57e7-4e17-9cbf-4f5e026d33bc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192164386 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_intg_
err.1192164386
Directory /workspace/6.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.364713877
Short name T950
Test name
Test status
Simulation time 99067720 ps
CPU time 1.55 seconds
Started Jun 23 05:02:34 PM PDT 24
Finished Jun 23 05:02:36 PM PDT 24
Peak memory 217916 kb
Host smart-e10dbbaf-1fdd-4792-bd8c-e59aaee9d10d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364713877 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 7.lc_ctrl_csr_mem_rw_with_rand_reset.364713877
Directory /workspace/7.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.492913587
Short name T960
Test name
Test status
Simulation time 22166789 ps
CPU time 0.85 seconds
Started Jun 23 05:02:31 PM PDT 24
Finished Jun 23 05:02:32 PM PDT 24
Peak memory 208824 kb
Host smart-7a94fb53-4962-4b10-a408-4bdea6c0ff78
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492913587 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_csr_rw.492913587
Directory /workspace/7.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.651162401
Short name T884
Test name
Test status
Simulation time 30053047 ps
CPU time 0.98 seconds
Started Jun 23 05:02:30 PM PDT 24
Finished Jun 23 05:02:32 PM PDT 24
Peak memory 209244 kb
Host smart-3fdd46d3-2413-4536-971b-830271112327
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651162401 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 7.lc_ctrl_jtag_alert_test.651162401
Directory /workspace/7.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.2008561021
Short name T887
Test name
Test status
Simulation time 1714778524 ps
CPU time 10.19 seconds
Started Jun 23 05:02:35 PM PDT 24
Finished Jun 23 05:02:45 PM PDT 24
Peak memory 209100 kb
Host smart-b6bac245-35a3-4c91-848a-10beb3d16328
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008561021 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_aliasing.2008561021
Directory /workspace/7.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.1485668471
Short name T968
Test name
Test status
Simulation time 13462873606 ps
CPU time 7.94 seconds
Started Jun 23 05:02:31 PM PDT 24
Finished Jun 23 05:02:39 PM PDT 24
Peak memory 209216 kb
Host smart-6faf1b8b-2b8d-4193-9fc8-96fb64822733
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485668471 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_bit_bash.1485668471
Directory /workspace/7.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.3523417780
Short name T957
Test name
Test status
Simulation time 85008453 ps
CPU time 2.58 seconds
Started Jun 23 05:02:32 PM PDT 24
Finished Jun 23 05:02:35 PM PDT 24
Peak memory 217532 kb
Host smart-86e1da27-999f-4e8b-a047-f82c2ff75699
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523417780 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_hw_reset.3523417780
Directory /workspace/7.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.432861140
Short name T991
Test name
Test status
Simulation time 90067017 ps
CPU time 3.64 seconds
Started Jun 23 05:02:32 PM PDT 24
Finished Jun 23 05:02:36 PM PDT 24
Peak memory 222984 kb
Host smart-df96be02-560a-4b2b-8e13-048839a24dff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432861
140 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.432861140
Directory /workspace/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.2068201181
Short name T883
Test name
Test status
Simulation time 44041524 ps
CPU time 1.15 seconds
Started Jun 23 05:02:33 PM PDT 24
Finished Jun 23 05:02:34 PM PDT 24
Peak memory 209468 kb
Host smart-2e7236b7-5e25-44b5-a700-40da1cf6d7d1
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068201181 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.lc_ctrl_jtag_csr_rw.2068201181
Directory /workspace/7.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.3980148963
Short name T143
Test name
Test status
Simulation time 48774888 ps
CPU time 1.38 seconds
Started Jun 23 05:02:30 PM PDT 24
Finished Jun 23 05:02:31 PM PDT 24
Peak memory 209456 kb
Host smart-47f2ed79-ca10-4b76-8306-914d0d95ea13
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980148963 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.lc_ctrl_jtag_same_csr_outstanding.3980148963
Directory /workspace/7.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.1095829190
Short name T948
Test name
Test status
Simulation time 71830378 ps
CPU time 1.32 seconds
Started Jun 23 05:02:33 PM PDT 24
Finished Jun 23 05:02:35 PM PDT 24
Peak memory 211300 kb
Host smart-4207515d-87f1-4871-835d-49cfac29f365
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095829190 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl
_same_csr_outstanding.1095829190
Directory /workspace/7.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.3717185806
Short name T996
Test name
Test status
Simulation time 44722322 ps
CPU time 2.12 seconds
Started Jun 23 05:02:32 PM PDT 24
Finished Jun 23 05:02:34 PM PDT 24
Peak memory 217672 kb
Host smart-7b0c2bd4-ed0f-4e37-9e61-996508d33dc0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717185806 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_errors.3717185806
Directory /workspace/7.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.986653678
Short name T129
Test name
Test status
Simulation time 482580751 ps
CPU time 2.95 seconds
Started Jun 23 05:02:35 PM PDT 24
Finished Jun 23 05:02:38 PM PDT 24
Peak memory 222324 kb
Host smart-a187dc97-5686-4da1-ba97-60f372c7bdf9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986653678 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_intg_e
rr.986653678
Directory /workspace/7.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.334483639
Short name T930
Test name
Test status
Simulation time 93221111 ps
CPU time 1.09 seconds
Started Jun 23 05:02:37 PM PDT 24
Finished Jun 23 05:02:39 PM PDT 24
Peak memory 217644 kb
Host smart-5df8f6ba-f38e-4a99-98c0-857bbf4071b4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334483639 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 8.lc_ctrl_csr_mem_rw_with_rand_reset.334483639
Directory /workspace/8.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.3903558072
Short name T910
Test name
Test status
Simulation time 45036629 ps
CPU time 0.92 seconds
Started Jun 23 05:02:40 PM PDT 24
Finished Jun 23 05:02:41 PM PDT 24
Peak memory 209240 kb
Host smart-d83572d1-459d-4b5d-90d7-0e973303f52c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903558072 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_csr_rw.3903558072
Directory /workspace/8.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.423093877
Short name T993
Test name
Test status
Simulation time 384755391 ps
CPU time 1.23 seconds
Started Jun 23 05:02:36 PM PDT 24
Finished Jun 23 05:02:38 PM PDT 24
Peak memory 209280 kb
Host smart-fa5fc492-b091-47c8-b574-d2d72b5f3ff1
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423093877 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 8.lc_ctrl_jtag_alert_test.423093877
Directory /workspace/8.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.3141779468
Short name T888
Test name
Test status
Simulation time 730555898 ps
CPU time 6.83 seconds
Started Jun 23 05:02:33 PM PDT 24
Finished Jun 23 05:02:41 PM PDT 24
Peak memory 208940 kb
Host smart-64e20000-6ced-46e9-a879-e425aee13873
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141779468 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_aliasing.3141779468
Directory /workspace/8.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.472500273
Short name T980
Test name
Test status
Simulation time 1470760947 ps
CPU time 9.58 seconds
Started Jun 23 05:02:30 PM PDT 24
Finished Jun 23 05:02:40 PM PDT 24
Peak memory 217168 kb
Host smart-c503d658-2c16-458c-b547-124cb049780a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472500273 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 8.lc_ctrl_jtag_csr_bit_bash.472500273
Directory /workspace/8.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.3604209501
Short name T932
Test name
Test status
Simulation time 193988684 ps
CPU time 1.92 seconds
Started Jun 23 05:02:33 PM PDT 24
Finished Jun 23 05:02:36 PM PDT 24
Peak memory 210536 kb
Host smart-1a963412-1b3d-4f7f-8f01-a43994885f27
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604209501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_hw_reset.3604209501
Directory /workspace/8.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2010303860
Short name T127
Test name
Test status
Simulation time 93300661 ps
CPU time 1.59 seconds
Started Jun 23 05:02:38 PM PDT 24
Finished Jun 23 05:02:40 PM PDT 24
Peak memory 218560 kb
Host smart-4689a3f0-17c5-4e79-b9d1-78a202ad7dcc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201030
3860 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2010303860
Directory /workspace/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.1822596453
Short name T880
Test name
Test status
Simulation time 82882915 ps
CPU time 1.04 seconds
Started Jun 23 05:02:32 PM PDT 24
Finished Jun 23 05:02:34 PM PDT 24
Peak memory 209332 kb
Host smart-3ecdb392-7fc5-424f-8f6e-655cf66abe58
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822596453 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.lc_ctrl_jtag_csr_rw.1822596453
Directory /workspace/8.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.3601902148
Short name T978
Test name
Test status
Simulation time 22249651 ps
CPU time 1.31 seconds
Started Jun 23 05:02:38 PM PDT 24
Finished Jun 23 05:02:39 PM PDT 24
Peak memory 217644 kb
Host smart-69e44d3a-0a8b-4d2b-a007-1ac7a2aadbf4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601902148 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.lc_ctrl_jtag_same_csr_outstanding.3601902148
Directory /workspace/8.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.2595353100
Short name T920
Test name
Test status
Simulation time 169983905 ps
CPU time 1.61 seconds
Started Jun 23 05:02:38 PM PDT 24
Finished Jun 23 05:02:40 PM PDT 24
Peak memory 217672 kb
Host smart-d8eea135-b846-4a26-a5c4-8c2f70fc64ca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595353100 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl
_same_csr_outstanding.2595353100
Directory /workspace/8.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.2697071395
Short name T128
Test name
Test status
Simulation time 106118065 ps
CPU time 3.16 seconds
Started Jun 23 05:02:39 PM PDT 24
Finished Jun 23 05:02:43 PM PDT 24
Peak memory 217672 kb
Host smart-3a2943e9-d230-4164-93b3-060a010ccb49
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697071395 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_errors.2697071395
Directory /workspace/8.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.3612225662
Short name T118
Test name
Test status
Simulation time 117387015 ps
CPU time 2.65 seconds
Started Jun 23 05:02:37 PM PDT 24
Finished Jun 23 05:02:40 PM PDT 24
Peak memory 217688 kb
Host smart-1209d0aa-0ff3-4686-8c33-98c3aa888119
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612225662 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_intg_
err.3612225662
Directory /workspace/8.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.1459920845
Short name T945
Test name
Test status
Simulation time 94583077 ps
CPU time 1.3 seconds
Started Jun 23 05:02:37 PM PDT 24
Finished Jun 23 05:02:39 PM PDT 24
Peak memory 217804 kb
Host smart-2117a36c-61d6-4643-a937-fc36d1fc02cc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459920845 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 9.lc_ctrl_csr_mem_rw_with_rand_reset.1459920845
Directory /workspace/9.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.945054733
Short name T206
Test name
Test status
Simulation time 16950196 ps
CPU time 1.06 seconds
Started Jun 23 05:02:36 PM PDT 24
Finished Jun 23 05:02:37 PM PDT 24
Peak memory 209144 kb
Host smart-22cf8fc1-ed56-4d89-a874-45a8cf397a63
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945054733 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_csr_rw.945054733
Directory /workspace/9.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.2828734268
Short name T941
Test name
Test status
Simulation time 79274010 ps
CPU time 1.14 seconds
Started Jun 23 05:02:37 PM PDT 24
Finished Jun 23 05:02:39 PM PDT 24
Peak memory 208892 kb
Host smart-adb2eb12-6458-40da-85ef-99277f4f202d
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828734268 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.lc_ctrl_jtag_alert_test.2828734268
Directory /workspace/9.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.2734895356
Short name T879
Test name
Test status
Simulation time 713512360 ps
CPU time 4.74 seconds
Started Jun 23 05:02:37 PM PDT 24
Finished Jun 23 05:02:42 PM PDT 24
Peak memory 209156 kb
Host smart-f3e583d6-0ab3-4f2c-b51c-c177c474140f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734895356 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_aliasing.2734895356
Directory /workspace/9.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.4044003765
Short name T146
Test name
Test status
Simulation time 904356867 ps
CPU time 19.6 seconds
Started Jun 23 05:02:39 PM PDT 24
Finished Jun 23 05:02:59 PM PDT 24
Peak memory 208944 kb
Host smart-c410ccee-832d-4ac7-ab9c-de3a5b51ea16
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044003765 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_bit_bash.4044003765
Directory /workspace/9.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.2691015327
Short name T939
Test name
Test status
Simulation time 94323569 ps
CPU time 1.7 seconds
Started Jun 23 05:02:36 PM PDT 24
Finished Jun 23 05:02:38 PM PDT 24
Peak memory 210932 kb
Host smart-2cea8c7a-87e3-4064-9d37-d78168f142be
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691015327 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_hw_reset.2691015327
Directory /workspace/9.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1745169060
Short name T947
Test name
Test status
Simulation time 88025819 ps
CPU time 1.67 seconds
Started Jun 23 05:02:36 PM PDT 24
Finished Jun 23 05:02:38 PM PDT 24
Peak memory 218676 kb
Host smart-feb1a8a8-062b-4c19-8095-5d99e7cdf48f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174516
9060 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1745169060
Directory /workspace/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.989226469
Short name T120
Test name
Test status
Simulation time 878459285 ps
CPU time 1.94 seconds
Started Jun 23 05:02:38 PM PDT 24
Finished Jun 23 05:02:41 PM PDT 24
Peak memory 209176 kb
Host smart-997b3f26-bb48-4c37-a702-c12b844d4325
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989226469 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.lc_ctrl_jtag_csr_rw.989226469
Directory /workspace/9.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.883526498
Short name T916
Test name
Test status
Simulation time 177546563 ps
CPU time 1.48 seconds
Started Jun 23 05:02:36 PM PDT 24
Finished Jun 23 05:02:38 PM PDT 24
Peak memory 217648 kb
Host smart-92417189-f77b-45fb-a39e-e2e3a7b745a3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883526498 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.lc_ctrl_jtag_same_csr_outstanding.883526498
Directory /workspace/9.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.1194910059
Short name T210
Test name
Test status
Simulation time 25118137 ps
CPU time 1.15 seconds
Started Jun 23 05:02:40 PM PDT 24
Finished Jun 23 05:02:41 PM PDT 24
Peak memory 209400 kb
Host smart-d246b46e-3bc1-4a6c-b92b-92f0a6ecdcc6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194910059 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl
_same_csr_outstanding.1194910059
Directory /workspace/9.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.245559882
Short name T901
Test name
Test status
Simulation time 220624989 ps
CPU time 1.83 seconds
Started Jun 23 05:02:35 PM PDT 24
Finished Jun 23 05:02:37 PM PDT 24
Peak memory 217732 kb
Host smart-997bfd75-d45d-481e-9fa4-005eba3a8e75
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245559882 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_errors.245559882
Directory /workspace/9.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_alert_test.1917290768
Short name T403
Test name
Test status
Simulation time 31617476 ps
CPU time 0.81 seconds
Started Jun 23 05:06:12 PM PDT 24
Finished Jun 23 05:06:13 PM PDT 24
Peak memory 208948 kb
Host smart-0b015647-4969-486b-aee2-6f5ff35b1a8d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917290768 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_alert_test.1917290768
Directory /workspace/0.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.lc_ctrl_errors.2042483555
Short name T379
Test name
Test status
Simulation time 1105001226 ps
CPU time 16.59 seconds
Started Jun 23 05:06:07 PM PDT 24
Finished Jun 23 05:06:24 PM PDT 24
Peak memory 218136 kb
Host smart-ecc451e0-7d07-40f7-a071-8a5028ee0a6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042483555 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_errors.2042483555
Directory /workspace/0.lc_ctrl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_errors.2887257893
Short name T837
Test name
Test status
Simulation time 16942242115 ps
CPU time 23.44 seconds
Started Jun 23 05:06:08 PM PDT 24
Finished Jun 23 05:06:32 PM PDT 24
Peak memory 218820 kb
Host smart-9d80be5a-1d15-435d-86c6-9a6fa4829840
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887257893 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_er
rors.2887257893
Directory /workspace/0.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_priority.1508950456
Short name T190
Test name
Test status
Simulation time 980471911 ps
CPU time 3.4 seconds
Started Jun 23 05:06:08 PM PDT 24
Finished Jun 23 05:06:12 PM PDT 24
Peak memory 217588 kb
Host smart-cf4c5101-0c12-4f37-9696-091814f44f40
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508950456 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_priority.1
508950456
Directory /workspace/0.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_prog_failure.17172402
Short name T159
Test name
Test status
Simulation time 301917355 ps
CPU time 9.43 seconds
Started Jun 23 05:06:09 PM PDT 24
Finished Jun 23 05:06:19 PM PDT 24
Peak memory 218188 kb
Host smart-e675a8f8-80cd-4d04-9bb5-7ccc9670e6cd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17172402 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_p
rog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_p
rog_failure.17172402
Directory /workspace/0.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_regwen_during_op.200327184
Short name T300
Test name
Test status
Simulation time 760853398 ps
CPU time 24.16 seconds
Started Jun 23 05:06:09 PM PDT 24
Finished Jun 23 05:06:33 PM PDT 24
Peak memory 217692 kb
Host smart-b6c63d6a-7fee-41a6-9b2a-dfdb1c79f11f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200327184 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_j
tag_regwen_during_op.200327184
Directory /workspace/0.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_smoke.2938171115
Short name T811
Test name
Test status
Simulation time 1757892188 ps
CPU time 7.51 seconds
Started Jun 23 05:06:09 PM PDT 24
Finished Jun 23 05:06:17 PM PDT 24
Peak memory 217692 kb
Host smart-25572a03-1eb8-4181-9d1d-275d665ad6e6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938171115 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_smoke.
2938171115
Directory /workspace/0.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_post_trans.272171251
Short name T488
Test name
Test status
Simulation time 684103372 ps
CPU time 24.92 seconds
Started Jun 23 05:06:07 PM PDT 24
Finished Jun 23 05:06:33 PM PDT 24
Peak memory 250816 kb
Host smart-34efadce-49f4-439a-bc4b-c5373821e30b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272171251 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_j
tag_state_post_trans.272171251
Directory /workspace/0.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_prog_failure.1833185596
Short name T801
Test name
Test status
Simulation time 178668958 ps
CPU time 2.52 seconds
Started Jun 23 05:06:04 PM PDT 24
Finished Jun 23 05:06:07 PM PDT 24
Peak memory 222288 kb
Host smart-b8baa7d1-f99e-4627-a623-3e51094edf00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833185596 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_prog_failure.1833185596
Directory /workspace/0.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_regwen_during_op.2068574907
Short name T749
Test name
Test status
Simulation time 494626993 ps
CPU time 6.45 seconds
Started Jun 23 05:06:08 PM PDT 24
Finished Jun 23 05:06:15 PM PDT 24
Peak memory 214596 kb
Host smart-1b6f10e5-8f37-4373-8af5-1b422f36e41b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068574907 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_regwen_during_op.2068574907
Directory /workspace/0.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_cm.2554360395
Short name T98
Test name
Test status
Simulation time 222003016 ps
CPU time 34.67 seconds
Started Jun 23 05:06:13 PM PDT 24
Finished Jun 23 05:06:48 PM PDT 24
Peak memory 269376 kb
Host smart-37fd689a-c795-4f95-8747-f90e2948d46d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554360395 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_cm.2554360395
Directory /workspace/0.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_mubi.1507047798
Short name T486
Test name
Test status
Simulation time 692037245 ps
CPU time 17.68 seconds
Started Jun 23 05:06:08 PM PDT 24
Finished Jun 23 05:06:27 PM PDT 24
Peak memory 218940 kb
Host smart-93570965-f6e4-4e0a-a872-8c2b04461a2f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507047798 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_mubi.1507047798
Directory /workspace/0.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_digest.368530358
Short name T633
Test name
Test status
Simulation time 721178022 ps
CPU time 9.97 seconds
Started Jun 23 05:06:07 PM PDT 24
Finished Jun 23 05:06:17 PM PDT 24
Peak memory 225972 kb
Host smart-62e8cfec-75c2-4aab-93bf-fb221cd81edf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368530358 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_dig
est.368530358
Directory /workspace/0.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_mux.374635844
Short name T769
Test name
Test status
Simulation time 256316729 ps
CPU time 6.88 seconds
Started Jun 23 05:06:09 PM PDT 24
Finished Jun 23 05:06:16 PM PDT 24
Peak memory 226072 kb
Host smart-9c6a4269-a6c2-4e20-aa4e-696955681df6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374635844 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_mux.374635844
Directory /workspace/0.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/0.lc_ctrl_smoke.2516512291
Short name T835
Test name
Test status
Simulation time 61042600 ps
CPU time 2.49 seconds
Started Jun 23 05:06:11 PM PDT 24
Finished Jun 23 05:06:14 PM PDT 24
Peak memory 214504 kb
Host smart-049f6d1a-17af-4dd8-a0be-dfc9da3e0bde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516512291 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_smoke.2516512291
Directory /workspace/0.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_failure.636740339
Short name T775
Test name
Test status
Simulation time 349187369 ps
CPU time 17.26 seconds
Started Jun 23 05:06:06 PM PDT 24
Finished Jun 23 05:06:23 PM PDT 24
Peak memory 250804 kb
Host smart-019236dd-20f5-4268-85c6-d7d123965b2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636740339 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_failure.636740339
Directory /workspace/0.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_post_trans.2091056632
Short name T465
Test name
Test status
Simulation time 412036413 ps
CPU time 8.63 seconds
Started Jun 23 05:06:10 PM PDT 24
Finished Jun 23 05:06:19 PM PDT 24
Peak memory 250400 kb
Host smart-28ec086e-20ef-4a71-a3af-0d581b6e67b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091056632 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_post_trans.2091056632
Directory /workspace/0.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all.1830103667
Short name T538
Test name
Test status
Simulation time 2427511101 ps
CPU time 44.46 seconds
Started Jun 23 05:06:12 PM PDT 24
Finished Jun 23 05:06:57 PM PDT 24
Peak memory 250928 kb
Host smart-a8997e03-6765-4503-9b3f-82dc1ab04f83
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830103667 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.lc_ctrl_stress_all.1830103667
Directory /workspace/0.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.lc_ctrl_volatile_unlock_smoke.71179226
Short name T692
Test name
Test status
Simulation time 16329134 ps
CPU time 1.04 seconds
Started Jun 23 05:06:05 PM PDT 24
Finished Jun 23 05:06:07 PM PDT 24
Peak memory 213028 kb
Host smart-2666befd-9938-44a0-a7d2-c71617c7439f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71179226 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vol
atile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl
_volatile_unlock_smoke.71179226
Directory /workspace/0.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_alert_test.3804723568
Short name T311
Test name
Test status
Simulation time 13093810 ps
CPU time 1.03 seconds
Started Jun 23 05:06:12 PM PDT 24
Finished Jun 23 05:06:14 PM PDT 24
Peak memory 208576 kb
Host smart-a55b7fde-4e92-4099-8b62-1c4bdb3dd3f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804723568 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_alert_test.3804723568
Directory /workspace/1.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.lc_ctrl_claim_transition_if.3291813682
Short name T296
Test name
Test status
Simulation time 31420132 ps
CPU time 0.9 seconds
Started Jun 23 05:06:13 PM PDT 24
Finished Jun 23 05:06:15 PM PDT 24
Peak memory 209036 kb
Host smart-0659af56-e920-4053-8405-ab28bee0c40d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291813682 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_claim_transition_if.3291813682
Directory /workspace/1.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/1.lc_ctrl_errors.254568886
Short name T330
Test name
Test status
Simulation time 647840100 ps
CPU time 14.32 seconds
Started Jun 23 05:06:12 PM PDT 24
Finished Jun 23 05:06:27 PM PDT 24
Peak memory 218184 kb
Host smart-f96a1383-a8ae-434f-b771-64aa8c40af0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254568886 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_errors.254568886
Directory /workspace/1.lc_ctrl_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_access.3316643440
Short name T710
Test name
Test status
Simulation time 6357192237 ps
CPU time 8.31 seconds
Started Jun 23 05:06:14 PM PDT 24
Finished Jun 23 05:06:23 PM PDT 24
Peak memory 217776 kb
Host smart-471acf53-86a6-4f10-bfad-43970533315b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316643440 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_access.3316643440
Directory /workspace/1.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_errors.1761960988
Short name T855
Test name
Test status
Simulation time 1794809079 ps
CPU time 47.53 seconds
Started Jun 23 05:06:17 PM PDT 24
Finished Jun 23 05:07:05 PM PDT 24
Peak memory 218164 kb
Host smart-333898fc-6b4e-4de4-b736-faeae6264672
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761960988 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_er
rors.1761960988
Directory /workspace/1.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_priority.1675382896
Short name T413
Test name
Test status
Simulation time 3952923344 ps
CPU time 6.02 seconds
Started Jun 23 05:06:14 PM PDT 24
Finished Jun 23 05:06:20 PM PDT 24
Peak memory 217856 kb
Host smart-9df39c44-d243-4333-8bf7-973372ceecae
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675382896 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_priority.1
675382896
Directory /workspace/1.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_prog_failure.2299008911
Short name T723
Test name
Test status
Simulation time 465036087 ps
CPU time 13.2 seconds
Started Jun 23 05:06:13 PM PDT 24
Finished Jun 23 05:06:27 PM PDT 24
Peak memory 218068 kb
Host smart-01162d30-0cff-407a-93a0-da39b597eddb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299008911 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag
_prog_failure.2299008911
Directory /workspace/1.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_regwen_during_op.4116424942
Short name T61
Test name
Test status
Simulation time 2685207117 ps
CPU time 23.16 seconds
Started Jun 23 05:06:12 PM PDT 24
Finished Jun 23 05:06:36 PM PDT 24
Peak memory 217640 kb
Host smart-ded39086-b4cb-4508-9409-8fb6d0a56057
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116424942 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_regwen_during_op.4116424942
Directory /workspace/1.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_smoke.3994168347
Short name T373
Test name
Test status
Simulation time 1450961067 ps
CPU time 10.34 seconds
Started Jun 23 05:06:09 PM PDT 24
Finished Jun 23 05:06:20 PM PDT 24
Peak memory 217592 kb
Host smart-bb47fa9c-93ad-4b87-9ed8-9c1e3bbc645f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994168347 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_smoke.
3994168347
Directory /workspace/1.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_failure.668875421
Short name T381
Test name
Test status
Simulation time 3830237661 ps
CPU time 67.1 seconds
Started Jun 23 05:06:12 PM PDT 24
Finished Jun 23 05:07:20 PM PDT 24
Peak memory 283484 kb
Host smart-5d764c69-cc89-48d2-b6ac-5de2ba5bbfdd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668875421 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag
_state_failure.668875421
Directory /workspace/1.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_prog_failure.4133477078
Short name T467
Test name
Test status
Simulation time 64785230 ps
CPU time 3.03 seconds
Started Jun 23 05:06:10 PM PDT 24
Finished Jun 23 05:06:14 PM PDT 24
Peak memory 218108 kb
Host smart-2aa0ef3d-c7d8-45c1-a866-3f88b919443a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133477078 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_prog_failure.4133477078
Directory /workspace/1.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_regwen_during_op.3776755655
Short name T193
Test name
Test status
Simulation time 1512753422 ps
CPU time 14.32 seconds
Started Jun 23 05:06:12 PM PDT 24
Finished Jun 23 05:06:27 PM PDT 24
Peak memory 217760 kb
Host smart-5b8783d6-e887-423c-ba15-b115efc837e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776755655 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_regwen_during_op.3776755655
Directory /workspace/1.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_cm.3733215442
Short name T86
Test name
Test status
Simulation time 229864221 ps
CPU time 50.05 seconds
Started Jun 23 05:06:12 PM PDT 24
Finished Jun 23 05:07:03 PM PDT 24
Peak memory 405172 kb
Host smart-cf698feb-abb2-4a06-bb4e-29a283107dc5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733215442 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_cm.3733215442
Directory /workspace/1.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_mubi.1624958145
Short name T418
Test name
Test status
Simulation time 1543809801 ps
CPU time 14.99 seconds
Started Jun 23 05:06:11 PM PDT 24
Finished Jun 23 05:06:27 PM PDT 24
Peak memory 218240 kb
Host smart-0ae13146-e0d2-4c10-82c9-0b7addc22892
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624958145 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_mubi.1624958145
Directory /workspace/1.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_digest.2510935994
Short name T783
Test name
Test status
Simulation time 903948489 ps
CPU time 14.04 seconds
Started Jun 23 05:06:17 PM PDT 24
Finished Jun 23 05:06:32 PM PDT 24
Peak memory 218232 kb
Host smart-fdb260be-c779-44c9-830c-01cb942dad33
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510935994 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_di
gest.2510935994
Directory /workspace/1.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_mux.2530151065
Short name T814
Test name
Test status
Simulation time 1405733133 ps
CPU time 8.93 seconds
Started Jun 23 05:06:17 PM PDT 24
Finished Jun 23 05:06:27 PM PDT 24
Peak memory 218224 kb
Host smart-d6c4a31f-37d5-4133-8502-24a7d3dd0303
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530151065 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_mux.2
530151065
Directory /workspace/1.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/1.lc_ctrl_security_escalation.467042453
Short name T621
Test name
Test status
Simulation time 268609071 ps
CPU time 8.98 seconds
Started Jun 23 05:06:17 PM PDT 24
Finished Jun 23 05:06:27 PM PDT 24
Peak memory 225136 kb
Host smart-005192ae-c65a-43d4-8dab-d945a5eed9b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467042453 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_security_escalation.467042453
Directory /workspace/1.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/1.lc_ctrl_smoke.2440482504
Short name T843
Test name
Test status
Simulation time 55387741 ps
CPU time 0.99 seconds
Started Jun 23 05:06:10 PM PDT 24
Finished Jun 23 05:06:12 PM PDT 24
Peak memory 212244 kb
Host smart-acd509c6-8e44-44f1-b942-fc54275e0c1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440482504 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_smoke.2440482504
Directory /workspace/1.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_failure.1498857474
Short name T362
Test name
Test status
Simulation time 1623431768 ps
CPU time 28.26 seconds
Started Jun 23 05:06:13 PM PDT 24
Finished Jun 23 05:06:42 PM PDT 24
Peak memory 250876 kb
Host smart-e6cb8cd4-6770-4033-b2de-5ca13d7bc18f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498857474 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_failure.1498857474
Directory /workspace/1.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_post_trans.1973529903
Short name T740
Test name
Test status
Simulation time 248168053 ps
CPU time 7.17 seconds
Started Jun 23 05:06:12 PM PDT 24
Finished Jun 23 05:06:19 PM PDT 24
Peak memory 250900 kb
Host smart-c5969194-6d14-4d57-a354-eb15151ec12a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973529903 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_post_trans.1973529903
Directory /workspace/1.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_volatile_unlock_smoke.4217534350
Short name T476
Test name
Test status
Simulation time 38744567 ps
CPU time 0.88 seconds
Started Jun 23 05:06:17 PM PDT 24
Finished Jun 23 05:06:19 PM PDT 24
Peak memory 208952 kb
Host smart-87948c9b-df00-493a-9e41-5cee59bf7c22
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217534350 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ct
rl_volatile_unlock_smoke.4217534350
Directory /workspace/1.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_alert_test.2133522527
Short name T461
Test name
Test status
Simulation time 20565704 ps
CPU time 0.83 seconds
Started Jun 23 05:06:44 PM PDT 24
Finished Jun 23 05:06:46 PM PDT 24
Peak memory 208780 kb
Host smart-8e184dc9-15a5-48eb-be5a-fd153a9b02a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133522527 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_alert_test.2133522527
Directory /workspace/10.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.lc_ctrl_errors.2283695492
Short name T356
Test name
Test status
Simulation time 272747674 ps
CPU time 12.66 seconds
Started Jun 23 05:06:43 PM PDT 24
Finished Jun 23 05:06:56 PM PDT 24
Peak memory 218232 kb
Host smart-3bd37091-67a8-41cc-976e-9a10a3474fa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283695492 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_errors.2283695492
Directory /workspace/10.lc_ctrl_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_access.569445589
Short name T480
Test name
Test status
Simulation time 393880832 ps
CPU time 5.33 seconds
Started Jun 23 05:06:43 PM PDT 24
Finished Jun 23 05:06:49 PM PDT 24
Peak memory 217008 kb
Host smart-98b21b28-7be7-44bf-9abf-cb8ef1167fbb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569445589 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_access.569445589
Directory /workspace/10.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_errors.2267397965
Short name T752
Test name
Test status
Simulation time 4820557318 ps
CPU time 22.5 seconds
Started Jun 23 05:06:42 PM PDT 24
Finished Jun 23 05:07:05 PM PDT 24
Peak memory 218892 kb
Host smart-7f8691ec-d30d-428a-8a8c-6326b97479f0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267397965 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_e
rrors.2267397965
Directory /workspace/10.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_prog_failure.1379225671
Short name T641
Test name
Test status
Simulation time 869236196 ps
CPU time 8.14 seconds
Started Jun 23 05:06:42 PM PDT 24
Finished Jun 23 05:06:52 PM PDT 24
Peak memory 218224 kb
Host smart-ac39d881-aa20-4fe1-bc36-2853037c7394
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379225671 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jta
g_prog_failure.1379225671
Directory /workspace/10.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_smoke.2018036234
Short name T335
Test name
Test status
Simulation time 189814206 ps
CPU time 3.47 seconds
Started Jun 23 05:06:43 PM PDT 24
Finished Jun 23 05:06:48 PM PDT 24
Peak memory 217592 kb
Host smart-3e1b6c65-bfb0-44a7-a279-13c57ce6c57d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018036234 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_smoke
.2018036234
Directory /workspace/10.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_failure.600250031
Short name T763
Test name
Test status
Simulation time 3192438843 ps
CPU time 62.64 seconds
Started Jun 23 05:06:42 PM PDT 24
Finished Jun 23 05:07:45 PM PDT 24
Peak memory 267152 kb
Host smart-eb095bba-64ca-4e0f-8e9b-9ed8b099f38e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600250031 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jta
g_state_failure.600250031
Directory /workspace/10.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_post_trans.3154576404
Short name T475
Test name
Test status
Simulation time 733208289 ps
CPU time 16.8 seconds
Started Jun 23 05:06:42 PM PDT 24
Finished Jun 23 05:07:00 PM PDT 24
Peak memory 250744 kb
Host smart-1f4e754d-ea17-4c23-a4d0-b965521f115d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154576404 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl
_jtag_state_post_trans.3154576404
Directory /workspace/10.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_prog_failure.297983300
Short name T366
Test name
Test status
Simulation time 58943951 ps
CPU time 3.2 seconds
Started Jun 23 05:06:42 PM PDT 24
Finished Jun 23 05:06:47 PM PDT 24
Peak memory 222320 kb
Host smart-e88e45b2-a457-49bf-b3cd-871cb6e0a9e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=297983300 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_prog_failure.297983300
Directory /workspace/10.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_mubi.366797951
Short name T393
Test name
Test status
Simulation time 510445620 ps
CPU time 20.01 seconds
Started Jun 23 05:06:43 PM PDT 24
Finished Jun 23 05:07:05 PM PDT 24
Peak memory 218864 kb
Host smart-539884a8-3a16-45c0-a476-84a944b0f8bb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366797951 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_mubi.366797951
Directory /workspace/10.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_digest.1963980202
Short name T104
Test name
Test status
Simulation time 491820876 ps
CPU time 10.54 seconds
Started Jun 23 05:06:44 PM PDT 24
Finished Jun 23 05:06:56 PM PDT 24
Peak memory 218268 kb
Host smart-ceb03c7c-49dc-4dd3-ab82-304f5b1a2d13
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963980202 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_d
igest.1963980202
Directory /workspace/10.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_mux.3981882722
Short name T312
Test name
Test status
Simulation time 331059029 ps
CPU time 8.84 seconds
Started Jun 23 05:06:46 PM PDT 24
Finished Jun 23 05:06:56 PM PDT 24
Peak memory 218088 kb
Host smart-8aa9a6cf-79f4-4817-9ce8-51d3545000ab
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981882722 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_mux.
3981882722
Directory /workspace/10.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/10.lc_ctrl_security_escalation.2146655231
Short name T656
Test name
Test status
Simulation time 413363286 ps
CPU time 12.15 seconds
Started Jun 23 05:06:42 PM PDT 24
Finished Jun 23 05:06:54 PM PDT 24
Peak memory 226060 kb
Host smart-ff1daf14-8554-4903-b38b-e0baa8312d7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146655231 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_security_escalation.2146655231
Directory /workspace/10.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/10.lc_ctrl_smoke.1818901416
Short name T63
Test name
Test status
Simulation time 199156231 ps
CPU time 2.8 seconds
Started Jun 23 05:06:41 PM PDT 24
Finished Jun 23 05:06:45 PM PDT 24
Peak memory 214476 kb
Host smart-7c69ee79-ff0c-4973-b900-d33d96d2e5dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818901416 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_smoke.1818901416
Directory /workspace/10.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_failure.827078976
Short name T110
Test name
Test status
Simulation time 324469425 ps
CPU time 24.88 seconds
Started Jun 23 05:06:44 PM PDT 24
Finished Jun 23 05:07:10 PM PDT 24
Peak memory 250784 kb
Host smart-6fd17436-2817-4570-b231-d97029f7c5a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827078976 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_failure.827078976
Directory /workspace/10.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_post_trans.1893965627
Short name T380
Test name
Test status
Simulation time 199883665 ps
CPU time 6.18 seconds
Started Jun 23 05:06:43 PM PDT 24
Finished Jun 23 05:06:50 PM PDT 24
Peak memory 250764 kb
Host smart-7479c529-2b11-494d-acf1-5ea0fe166358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893965627 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_post_trans.1893965627
Directory /workspace/10.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all_with_rand_reset.2630745809
Short name T705
Test name
Test status
Simulation time 105029840354 ps
CPU time 599.79 seconds
Started Jun 23 05:06:43 PM PDT 24
Finished Jun 23 05:16:44 PM PDT 24
Peak memory 422100 kb
Host smart-e93307df-0607-43da-8a92-a6654d67237a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2630745809 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_stress_all_with_rand_reset.2630745809
Directory /workspace/10.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.lc_ctrl_volatile_unlock_smoke.899225205
Short name T611
Test name
Test status
Simulation time 14522262 ps
CPU time 1.11 seconds
Started Jun 23 05:06:42 PM PDT 24
Finished Jun 23 05:06:44 PM PDT 24
Peak memory 211948 kb
Host smart-120aca40-e153-4a0b-a0eb-222f86f2abb4
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899225205 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ct
rl_volatile_unlock_smoke.899225205
Directory /workspace/10.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_alert_test.3689454236
Short name T236
Test name
Test status
Simulation time 48918074 ps
CPU time 0.9 seconds
Started Jun 23 05:06:51 PM PDT 24
Finished Jun 23 05:06:53 PM PDT 24
Peak memory 208956 kb
Host smart-f83943a4-a2bd-47bc-a91a-582d655faaf3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689454236 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_alert_test.3689454236
Directory /workspace/11.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.lc_ctrl_errors.3271654054
Short name T636
Test name
Test status
Simulation time 362824615 ps
CPU time 7.88 seconds
Started Jun 23 05:06:47 PM PDT 24
Finished Jun 23 05:06:55 PM PDT 24
Peak memory 218132 kb
Host smart-9fe4182a-861e-45c1-9087-1a2a100a2da0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271654054 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_errors.3271654054
Directory /workspace/11.lc_ctrl_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_access.1389683207
Short name T5
Test name
Test status
Simulation time 67512521 ps
CPU time 2.57 seconds
Started Jun 23 05:06:51 PM PDT 24
Finished Jun 23 05:06:54 PM PDT 24
Peak memory 217168 kb
Host smart-28dca481-569e-4920-b6f3-25da187fa2ce
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389683207 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_access.1389683207
Directory /workspace/11.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_errors.2288846919
Short name T442
Test name
Test status
Simulation time 5014202549 ps
CPU time 123.88 seconds
Started Jun 23 05:06:50 PM PDT 24
Finished Jun 23 05:08:55 PM PDT 24
Peak memory 220068 kb
Host smart-79e01c76-ba53-49d5-a798-3c9b833454b6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288846919 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_e
rrors.2288846919
Directory /workspace/11.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_prog_failure.3832052012
Short name T628
Test name
Test status
Simulation time 119121595 ps
CPU time 4.24 seconds
Started Jun 23 05:06:47 PM PDT 24
Finished Jun 23 05:06:52 PM PDT 24
Peak memory 218188 kb
Host smart-86a5bff1-75d5-4793-883c-02ce0c66e9d7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832052012 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jta
g_prog_failure.3832052012
Directory /workspace/11.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_smoke.922653887
Short name T331
Test name
Test status
Simulation time 476629837 ps
CPU time 3.64 seconds
Started Jun 23 05:06:44 PM PDT 24
Finished Jun 23 05:06:49 PM PDT 24
Peak memory 217748 kb
Host smart-cb670b84-47af-4bbf-8f15-9268b94cc489
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922653887 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_smoke.
922653887
Directory /workspace/11.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_failure.1264205154
Short name T518
Test name
Test status
Simulation time 8194480007 ps
CPU time 54.49 seconds
Started Jun 23 05:06:46 PM PDT 24
Finished Jun 23 05:07:41 PM PDT 24
Peak memory 267372 kb
Host smart-71defede-2b8d-4c8d-b404-07620bf83cf8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264205154 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jt
ag_state_failure.1264205154
Directory /workspace/11.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_post_trans.2030613491
Short name T664
Test name
Test status
Simulation time 372918755 ps
CPU time 13.92 seconds
Started Jun 23 05:06:46 PM PDT 24
Finished Jun 23 05:07:01 PM PDT 24
Peak memory 245940 kb
Host smart-bb9aab27-3a77-4c34-a8e2-9d3742d98915
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030613491 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl
_jtag_state_post_trans.2030613491
Directory /workspace/11.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_prog_failure.2002299878
Short name T105
Test name
Test status
Simulation time 55279470 ps
CPU time 2.95 seconds
Started Jun 23 05:06:44 PM PDT 24
Finished Jun 23 05:06:48 PM PDT 24
Peak memory 222548 kb
Host smart-9bc5a509-2e7d-4af5-b86a-763ba587f081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002299878 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_prog_failure.2002299878
Directory /workspace/11.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_mubi.3087940605
Short name T511
Test name
Test status
Simulation time 446134007 ps
CPU time 15.49 seconds
Started Jun 23 05:06:47 PM PDT 24
Finished Jun 23 05:07:03 PM PDT 24
Peak memory 218924 kb
Host smart-9817e073-8362-4755-9e99-24004643e306
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087940605 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_mubi.3087940605
Directory /workspace/11.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_digest.1531758666
Short name T449
Test name
Test status
Simulation time 1121558289 ps
CPU time 11.35 seconds
Started Jun 23 05:06:50 PM PDT 24
Finished Jun 23 05:07:02 PM PDT 24
Peak memory 218268 kb
Host smart-e6bcff3b-035c-43ed-9207-7b7f831328a1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531758666 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_d
igest.1531758666
Directory /workspace/11.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_mux.4200560278
Short name T282
Test name
Test status
Simulation time 521774370 ps
CPU time 11.24 seconds
Started Jun 23 05:06:48 PM PDT 24
Finished Jun 23 05:06:59 PM PDT 24
Peak memory 226068 kb
Host smart-a3e0b75a-b695-46e3-b153-25e960105428
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200560278 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_mux.
4200560278
Directory /workspace/11.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/11.lc_ctrl_security_escalation.2884804176
Short name T508
Test name
Test status
Simulation time 327915352 ps
CPU time 10.87 seconds
Started Jun 23 05:06:46 PM PDT 24
Finished Jun 23 05:06:58 PM PDT 24
Peak memory 218184 kb
Host smart-c62fd746-4378-45f4-9e57-2e1b2bca4ace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2884804176 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_security_escalation.2884804176
Directory /workspace/11.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/11.lc_ctrl_smoke.2597098052
Short name T376
Test name
Test status
Simulation time 94914764 ps
CPU time 1.75 seconds
Started Jun 23 05:06:46 PM PDT 24
Finished Jun 23 05:06:48 PM PDT 24
Peak memory 213960 kb
Host smart-9cef74f7-1dbd-423f-8ba5-632f58bcde6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597098052 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_smoke.2597098052
Directory /workspace/11.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_failure.2424851591
Short name T339
Test name
Test status
Simulation time 213971937 ps
CPU time 26.51 seconds
Started Jun 23 05:06:45 PM PDT 24
Finished Jun 23 05:07:12 PM PDT 24
Peak memory 250820 kb
Host smart-c5de8e79-0f4b-4312-8eb7-c42de61cde63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424851591 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_failure.2424851591
Directory /workspace/11.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_post_trans.3483566157
Short name T717
Test name
Test status
Simulation time 89560143 ps
CPU time 7.85 seconds
Started Jun 23 05:06:44 PM PDT 24
Finished Jun 23 05:06:53 PM PDT 24
Peak memory 250808 kb
Host smart-8c5c2b91-28c4-4de0-8925-b7df6bf6e414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483566157 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_post_trans.3483566157
Directory /workspace/11.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_stress_all.3391645973
Short name T658
Test name
Test status
Simulation time 5320055402 ps
CPU time 196.75 seconds
Started Jun 23 05:06:48 PM PDT 24
Finished Jun 23 05:10:05 PM PDT 24
Peak memory 276560 kb
Host smart-d0387f14-fa44-434b-8b65-d99cd76ba560
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391645973 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.lc_ctrl_stress_all.3391645973
Directory /workspace/11.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.lc_ctrl_stress_all_with_rand_reset.1705503601
Short name T162
Test name
Test status
Simulation time 84316037533 ps
CPU time 534.69 seconds
Started Jun 23 05:06:51 PM PDT 24
Finished Jun 23 05:15:47 PM PDT 24
Peak memory 366796 kb
Host smart-c7ffccaf-d586-438f-a095-fb85ebb2bc4f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1705503601 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_stress_all_with_rand_reset.1705503601
Directory /workspace/11.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.lc_ctrl_volatile_unlock_smoke.1717557164
Short name T35
Test name
Test status
Simulation time 27483361 ps
CPU time 0.95 seconds
Started Jun 23 05:06:43 PM PDT 24
Finished Jun 23 05:06:45 PM PDT 24
Peak memory 211932 kb
Host smart-3e6ec21d-3610-4a26-9a62-38ee310819de
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717557164 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_c
trl_volatile_unlock_smoke.1717557164
Directory /workspace/11.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_alert_test.881096569
Short name T85
Test name
Test status
Simulation time 18073076 ps
CPU time 0.94 seconds
Started Jun 23 05:06:50 PM PDT 24
Finished Jun 23 05:06:52 PM PDT 24
Peak memory 209020 kb
Host smart-0fbabb59-c1f5-407b-8b77-bceaf719627c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881096569 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_alert_test.881096569
Directory /workspace/12.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.lc_ctrl_errors.3943254923
Short name T497
Test name
Test status
Simulation time 908224572 ps
CPU time 15.45 seconds
Started Jun 23 05:06:52 PM PDT 24
Finished Jun 23 05:07:08 PM PDT 24
Peak memory 218132 kb
Host smart-9b1e6c59-3dc5-4416-8d4f-5e1ee24dd705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943254923 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_errors.3943254923
Directory /workspace/12.lc_ctrl_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_access.1820676654
Short name T474
Test name
Test status
Simulation time 1390062326 ps
CPU time 5.42 seconds
Started Jun 23 05:06:51 PM PDT 24
Finished Jun 23 05:06:57 PM PDT 24
Peak memory 217072 kb
Host smart-0128bc40-27da-4b08-bc17-7f1e36f11ad3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820676654 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_access.1820676654
Directory /workspace/12.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_errors.1072340034
Short name T264
Test name
Test status
Simulation time 10670658997 ps
CPU time 37.72 seconds
Started Jun 23 05:06:50 PM PDT 24
Finished Jun 23 05:07:29 PM PDT 24
Peak memory 218912 kb
Host smart-7bbd66c6-4118-4fc1-93de-744afdc036e5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072340034 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_e
rrors.1072340034
Directory /workspace/12.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_prog_failure.1584129065
Short name T315
Test name
Test status
Simulation time 4174404641 ps
CPU time 9.73 seconds
Started Jun 23 05:06:51 PM PDT 24
Finished Jun 23 05:07:01 PM PDT 24
Peak memory 218248 kb
Host smart-1dec6725-b3df-4b6d-a01c-0aa066dc2dfa
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584129065 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jta
g_prog_failure.1584129065
Directory /workspace/12.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_smoke.1233198618
Short name T390
Test name
Test status
Simulation time 97044253 ps
CPU time 2.13 seconds
Started Jun 23 05:06:51 PM PDT 24
Finished Jun 23 05:06:54 PM PDT 24
Peak memory 217692 kb
Host smart-d0c367ff-4593-4eda-bf90-b0c9ad316ed8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233198618 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_smoke
.1233198618
Directory /workspace/12.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_failure.434428658
Short name T479
Test name
Test status
Simulation time 13263016484 ps
CPU time 40.68 seconds
Started Jun 23 05:06:51 PM PDT 24
Finished Jun 23 05:07:33 PM PDT 24
Peak memory 267324 kb
Host smart-d52bdbfc-423f-416a-a407-d9686c346a66
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434428658 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jta
g_state_failure.434428658
Directory /workspace/12.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_post_trans.258223429
Short name T673
Test name
Test status
Simulation time 3172662699 ps
CPU time 11.25 seconds
Started Jun 23 05:06:50 PM PDT 24
Finished Jun 23 05:07:03 PM PDT 24
Peak memory 247448 kb
Host smart-71d06ec8-537b-46c4-83a8-fb8439a3c903
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258223429 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_
jtag_state_post_trans.258223429
Directory /workspace/12.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_prog_failure.2575406285
Short name T1
Test name
Test status
Simulation time 19530093 ps
CPU time 1.45 seconds
Started Jun 23 05:06:53 PM PDT 24
Finished Jun 23 05:06:54 PM PDT 24
Peak memory 221868 kb
Host smart-fa1a4213-64ca-4296-ab1d-1b6b0ba14e76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575406285 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_prog_failure.2575406285
Directory /workspace/12.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_mubi.3942025764
Short name T548
Test name
Test status
Simulation time 616100077 ps
CPU time 11.52 seconds
Started Jun 23 05:06:51 PM PDT 24
Finished Jun 23 05:07:03 PM PDT 24
Peak memory 218276 kb
Host smart-91011db0-daa2-45bd-bace-b347550ebc2a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942025764 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_mubi.3942025764
Directory /workspace/12.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_digest.3498851684
Short name T466
Test name
Test status
Simulation time 1066831667 ps
CPU time 12 seconds
Started Jun 23 05:06:50 PM PDT 24
Finished Jun 23 05:07:03 PM PDT 24
Peak memory 218200 kb
Host smart-7411d52e-e9fb-4dd7-bc93-8ff576334d85
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498851684 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_d
igest.3498851684
Directory /workspace/12.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_mux.3841849868
Short name T564
Test name
Test status
Simulation time 270097127 ps
CPU time 6.97 seconds
Started Jun 23 05:06:53 PM PDT 24
Finished Jun 23 05:07:00 PM PDT 24
Peak memory 218228 kb
Host smart-ff56c244-a22e-40c2-b06c-4285503c8de9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841849868 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_mux.
3841849868
Directory /workspace/12.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/12.lc_ctrl_security_escalation.357420728
Short name T83
Test name
Test status
Simulation time 505167952 ps
CPU time 9.92 seconds
Started Jun 23 05:06:52 PM PDT 24
Finished Jun 23 05:07:02 PM PDT 24
Peak memory 218364 kb
Host smart-cebd3702-eea6-4f10-9753-90062e99c1a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357420728 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_security_escalation.357420728
Directory /workspace/12.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/12.lc_ctrl_smoke.849547287
Short name T79
Test name
Test status
Simulation time 88496662 ps
CPU time 1.38 seconds
Started Jun 23 05:06:44 PM PDT 24
Finished Jun 23 05:06:47 PM PDT 24
Peak memory 217756 kb
Host smart-43ee91c9-fdcf-4b11-bdd1-94a7d0b7f8f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849547287 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_smoke.849547287
Directory /workspace/12.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_failure.1628230488
Short name T226
Test name
Test status
Simulation time 693413837 ps
CPU time 30.24 seconds
Started Jun 23 05:06:46 PM PDT 24
Finished Jun 23 05:07:16 PM PDT 24
Peak memory 250888 kb
Host smart-45935df4-140c-4c30-a51a-aaf345e217aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628230488 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_failure.1628230488
Directory /workspace/12.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_post_trans.3936497826
Short name T589
Test name
Test status
Simulation time 269542067 ps
CPU time 3.91 seconds
Started Jun 23 05:06:51 PM PDT 24
Finished Jun 23 05:06:56 PM PDT 24
Peak memory 222444 kb
Host smart-f33bf881-0cc3-4196-bed4-1772d9186158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936497826 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_post_trans.3936497826
Directory /workspace/12.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_stress_all.734664596
Short name T771
Test name
Test status
Simulation time 10741224144 ps
CPU time 219.47 seconds
Started Jun 23 05:06:52 PM PDT 24
Finished Jun 23 05:10:32 PM PDT 24
Peak memory 267240 kb
Host smart-7c36e500-34f5-4267-88f2-d02d68258f7d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734664596 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.lc_ctrl_stress_all.734664596
Directory /workspace/12.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.lc_ctrl_stress_all_with_rand_reset.3436107543
Short name T824
Test name
Test status
Simulation time 88276646146 ps
CPU time 359.89 seconds
Started Jun 23 05:06:51 PM PDT 24
Finished Jun 23 05:12:52 PM PDT 24
Peak memory 283828 kb
Host smart-bd34eaf7-e385-4d9e-8bbd-9bc89c1ff3ef
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3436107543 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_stress_all_with_rand_reset.3436107543
Directory /workspace/12.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.lc_ctrl_volatile_unlock_smoke.3485995598
Short name T600
Test name
Test status
Simulation time 13112390 ps
CPU time 0.96 seconds
Started Jun 23 05:06:47 PM PDT 24
Finished Jun 23 05:06:49 PM PDT 24
Peak memory 212020 kb
Host smart-35b42000-f03c-4e37-989b-19b6e38c8410
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485995598 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_c
trl_volatile_unlock_smoke.3485995598
Directory /workspace/12.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_alert_test.2227121278
Short name T359
Test name
Test status
Simulation time 19117417 ps
CPU time 1.18 seconds
Started Jun 23 05:06:57 PM PDT 24
Finished Jun 23 05:06:59 PM PDT 24
Peak memory 209040 kb
Host smart-c7c62ee6-8a60-43e2-98d4-cf6dc0730cf0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227121278 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_alert_test.2227121278
Directory /workspace/13.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.lc_ctrl_errors.4037976648
Short name T637
Test name
Test status
Simulation time 922900948 ps
CPU time 8.14 seconds
Started Jun 23 05:06:55 PM PDT 24
Finished Jun 23 05:07:03 PM PDT 24
Peak memory 218196 kb
Host smart-19dce3f3-08b0-42e5-a749-fbf4de9f5a81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037976648 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_errors.4037976648
Directory /workspace/13.lc_ctrl_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_access.616283783
Short name T726
Test name
Test status
Simulation time 613979293 ps
CPU time 7.45 seconds
Started Jun 23 05:06:57 PM PDT 24
Finished Jun 23 05:07:05 PM PDT 24
Peak memory 217568 kb
Host smart-272da11b-025c-41e3-b57a-e188eab129d1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616283783 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_access.616283783
Directory /workspace/13.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_errors.3321918779
Short name T853
Test name
Test status
Simulation time 1457315722 ps
CPU time 46.25 seconds
Started Jun 23 05:06:59 PM PDT 24
Finished Jun 23 05:07:45 PM PDT 24
Peak memory 218836 kb
Host smart-e3c986fd-5736-452c-a2f3-38374bbd38f3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321918779 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_e
rrors.3321918779
Directory /workspace/13.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_prog_failure.2326366275
Short name T107
Test name
Test status
Simulation time 614869776 ps
CPU time 4.66 seconds
Started Jun 23 05:07:00 PM PDT 24
Finished Jun 23 05:07:05 PM PDT 24
Peak memory 218152 kb
Host smart-419c0c55-6db6-4e58-a044-e08b15ef166e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326366275 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jta
g_prog_failure.2326366275
Directory /workspace/13.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_smoke.1475797895
Short name T832
Test name
Test status
Simulation time 456389070 ps
CPU time 6.15 seconds
Started Jun 23 05:06:57 PM PDT 24
Finished Jun 23 05:07:04 PM PDT 24
Peak memory 217692 kb
Host smart-0be18e02-83a8-419d-a6e4-16d42daf63f9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475797895 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_smoke
.1475797895
Directory /workspace/13.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_failure.1256355424
Short name T857
Test name
Test status
Simulation time 14451215492 ps
CPU time 48.18 seconds
Started Jun 23 05:06:58 PM PDT 24
Finished Jun 23 05:07:46 PM PDT 24
Peak memory 278968 kb
Host smart-4ea118b1-ca5e-4d7a-9f05-33b52015d0ea
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256355424 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jt
ag_state_failure.1256355424
Directory /workspace/13.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_post_trans.4024477005
Short name T570
Test name
Test status
Simulation time 367289940 ps
CPU time 14.51 seconds
Started Jun 23 05:06:57 PM PDT 24
Finished Jun 23 05:07:12 PM PDT 24
Peak memory 250744 kb
Host smart-8c411bef-c969-4cf2-9dce-9c526c93458b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024477005 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl
_jtag_state_post_trans.4024477005
Directory /workspace/13.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_prog_failure.241210600
Short name T784
Test name
Test status
Simulation time 511115059 ps
CPU time 2.65 seconds
Started Jun 23 05:07:00 PM PDT 24
Finished Jun 23 05:07:04 PM PDT 24
Peak memory 222280 kb
Host smart-2be484ee-4044-496a-8a11-05343ffd952c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241210600 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_prog_failure.241210600
Directory /workspace/13.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_mubi.645397679
Short name T844
Test name
Test status
Simulation time 1155957357 ps
CPU time 16.2 seconds
Started Jun 23 05:06:59 PM PDT 24
Finished Jun 23 05:07:15 PM PDT 24
Peak memory 218836 kb
Host smart-35a24672-4956-4b5e-9826-861cf5158a49
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645397679 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_mubi.645397679
Directory /workspace/13.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_digest.3750077537
Short name T501
Test name
Test status
Simulation time 1923512596 ps
CPU time 13.92 seconds
Started Jun 23 05:06:57 PM PDT 24
Finished Jun 23 05:07:12 PM PDT 24
Peak memory 218196 kb
Host smart-f2e75f79-3366-4f0f-993b-8af285752e98
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750077537 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_d
igest.3750077537
Directory /workspace/13.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_mux.2172265114
Short name T410
Test name
Test status
Simulation time 166977817 ps
CPU time 7.26 seconds
Started Jun 23 05:06:56 PM PDT 24
Finished Jun 23 05:07:04 PM PDT 24
Peak memory 225532 kb
Host smart-1bf6f075-43cc-49e4-a7b1-cef16fcae68c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172265114 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_mux.
2172265114
Directory /workspace/13.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/13.lc_ctrl_security_escalation.2860886629
Short name T678
Test name
Test status
Simulation time 2727121709 ps
CPU time 9.05 seconds
Started Jun 23 05:06:55 PM PDT 24
Finished Jun 23 05:07:05 PM PDT 24
Peak memory 225412 kb
Host smart-ea5e4313-7c19-4348-a653-8d57d067e977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860886629 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_security_escalation.2860886629
Directory /workspace/13.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/13.lc_ctrl_smoke.977109172
Short name T254
Test name
Test status
Simulation time 47094110 ps
CPU time 3.39 seconds
Started Jun 23 05:06:50 PM PDT 24
Finished Jun 23 05:06:54 PM PDT 24
Peak memory 217760 kb
Host smart-a833f59a-6fc0-457d-8113-85555ad4e923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977109172 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_smoke.977109172
Directory /workspace/13.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_failure.4215869894
Short name T420
Test name
Test status
Simulation time 544322756 ps
CPU time 23.39 seconds
Started Jun 23 05:06:53 PM PDT 24
Finished Jun 23 05:07:17 PM PDT 24
Peak memory 250912 kb
Host smart-105211b9-704c-4f04-8829-8223b4a5a9d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215869894 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_failure.4215869894
Directory /workspace/13.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_post_trans.3946365260
Short name T566
Test name
Test status
Simulation time 134806902 ps
CPU time 8.4 seconds
Started Jun 23 05:06:56 PM PDT 24
Finished Jun 23 05:07:05 PM PDT 24
Peak memory 250876 kb
Host smart-bbd72a52-b707-4cae-9b33-73c66d3bbb5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946365260 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_post_trans.3946365260
Directory /workspace/13.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all.3091106450
Short name T459
Test name
Test status
Simulation time 32157798275 ps
CPU time 70.13 seconds
Started Jun 23 05:06:57 PM PDT 24
Finished Jun 23 05:08:08 PM PDT 24
Peak memory 267240 kb
Host smart-cd32d523-0be7-4417-8fdb-62f4983bc881
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091106450 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.lc_ctrl_stress_all.3091106450
Directory /workspace/13.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all_with_rand_reset.3847171378
Short name T160
Test name
Test status
Simulation time 61005313269 ps
CPU time 1032.11 seconds
Started Jun 23 05:06:55 PM PDT 24
Finished Jun 23 05:24:07 PM PDT 24
Peak memory 283756 kb
Host smart-62e56d36-1d7c-46b0-8cd3-81c5fa097bdf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3847171378 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_stress_all_with_rand_reset.3847171378
Directory /workspace/13.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.lc_ctrl_volatile_unlock_smoke.2450035877
Short name T28
Test name
Test status
Simulation time 24222236 ps
CPU time 0.88 seconds
Started Jun 23 05:06:51 PM PDT 24
Finished Jun 23 05:06:52 PM PDT 24
Peak memory 208140 kb
Host smart-b74cf10d-4706-4e74-829f-377168af91e5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450035877 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_c
trl_volatile_unlock_smoke.2450035877
Directory /workspace/13.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_alert_test.1711984371
Short name T701
Test name
Test status
Simulation time 34870297 ps
CPU time 0.91 seconds
Started Jun 23 05:07:04 PM PDT 24
Finished Jun 23 05:07:05 PM PDT 24
Peak memory 208960 kb
Host smart-4ae63707-3ecd-4908-a504-b9a5278b9a49
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711984371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_alert_test.1711984371
Directory /workspace/14.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.lc_ctrl_errors.3812911853
Short name T227
Test name
Test status
Simulation time 380073592 ps
CPU time 15.39 seconds
Started Jun 23 05:07:10 PM PDT 24
Finished Jun 23 05:07:26 PM PDT 24
Peak memory 218160 kb
Host smart-bb8418f7-1c42-46a9-ad40-2c2995fc1320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812911853 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_errors.3812911853
Directory /workspace/14.lc_ctrl_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_access.2034908141
Short name T195
Test name
Test status
Simulation time 2058025733 ps
CPU time 6.05 seconds
Started Jun 23 05:07:04 PM PDT 24
Finished Jun 23 05:07:10 PM PDT 24
Peak memory 217240 kb
Host smart-877318ed-d72f-44f6-bdb7-a889914a902f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034908141 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_access.2034908141
Directory /workspace/14.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_errors.3093235741
Short name T417
Test name
Test status
Simulation time 4832108949 ps
CPU time 40.9 seconds
Started Jun 23 05:07:02 PM PDT 24
Finished Jun 23 05:07:43 PM PDT 24
Peak memory 225952 kb
Host smart-123edbc0-9ffd-4c1e-99ea-00d137f923b7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093235741 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_e
rrors.3093235741
Directory /workspace/14.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_prog_failure.533079318
Short name T609
Test name
Test status
Simulation time 925775923 ps
CPU time 2.42 seconds
Started Jun 23 05:07:00 PM PDT 24
Finished Jun 23 05:07:02 PM PDT 24
Peak memory 221428 kb
Host smart-7ab6b337-2eb7-4f19-bf8d-82008d7e6e01
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533079318 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag
_prog_failure.533079318
Directory /workspace/14.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_smoke.4218051797
Short name T593
Test name
Test status
Simulation time 3535381066 ps
CPU time 13.09 seconds
Started Jun 23 05:07:06 PM PDT 24
Finished Jun 23 05:07:20 PM PDT 24
Peak memory 217648 kb
Host smart-dc2e2cc8-a19d-4963-bc5e-cb33359e0571
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218051797 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_smoke
.4218051797
Directory /workspace/14.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_failure.3969012735
Short name T550
Test name
Test status
Simulation time 2961236406 ps
CPU time 56.17 seconds
Started Jun 23 05:07:03 PM PDT 24
Finished Jun 23 05:08:00 PM PDT 24
Peak memory 253304 kb
Host smart-15e0801f-8f3b-4aae-b09d-2122fd809252
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969012735 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jt
ag_state_failure.3969012735
Directory /workspace/14.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_post_trans.931721123
Short name T185
Test name
Test status
Simulation time 814235310 ps
CPU time 26.04 seconds
Started Jun 23 05:07:06 PM PDT 24
Finished Jun 23 05:07:33 PM PDT 24
Peak memory 250668 kb
Host smart-5629cdf6-ef46-42e7-959e-e13b8bf35c0b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931721123 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_
jtag_state_post_trans.931721123
Directory /workspace/14.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_prog_failure.2382775687
Short name T833
Test name
Test status
Simulation time 105212443 ps
CPU time 3.63 seconds
Started Jun 23 05:07:01 PM PDT 24
Finished Jun 23 05:07:05 PM PDT 24
Peak memory 222208 kb
Host smart-bd10ad78-4a3d-448d-8460-295ec94dae27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382775687 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_prog_failure.2382775687
Directory /workspace/14.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_mubi.3126844655
Short name T585
Test name
Test status
Simulation time 805992562 ps
CPU time 18.07 seconds
Started Jun 23 05:07:01 PM PDT 24
Finished Jun 23 05:07:19 PM PDT 24
Peak memory 225980 kb
Host smart-6b8277dd-f5a7-4812-961e-f29983790196
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126844655 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_mubi.3126844655
Directory /workspace/14.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_digest.3618590852
Short name T846
Test name
Test status
Simulation time 315568626 ps
CPU time 13.55 seconds
Started Jun 23 05:07:03 PM PDT 24
Finished Jun 23 05:07:17 PM PDT 24
Peak memory 218272 kb
Host smart-e46bd2a5-f16c-4883-b0a0-88b29fd7c946
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618590852 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_d
igest.3618590852
Directory /workspace/14.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_mux.3525635210
Short name T685
Test name
Test status
Simulation time 328889041 ps
CPU time 8.77 seconds
Started Jun 23 05:07:06 PM PDT 24
Finished Jun 23 05:07:15 PM PDT 24
Peak memory 218260 kb
Host smart-f597062b-ceff-49c5-b649-2b89ed1cddfb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525635210 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_mux.
3525635210
Directory /workspace/14.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/14.lc_ctrl_security_escalation.859533816
Short name T591
Test name
Test status
Simulation time 344869158 ps
CPU time 12.71 seconds
Started Jun 23 05:07:00 PM PDT 24
Finished Jun 23 05:07:13 PM PDT 24
Peak memory 225780 kb
Host smart-877f3744-d6cc-4574-bd2e-5c55e6074fd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859533816 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_security_escalation.859533816
Directory /workspace/14.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/14.lc_ctrl_smoke.3140468945
Short name T385
Test name
Test status
Simulation time 57541078 ps
CPU time 2.59 seconds
Started Jun 23 05:06:56 PM PDT 24
Finished Jun 23 05:06:59 PM PDT 24
Peak memory 214376 kb
Host smart-0a70a143-8361-41a4-b0cf-0304d4e11340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140468945 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_smoke.3140468945
Directory /workspace/14.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_failure.3939957835
Short name T808
Test name
Test status
Simulation time 791565139 ps
CPU time 23.27 seconds
Started Jun 23 05:07:02 PM PDT 24
Finished Jun 23 05:07:26 PM PDT 24
Peak memory 250916 kb
Host smart-7623ced6-dda6-4639-b10d-357c3cda60bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939957835 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_failure.3939957835
Directory /workspace/14.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_post_trans.1496679108
Short name T510
Test name
Test status
Simulation time 259999356 ps
CPU time 4.05 seconds
Started Jun 23 05:07:06 PM PDT 24
Finished Jun 23 05:07:11 PM PDT 24
Peak memory 222768 kb
Host smart-66f20cb0-012c-4226-b2a8-ab1449d9e276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496679108 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_post_trans.1496679108
Directory /workspace/14.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_stress_all.813056920
Short name T499
Test name
Test status
Simulation time 642428143 ps
CPU time 33.62 seconds
Started Jun 23 05:07:02 PM PDT 24
Finished Jun 23 05:07:36 PM PDT 24
Peak memory 250836 kb
Host smart-e10a3820-19f0-46f5-9a7b-d9c0b448a270
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813056920 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.lc_ctrl_stress_all.813056920
Directory /workspace/14.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.lc_ctrl_stress_all_with_rand_reset.3895301503
Short name T148
Test name
Test status
Simulation time 4380390997 ps
CPU time 166.8 seconds
Started Jun 23 05:07:03 PM PDT 24
Finished Jun 23 05:09:50 PM PDT 24
Peak memory 277464 kb
Host smart-eca15c9f-dc71-4ec4-ad65-75ec5a7d50ab
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3895301503 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_stress_all_with_rand_reset.3895301503
Directory /workspace/14.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.lc_ctrl_volatile_unlock_smoke.1221594046
Short name T729
Test name
Test status
Simulation time 15091040 ps
CPU time 0.85 seconds
Started Jun 23 05:07:07 PM PDT 24
Finished Jun 23 05:07:08 PM PDT 24
Peak memory 208940 kb
Host smart-940e0eb3-d759-4d3d-b891-4b22d6a16d28
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221594046 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_c
trl_volatile_unlock_smoke.1221594046
Directory /workspace/14.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_alert_test.2315901811
Short name T235
Test name
Test status
Simulation time 51714137 ps
CPU time 0.9 seconds
Started Jun 23 05:07:13 PM PDT 24
Finished Jun 23 05:07:15 PM PDT 24
Peak memory 208892 kb
Host smart-b788e1ae-7bf9-4bd7-9cd4-9f64ed8ac951
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315901811 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_alert_test.2315901811
Directory /workspace/15.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.lc_ctrl_errors.3871052397
Short name T262
Test name
Test status
Simulation time 532570915 ps
CPU time 20.17 seconds
Started Jun 23 05:07:05 PM PDT 24
Finished Jun 23 05:07:25 PM PDT 24
Peak memory 218228 kb
Host smart-829c3809-4979-4b83-ac47-c10ef4a39230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871052397 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_errors.3871052397
Directory /workspace/15.lc_ctrl_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_access.3978784139
Short name T388
Test name
Test status
Simulation time 373821545 ps
CPU time 5.29 seconds
Started Jun 23 05:07:02 PM PDT 24
Finished Jun 23 05:07:08 PM PDT 24
Peak memory 217340 kb
Host smart-06bb382f-56d6-462f-8213-2ba515bc53ef
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978784139 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_access.3978784139
Directory /workspace/15.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_errors.3399831557
Short name T532
Test name
Test status
Simulation time 8175390937 ps
CPU time 100.11 seconds
Started Jun 23 05:07:09 PM PDT 24
Finished Jun 23 05:08:50 PM PDT 24
Peak memory 226024 kb
Host smart-54b1660d-8efc-46fd-9e00-61304ceedcd7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399831557 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_e
rrors.3399831557
Directory /workspace/15.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_prog_failure.3795921925
Short name T876
Test name
Test status
Simulation time 661955202 ps
CPU time 3.66 seconds
Started Jun 23 05:07:04 PM PDT 24
Finished Jun 23 05:07:08 PM PDT 24
Peak memory 222704 kb
Host smart-64f137af-d5d7-438e-9030-9bfcc5efd489
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795921925 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jta
g_prog_failure.3795921925
Directory /workspace/15.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_smoke.805182459
Short name T71
Test name
Test status
Simulation time 2108084526 ps
CPU time 12.93 seconds
Started Jun 23 05:07:01 PM PDT 24
Finished Jun 23 05:07:14 PM PDT 24
Peak memory 217592 kb
Host smart-469ce373-29a0-49d5-8ea5-c95eeead4e84
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805182459 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_smoke.
805182459
Directory /workspace/15.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_failure.3522412389
Short name T651
Test name
Test status
Simulation time 4738113789 ps
CPU time 55.18 seconds
Started Jun 23 05:07:10 PM PDT 24
Finished Jun 23 05:08:05 PM PDT 24
Peak memory 275436 kb
Host smart-b2c90e6b-0143-43c0-ade9-862452e9254b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522412389 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jt
ag_state_failure.3522412389
Directory /workspace/15.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_post_trans.2228513952
Short name T524
Test name
Test status
Simulation time 3422988576 ps
CPU time 17.44 seconds
Started Jun 23 05:07:05 PM PDT 24
Finished Jun 23 05:07:23 PM PDT 24
Peak memory 250796 kb
Host smart-05a8cc14-cbd9-4087-9cfa-8a77e12de9fa
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228513952 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl
_jtag_state_post_trans.2228513952
Directory /workspace/15.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_prog_failure.1987457228
Short name T622
Test name
Test status
Simulation time 122339451 ps
CPU time 1.91 seconds
Started Jun 23 05:07:04 PM PDT 24
Finished Jun 23 05:07:06 PM PDT 24
Peak memory 218228 kb
Host smart-0bbd3a0f-017d-4c35-a9f1-ba9de2bf829a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987457228 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_prog_failure.1987457228
Directory /workspace/15.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_mubi.438850023
Short name T477
Test name
Test status
Simulation time 793437365 ps
CPU time 10.48 seconds
Started Jun 23 05:07:04 PM PDT 24
Finished Jun 23 05:07:15 PM PDT 24
Peak memory 218256 kb
Host smart-212d0be5-8773-4ba8-8dc9-57e185b6a118
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438850023 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_mubi.438850023
Directory /workspace/15.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_digest.1966734790
Short name T355
Test name
Test status
Simulation time 1107214399 ps
CPU time 13.75 seconds
Started Jun 23 05:07:08 PM PDT 24
Finished Jun 23 05:07:22 PM PDT 24
Peak memory 226056 kb
Host smart-d1b18c26-64c3-474f-90ec-0be25a69d01b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966734790 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_d
igest.1966734790
Directory /workspace/15.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_mux.2495157959
Short name T436
Test name
Test status
Simulation time 1288154445 ps
CPU time 19.98 seconds
Started Jun 23 05:07:07 PM PDT 24
Finished Jun 23 05:07:27 PM PDT 24
Peak memory 226068 kb
Host smart-63098466-7ede-4b85-98f7-e556d6b476f5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495157959 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_mux.
2495157959
Directory /workspace/15.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/15.lc_ctrl_security_escalation.3640422848
Short name T648
Test name
Test status
Simulation time 589306061 ps
CPU time 7.21 seconds
Started Jun 23 05:07:05 PM PDT 24
Finished Jun 23 05:07:13 PM PDT 24
Peak memory 225936 kb
Host smart-59b29e99-8a55-444e-bc15-501f274be720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640422848 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_security_escalation.3640422848
Directory /workspace/15.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/15.lc_ctrl_smoke.2883977123
Short name T303
Test name
Test status
Simulation time 586251593 ps
CPU time 2.99 seconds
Started Jun 23 05:07:00 PM PDT 24
Finished Jun 23 05:07:03 PM PDT 24
Peak memory 217732 kb
Host smart-5ab51c1f-fcde-4829-a1f2-3295ec605cdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883977123 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_smoke.2883977123
Directory /workspace/15.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_failure.1357090303
Short name T175
Test name
Test status
Simulation time 1002338081 ps
CPU time 23.32 seconds
Started Jun 23 05:07:02 PM PDT 24
Finished Jun 23 05:07:25 PM PDT 24
Peak memory 250780 kb
Host smart-5656fd88-e684-456a-b276-6db9dad9653b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357090303 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_failure.1357090303
Directory /workspace/15.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_post_trans.620373202
Short name T795
Test name
Test status
Simulation time 253171079 ps
CPU time 7.65 seconds
Started Jun 23 05:07:05 PM PDT 24
Finished Jun 23 05:07:13 PM PDT 24
Peak memory 250800 kb
Host smart-17cc59fd-f869-4321-a3ee-b7afb39d03b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620373202 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_post_trans.620373202
Directory /workspace/15.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all.636600249
Short name T713
Test name
Test status
Simulation time 876554410 ps
CPU time 15.12 seconds
Started Jun 23 05:07:06 PM PDT 24
Finished Jun 23 05:07:22 PM PDT 24
Peak memory 245484 kb
Host smart-18ee04df-57c5-4ae9-8d49-7bae1bce30f3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636600249 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.lc_ctrl_stress_all.636600249
Directory /workspace/15.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.lc_ctrl_volatile_unlock_smoke.3664817724
Short name T66
Test name
Test status
Simulation time 21510252 ps
CPU time 1.01 seconds
Started Jun 23 05:07:06 PM PDT 24
Finished Jun 23 05:07:07 PM PDT 24
Peak memory 211888 kb
Host smart-b06d9de2-e48c-4a54-bddf-fbbdf89aabd0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664817724 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_c
trl_volatile_unlock_smoke.3664817724
Directory /workspace/15.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_alert_test.2933405353
Short name T863
Test name
Test status
Simulation time 20995388 ps
CPU time 1.18 seconds
Started Jun 23 05:07:12 PM PDT 24
Finished Jun 23 05:07:14 PM PDT 24
Peak memory 208968 kb
Host smart-5c09dffd-723e-4e87-8c8d-3f687eb70ab8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933405353 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_alert_test.2933405353
Directory /workspace/16.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_access.3216574574
Short name T680
Test name
Test status
Simulation time 398500039 ps
CPU time 3.22 seconds
Started Jun 23 05:07:13 PM PDT 24
Finished Jun 23 05:07:17 PM PDT 24
Peak memory 217016 kb
Host smart-efa02f5b-2c29-4db6-a90f-8f68ff26723f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216574574 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_access.3216574574
Directory /workspace/16.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_errors.905881655
Short name T234
Test name
Test status
Simulation time 5241085816 ps
CPU time 41.93 seconds
Started Jun 23 05:07:09 PM PDT 24
Finished Jun 23 05:07:51 PM PDT 24
Peak memory 218280 kb
Host smart-02af7471-eecc-48c1-8a1f-0f96ec245e75
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905881655 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_er
rors.905881655
Directory /workspace/16.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_prog_failure.1507967215
Short name T778
Test name
Test status
Simulation time 400787060 ps
CPU time 11.94 seconds
Started Jun 23 05:07:07 PM PDT 24
Finished Jun 23 05:07:20 PM PDT 24
Peak memory 218188 kb
Host smart-47490773-fa8b-4741-81ec-1f66e86f15d3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507967215 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jta
g_prog_failure.1507967215
Directory /workspace/16.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_smoke.956779354
Short name T830
Test name
Test status
Simulation time 202477659 ps
CPU time 3.26 seconds
Started Jun 23 05:07:07 PM PDT 24
Finished Jun 23 05:07:11 PM PDT 24
Peak memory 217628 kb
Host smart-00ac66a0-5c3a-4015-95e8-992c2458169b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956779354 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_smoke.
956779354
Directory /workspace/16.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_failure.446015107
Short name T597
Test name
Test status
Simulation time 3449397977 ps
CPU time 42.55 seconds
Started Jun 23 05:07:08 PM PDT 24
Finished Jun 23 05:07:51 PM PDT 24
Peak memory 276968 kb
Host smart-6a82e1ac-3938-483f-89fd-75b06bd6a0fe
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446015107 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jta
g_state_failure.446015107
Directory /workspace/16.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_post_trans.2851885544
Short name T509
Test name
Test status
Simulation time 3492862998 ps
CPU time 17.37 seconds
Started Jun 23 05:07:06 PM PDT 24
Finished Jun 23 05:07:23 PM PDT 24
Peak memory 247216 kb
Host smart-d2f0006e-c564-4c3b-aa16-58664749a829
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851885544 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl
_jtag_state_post_trans.2851885544
Directory /workspace/16.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_prog_failure.1043126177
Short name T99
Test name
Test status
Simulation time 404605145 ps
CPU time 3.08 seconds
Started Jun 23 05:07:04 PM PDT 24
Finished Jun 23 05:07:08 PM PDT 24
Peak memory 218292 kb
Host smart-f9b72068-a745-4feb-a96d-74afb479f1d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043126177 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_prog_failure.1043126177
Directory /workspace/16.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_mubi.3609162073
Short name T810
Test name
Test status
Simulation time 376296343 ps
CPU time 14.52 seconds
Started Jun 23 05:07:05 PM PDT 24
Finished Jun 23 05:07:20 PM PDT 24
Peak memory 218864 kb
Host smart-e1f651bc-32db-4ab6-948c-36a82394aaf2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609162073 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_mubi.3609162073
Directory /workspace/16.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_digest.4184362250
Short name T507
Test name
Test status
Simulation time 4451404583 ps
CPU time 10.69 seconds
Started Jun 23 05:07:13 PM PDT 24
Finished Jun 23 05:07:25 PM PDT 24
Peak memory 218188 kb
Host smart-b00f1f60-05f0-4db1-b68e-d96bde5d9846
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184362250 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_d
igest.4184362250
Directory /workspace/16.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_mux.3332799423
Short name T875
Test name
Test status
Simulation time 1382754885 ps
CPU time 9.13 seconds
Started Jun 23 05:07:10 PM PDT 24
Finished Jun 23 05:07:20 PM PDT 24
Peak memory 218224 kb
Host smart-1a28e227-a94b-4d46-ac16-be84196efe37
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332799423 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_mux.
3332799423
Directory /workspace/16.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/16.lc_ctrl_security_escalation.975856235
Short name T708
Test name
Test status
Simulation time 871558828 ps
CPU time 14.42 seconds
Started Jun 23 05:07:13 PM PDT 24
Finished Jun 23 05:07:28 PM PDT 24
Peak memory 225632 kb
Host smart-a7b753bd-898e-4587-8820-e634d7cdd02a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975856235 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_security_escalation.975856235
Directory /workspace/16.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/16.lc_ctrl_smoke.4221683178
Short name T62
Test name
Test status
Simulation time 73508286 ps
CPU time 3.11 seconds
Started Jun 23 05:07:07 PM PDT 24
Finished Jun 23 05:07:11 PM PDT 24
Peak memory 214680 kb
Host smart-3c3eddaf-c056-40db-a1c4-b6950b91362a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221683178 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_smoke.4221683178
Directory /workspace/16.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_failure.248254370
Short name T350
Test name
Test status
Simulation time 420032307 ps
CPU time 23.57 seconds
Started Jun 23 05:07:09 PM PDT 24
Finished Jun 23 05:07:33 PM PDT 24
Peak memory 250840 kb
Host smart-f5323beb-bbf3-4f0d-a617-f724e9adfc4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248254370 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_failure.248254370
Directory /workspace/16.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_post_trans.1865723512
Short name T457
Test name
Test status
Simulation time 121342432 ps
CPU time 7.83 seconds
Started Jun 23 05:07:12 PM PDT 24
Finished Jun 23 05:07:21 PM PDT 24
Peak memory 250784 kb
Host smart-cd4479be-71c9-4a51-b3e2-5bc39ce0c85f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865723512 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_post_trans.1865723512
Directory /workspace/16.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_stress_all.2238546482
Short name T463
Test name
Test status
Simulation time 19885774544 ps
CPU time 139.96 seconds
Started Jun 23 05:07:13 PM PDT 24
Finished Jun 23 05:09:33 PM PDT 24
Peak memory 267240 kb
Host smart-a61b0042-50ef-42b2-8a11-82f39d513adb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238546482 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.lc_ctrl_stress_all.2238546482
Directory /workspace/16.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.lc_ctrl_volatile_unlock_smoke.4276181594
Short name T253
Test name
Test status
Simulation time 33170245 ps
CPU time 0.89 seconds
Started Jun 23 05:07:08 PM PDT 24
Finished Jun 23 05:07:10 PM PDT 24
Peak memory 209024 kb
Host smart-8bc48168-2244-4b77-ac7c-ce9ebffd3b35
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276181594 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_c
trl_volatile_unlock_smoke.4276181594
Directory /workspace/16.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_alert_test.687831196
Short name T781
Test name
Test status
Simulation time 42981443 ps
CPU time 0.95 seconds
Started Jun 23 05:07:13 PM PDT 24
Finished Jun 23 05:07:15 PM PDT 24
Peak memory 209024 kb
Host smart-a7f7c4cc-b774-4ee5-aa16-a715f625bded
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687831196 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_alert_test.687831196
Directory /workspace/17.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.lc_ctrl_errors.603624938
Short name T92
Test name
Test status
Simulation time 811749775 ps
CPU time 8.02 seconds
Started Jun 23 05:07:08 PM PDT 24
Finished Jun 23 05:07:16 PM PDT 24
Peak memory 218204 kb
Host smart-3d39bb71-65f2-4885-bfbd-d1f8d4866da4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603624938 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_errors.603624938
Directory /workspace/17.lc_ctrl_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_access.506732828
Short name T512
Test name
Test status
Simulation time 823301611 ps
CPU time 1.86 seconds
Started Jun 23 05:07:11 PM PDT 24
Finished Jun 23 05:07:13 PM PDT 24
Peak memory 217164 kb
Host smart-4fec3139-454a-46ec-9a85-cdc113fd6524
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506732828 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_access.506732828
Directory /workspace/17.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_errors.1885002244
Short name T328
Test name
Test status
Simulation time 1449514576 ps
CPU time 25.01 seconds
Started Jun 23 05:07:11 PM PDT 24
Finished Jun 23 05:07:36 PM PDT 24
Peak memory 218124 kb
Host smart-fd62039e-8c8a-42dd-a409-f9088523ef79
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885002244 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_e
rrors.1885002244
Directory /workspace/17.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_prog_failure.1604502783
Short name T864
Test name
Test status
Simulation time 3067698727 ps
CPU time 5.28 seconds
Started Jun 23 05:07:13 PM PDT 24
Finished Jun 23 05:07:19 PM PDT 24
Peak memory 221936 kb
Host smart-1a30b078-aec8-4701-96ff-c3dc3e9f3aea
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604502783 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jta
g_prog_failure.1604502783
Directory /workspace/17.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_smoke.676031814
Short name T338
Test name
Test status
Simulation time 441085899 ps
CPU time 5.7 seconds
Started Jun 23 05:07:13 PM PDT 24
Finished Jun 23 05:07:20 PM PDT 24
Peak memory 217556 kb
Host smart-0ac9f36d-4d6a-419b-98c4-700e45af8e97
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676031814 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_smoke.
676031814
Directory /workspace/17.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_failure.1459711688
Short name T308
Test name
Test status
Simulation time 2704207866 ps
CPU time 50.97 seconds
Started Jun 23 05:07:12 PM PDT 24
Finished Jun 23 05:08:03 PM PDT 24
Peak memory 275396 kb
Host smart-d1c17fe0-fbba-4363-b0af-110365a7f85e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459711688 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jt
ag_state_failure.1459711688
Directory /workspace/17.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_post_trans.1439331342
Short name T793
Test name
Test status
Simulation time 625688642 ps
CPU time 14.12 seconds
Started Jun 23 05:07:11 PM PDT 24
Finished Jun 23 05:07:26 PM PDT 24
Peak memory 242512 kb
Host smart-61990345-7d49-4cbc-8d15-93b5541b5978
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439331342 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl
_jtag_state_post_trans.1439331342
Directory /workspace/17.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_prog_failure.1649280099
Short name T687
Test name
Test status
Simulation time 1393502659 ps
CPU time 4.63 seconds
Started Jun 23 05:07:08 PM PDT 24
Finished Jun 23 05:07:13 PM PDT 24
Peak memory 222560 kb
Host smart-e0caf517-069e-4f4f-8674-77cdbb4a8e93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649280099 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_prog_failure.1649280099
Directory /workspace/17.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_mubi.2957520478
Short name T529
Test name
Test status
Simulation time 5931755759 ps
CPU time 10.64 seconds
Started Jun 23 05:07:23 PM PDT 24
Finished Jun 23 05:07:34 PM PDT 24
Peak memory 218972 kb
Host smart-3ff2db2f-e12e-46e8-8f83-ca0753b786f0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957520478 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_mubi.2957520478
Directory /workspace/17.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_digest.3231126937
Short name T374
Test name
Test status
Simulation time 263231598 ps
CPU time 10.01 seconds
Started Jun 23 05:07:12 PM PDT 24
Finished Jun 23 05:07:23 PM PDT 24
Peak memory 218344 kb
Host smart-8f5a1a61-e64e-4a28-91e4-2feb6bcf0213
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231126937 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_d
igest.3231126937
Directory /workspace/17.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_mux.2499169715
Short name T574
Test name
Test status
Simulation time 1096242280 ps
CPU time 8.89 seconds
Started Jun 23 05:07:13 PM PDT 24
Finished Jun 23 05:07:23 PM PDT 24
Peak memory 218312 kb
Host smart-c853a500-effa-4cd8-913b-1a5ed838b933
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499169715 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_mux.
2499169715
Directory /workspace/17.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/17.lc_ctrl_security_escalation.1456773848
Short name T492
Test name
Test status
Simulation time 354802348 ps
CPU time 7.56 seconds
Started Jun 23 05:07:09 PM PDT 24
Finished Jun 23 05:07:17 PM PDT 24
Peak memory 218300 kb
Host smart-685bc827-a782-439d-861f-706894d00653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456773848 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_security_escalation.1456773848
Directory /workspace/17.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/17.lc_ctrl_smoke.1104018912
Short name T55
Test name
Test status
Simulation time 64799644 ps
CPU time 1.44 seconds
Started Jun 23 05:07:06 PM PDT 24
Finished Jun 23 05:07:08 PM PDT 24
Peak memory 217760 kb
Host smart-30f8fd7f-e5cd-4887-9622-9e8669d15f79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104018912 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_smoke.1104018912
Directory /workspace/17.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_failure.35797326
Short name T333
Test name
Test status
Simulation time 522351990 ps
CPU time 17.78 seconds
Started Jun 23 05:07:07 PM PDT 24
Finished Jun 23 05:07:25 PM PDT 24
Peak memory 250908 kb
Host smart-74ffb754-f2d7-4279-8abb-89b64467b3be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35797326 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_failure.35797326
Directory /workspace/17.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_post_trans.968170851
Short name T773
Test name
Test status
Simulation time 391260063 ps
CPU time 8.29 seconds
Started Jun 23 05:07:08 PM PDT 24
Finished Jun 23 05:07:16 PM PDT 24
Peak memory 250352 kb
Host smart-cb4fedc1-9e8f-470b-a6c3-128335319c32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968170851 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_post_trans.968170851
Directory /workspace/17.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all.3484599679
Short name T252
Test name
Test status
Simulation time 12906891623 ps
CPU time 111.3 seconds
Started Jun 23 05:07:26 PM PDT 24
Finished Jun 23 05:09:18 PM PDT 24
Peak memory 250936 kb
Host smart-b884548b-eb04-492a-b2eb-fbbc40671984
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484599679 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.lc_ctrl_stress_all.3484599679
Directory /workspace/17.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all_with_rand_reset.1757266843
Short name T654
Test name
Test status
Simulation time 205716701993 ps
CPU time 279.12 seconds
Started Jun 23 05:07:13 PM PDT 24
Finished Jun 23 05:11:53 PM PDT 24
Peak memory 438360 kb
Host smart-bd96fa20-2b3d-4c4d-bbc4-0e738a2b44f5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1757266843 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_stress_all_with_rand_reset.1757266843
Directory /workspace/17.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.lc_ctrl_volatile_unlock_smoke.558590048
Short name T153
Test name
Test status
Simulation time 53544237 ps
CPU time 0.85 seconds
Started Jun 23 05:07:05 PM PDT 24
Finished Jun 23 05:07:07 PM PDT 24
Peak memory 209164 kb
Host smart-2435dcce-4201-49f5-b850-f9f7f1d9affc
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558590048 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ct
rl_volatile_unlock_smoke.558590048
Directory /workspace/17.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_alert_test.1919255949
Short name T668
Test name
Test status
Simulation time 65755171 ps
CPU time 1.1 seconds
Started Jun 23 05:07:13 PM PDT 24
Finished Jun 23 05:07:15 PM PDT 24
Peak memory 208904 kb
Host smart-a613999d-8138-4b1e-880c-5a43198e5320
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919255949 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_alert_test.1919255949
Directory /workspace/18.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.lc_ctrl_errors.2957330286
Short name T506
Test name
Test status
Simulation time 1551723694 ps
CPU time 18.76 seconds
Started Jun 23 05:07:14 PM PDT 24
Finished Jun 23 05:07:33 PM PDT 24
Peak memory 226048 kb
Host smart-4d0bdb0f-e521-47dd-9d98-0c73003db661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957330286 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_errors.2957330286
Directory /workspace/18.lc_ctrl_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_access.1352203168
Short name T862
Test name
Test status
Simulation time 408471441 ps
CPU time 10.17 seconds
Started Jun 23 05:07:13 PM PDT 24
Finished Jun 23 05:07:24 PM PDT 24
Peak memory 217116 kb
Host smart-d73759a2-342b-4f53-9555-708e66ddba5f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352203168 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_access.1352203168
Directory /workspace/18.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_errors.1764298603
Short name T387
Test name
Test status
Simulation time 3953963917 ps
CPU time 57.39 seconds
Started Jun 23 05:07:13 PM PDT 24
Finished Jun 23 05:08:11 PM PDT 24
Peak memory 219004 kb
Host smart-3fa41f67-eaae-42c8-9d3b-33daa7498d01
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764298603 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_e
rrors.1764298603
Directory /workspace/18.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_prog_failure.2593886585
Short name T821
Test name
Test status
Simulation time 921063763 ps
CPU time 7.5 seconds
Started Jun 23 05:07:12 PM PDT 24
Finished Jun 23 05:07:21 PM PDT 24
Peak memory 223096 kb
Host smart-5f4ccd2a-6a88-4265-b21e-79046554b7c1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593886585 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jta
g_prog_failure.2593886585
Directory /workspace/18.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_smoke.2940096155
Short name T741
Test name
Test status
Simulation time 70375366 ps
CPU time 1.77 seconds
Started Jun 23 05:07:23 PM PDT 24
Finished Jun 23 05:07:25 PM PDT 24
Peak memory 217676 kb
Host smart-557eebb6-960a-4dc2-966c-6e4159457509
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940096155 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_smoke
.2940096155
Directory /workspace/18.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_failure.2724867676
Short name T662
Test name
Test status
Simulation time 9956257287 ps
CPU time 46.33 seconds
Started Jun 23 05:07:11 PM PDT 24
Finished Jun 23 05:07:58 PM PDT 24
Peak memory 271840 kb
Host smart-9f2c058c-70a8-46ed-aa77-02fcf16e4205
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724867676 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jt
ag_state_failure.2724867676
Directory /workspace/18.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_post_trans.293193316
Short name T17
Test name
Test status
Simulation time 699211115 ps
CPU time 18.46 seconds
Started Jun 23 05:07:13 PM PDT 24
Finished Jun 23 05:07:33 PM PDT 24
Peak memory 250764 kb
Host smart-cad7c32d-2589-4487-818c-a236f566bff2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293193316 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_
jtag_state_post_trans.293193316
Directory /workspace/18.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_prog_failure.4279080041
Short name T797
Test name
Test status
Simulation time 81303026 ps
CPU time 4.18 seconds
Started Jun 23 05:07:12 PM PDT 24
Finished Jun 23 05:07:17 PM PDT 24
Peak memory 218128 kb
Host smart-8844cd4f-304e-40c3-adaa-62ffcbde26b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4279080041 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_prog_failure.4279080041
Directory /workspace/18.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_mubi.3973380853
Short name T102
Test name
Test status
Simulation time 442557971 ps
CPU time 13.75 seconds
Started Jun 23 05:07:14 PM PDT 24
Finished Jun 23 05:07:28 PM PDT 24
Peak memory 218344 kb
Host smart-ca69e85a-cf09-40a8-b42a-841f78e94e16
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973380853 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_mubi.3973380853
Directory /workspace/18.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_digest.1845568199
Short name T32
Test name
Test status
Simulation time 350556361 ps
CPU time 13.87 seconds
Started Jun 23 05:07:13 PM PDT 24
Finished Jun 23 05:07:28 PM PDT 24
Peak memory 218168 kb
Host smart-878dfe9d-0ccd-4651-b41f-68bd2d99ef04
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845568199 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_d
igest.1845568199
Directory /workspace/18.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_mux.3479365700
Short name T58
Test name
Test status
Simulation time 3982337879 ps
CPU time 8.67 seconds
Started Jun 23 05:07:13 PM PDT 24
Finished Jun 23 05:07:23 PM PDT 24
Peak memory 218316 kb
Host smart-8c5e0e34-34e3-4b7e-8a79-e0c46db691c6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479365700 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_mux.
3479365700
Directory /workspace/18.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/18.lc_ctrl_security_escalation.829505410
Short name T630
Test name
Test status
Simulation time 271136702 ps
CPU time 11.21 seconds
Started Jun 23 05:07:14 PM PDT 24
Finished Jun 23 05:07:26 PM PDT 24
Peak memory 218092 kb
Host smart-2c6e3238-5b8b-44e7-8874-e7006739c791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829505410 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_security_escalation.829505410
Directory /workspace/18.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/18.lc_ctrl_smoke.4290492467
Short name T81
Test name
Test status
Simulation time 17078590 ps
CPU time 1.62 seconds
Started Jun 23 05:07:11 PM PDT 24
Finished Jun 23 05:07:13 PM PDT 24
Peak memory 213688 kb
Host smart-396fa413-c87f-4417-9b01-ea389b803358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290492467 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_smoke.4290492467
Directory /workspace/18.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_failure.4071536073
Short name T156
Test name
Test status
Simulation time 198555828 ps
CPU time 18.95 seconds
Started Jun 23 05:07:11 PM PDT 24
Finished Jun 23 05:07:30 PM PDT 24
Peak memory 250892 kb
Host smart-061b7f84-56f2-4ed1-b834-824beaf872d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071536073 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_failure.4071536073
Directory /workspace/18.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_post_trans.3268440305
Short name T631
Test name
Test status
Simulation time 89892198 ps
CPU time 7 seconds
Started Jun 23 05:07:26 PM PDT 24
Finished Jun 23 05:07:33 PM PDT 24
Peak memory 250452 kb
Host smart-829ba4ad-106d-4bea-880e-85f58a7251cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268440305 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_post_trans.3268440305
Directory /workspace/18.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all.2719567850
Short name T779
Test name
Test status
Simulation time 1919604837 ps
CPU time 37.48 seconds
Started Jun 23 05:07:23 PM PDT 24
Finished Jun 23 05:08:01 PM PDT 24
Peak memory 267268 kb
Host smart-eb3fa503-2510-40b3-9802-71e45d93c1d1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719567850 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.lc_ctrl_stress_all.2719567850
Directory /workspace/18.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all_with_rand_reset.2673087097
Short name T151
Test name
Test status
Simulation time 109075035974 ps
CPU time 842.47 seconds
Started Jun 23 05:07:15 PM PDT 24
Finished Jun 23 05:21:18 PM PDT 24
Peak memory 308288 kb
Host smart-a0b406f5-21b6-41df-adc9-ea36bed27871
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2673087097 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_stress_all_with_rand_reset.2673087097
Directory /workspace/18.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.lc_ctrl_volatile_unlock_smoke.487048604
Short name T425
Test name
Test status
Simulation time 34209610 ps
CPU time 0.73 seconds
Started Jun 23 05:07:13 PM PDT 24
Finished Jun 23 05:07:15 PM PDT 24
Peak memory 207120 kb
Host smart-d22323fc-898b-4833-b09f-dd46a029ffc7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487048604 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ct
rl_volatile_unlock_smoke.487048604
Directory /workspace/18.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_alert_test.136579701
Short name T728
Test name
Test status
Simulation time 26213121 ps
CPU time 0.82 seconds
Started Jun 23 05:07:20 PM PDT 24
Finished Jun 23 05:07:21 PM PDT 24
Peak memory 208708 kb
Host smart-6d346425-c19b-4b1a-bbe6-93ec904d8100
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136579701 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_alert_test.136579701
Directory /workspace/19.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.lc_ctrl_errors.2391100037
Short name T850
Test name
Test status
Simulation time 850163835 ps
CPU time 19.62 seconds
Started Jun 23 05:07:19 PM PDT 24
Finished Jun 23 05:07:39 PM PDT 24
Peak memory 218064 kb
Host smart-bb68cdfd-afc8-48a7-a2e1-17df17f78a4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391100037 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_errors.2391100037
Directory /workspace/19.lc_ctrl_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_access.950562276
Short name T27
Test name
Test status
Simulation time 578169048 ps
CPU time 14.51 seconds
Started Jun 23 05:07:18 PM PDT 24
Finished Jun 23 05:07:33 PM PDT 24
Peak memory 217400 kb
Host smart-12bcf241-3e17-407d-97fb-70f34b1a2c6f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950562276 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_access.950562276
Directory /workspace/19.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_errors.3244002693
Short name T836
Test name
Test status
Simulation time 3392461330 ps
CPU time 26.86 seconds
Started Jun 23 05:07:22 PM PDT 24
Finished Jun 23 05:07:49 PM PDT 24
Peak memory 218436 kb
Host smart-94437742-258d-4d08-b155-5aa462cdc6a9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244002693 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_e
rrors.3244002693
Directory /workspace/19.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_prog_failure.3332916205
Short name T730
Test name
Test status
Simulation time 875942119 ps
CPU time 3.95 seconds
Started Jun 23 05:07:26 PM PDT 24
Finished Jun 23 05:07:30 PM PDT 24
Peak memory 222736 kb
Host smart-c81cdcd1-445c-4e29-ac38-209426dbe466
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332916205 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jta
g_prog_failure.3332916205
Directory /workspace/19.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_smoke.1437701521
Short name T424
Test name
Test status
Simulation time 399691170 ps
CPU time 10.4 seconds
Started Jun 23 05:07:16 PM PDT 24
Finished Jun 23 05:07:26 PM PDT 24
Peak memory 217680 kb
Host smart-919de7f4-75f8-4907-a3ac-7c5f6c20f66f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437701521 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_smoke
.1437701521
Directory /workspace/19.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_failure.1747916701
Short name T91
Test name
Test status
Simulation time 15416327716 ps
CPU time 53.82 seconds
Started Jun 23 05:07:19 PM PDT 24
Finished Jun 23 05:08:13 PM PDT 24
Peak memory 282936 kb
Host smart-e6251e65-f123-4b37-9093-a12d67da807d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747916701 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jt
ag_state_failure.1747916701
Directory /workspace/19.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_post_trans.659197582
Short name T223
Test name
Test status
Simulation time 350219583 ps
CPU time 10.79 seconds
Started Jun 23 05:07:19 PM PDT 24
Finished Jun 23 05:07:30 PM PDT 24
Peak memory 246084 kb
Host smart-133daebc-1988-4746-b328-94f00c73a03f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659197582 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_
jtag_state_post_trans.659197582
Directory /workspace/19.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_prog_failure.3261597022
Short name T319
Test name
Test status
Simulation time 38774423 ps
CPU time 1.56 seconds
Started Jun 23 05:07:17 PM PDT 24
Finished Jun 23 05:07:19 PM PDT 24
Peak memory 221516 kb
Host smart-5f89f47a-7204-4453-a76b-bce20e03f8ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261597022 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_prog_failure.3261597022
Directory /workspace/19.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_mubi.1273979760
Short name T349
Test name
Test status
Simulation time 274848313 ps
CPU time 11.82 seconds
Started Jun 23 05:07:26 PM PDT 24
Finished Jun 23 05:07:38 PM PDT 24
Peak memory 218248 kb
Host smart-124f04ff-4f9c-487a-8212-be7d3c74b42b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273979760 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_mubi.1273979760
Directory /workspace/19.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_digest.67567424
Short name T776
Test name
Test status
Simulation time 1538611867 ps
CPU time 12.79 seconds
Started Jun 23 05:07:17 PM PDT 24
Finished Jun 23 05:07:31 PM PDT 24
Peak memory 218228 kb
Host smart-59e8bf11-46e1-45c6-b4fd-9c6c292623e6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67567424 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_dig
est_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_dig
est.67567424
Directory /workspace/19.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_mux.2577357720
Short name T419
Test name
Test status
Simulation time 665615343 ps
CPU time 10.98 seconds
Started Jun 23 05:07:17 PM PDT 24
Finished Jun 23 05:07:28 PM PDT 24
Peak memory 218160 kb
Host smart-fe4bd322-feb0-4162-80d8-3c74bbdc6633
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577357720 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_mux.
2577357720
Directory /workspace/19.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/19.lc_ctrl_security_escalation.3569555444
Short name T422
Test name
Test status
Simulation time 3070517778 ps
CPU time 11.27 seconds
Started Jun 23 05:07:18 PM PDT 24
Finished Jun 23 05:07:30 PM PDT 24
Peak memory 226116 kb
Host smart-bef6fa0e-f334-464a-b77f-adfc8fc7c987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569555444 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_security_escalation.3569555444
Directory /workspace/19.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/19.lc_ctrl_smoke.2521045931
Short name T812
Test name
Test status
Simulation time 56884927 ps
CPU time 1.09 seconds
Started Jun 23 05:07:14 PM PDT 24
Finished Jun 23 05:07:16 PM PDT 24
Peak memory 213508 kb
Host smart-d1994507-3221-4773-849e-0200e925b3a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2521045931 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_smoke.2521045931
Directory /workspace/19.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_failure.2483799195
Short name T796
Test name
Test status
Simulation time 1016905368 ps
CPU time 23.69 seconds
Started Jun 23 05:07:18 PM PDT 24
Finished Jun 23 05:07:42 PM PDT 24
Peak memory 250912 kb
Host smart-3755acf0-1d2a-48ca-b229-45d6b9c564a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483799195 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_failure.2483799195
Directory /workspace/19.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_post_trans.3784065421
Short name T870
Test name
Test status
Simulation time 312518576 ps
CPU time 7.67 seconds
Started Jun 23 05:07:18 PM PDT 24
Finished Jun 23 05:07:27 PM PDT 24
Peak memory 250856 kb
Host smart-23d4cb83-b5ea-4b8d-925c-c75db433b104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3784065421 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_post_trans.3784065421
Directory /workspace/19.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all.2396104216
Short name T407
Test name
Test status
Simulation time 60849917195 ps
CPU time 290.27 seconds
Started Jun 23 05:07:18 PM PDT 24
Finished Jun 23 05:12:08 PM PDT 24
Peak memory 283200 kb
Host smart-676fdb79-12c7-4c4f-9ce8-e93a9b547f9d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396104216 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.lc_ctrl_stress_all.2396104216
Directory /workspace/19.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.lc_ctrl_volatile_unlock_smoke.733093136
Short name T440
Test name
Test status
Simulation time 86390115 ps
CPU time 1 seconds
Started Jun 23 05:07:12 PM PDT 24
Finished Jun 23 05:07:14 PM PDT 24
Peak memory 211852 kb
Host smart-9d29a71c-65ec-43d4-be06-b27e3b8d0f60
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733093136 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ct
rl_volatile_unlock_smoke.733093136
Directory /workspace/19.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_alert_test.1047564044
Short name T263
Test name
Test status
Simulation time 17256373 ps
CPU time 1.09 seconds
Started Jun 23 05:06:16 PM PDT 24
Finished Jun 23 05:06:18 PM PDT 24
Peak memory 208928 kb
Host smart-07a1e630-2368-4884-80ec-2f9f4f7a6df0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047564044 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_alert_test.1047564044
Directory /workspace/2.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.lc_ctrl_errors.2369066917
Short name T789
Test name
Test status
Simulation time 515239735 ps
CPU time 13.82 seconds
Started Jun 23 05:06:18 PM PDT 24
Finished Jun 23 05:06:33 PM PDT 24
Peak memory 218048 kb
Host smart-61a2080a-c9e5-454b-84c6-320f6c0e5515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369066917 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_errors.2369066917
Directory /workspace/2.lc_ctrl_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_access.1003696462
Short name T581
Test name
Test status
Simulation time 139836176 ps
CPU time 2.55 seconds
Started Jun 23 05:06:17 PM PDT 24
Finished Jun 23 05:06:20 PM PDT 24
Peak memory 217088 kb
Host smart-21274ac1-b955-4cb1-aafa-39e889240c64
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003696462 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_access.1003696462
Directory /workspace/2.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_errors.2741951762
Short name T849
Test name
Test status
Simulation time 8417371655 ps
CPU time 52.55 seconds
Started Jun 23 05:06:18 PM PDT 24
Finished Jun 23 05:07:11 PM PDT 24
Peak memory 218816 kb
Host smart-96c26cff-a4e6-406e-b4f2-75c9e60f4537
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741951762 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_er
rors.2741951762
Directory /workspace/2.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_priority.1763177995
Short name T326
Test name
Test status
Simulation time 1091792267 ps
CPU time 9.41 seconds
Started Jun 23 05:06:20 PM PDT 24
Finished Jun 23 05:06:30 PM PDT 24
Peak memory 217784 kb
Host smart-b23957a6-68f3-443e-8ea0-8c7863ed831c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763177995 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_priority.1
763177995
Directory /workspace/2.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_prog_failure.3652953568
Short name T237
Test name
Test status
Simulation time 2883550036 ps
CPU time 7.22 seconds
Started Jun 23 05:06:16 PM PDT 24
Finished Jun 23 05:06:24 PM PDT 24
Peak memory 224384 kb
Host smart-9e9accdd-a5fc-41ea-8d16-ba219a435032
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652953568 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag
_prog_failure.3652953568
Directory /workspace/2.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_regwen_during_op.1709786748
Short name T230
Test name
Test status
Simulation time 1358448142 ps
CPU time 35.29 seconds
Started Jun 23 05:06:19 PM PDT 24
Finished Jun 23 05:06:55 PM PDT 24
Peak memory 217688 kb
Host smart-053b7bb9-837f-437e-bb70-fe4c9f8fd413
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709786748 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_regwen_during_op.1709786748
Directory /workspace/2.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_smoke.1526769689
Short name T841
Test name
Test status
Simulation time 254549935 ps
CPU time 6.74 seconds
Started Jun 23 05:06:20 PM PDT 24
Finished Jun 23 05:06:27 PM PDT 24
Peak memory 217748 kb
Host smart-a8ace669-c7b2-4d19-a5aa-fafc260b6e27
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526769689 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_smoke.
1526769689
Directory /workspace/2.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_failure.360058836
Short name T6
Test name
Test status
Simulation time 8374225556 ps
CPU time 90.74 seconds
Started Jun 23 05:06:17 PM PDT 24
Finished Jun 23 05:07:49 PM PDT 24
Peak memory 283556 kb
Host smart-af51e521-6ca4-4556-94f7-22c47ce4330d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360058836 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag
_state_failure.360058836
Directory /workspace/2.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_post_trans.1097588211
Short name T642
Test name
Test status
Simulation time 1903013322 ps
CPU time 11.15 seconds
Started Jun 23 05:06:22 PM PDT 24
Finished Jun 23 05:06:33 PM PDT 24
Peak memory 250396 kb
Host smart-b468feb5-45b4-4d52-b501-ee7d78ceef5b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097588211 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_state_post_trans.1097588211
Directory /workspace/2.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_prog_failure.2185530894
Short name T56
Test name
Test status
Simulation time 243280382 ps
CPU time 3.32 seconds
Started Jun 23 05:06:13 PM PDT 24
Finished Jun 23 05:06:17 PM PDT 24
Peak memory 218112 kb
Host smart-c4f51eba-40f4-4115-bdcd-1bc1113fee9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185530894 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_prog_failure.2185530894
Directory /workspace/2.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_digest.733396717
Short name T231
Test name
Test status
Simulation time 2753858983 ps
CPU time 12.46 seconds
Started Jun 23 05:06:22 PM PDT 24
Finished Jun 23 05:06:35 PM PDT 24
Peak memory 218296 kb
Host smart-1541c5ff-5d34-4c9d-87ca-f379dd04816d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733396717 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_dig
est.733396717
Directory /workspace/2.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_mux.1351009803
Short name T655
Test name
Test status
Simulation time 3024760652 ps
CPU time 10.87 seconds
Started Jun 23 05:06:18 PM PDT 24
Finished Jun 23 05:06:30 PM PDT 24
Peak memory 218248 kb
Host smart-7c803f48-3c64-484e-bd0f-21ffabe7043f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351009803 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_mux.1
351009803
Directory /workspace/2.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/2.lc_ctrl_security_escalation.3554434087
Short name T434
Test name
Test status
Simulation time 2404473868 ps
CPU time 14.43 seconds
Started Jun 23 05:06:16 PM PDT 24
Finished Jun 23 05:06:31 PM PDT 24
Peak memory 226096 kb
Host smart-cf499878-b577-43c2-ad9e-7e95de321ef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554434087 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_security_escalation.3554434087
Directory /workspace/2.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/2.lc_ctrl_smoke.1201713675
Short name T53
Test name
Test status
Simulation time 43403683 ps
CPU time 2.14 seconds
Started Jun 23 05:06:13 PM PDT 24
Finished Jun 23 05:06:16 PM PDT 24
Peak memory 217736 kb
Host smart-5cf81592-8e29-48d5-b0f9-92979801e043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201713675 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_smoke.1201713675
Directory /workspace/2.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_failure.1814940182
Short name T650
Test name
Test status
Simulation time 779811891 ps
CPU time 21.36 seconds
Started Jun 23 05:06:12 PM PDT 24
Finished Jun 23 05:06:34 PM PDT 24
Peak memory 250824 kb
Host smart-67605fed-156a-4969-a45c-cc158e20811f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814940182 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_failure.1814940182
Directory /workspace/2.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_post_trans.2969317215
Short name T828
Test name
Test status
Simulation time 158016285 ps
CPU time 8.19 seconds
Started Jun 23 05:06:11 PM PDT 24
Finished Jun 23 05:06:20 PM PDT 24
Peak memory 242608 kb
Host smart-4559a91a-2863-432b-99d8-6b314b663059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969317215 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_post_trans.2969317215
Directory /workspace/2.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all.2731316600
Short name T802
Test name
Test status
Simulation time 1282770414 ps
CPU time 29.75 seconds
Started Jun 23 05:06:17 PM PDT 24
Finished Jun 23 05:06:47 PM PDT 24
Peak memory 250344 kb
Host smart-22856516-55a4-4a9a-a38f-adda94718124
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731316600 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.lc_ctrl_stress_all.2731316600
Directory /workspace/2.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.lc_ctrl_volatile_unlock_smoke.3371342131
Short name T496
Test name
Test status
Simulation time 12504831 ps
CPU time 0.96 seconds
Started Jun 23 05:06:12 PM PDT 24
Finished Jun 23 05:06:14 PM PDT 24
Peak memory 208656 kb
Host smart-dfceabb0-a737-4da2-ab6b-cb36fc6e4b71
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371342131 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ct
rl_volatile_unlock_smoke.3371342131
Directory /workspace/2.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_alert_test.4105449359
Short name T87
Test name
Test status
Simulation time 55626635 ps
CPU time 0.88 seconds
Started Jun 23 05:07:24 PM PDT 24
Finished Jun 23 05:07:26 PM PDT 24
Peak memory 209024 kb
Host smart-ea46aa92-bf81-48bc-987a-f9545e654569
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105449359 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_alert_test.4105449359
Directory /workspace/20.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.lc_ctrl_errors.1659778972
Short name T371
Test name
Test status
Simulation time 219116266 ps
CPU time 8.54 seconds
Started Jun 23 05:07:24 PM PDT 24
Finished Jun 23 05:07:33 PM PDT 24
Peak memory 218232 kb
Host smart-a229976b-1bc1-4282-8bc8-fe3fa1fad169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659778972 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_errors.1659778972
Directory /workspace/20.lc_ctrl_errors/latest

Test location /workspace/coverage/default/20.lc_ctrl_jtag_access.4028919677
Short name T798
Test name
Test status
Simulation time 2260820985 ps
CPU time 3.86 seconds
Started Jun 23 05:07:27 PM PDT 24
Finished Jun 23 05:07:32 PM PDT 24
Peak memory 217344 kb
Host smart-25e6cd24-782b-4dfe-9b8c-a12c5826f7b0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028919677 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_jtag_access.4028919677
Directory /workspace/20.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/20.lc_ctrl_prog_failure.52066545
Short name T192
Test name
Test status
Simulation time 58078150 ps
CPU time 3.13 seconds
Started Jun 23 05:07:25 PM PDT 24
Finished Jun 23 05:07:29 PM PDT 24
Peak memory 222500 kb
Host smart-900645e8-64fe-4956-aece-4d2914e9d796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52066545 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_prog_failure.52066545
Directory /workspace/20.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_mubi.1500956788
Short name T158
Test name
Test status
Simulation time 547836204 ps
CPU time 21.49 seconds
Started Jun 23 05:07:25 PM PDT 24
Finished Jun 23 05:07:48 PM PDT 24
Peak memory 225980 kb
Host smart-64a35bd2-9b3d-447c-9228-6f999ffea4e2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500956788 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_mubi.1500956788
Directory /workspace/20.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_digest.3478874203
Short name T239
Test name
Test status
Simulation time 1074276094 ps
CPU time 11.14 seconds
Started Jun 23 05:07:25 PM PDT 24
Finished Jun 23 05:07:37 PM PDT 24
Peak memory 225980 kb
Host smart-07dccca2-445b-474b-a491-f59420940d0a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478874203 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_d
igest.3478874203
Directory /workspace/20.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_mux.2243235592
Short name T693
Test name
Test status
Simulation time 277052598 ps
CPU time 11.63 seconds
Started Jun 23 05:07:26 PM PDT 24
Finished Jun 23 05:07:38 PM PDT 24
Peak memory 218228 kb
Host smart-bfde8812-28f8-4206-b5a9-e2928ddb062c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243235592 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_mux.
2243235592
Directory /workspace/20.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/20.lc_ctrl_security_escalation.1610661249
Short name T794
Test name
Test status
Simulation time 627117071 ps
CPU time 12.43 seconds
Started Jun 23 05:07:24 PM PDT 24
Finished Jun 23 05:07:37 PM PDT 24
Peak memory 226068 kb
Host smart-fbef01f2-2fc6-46d9-802e-a13dbf1444ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1610661249 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_security_escalation.1610661249
Directory /workspace/20.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/20.lc_ctrl_smoke.1136315012
Short name T505
Test name
Test status
Simulation time 105742993 ps
CPU time 3.21 seconds
Started Jun 23 05:07:25 PM PDT 24
Finished Jun 23 05:07:29 PM PDT 24
Peak memory 214684 kb
Host smart-a5b9880f-2320-4704-af24-613f02d33cb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136315012 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_smoke.1136315012
Directory /workspace/20.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_failure.2408413276
Short name T49
Test name
Test status
Simulation time 369128523 ps
CPU time 35.12 seconds
Started Jun 23 05:07:23 PM PDT 24
Finished Jun 23 05:07:59 PM PDT 24
Peak memory 250848 kb
Host smart-589adb93-a1f5-4113-9421-7c8ff4d42e6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408413276 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_failure.2408413276
Directory /workspace/20.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_post_trans.142615885
Short name T767
Test name
Test status
Simulation time 49782554 ps
CPU time 8.89 seconds
Started Jun 23 05:07:24 PM PDT 24
Finished Jun 23 05:07:34 PM PDT 24
Peak memory 250904 kb
Host smart-f3a6facd-8963-4132-a56e-3f2ef5c98e4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142615885 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_post_trans.142615885
Directory /workspace/20.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/20.lc_ctrl_stress_all.238994018
Short name T90
Test name
Test status
Simulation time 22735375533 ps
CPU time 192.1 seconds
Started Jun 23 05:07:26 PM PDT 24
Finished Jun 23 05:10:39 PM PDT 24
Peak memory 447444 kb
Host smart-d19a4d2c-3606-4a92-861b-9c26fb66a27c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238994018 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.lc_ctrl_stress_all.238994018
Directory /workspace/20.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.lc_ctrl_stress_all_with_rand_reset.2395512152
Short name T152
Test name
Test status
Simulation time 7037339070 ps
CPU time 171.65 seconds
Started Jun 23 05:07:26 PM PDT 24
Finished Jun 23 05:10:18 PM PDT 24
Peak memory 279464 kb
Host smart-7e405527-0d53-4117-b88f-0dc4ba12e4ad
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2395512152 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_stress_all_with_rand_reset.2395512152
Directory /workspace/20.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.lc_ctrl_volatile_unlock_smoke.362553626
Short name T103
Test name
Test status
Simulation time 41935366 ps
CPU time 0.98 seconds
Started Jun 23 05:07:24 PM PDT 24
Finished Jun 23 05:07:25 PM PDT 24
Peak memory 211940 kb
Host smart-c17aa586-3c45-4361-b27c-891153967387
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362553626 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ct
rl_volatile_unlock_smoke.362553626
Directory /workspace/20.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_alert_test.3582270227
Short name T545
Test name
Test status
Simulation time 14002080 ps
CPU time 1.02 seconds
Started Jun 23 05:07:35 PM PDT 24
Finished Jun 23 05:07:37 PM PDT 24
Peak memory 209040 kb
Host smart-a836397b-0a2f-45cd-84a6-4dc14a38d9bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582270227 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_alert_test.3582270227
Directory /workspace/21.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.lc_ctrl_errors.669809754
Short name T384
Test name
Test status
Simulation time 1761568385 ps
CPU time 11.52 seconds
Started Jun 23 05:07:35 PM PDT 24
Finished Jun 23 05:07:47 PM PDT 24
Peak memory 218228 kb
Host smart-b7f83c70-a02e-4b2c-b6ec-a4ac87f371f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669809754 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_errors.669809754
Directory /workspace/21.lc_ctrl_errors/latest

Test location /workspace/coverage/default/21.lc_ctrl_jtag_access.4021137248
Short name T26
Test name
Test status
Simulation time 570131983 ps
CPU time 8.21 seconds
Started Jun 23 05:07:36 PM PDT 24
Finished Jun 23 05:07:45 PM PDT 24
Peak memory 217500 kb
Host smart-4a4b717c-b9e9-4ea9-b09f-475dec525d70
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021137248 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_jtag_access.4021137248
Directory /workspace/21.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/21.lc_ctrl_prog_failure.4234282204
Short name T536
Test name
Test status
Simulation time 492734776 ps
CPU time 2.61 seconds
Started Jun 23 05:07:26 PM PDT 24
Finished Jun 23 05:07:30 PM PDT 24
Peak memory 218160 kb
Host smart-eb6a2c08-4060-42dd-8e57-43228437f354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234282204 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_prog_failure.4234282204
Directory /workspace/21.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_mubi.900559575
Short name T586
Test name
Test status
Simulation time 505891879 ps
CPU time 8.42 seconds
Started Jun 23 05:07:37 PM PDT 24
Finished Jun 23 05:07:46 PM PDT 24
Peak memory 218340 kb
Host smart-0ec70a2d-5a9b-41a5-982a-4c9b53e3cddf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900559575 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_mubi.900559575
Directory /workspace/21.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_digest.1656251630
Short name T353
Test name
Test status
Simulation time 378367893 ps
CPU time 7.22 seconds
Started Jun 23 05:07:41 PM PDT 24
Finished Jun 23 05:07:49 PM PDT 24
Peak memory 218244 kb
Host smart-d1630a37-a880-4265-8f08-c2b715a6049a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656251630 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_d
igest.1656251630
Directory /workspace/21.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_mux.2890082892
Short name T596
Test name
Test status
Simulation time 1249877118 ps
CPU time 12.19 seconds
Started Jun 23 05:07:37 PM PDT 24
Finished Jun 23 05:07:50 PM PDT 24
Peak memory 225972 kb
Host smart-1de42800-518d-4e40-9a7d-5eb8155cbad9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890082892 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_mux.
2890082892
Directory /workspace/21.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/21.lc_ctrl_security_escalation.1329380667
Short name T745
Test name
Test status
Simulation time 496957975 ps
CPU time 17.07 seconds
Started Jun 23 05:07:37 PM PDT 24
Finished Jun 23 05:07:55 PM PDT 24
Peak memory 218256 kb
Host smart-3844dbb7-ebbd-4570-8855-94f9a9ab4362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329380667 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_security_escalation.1329380667
Directory /workspace/21.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/21.lc_ctrl_smoke.645719948
Short name T238
Test name
Test status
Simulation time 653752700 ps
CPU time 4.41 seconds
Started Jun 23 05:07:24 PM PDT 24
Finished Jun 23 05:07:29 PM PDT 24
Peak memory 217760 kb
Host smart-82311a12-7759-4aff-b2ad-afa35cd8fad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645719948 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_smoke.645719948
Directory /workspace/21.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_failure.1699815943
Short name T432
Test name
Test status
Simulation time 560195459 ps
CPU time 18.78 seconds
Started Jun 23 05:07:24 PM PDT 24
Finished Jun 23 05:07:44 PM PDT 24
Peak memory 250840 kb
Host smart-b6c8ba3b-0440-43af-aabe-2b2821d40db0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699815943 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_failure.1699815943
Directory /workspace/21.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_post_trans.3809685072
Short name T332
Test name
Test status
Simulation time 128752712 ps
CPU time 2.86 seconds
Started Jun 23 05:07:27 PM PDT 24
Finished Jun 23 05:07:30 PM PDT 24
Peak memory 226260 kb
Host smart-7ab51475-bb7b-4547-be8f-861817f1b1b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809685072 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_post_trans.3809685072
Directory /workspace/21.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/21.lc_ctrl_stress_all.4164759274
Short name T462
Test name
Test status
Simulation time 6324776111 ps
CPU time 25.21 seconds
Started Jun 23 05:07:34 PM PDT 24
Finished Jun 23 05:07:59 PM PDT 24
Peak memory 226120 kb
Host smart-a0efa89f-07e8-4fa0-a151-44aa4dd3b785
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164759274 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.lc_ctrl_stress_all.4164759274
Directory /workspace/21.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.lc_ctrl_volatile_unlock_smoke.3157930657
Short name T248
Test name
Test status
Simulation time 84670360 ps
CPU time 1.08 seconds
Started Jun 23 05:07:24 PM PDT 24
Finished Jun 23 05:07:26 PM PDT 24
Peak memory 217696 kb
Host smart-f3eeb94f-accb-484f-bb18-6deb4a3c641c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157930657 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_c
trl_volatile_unlock_smoke.3157930657
Directory /workspace/21.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_alert_test.3506910439
Short name T233
Test name
Test status
Simulation time 251165850 ps
CPU time 1.06 seconds
Started Jun 23 05:07:39 PM PDT 24
Finished Jun 23 05:07:41 PM PDT 24
Peak memory 208928 kb
Host smart-2421d3ec-6914-4be4-9280-8f22f118b9a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506910439 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_alert_test.3506910439
Directory /workspace/22.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.lc_ctrl_errors.4202619412
Short name T481
Test name
Test status
Simulation time 607272893 ps
CPU time 14.4 seconds
Started Jun 23 05:07:34 PM PDT 24
Finished Jun 23 05:07:49 PM PDT 24
Peak memory 218232 kb
Host smart-0134c52c-c03b-4e8e-bf98-f57603fe0757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202619412 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_errors.4202619412
Directory /workspace/22.lc_ctrl_errors/latest

Test location /workspace/coverage/default/22.lc_ctrl_jtag_access.1900026380
Short name T719
Test name
Test status
Simulation time 1184957760 ps
CPU time 4.26 seconds
Started Jun 23 05:07:42 PM PDT 24
Finished Jun 23 05:07:47 PM PDT 24
Peak memory 217228 kb
Host smart-c45fa342-a339-44b3-bad8-05e5ef424555
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900026380 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_jtag_access.1900026380
Directory /workspace/22.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/22.lc_ctrl_prog_failure.1308535396
Short name T423
Test name
Test status
Simulation time 44344689 ps
CPU time 2.17 seconds
Started Jun 23 05:07:36 PM PDT 24
Finished Jun 23 05:07:38 PM PDT 24
Peak memory 218188 kb
Host smart-03b1c1e9-5612-43b0-9932-b07f569d4c06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308535396 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_prog_failure.1308535396
Directory /workspace/22.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_mubi.808879176
Short name T37
Test name
Test status
Simulation time 810670445 ps
CPU time 8.65 seconds
Started Jun 23 05:07:41 PM PDT 24
Finished Jun 23 05:07:50 PM PDT 24
Peak memory 218832 kb
Host smart-3a6e8aab-3846-420f-a6e5-9b112b750930
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808879176 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_mubi.808879176
Directory /workspace/22.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_digest.3180214536
Short name T681
Test name
Test status
Simulation time 499424059 ps
CPU time 13.24 seconds
Started Jun 23 05:07:41 PM PDT 24
Finished Jun 23 05:07:55 PM PDT 24
Peak memory 225980 kb
Host smart-300c3bbc-aa70-4d48-9b8c-1d874ffae831
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180214536 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_d
igest.3180214536
Directory /workspace/22.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_mux.4169652520
Short name T644
Test name
Test status
Simulation time 1772655692 ps
CPU time 11.88 seconds
Started Jun 23 05:07:40 PM PDT 24
Finished Jun 23 05:07:53 PM PDT 24
Peak memory 226068 kb
Host smart-ed93fa45-18e8-4338-8973-ca0aa4adc895
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169652520 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_mux.
4169652520
Directory /workspace/22.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/22.lc_ctrl_security_escalation.1135828362
Short name T284
Test name
Test status
Simulation time 1232720870 ps
CPU time 10.27 seconds
Started Jun 23 05:07:35 PM PDT 24
Finished Jun 23 05:07:46 PM PDT 24
Peak memory 225368 kb
Host smart-ac7ded21-5418-4a5d-9102-c6a47ebbdbdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135828362 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_security_escalation.1135828362
Directory /workspace/22.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/22.lc_ctrl_smoke.1778408679
Short name T345
Test name
Test status
Simulation time 23245516 ps
CPU time 1.94 seconds
Started Jun 23 05:07:37 PM PDT 24
Finished Jun 23 05:07:40 PM PDT 24
Peak memory 214268 kb
Host smart-56c62111-e0c4-41ad-9dc3-29d695cb37d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778408679 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_smoke.1778408679
Directory /workspace/22.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_failure.2239992343
Short name T572
Test name
Test status
Simulation time 1133462864 ps
CPU time 31.42 seconds
Started Jun 23 05:07:35 PM PDT 24
Finished Jun 23 05:08:07 PM PDT 24
Peak memory 250900 kb
Host smart-b85b3959-95b3-4f07-8267-0825ff0f8ebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239992343 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_failure.2239992343
Directory /workspace/22.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_post_trans.4079623313
Short name T787
Test name
Test status
Simulation time 260571629 ps
CPU time 3.01 seconds
Started Jun 23 05:07:35 PM PDT 24
Finished Jun 23 05:07:39 PM PDT 24
Peak memory 226300 kb
Host smart-a83bfa9a-459b-4855-8613-f37504489424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079623313 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_post_trans.4079623313
Directory /workspace/22.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/22.lc_ctrl_stress_all.2021700155
Short name T861
Test name
Test status
Simulation time 4120369625 ps
CPU time 90.91 seconds
Started Jun 23 05:07:37 PM PDT 24
Finished Jun 23 05:09:09 PM PDT 24
Peak memory 252884 kb
Host smart-1649f37f-482a-4a8f-a47f-159282df274b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021700155 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.lc_ctrl_stress_all.2021700155
Directory /workspace/22.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.lc_ctrl_volatile_unlock_smoke.3218666038
Short name T170
Test name
Test status
Simulation time 26453325 ps
CPU time 1.08 seconds
Started Jun 23 05:07:35 PM PDT 24
Finished Jun 23 05:07:37 PM PDT 24
Peak memory 211980 kb
Host smart-9e76d8e5-ac73-4a45-ae70-f4522bfa0707
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218666038 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_c
trl_volatile_unlock_smoke.3218666038
Directory /workspace/22.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_errors.544991611
Short name T582
Test name
Test status
Simulation time 1022742320 ps
CPU time 12.65 seconds
Started Jun 23 05:07:41 PM PDT 24
Finished Jun 23 05:07:54 PM PDT 24
Peak memory 218184 kb
Host smart-8607def7-527c-4734-8edc-13605e1b7b1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544991611 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_errors.544991611
Directory /workspace/23.lc_ctrl_errors/latest

Test location /workspace/coverage/default/23.lc_ctrl_jtag_access.3123388588
Short name T453
Test name
Test status
Simulation time 258310614 ps
CPU time 3.57 seconds
Started Jun 23 05:07:41 PM PDT 24
Finished Jun 23 05:07:45 PM PDT 24
Peak memory 217272 kb
Host smart-6c0837f1-baf6-4177-90a8-9ea63edb8eca
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123388588 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_jtag_access.3123388588
Directory /workspace/23.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/23.lc_ctrl_prog_failure.2274047589
Short name T559
Test name
Test status
Simulation time 180964497 ps
CPU time 2.27 seconds
Started Jun 23 05:07:37 PM PDT 24
Finished Jun 23 05:07:40 PM PDT 24
Peak memory 218128 kb
Host smart-f4e1093c-6198-42cc-82f0-edc74befcb8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274047589 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_prog_failure.2274047589
Directory /workspace/23.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_mubi.2181002273
Short name T618
Test name
Test status
Simulation time 1377573162 ps
CPU time 9.83 seconds
Started Jun 23 05:07:42 PM PDT 24
Finished Jun 23 05:07:53 PM PDT 24
Peak memory 218332 kb
Host smart-d51a4241-b588-4880-8188-98d88b98864f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181002273 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_mubi.2181002273
Directory /workspace/23.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_digest.2496198547
Short name T563
Test name
Test status
Simulation time 363977743 ps
CPU time 11.77 seconds
Started Jun 23 05:07:42 PM PDT 24
Finished Jun 23 05:07:54 PM PDT 24
Peak memory 218272 kb
Host smart-7c9064c1-563b-4042-8170-800ab7ceaf19
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496198547 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_d
igest.2496198547
Directory /workspace/23.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_mux.1257465506
Short name T626
Test name
Test status
Simulation time 351999580 ps
CPU time 6.5 seconds
Started Jun 23 05:07:44 PM PDT 24
Finished Jun 23 05:07:52 PM PDT 24
Peak memory 218260 kb
Host smart-8ffd6406-2819-4b0e-a65f-de669ffa47c9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257465506 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_mux.
1257465506
Directory /workspace/23.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/23.lc_ctrl_security_escalation.3046177401
Short name T399
Test name
Test status
Simulation time 281272778 ps
CPU time 11.57 seconds
Started Jun 23 05:07:38 PM PDT 24
Finished Jun 23 05:07:51 PM PDT 24
Peak memory 225952 kb
Host smart-c8888151-a8dd-4b71-bd41-87c448059851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046177401 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_security_escalation.3046177401
Directory /workspace/23.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/23.lc_ctrl_smoke.1803591429
Short name T805
Test name
Test status
Simulation time 28990411 ps
CPU time 2.12 seconds
Started Jun 23 05:07:39 PM PDT 24
Finished Jun 23 05:07:42 PM PDT 24
Peak memory 214368 kb
Host smart-684a3cf9-0101-4135-b352-69cc28cc3a53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803591429 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_smoke.1803591429
Directory /workspace/23.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_failure.958491809
Short name T269
Test name
Test status
Simulation time 557436355 ps
CPU time 32.2 seconds
Started Jun 23 05:07:38 PM PDT 24
Finished Jun 23 05:08:11 PM PDT 24
Peak memory 251044 kb
Host smart-f7fe4920-ca34-4c52-b269-ad25df8aad6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958491809 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_failure.958491809
Directory /workspace/23.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_post_trans.4190011496
Short name T782
Test name
Test status
Simulation time 257734586 ps
CPU time 7.11 seconds
Started Jun 23 05:07:37 PM PDT 24
Finished Jun 23 05:07:45 PM PDT 24
Peak memory 250804 kb
Host smart-0e7b4902-0cdd-409e-a87d-d995abffb2dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190011496 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_post_trans.4190011496
Directory /workspace/23.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all.3267219783
Short name T351
Test name
Test status
Simulation time 42005382439 ps
CPU time 204.91 seconds
Started Jun 23 05:07:42 PM PDT 24
Finished Jun 23 05:11:08 PM PDT 24
Peak memory 314424 kb
Host smart-d0cc1f06-273d-41f6-b1ed-09d44811fed5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267219783 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.lc_ctrl_stress_all.3267219783
Directory /workspace/23.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.lc_ctrl_volatile_unlock_smoke.2418003101
Short name T259
Test name
Test status
Simulation time 21980783 ps
CPU time 0.87 seconds
Started Jun 23 05:07:40 PM PDT 24
Finished Jun 23 05:07:42 PM PDT 24
Peak memory 208636 kb
Host smart-52b1185d-a318-4d8d-9a65-d26d9bf3facd
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418003101 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_c
trl_volatile_unlock_smoke.2418003101
Directory /workspace/23.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_alert_test.1691082563
Short name T552
Test name
Test status
Simulation time 38292540 ps
CPU time 1.04 seconds
Started Jun 23 05:07:49 PM PDT 24
Finished Jun 23 05:07:51 PM PDT 24
Peak memory 209032 kb
Host smart-ec263691-c861-49f3-90c0-c1d5dc4d4ead
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691082563 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_alert_test.1691082563
Directory /workspace/24.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.lc_ctrl_errors.3302929416
Short name T874
Test name
Test status
Simulation time 1492521857 ps
CPU time 26.61 seconds
Started Jun 23 05:07:45 PM PDT 24
Finished Jun 23 05:08:12 PM PDT 24
Peak memory 218232 kb
Host smart-31372543-368d-4592-bc80-7ccc44209b9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302929416 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_errors.3302929416
Directory /workspace/24.lc_ctrl_errors/latest

Test location /workspace/coverage/default/24.lc_ctrl_jtag_access.1681918734
Short name T8
Test name
Test status
Simulation time 6721858786 ps
CPU time 18.78 seconds
Started Jun 23 05:07:43 PM PDT 24
Finished Jun 23 05:08:03 PM PDT 24
Peak memory 217716 kb
Host smart-1c47bb8d-d664-4175-a9b0-994f0ee90c9e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681918734 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_jtag_access.1681918734
Directory /workspace/24.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/24.lc_ctrl_prog_failure.3297001017
Short name T365
Test name
Test status
Simulation time 72026355 ps
CPU time 3.35 seconds
Started Jun 23 05:07:45 PM PDT 24
Finished Jun 23 05:07:49 PM PDT 24
Peak memory 218228 kb
Host smart-f03f1c79-c412-4fd6-8500-85d87ef02ff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297001017 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_prog_failure.3297001017
Directory /workspace/24.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_mubi.3613380818
Short name T334
Test name
Test status
Simulation time 1010435882 ps
CPU time 9.44 seconds
Started Jun 23 05:07:47 PM PDT 24
Finished Jun 23 05:07:57 PM PDT 24
Peak memory 218832 kb
Host smart-475504ba-ac4b-45c9-bbbb-5448f653a561
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613380818 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_mubi.3613380818
Directory /workspace/24.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_digest.1200538099
Short name T603
Test name
Test status
Simulation time 1108750099 ps
CPU time 9.82 seconds
Started Jun 23 05:07:44 PM PDT 24
Finished Jun 23 05:07:55 PM PDT 24
Peak memory 226080 kb
Host smart-04f0875a-b5d5-496a-92d1-0650a505cc94
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200538099 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_d
igest.1200538099
Directory /workspace/24.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/24.lc_ctrl_security_escalation.1652240589
Short name T266
Test name
Test status
Simulation time 1789273174 ps
CPU time 10.69 seconds
Started Jun 23 05:07:43 PM PDT 24
Finished Jun 23 05:07:55 PM PDT 24
Peak memory 218284 kb
Host smart-0c17122d-698e-4bdd-b696-aaa8a5783392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652240589 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_security_escalation.1652240589
Directory /workspace/24.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/24.lc_ctrl_smoke.2058511506
Short name T246
Test name
Test status
Simulation time 149961682 ps
CPU time 3.67 seconds
Started Jun 23 05:07:43 PM PDT 24
Finished Jun 23 05:07:48 PM PDT 24
Peak memory 214620 kb
Host smart-d539f593-3063-474a-b1a0-a7e440503847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058511506 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_smoke.2058511506
Directory /workspace/24.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_failure.1642655332
Short name T696
Test name
Test status
Simulation time 331805599 ps
CPU time 25.07 seconds
Started Jun 23 05:07:45 PM PDT 24
Finished Jun 23 05:08:11 PM PDT 24
Peak memory 250912 kb
Host smart-e3aaf379-60c9-4592-83e8-b6033a4b0adb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642655332 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_failure.1642655332
Directory /workspace/24.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_post_trans.4277485640
Short name T372
Test name
Test status
Simulation time 102264192 ps
CPU time 7.39 seconds
Started Jun 23 05:07:42 PM PDT 24
Finished Jun 23 05:07:51 PM PDT 24
Peak memory 250876 kb
Host smart-3781b380-fcfd-447f-8fe7-5fc6674f419a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277485640 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_post_trans.4277485640
Directory /workspace/24.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all.4268972786
Short name T77
Test name
Test status
Simulation time 27589750167 ps
CPU time 118.24 seconds
Started Jun 23 05:07:44 PM PDT 24
Finished Jun 23 05:09:44 PM PDT 24
Peak memory 283692 kb
Host smart-54c54037-7944-4e81-9770-12665db09bd7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268972786 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.lc_ctrl_stress_all.4268972786
Directory /workspace/24.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all_with_rand_reset.3573101930
Short name T111
Test name
Test status
Simulation time 19899895908 ps
CPU time 356.11 seconds
Started Jun 23 05:07:44 PM PDT 24
Finished Jun 23 05:13:41 PM PDT 24
Peak memory 277636 kb
Host smart-754e4e1b-508a-4864-85cd-795fc40ebb42
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3573101930 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_stress_all_with_rand_reset.3573101930
Directory /workspace/24.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.lc_ctrl_volatile_unlock_smoke.920034518
Short name T285
Test name
Test status
Simulation time 14102907 ps
CPU time 1.09 seconds
Started Jun 23 05:07:52 PM PDT 24
Finished Jun 23 05:07:54 PM PDT 24
Peak memory 211800 kb
Host smart-8fa0f5c9-878d-45cd-b016-7286e9e9968a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920034518 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ct
rl_volatile_unlock_smoke.920034518
Directory /workspace/24.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_alert_test.3399495365
Short name T737
Test name
Test status
Simulation time 40003464 ps
CPU time 0.83 seconds
Started Jun 23 05:07:57 PM PDT 24
Finished Jun 23 05:07:59 PM PDT 24
Peak memory 208708 kb
Host smart-3afc38ba-50cd-479d-815a-5cffef4f854e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399495365 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_alert_test.3399495365
Directory /workspace/25.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.lc_ctrl_errors.4037359180
Short name T679
Test name
Test status
Simulation time 1345418398 ps
CPU time 10.9 seconds
Started Jun 23 05:07:52 PM PDT 24
Finished Jun 23 05:08:04 PM PDT 24
Peak memory 218188 kb
Host smart-c1b024c8-6d21-47a1-8082-98b58f91f214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037359180 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_errors.4037359180
Directory /workspace/25.lc_ctrl_errors/latest

Test location /workspace/coverage/default/25.lc_ctrl_jtag_access.1254081300
Short name T25
Test name
Test status
Simulation time 1493740956 ps
CPU time 5.47 seconds
Started Jun 23 05:07:52 PM PDT 24
Finished Jun 23 05:07:59 PM PDT 24
Peak memory 217256 kb
Host smart-65d7c92c-e48d-4f9f-8355-bda0a9d1104b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254081300 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_jtag_access.1254081300
Directory /workspace/25.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/25.lc_ctrl_prog_failure.3288925170
Short name T258
Test name
Test status
Simulation time 438788721 ps
CPU time 4.71 seconds
Started Jun 23 05:07:51 PM PDT 24
Finished Jun 23 05:07:57 PM PDT 24
Peak memory 218176 kb
Host smart-98fb32aa-52ce-4c85-b23e-d8ddd3c36226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288925170 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_prog_failure.3288925170
Directory /workspace/25.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_mubi.3381356486
Short name T295
Test name
Test status
Simulation time 319498480 ps
CPU time 11.65 seconds
Started Jun 23 05:07:51 PM PDT 24
Finished Jun 23 05:08:04 PM PDT 24
Peak memory 226008 kb
Host smart-69807912-ec65-4117-a49a-e23662ae6e74
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381356486 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_mubi.3381356486
Directory /workspace/25.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_digest.2529944226
Short name T520
Test name
Test status
Simulation time 536553872 ps
CPU time 9.38 seconds
Started Jun 23 05:07:51 PM PDT 24
Finished Jun 23 05:08:01 PM PDT 24
Peak memory 218192 kb
Host smart-46b5cfe8-e830-42b2-89fd-a01e8f2ba729
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529944226 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_d
igest.2529944226
Directory /workspace/25.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_mux.3285512469
Short name T786
Test name
Test status
Simulation time 231018488 ps
CPU time 8.71 seconds
Started Jun 23 05:07:52 PM PDT 24
Finished Jun 23 05:08:02 PM PDT 24
Peak memory 225116 kb
Host smart-d67d673d-7322-47a1-bd40-1288783e47bb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285512469 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_mux.
3285512469
Directory /workspace/25.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/25.lc_ctrl_security_escalation.46616649
Short name T404
Test name
Test status
Simulation time 213265339 ps
CPU time 8.52 seconds
Started Jun 23 05:07:53 PM PDT 24
Finished Jun 23 05:08:02 PM PDT 24
Peak memory 218232 kb
Host smart-d824a335-d116-4961-8d8b-87a5dc8a59fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46616649 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_security_escalation.46616649
Directory /workspace/25.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/25.lc_ctrl_smoke.545764638
Short name T75
Test name
Test status
Simulation time 21341380 ps
CPU time 1.45 seconds
Started Jun 23 05:07:49 PM PDT 24
Finished Jun 23 05:07:52 PM PDT 24
Peak memory 213616 kb
Host smart-73696452-d0b9-485b-b10e-d15bd86d8fcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545764638 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_smoke.545764638
Directory /workspace/25.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_failure.2529223574
Short name T762
Test name
Test status
Simulation time 1288578216 ps
CPU time 32.07 seconds
Started Jun 23 05:07:50 PM PDT 24
Finished Jun 23 05:08:24 PM PDT 24
Peak memory 250812 kb
Host smart-b4961b66-5227-4d4a-a8a8-5326b397fbce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529223574 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_failure.2529223574
Directory /workspace/25.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_post_trans.3334668401
Short name T314
Test name
Test status
Simulation time 66545951 ps
CPU time 3.84 seconds
Started Jun 23 05:07:51 PM PDT 24
Finished Jun 23 05:07:56 PM PDT 24
Peak memory 222708 kb
Host smart-bd43a0a0-aaa1-4812-a5c1-fd6e304b82a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334668401 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_post_trans.3334668401
Directory /workspace/25.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/25.lc_ctrl_stress_all.207567296
Short name T671
Test name
Test status
Simulation time 20680809646 ps
CPU time 696.69 seconds
Started Jun 23 05:07:59 PM PDT 24
Finished Jun 23 05:19:37 PM PDT 24
Peak memory 267376 kb
Host smart-7d1f5d50-6a8f-44d5-aa27-aa0c1c7f88b1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207567296 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.lc_ctrl_stress_all.207567296
Directory /workspace/25.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.lc_ctrl_volatile_unlock_smoke.1046144768
Short name T755
Test name
Test status
Simulation time 16270514 ps
CPU time 0.94 seconds
Started Jun 23 05:07:53 PM PDT 24
Finished Jun 23 05:07:55 PM PDT 24
Peak memory 211876 kb
Host smart-c401b17e-cb77-4bc8-bd49-2c6eba8bf82b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046144768 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_c
trl_volatile_unlock_smoke.1046144768
Directory /workspace/25.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_alert_test.1247399154
Short name T791
Test name
Test status
Simulation time 335454004 ps
CPU time 0.9 seconds
Started Jun 23 05:07:57 PM PDT 24
Finished Jun 23 05:07:59 PM PDT 24
Peak memory 209012 kb
Host smart-aacd8487-25c6-443e-ba11-8884d9fd8fe9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247399154 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_alert_test.1247399154
Directory /workspace/26.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.lc_ctrl_errors.1306103410
Short name T663
Test name
Test status
Simulation time 707917431 ps
CPU time 12.79 seconds
Started Jun 23 05:07:57 PM PDT 24
Finished Jun 23 05:08:10 PM PDT 24
Peak memory 218208 kb
Host smart-53e8d0cd-e871-47c6-a349-62f71a7ed5e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306103410 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_errors.1306103410
Directory /workspace/26.lc_ctrl_errors/latest

Test location /workspace/coverage/default/26.lc_ctrl_jtag_access.2010773712
Short name T653
Test name
Test status
Simulation time 6156157013 ps
CPU time 13.55 seconds
Started Jun 23 05:07:58 PM PDT 24
Finished Jun 23 05:08:12 PM PDT 24
Peak memory 217736 kb
Host smart-f2b1a1de-3e18-4f5c-997d-d55b23b86cd2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010773712 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_jtag_access.2010773712
Directory /workspace/26.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/26.lc_ctrl_prog_failure.1557758715
Short name T3
Test name
Test status
Simulation time 93694663 ps
CPU time 2.86 seconds
Started Jun 23 05:07:58 PM PDT 24
Finished Jun 23 05:08:02 PM PDT 24
Peak memory 218216 kb
Host smart-928e0e7a-c6d9-4427-9022-5adc6d8ad479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557758715 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_prog_failure.1557758715
Directory /workspace/26.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_mubi.183128907
Short name T556
Test name
Test status
Simulation time 1323902859 ps
CPU time 11.92 seconds
Started Jun 23 05:07:59 PM PDT 24
Finished Jun 23 05:08:11 PM PDT 24
Peak memory 218892 kb
Host smart-088bf10e-f5b1-4f6d-95c5-36cdad16513c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183128907 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_mubi.183128907
Directory /workspace/26.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_digest.704051196
Short name T549
Test name
Test status
Simulation time 561180325 ps
CPU time 15.64 seconds
Started Jun 23 05:07:57 PM PDT 24
Finished Jun 23 05:08:14 PM PDT 24
Peak memory 225980 kb
Host smart-2092ec7a-807e-40f5-b62c-f98d1187158a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704051196 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_di
gest.704051196
Directory /workspace/26.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_mux.217966476
Short name T464
Test name
Test status
Simulation time 1209983697 ps
CPU time 12.39 seconds
Started Jun 23 05:08:03 PM PDT 24
Finished Jun 23 05:08:16 PM PDT 24
Peak memory 218300 kb
Host smart-536313be-87ce-4a7b-81e2-88de0b0424ba
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217966476 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_mux.217966476
Directory /workspace/26.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/26.lc_ctrl_security_escalation.3608575121
Short name T865
Test name
Test status
Simulation time 461010384 ps
CPU time 10.47 seconds
Started Jun 23 05:07:57 PM PDT 24
Finished Jun 23 05:08:08 PM PDT 24
Peak memory 226056 kb
Host smart-0a485ba2-a969-4f5b-b0d7-d6f688894b8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608575121 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_security_escalation.3608575121
Directory /workspace/26.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/26.lc_ctrl_smoke.3759954618
Short name T522
Test name
Test status
Simulation time 171678416 ps
CPU time 5.42 seconds
Started Jun 23 05:07:57 PM PDT 24
Finished Jun 23 05:08:04 PM PDT 24
Peak memory 217756 kb
Host smart-76d79037-dd04-44b5-b836-4808a7ef0604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759954618 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_smoke.3759954618
Directory /workspace/26.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_failure.4143329792
Short name T747
Test name
Test status
Simulation time 698231990 ps
CPU time 26.51 seconds
Started Jun 23 05:07:57 PM PDT 24
Finished Jun 23 05:08:25 PM PDT 24
Peak memory 250980 kb
Host smart-3a955bf8-913d-495f-9d0a-11fe02a4921b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143329792 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_failure.4143329792
Directory /workspace/26.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_post_trans.2051640617
Short name T652
Test name
Test status
Simulation time 74147709 ps
CPU time 6.57 seconds
Started Jun 23 05:07:57 PM PDT 24
Finished Jun 23 05:08:04 PM PDT 24
Peak memory 250468 kb
Host smart-1c40888a-433f-4feb-a681-dde56230b472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051640617 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_post_trans.2051640617
Directory /workspace/26.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all.4173880157
Short name T396
Test name
Test status
Simulation time 39839035609 ps
CPU time 296.18 seconds
Started Jun 23 05:07:56 PM PDT 24
Finished Jun 23 05:12:54 PM PDT 24
Peak memory 496668 kb
Host smart-f65d94ba-91ae-478c-adbc-498665b26491
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173880157 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.lc_ctrl_stress_all.4173880157
Directory /workspace/26.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all_with_rand_reset.785684455
Short name T40
Test name
Test status
Simulation time 22748447271 ps
CPU time 762.28 seconds
Started Jun 23 05:07:57 PM PDT 24
Finished Jun 23 05:20:41 PM PDT 24
Peak memory 283752 kb
Host smart-6118286f-0fbf-459c-bb1b-652cd15e21a1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=785684455 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_stress_all_with_rand_reset.785684455
Directory /workspace/26.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.lc_ctrl_volatile_unlock_smoke.2851796415
Short name T427
Test name
Test status
Simulation time 13004068 ps
CPU time 0.96 seconds
Started Jun 23 05:07:58 PM PDT 24
Finished Jun 23 05:08:00 PM PDT 24
Peak memory 209224 kb
Host smart-c95c73b2-ba2b-471e-82ea-2142114cbe0e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851796415 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_c
trl_volatile_unlock_smoke.2851796415
Directory /workspace/26.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_alert_test.3287415761
Short name T240
Test name
Test status
Simulation time 24289934 ps
CPU time 0.9 seconds
Started Jun 23 05:08:03 PM PDT 24
Finished Jun 23 05:08:05 PM PDT 24
Peak memory 208868 kb
Host smart-695ec466-5654-4627-a87e-9cf699dba148
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287415761 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_alert_test.3287415761
Directory /workspace/27.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.lc_ctrl_errors.3216093674
Short name T592
Test name
Test status
Simulation time 2827879106 ps
CPU time 17.82 seconds
Started Jun 23 05:08:04 PM PDT 24
Finished Jun 23 05:08:23 PM PDT 24
Peak memory 218892 kb
Host smart-670865cc-ef1f-4bda-a3ac-78389fdb2ff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216093674 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_errors.3216093674
Directory /workspace/27.lc_ctrl_errors/latest

Test location /workspace/coverage/default/27.lc_ctrl_jtag_access.1745777883
Short name T489
Test name
Test status
Simulation time 51116544 ps
CPU time 2.03 seconds
Started Jun 23 05:08:03 PM PDT 24
Finished Jun 23 05:08:07 PM PDT 24
Peak memory 217168 kb
Host smart-a4a65b60-80ec-47c0-855a-7915dcca53d7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745777883 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_jtag_access.1745777883
Directory /workspace/27.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/27.lc_ctrl_prog_failure.2743729006
Short name T722
Test name
Test status
Simulation time 145158239 ps
CPU time 3.72 seconds
Started Jun 23 05:08:03 PM PDT 24
Finished Jun 23 05:08:08 PM PDT 24
Peak memory 218156 kb
Host smart-af44a2e1-1e1f-4136-a321-3d2dd8ff108e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743729006 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_prog_failure.2743729006
Directory /workspace/27.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_mubi.2914923441
Short name T807
Test name
Test status
Simulation time 2415534028 ps
CPU time 14.75 seconds
Started Jun 23 05:08:06 PM PDT 24
Finished Jun 23 05:08:22 PM PDT 24
Peak memory 220108 kb
Host smart-d3ca9ddd-0dc9-4650-826e-6a1e3f2665d7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914923441 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_mubi.2914923441
Directory /workspace/27.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_digest.1933582512
Short name T562
Test name
Test status
Simulation time 265944661 ps
CPU time 9.42 seconds
Started Jun 23 05:08:04 PM PDT 24
Finished Jun 23 05:08:14 PM PDT 24
Peak memory 218244 kb
Host smart-c78f0794-d854-44af-81bf-db7a99d4d6e2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933582512 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_d
igest.1933582512
Directory /workspace/27.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_mux.642427961
Short name T822
Test name
Test status
Simulation time 726814621 ps
CPU time 8.2 seconds
Started Jun 23 05:08:06 PM PDT 24
Finished Jun 23 05:08:15 PM PDT 24
Peak memory 225472 kb
Host smart-28e57ed1-35ca-47a3-ae96-1c2e2ed4c5f1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642427961 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_mux.642427961
Directory /workspace/27.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/27.lc_ctrl_security_escalation.4152034955
Short name T695
Test name
Test status
Simulation time 1314158094 ps
CPU time 11.2 seconds
Started Jun 23 05:08:07 PM PDT 24
Finished Jun 23 05:08:19 PM PDT 24
Peak memory 226144 kb
Host smart-2cc2d6cb-8652-4217-878e-88bbfee3af4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152034955 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_security_escalation.4152034955
Directory /workspace/27.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/27.lc_ctrl_smoke.575476228
Short name T635
Test name
Test status
Simulation time 384776231 ps
CPU time 2.5 seconds
Started Jun 23 05:07:56 PM PDT 24
Finished Jun 23 05:07:59 PM PDT 24
Peak memory 214328 kb
Host smart-ab747649-8d9f-433e-a64c-4f2c3677a18f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575476228 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_smoke.575476228
Directory /workspace/27.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_failure.988029643
Short name T304
Test name
Test status
Simulation time 968572877 ps
CPU time 25.8 seconds
Started Jun 23 05:08:05 PM PDT 24
Finished Jun 23 05:08:31 PM PDT 24
Peak memory 250904 kb
Host smart-07a0b663-0d6b-42e4-9f1b-8ce3791966be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988029643 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_failure.988029643
Directory /workspace/27.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_post_trans.4173170962
Short name T352
Test name
Test status
Simulation time 451236599 ps
CPU time 6.9 seconds
Started Jun 23 05:08:03 PM PDT 24
Finished Jun 23 05:08:11 PM PDT 24
Peak memory 246924 kb
Host smart-c5aa7561-71d1-4399-a682-2d24a7b211b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173170962 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_post_trans.4173170962
Directory /workspace/27.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all.51614963
Short name T54
Test name
Test status
Simulation time 19179635992 ps
CPU time 95.67 seconds
Started Jun 23 05:08:04 PM PDT 24
Finished Jun 23 05:09:41 PM PDT 24
Peak memory 270048 kb
Host smart-50ee41d9-c1e9-4f97-9d03-9a142d94af2a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51614963 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_T
EST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
7.lc_ctrl_stress_all.51614963
Directory /workspace/27.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.lc_ctrl_volatile_unlock_smoke.2304999375
Short name T347
Test name
Test status
Simulation time 25889783 ps
CPU time 1.1 seconds
Started Jun 23 05:08:05 PM PDT 24
Finished Jun 23 05:08:07 PM PDT 24
Peak memory 212000 kb
Host smart-6db0cb0b-ab91-41ef-bd5f-0e0bc0f69c9b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304999375 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_c
trl_volatile_unlock_smoke.2304999375
Directory /workspace/27.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_alert_test.2834382553
Short name T765
Test name
Test status
Simulation time 150124358 ps
CPU time 0.98 seconds
Started Jun 23 05:08:11 PM PDT 24
Finished Jun 23 05:08:13 PM PDT 24
Peak memory 209024 kb
Host smart-ba18c9f8-c421-4cf9-be44-6532cc6c3691
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834382553 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_alert_test.2834382553
Directory /workspace/28.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.lc_ctrl_errors.3402040618
Short name T590
Test name
Test status
Simulation time 261538166 ps
CPU time 9.76 seconds
Started Jun 23 05:08:06 PM PDT 24
Finished Jun 23 05:08:17 PM PDT 24
Peak memory 218140 kb
Host smart-f2fda8a2-17b6-4db8-b428-2896c9159a79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402040618 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_errors.3402040618
Directory /workspace/28.lc_ctrl_errors/latest

Test location /workspace/coverage/default/28.lc_ctrl_jtag_access.1323021080
Short name T2
Test name
Test status
Simulation time 1275997375 ps
CPU time 16.51 seconds
Started Jun 23 05:08:14 PM PDT 24
Finished Jun 23 05:08:32 PM PDT 24
Peak memory 217612 kb
Host smart-37c80c97-c3d8-47d1-b7bf-c000ad1963ac
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323021080 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_jtag_access.1323021080
Directory /workspace/28.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/28.lc_ctrl_prog_failure.3793344358
Short name T736
Test name
Test status
Simulation time 50711967 ps
CPU time 3.18 seconds
Started Jun 23 05:08:05 PM PDT 24
Finished Jun 23 05:08:09 PM PDT 24
Peak memory 218160 kb
Host smart-547544b3-d848-4e8b-b448-ed8bfd2aa704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793344358 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_prog_failure.3793344358
Directory /workspace/28.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_mubi.1761827630
Short name T306
Test name
Test status
Simulation time 1428688732 ps
CPU time 16.01 seconds
Started Jun 23 05:08:14 PM PDT 24
Finished Jun 23 05:08:31 PM PDT 24
Peak memory 218932 kb
Host smart-9bc590f3-3937-439d-beca-79cddbd93796
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761827630 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_mubi.1761827630
Directory /workspace/28.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_digest.1750191716
Short name T154
Test name
Test status
Simulation time 266515334 ps
CPU time 12.82 seconds
Started Jun 23 05:08:11 PM PDT 24
Finished Jun 23 05:08:24 PM PDT 24
Peak memory 218172 kb
Host smart-5e1a54e8-db71-43bb-ad20-c6777bb66eea
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750191716 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_d
igest.1750191716
Directory /workspace/28.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_mux.2742951014
Short name T623
Test name
Test status
Simulation time 597137836 ps
CPU time 10.55 seconds
Started Jun 23 05:08:10 PM PDT 24
Finished Jun 23 05:08:21 PM PDT 24
Peak memory 218264 kb
Host smart-efb83c2c-a57b-42f9-8869-09efea99896f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742951014 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_mux.
2742951014
Directory /workspace/28.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/28.lc_ctrl_security_escalation.1559079391
Short name T367
Test name
Test status
Simulation time 335200469 ps
CPU time 8.79 seconds
Started Jun 23 05:08:13 PM PDT 24
Finished Jun 23 05:08:23 PM PDT 24
Peak memory 224796 kb
Host smart-289e91a3-35ee-417c-8e93-9919ab6650d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559079391 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_security_escalation.1559079391
Directory /workspace/28.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/28.lc_ctrl_smoke.2392989871
Short name T397
Test name
Test status
Simulation time 64264579 ps
CPU time 2.93 seconds
Started Jun 23 05:08:04 PM PDT 24
Finished Jun 23 05:08:08 PM PDT 24
Peak memory 214756 kb
Host smart-34433e8f-a399-4616-aaea-814685290462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392989871 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_smoke.2392989871
Directory /workspace/28.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_failure.939657245
Short name T491
Test name
Test status
Simulation time 381272058 ps
CPU time 18.32 seconds
Started Jun 23 05:08:03 PM PDT 24
Finished Jun 23 05:08:22 PM PDT 24
Peak memory 250776 kb
Host smart-d395e152-d45f-4d55-aba2-b2f63f90246f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939657245 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_failure.939657245
Directory /workspace/28.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_post_trans.4080941000
Short name T255
Test name
Test status
Simulation time 75797952 ps
CPU time 7.4 seconds
Started Jun 23 05:08:08 PM PDT 24
Finished Jun 23 05:08:16 PM PDT 24
Peak memory 250912 kb
Host smart-56cd2276-3bce-420e-a1d4-ab10a5391e6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080941000 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_post_trans.4080941000
Directory /workspace/28.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/28.lc_ctrl_stress_all.1155625637
Short name T617
Test name
Test status
Simulation time 260789922 ps
CPU time 25.11 seconds
Started Jun 23 05:08:13 PM PDT 24
Finished Jun 23 05:08:40 PM PDT 24
Peak memory 247292 kb
Host smart-16b33776-46e9-4ad6-bed3-80ac4980ce63
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155625637 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.lc_ctrl_stress_all.1155625637
Directory /workspace/28.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.lc_ctrl_stress_all_with_rand_reset.4106706430
Short name T684
Test name
Test status
Simulation time 129678545429 ps
CPU time 302.4 seconds
Started Jun 23 05:08:12 PM PDT 24
Finished Jun 23 05:13:16 PM PDT 24
Peak memory 227788 kb
Host smart-fe71f73f-2cd5-4b86-ac50-429802d2e771
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4106706430 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_stress_all_with_rand_reset.4106706430
Directory /workspace/28.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.lc_ctrl_volatile_unlock_smoke.2142365912
Short name T627
Test name
Test status
Simulation time 45210641 ps
CPU time 0.8 seconds
Started Jun 23 05:08:05 PM PDT 24
Finished Jun 23 05:08:07 PM PDT 24
Peak memory 209112 kb
Host smart-141880d9-d305-4d2c-823c-7cce7dce8b43
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142365912 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_c
trl_volatile_unlock_smoke.2142365912
Directory /workspace/28.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_alert_test.2889017423
Short name T829
Test name
Test status
Simulation time 95328569 ps
CPU time 0.95 seconds
Started Jun 23 05:08:19 PM PDT 24
Finished Jun 23 05:08:21 PM PDT 24
Peak memory 208928 kb
Host smart-be5a2e06-5b34-4c7a-8724-1826845f79c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889017423 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_alert_test.2889017423
Directory /workspace/29.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.lc_ctrl_errors.4292555247
Short name T554
Test name
Test status
Simulation time 268658475 ps
CPU time 12.32 seconds
Started Jun 23 05:08:12 PM PDT 24
Finished Jun 23 05:08:27 PM PDT 24
Peak memory 218236 kb
Host smart-4e4042bd-8b69-4f66-b8bb-bec81b10ec82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292555247 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_errors.4292555247
Directory /workspace/29.lc_ctrl_errors/latest

Test location /workspace/coverage/default/29.lc_ctrl_jtag_access.435827689
Short name T750
Test name
Test status
Simulation time 520579161 ps
CPU time 5.23 seconds
Started Jun 23 05:08:12 PM PDT 24
Finished Jun 23 05:08:19 PM PDT 24
Peak memory 217392 kb
Host smart-a2663efa-f502-4cf7-8261-90b6b7d3155e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435827689 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_jtag_access.435827689
Directory /workspace/29.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/29.lc_ctrl_prog_failure.1560562180
Short name T503
Test name
Test status
Simulation time 189095039 ps
CPU time 3.08 seconds
Started Jun 23 05:08:14 PM PDT 24
Finished Jun 23 05:08:18 PM PDT 24
Peak memory 222800 kb
Host smart-d75eaa27-bf10-4241-9ae1-fbb0b30390c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560562180 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_prog_failure.1560562180
Directory /workspace/29.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_mubi.330748564
Short name T51
Test name
Test status
Simulation time 2576160526 ps
CPU time 12.77 seconds
Started Jun 23 05:08:13 PM PDT 24
Finished Jun 23 05:08:28 PM PDT 24
Peak memory 218328 kb
Host smart-77bb641a-1f04-4b1f-9eb0-1cc2e3a4d913
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330748564 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_mubi.330748564
Directory /workspace/29.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_digest.1396815393
Short name T817
Test name
Test status
Simulation time 912448081 ps
CPU time 8.68 seconds
Started Jun 23 05:08:17 PM PDT 24
Finished Jun 23 05:08:27 PM PDT 24
Peak memory 218268 kb
Host smart-65e4c2bd-dd15-4e6d-8efd-8eb50ac55083
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396815393 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_d
igest.1396815393
Directory /workspace/29.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_mux.1939735818
Short name T612
Test name
Test status
Simulation time 1002576570 ps
CPU time 10.69 seconds
Started Jun 23 05:08:11 PM PDT 24
Finished Jun 23 05:08:22 PM PDT 24
Peak memory 218260 kb
Host smart-6767b538-d0a4-42ad-831f-1ff515549494
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939735818 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_mux.
1939735818
Directory /workspace/29.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/29.lc_ctrl_security_escalation.485230990
Short name T346
Test name
Test status
Simulation time 653409637 ps
CPU time 12.8 seconds
Started Jun 23 05:08:10 PM PDT 24
Finished Jun 23 05:08:23 PM PDT 24
Peak memory 226068 kb
Host smart-55490b75-2e03-4eb8-bbfb-64fa61e3db8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485230990 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_security_escalation.485230990
Directory /workspace/29.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/29.lc_ctrl_smoke.1724012333
Short name T601
Test name
Test status
Simulation time 43830697 ps
CPU time 3.16 seconds
Started Jun 23 05:08:14 PM PDT 24
Finished Jun 23 05:08:19 PM PDT 24
Peak memory 214532 kb
Host smart-e6c154b3-534f-4373-b85b-2028145e0bc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724012333 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_smoke.1724012333
Directory /workspace/29.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_failure.310464304
Short name T241
Test name
Test status
Simulation time 1198350649 ps
CPU time 28.4 seconds
Started Jun 23 05:08:15 PM PDT 24
Finished Jun 23 05:08:44 PM PDT 24
Peak memory 250884 kb
Host smart-1745b922-79bd-4c77-95d1-c5c063012452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310464304 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_failure.310464304
Directory /workspace/29.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_post_trans.1511250486
Short name T720
Test name
Test status
Simulation time 229701214 ps
CPU time 3.09 seconds
Started Jun 23 05:08:11 PM PDT 24
Finished Jun 23 05:08:15 PM PDT 24
Peak memory 222500 kb
Host smart-7bcb45d1-9a87-4627-a1e3-a5126030bcf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511250486 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_post_trans.1511250486
Directory /workspace/29.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/29.lc_ctrl_stress_all.4184922741
Short name T421
Test name
Test status
Simulation time 3762407233 ps
CPU time 90.9 seconds
Started Jun 23 05:08:18 PM PDT 24
Finished Jun 23 05:09:49 PM PDT 24
Peak memory 250904 kb
Host smart-bffd009e-ce12-4fa4-a006-ce86184eb9ba
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184922741 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.lc_ctrl_stress_all.4184922741
Directory /workspace/29.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.lc_ctrl_volatile_unlock_smoke.4158602396
Short name T594
Test name
Test status
Simulation time 13629085 ps
CPU time 1.06 seconds
Started Jun 23 05:08:10 PM PDT 24
Finished Jun 23 05:08:11 PM PDT 24
Peak memory 209048 kb
Host smart-2c27d994-cd09-4b64-bc1c-a75eb1a29cc7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158602396 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_c
trl_volatile_unlock_smoke.4158602396
Directory /workspace/29.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_alert_test.212744798
Short name T472
Test name
Test status
Simulation time 66650296 ps
CPU time 0.97 seconds
Started Jun 23 05:06:23 PM PDT 24
Finished Jun 23 05:06:25 PM PDT 24
Peak memory 209048 kb
Host smart-bc1c105e-fe01-4402-8225-b2195ab2789b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212744798 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_alert_test.212744798
Directory /workspace/3.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.lc_ctrl_claim_transition_if.1602424117
Short name T406
Test name
Test status
Simulation time 33357180 ps
CPU time 0.85 seconds
Started Jun 23 05:06:17 PM PDT 24
Finished Jun 23 05:06:19 PM PDT 24
Peak memory 208784 kb
Host smart-738fa512-0434-4bc9-be42-386d30e52b56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602424117 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_claim_transition_if.1602424117
Directory /workspace/3.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/3.lc_ctrl_errors.3556146314
Short name T872
Test name
Test status
Simulation time 3200477525 ps
CPU time 18.4 seconds
Started Jun 23 05:06:16 PM PDT 24
Finished Jun 23 05:06:35 PM PDT 24
Peak memory 225992 kb
Host smart-2234ec02-448b-4254-9d48-3577fd8bd4af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556146314 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_errors.3556146314
Directory /workspace/3.lc_ctrl_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_access.1604189049
Short name T584
Test name
Test status
Simulation time 370262864 ps
CPU time 3.25 seconds
Started Jun 23 05:06:21 PM PDT 24
Finished Jun 23 05:06:25 PM PDT 24
Peak memory 217188 kb
Host smart-c011b428-eb79-44de-a934-cd3c5d4cc21e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604189049 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_access.1604189049
Directory /workspace/3.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_errors.333585026
Short name T774
Test name
Test status
Simulation time 1938647392 ps
CPU time 53.38 seconds
Started Jun 23 05:06:18 PM PDT 24
Finished Jun 23 05:07:12 PM PDT 24
Peak memory 226016 kb
Host smart-9a616d8e-6644-4a8c-9bd4-448d0aa67ca2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333585026 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_err
ors.333585026
Directory /workspace/3.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_priority.1326786892
Short name T172
Test name
Test status
Simulation time 4911409019 ps
CPU time 11.64 seconds
Started Jun 23 05:06:16 PM PDT 24
Finished Jun 23 05:06:28 PM PDT 24
Peak memory 217836 kb
Host smart-a9711cfe-04f1-4017-bf73-ab7fdb505071
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326786892 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_priority.1
326786892
Directory /workspace/3.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_prog_failure.1999746861
Short name T289
Test name
Test status
Simulation time 672847144 ps
CPU time 18.28 seconds
Started Jun 23 05:06:18 PM PDT 24
Finished Jun 23 05:06:37 PM PDT 24
Peak memory 218188 kb
Host smart-02efc1ef-c41a-4d5a-9b27-c238f1476e8f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999746861 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag
_prog_failure.1999746861
Directory /workspace/3.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_regwen_during_op.1478955620
Short name T80
Test name
Test status
Simulation time 670662373 ps
CPU time 11.14 seconds
Started Jun 23 05:06:19 PM PDT 24
Finished Jun 23 05:06:31 PM PDT 24
Peak memory 217644 kb
Host smart-3ccfcad2-87f0-4bd4-bd61-785b3615a378
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478955620 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_regwen_during_op.1478955620
Directory /workspace/3.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_smoke.3755457120
Short name T267
Test name
Test status
Simulation time 2933015125 ps
CPU time 7.87 seconds
Started Jun 23 05:06:19 PM PDT 24
Finished Jun 23 05:06:28 PM PDT 24
Peak memory 217648 kb
Host smart-e8b54e37-9f13-43d0-a89d-4857605db26d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755457120 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_smoke.
3755457120
Directory /workspace/3.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_failure.2506896952
Short name T283
Test name
Test status
Simulation time 41644003797 ps
CPU time 131.51 seconds
Started Jun 23 05:06:20 PM PDT 24
Finished Jun 23 05:08:32 PM PDT 24
Peak memory 283720 kb
Host smart-32083962-d11d-4897-91c5-de9781309dce
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506896952 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jta
g_state_failure.2506896952
Directory /workspace/3.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_post_trans.480100462
Short name T325
Test name
Test status
Simulation time 1877222345 ps
CPU time 9.1 seconds
Started Jun 23 05:06:17 PM PDT 24
Finished Jun 23 05:06:26 PM PDT 24
Peak memory 226248 kb
Host smart-4ba5908f-f8da-41ef-aae2-0591250ff131
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480100462 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_j
tag_state_post_trans.480100462
Directory /workspace/3.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_prog_failure.646435083
Short name T455
Test name
Test status
Simulation time 280316926 ps
CPU time 2.49 seconds
Started Jun 23 05:06:21 PM PDT 24
Finished Jun 23 05:06:24 PM PDT 24
Peak memory 222404 kb
Host smart-a3f0cd7f-760b-4138-8dc0-57d95ba75a95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646435083 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_prog_failure.646435083
Directory /workspace/3.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_regwen_during_op.504930003
Short name T382
Test name
Test status
Simulation time 239963040 ps
CPU time 8.75 seconds
Started Jun 23 05:06:19 PM PDT 24
Finished Jun 23 05:06:28 PM PDT 24
Peak memory 217652 kb
Host smart-54826e81-dc70-4a6f-a419-d5ba7894fbab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504930003 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_regwen_during_op.504930003
Directory /workspace/3.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_cm.3977996974
Short name T44
Test name
Test status
Simulation time 641006634 ps
CPU time 36.7 seconds
Started Jun 23 05:06:22 PM PDT 24
Finished Jun 23 05:06:59 PM PDT 24
Peak memory 269524 kb
Host smart-0636d62b-765c-4c44-a45d-2b23ec1bce0d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977996974 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_cm.3977996974
Directory /workspace/3.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_mubi.2518869866
Short name T732
Test name
Test status
Simulation time 464649838 ps
CPU time 12.5 seconds
Started Jun 23 05:06:18 PM PDT 24
Finished Jun 23 05:06:31 PM PDT 24
Peak memory 225888 kb
Host smart-e783a904-2c8d-4ddd-b988-835bb48b38a9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518869866 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_mubi.2518869866
Directory /workspace/3.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_digest.2479120192
Short name T640
Test name
Test status
Simulation time 454388054 ps
CPU time 16.84 seconds
Started Jun 23 05:06:23 PM PDT 24
Finished Jun 23 05:06:40 PM PDT 24
Peak memory 218268 kb
Host smart-314ac037-a0f5-4cd5-b6df-67945000e815
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479120192 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_di
gest.2479120192
Directory /workspace/3.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_mux.2133816074
Short name T620
Test name
Test status
Simulation time 729901702 ps
CPU time 12.1 seconds
Started Jun 23 05:06:20 PM PDT 24
Finished Jun 23 05:06:33 PM PDT 24
Peak memory 218092 kb
Host smart-97da0e6c-7738-4b72-84e2-239490ad7a52
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133816074 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_mux.2
133816074
Directory /workspace/3.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/3.lc_ctrl_security_escalation.1581993568
Short name T733
Test name
Test status
Simulation time 773100249 ps
CPU time 9.44 seconds
Started Jun 23 05:06:18 PM PDT 24
Finished Jun 23 05:06:29 PM PDT 24
Peak memory 226036 kb
Host smart-a61d0aaf-44b8-461c-8d80-1a74d245a27f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581993568 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_security_escalation.1581993568
Directory /workspace/3.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/3.lc_ctrl_smoke.1680773336
Short name T526
Test name
Test status
Simulation time 147136431 ps
CPU time 2.91 seconds
Started Jun 23 05:06:18 PM PDT 24
Finished Jun 23 05:06:22 PM PDT 24
Peak memory 214976 kb
Host smart-920baf22-792a-428c-bb10-688aa59d5fdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680773336 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_smoke.1680773336
Directory /workspace/3.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_failure.2146704397
Short name T517
Test name
Test status
Simulation time 914217216 ps
CPU time 32.82 seconds
Started Jun 23 05:06:19 PM PDT 24
Finished Jun 23 05:06:53 PM PDT 24
Peak memory 250800 kb
Host smart-38304097-611f-40d9-ad48-3370c644493c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146704397 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_failure.2146704397
Directory /workspace/3.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_post_trans.1153747281
Short name T758
Test name
Test status
Simulation time 95244018 ps
CPU time 7.83 seconds
Started Jun 23 05:06:20 PM PDT 24
Finished Jun 23 05:06:28 PM PDT 24
Peak memory 250896 kb
Host smart-b44ecb0c-1df4-4b29-b79b-ce6c7b1165d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153747281 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_post_trans.1153747281
Directory /workspace/3.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_stress_all.3266994502
Short name T89
Test name
Test status
Simulation time 8898600266 ps
CPU time 32.03 seconds
Started Jun 23 05:06:22 PM PDT 24
Finished Jun 23 05:06:55 PM PDT 24
Peak memory 226124 kb
Host smart-d1149457-c795-4634-92b9-e54f26a0a2be
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266994502 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.lc_ctrl_stress_all.3266994502
Directory /workspace/3.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.lc_ctrl_volatile_unlock_smoke.3701563313
Short name T485
Test name
Test status
Simulation time 27634886 ps
CPU time 1.22 seconds
Started Jun 23 05:06:20 PM PDT 24
Finished Jun 23 05:06:22 PM PDT 24
Peak memory 213032 kb
Host smart-8cac5fec-c946-481c-b20a-710affccd958
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701563313 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ct
rl_volatile_unlock_smoke.3701563313
Directory /workspace/3.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_alert_test.2656634416
Short name T604
Test name
Test status
Simulation time 84926386 ps
CPU time 0.97 seconds
Started Jun 23 05:08:16 PM PDT 24
Finished Jun 23 05:08:17 PM PDT 24
Peak memory 209128 kb
Host smart-8e6f9d1a-cac2-4c28-93a2-64835539c8ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656634416 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_alert_test.2656634416
Directory /workspace/30.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.lc_ctrl_errors.163723148
Short name T677
Test name
Test status
Simulation time 2015929147 ps
CPU time 16.28 seconds
Started Jun 23 05:08:25 PM PDT 24
Finished Jun 23 05:08:42 PM PDT 24
Peak memory 218148 kb
Host smart-1d3845f8-029c-4cdd-a925-1d988ecc5330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163723148 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_errors.163723148
Directory /workspace/30.lc_ctrl_errors/latest

Test location /workspace/coverage/default/30.lc_ctrl_jtag_access.2434403477
Short name T378
Test name
Test status
Simulation time 1021538221 ps
CPU time 7.21 seconds
Started Jun 23 05:08:22 PM PDT 24
Finished Jun 23 05:08:30 PM PDT 24
Peak memory 217444 kb
Host smart-4e4d5dd7-3ccc-4911-98e7-10872b87e2ef
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434403477 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_jtag_access.2434403477
Directory /workspace/30.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/30.lc_ctrl_prog_failure.75056663
Short name T323
Test name
Test status
Simulation time 483418986 ps
CPU time 3.11 seconds
Started Jun 23 05:08:20 PM PDT 24
Finished Jun 23 05:08:24 PM PDT 24
Peak memory 218196 kb
Host smart-ea4c453a-86ea-4f20-b231-fbf041d1c90a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75056663 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_prog_failure.75056663
Directory /workspace/30.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_mubi.4176961899
Short name T290
Test name
Test status
Simulation time 1963324783 ps
CPU time 12.52 seconds
Started Jun 23 05:08:23 PM PDT 24
Finished Jun 23 05:08:36 PM PDT 24
Peak memory 226008 kb
Host smart-567ce130-0f62-4375-ace7-1cfc98bec8f2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176961899 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_mubi.4176961899
Directory /workspace/30.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_digest.2806641811
Short name T577
Test name
Test status
Simulation time 419854716 ps
CPU time 16.35 seconds
Started Jun 23 05:08:16 PM PDT 24
Finished Jun 23 05:08:33 PM PDT 24
Peak memory 226080 kb
Host smart-55295a1d-73be-4c4e-8b33-5ff8119f3b75
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806641811 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_d
igest.2806641811
Directory /workspace/30.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_mux.1290746764
Short name T321
Test name
Test status
Simulation time 1135749049 ps
CPU time 10.71 seconds
Started Jun 23 05:08:17 PM PDT 24
Finished Jun 23 05:08:28 PM PDT 24
Peak memory 218336 kb
Host smart-f7fc61c3-c33d-444b-95fb-fce801f26ca7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290746764 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_mux.
1290746764
Directory /workspace/30.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/30.lc_ctrl_security_escalation.2341728017
Short name T659
Test name
Test status
Simulation time 398366190 ps
CPU time 15.47 seconds
Started Jun 23 05:08:19 PM PDT 24
Finished Jun 23 05:08:35 PM PDT 24
Peak memory 218280 kb
Host smart-f35cc1fe-e9aa-4acd-8a6f-39b344d30e97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341728017 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_security_escalation.2341728017
Directory /workspace/30.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/30.lc_ctrl_smoke.3434289320
Short name T64
Test name
Test status
Simulation time 265886294 ps
CPU time 3.05 seconds
Started Jun 23 05:08:18 PM PDT 24
Finished Jun 23 05:08:22 PM PDT 24
Peak memory 217796 kb
Host smart-a5422149-d6de-42b0-a633-6dd28249a5ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434289320 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_smoke.3434289320
Directory /workspace/30.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_failure.223862883
Short name T176
Test name
Test status
Simulation time 193274992 ps
CPU time 25.22 seconds
Started Jun 23 05:08:17 PM PDT 24
Finished Jun 23 05:08:43 PM PDT 24
Peak memory 250896 kb
Host smart-d4036ea0-9fba-46f0-aae3-69af2c08d0c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223862883 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_failure.223862883
Directory /workspace/30.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_post_trans.1633217836
Short name T756
Test name
Test status
Simulation time 975280598 ps
CPU time 10.67 seconds
Started Jun 23 05:08:19 PM PDT 24
Finished Jun 23 05:08:30 PM PDT 24
Peak memory 250804 kb
Host smart-cfceab20-81f2-4e16-b0d7-7c41687e55d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633217836 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_post_trans.1633217836
Directory /workspace/30.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all.2646639077
Short name T614
Test name
Test status
Simulation time 42631585624 ps
CPU time 89.71 seconds
Started Jun 23 05:08:20 PM PDT 24
Finished Jun 23 05:09:50 PM PDT 24
Peak memory 266864 kb
Host smart-8ac0fc49-d260-42c3-8742-b01e030c7ace
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646639077 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.lc_ctrl_stress_all.2646639077
Directory /workspace/30.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all_with_rand_reset.3328045032
Short name T149
Test name
Test status
Simulation time 29433006632 ps
CPU time 626.44 seconds
Started Jun 23 05:08:17 PM PDT 24
Finished Jun 23 05:18:44 PM PDT 24
Peak memory 438408 kb
Host smart-5962a2e4-9498-451f-8d8a-9fbcf5966f0d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3328045032 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_stress_all_with_rand_reset.3328045032
Directory /workspace/30.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.lc_ctrl_volatile_unlock_smoke.2934645710
Short name T645
Test name
Test status
Simulation time 13069894 ps
CPU time 0.84 seconds
Started Jun 23 05:08:20 PM PDT 24
Finished Jun 23 05:08:22 PM PDT 24
Peak memory 208928 kb
Host smart-1cccdd94-5da9-47ba-bbac-bdc34c591f35
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934645710 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_c
trl_volatile_unlock_smoke.2934645710
Directory /workspace/30.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_alert_test.905489055
Short name T760
Test name
Test status
Simulation time 45221085 ps
CPU time 1.01 seconds
Started Jun 23 05:08:21 PM PDT 24
Finished Jun 23 05:08:23 PM PDT 24
Peak memory 208960 kb
Host smart-7a40385b-4a5e-4644-aea2-cf9784b2a3b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905489055 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_alert_test.905489055
Directory /workspace/31.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.lc_ctrl_errors.2519254814
Short name T316
Test name
Test status
Simulation time 1285250744 ps
CPU time 15.23 seconds
Started Jun 23 05:08:24 PM PDT 24
Finished Jun 23 05:08:40 PM PDT 24
Peak memory 218160 kb
Host smart-54c4d765-9322-4947-9e20-151614099999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519254814 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_errors.2519254814
Directory /workspace/31.lc_ctrl_errors/latest

Test location /workspace/coverage/default/31.lc_ctrl_jtag_access.3627896933
Short name T495
Test name
Test status
Simulation time 270422943 ps
CPU time 5.6 seconds
Started Jun 23 05:08:29 PM PDT 24
Finished Jun 23 05:08:35 PM PDT 24
Peak memory 217164 kb
Host smart-00fc1325-1b30-4832-8406-d5ee3e3f30ed
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627896933 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_jtag_access.3627896933
Directory /workspace/31.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/31.lc_ctrl_prog_failure.371390187
Short name T225
Test name
Test status
Simulation time 110127840 ps
CPU time 1.94 seconds
Started Jun 23 05:08:22 PM PDT 24
Finished Jun 23 05:08:25 PM PDT 24
Peak memory 222112 kb
Host smart-d779d7c8-6745-45de-8583-f5bbeeb833c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371390187 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_prog_failure.371390187
Directory /workspace/31.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_mubi.1099773860
Short name T244
Test name
Test status
Simulation time 324789036 ps
CPU time 11.11 seconds
Started Jun 23 05:08:21 PM PDT 24
Finished Jun 23 05:08:33 PM PDT 24
Peak memory 218808 kb
Host smart-f24b98a1-5c63-4346-a093-5cc42ec244a9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099773860 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_mubi.1099773860
Directory /workspace/31.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_digest.1045963771
Short name T746
Test name
Test status
Simulation time 3255484065 ps
CPU time 21.99 seconds
Started Jun 23 05:08:29 PM PDT 24
Finished Jun 23 05:08:52 PM PDT 24
Peak memory 218956 kb
Host smart-45c0f45d-6ad6-448b-b114-50c5edc991d4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045963771 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_d
igest.1045963771
Directory /workspace/31.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_mux.3573873970
Short name T487
Test name
Test status
Simulation time 334643399 ps
CPU time 7.32 seconds
Started Jun 23 05:08:23 PM PDT 24
Finished Jun 23 05:08:31 PM PDT 24
Peak memory 218260 kb
Host smart-89796d9f-619d-4737-aecd-cd288ffd7254
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573873970 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_mux.
3573873970
Directory /workspace/31.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/31.lc_ctrl_security_escalation.2065367907
Short name T48
Test name
Test status
Simulation time 1201087801 ps
CPU time 8.04 seconds
Started Jun 23 05:08:20 PM PDT 24
Finished Jun 23 05:08:28 PM PDT 24
Peak memory 225076 kb
Host smart-028b840e-fac1-4c59-8cde-b09a178f111b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065367907 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_security_escalation.2065367907
Directory /workspace/31.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/31.lc_ctrl_smoke.1704608244
Short name T229
Test name
Test status
Simulation time 51853419 ps
CPU time 2.62 seconds
Started Jun 23 05:08:18 PM PDT 24
Finished Jun 23 05:08:22 PM PDT 24
Peak memory 217660 kb
Host smart-033685d3-0c22-473b-aa91-2b7d8e9f0eed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704608244 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_smoke.1704608244
Directory /workspace/31.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_failure.31599376
Short name T168
Test name
Test status
Simulation time 324535309 ps
CPU time 25.75 seconds
Started Jun 23 05:08:23 PM PDT 24
Finished Jun 23 05:08:50 PM PDT 24
Peak memory 250884 kb
Host smart-9d7c2ac4-15a0-486f-9764-f2c48a01aa7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31599376 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_failure.31599376
Directory /workspace/31.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_post_trans.2644035752
Short name T770
Test name
Test status
Simulation time 74009081 ps
CPU time 6.4 seconds
Started Jun 23 05:08:22 PM PDT 24
Finished Jun 23 05:08:30 PM PDT 24
Peak memory 246068 kb
Host smart-a417eeb1-d558-4923-9763-a49be8a632cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644035752 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_post_trans.2644035752
Directory /workspace/31.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/31.lc_ctrl_stress_all.1847015514
Short name T739
Test name
Test status
Simulation time 4575430946 ps
CPU time 123.18 seconds
Started Jun 23 05:08:24 PM PDT 24
Finished Jun 23 05:10:28 PM PDT 24
Peak memory 283648 kb
Host smart-6228167f-25c6-4618-9997-0f06522776b5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847015514 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.lc_ctrl_stress_all.1847015514
Directory /workspace/31.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.lc_ctrl_volatile_unlock_smoke.3761998607
Short name T78
Test name
Test status
Simulation time 37714922 ps
CPU time 1.01 seconds
Started Jun 23 05:08:23 PM PDT 24
Finished Jun 23 05:08:25 PM PDT 24
Peak memory 212868 kb
Host smart-e8da6244-9ce4-4877-8a46-78d23a88c4c6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761998607 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_c
trl_volatile_unlock_smoke.3761998607
Directory /workspace/31.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_alert_test.2167552240
Short name T707
Test name
Test status
Simulation time 18338181 ps
CPU time 1.26 seconds
Started Jun 23 05:08:31 PM PDT 24
Finished Jun 23 05:08:33 PM PDT 24
Peak memory 208996 kb
Host smart-2bc31b39-9604-411c-baf2-556b90273277
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167552240 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_alert_test.2167552240
Directory /workspace/32.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.lc_ctrl_errors.122762961
Short name T567
Test name
Test status
Simulation time 175250378 ps
CPU time 9.37 seconds
Started Jun 23 05:08:32 PM PDT 24
Finished Jun 23 05:08:42 PM PDT 24
Peak memory 218196 kb
Host smart-a6bdbd22-65cd-4452-87e3-2e3c8575e437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122762961 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_errors.122762961
Directory /workspace/32.lc_ctrl_errors/latest

Test location /workspace/coverage/default/32.lc_ctrl_jtag_access.657522197
Short name T386
Test name
Test status
Simulation time 257044952 ps
CPU time 7.29 seconds
Started Jun 23 05:08:29 PM PDT 24
Finished Jun 23 05:08:37 PM PDT 24
Peak memory 217352 kb
Host smart-843d4579-e50a-4bd3-a74a-0120b400adbc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657522197 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_jtag_access.657522197
Directory /workspace/32.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/32.lc_ctrl_prog_failure.1303301902
Short name T433
Test name
Test status
Simulation time 73849757 ps
CPU time 3.83 seconds
Started Jun 23 05:08:29 PM PDT 24
Finished Jun 23 05:08:33 PM PDT 24
Peak memory 218364 kb
Host smart-463b7fe0-01be-4790-9f1f-7bbe5e15956f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303301902 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_prog_failure.1303301902
Directory /workspace/32.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_mubi.401534238
Short name T174
Test name
Test status
Simulation time 1639505259 ps
CPU time 16.28 seconds
Started Jun 23 05:08:28 PM PDT 24
Finished Jun 23 05:08:45 PM PDT 24
Peak memory 218288 kb
Host smart-4682ae12-4941-49c6-bd03-83665a581b60
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401534238 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_mubi.401534238
Directory /workspace/32.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_digest.867312151
Short name T744
Test name
Test status
Simulation time 436589296 ps
CPU time 9.07 seconds
Started Jun 23 05:08:26 PM PDT 24
Finished Jun 23 05:08:36 PM PDT 24
Peak memory 225980 kb
Host smart-2761f9d0-ffd7-4174-9345-9926a7372b06
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867312151 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_di
gest.867312151
Directory /workspace/32.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_mux.3020715859
Short name T823
Test name
Test status
Simulation time 275023773 ps
CPU time 8 seconds
Started Jun 23 05:08:29 PM PDT 24
Finished Jun 23 05:08:38 PM PDT 24
Peak memory 226072 kb
Host smart-bf3bdd6c-d782-48e4-ac40-a946888c814e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020715859 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_mux.
3020715859
Directory /workspace/32.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/32.lc_ctrl_smoke.559416104
Short name T638
Test name
Test status
Simulation time 276566281 ps
CPU time 2.66 seconds
Started Jun 23 05:08:22 PM PDT 24
Finished Jun 23 05:08:26 PM PDT 24
Peak memory 214376 kb
Host smart-a58b9a1d-a5f2-422b-a237-66bf72bd45f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559416104 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_smoke.559416104
Directory /workspace/32.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_failure.3797802040
Short name T292
Test name
Test status
Simulation time 253374374 ps
CPU time 26.17 seconds
Started Jun 23 05:08:24 PM PDT 24
Finished Jun 23 05:08:51 PM PDT 24
Peak memory 250916 kb
Host smart-f7e5b550-aa5c-4d14-8765-f018bf83f189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797802040 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_failure.3797802040
Directory /workspace/32.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_post_trans.3215033492
Short name T561
Test name
Test status
Simulation time 253915423 ps
CPU time 7.35 seconds
Started Jun 23 05:08:27 PM PDT 24
Finished Jun 23 05:08:35 PM PDT 24
Peak memory 250912 kb
Host smart-05481678-4a4f-4040-a407-5422a8526885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215033492 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_post_trans.3215033492
Directory /workspace/32.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all.1951820020
Short name T340
Test name
Test status
Simulation time 2987176737 ps
CPU time 110.08 seconds
Started Jun 23 05:08:27 PM PDT 24
Finished Jun 23 05:10:18 PM PDT 24
Peak memory 273768 kb
Host smart-fc12a00a-05de-4c32-bdfa-b59e44a5abe0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951820020 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.lc_ctrl_stress_all.1951820020
Directory /workspace/32.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.lc_ctrl_volatile_unlock_smoke.2392018971
Short name T734
Test name
Test status
Simulation time 36085727 ps
CPU time 0.89 seconds
Started Jun 23 05:08:23 PM PDT 24
Finished Jun 23 05:08:24 PM PDT 24
Peak memory 211948 kb
Host smart-d2150072-6faf-4035-abf5-9066207e7faf
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392018971 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_c
trl_volatile_unlock_smoke.2392018971
Directory /workspace/32.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_alert_test.2374199407
Short name T441
Test name
Test status
Simulation time 68913709 ps
CPU time 1.02 seconds
Started Jun 23 05:08:32 PM PDT 24
Finished Jun 23 05:08:34 PM PDT 24
Peak memory 209032 kb
Host smart-795c050d-c03a-4f15-bda4-cc8c42f4d8a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374199407 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_alert_test.2374199407
Directory /workspace/33.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.lc_ctrl_errors.1245327598
Short name T610
Test name
Test status
Simulation time 1083484643 ps
CPU time 11.06 seconds
Started Jun 23 05:08:32 PM PDT 24
Finished Jun 23 05:08:44 PM PDT 24
Peak memory 218324 kb
Host smart-143c5914-8d96-4fda-b520-58cd423fb36a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245327598 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_errors.1245327598
Directory /workspace/33.lc_ctrl_errors/latest

Test location /workspace/coverage/default/33.lc_ctrl_jtag_access.3940845591
Short name T106
Test name
Test status
Simulation time 1756251714 ps
CPU time 5.6 seconds
Started Jun 23 05:08:33 PM PDT 24
Finished Jun 23 05:08:39 PM PDT 24
Peak memory 217420 kb
Host smart-c5e16e1a-e197-4993-b95b-403c1d8f4f3c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940845591 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_jtag_access.3940845591
Directory /workspace/33.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/33.lc_ctrl_prog_failure.3836646132
Short name T711
Test name
Test status
Simulation time 33540320 ps
CPU time 2.29 seconds
Started Jun 23 05:08:33 PM PDT 24
Finished Jun 23 05:08:36 PM PDT 24
Peak memory 218228 kb
Host smart-a6df67b9-8730-4341-8bbb-edf667f5f88d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836646132 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_prog_failure.3836646132
Directory /workspace/33.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_mubi.1049568087
Short name T398
Test name
Test status
Simulation time 612677925 ps
CPU time 10.06 seconds
Started Jun 23 05:08:34 PM PDT 24
Finished Jun 23 05:08:44 PM PDT 24
Peak memory 218936 kb
Host smart-980d17a1-d341-4600-90ea-3a7102536357
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049568087 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_mubi.1049568087
Directory /workspace/33.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_digest.137982156
Short name T360
Test name
Test status
Simulation time 995499703 ps
CPU time 14.27 seconds
Started Jun 23 05:08:34 PM PDT 24
Finished Jun 23 05:08:49 PM PDT 24
Peak memory 218256 kb
Host smart-9d3526fc-44b9-4a91-8294-fbea3dc18b28
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137982156 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_di
gest.137982156
Directory /workspace/33.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_mux.2544005054
Short name T826
Test name
Test status
Simulation time 1188708961 ps
CPU time 8.13 seconds
Started Jun 23 05:08:32 PM PDT 24
Finished Jun 23 05:08:41 PM PDT 24
Peak memory 218264 kb
Host smart-2a2f07d8-f0ca-4daa-9de5-a8ba76395fd3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544005054 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_mux.
2544005054
Directory /workspace/33.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/33.lc_ctrl_security_escalation.2119249186
Short name T47
Test name
Test status
Simulation time 4032355890 ps
CPU time 10.63 seconds
Started Jun 23 05:08:33 PM PDT 24
Finished Jun 23 05:08:44 PM PDT 24
Peak memory 226116 kb
Host smart-355b3e12-6be6-400a-b510-deb1fd60fff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119249186 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_security_escalation.2119249186
Directory /workspace/33.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/33.lc_ctrl_smoke.876532696
Short name T858
Test name
Test status
Simulation time 922944906 ps
CPU time 5.04 seconds
Started Jun 23 05:08:26 PM PDT 24
Finished Jun 23 05:08:31 PM PDT 24
Peak memory 217748 kb
Host smart-93157c66-857e-4313-8f72-16b265e6f523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876532696 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_smoke.876532696
Directory /workspace/33.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_failure.2145838264
Short name T224
Test name
Test status
Simulation time 1109257053 ps
CPU time 25.03 seconds
Started Jun 23 05:08:27 PM PDT 24
Finished Jun 23 05:08:53 PM PDT 24
Peak memory 251064 kb
Host smart-a084e8e6-0595-4b7c-81e3-e9a6240a7167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145838264 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_failure.2145838264
Directory /workspace/33.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_post_trans.3796350085
Short name T555
Test name
Test status
Simulation time 126305559 ps
CPU time 5.52 seconds
Started Jun 23 05:08:30 PM PDT 24
Finished Jun 23 05:08:36 PM PDT 24
Peak memory 218232 kb
Host smart-adc1a244-9073-4262-aa42-2f7e7b323cda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796350085 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_post_trans.3796350085
Directory /workspace/33.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all.3965146686
Short name T357
Test name
Test status
Simulation time 5545227415 ps
CPU time 103.99 seconds
Started Jun 23 05:08:36 PM PDT 24
Finished Jun 23 05:10:21 PM PDT 24
Peak memory 242764 kb
Host smart-437e6974-2a14-4f07-ae8c-87a46e23723f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965146686 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.lc_ctrl_stress_all.3965146686
Directory /workspace/33.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all_with_rand_reset.2120328734
Short name T813
Test name
Test status
Simulation time 188407843353 ps
CPU time 888.54 seconds
Started Jun 23 05:08:34 PM PDT 24
Finished Jun 23 05:23:23 PM PDT 24
Peak memory 496916 kb
Host smart-a5d22210-7c04-463f-a0aa-850328e7a381
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2120328734 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_stress_all_with_rand_reset.2120328734
Directory /workspace/33.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.lc_ctrl_volatile_unlock_smoke.2617968941
Short name T408
Test name
Test status
Simulation time 36240980 ps
CPU time 0.88 seconds
Started Jun 23 05:08:27 PM PDT 24
Finished Jun 23 05:08:29 PM PDT 24
Peak memory 209156 kb
Host smart-a4825a7f-6058-43fc-9a77-a00f750ab376
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617968941 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_c
trl_volatile_unlock_smoke.2617968941
Directory /workspace/33.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_alert_test.1796418994
Short name T615
Test name
Test status
Simulation time 18346545 ps
CPU time 0.98 seconds
Started Jun 23 05:08:36 PM PDT 24
Finished Jun 23 05:08:38 PM PDT 24
Peak memory 209020 kb
Host smart-4719eb68-a8ff-42f1-8bd6-f4ac26028265
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796418994 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_alert_test.1796418994
Directory /workspace/34.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.lc_ctrl_errors.3874599483
Short name T302
Test name
Test status
Simulation time 484719430 ps
CPU time 10.35 seconds
Started Jun 23 05:08:38 PM PDT 24
Finished Jun 23 05:08:49 PM PDT 24
Peak memory 218204 kb
Host smart-e489134c-5a44-47db-b4a9-10043aac870d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874599483 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_errors.3874599483
Directory /workspace/34.lc_ctrl_errors/latest

Test location /workspace/coverage/default/34.lc_ctrl_jtag_access.619863180
Short name T181
Test name
Test status
Simulation time 132098927 ps
CPU time 1.56 seconds
Started Jun 23 05:08:46 PM PDT 24
Finished Jun 23 05:08:48 PM PDT 24
Peak memory 217048 kb
Host smart-cf2ffd61-4cd7-4d64-8af4-340b69a76721
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619863180 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_jtag_access.619863180
Directory /workspace/34.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/34.lc_ctrl_prog_failure.3120622894
Short name T539
Test name
Test status
Simulation time 77195652 ps
CPU time 1.6 seconds
Started Jun 23 05:08:37 PM PDT 24
Finished Jun 23 05:08:39 PM PDT 24
Peak memory 221844 kb
Host smart-e9334252-9cf2-412b-830e-09ea7155be87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120622894 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_prog_failure.3120622894
Directory /workspace/34.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_mubi.1912123884
Short name T700
Test name
Test status
Simulation time 738308188 ps
CPU time 12.04 seconds
Started Jun 23 05:08:41 PM PDT 24
Finished Jun 23 05:08:54 PM PDT 24
Peak memory 218452 kb
Host smart-32246326-ee74-4088-9cc4-96f6a4f29b0c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912123884 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_mubi.1912123884
Directory /workspace/34.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_digest.115771388
Short name T804
Test name
Test status
Simulation time 804245571 ps
CPU time 17.16 seconds
Started Jun 23 05:08:40 PM PDT 24
Finished Jun 23 05:08:59 PM PDT 24
Peak memory 218196 kb
Host smart-855ea491-5b51-41d9-884d-07fc478a2126
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115771388 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_di
gest.115771388
Directory /workspace/34.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_mux.1185577123
Short name T576
Test name
Test status
Simulation time 1747373526 ps
CPU time 15.04 seconds
Started Jun 23 05:08:40 PM PDT 24
Finished Jun 23 05:08:56 PM PDT 24
Peak memory 226040 kb
Host smart-504bdb49-dcb7-418c-b7b0-5db7f0568112
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185577123 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_mux.
1185577123
Directory /workspace/34.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/34.lc_ctrl_security_escalation.339903669
Short name T608
Test name
Test status
Simulation time 1577806683 ps
CPU time 8.8 seconds
Started Jun 23 05:08:38 PM PDT 24
Finished Jun 23 05:08:47 PM PDT 24
Peak memory 225056 kb
Host smart-754e4fcd-aeab-48e2-9fca-6b13b9365d52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339903669 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_security_escalation.339903669
Directory /workspace/34.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/34.lc_ctrl_smoke.2574837583
Short name T460
Test name
Test status
Simulation time 141727758 ps
CPU time 2.32 seconds
Started Jun 23 05:08:40 PM PDT 24
Finished Jun 23 05:08:42 PM PDT 24
Peak memory 214156 kb
Host smart-961f2d35-7655-4601-8bd7-46bd677bc83f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574837583 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_smoke.2574837583
Directory /workspace/34.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_failure.3605901950
Short name T443
Test name
Test status
Simulation time 1277462937 ps
CPU time 29.7 seconds
Started Jun 23 05:08:46 PM PDT 24
Finished Jun 23 05:09:16 PM PDT 24
Peak memory 250836 kb
Host smart-d885c5a8-65f8-433b-be41-07b645dcaae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605901950 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_failure.3605901950
Directory /workspace/34.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_post_trans.2248520190
Short name T173
Test name
Test status
Simulation time 83488065 ps
CPU time 6.43 seconds
Started Jun 23 05:08:40 PM PDT 24
Finished Jun 23 05:08:48 PM PDT 24
Peak memory 246440 kb
Host smart-f1caa551-4800-477c-a791-155e52cb628b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248520190 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_post_trans.2248520190
Directory /workspace/34.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all.3068387124
Short name T458
Test name
Test status
Simulation time 2024984406 ps
CPU time 77.36 seconds
Started Jun 23 05:08:40 PM PDT 24
Finished Jun 23 05:09:59 PM PDT 24
Peak memory 248856 kb
Host smart-d89adb55-5ac3-40c4-b8d9-2f08029bbad7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068387124 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.lc_ctrl_stress_all.3068387124
Directory /workspace/34.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.lc_ctrl_volatile_unlock_smoke.94582597
Short name T575
Test name
Test status
Simulation time 33147392 ps
CPU time 0.98 seconds
Started Jun 23 05:08:33 PM PDT 24
Finished Jun 23 05:08:35 PM PDT 24
Peak memory 211992 kb
Host smart-05cd199c-72a2-458c-b718-c3acee64e8f6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94582597 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vol
atile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctr
l_volatile_unlock_smoke.94582597
Directory /workspace/34.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_alert_test.1062238510
Short name T859
Test name
Test status
Simulation time 14189628 ps
CPU time 0.9 seconds
Started Jun 23 05:08:47 PM PDT 24
Finished Jun 23 05:08:49 PM PDT 24
Peak memory 208916 kb
Host smart-ad04ac33-87ff-443d-9ce0-b6a4806337e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062238510 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_alert_test.1062238510
Directory /workspace/35.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.lc_ctrl_errors.1975963703
Short name T540
Test name
Test status
Simulation time 2101092944 ps
CPU time 7.21 seconds
Started Jun 23 05:08:43 PM PDT 24
Finished Jun 23 05:08:51 PM PDT 24
Peak memory 218232 kb
Host smart-05eb0016-207e-4f29-8231-4c579621ef2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1975963703 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_errors.1975963703
Directory /workspace/35.lc_ctrl_errors/latest

Test location /workspace/coverage/default/35.lc_ctrl_jtag_access.2907149016
Short name T657
Test name
Test status
Simulation time 1235626614 ps
CPU time 8.07 seconds
Started Jun 23 05:08:46 PM PDT 24
Finished Jun 23 05:08:55 PM PDT 24
Peak memory 217316 kb
Host smart-9985b2d7-9350-412e-8e66-0289b773e77c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907149016 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_jtag_access.2907149016
Directory /workspace/35.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/35.lc_ctrl_prog_failure.1085211264
Short name T261
Test name
Test status
Simulation time 428490405 ps
CPU time 3.93 seconds
Started Jun 23 05:08:43 PM PDT 24
Finished Jun 23 05:08:48 PM PDT 24
Peak memory 218228 kb
Host smart-938bfa13-34e5-4a48-b90d-7a30ac617943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085211264 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_prog_failure.1085211264
Directory /workspace/35.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_mubi.3505775216
Short name T854
Test name
Test status
Simulation time 404460435 ps
CPU time 14.66 seconds
Started Jun 23 05:08:43 PM PDT 24
Finished Jun 23 05:08:59 PM PDT 24
Peak memory 218904 kb
Host smart-a38d0aee-263e-4302-b379-56240a01706e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505775216 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_mubi.3505775216
Directory /workspace/35.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_digest.3588850112
Short name T625
Test name
Test status
Simulation time 643873101 ps
CPU time 9.44 seconds
Started Jun 23 05:08:46 PM PDT 24
Finished Jun 23 05:08:56 PM PDT 24
Peak memory 226044 kb
Host smart-20290d99-e74c-4dff-bd80-9e19e3e4be2d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588850112 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_d
igest.3588850112
Directory /workspace/35.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_mux.1447385570
Short name T265
Test name
Test status
Simulation time 1807080540 ps
CPU time 7.23 seconds
Started Jun 23 05:08:48 PM PDT 24
Finished Jun 23 05:08:57 PM PDT 24
Peak memory 218236 kb
Host smart-6c6eaae1-d96b-4636-b10c-ccbf14139ca2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447385570 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_mux.
1447385570
Directory /workspace/35.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/35.lc_ctrl_security_escalation.3259961109
Short name T840
Test name
Test status
Simulation time 367021372 ps
CPU time 13.71 seconds
Started Jun 23 05:08:44 PM PDT 24
Finished Jun 23 05:08:58 PM PDT 24
Peak memory 225988 kb
Host smart-66f3889d-c79a-4d67-a40c-e4484600f355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259961109 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_security_escalation.3259961109
Directory /workspace/35.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/35.lc_ctrl_smoke.3260891303
Short name T551
Test name
Test status
Simulation time 40215314 ps
CPU time 2 seconds
Started Jun 23 05:08:38 PM PDT 24
Finished Jun 23 05:08:41 PM PDT 24
Peak memory 217764 kb
Host smart-5804fe40-5c68-49a1-8c30-2a0be20ceb03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260891303 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_smoke.3260891303
Directory /workspace/35.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_failure.2794449838
Short name T400
Test name
Test status
Simulation time 872602948 ps
CPU time 20.59 seconds
Started Jun 23 05:08:46 PM PDT 24
Finished Jun 23 05:09:07 PM PDT 24
Peak memory 250836 kb
Host smart-135c3857-a402-452c-a64e-7400793c16f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794449838 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_failure.2794449838
Directory /workspace/35.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_post_trans.3147804293
Short name T500
Test name
Test status
Simulation time 97452737 ps
CPU time 8.66 seconds
Started Jun 23 05:08:43 PM PDT 24
Finished Jun 23 05:08:52 PM PDT 24
Peak memory 250912 kb
Host smart-bdee3574-5c40-46dd-96f1-008c330c13e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147804293 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_post_trans.3147804293
Directory /workspace/35.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all.1601757394
Short name T293
Test name
Test status
Simulation time 23574582687 ps
CPU time 776.89 seconds
Started Jun 23 05:08:48 PM PDT 24
Finished Jun 23 05:21:46 PM PDT 24
Peak memory 227588 kb
Host smart-a2e32d84-f11f-4203-8f3d-09c9cefd3511
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601757394 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.lc_ctrl_stress_all.1601757394
Directory /workspace/35.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.lc_ctrl_volatile_unlock_smoke.2533081351
Short name T761
Test name
Test status
Simulation time 71778851 ps
CPU time 1.35 seconds
Started Jun 23 05:08:38 PM PDT 24
Finished Jun 23 05:08:40 PM PDT 24
Peak memory 217844 kb
Host smart-ecbb4cb7-b4ef-4bb3-86c3-ffb8428d427d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533081351 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_c
trl_volatile_unlock_smoke.2533081351
Directory /workspace/35.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_alert_test.1700511531
Short name T757
Test name
Test status
Simulation time 17176953 ps
CPU time 1.09 seconds
Started Jun 23 05:08:49 PM PDT 24
Finished Jun 23 05:08:51 PM PDT 24
Peak memory 209116 kb
Host smart-996a613a-cfe6-43d2-a9f7-c02fd66e4bbd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700511531 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_alert_test.1700511531
Directory /workspace/36.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.lc_ctrl_errors.2960586930
Short name T232
Test name
Test status
Simulation time 797927209 ps
CPU time 17.38 seconds
Started Jun 23 05:08:49 PM PDT 24
Finished Jun 23 05:09:07 PM PDT 24
Peak memory 218232 kb
Host smart-b176be1d-ba41-4c9b-b0e2-0dce6c621562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960586930 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_errors.2960586930
Directory /workspace/36.lc_ctrl_errors/latest

Test location /workspace/coverage/default/36.lc_ctrl_jtag_access.4037042792
Short name T23
Test name
Test status
Simulation time 8898136195 ps
CPU time 9.11 seconds
Started Jun 23 05:08:51 PM PDT 24
Finished Jun 23 05:09:01 PM PDT 24
Peak memory 217768 kb
Host smart-d3522013-8e14-416a-880f-f6102233058b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037042792 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_jtag_access.4037042792
Directory /workspace/36.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/36.lc_ctrl_prog_failure.2795791834
Short name T639
Test name
Test status
Simulation time 177337614 ps
CPU time 3.36 seconds
Started Jun 23 05:08:50 PM PDT 24
Finished Jun 23 05:08:55 PM PDT 24
Peak memory 218232 kb
Host smart-fc6f7818-c5b1-4894-aa3d-615961a7dc25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795791834 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_prog_failure.2795791834
Directory /workspace/36.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_mubi.196750869
Short name T392
Test name
Test status
Simulation time 342202279 ps
CPU time 12.64 seconds
Started Jun 23 05:08:49 PM PDT 24
Finished Jun 23 05:09:02 PM PDT 24
Peak memory 218240 kb
Host smart-7b1e29c4-2f15-4b96-99cb-7ab12756741d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196750869 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_mubi.196750869
Directory /workspace/36.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_digest.276063480
Short name T721
Test name
Test status
Simulation time 1107579790 ps
CPU time 15.12 seconds
Started Jun 23 05:08:52 PM PDT 24
Finished Jun 23 05:09:08 PM PDT 24
Peak memory 225980 kb
Host smart-4c21586f-ca07-47ac-aa8d-50417f643c20
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276063480 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_di
gest.276063480
Directory /workspace/36.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_mux.45464382
Short name T281
Test name
Test status
Simulation time 1197815334 ps
CPU time 6.34 seconds
Started Jun 23 05:08:49 PM PDT 24
Finished Jun 23 05:08:56 PM PDT 24
Peak memory 226092 kb
Host smart-9fe68f3a-80ae-4546-b7ca-ee80a1ecc171
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45464382 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_mux.45464382
Directory /workspace/36.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/36.lc_ctrl_security_escalation.2644008262
Short name T718
Test name
Test status
Simulation time 1438385843 ps
CPU time 8.22 seconds
Started Jun 23 05:08:51 PM PDT 24
Finished Jun 23 05:09:00 PM PDT 24
Peak memory 225220 kb
Host smart-6952432e-c411-4ef3-952b-7a5c6f002d31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644008262 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_security_escalation.2644008262
Directory /workspace/36.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/36.lc_ctrl_smoke.1724893489
Short name T270
Test name
Test status
Simulation time 51649865 ps
CPU time 3 seconds
Started Jun 23 05:08:44 PM PDT 24
Finished Jun 23 05:08:48 PM PDT 24
Peak memory 217756 kb
Host smart-6042d3b9-c20b-498e-800e-afcebb36aad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724893489 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_smoke.1724893489
Directory /workspace/36.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_failure.3105291775
Short name T764
Test name
Test status
Simulation time 519516705 ps
CPU time 18.08 seconds
Started Jun 23 05:08:48 PM PDT 24
Finished Jun 23 05:09:07 PM PDT 24
Peak memory 250888 kb
Host smart-71f188cb-4856-4517-8910-6d9716bd957f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105291775 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_failure.3105291775
Directory /workspace/36.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_post_trans.1823244119
Short name T579
Test name
Test status
Simulation time 249211920 ps
CPU time 9.66 seconds
Started Jun 23 05:08:48 PM PDT 24
Finished Jun 23 05:08:59 PM PDT 24
Peak memory 250864 kb
Host smart-a3144bc1-8031-4544-b20f-ac4214b9fc10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823244119 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_post_trans.1823244119
Directory /workspace/36.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all.2844998484
Short name T478
Test name
Test status
Simulation time 88525104855 ps
CPU time 321.4 seconds
Started Jun 23 05:08:51 PM PDT 24
Finished Jun 23 05:14:13 PM PDT 24
Peak memory 332924 kb
Host smart-d0d3e65e-fe51-4796-84b2-819196461aa3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844998484 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.lc_ctrl_stress_all.2844998484
Directory /workspace/36.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.lc_ctrl_volatile_unlock_smoke.2554569731
Short name T344
Test name
Test status
Simulation time 15399585 ps
CPU time 0.98 seconds
Started Jun 23 05:08:48 PM PDT 24
Finished Jun 23 05:08:50 PM PDT 24
Peak memory 211964 kb
Host smart-861f2ee9-09d9-4699-b979-b4cb99b6852c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554569731 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_c
trl_volatile_unlock_smoke.2554569731
Directory /workspace/36.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_alert_test.641635621
Short name T93
Test name
Test status
Simulation time 31218785 ps
CPU time 1.08 seconds
Started Jun 23 05:08:58 PM PDT 24
Finished Jun 23 05:08:59 PM PDT 24
Peak memory 209104 kb
Host smart-7a7fccf7-91ec-46d3-b44e-f15eb171b013
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641635621 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_alert_test.641635621
Directory /workspace/37.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.lc_ctrl_errors.2205636281
Short name T13
Test name
Test status
Simulation time 398240247 ps
CPU time 13.96 seconds
Started Jun 23 05:08:52 PM PDT 24
Finished Jun 23 05:09:06 PM PDT 24
Peak memory 218264 kb
Host smart-d1e9de44-74ce-4edd-8805-ed854c37f229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205636281 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_errors.2205636281
Directory /workspace/37.lc_ctrl_errors/latest

Test location /workspace/coverage/default/37.lc_ctrl_jtag_access.530979780
Short name T569
Test name
Test status
Simulation time 480464547 ps
CPU time 12.75 seconds
Started Jun 23 05:08:55 PM PDT 24
Finished Jun 23 05:09:08 PM PDT 24
Peak memory 217312 kb
Host smart-ca07b6fa-206e-4bce-8930-4eca3ab57611
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530979780 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_jtag_access.530979780
Directory /workspace/37.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/37.lc_ctrl_prog_failure.4185778000
Short name T327
Test name
Test status
Simulation time 312138852 ps
CPU time 2.83 seconds
Started Jun 23 05:08:52 PM PDT 24
Finished Jun 23 05:08:55 PM PDT 24
Peak memory 218232 kb
Host smart-d31f9e5b-3c5b-4933-ba1a-0c5ee96e54bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185778000 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_prog_failure.4185778000
Directory /workspace/37.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_mubi.1433647679
Short name T348
Test name
Test status
Simulation time 1310258940 ps
CPU time 11.33 seconds
Started Jun 23 05:08:55 PM PDT 24
Finished Jun 23 05:09:07 PM PDT 24
Peak memory 218212 kb
Host smart-17a62d25-b864-4540-8caf-adafe9aa284f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433647679 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_mubi.1433647679
Directory /workspace/37.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_digest.859350847
Short name T428
Test name
Test status
Simulation time 237797515 ps
CPU time 11.16 seconds
Started Jun 23 05:08:55 PM PDT 24
Finished Jun 23 05:09:07 PM PDT 24
Peak memory 218272 kb
Host smart-3fdd12bb-7ec1-4db6-a8e1-9fdb81d4c869
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859350847 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_di
gest.859350847
Directory /workspace/37.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_mux.4101818773
Short name T329
Test name
Test status
Simulation time 682381853 ps
CPU time 12.01 seconds
Started Jun 23 05:08:55 PM PDT 24
Finished Jun 23 05:09:07 PM PDT 24
Peak memory 218160 kb
Host smart-07f1469b-54fc-4a64-8e5d-d569003bda0a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101818773 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_mux.
4101818773
Directory /workspace/37.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/37.lc_ctrl_security_escalation.2566236386
Short name T188
Test name
Test status
Simulation time 842020720 ps
CPU time 9.68 seconds
Started Jun 23 05:08:50 PM PDT 24
Finished Jun 23 05:09:01 PM PDT 24
Peak memory 218300 kb
Host smart-95634ff0-94f6-4833-bc07-19d4428a6b79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566236386 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_security_escalation.2566236386
Directory /workspace/37.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/37.lc_ctrl_smoke.3783559888
Short name T368
Test name
Test status
Simulation time 114600860 ps
CPU time 1.65 seconds
Started Jun 23 05:08:52 PM PDT 24
Finished Jun 23 05:08:54 PM PDT 24
Peak memory 213992 kb
Host smart-6199410e-7b41-4c80-8ec2-d236397fce0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783559888 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_smoke.3783559888
Directory /workspace/37.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_failure.2643005587
Short name T257
Test name
Test status
Simulation time 1383881019 ps
CPU time 32.68 seconds
Started Jun 23 05:08:49 PM PDT 24
Finished Jun 23 05:09:22 PM PDT 24
Peak memory 250920 kb
Host smart-16a1b439-728f-4726-a19e-aa0c86ec3b04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643005587 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_failure.2643005587
Directory /workspace/37.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_post_trans.443594521
Short name T444
Test name
Test status
Simulation time 83491571 ps
CPU time 8.65 seconds
Started Jun 23 05:08:48 PM PDT 24
Finished Jun 23 05:08:58 PM PDT 24
Peak memory 250900 kb
Host smart-d6c1ad46-9580-41e1-a138-45f386556dc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443594521 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_post_trans.443594521
Directory /workspace/37.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all.849536650
Short name T41
Test name
Test status
Simulation time 30501852512 ps
CPU time 255.13 seconds
Started Jun 23 05:08:53 PM PDT 24
Finished Jun 23 05:13:09 PM PDT 24
Peak memory 228356 kb
Host smart-c5893a5f-d73b-4604-9956-97595397f702
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849536650 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.lc_ctrl_stress_all.849536650
Directory /workspace/37.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all_with_rand_reset.1634409033
Short name T161
Test name
Test status
Simulation time 17228831632 ps
CPU time 402.28 seconds
Started Jun 23 05:08:54 PM PDT 24
Finished Jun 23 05:15:36 PM PDT 24
Peak memory 496788 kb
Host smart-ec15ecb5-3564-40ec-84b6-4cbd45c52c4a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1634409033 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_stress_all_with_rand_reset.1634409033
Directory /workspace/37.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.lc_ctrl_alert_test.1965257518
Short name T868
Test name
Test status
Simulation time 15593714 ps
CPU time 1.06 seconds
Started Jun 23 05:08:59 PM PDT 24
Finished Jun 23 05:09:01 PM PDT 24
Peak memory 209032 kb
Host smart-04ddea61-cde2-4e4f-97fc-746c9766e326
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965257518 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_alert_test.1965257518
Directory /workspace/38.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.lc_ctrl_errors.965549826
Short name T709
Test name
Test status
Simulation time 1467307013 ps
CPU time 15.21 seconds
Started Jun 23 05:08:57 PM PDT 24
Finished Jun 23 05:09:13 PM PDT 24
Peak memory 218192 kb
Host smart-ae8b37de-24d1-4845-b2df-efe94006e088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965549826 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_errors.965549826
Directory /workspace/38.lc_ctrl_errors/latest

Test location /workspace/coverage/default/38.lc_ctrl_jtag_access.3491623101
Short name T667
Test name
Test status
Simulation time 304552155 ps
CPU time 8.67 seconds
Started Jun 23 05:09:00 PM PDT 24
Finished Jun 23 05:09:10 PM PDT 24
Peak memory 217308 kb
Host smart-1c6a1bf3-1fe9-4453-901e-942d18146e6b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491623101 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_jtag_access.3491623101
Directory /workspace/38.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/38.lc_ctrl_prog_failure.795345390
Short name T342
Test name
Test status
Simulation time 69592640 ps
CPU time 3.12 seconds
Started Jun 23 05:08:57 PM PDT 24
Finished Jun 23 05:09:00 PM PDT 24
Peak memory 222516 kb
Host smart-0d3661c9-3a79-4d1b-bf6d-1e766df7de6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795345390 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_prog_failure.795345390
Directory /workspace/38.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_mubi.215380979
Short name T375
Test name
Test status
Simulation time 2200631200 ps
CPU time 12.65 seconds
Started Jun 23 05:08:58 PM PDT 24
Finished Jun 23 05:09:11 PM PDT 24
Peak memory 218996 kb
Host smart-3759d168-51f6-49e7-ae04-c965435ac2e9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215380979 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_mubi.215380979
Directory /workspace/38.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_digest.159054339
Short name T171
Test name
Test status
Simulation time 906112937 ps
CPU time 16.5 seconds
Started Jun 23 05:09:07 PM PDT 24
Finished Jun 23 05:09:25 PM PDT 24
Peak memory 218244 kb
Host smart-ca7e81b1-2937-43a6-9be0-6be480fdfbd1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159054339 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_di
gest.159054339
Directory /workspace/38.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_mux.783430238
Short name T533
Test name
Test status
Simulation time 724625619 ps
CPU time 18.15 seconds
Started Jun 23 05:09:00 PM PDT 24
Finished Jun 23 05:09:18 PM PDT 24
Peak memory 218276 kb
Host smart-75eb2818-35ff-4d6f-be1d-ed54cf0ddc9f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783430238 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_mux.783430238
Directory /workspace/38.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/38.lc_ctrl_security_escalation.2573497671
Short name T580
Test name
Test status
Simulation time 3671515866 ps
CPU time 7.95 seconds
Started Jun 23 05:09:00 PM PDT 24
Finished Jun 23 05:09:09 PM PDT 24
Peak memory 218276 kb
Host smart-912e3210-c227-4a92-a5cc-abf66e753e9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573497671 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_security_escalation.2573497671
Directory /workspace/38.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/38.lc_ctrl_smoke.14646322
Short name T294
Test name
Test status
Simulation time 109471401 ps
CPU time 7.74 seconds
Started Jun 23 05:08:56 PM PDT 24
Finished Jun 23 05:09:04 PM PDT 24
Peak memory 217772 kb
Host smart-f14fa1b7-d9da-4328-a4be-44ed27340d34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14646322 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_smoke.14646322
Directory /workspace/38.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_failure.1468905743
Short name T670
Test name
Test status
Simulation time 479184313 ps
CPU time 33.03 seconds
Started Jun 23 05:08:55 PM PDT 24
Finished Jun 23 05:09:28 PM PDT 24
Peak memory 250916 kb
Host smart-599b22f0-d068-4dd1-99d4-7fef7088a63e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468905743 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_failure.1468905743
Directory /workspace/38.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_post_trans.966727400
Short name T274
Test name
Test status
Simulation time 67571898 ps
CPU time 6.21 seconds
Started Jun 23 05:08:57 PM PDT 24
Finished Jun 23 05:09:04 PM PDT 24
Peak memory 247020 kb
Host smart-1a4cd61b-2cd8-476a-a4fc-ead5edde0b7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966727400 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_post_trans.966727400
Directory /workspace/38.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all.1188370354
Short name T108
Test name
Test status
Simulation time 7552290231 ps
CPU time 282.53 seconds
Started Jun 23 05:09:01 PM PDT 24
Finished Jun 23 05:13:44 PM PDT 24
Peak memory 278984 kb
Host smart-97311cac-205a-4d3f-9cc0-1b406b61e41b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188370354 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.lc_ctrl_stress_all.1188370354
Directory /workspace/38.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.lc_ctrl_volatile_unlock_smoke.2076026015
Short name T389
Test name
Test status
Simulation time 97210587 ps
CPU time 0.99 seconds
Started Jun 23 05:08:57 PM PDT 24
Finished Jun 23 05:08:58 PM PDT 24
Peak memory 217892 kb
Host smart-4a42ccb9-75c4-4a88-8547-d82bf4a679b1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076026015 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_c
trl_volatile_unlock_smoke.2076026015
Directory /workspace/38.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_alert_test.1472520110
Short name T415
Test name
Test status
Simulation time 36017564 ps
CPU time 0.83 seconds
Started Jun 23 05:09:07 PM PDT 24
Finished Jun 23 05:09:09 PM PDT 24
Peak memory 208772 kb
Host smart-ae6eba65-e7e1-4230-a11b-1a4cd4c4f593
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472520110 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_alert_test.1472520110
Directory /workspace/39.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.lc_ctrl_errors.3639801163
Short name T448
Test name
Test status
Simulation time 593434877 ps
CPU time 14.8 seconds
Started Jun 23 05:09:03 PM PDT 24
Finished Jun 23 05:09:18 PM PDT 24
Peak memory 218208 kb
Host smart-712f7950-57e8-4335-b382-f3b9a6a3caab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639801163 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_errors.3639801163
Directory /workspace/39.lc_ctrl_errors/latest

Test location /workspace/coverage/default/39.lc_ctrl_jtag_access.3712943910
Short name T21
Test name
Test status
Simulation time 2152570192 ps
CPU time 3.58 seconds
Started Jun 23 05:09:03 PM PDT 24
Finished Jun 23 05:09:07 PM PDT 24
Peak memory 217112 kb
Host smart-a8305ac1-9e6a-469f-bc1b-88ef917354cb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712943910 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_jtag_access.3712943910
Directory /workspace/39.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/39.lc_ctrl_prog_failure.1611067550
Short name T451
Test name
Test status
Simulation time 27671032 ps
CPU time 1.7 seconds
Started Jun 23 05:09:01 PM PDT 24
Finished Jun 23 05:09:03 PM PDT 24
Peak memory 218132 kb
Host smart-dff3f8a4-31df-471f-a6f7-a76b09511f03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611067550 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_prog_failure.1611067550
Directory /workspace/39.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_mubi.3793786795
Short name T743
Test name
Test status
Simulation time 819869455 ps
CPU time 10.66 seconds
Started Jun 23 05:09:08 PM PDT 24
Finished Jun 23 05:09:20 PM PDT 24
Peak memory 218340 kb
Host smart-95db0093-98ae-4517-8ec4-c6245c32240d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793786795 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_mubi.3793786795
Directory /workspace/39.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_digest.3891488654
Short name T842
Test name
Test status
Simulation time 4941688960 ps
CPU time 11.29 seconds
Started Jun 23 05:09:08 PM PDT 24
Finished Jun 23 05:09:21 PM PDT 24
Peak memory 226112 kb
Host smart-3b4c0e35-47f6-4402-914d-f27160bcfa82
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891488654 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_d
igest.3891488654
Directory /workspace/39.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_mux.2911259081
Short name T602
Test name
Test status
Simulation time 2261131227 ps
CPU time 11.5 seconds
Started Jun 23 05:09:06 PM PDT 24
Finished Jun 23 05:09:19 PM PDT 24
Peak memory 226124 kb
Host smart-c103a507-5d40-4059-856b-6f397875535f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911259081 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_mux.
2911259081
Directory /workspace/39.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/39.lc_ctrl_security_escalation.2231315831
Short name T856
Test name
Test status
Simulation time 515983693 ps
CPU time 11.81 seconds
Started Jun 23 05:09:07 PM PDT 24
Finished Jun 23 05:09:20 PM PDT 24
Peak memory 224924 kb
Host smart-45ca6202-907b-403e-bfed-c08098d8e1df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231315831 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_security_escalation.2231315831
Directory /workspace/39.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/39.lc_ctrl_smoke.1273227241
Short name T785
Test name
Test status
Simulation time 59937207 ps
CPU time 2.43 seconds
Started Jun 23 05:09:01 PM PDT 24
Finished Jun 23 05:09:04 PM PDT 24
Peak memory 222556 kb
Host smart-ce159040-a83c-4935-8d48-6ac888e5f70a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273227241 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_smoke.1273227241
Directory /workspace/39.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_failure.4164636981
Short name T446
Test name
Test status
Simulation time 517966594 ps
CPU time 36.88 seconds
Started Jun 23 05:09:06 PM PDT 24
Finished Jun 23 05:09:43 PM PDT 24
Peak memory 250916 kb
Host smart-8a7df35a-1355-4b88-b930-02a9f6f67520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164636981 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_failure.4164636981
Directory /workspace/39.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_post_trans.891090495
Short name T691
Test name
Test status
Simulation time 321308256 ps
CPU time 11.18 seconds
Started Jun 23 05:09:01 PM PDT 24
Finished Jun 23 05:09:13 PM PDT 24
Peak memory 250900 kb
Host smart-40635fea-b9a5-477a-a845-278b05190285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891090495 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_post_trans.891090495
Directory /workspace/39.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all.4038840942
Short name T256
Test name
Test status
Simulation time 13163966062 ps
CPU time 362.95 seconds
Started Jun 23 05:09:15 PM PDT 24
Finished Jun 23 05:15:19 PM PDT 24
Peak memory 270388 kb
Host smart-a2afe5ef-ed7f-4933-bad9-a1b8406b3963
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038840942 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.lc_ctrl_stress_all.4038840942
Directory /workspace/39.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.lc_ctrl_volatile_unlock_smoke.3327470803
Short name T216
Test name
Test status
Simulation time 24066343 ps
CPU time 0.97 seconds
Started Jun 23 05:09:01 PM PDT 24
Finished Jun 23 05:09:03 PM PDT 24
Peak memory 209224 kb
Host smart-97ed352b-938d-455f-b063-b75e87e01b44
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327470803 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_c
trl_volatile_unlock_smoke.3327470803
Directory /workspace/39.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_alert_test.4127373068
Short name T273
Test name
Test status
Simulation time 144542220 ps
CPU time 1.19 seconds
Started Jun 23 05:06:28 PM PDT 24
Finished Jun 23 05:06:30 PM PDT 24
Peak memory 208916 kb
Host smart-d7793633-70f4-4568-aed4-7e47a342636b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127373068 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_alert_test.4127373068
Directory /workspace/4.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.lc_ctrl_claim_transition_if.3804265923
Short name T243
Test name
Test status
Simulation time 10401587 ps
CPU time 0.94 seconds
Started Jun 23 05:06:25 PM PDT 24
Finished Jun 23 05:06:27 PM PDT 24
Peak memory 208932 kb
Host smart-12058cb5-b713-4c55-acab-3668391b25cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804265923 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_claim_transition_if.3804265923
Directory /workspace/4.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/4.lc_ctrl_errors.1136518428
Short name T535
Test name
Test status
Simulation time 927578364 ps
CPU time 10.53 seconds
Started Jun 23 05:06:24 PM PDT 24
Finished Jun 23 05:06:35 PM PDT 24
Peak memory 218184 kb
Host smart-ade87da8-f4f9-4178-bc6f-58b6a040c955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136518428 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_errors.1136518428
Directory /workspace/4.lc_ctrl_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_access.1635551274
Short name T364
Test name
Test status
Simulation time 2799931089 ps
CPU time 10.66 seconds
Started Jun 23 05:06:26 PM PDT 24
Finished Jun 23 05:06:37 PM PDT 24
Peak memory 217620 kb
Host smart-974281fa-ba85-4984-851d-b3bf3e0ab5e5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635551274 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_access.1635551274
Directory /workspace/4.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_errors.1984028597
Short name T19
Test name
Test status
Simulation time 2089921789 ps
CPU time 60.69 seconds
Started Jun 23 05:06:25 PM PDT 24
Finished Jun 23 05:07:26 PM PDT 24
Peak memory 219212 kb
Host smart-eeea51d0-3607-40c6-9beb-6dff2bd69f3b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984028597 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_er
rors.1984028597
Directory /workspace/4.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_priority.586188195
Short name T498
Test name
Test status
Simulation time 3188686342 ps
CPU time 9.88 seconds
Started Jun 23 05:06:26 PM PDT 24
Finished Jun 23 05:06:36 PM PDT 24
Peak memory 217964 kb
Host smart-2636b401-aa74-4908-9f00-4363074e68a7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586188195 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_priority.586188195
Directory /workspace/4.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_prog_failure.3366198853
Short name T672
Test name
Test status
Simulation time 1369655772 ps
CPU time 6.6 seconds
Started Jun 23 05:06:26 PM PDT 24
Finished Jun 23 05:06:33 PM PDT 24
Peak memory 217724 kb
Host smart-15369cee-f26e-41ba-ae6e-ee372d2f6b13
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366198853 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag
_prog_failure.3366198853
Directory /workspace/4.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_regwen_during_op.1176289023
Short name T643
Test name
Test status
Simulation time 6645400945 ps
CPU time 22.68 seconds
Started Jun 23 05:06:21 PM PDT 24
Finished Jun 23 05:06:44 PM PDT 24
Peak memory 217612 kb
Host smart-f3b5fdaf-24f3-4523-b5a4-004e93bc9d14
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176289023 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_regwen_during_op.1176289023
Directory /workspace/4.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_smoke.3849331040
Short name T852
Test name
Test status
Simulation time 2420142363 ps
CPU time 10.37 seconds
Started Jun 23 05:06:25 PM PDT 24
Finished Jun 23 05:06:36 PM PDT 24
Peak memory 217720 kb
Host smart-792dee31-2ad1-410b-a8be-5dabc27722c1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849331040 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_smoke.
3849331040
Directory /workspace/4.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_failure.1763151328
Short name T10
Test name
Test status
Simulation time 3357510948 ps
CPU time 61.48 seconds
Started Jun 23 05:06:25 PM PDT 24
Finished Jun 23 05:07:27 PM PDT 24
Peak memory 251280 kb
Host smart-da8aa51d-dfd1-4746-b864-0b2f3a5b60a3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763151328 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jta
g_state_failure.1763151328
Directory /workspace/4.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_post_trans.2426295277
Short name T803
Test name
Test status
Simulation time 697386399 ps
CPU time 21.62 seconds
Started Jun 23 05:06:24 PM PDT 24
Finished Jun 23 05:06:46 PM PDT 24
Peak memory 250840 kb
Host smart-0f878da4-1b73-401b-a049-4b4b2710689d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426295277 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_state_post_trans.2426295277
Directory /workspace/4.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_prog_failure.1161504053
Short name T521
Test name
Test status
Simulation time 238048494 ps
CPU time 2.8 seconds
Started Jun 23 05:06:26 PM PDT 24
Finished Jun 23 05:06:29 PM PDT 24
Peak memory 218360 kb
Host smart-34815586-a022-44bf-9b76-a8cee1f0bed5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161504053 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_prog_failure.1161504053
Directory /workspace/4.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_regwen_during_op.1164743289
Short name T72
Test name
Test status
Simulation time 168686331 ps
CPU time 4.73 seconds
Started Jun 23 05:06:26 PM PDT 24
Finished Jun 23 05:06:31 PM PDT 24
Peak memory 217392 kb
Host smart-c21544c8-866e-4e1d-a4cc-cec9e8f94924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164743289 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_regwen_during_op.1164743289
Directory /workspace/4.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_cm.350248901
Short name T73
Test name
Test status
Simulation time 1899243820 ps
CPU time 38.7 seconds
Started Jun 23 05:06:24 PM PDT 24
Finished Jun 23 05:07:03 PM PDT 24
Peak memory 282008 kb
Host smart-c912d477-e6a2-4db3-b8d9-2b1a4f451f8e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350248901 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_cm.350248901
Directory /workspace/4.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_mubi.621763992
Short name T595
Test name
Test status
Simulation time 425941778 ps
CPU time 15.06 seconds
Started Jun 23 05:06:22 PM PDT 24
Finished Jun 23 05:06:37 PM PDT 24
Peak memory 219004 kb
Host smart-69ae3c56-693e-4211-b954-c6b2dd1942d5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621763992 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_mubi.621763992
Directory /workspace/4.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_digest.3228207474
Short name T543
Test name
Test status
Simulation time 1202603712 ps
CPU time 8.12 seconds
Started Jun 23 05:06:23 PM PDT 24
Finished Jun 23 05:06:31 PM PDT 24
Peak memory 218104 kb
Host smart-7b1014ce-d76b-4c89-bca2-1ac8e708e846
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228207474 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_di
gest.3228207474
Directory /workspace/4.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_mux.275781123
Short name T697
Test name
Test status
Simulation time 320097688 ps
CPU time 8.43 seconds
Started Jun 23 05:06:25 PM PDT 24
Finished Jun 23 05:06:34 PM PDT 24
Peak memory 218416 kb
Host smart-06e1d6ce-ce85-4c1e-8188-5738186c4cd1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275781123 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_mux.275781123
Directory /workspace/4.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/4.lc_ctrl_security_escalation.4183130824
Short name T221
Test name
Test status
Simulation time 6913834591 ps
CPU time 13.59 seconds
Started Jun 23 05:06:23 PM PDT 24
Finished Jun 23 05:06:37 PM PDT 24
Peak memory 226136 kb
Host smart-c76c7dca-7bee-4750-a6fb-e6ddb712304b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183130824 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_security_escalation.4183130824
Directory /workspace/4.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/4.lc_ctrl_smoke.2918147535
Short name T660
Test name
Test status
Simulation time 78551186 ps
CPU time 3.21 seconds
Started Jun 23 05:06:24 PM PDT 24
Finished Jun 23 05:06:28 PM PDT 24
Peak memory 214736 kb
Host smart-b0ca86df-73bb-48ab-8bf5-22d17f175e6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918147535 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_smoke.2918147535
Directory /workspace/4.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_failure.888492229
Short name T320
Test name
Test status
Simulation time 169792929 ps
CPU time 17.83 seconds
Started Jun 23 05:06:28 PM PDT 24
Finished Jun 23 05:06:47 PM PDT 24
Peak memory 243788 kb
Host smart-b1b3723c-8bf3-44c6-b022-0a915a5000a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888492229 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_failure.888492229
Directory /workspace/4.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_post_trans.463200249
Short name T676
Test name
Test status
Simulation time 66276924 ps
CPU time 9.19 seconds
Started Jun 23 05:06:21 PM PDT 24
Finished Jun 23 05:06:31 PM PDT 24
Peak memory 250900 kb
Host smart-75156dfa-5500-4322-a603-2b49a2bd1439
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463200249 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_post_trans.463200249
Directory /workspace/4.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_stress_all.3780650611
Short name T523
Test name
Test status
Simulation time 9024798602 ps
CPU time 320.88 seconds
Started Jun 23 05:06:24 PM PDT 24
Finished Jun 23 05:11:46 PM PDT 24
Peak memory 272164 kb
Host smart-e52526df-30bd-41e7-ad9b-7c0999219e7e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780650611 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.lc_ctrl_stress_all.3780650611
Directory /workspace/4.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.lc_ctrl_volatile_unlock_smoke.1613773871
Short name T322
Test name
Test status
Simulation time 12692232 ps
CPU time 0.78 seconds
Started Jun 23 05:06:25 PM PDT 24
Finished Jun 23 05:06:26 PM PDT 24
Peak memory 208928 kb
Host smart-ce41efa6-84c1-4a21-afad-983e064e1519
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613773871 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ct
rl_volatile_unlock_smoke.1613773871
Directory /workspace/4.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_alert_test.1571672254
Short name T751
Test name
Test status
Simulation time 15318137 ps
CPU time 0.87 seconds
Started Jun 23 05:09:06 PM PDT 24
Finished Jun 23 05:09:07 PM PDT 24
Peak memory 208828 kb
Host smart-bfbf8243-efd0-4054-96f0-7ba58e0aa957
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571672254 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_alert_test.1571672254
Directory /workspace/40.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.lc_ctrl_errors.1219617593
Short name T527
Test name
Test status
Simulation time 245640013 ps
CPU time 11.21 seconds
Started Jun 23 05:09:15 PM PDT 24
Finished Jun 23 05:09:27 PM PDT 24
Peak memory 218264 kb
Host smart-a13c3851-c65a-4037-b589-66d5d429ba21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219617593 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_errors.1219617593
Directory /workspace/40.lc_ctrl_errors/latest

Test location /workspace/coverage/default/40.lc_ctrl_jtag_access.419962542
Short name T712
Test name
Test status
Simulation time 1331375479 ps
CPU time 16.93 seconds
Started Jun 23 05:09:07 PM PDT 24
Finished Jun 23 05:09:25 PM PDT 24
Peak memory 217504 kb
Host smart-80f6eaaf-f331-4d03-9847-0a395567ad82
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419962542 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_jtag_access.419962542
Directory /workspace/40.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/40.lc_ctrl_prog_failure.3225374511
Short name T260
Test name
Test status
Simulation time 74169020 ps
CPU time 2.73 seconds
Started Jun 23 05:09:08 PM PDT 24
Finished Jun 23 05:09:12 PM PDT 24
Peak memory 218204 kb
Host smart-46c8af43-e8d2-4e78-8a76-83a5be8d08b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225374511 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_prog_failure.3225374511
Directory /workspace/40.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_mubi.3452423183
Short name T565
Test name
Test status
Simulation time 267584564 ps
CPU time 10.99 seconds
Started Jun 23 05:09:08 PM PDT 24
Finished Jun 23 05:09:20 PM PDT 24
Peak memory 218336 kb
Host smart-bd7a139f-6eb6-4610-8608-aab498bb20bb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452423183 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_mubi.3452423183
Directory /workspace/40.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_digest.1885238815
Short name T438
Test name
Test status
Simulation time 1214744189 ps
CPU time 10.39 seconds
Started Jun 23 05:09:06 PM PDT 24
Finished Jun 23 05:09:17 PM PDT 24
Peak memory 226080 kb
Host smart-45570ae6-6c93-4671-adf2-897c840f6224
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885238815 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_d
igest.1885238815
Directory /workspace/40.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_mux.1147808006
Short name T772
Test name
Test status
Simulation time 465961068 ps
CPU time 10.24 seconds
Started Jun 23 05:09:07 PM PDT 24
Finished Jun 23 05:09:18 PM PDT 24
Peak memory 226232 kb
Host smart-47e79ef4-e47e-4ed3-bd31-c36773256520
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147808006 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_mux.
1147808006
Directory /workspace/40.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/40.lc_ctrl_security_escalation.404679498
Short name T391
Test name
Test status
Simulation time 1685162571 ps
CPU time 9.85 seconds
Started Jun 23 05:09:15 PM PDT 24
Finished Jun 23 05:09:26 PM PDT 24
Peak memory 224744 kb
Host smart-29a8a75f-5151-4af1-81ad-d14701caaac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404679498 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_security_escalation.404679498
Directory /workspace/40.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/40.lc_ctrl_smoke.287747758
Short name T827
Test name
Test status
Simulation time 34282027 ps
CPU time 2.01 seconds
Started Jun 23 05:09:08 PM PDT 24
Finished Jun 23 05:09:11 PM PDT 24
Peak memory 214080 kb
Host smart-eef009e1-69d7-4c54-a044-a505ac3c06a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287747758 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_smoke.287747758
Directory /workspace/40.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_failure.479919745
Short name T275
Test name
Test status
Simulation time 1138746952 ps
CPU time 32.01 seconds
Started Jun 23 05:09:07 PM PDT 24
Finished Jun 23 05:09:40 PM PDT 24
Peak memory 250956 kb
Host smart-e54b11f6-34aa-491c-895e-79a9d9859c7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479919745 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_failure.479919745
Directory /workspace/40.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_post_trans.2550177755
Short name T530
Test name
Test status
Simulation time 315559678 ps
CPU time 7.7 seconds
Started Jun 23 05:09:07 PM PDT 24
Finished Jun 23 05:09:16 PM PDT 24
Peak memory 250888 kb
Host smart-f3e7d084-c138-4427-a99d-074f947406dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550177755 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_post_trans.2550177755
Directory /workspace/40.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/40.lc_ctrl_stress_all.1319663642
Short name T647
Test name
Test status
Simulation time 46252681579 ps
CPU time 151.97 seconds
Started Jun 23 05:09:06 PM PDT 24
Finished Jun 23 05:11:39 PM PDT 24
Peak memory 281256 kb
Host smart-786dd84d-662e-4aec-97c2-5a30437ca78d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319663642 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.lc_ctrl_stress_all.1319663642
Directory /workspace/40.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.lc_ctrl_stress_all_with_rand_reset.2102329490
Short name T220
Test name
Test status
Simulation time 84226585062 ps
CPU time 503.47 seconds
Started Jun 23 05:09:06 PM PDT 24
Finished Jun 23 05:17:31 PM PDT 24
Peak memory 283884 kb
Host smart-f56f1cf7-3ebc-430d-8f46-1413a457336c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2102329490 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_stress_all_with_rand_reset.2102329490
Directory /workspace/40.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.lc_ctrl_volatile_unlock_smoke.3799378714
Short name T369
Test name
Test status
Simulation time 121697188 ps
CPU time 0.79 seconds
Started Jun 23 05:09:05 PM PDT 24
Finished Jun 23 05:09:06 PM PDT 24
Peak memory 208860 kb
Host smart-d3f019a5-3af7-41a3-9233-b4779a6e907d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799378714 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_c
trl_volatile_unlock_smoke.3799378714
Directory /workspace/40.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_alert_test.2526755239
Short name T95
Test name
Test status
Simulation time 30417304 ps
CPU time 1.09 seconds
Started Jun 23 05:09:11 PM PDT 24
Finished Jun 23 05:09:12 PM PDT 24
Peak memory 209072 kb
Host smart-5831ca26-03aa-4594-9351-6f0677cd374e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526755239 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_alert_test.2526755239
Directory /workspace/41.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.lc_ctrl_errors.2002310720
Short name T847
Test name
Test status
Simulation time 458260245 ps
CPU time 9.34 seconds
Started Jun 23 05:09:12 PM PDT 24
Finished Jun 23 05:09:22 PM PDT 24
Peak memory 218208 kb
Host smart-6d251214-9f06-4c39-8c80-21107074c0d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002310720 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_errors.2002310720
Directory /workspace/41.lc_ctrl_errors/latest

Test location /workspace/coverage/default/41.lc_ctrl_jtag_access.992058910
Short name T683
Test name
Test status
Simulation time 2228944101 ps
CPU time 6.27 seconds
Started Jun 23 05:09:14 PM PDT 24
Finished Jun 23 05:09:20 PM PDT 24
Peak memory 217612 kb
Host smart-6adfc522-fbe1-45dd-bdec-70a3b0ae64fc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992058910 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_jtag_access.992058910
Directory /workspace/41.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/41.lc_ctrl_prog_failure.3396581140
Short name T537
Test name
Test status
Simulation time 84176712 ps
CPU time 1.86 seconds
Started Jun 23 05:09:17 PM PDT 24
Finished Jun 23 05:09:19 PM PDT 24
Peak memory 218260 kb
Host smart-c344c2ac-d54d-4ee8-bd38-99a9e6468ac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396581140 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_prog_failure.3396581140
Directory /workspace/41.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_mubi.2121463432
Short name T317
Test name
Test status
Simulation time 1674105318 ps
CPU time 14.2 seconds
Started Jun 23 05:09:12 PM PDT 24
Finished Jun 23 05:09:27 PM PDT 24
Peak memory 218864 kb
Host smart-04d8abd1-ddce-43c2-9307-b743d0c7c7ff
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121463432 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_mubi.2121463432
Directory /workspace/41.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_digest.2105558798
Short name T271
Test name
Test status
Simulation time 483270288 ps
CPU time 12.21 seconds
Started Jun 23 05:09:12 PM PDT 24
Finished Jun 23 05:09:25 PM PDT 24
Peak memory 226084 kb
Host smart-e6e7b154-fe46-469f-addd-8f1e22b4ad32
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105558798 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_d
igest.2105558798
Directory /workspace/41.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_mux.1929985464
Short name T616
Test name
Test status
Simulation time 216045179 ps
CPU time 8.96 seconds
Started Jun 23 05:09:11 PM PDT 24
Finished Jun 23 05:09:20 PM PDT 24
Peak memory 218264 kb
Host smart-b0b11a19-53f7-479e-b23e-c1dab581903a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929985464 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_mux.
1929985464
Directory /workspace/41.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/41.lc_ctrl_security_escalation.975991861
Short name T182
Test name
Test status
Simulation time 368771364 ps
CPU time 7.71 seconds
Started Jun 23 05:09:14 PM PDT 24
Finished Jun 23 05:09:22 PM PDT 24
Peak memory 224504 kb
Host smart-1cdd1051-6f1c-4459-be0e-7402973a0eb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975991861 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_security_escalation.975991861
Directory /workspace/41.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/41.lc_ctrl_smoke.2581044614
Short name T819
Test name
Test status
Simulation time 63216571 ps
CPU time 2.24 seconds
Started Jun 23 05:09:13 PM PDT 24
Finished Jun 23 05:09:16 PM PDT 24
Peak memory 217844 kb
Host smart-bc14943a-2b35-40db-99c2-bc9af686ef3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581044614 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_smoke.2581044614
Directory /workspace/41.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_failure.2381357345
Short name T341
Test name
Test status
Simulation time 2835748629 ps
CPU time 24.49 seconds
Started Jun 23 05:09:15 PM PDT 24
Finished Jun 23 05:09:40 PM PDT 24
Peak memory 250868 kb
Host smart-70cd8be3-e36e-410d-8cb9-cc0b1315d1c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381357345 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_failure.2381357345
Directory /workspace/41.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_post_trans.3034252730
Short name T439
Test name
Test status
Simulation time 138959482 ps
CPU time 7.21 seconds
Started Jun 23 05:09:11 PM PDT 24
Finished Jun 23 05:09:19 PM PDT 24
Peak memory 247196 kb
Host smart-62722d43-b6da-4161-8473-126cce06ab74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3034252730 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_post_trans.3034252730
Directory /workspace/41.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all.1211525341
Short name T183
Test name
Test status
Simulation time 4113070165 ps
CPU time 84.26 seconds
Started Jun 23 05:09:12 PM PDT 24
Finished Jun 23 05:10:37 PM PDT 24
Peak memory 273612 kb
Host smart-4d0e3b64-1340-4aa0-8bb3-441997d4c2ff
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211525341 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.lc_ctrl_stress_all.1211525341
Directory /workspace/41.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.lc_ctrl_volatile_unlock_smoke.2172174002
Short name T414
Test name
Test status
Simulation time 15561668 ps
CPU time 0.82 seconds
Started Jun 23 05:09:11 PM PDT 24
Finished Jun 23 05:09:13 PM PDT 24
Peak memory 209120 kb
Host smart-94d7509f-5ea9-49d2-8298-f1f5e11440ab
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172174002 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_c
trl_volatile_unlock_smoke.2172174002
Directory /workspace/41.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_alert_test.1241339132
Short name T245
Test name
Test status
Simulation time 30133678 ps
CPU time 1.12 seconds
Started Jun 23 05:09:29 PM PDT 24
Finished Jun 23 05:09:31 PM PDT 24
Peak memory 209020 kb
Host smart-686238f5-479c-4a2e-bd05-df6783be0376
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241339132 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_alert_test.1241339132
Directory /workspace/42.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.lc_ctrl_errors.3730411402
Short name T605
Test name
Test status
Simulation time 336353970 ps
CPU time 12.79 seconds
Started Jun 23 05:09:17 PM PDT 24
Finished Jun 23 05:09:30 PM PDT 24
Peak memory 218264 kb
Host smart-d89cebcd-595d-4a74-a085-6b5adef7b574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730411402 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_errors.3730411402
Directory /workspace/42.lc_ctrl_errors/latest

Test location /workspace/coverage/default/42.lc_ctrl_jtag_access.3653891480
Short name T519
Test name
Test status
Simulation time 3260538517 ps
CPU time 19.02 seconds
Started Jun 23 05:09:20 PM PDT 24
Finished Jun 23 05:09:39 PM PDT 24
Peak memory 217752 kb
Host smart-81ec7a47-3f50-4665-b169-d895bb2239e6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653891480 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_jtag_access.3653891480
Directory /workspace/42.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/42.lc_ctrl_prog_failure.406550471
Short name T450
Test name
Test status
Simulation time 31608357 ps
CPU time 2.17 seconds
Started Jun 23 05:09:18 PM PDT 24
Finished Jun 23 05:09:21 PM PDT 24
Peak memory 222408 kb
Host smart-3bac8e80-9890-4cbd-96cc-a29f91f9152d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406550471 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_prog_failure.406550471
Directory /workspace/42.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_mubi.3152972096
Short name T699
Test name
Test status
Simulation time 229261989 ps
CPU time 9.43 seconds
Started Jun 23 05:09:17 PM PDT 24
Finished Jun 23 05:09:27 PM PDT 24
Peak memory 218936 kb
Host smart-4e93d907-9ac9-416b-aa29-fe006106eae8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152972096 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_mubi.3152972096
Directory /workspace/42.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_digest.3726589373
Short name T228
Test name
Test status
Simulation time 392943454 ps
CPU time 14.31 seconds
Started Jun 23 05:09:18 PM PDT 24
Finished Jun 23 05:09:33 PM PDT 24
Peak memory 218268 kb
Host smart-2cb4d0a7-a10c-4166-b544-ce561337bfde
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726589373 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_d
igest.3726589373
Directory /workspace/42.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_mux.3986460571
Short name T598
Test name
Test status
Simulation time 759824001 ps
CPU time 9.09 seconds
Started Jun 23 05:09:19 PM PDT 24
Finished Jun 23 05:09:29 PM PDT 24
Peak memory 218260 kb
Host smart-951f361b-fce0-48a6-9859-2ca900821aa9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986460571 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_mux.
3986460571
Directory /workspace/42.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/42.lc_ctrl_smoke.2764002852
Short name T493
Test name
Test status
Simulation time 456304939 ps
CPU time 4.85 seconds
Started Jun 23 05:09:20 PM PDT 24
Finished Jun 23 05:09:26 PM PDT 24
Peak memory 217724 kb
Host smart-1adc43db-4ca3-4418-9fb1-6777f760f0ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764002852 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_smoke.2764002852
Directory /workspace/42.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_failure.3076580089
Short name T307
Test name
Test status
Simulation time 190623125 ps
CPU time 19.13 seconds
Started Jun 23 05:09:23 PM PDT 24
Finished Jun 23 05:09:43 PM PDT 24
Peak memory 250972 kb
Host smart-88b70c4a-2413-4a8e-ac9a-9c45db5919fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076580089 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_failure.3076580089
Directory /workspace/42.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_post_trans.1538397933
Short name T871
Test name
Test status
Simulation time 165591485 ps
CPU time 8.42 seconds
Started Jun 23 05:09:16 PM PDT 24
Finished Jun 23 05:09:25 PM PDT 24
Peak memory 251004 kb
Host smart-2c70a440-3328-4367-8bb7-c0a14e90c9ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538397933 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_post_trans.1538397933
Directory /workspace/42.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/42.lc_ctrl_stress_all_with_rand_reset.1627566819
Short name T164
Test name
Test status
Simulation time 48107605315 ps
CPU time 971.43 seconds
Started Jun 23 05:09:22 PM PDT 24
Finished Jun 23 05:25:34 PM PDT 24
Peak memory 316616 kb
Host smart-5c5d844e-4852-4310-af99-60245ac04de8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1627566819 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_stress_all_with_rand_reset.1627566819
Directory /workspace/42.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.lc_ctrl_volatile_unlock_smoke.2297378109
Short name T318
Test name
Test status
Simulation time 40216715 ps
CPU time 0.82 seconds
Started Jun 23 05:09:17 PM PDT 24
Finished Jun 23 05:09:18 PM PDT 24
Peak memory 208980 kb
Host smart-4655c1c0-c320-4d92-a071-9fa446cab276
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297378109 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_c
trl_volatile_unlock_smoke.2297378109
Directory /workspace/42.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_alert_test.744685130
Short name T247
Test name
Test status
Simulation time 14987432 ps
CPU time 0.88 seconds
Started Jun 23 05:09:31 PM PDT 24
Finished Jun 23 05:09:32 PM PDT 24
Peak memory 208784 kb
Host smart-de01d2d1-7c8e-4718-8352-f01c070e23be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744685130 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_alert_test.744685130
Directory /workspace/43.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.lc_ctrl_errors.920482746
Short name T619
Test name
Test status
Simulation time 670271073 ps
CPU time 17.59 seconds
Started Jun 23 05:09:24 PM PDT 24
Finished Jun 23 05:09:42 PM PDT 24
Peak memory 218148 kb
Host smart-9e132cb9-4480-4471-b8d9-245226d8cb5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920482746 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_errors.920482746
Directory /workspace/43.lc_ctrl_errors/latest

Test location /workspace/coverage/default/43.lc_ctrl_jtag_access.4173986227
Short name T394
Test name
Test status
Simulation time 120810976 ps
CPU time 1.88 seconds
Started Jun 23 05:09:23 PM PDT 24
Finished Jun 23 05:09:25 PM PDT 24
Peak memory 217188 kb
Host smart-21356dd4-eac1-417a-b670-4ab9f05d32f8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173986227 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_jtag_access.4173986227
Directory /workspace/43.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/43.lc_ctrl_prog_failure.3584302037
Short name T831
Test name
Test status
Simulation time 155057858 ps
CPU time 1.9 seconds
Started Jun 23 05:09:24 PM PDT 24
Finished Jun 23 05:09:27 PM PDT 24
Peak memory 218228 kb
Host smart-08e0e0cd-8223-45a9-805f-a25f1f98c582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584302037 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_prog_failure.3584302037
Directory /workspace/43.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_digest.2062231032
Short name T666
Test name
Test status
Simulation time 301217139 ps
CPU time 13.22 seconds
Started Jun 23 05:09:29 PM PDT 24
Finished Jun 23 05:09:43 PM PDT 24
Peak memory 218240 kb
Host smart-6914304f-171b-4ae5-8a72-25ad1f5ea070
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062231032 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_d
igest.2062231032
Directory /workspace/43.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_mux.2175431930
Short name T703
Test name
Test status
Simulation time 690390679 ps
CPU time 10.35 seconds
Started Jun 23 05:09:25 PM PDT 24
Finished Jun 23 05:09:36 PM PDT 24
Peak memory 218276 kb
Host smart-5bf6d18a-1b3c-487d-a877-1b0bc1f96388
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175431930 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_mux.
2175431930
Directory /workspace/43.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/43.lc_ctrl_security_escalation.1020301476
Short name T534
Test name
Test status
Simulation time 312142727 ps
CPU time 8.76 seconds
Started Jun 23 05:09:24 PM PDT 24
Finished Jun 23 05:09:33 PM PDT 24
Peak memory 225164 kb
Host smart-7ab18195-4ea1-4f5c-8627-1e93578a2569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020301476 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_security_escalation.1020301476
Directory /workspace/43.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/43.lc_ctrl_smoke.3730507659
Short name T309
Test name
Test status
Simulation time 97138012 ps
CPU time 3.81 seconds
Started Jun 23 05:09:26 PM PDT 24
Finished Jun 23 05:09:30 PM PDT 24
Peak memory 217756 kb
Host smart-086f4410-ba13-45a8-9097-7e7013c92973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730507659 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_smoke.3730507659
Directory /workspace/43.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_failure.3771861879
Short name T547
Test name
Test status
Simulation time 995798956 ps
CPU time 31.23 seconds
Started Jun 23 05:09:23 PM PDT 24
Finished Jun 23 05:09:54 PM PDT 24
Peak memory 250924 kb
Host smart-912a6c83-1334-4f75-adb6-bbf6594b08f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771861879 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_failure.3771861879
Directory /workspace/43.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_post_trans.2822346987
Short name T94
Test name
Test status
Simulation time 151819068 ps
CPU time 8.21 seconds
Started Jun 23 05:09:23 PM PDT 24
Finished Jun 23 05:09:32 PM PDT 24
Peak memory 250908 kb
Host smart-95233f63-d0cf-4d6c-8d91-154d91a84852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822346987 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_post_trans.2822346987
Directory /workspace/43.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all.537067990
Short name T279
Test name
Test status
Simulation time 22598526368 ps
CPU time 249.37 seconds
Started Jun 23 05:09:22 PM PDT 24
Finished Jun 23 05:13:32 PM PDT 24
Peak memory 228440 kb
Host smart-3a518bef-40d6-4833-86f3-4958e06917ed
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537067990 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.lc_ctrl_stress_all.537067990
Directory /workspace/43.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all_with_rand_reset.528925322
Short name T150
Test name
Test status
Simulation time 34340233441 ps
CPU time 410.62 seconds
Started Jun 23 05:09:24 PM PDT 24
Finished Jun 23 05:16:16 PM PDT 24
Peak memory 283756 kb
Host smart-23b58996-30e7-4414-a29b-9fa6cbac1a09
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=528925322 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_stress_all_with_rand_reset.528925322
Directory /workspace/43.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.lc_ctrl_volatile_unlock_smoke.3180957370
Short name T276
Test name
Test status
Simulation time 14307913 ps
CPU time 0.91 seconds
Started Jun 23 05:09:24 PM PDT 24
Finished Jun 23 05:09:25 PM PDT 24
Peak memory 208988 kb
Host smart-355c8ad3-f1f3-402d-82c9-6d7a90ff8df0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180957370 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_c
trl_volatile_unlock_smoke.3180957370
Directory /workspace/43.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_alert_test.2716385743
Short name T291
Test name
Test status
Simulation time 155172162 ps
CPU time 1.01 seconds
Started Jun 23 05:09:28 PM PDT 24
Finished Jun 23 05:09:29 PM PDT 24
Peak memory 208976 kb
Host smart-6ca8a185-54ca-4e44-b52c-0be7cf3ec5a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716385743 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_alert_test.2716385743
Directory /workspace/44.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.lc_ctrl_errors.2916958223
Short name T742
Test name
Test status
Simulation time 692664256 ps
CPU time 17.67 seconds
Started Jun 23 05:09:28 PM PDT 24
Finished Jun 23 05:09:46 PM PDT 24
Peak memory 218336 kb
Host smart-02d9a572-eaa4-40af-a530-d2b8a31b0983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916958223 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_errors.2916958223
Directory /workspace/44.lc_ctrl_errors/latest

Test location /workspace/coverage/default/44.lc_ctrl_jtag_access.1292951384
Short name T541
Test name
Test status
Simulation time 1281653154 ps
CPU time 11.79 seconds
Started Jun 23 05:09:28 PM PDT 24
Finished Jun 23 05:09:40 PM PDT 24
Peak memory 217508 kb
Host smart-43dd0ce4-ef0b-42e5-aec3-a5b6f39a8b66
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292951384 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_jtag_access.1292951384
Directory /workspace/44.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/44.lc_ctrl_prog_failure.3477479422
Short name T101
Test name
Test status
Simulation time 87472428 ps
CPU time 3.18 seconds
Started Jun 23 05:09:30 PM PDT 24
Finished Jun 23 05:09:33 PM PDT 24
Peak memory 222720 kb
Host smart-d63ef48d-70c0-440f-9e74-fffafd5e0663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477479422 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_prog_failure.3477479422
Directory /workspace/44.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_mubi.2756473873
Short name T629
Test name
Test status
Simulation time 454339421 ps
CPU time 9.74 seconds
Started Jun 23 05:09:31 PM PDT 24
Finished Jun 23 05:09:41 PM PDT 24
Peak memory 225980 kb
Host smart-4e05984b-5396-4085-92f4-3fc44793c921
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756473873 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_mubi.2756473873
Directory /workspace/44.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_digest.3321826772
Short name T297
Test name
Test status
Simulation time 2694137004 ps
CPU time 14.2 seconds
Started Jun 23 05:09:29 PM PDT 24
Finished Jun 23 05:09:44 PM PDT 24
Peak memory 226124 kb
Host smart-4eb0f0ec-c5d8-4b08-803f-a0ac26e2f3b6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321826772 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_d
igest.3321826772
Directory /workspace/44.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_mux.2768470482
Short name T714
Test name
Test status
Simulation time 497606021 ps
CPU time 11.9 seconds
Started Jun 23 05:09:30 PM PDT 24
Finished Jun 23 05:09:42 PM PDT 24
Peak memory 218260 kb
Host smart-8ce59fd4-bd18-4513-9866-0783ff3ee73b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768470482 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_mux.
2768470482
Directory /workspace/44.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/44.lc_ctrl_security_escalation.416194413
Short name T573
Test name
Test status
Simulation time 776655452 ps
CPU time 11.22 seconds
Started Jun 23 05:09:31 PM PDT 24
Finished Jun 23 05:09:43 PM PDT 24
Peak memory 226032 kb
Host smart-703abecf-1f31-4c17-923d-7bd5db66cd09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416194413 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_security_escalation.416194413
Directory /workspace/44.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/44.lc_ctrl_smoke.3829902712
Short name T698
Test name
Test status
Simulation time 73578446 ps
CPU time 2.21 seconds
Started Jun 23 05:09:27 PM PDT 24
Finished Jun 23 05:09:29 PM PDT 24
Peak memory 214180 kb
Host smart-1d10caf4-64e7-4da0-9d66-7c9f8037941b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829902712 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_smoke.3829902712
Directory /workspace/44.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_failure.2637053151
Short name T358
Test name
Test status
Simulation time 6130583844 ps
CPU time 25.86 seconds
Started Jun 23 05:09:29 PM PDT 24
Finished Jun 23 05:09:55 PM PDT 24
Peak memory 250944 kb
Host smart-d91122b9-c7fc-45ce-8a77-79d93919446e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637053151 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_failure.2637053151
Directory /workspace/44.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_post_trans.2021767459
Short name T587
Test name
Test status
Simulation time 335852290 ps
CPU time 7.6 seconds
Started Jun 23 05:09:36 PM PDT 24
Finished Jun 23 05:09:44 PM PDT 24
Peak memory 250872 kb
Host smart-e067a056-f13b-4555-8f04-deeab5efd6de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021767459 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_post_trans.2021767459
Directory /workspace/44.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/44.lc_ctrl_stress_all.2368867529
Short name T426
Test name
Test status
Simulation time 24451087567 ps
CPU time 130.68 seconds
Started Jun 23 05:09:30 PM PDT 24
Finished Jun 23 05:11:41 PM PDT 24
Peak memory 332872 kb
Host smart-053c9160-4208-4fa2-89b0-125be301e48c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368867529 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.lc_ctrl_stress_all.2368867529
Directory /workspace/44.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.lc_ctrl_volatile_unlock_smoke.18556375
Short name T800
Test name
Test status
Simulation time 18845739 ps
CPU time 0.82 seconds
Started Jun 23 05:09:27 PM PDT 24
Finished Jun 23 05:09:28 PM PDT 24
Peak memory 208996 kb
Host smart-84957daa-3611-4441-af92-dfa24b87acd1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18556375 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vol
atile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctr
l_volatile_unlock_smoke.18556375
Directory /workspace/44.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_alert_test.3449145736
Short name T280
Test name
Test status
Simulation time 41267434 ps
CPU time 1.24 seconds
Started Jun 23 05:09:34 PM PDT 24
Finished Jun 23 05:09:35 PM PDT 24
Peak memory 208964 kb
Host smart-4143b954-942d-43c6-ac91-11a8eaf5864b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449145736 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_alert_test.3449145736
Directory /workspace/45.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.lc_ctrl_errors.2055760707
Short name T278
Test name
Test status
Simulation time 341536776 ps
CPU time 11.33 seconds
Started Jun 23 05:09:36 PM PDT 24
Finished Jun 23 05:09:48 PM PDT 24
Peak memory 218236 kb
Host smart-acd25561-9478-4402-bdec-3300e88904a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055760707 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_errors.2055760707
Directory /workspace/45.lc_ctrl_errors/latest

Test location /workspace/coverage/default/45.lc_ctrl_jtag_access.498239177
Short name T513
Test name
Test status
Simulation time 258885392 ps
CPU time 3.32 seconds
Started Jun 23 05:09:32 PM PDT 24
Finished Jun 23 05:09:35 PM PDT 24
Peak memory 217204 kb
Host smart-004c34fe-a1f1-4345-9965-c361445d3c3d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498239177 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_jtag_access.498239177
Directory /workspace/45.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/45.lc_ctrl_prog_failure.3567755930
Short name T354
Test name
Test status
Simulation time 46700697 ps
CPU time 2.36 seconds
Started Jun 23 05:09:35 PM PDT 24
Finished Jun 23 05:09:38 PM PDT 24
Peak memory 218200 kb
Host smart-dfbda430-12ca-4ffb-a2dd-f3421e1e1ed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567755930 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_prog_failure.3567755930
Directory /workspace/45.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_mubi.1542455216
Short name T38
Test name
Test status
Simulation time 213341317 ps
CPU time 11.4 seconds
Started Jun 23 05:09:36 PM PDT 24
Finished Jun 23 05:09:48 PM PDT 24
Peak memory 218932 kb
Host smart-96d8a705-68ac-4b13-90b6-cb55ffeab486
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542455216 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_mubi.1542455216
Directory /workspace/45.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_digest.1770272782
Short name T430
Test name
Test status
Simulation time 1269682633 ps
CPU time 22.38 seconds
Started Jun 23 05:09:36 PM PDT 24
Finished Jun 23 05:09:59 PM PDT 24
Peak memory 218272 kb
Host smart-7a58fd63-2f0e-470a-ad67-f0ca6b87d6c6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770272782 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_d
igest.1770272782
Directory /workspace/45.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_mux.4276336090
Short name T469
Test name
Test status
Simulation time 316591369 ps
CPU time 9.54 seconds
Started Jun 23 05:09:36 PM PDT 24
Finished Jun 23 05:09:46 PM PDT 24
Peak memory 218220 kb
Host smart-4eacd10f-cda3-40b2-9273-38e9f24637f7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276336090 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_mux.
4276336090
Directory /workspace/45.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/45.lc_ctrl_security_escalation.2767204669
Short name T682
Test name
Test status
Simulation time 610699698 ps
CPU time 8.05 seconds
Started Jun 23 05:09:35 PM PDT 24
Finished Jun 23 05:09:44 PM PDT 24
Peak memory 225012 kb
Host smart-bb97d4cd-b5a8-46fe-8ffe-bf85b4a93cd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767204669 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_security_escalation.2767204669
Directory /workspace/45.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/45.lc_ctrl_smoke.734343933
Short name T416
Test name
Test status
Simulation time 109052713 ps
CPU time 1.22 seconds
Started Jun 23 05:09:37 PM PDT 24
Finished Jun 23 05:09:39 PM PDT 24
Peak memory 213612 kb
Host smart-c4de223d-2836-46e3-9a85-17947d2cb24d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734343933 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_smoke.734343933
Directory /workspace/45.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_failure.4188391868
Short name T816
Test name
Test status
Simulation time 296676405 ps
CPU time 27.03 seconds
Started Jun 23 05:09:46 PM PDT 24
Finished Jun 23 05:10:14 PM PDT 24
Peak memory 250880 kb
Host smart-2703e93b-1090-40f6-9073-c877b3aaefe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188391868 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_failure.4188391868
Directory /workspace/45.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_post_trans.2175185621
Short name T702
Test name
Test status
Simulation time 71999937 ps
CPU time 6.52 seconds
Started Jun 23 05:09:34 PM PDT 24
Finished Jun 23 05:09:40 PM PDT 24
Peak memory 244320 kb
Host smart-07e5f8b0-7f3e-4ca0-83b3-fa00d8470414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175185621 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_post_trans.2175185621
Directory /workspace/45.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/45.lc_ctrl_stress_all.2089415365
Short name T401
Test name
Test status
Simulation time 7451135300 ps
CPU time 56.22 seconds
Started Jun 23 05:09:46 PM PDT 24
Finished Jun 23 05:10:43 PM PDT 24
Peak memory 226068 kb
Host smart-f8f5afd9-1f44-40ff-ba62-0a081d6cfbaa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089415365 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.lc_ctrl_stress_all.2089415365
Directory /workspace/45.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.lc_ctrl_volatile_unlock_smoke.384165430
Short name T851
Test name
Test status
Simulation time 14627418 ps
CPU time 0.99 seconds
Started Jun 23 05:09:35 PM PDT 24
Finished Jun 23 05:09:36 PM PDT 24
Peak memory 209252 kb
Host smart-6ab8b1db-2ba5-4206-a570-c0976e215c6f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384165430 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ct
rl_volatile_unlock_smoke.384165430
Directory /workspace/45.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_alert_test.3971701705
Short name T169
Test name
Test status
Simulation time 41610156 ps
CPU time 0.96 seconds
Started Jun 23 05:09:42 PM PDT 24
Finished Jun 23 05:09:43 PM PDT 24
Peak memory 209012 kb
Host smart-ade4a5b4-b58c-4e69-b4d6-f6eb91241b52
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971701705 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_alert_test.3971701705
Directory /workspace/46.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.lc_ctrl_errors.3700603343
Short name T31
Test name
Test status
Simulation time 259625965 ps
CPU time 10.16 seconds
Started Jun 23 05:09:38 PM PDT 24
Finished Jun 23 05:09:49 PM PDT 24
Peak memory 218132 kb
Host smart-33f0db4d-3e59-4336-868e-9bf6b0f172f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700603343 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_errors.3700603343
Directory /workspace/46.lc_ctrl_errors/latest

Test location /workspace/coverage/default/46.lc_ctrl_jtag_access.3994520495
Short name T24
Test name
Test status
Simulation time 1429093334 ps
CPU time 4.96 seconds
Started Jun 23 05:09:39 PM PDT 24
Finished Jun 23 05:09:45 PM PDT 24
Peak memory 217232 kb
Host smart-2cc11d16-166f-49c5-aba3-5c024d39e1b0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994520495 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_jtag_access.3994520495
Directory /workspace/46.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/46.lc_ctrl_prog_failure.3971218626
Short name T848
Test name
Test status
Simulation time 33017142 ps
CPU time 2.32 seconds
Started Jun 23 05:09:34 PM PDT 24
Finished Jun 23 05:09:37 PM PDT 24
Peak memory 222344 kb
Host smart-726f89b1-e1b3-49c8-b7a9-33ef2952bd39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971218626 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_prog_failure.3971218626
Directory /workspace/46.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_mubi.633670001
Short name T557
Test name
Test status
Simulation time 396386806 ps
CPU time 12.39 seconds
Started Jun 23 05:09:38 PM PDT 24
Finished Jun 23 05:09:51 PM PDT 24
Peak memory 218340 kb
Host smart-470fd3b2-b792-42a4-a420-8f25f011177b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633670001 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_mubi.633670001
Directory /workspace/46.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_digest.3040134521
Short name T429
Test name
Test status
Simulation time 532796030 ps
CPU time 12.24 seconds
Started Jun 23 05:09:42 PM PDT 24
Finished Jun 23 05:09:55 PM PDT 24
Peak memory 225952 kb
Host smart-40c5e159-ba40-4a4b-b4e5-7451f1d4f79d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040134521 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_d
igest.3040134521
Directory /workspace/46.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_mux.3548104582
Short name T588
Test name
Test status
Simulation time 1040055825 ps
CPU time 9.95 seconds
Started Jun 23 05:09:41 PM PDT 24
Finished Jun 23 05:09:52 PM PDT 24
Peak memory 218264 kb
Host smart-bb0d1f4e-c9e9-4657-9bfd-215383ae7587
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548104582 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_mux.
3548104582
Directory /workspace/46.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/46.lc_ctrl_security_escalation.4220254101
Short name T377
Test name
Test status
Simulation time 386258424 ps
CPU time 10.41 seconds
Started Jun 23 05:09:39 PM PDT 24
Finished Jun 23 05:09:50 PM PDT 24
Peak memory 226064 kb
Host smart-a9a4e2ab-8386-4f13-8e4d-97c6c966a908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220254101 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_security_escalation.4220254101
Directory /workspace/46.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/46.lc_ctrl_smoke.2254230352
Short name T838
Test name
Test status
Simulation time 24100104 ps
CPU time 1 seconds
Started Jun 23 05:09:34 PM PDT 24
Finished Jun 23 05:09:35 PM PDT 24
Peak memory 212012 kb
Host smart-f77d4bcf-df37-4553-9e41-08f5557228e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254230352 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_smoke.2254230352
Directory /workspace/46.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_failure.2387942986
Short name T287
Test name
Test status
Simulation time 738608896 ps
CPU time 25.34 seconds
Started Jun 23 05:09:33 PM PDT 24
Finished Jun 23 05:09:59 PM PDT 24
Peak memory 250996 kb
Host smart-a067dd36-f061-435b-b9b2-bf98087ef6eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387942986 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_failure.2387942986
Directory /workspace/46.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_post_trans.2429172854
Short name T688
Test name
Test status
Simulation time 74405580 ps
CPU time 7.08 seconds
Started Jun 23 05:09:33 PM PDT 24
Finished Jun 23 05:09:40 PM PDT 24
Peak memory 250992 kb
Host smart-dc4885ed-3935-47b6-aaf1-3ea1b329bfa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429172854 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_post_trans.2429172854
Directory /workspace/46.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all.1498228071
Short name T409
Test name
Test status
Simulation time 19635366546 ps
CPU time 158.37 seconds
Started Jun 23 05:09:40 PM PDT 24
Finished Jun 23 05:12:19 PM PDT 24
Peak memory 278156 kb
Host smart-53729dcf-0ecc-4343-8a7a-c9298bfddf00
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498228071 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.lc_ctrl_stress_all.1498228071
Directory /workspace/46.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.lc_ctrl_volatile_unlock_smoke.3875507589
Short name T825
Test name
Test status
Simulation time 39998499 ps
CPU time 0.92 seconds
Started Jun 23 05:09:46 PM PDT 24
Finished Jun 23 05:09:48 PM PDT 24
Peak memory 211924 kb
Host smart-ebc116dc-46ba-4d2a-8f8a-a2e7e1d12b86
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875507589 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_c
trl_volatile_unlock_smoke.3875507589
Directory /workspace/46.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_alert_test.1233516452
Short name T336
Test name
Test status
Simulation time 20429015 ps
CPU time 0.99 seconds
Started Jun 23 05:09:49 PM PDT 24
Finished Jun 23 05:09:50 PM PDT 24
Peak memory 208960 kb
Host smart-957f449f-cd0d-4fef-b8f0-25d9aa9f65be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233516452 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_alert_test.1233516452
Directory /workspace/47.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.lc_ctrl_errors.4106410120
Short name T39
Test name
Test status
Simulation time 608451518 ps
CPU time 19.28 seconds
Started Jun 23 05:09:44 PM PDT 24
Finished Jun 23 05:10:04 PM PDT 24
Peak memory 218288 kb
Host smart-624d5958-cc56-43d0-a8b6-9d7b8c344ddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106410120 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_errors.4106410120
Directory /workspace/47.lc_ctrl_errors/latest

Test location /workspace/coverage/default/47.lc_ctrl_jtag_access.2753844191
Short name T583
Test name
Test status
Simulation time 654540236 ps
CPU time 2.15 seconds
Started Jun 23 05:09:47 PM PDT 24
Finished Jun 23 05:09:50 PM PDT 24
Peak memory 217000 kb
Host smart-12d42a95-54b0-4760-a01b-efec4613f2cc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753844191 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_jtag_access.2753844191
Directory /workspace/47.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/47.lc_ctrl_prog_failure.2313547969
Short name T155
Test name
Test status
Simulation time 124977266 ps
CPU time 4.77 seconds
Started Jun 23 05:09:43 PM PDT 24
Finished Jun 23 05:09:49 PM PDT 24
Peak memory 222728 kb
Host smart-7a870788-d6b9-490a-9ca4-b13d26595864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313547969 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_prog_failure.2313547969
Directory /workspace/47.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_mubi.3661688123
Short name T624
Test name
Test status
Simulation time 1671736985 ps
CPU time 18.99 seconds
Started Jun 23 05:09:48 PM PDT 24
Finished Jun 23 05:10:08 PM PDT 24
Peak memory 218868 kb
Host smart-93b019e4-c975-498f-8602-8bb81fd2b122
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661688123 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_mubi.3661688123
Directory /workspace/47.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_digest.736753685
Short name T189
Test name
Test status
Simulation time 343420427 ps
CPU time 12.07 seconds
Started Jun 23 05:09:44 PM PDT 24
Finished Jun 23 05:09:57 PM PDT 24
Peak memory 226056 kb
Host smart-60d5799f-398c-4914-aaee-6ff0651d1c3c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736753685 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_di
gest.736753685
Directory /workspace/47.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_mux.3145742417
Short name T873
Test name
Test status
Simulation time 303941377 ps
CPU time 12.24 seconds
Started Jun 23 05:09:48 PM PDT 24
Finished Jun 23 05:10:01 PM PDT 24
Peak memory 225972 kb
Host smart-eb8ef0f7-383f-4a75-bd43-0fe356b4c726
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145742417 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_mux.
3145742417
Directory /workspace/47.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/47.lc_ctrl_security_escalation.2675068097
Short name T649
Test name
Test status
Simulation time 316015433 ps
CPU time 11.94 seconds
Started Jun 23 05:09:47 PM PDT 24
Finished Jun 23 05:10:00 PM PDT 24
Peak memory 218284 kb
Host smart-a2649ea0-5c60-4f38-b8a2-0aea063a01ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675068097 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_security_escalation.2675068097
Directory /workspace/47.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/47.lc_ctrl_smoke.3233102450
Short name T191
Test name
Test status
Simulation time 139281162 ps
CPU time 2.31 seconds
Started Jun 23 05:09:44 PM PDT 24
Finished Jun 23 05:09:47 PM PDT 24
Peak memory 214672 kb
Host smart-ebee9bfb-8380-4105-b96c-94d97092e32e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233102450 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_smoke.3233102450
Directory /workspace/47.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_failure.3215924069
Short name T525
Test name
Test status
Simulation time 994523745 ps
CPU time 23.74 seconds
Started Jun 23 05:09:39 PM PDT 24
Finished Jun 23 05:10:03 PM PDT 24
Peak memory 250844 kb
Host smart-a7475ecb-58d8-46d0-9976-cb317018e42f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215924069 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_failure.3215924069
Directory /workspace/47.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_post_trans.1916186538
Short name T468
Test name
Test status
Simulation time 42407930 ps
CPU time 6.56 seconds
Started Jun 23 05:09:41 PM PDT 24
Finished Jun 23 05:09:48 PM PDT 24
Peak memory 250272 kb
Host smart-2f1ca386-ca04-4655-ab56-579aecd24b47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1916186538 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_post_trans.1916186538
Directory /workspace/47.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/47.lc_ctrl_stress_all.2060704828
Short name T502
Test name
Test status
Simulation time 2948346652 ps
CPU time 93.92 seconds
Started Jun 23 05:09:44 PM PDT 24
Finished Jun 23 05:11:19 PM PDT 24
Peak memory 231576 kb
Host smart-a740447a-7bd0-4107-9b32-20f8e3cde98b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060704828 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.lc_ctrl_stress_all.2060704828
Directory /workspace/47.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.lc_ctrl_stress_all_with_rand_reset.2528342146
Short name T52
Test name
Test status
Simulation time 50005629331 ps
CPU time 933.25 seconds
Started Jun 23 05:09:44 PM PDT 24
Finished Jun 23 05:25:18 PM PDT 24
Peak memory 447680 kb
Host smart-f117258d-2bf2-4b7d-a23c-aa30192b83a5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2528342146 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_stress_all_with_rand_reset.2528342146
Directory /workspace/47.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.lc_ctrl_volatile_unlock_smoke.1415481489
Short name T669
Test name
Test status
Simulation time 29621309 ps
CPU time 0.74 seconds
Started Jun 23 05:09:40 PM PDT 24
Finished Jun 23 05:09:42 PM PDT 24
Peak memory 207492 kb
Host smart-82b4abc6-41ed-4f49-863b-a53ef5bc9779
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415481489 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_c
trl_volatile_unlock_smoke.1415481489
Directory /workspace/47.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_alert_test.1483281712
Short name T97
Test name
Test status
Simulation time 45836994 ps
CPU time 1.02 seconds
Started Jun 23 05:09:45 PM PDT 24
Finished Jun 23 05:09:47 PM PDT 24
Peak memory 209028 kb
Host smart-e1ad0ad1-a3fb-4bd7-9f34-75cd50ffae07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483281712 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_alert_test.1483281712
Directory /workspace/48.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.lc_ctrl_errors.3552547237
Short name T542
Test name
Test status
Simulation time 317661044 ps
CPU time 9.96 seconds
Started Jun 23 05:09:46 PM PDT 24
Finished Jun 23 05:09:57 PM PDT 24
Peak memory 218168 kb
Host smart-9bccc4f9-be3d-4a79-8dbe-4c700ada3034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552547237 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_errors.3552547237
Directory /workspace/48.lc_ctrl_errors/latest

Test location /workspace/coverage/default/48.lc_ctrl_jtag_access.794463292
Short name T675
Test name
Test status
Simulation time 782957838 ps
CPU time 4.83 seconds
Started Jun 23 05:09:46 PM PDT 24
Finished Jun 23 05:09:51 PM PDT 24
Peak memory 217180 kb
Host smart-3c616cc9-9299-40c0-9d82-b0168de1345a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794463292 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_jtag_access.794463292
Directory /workspace/48.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/48.lc_ctrl_prog_failure.3498635256
Short name T299
Test name
Test status
Simulation time 68722017 ps
CPU time 2.67 seconds
Started Jun 23 05:09:48 PM PDT 24
Finished Jun 23 05:09:51 PM PDT 24
Peak memory 218232 kb
Host smart-2d296554-aedf-4ede-829c-9f2f67f61d3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3498635256 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_prog_failure.3498635256
Directory /workspace/48.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_mubi.294352752
Short name T738
Test name
Test status
Simulation time 1629444886 ps
CPU time 13.49 seconds
Started Jun 23 05:09:50 PM PDT 24
Finished Jun 23 05:10:05 PM PDT 24
Peak memory 218940 kb
Host smart-662ebe6f-0cf2-4150-b7ce-5a92cf650d1d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294352752 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_mubi.294352752
Directory /workspace/48.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_digest.2747833690
Short name T361
Test name
Test status
Simulation time 309721614 ps
CPU time 12.06 seconds
Started Jun 23 05:09:47 PM PDT 24
Finished Jun 23 05:10:00 PM PDT 24
Peak memory 218136 kb
Host smart-d05421db-d9b0-43c5-9c58-929e9ae8e3cb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747833690 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_d
igest.2747833690
Directory /workspace/48.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_mux.1339727721
Short name T452
Test name
Test status
Simulation time 1428640768 ps
CPU time 10.47 seconds
Started Jun 23 05:09:47 PM PDT 24
Finished Jun 23 05:09:58 PM PDT 24
Peak memory 218224 kb
Host smart-321797eb-1884-4d6d-ab0c-20def753766c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339727721 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_mux.
1339727721
Directory /workspace/48.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/48.lc_ctrl_security_escalation.3967081442
Short name T634
Test name
Test status
Simulation time 518504066 ps
CPU time 11.34 seconds
Started Jun 23 05:09:45 PM PDT 24
Finished Jun 23 05:09:57 PM PDT 24
Peak memory 218372 kb
Host smart-0d461310-3160-44e7-a22d-8922f69e989f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967081442 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_security_escalation.3967081442
Directory /workspace/48.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/48.lc_ctrl_smoke.3336537321
Short name T606
Test name
Test status
Simulation time 36572531 ps
CPU time 1.54 seconds
Started Jun 23 05:09:50 PM PDT 24
Finished Jun 23 05:09:52 PM PDT 24
Peak memory 213816 kb
Host smart-40efcc51-87f3-4f7e-b86c-c6ef0a35a94e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336537321 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_smoke.3336537321
Directory /workspace/48.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_failure.1083983228
Short name T735
Test name
Test status
Simulation time 204826301 ps
CPU time 22.03 seconds
Started Jun 23 05:09:46 PM PDT 24
Finished Jun 23 05:10:09 PM PDT 24
Peak memory 250780 kb
Host smart-70471450-8d83-4412-b0f2-70edaac22e46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083983228 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_failure.1083983228
Directory /workspace/48.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_post_trans.2708309355
Short name T866
Test name
Test status
Simulation time 357318993 ps
CPU time 6.69 seconds
Started Jun 23 05:09:46 PM PDT 24
Finished Jun 23 05:09:53 PM PDT 24
Peak memory 247028 kb
Host smart-6c5630bc-604f-49e9-aeec-b5a81c3c3a37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708309355 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_post_trans.2708309355
Directory /workspace/48.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all.3161431237
Short name T716
Test name
Test status
Simulation time 17420487301 ps
CPU time 153.58 seconds
Started Jun 23 05:09:46 PM PDT 24
Finished Jun 23 05:12:21 PM PDT 24
Peak memory 251032 kb
Host smart-5c800781-ff4e-4d3e-8838-222faab642c0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161431237 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.lc_ctrl_stress_all.3161431237
Directory /workspace/48.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.lc_ctrl_volatile_unlock_smoke.2590329279
Short name T471
Test name
Test status
Simulation time 11548863 ps
CPU time 0.84 seconds
Started Jun 23 05:09:44 PM PDT 24
Finished Jun 23 05:09:45 PM PDT 24
Peak memory 209128 kb
Host smart-31c69eeb-b353-4465-9fa6-189b3e137681
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590329279 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_c
trl_volatile_unlock_smoke.2590329279
Directory /workspace/48.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_alert_test.880767127
Short name T599
Test name
Test status
Simulation time 25095266 ps
CPU time 1.25 seconds
Started Jun 23 05:09:56 PM PDT 24
Finished Jun 23 05:09:58 PM PDT 24
Peak memory 209048 kb
Host smart-a99a0782-c752-4d21-b093-fbf9822ef106
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880767127 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_alert_test.880767127
Directory /workspace/49.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.lc_ctrl_errors.1012260729
Short name T288
Test name
Test status
Simulation time 1548972695 ps
CPU time 17.31 seconds
Started Jun 23 05:09:50 PM PDT 24
Finished Jun 23 05:10:09 PM PDT 24
Peak memory 218304 kb
Host smart-08026b8e-7283-45ed-a453-6d7b9800dd73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012260729 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_errors.1012260729
Directory /workspace/49.lc_ctrl_errors/latest

Test location /workspace/coverage/default/49.lc_ctrl_jtag_access.1994182050
Short name T578
Test name
Test status
Simulation time 1937845674 ps
CPU time 5.6 seconds
Started Jun 23 05:09:51 PM PDT 24
Finished Jun 23 05:09:58 PM PDT 24
Peak memory 217380 kb
Host smart-95e1a7a9-d9d2-4a34-b662-3cefc30e309e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994182050 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_jtag_access.1994182050
Directory /workspace/49.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/49.lc_ctrl_prog_failure.1356929959
Short name T788
Test name
Test status
Simulation time 263937351 ps
CPU time 2.71 seconds
Started Jun 23 05:09:49 PM PDT 24
Finished Jun 23 05:09:52 PM PDT 24
Peak memory 222364 kb
Host smart-a0951476-764b-48b1-a036-b3e4b24184f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356929959 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_prog_failure.1356929959
Directory /workspace/49.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_mubi.2413225841
Short name T860
Test name
Test status
Simulation time 1087071934 ps
CPU time 21.72 seconds
Started Jun 23 05:09:51 PM PDT 24
Finished Jun 23 05:10:14 PM PDT 24
Peak memory 219980 kb
Host smart-41dcc6e8-f9da-4f14-9da5-5c40b846d599
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413225841 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_mubi.2413225841
Directory /workspace/49.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_digest.2740055851
Short name T157
Test name
Test status
Simulation time 364543905 ps
CPU time 14.28 seconds
Started Jun 23 05:09:49 PM PDT 24
Finished Jun 23 05:10:04 PM PDT 24
Peak memory 218240 kb
Host smart-6a844f28-ff2e-4776-8c03-375b7fac23a9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740055851 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_d
igest.2740055851
Directory /workspace/49.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_mux.3182077414
Short name T544
Test name
Test status
Simulation time 767092014 ps
CPU time 12.23 seconds
Started Jun 23 05:09:51 PM PDT 24
Finished Jun 23 05:10:04 PM PDT 24
Peak memory 218236 kb
Host smart-3f2b1770-782d-4a41-a2eb-e4d429badd2c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182077414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_mux.
3182077414
Directory /workspace/49.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/49.lc_ctrl_security_escalation.3722976764
Short name T33
Test name
Test status
Simulation time 1981623322 ps
CPU time 11.52 seconds
Started Jun 23 05:09:50 PM PDT 24
Finished Jun 23 05:10:03 PM PDT 24
Peak memory 218184 kb
Host smart-e034ec52-5cf4-4bf8-a5bf-da092ab467e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722976764 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_security_escalation.3722976764
Directory /workspace/49.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/49.lc_ctrl_smoke.1006707075
Short name T437
Test name
Test status
Simulation time 96896252 ps
CPU time 6.94 seconds
Started Jun 23 05:09:55 PM PDT 24
Finished Jun 23 05:10:02 PM PDT 24
Peak memory 217740 kb
Host smart-c92b45b7-8827-418a-b6b7-64e663bd762e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006707075 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_smoke.1006707075
Directory /workspace/49.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_failure.430609268
Short name T67
Test name
Test status
Simulation time 305020187 ps
CPU time 28.97 seconds
Started Jun 23 05:09:50 PM PDT 24
Finished Jun 23 05:10:21 PM PDT 24
Peak memory 250984 kb
Host smart-a4a68a8c-d8a9-4b86-82f2-9e056b530dca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430609268 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_failure.430609268
Directory /workspace/49.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_post_trans.3582109425
Short name T180
Test name
Test status
Simulation time 128354425 ps
CPU time 9.56 seconds
Started Jun 23 05:09:51 PM PDT 24
Finished Jun 23 05:10:01 PM PDT 24
Peak memory 247136 kb
Host smart-76a09c13-66f0-4a92-9ac2-38d90fe9b846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582109425 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_post_trans.3582109425
Directory /workspace/49.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/49.lc_ctrl_stress_all.217996779
Short name T82
Test name
Test status
Simulation time 8584054156 ps
CPU time 36.42 seconds
Started Jun 23 05:09:49 PM PDT 24
Finished Jun 23 05:10:27 PM PDT 24
Peak memory 234648 kb
Host smart-7730f0dc-386a-4a38-a68f-63be7ef8eae7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217996779 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.lc_ctrl_stress_all.217996779
Directory /workspace/49.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.lc_ctrl_volatile_unlock_smoke.2570637459
Short name T815
Test name
Test status
Simulation time 24004901 ps
CPU time 1.13 seconds
Started Jun 23 05:09:51 PM PDT 24
Finished Jun 23 05:09:53 PM PDT 24
Peak memory 212040 kb
Host smart-2eec50b6-dee4-4dc1-9424-478d2f269a1b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570637459 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_c
trl_volatile_unlock_smoke.2570637459
Directory /workspace/49.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_alert_test.1196090656
Short name T516
Test name
Test status
Simulation time 72382514 ps
CPU time 1.1 seconds
Started Jun 23 05:06:30 PM PDT 24
Finished Jun 23 05:06:32 PM PDT 24
Peak memory 209108 kb
Host smart-edf8aeff-7d49-474d-838b-e30931927bad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196090656 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_alert_test.1196090656
Directory /workspace/5.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.lc_ctrl_claim_transition_if.1755765775
Short name T251
Test name
Test status
Simulation time 27286729 ps
CPU time 0.95 seconds
Started Jun 23 05:06:22 PM PDT 24
Finished Jun 23 05:06:24 PM PDT 24
Peak memory 208928 kb
Host smart-a9bc6173-f369-43e1-8d83-0a21424a87ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1755765775 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_claim_transition_if.1755765775
Directory /workspace/5.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/5.lc_ctrl_errors.2677986169
Short name T818
Test name
Test status
Simulation time 674247476 ps
CPU time 18.85 seconds
Started Jun 23 05:06:21 PM PDT 24
Finished Jun 23 05:06:41 PM PDT 24
Peak memory 218220 kb
Host smart-79743e0d-bdb0-4039-ac05-6f66c0d74c17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677986169 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_errors.2677986169
Directory /workspace/5.lc_ctrl_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_access.3964373955
Short name T553
Test name
Test status
Simulation time 816581362 ps
CPU time 5.63 seconds
Started Jun 23 05:06:30 PM PDT 24
Finished Jun 23 05:06:36 PM PDT 24
Peak memory 217244 kb
Host smart-d63e67fe-2383-4b4f-8b79-a3874f48b3ae
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964373955 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_access.3964373955
Directory /workspace/5.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_errors.3418429909
Short name T515
Test name
Test status
Simulation time 5870343468 ps
CPU time 81.74 seconds
Started Jun 23 05:06:30 PM PDT 24
Finished Jun 23 05:07:53 PM PDT 24
Peak memory 218820 kb
Host smart-b08d0638-ad32-45f7-8494-4261ccdf25eb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418429909 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_er
rors.3418429909
Directory /workspace/5.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_priority.1322205255
Short name T194
Test name
Test status
Simulation time 2673361526 ps
CPU time 4.93 seconds
Started Jun 23 05:06:29 PM PDT 24
Finished Jun 23 05:06:34 PM PDT 24
Peak memory 217756 kb
Host smart-97205fa9-5ae0-4d45-8f73-ea98af696ec8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322205255 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_priority.1
322205255
Directory /workspace/5.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_prog_failure.2964594173
Short name T504
Test name
Test status
Simulation time 2317481383 ps
CPU time 6.06 seconds
Started Jun 23 05:06:27 PM PDT 24
Finished Jun 23 05:06:33 PM PDT 24
Peak memory 223084 kb
Host smart-b4c804d4-487d-41ef-8af3-bc778c0097c8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964594173 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag
_prog_failure.2964594173
Directory /workspace/5.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_regwen_during_op.472121615
Short name T70
Test name
Test status
Simulation time 4215229344 ps
CPU time 31.49 seconds
Started Jun 23 05:06:30 PM PDT 24
Finished Jun 23 05:07:02 PM PDT 24
Peak memory 217672 kb
Host smart-a85ba9dd-0ac6-4dca-bda3-18364185b8e9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472121615 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_j
tag_regwen_during_op.472121615
Directory /workspace/5.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_smoke.606611715
Short name T661
Test name
Test status
Simulation time 1056839767 ps
CPU time 5.43 seconds
Started Jun 23 05:06:26 PM PDT 24
Finished Jun 23 05:06:32 PM PDT 24
Peak memory 217584 kb
Host smart-b18f2b86-6524-4fc7-9af5-02035a5518bd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606611715 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_smoke.606611715
Directory /workspace/5.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_failure.3511157732
Short name T405
Test name
Test status
Simulation time 1027905399 ps
CPU time 30.71 seconds
Started Jun 23 05:06:23 PM PDT 24
Finished Jun 23 05:06:55 PM PDT 24
Peak memory 266412 kb
Host smart-c6177b43-b4e6-41fd-a9f8-f93ab4cbaa75
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511157732 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jta
g_state_failure.3511157732
Directory /workspace/5.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_post_trans.66935482
Short name T546
Test name
Test status
Simulation time 1285488092 ps
CPU time 7.14 seconds
Started Jun 23 05:06:23 PM PDT 24
Finished Jun 23 05:06:30 PM PDT 24
Peak memory 226028 kb
Host smart-2b07914a-1857-42e0-ac3f-b1921e88f815
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66935482 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_s
tate_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jt
ag_state_post_trans.66935482
Directory /workspace/5.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_prog_failure.4058015369
Short name T337
Test name
Test status
Simulation time 209672242 ps
CPU time 3.88 seconds
Started Jun 23 05:06:24 PM PDT 24
Finished Jun 23 05:06:28 PM PDT 24
Peak memory 218212 kb
Host smart-24225de4-43df-42a1-937f-6fef4c3d6e21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058015369 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_prog_failure.4058015369
Directory /workspace/5.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_regwen_during_op.869126548
Short name T84
Test name
Test status
Simulation time 786835765 ps
CPU time 12.19 seconds
Started Jun 23 05:06:28 PM PDT 24
Finished Jun 23 05:06:41 PM PDT 24
Peak memory 217660 kb
Host smart-4da58f7f-dad1-4b31-a556-8760f9a1b950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869126548 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_regwen_during_op.869126548
Directory /workspace/5.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_mubi.1300932404
Short name T363
Test name
Test status
Simulation time 356851367 ps
CPU time 11.51 seconds
Started Jun 23 05:06:30 PM PDT 24
Finished Jun 23 05:06:42 PM PDT 24
Peak memory 218936 kb
Host smart-09fa15e0-88f6-4e31-b368-ea2ee095c46a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300932404 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_mubi.1300932404
Directory /workspace/5.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_digest.90907934
Short name T100
Test name
Test status
Simulation time 2185852574 ps
CPU time 10.97 seconds
Started Jun 23 05:06:30 PM PDT 24
Finished Jun 23 05:06:41 PM PDT 24
Peak memory 226216 kb
Host smart-af8dbf09-3d4d-49b8-8089-a92cffa9792c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90907934 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_dig
est_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_dige
st.90907934
Directory /workspace/5.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_mux.322635886
Short name T57
Test name
Test status
Simulation time 1119164094 ps
CPU time 7.34 seconds
Started Jun 23 05:06:29 PM PDT 24
Finished Jun 23 05:06:37 PM PDT 24
Peak memory 226156 kb
Host smart-9bc7c3eb-ca1b-4aa2-b500-6fe404ae22db
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322635886 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_mux.322635886
Directory /workspace/5.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/5.lc_ctrl_security_escalation.428062155
Short name T43
Test name
Test status
Simulation time 651400376 ps
CPU time 12.85 seconds
Started Jun 23 05:06:26 PM PDT 24
Finished Jun 23 05:06:40 PM PDT 24
Peak memory 226076 kb
Host smart-5a288fdd-a73e-445e-873b-a679ec4d9230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428062155 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_security_escalation.428062155
Directory /workspace/5.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/5.lc_ctrl_smoke.2283831524
Short name T286
Test name
Test status
Simulation time 78177008 ps
CPU time 2.99 seconds
Started Jun 23 05:06:24 PM PDT 24
Finished Jun 23 05:06:27 PM PDT 24
Peak memory 217764 kb
Host smart-653b7926-6baa-4e35-9d09-128ba29f11ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283831524 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_smoke.2283831524
Directory /workspace/5.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_failure.4144349781
Short name T272
Test name
Test status
Simulation time 1095914473 ps
CPU time 25.17 seconds
Started Jun 23 05:06:26 PM PDT 24
Finished Jun 23 05:06:52 PM PDT 24
Peak memory 250880 kb
Host smart-c1b92f37-b024-4fc0-a6ed-436723dd1509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144349781 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_failure.4144349781
Directory /workspace/5.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_post_trans.558344696
Short name T674
Test name
Test status
Simulation time 163837806 ps
CPU time 3.32 seconds
Started Jun 23 05:06:26 PM PDT 24
Finished Jun 23 05:06:30 PM PDT 24
Peak memory 221560 kb
Host smart-22519231-84db-4229-b91b-939a219971d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558344696 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_post_trans.558344696
Directory /workspace/5.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_stress_all.134082627
Short name T867
Test name
Test status
Simulation time 27232969910 ps
CPU time 243.32 seconds
Started Jun 23 05:06:28 PM PDT 24
Finished Jun 23 05:10:32 PM PDT 24
Peak memory 250836 kb
Host smart-44447087-4006-405b-bfcf-542a8f5c272f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134082627 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.lc_ctrl_stress_all.134082627
Directory /workspace/5.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.lc_ctrl_volatile_unlock_smoke.3064760218
Short name T411
Test name
Test status
Simulation time 18865654 ps
CPU time 1 seconds
Started Jun 23 05:06:27 PM PDT 24
Finished Jun 23 05:06:28 PM PDT 24
Peak memory 213008 kb
Host smart-c57d0106-de51-45b0-8a15-c8ca2622ddd4
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064760218 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ct
rl_volatile_unlock_smoke.3064760218
Directory /workspace/5.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_alert_test.3660533954
Short name T694
Test name
Test status
Simulation time 17356198 ps
CPU time 0.91 seconds
Started Jun 23 05:06:28 PM PDT 24
Finished Jun 23 05:06:30 PM PDT 24
Peak memory 209012 kb
Host smart-5e8e8c16-83b8-4cd7-a597-73721c5ce91e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660533954 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_alert_test.3660533954
Directory /workspace/6.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.lc_ctrl_claim_transition_if.1811044790
Short name T759
Test name
Test status
Simulation time 29162742 ps
CPU time 0.82 seconds
Started Jun 23 05:06:32 PM PDT 24
Finished Jun 23 05:06:33 PM PDT 24
Peak memory 209044 kb
Host smart-9ee96c1e-a52f-4d2c-94dd-097e9244cc0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811044790 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_claim_transition_if.1811044790
Directory /workspace/6.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/6.lc_ctrl_errors.1564550598
Short name T834
Test name
Test status
Simulation time 538832428 ps
CPU time 21.62 seconds
Started Jun 23 05:06:27 PM PDT 24
Finished Jun 23 05:06:50 PM PDT 24
Peak memory 218120 kb
Host smart-8acc1f5a-f037-4fdf-a9b3-b88bfcc6a5fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1564550598 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_errors.1564550598
Directory /workspace/6.lc_ctrl_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_access.1666444596
Short name T724
Test name
Test status
Simulation time 96034841 ps
CPU time 1.8 seconds
Started Jun 23 05:06:30 PM PDT 24
Finished Jun 23 05:06:33 PM PDT 24
Peak memory 216980 kb
Host smart-d30ebd2e-75b4-4f33-8bc3-f81df0e84b8f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666444596 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_access.1666444596
Directory /workspace/6.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_errors.970939139
Short name T799
Test name
Test status
Simulation time 18972111526 ps
CPU time 48.87 seconds
Started Jun 23 05:06:30 PM PDT 24
Finished Jun 23 05:07:20 PM PDT 24
Peak memory 218872 kb
Host smart-d733cc4f-7f4c-4e84-ace4-011f7775c45f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970939139 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_err
ors.970939139
Directory /workspace/6.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_priority.3398795294
Short name T727
Test name
Test status
Simulation time 189953911 ps
CPU time 4.01 seconds
Started Jun 23 05:06:27 PM PDT 24
Finished Jun 23 05:06:32 PM PDT 24
Peak memory 217212 kb
Host smart-b314b442-5627-4460-a238-06a79b561013
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398795294 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_priority.3
398795294
Directory /workspace/6.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_prog_failure.132699123
Short name T869
Test name
Test status
Simulation time 246993924 ps
CPU time 4.09 seconds
Started Jun 23 05:06:28 PM PDT 24
Finished Jun 23 05:06:33 PM PDT 24
Peak memory 218120 kb
Host smart-c2f8f664-ebbe-46d5-a4be-f553a0520b12
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132699123 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_
prog_failure.132699123
Directory /workspace/6.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_regwen_during_op.25973445
Short name T531
Test name
Test status
Simulation time 3568691851 ps
CPU time 24.83 seconds
Started Jun 23 05:06:28 PM PDT 24
Finished Jun 23 05:06:54 PM PDT 24
Peak memory 217632 kb
Host smart-9ca8917c-de06-42b9-b3f2-54e5b2e5bfaa
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25973445 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_r
egwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jt
ag_regwen_during_op.25973445
Directory /workspace/6.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_smoke.3101440864
Short name T686
Test name
Test status
Simulation time 360593269 ps
CPU time 10.51 seconds
Started Jun 23 05:06:27 PM PDT 24
Finished Jun 23 05:06:38 PM PDT 24
Peak memory 217816 kb
Host smart-e0c39cec-8097-413c-a326-d82e7e3d20d4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101440864 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_smoke.
3101440864
Directory /workspace/6.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_failure.137757885
Short name T250
Test name
Test status
Simulation time 6043635959 ps
CPU time 95.45 seconds
Started Jun 23 05:06:31 PM PDT 24
Finished Jun 23 05:08:07 PM PDT 24
Peak memory 283508 kb
Host smart-c2421239-a2bc-4064-94e9-96e8d682084c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137757885 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag
_state_failure.137757885
Directory /workspace/6.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_post_trans.2122517305
Short name T187
Test name
Test status
Simulation time 1074008594 ps
CPU time 20.59 seconds
Started Jun 23 05:06:31 PM PDT 24
Finished Jun 23 05:06:53 PM PDT 24
Peak memory 250348 kb
Host smart-1d537c1a-1c22-407d-89f1-b3e4ea140ff7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122517305 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_state_post_trans.2122517305
Directory /workspace/6.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_prog_failure.1589663257
Short name T473
Test name
Test status
Simulation time 98377269 ps
CPU time 4.58 seconds
Started Jun 23 05:06:30 PM PDT 24
Finished Jun 23 05:06:35 PM PDT 24
Peak memory 222752 kb
Host smart-2a87f9be-4751-4832-8a20-a57563a5aca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589663257 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_prog_failure.1589663257
Directory /workspace/6.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_regwen_during_op.1583205073
Short name T68
Test name
Test status
Simulation time 1147290512 ps
CPU time 15.29 seconds
Started Jun 23 05:06:30 PM PDT 24
Finished Jun 23 05:06:46 PM PDT 24
Peak memory 213996 kb
Host smart-c7af14c1-ec55-4d09-980d-35ad7b9666cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583205073 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_regwen_during_op.1583205073
Directory /workspace/6.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_mubi.3355776398
Short name T301
Test name
Test status
Simulation time 243594172 ps
CPU time 12.88 seconds
Started Jun 23 05:06:30 PM PDT 24
Finished Jun 23 05:06:44 PM PDT 24
Peak memory 226056 kb
Host smart-9661a7e0-f364-49e4-963a-bf45ca7b01ba
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355776398 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_mubi.3355776398
Directory /workspace/6.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_digest.2750192653
Short name T12
Test name
Test status
Simulation time 355314299 ps
CPU time 14.77 seconds
Started Jun 23 05:06:31 PM PDT 24
Finished Jun 23 05:06:47 PM PDT 24
Peak memory 218196 kb
Host smart-d1c309cf-bc44-4029-a33b-265cca6edb1b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750192653 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_di
gest.2750192653
Directory /workspace/6.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_mux.1126113917
Short name T725
Test name
Test status
Simulation time 201543456 ps
CPU time 6.94 seconds
Started Jun 23 05:06:28 PM PDT 24
Finished Jun 23 05:06:35 PM PDT 24
Peak memory 218220 kb
Host smart-b332eb0d-6338-4483-978b-93e1162485d9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126113917 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_mux.1
126113917
Directory /workspace/6.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/6.lc_ctrl_security_escalation.66464967
Short name T431
Test name
Test status
Simulation time 1176044921 ps
CPU time 8.25 seconds
Started Jun 23 05:06:28 PM PDT 24
Finished Jun 23 05:06:36 PM PDT 24
Peak memory 225068 kb
Host smart-b5931a6f-18ef-4e25-b497-9e03c1616325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66464967 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_security_escalation.66464967
Directory /workspace/6.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/6.lc_ctrl_smoke.1890750894
Short name T305
Test name
Test status
Simulation time 38972553 ps
CPU time 2 seconds
Started Jun 23 05:06:28 PM PDT 24
Finished Jun 23 05:06:31 PM PDT 24
Peak memory 214244 kb
Host smart-d24bd8f4-304f-4255-8163-41d41eb713f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890750894 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_smoke.1890750894
Directory /workspace/6.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_failure.3550604190
Short name T753
Test name
Test status
Simulation time 1304687545 ps
CPU time 33.79 seconds
Started Jun 23 05:06:31 PM PDT 24
Finished Jun 23 05:07:06 PM PDT 24
Peak memory 250804 kb
Host smart-be40caa6-1ca9-4122-bac9-c9b6be8b5e9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550604190 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_failure.3550604190
Directory /workspace/6.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_post_trans.4001283047
Short name T268
Test name
Test status
Simulation time 895508558 ps
CPU time 3.18 seconds
Started Jun 23 05:06:32 PM PDT 24
Finished Jun 23 05:06:36 PM PDT 24
Peak memory 218264 kb
Host smart-58bbd282-80eb-4f9c-8b6c-df6aa1415892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001283047 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_post_trans.4001283047
Directory /workspace/6.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all.1963999242
Short name T402
Test name
Test status
Simulation time 397401751 ps
CPU time 15.15 seconds
Started Jun 23 05:06:30 PM PDT 24
Finished Jun 23 05:06:46 PM PDT 24
Peak memory 247616 kb
Host smart-46661cb2-3233-4f2e-9a46-c216c22ec83f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963999242 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.lc_ctrl_stress_all.1963999242
Directory /workspace/6.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all_with_rand_reset.1928901924
Short name T163
Test name
Test status
Simulation time 22509424372 ps
CPU time 283.12 seconds
Started Jun 23 05:06:32 PM PDT 24
Finished Jun 23 05:11:16 PM PDT 24
Peak memory 283800 kb
Host smart-c39ff9e4-a419-4b4a-83a4-6d721ea79100
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1928901924 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_stress_all_with_rand_reset.1928901924
Directory /workspace/6.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.lc_ctrl_volatile_unlock_smoke.1406960428
Short name T454
Test name
Test status
Simulation time 35424705 ps
CPU time 0.89 seconds
Started Jun 23 05:06:29 PM PDT 24
Finished Jun 23 05:06:30 PM PDT 24
Peak memory 208996 kb
Host smart-18c82be4-10da-4232-8e60-792a1cc59fd7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406960428 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ct
rl_volatile_unlock_smoke.1406960428
Directory /workspace/6.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_alert_test.294542946
Short name T809
Test name
Test status
Simulation time 68382275 ps
CPU time 1.15 seconds
Started Jun 23 05:06:44 PM PDT 24
Finished Jun 23 05:06:46 PM PDT 24
Peak memory 208932 kb
Host smart-d5682ab7-3934-4d10-8330-3a2ef6443a55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294542946 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_alert_test.294542946
Directory /workspace/7.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.lc_ctrl_claim_transition_if.1814568251
Short name T74
Test name
Test status
Simulation time 18716918 ps
CPU time 0.84 seconds
Started Jun 23 05:06:35 PM PDT 24
Finished Jun 23 05:06:37 PM PDT 24
Peak memory 208840 kb
Host smart-6f5aed52-4f57-455e-9556-5e622e42e050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814568251 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_claim_transition_if.1814568251
Directory /workspace/7.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/7.lc_ctrl_errors.1264964158
Short name T568
Test name
Test status
Simulation time 368037741 ps
CPU time 11.25 seconds
Started Jun 23 05:06:36 PM PDT 24
Finished Jun 23 05:06:49 PM PDT 24
Peak memory 218184 kb
Host smart-deb524e7-26c3-4e98-8fc3-abb2313ab20a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264964158 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_errors.1264964158
Directory /workspace/7.lc_ctrl_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_access.3087715236
Short name T484
Test name
Test status
Simulation time 104667390 ps
CPU time 3.43 seconds
Started Jun 23 05:06:34 PM PDT 24
Finished Jun 23 05:06:39 PM PDT 24
Peak memory 217144 kb
Host smart-079d5e1c-e339-4b27-b300-1102e6785437
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087715236 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_access.3087715236
Directory /workspace/7.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_errors.2592449077
Short name T178
Test name
Test status
Simulation time 3038047509 ps
CPU time 39.9 seconds
Started Jun 23 05:06:33 PM PDT 24
Finished Jun 23 05:07:14 PM PDT 24
Peak memory 218992 kb
Host smart-a422abee-f14d-485a-94ed-82a57e5f4a44
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592449077 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_er
rors.2592449077
Directory /workspace/7.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_prog_failure.1306990269
Short name T839
Test name
Test status
Simulation time 503803583 ps
CPU time 14.95 seconds
Started Jun 23 05:06:39 PM PDT 24
Finished Jun 23 05:06:55 PM PDT 24
Peak memory 221996 kb
Host smart-27ea977e-9980-4091-a119-3f24a6383dd4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306990269 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag
_prog_failure.1306990269
Directory /workspace/7.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_regwen_during_op.4224439768
Short name T613
Test name
Test status
Simulation time 2050745799 ps
CPU time 23.07 seconds
Started Jun 23 05:06:33 PM PDT 24
Finished Jun 23 05:06:57 PM PDT 24
Peak memory 217656 kb
Host smart-9cb393ac-0eb4-474b-bb66-738944968509
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224439768 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_regwen_during_op.4224439768
Directory /workspace/7.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_smoke.1796327948
Short name T754
Test name
Test status
Simulation time 280783344 ps
CPU time 4.69 seconds
Started Jun 23 05:06:34 PM PDT 24
Finished Jun 23 05:06:40 PM PDT 24
Peak memory 217592 kb
Host smart-f8ea28f8-e5ac-4844-8d00-3723000da06f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796327948 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_smoke.
1796327948
Directory /workspace/7.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_failure.80857272
Short name T9
Test name
Test status
Simulation time 6330843805 ps
CPU time 58.77 seconds
Started Jun 23 05:06:38 PM PDT 24
Finished Jun 23 05:07:38 PM PDT 24
Peak memory 267324 kb
Host smart-04eea5da-3529-44ac-8c20-e7448a03528f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80857272 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_s
tate_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_
state_failure.80857272
Directory /workspace/7.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_post_trans.3861810830
Short name T665
Test name
Test status
Simulation time 299734253 ps
CPU time 16.5 seconds
Started Jun 23 05:06:33 PM PDT 24
Finished Jun 23 05:06:50 PM PDT 24
Peak memory 250952 kb
Host smart-372a319a-d961-4d8a-b645-755e452ad684
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861810830 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_state_post_trans.3861810830
Directory /workspace/7.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_prog_failure.3202457272
Short name T558
Test name
Test status
Simulation time 16357157 ps
CPU time 1.7 seconds
Started Jun 23 05:06:36 PM PDT 24
Finished Jun 23 05:06:39 PM PDT 24
Peak memory 221780 kb
Host smart-246bda80-0536-459e-92d2-398025863893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202457272 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_prog_failure.3202457272
Directory /workspace/7.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_regwen_during_op.1609138599
Short name T383
Test name
Test status
Simulation time 351413931 ps
CPU time 20.4 seconds
Started Jun 23 05:06:38 PM PDT 24
Finished Jun 23 05:06:59 PM PDT 24
Peak memory 214292 kb
Host smart-57425e65-cf83-4ab3-9d3e-f35b16f7ad85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609138599 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_regwen_during_op.1609138599
Directory /workspace/7.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_mubi.3392933898
Short name T792
Test name
Test status
Simulation time 1362265874 ps
CPU time 15.55 seconds
Started Jun 23 05:06:39 PM PDT 24
Finished Jun 23 05:06:56 PM PDT 24
Peak memory 218328 kb
Host smart-b69902a5-3eaa-45da-9560-2d5faaf14146
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392933898 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_mubi.3392933898
Directory /workspace/7.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_digest.2959947344
Short name T298
Test name
Test status
Simulation time 713426515 ps
CPU time 8.8 seconds
Started Jun 23 05:06:37 PM PDT 24
Finished Jun 23 05:06:47 PM PDT 24
Peak memory 218244 kb
Host smart-0c89463e-576d-44db-b5c3-c53cb44a0cca
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959947344 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_di
gest.2959947344
Directory /workspace/7.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_mux.2172402265
Short name T249
Test name
Test status
Simulation time 2496400429 ps
CPU time 7.86 seconds
Started Jun 23 05:06:37 PM PDT 24
Finished Jun 23 05:06:46 PM PDT 24
Peak memory 226024 kb
Host smart-b4053709-d9b1-4ec2-b309-ef90dcee44f4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172402265 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_mux.2
172402265
Directory /workspace/7.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/7.lc_ctrl_security_escalation.1836323610
Short name T528
Test name
Test status
Simulation time 624534771 ps
CPU time 8.56 seconds
Started Jun 23 05:06:34 PM PDT 24
Finished Jun 23 05:06:44 PM PDT 24
Peak memory 225300 kb
Host smart-89becb54-66fa-456b-8536-96f203c592e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836323610 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_security_escalation.1836323610
Directory /workspace/7.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/7.lc_ctrl_smoke.237141870
Short name T60
Test name
Test status
Simulation time 55671185 ps
CPU time 2.63 seconds
Started Jun 23 05:06:31 PM PDT 24
Finished Jun 23 05:06:35 PM PDT 24
Peak memory 214756 kb
Host smart-2d93b66f-f8b2-4bd0-9fb4-a8f96121e295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237141870 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_smoke.237141870
Directory /workspace/7.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_failure.4225441891
Short name T483
Test name
Test status
Simulation time 205782009 ps
CPU time 21.96 seconds
Started Jun 23 05:06:35 PM PDT 24
Finished Jun 23 05:06:58 PM PDT 24
Peak memory 250900 kb
Host smart-25002ecb-2396-4c1b-9e14-ffcdeeedc9c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225441891 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_failure.4225441891
Directory /workspace/7.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_post_trans.2782146024
Short name T395
Test name
Test status
Simulation time 273482634 ps
CPU time 7.57 seconds
Started Jun 23 05:06:33 PM PDT 24
Finished Jun 23 05:06:42 PM PDT 24
Peak memory 250904 kb
Host smart-1a8f1735-49aa-431b-9f93-21c7d6dfc737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782146024 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_post_trans.2782146024
Directory /workspace/7.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_stress_all.2010172596
Short name T571
Test name
Test status
Simulation time 3808363848 ps
CPU time 122.85 seconds
Started Jun 23 05:06:36 PM PDT 24
Finished Jun 23 05:08:40 PM PDT 24
Peak memory 250884 kb
Host smart-c0099d0d-30a2-4f84-a752-e11afebeaaec
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010172596 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.lc_ctrl_stress_all.2010172596
Directory /workspace/7.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.lc_ctrl_volatile_unlock_smoke.2427577147
Short name T845
Test name
Test status
Simulation time 13965382 ps
CPU time 0.8 seconds
Started Jun 23 05:06:37 PM PDT 24
Finished Jun 23 05:06:38 PM PDT 24
Peak memory 208900 kb
Host smart-83c86fa2-8693-441c-93a8-03d95bd05bc6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427577147 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ct
rl_volatile_unlock_smoke.2427577147
Directory /workspace/7.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_alert_test.1557216621
Short name T715
Test name
Test status
Simulation time 33022772 ps
CPU time 0.91 seconds
Started Jun 23 05:06:34 PM PDT 24
Finished Jun 23 05:06:36 PM PDT 24
Peak memory 208920 kb
Host smart-9ec4ecad-b701-4b65-9f0a-a29186545fdf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557216621 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_alert_test.1557216621
Directory /workspace/8.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.lc_ctrl_claim_transition_if.3842253056
Short name T218
Test name
Test status
Simulation time 21449780 ps
CPU time 0.79 seconds
Started Jun 23 05:06:39 PM PDT 24
Finished Jun 23 05:06:41 PM PDT 24
Peak memory 208980 kb
Host smart-d03a1011-3283-409b-9432-7786012fd2be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842253056 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_claim_transition_if.3842253056
Directory /workspace/8.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/8.lc_ctrl_errors.3537677750
Short name T46
Test name
Test status
Simulation time 241997550 ps
CPU time 8.39 seconds
Started Jun 23 05:06:36 PM PDT 24
Finished Jun 23 05:06:46 PM PDT 24
Peak memory 218216 kb
Host smart-2c120e4e-85e6-4a58-bf53-bc4838146577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537677750 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_errors.3537677750
Directory /workspace/8.lc_ctrl_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_access.136225164
Short name T690
Test name
Test status
Simulation time 1144272165 ps
CPU time 6.32 seconds
Started Jun 23 05:06:37 PM PDT 24
Finished Jun 23 05:06:44 PM PDT 24
Peak memory 217128 kb
Host smart-631a07f1-1cad-4225-8259-a562ac85959f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136225164 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_access.136225164
Directory /workspace/8.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_errors.2359704731
Short name T632
Test name
Test status
Simulation time 32583674071 ps
CPU time 42.76 seconds
Started Jun 23 05:06:35 PM PDT 24
Finished Jun 23 05:07:19 PM PDT 24
Peak memory 218864 kb
Host smart-3608d244-0f63-4e2a-835e-d1adbc9e1c7d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359704731 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_er
rors.2359704731
Directory /workspace/8.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_priority.3262581071
Short name T445
Test name
Test status
Simulation time 1717140923 ps
CPU time 5.08 seconds
Started Jun 23 05:06:34 PM PDT 24
Finished Jun 23 05:06:40 PM PDT 24
Peak memory 217608 kb
Host smart-e809ec19-1853-4033-9ff3-50a37e46fd4c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262581071 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_priority.3
262581071
Directory /workspace/8.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_prog_failure.483451691
Short name T560
Test name
Test status
Simulation time 2037636671 ps
CPU time 16.04 seconds
Started Jun 23 05:06:36 PM PDT 24
Finished Jun 23 05:06:53 PM PDT 24
Peak memory 218184 kb
Host smart-bb796ad6-10cf-4306-a5d3-f5c0341023a0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483451691 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_
prog_failure.483451691
Directory /workspace/8.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_regwen_during_op.2693614742
Short name T65
Test name
Test status
Simulation time 4759689634 ps
CPU time 16.46 seconds
Started Jun 23 05:06:39 PM PDT 24
Finished Jun 23 05:06:57 PM PDT 24
Peak memory 217804 kb
Host smart-04d5b638-a850-4f17-9c96-ff5e941825c7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693614742 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_regwen_during_op.2693614742
Directory /workspace/8.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_smoke.1495243336
Short name T69
Test name
Test status
Simulation time 2400188147 ps
CPU time 3.67 seconds
Started Jun 23 05:06:38 PM PDT 24
Finished Jun 23 05:06:42 PM PDT 24
Peak memory 217748 kb
Host smart-90ce840f-94db-48e9-96c6-fbd9a82591fe
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495243336 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_smoke.
1495243336
Directory /workspace/8.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_failure.3009102818
Short name T310
Test name
Test status
Simulation time 2804652929 ps
CPU time 61.32 seconds
Started Jun 23 05:06:35 PM PDT 24
Finished Jun 23 05:07:38 PM PDT 24
Peak memory 281688 kb
Host smart-2797f5fb-3630-4885-b2ae-50d61eb41355
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009102818 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jta
g_state_failure.3009102818
Directory /workspace/8.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_post_trans.84622475
Short name T607
Test name
Test status
Simulation time 1472665578 ps
CPU time 24.74 seconds
Started Jun 23 05:06:37 PM PDT 24
Finished Jun 23 05:07:03 PM PDT 24
Peak memory 250740 kb
Host smart-7979e844-a52a-4d7f-a1f8-2b113c1aa538
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84622475 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_s
tate_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jt
ag_state_post_trans.84622475
Directory /workspace/8.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_prog_failure.794694964
Short name T689
Test name
Test status
Simulation time 59307351 ps
CPU time 1.47 seconds
Started Jun 23 05:06:36 PM PDT 24
Finished Jun 23 05:06:39 PM PDT 24
Peak memory 218216 kb
Host smart-ce7d0b2b-416c-4a0a-8591-de4b07d3b420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794694964 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_prog_failure.794694964
Directory /workspace/8.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_regwen_during_op.2481290644
Short name T490
Test name
Test status
Simulation time 810675874 ps
CPU time 6.03 seconds
Started Jun 23 05:06:35 PM PDT 24
Finished Jun 23 05:06:42 PM PDT 24
Peak memory 217756 kb
Host smart-71bc5895-f200-4fd6-8e86-f90747b92d7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481290644 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_regwen_during_op.2481290644
Directory /workspace/8.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_mubi.3608765068
Short name T370
Test name
Test status
Simulation time 3827892213 ps
CPU time 11.86 seconds
Started Jun 23 05:06:38 PM PDT 24
Finished Jun 23 05:06:51 PM PDT 24
Peak memory 220328 kb
Host smart-cc4150b4-3f9f-48fe-9637-c721b1a0fa96
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608765068 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_mubi.3608765068
Directory /workspace/8.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_digest.2560201522
Short name T277
Test name
Test status
Simulation time 823378351 ps
CPU time 14.97 seconds
Started Jun 23 05:06:38 PM PDT 24
Finished Jun 23 05:06:53 PM PDT 24
Peak memory 218268 kb
Host smart-fdaa4b60-cb30-45f1-825d-6e87dc13b97a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560201522 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_di
gest.2560201522
Directory /workspace/8.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_mux.3457981364
Short name T748
Test name
Test status
Simulation time 367950690 ps
CPU time 12.67 seconds
Started Jun 23 05:06:36 PM PDT 24
Finished Jun 23 05:06:50 PM PDT 24
Peak memory 226072 kb
Host smart-bb556aba-a583-437e-ba7c-4c511d153166
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457981364 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_mux.3
457981364
Directory /workspace/8.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/8.lc_ctrl_security_escalation.2960510276
Short name T514
Test name
Test status
Simulation time 1114897152 ps
CPU time 14.78 seconds
Started Jun 23 05:06:36 PM PDT 24
Finished Jun 23 05:06:52 PM PDT 24
Peak memory 224828 kb
Host smart-832c5070-6532-42bf-b7de-32fcdc16d46f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960510276 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_security_escalation.2960510276
Directory /workspace/8.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/8.lc_ctrl_smoke.3468586262
Short name T780
Test name
Test status
Simulation time 265202607 ps
CPU time 2.61 seconds
Started Jun 23 05:06:33 PM PDT 24
Finished Jun 23 05:06:36 PM PDT 24
Peak memory 217848 kb
Host smart-c0546448-731e-46a8-b298-c5c4fea7e661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468586262 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_smoke.3468586262
Directory /workspace/8.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_failure.2642596052
Short name T806
Test name
Test status
Simulation time 427070912 ps
CPU time 23.52 seconds
Started Jun 23 05:06:36 PM PDT 24
Finished Jun 23 05:07:01 PM PDT 24
Peak memory 250852 kb
Host smart-f76e195b-66dd-495f-9659-1d803afad20c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642596052 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_failure.2642596052
Directory /workspace/8.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_post_trans.982681800
Short name T313
Test name
Test status
Simulation time 75283995 ps
CPU time 10.37 seconds
Started Jun 23 05:06:35 PM PDT 24
Finished Jun 23 05:06:46 PM PDT 24
Peak memory 250904 kb
Host smart-3363699f-f0db-47e0-858f-7bb52f0e714b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982681800 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_post_trans.982681800
Directory /workspace/8.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all.1803009154
Short name T704
Test name
Test status
Simulation time 784693268 ps
CPU time 13.9 seconds
Started Jun 23 05:06:37 PM PDT 24
Finished Jun 23 05:06:52 PM PDT 24
Peak memory 242876 kb
Host smart-791eafd2-e54f-48ee-a452-3ceed88a1eb6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803009154 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.lc_ctrl_stress_all.1803009154
Directory /workspace/8.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.lc_ctrl_volatile_unlock_smoke.3503541153
Short name T29
Test name
Test status
Simulation time 13117177 ps
CPU time 0.78 seconds
Started Jun 23 05:06:39 PM PDT 24
Finished Jun 23 05:06:41 PM PDT 24
Peak memory 209096 kb
Host smart-e85fb19d-1505-4907-81da-fdcd1ffb06f6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503541153 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ct
rl_volatile_unlock_smoke.3503541153
Directory /workspace/8.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_alert_test.336875231
Short name T766
Test name
Test status
Simulation time 42711892 ps
CPU time 1.2 seconds
Started Jun 23 05:06:42 PM PDT 24
Finished Jun 23 05:06:44 PM PDT 24
Peak memory 208948 kb
Host smart-e5345597-9dd7-4102-96a1-31490369b901
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336875231 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_alert_test.336875231
Directory /workspace/9.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.lc_ctrl_claim_transition_if.3775556122
Short name T646
Test name
Test status
Simulation time 37783430 ps
CPU time 0.85 seconds
Started Jun 23 05:06:43 PM PDT 24
Finished Jun 23 05:06:44 PM PDT 24
Peak memory 208748 kb
Host smart-83450eea-30a0-4614-bb3b-2144732836eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775556122 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_claim_transition_if.3775556122
Directory /workspace/9.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/9.lc_ctrl_errors.4184328442
Short name T242
Test name
Test status
Simulation time 1190580362 ps
CPU time 12.91 seconds
Started Jun 23 05:06:44 PM PDT 24
Finished Jun 23 05:06:58 PM PDT 24
Peak memory 218136 kb
Host smart-b5268dd7-6b3c-49f8-a73f-5e6ab313e13d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184328442 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_errors.4184328442
Directory /workspace/9.lc_ctrl_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_access.363185313
Short name T7
Test name
Test status
Simulation time 282440980 ps
CPU time 7.24 seconds
Started Jun 23 05:06:41 PM PDT 24
Finished Jun 23 05:06:49 PM PDT 24
Peak memory 217124 kb
Host smart-def7df81-126c-4ed1-8d36-df1c512517c0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363185313 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_access.363185313
Directory /workspace/9.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_errors.4054552525
Short name T706
Test name
Test status
Simulation time 3886937787 ps
CPU time 105.3 seconds
Started Jun 23 05:06:41 PM PDT 24
Finished Jun 23 05:08:27 PM PDT 24
Peak memory 226228 kb
Host smart-21b65a92-8c48-4056-8588-9fcaaa25c1f9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054552525 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_er
rors.4054552525
Directory /workspace/9.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_priority.4040639574
Short name T470
Test name
Test status
Simulation time 302330743 ps
CPU time 4.07 seconds
Started Jun 23 05:06:40 PM PDT 24
Finished Jun 23 05:06:45 PM PDT 24
Peak memory 217424 kb
Host smart-956be94a-6ab6-48b6-b8fd-797547c59fb7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040639574 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_priority.4
040639574
Directory /workspace/9.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_prog_failure.3894257006
Short name T768
Test name
Test status
Simulation time 1225642647 ps
CPU time 7.87 seconds
Started Jun 23 05:06:38 PM PDT 24
Finished Jun 23 05:06:47 PM PDT 24
Peak memory 221708 kb
Host smart-4b26ed00-b7eb-4985-9267-8e33d1b9da80
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894257006 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag
_prog_failure.3894257006
Directory /workspace/9.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_regwen_during_op.3583079304
Short name T447
Test name
Test status
Simulation time 1214858392 ps
CPU time 35.79 seconds
Started Jun 23 05:06:39 PM PDT 24
Finished Jun 23 05:07:16 PM PDT 24
Peak memory 217664 kb
Host smart-0e68e027-d935-4eff-bb66-7f317a39b5bd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583079304 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_regwen_during_op.3583079304
Directory /workspace/9.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_smoke.559592622
Short name T820
Test name
Test status
Simulation time 215397244 ps
CPU time 4.64 seconds
Started Jun 23 05:06:39 PM PDT 24
Finished Jun 23 05:06:44 PM PDT 24
Peak memory 217700 kb
Host smart-bec10de9-4f95-46bc-89f6-634aceb2e625
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559592622 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_smoke.559592622
Directory /workspace/9.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_failure.1405436507
Short name T731
Test name
Test status
Simulation time 9288989471 ps
CPU time 39.11 seconds
Started Jun 23 05:06:41 PM PDT 24
Finished Jun 23 05:07:21 PM PDT 24
Peak memory 250876 kb
Host smart-78af1bf5-30d0-4b04-bfb6-7d2761a7013a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405436507 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jta
g_state_failure.1405436507
Directory /workspace/9.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_post_trans.252290293
Short name T324
Test name
Test status
Simulation time 390802009 ps
CPU time 11.88 seconds
Started Jun 23 05:06:43 PM PDT 24
Finished Jun 23 05:06:55 PM PDT 24
Peak memory 223036 kb
Host smart-e3e51687-a651-4cdf-b32c-9a27ca1e6c65
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252290293 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_j
tag_state_post_trans.252290293
Directory /workspace/9.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_prog_failure.211624120
Short name T456
Test name
Test status
Simulation time 46035001 ps
CPU time 2.87 seconds
Started Jun 23 05:06:38 PM PDT 24
Finished Jun 23 05:06:41 PM PDT 24
Peak memory 218256 kb
Host smart-1dea89b2-78cf-4cab-b202-c9503d1bee10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211624120 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_prog_failure.211624120
Directory /workspace/9.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_regwen_during_op.1246875873
Short name T494
Test name
Test status
Simulation time 361323403 ps
CPU time 25.14 seconds
Started Jun 23 05:06:43 PM PDT 24
Finished Jun 23 05:07:09 PM PDT 24
Peak memory 217736 kb
Host smart-d3f36847-1f20-49f7-b263-0dbe47f9f771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246875873 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_regwen_during_op.1246875873
Directory /workspace/9.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_mubi.3217610693
Short name T412
Test name
Test status
Simulation time 237335336 ps
CPU time 10.56 seconds
Started Jun 23 05:06:41 PM PDT 24
Finished Jun 23 05:06:52 PM PDT 24
Peak memory 218260 kb
Host smart-d52c0e3a-d1a8-4f35-8d38-ff64ccbd66ae
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217610693 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_mubi.3217610693
Directory /workspace/9.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_digest.2530047267
Short name T50
Test name
Test status
Simulation time 573914865 ps
CPU time 10.2 seconds
Started Jun 23 05:06:41 PM PDT 24
Finished Jun 23 05:06:52 PM PDT 24
Peak memory 218240 kb
Host smart-51092176-68aa-428f-9da7-a0fb221cc0c1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530047267 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_di
gest.2530047267
Directory /workspace/9.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_mux.3189134571
Short name T343
Test name
Test status
Simulation time 475273330 ps
CPU time 15.14 seconds
Started Jun 23 05:06:40 PM PDT 24
Finished Jun 23 05:06:56 PM PDT 24
Peak memory 218160 kb
Host smart-fc9026fe-154b-444d-94db-93a873ee6fc1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189134571 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_mux.3
189134571
Directory /workspace/9.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/9.lc_ctrl_security_escalation.1746768383
Short name T184
Test name
Test status
Simulation time 712461494 ps
CPU time 6.01 seconds
Started Jun 23 05:06:43 PM PDT 24
Finished Jun 23 05:06:50 PM PDT 24
Peak memory 225968 kb
Host smart-b4efa9f4-e35e-4e1c-b880-b46a40815491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746768383 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_security_escalation.1746768383
Directory /workspace/9.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/9.lc_ctrl_smoke.3965337712
Short name T482
Test name
Test status
Simulation time 132305076 ps
CPU time 3.22 seconds
Started Jun 23 05:06:44 PM PDT 24
Finished Jun 23 05:06:48 PM PDT 24
Peak memory 217672 kb
Host smart-7f7fd2f9-7324-4d0a-b3a6-c3f29d9cd721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965337712 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_smoke.3965337712
Directory /workspace/9.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_failure.1258350780
Short name T96
Test name
Test status
Simulation time 204899813 ps
CPU time 18.88 seconds
Started Jun 23 05:06:35 PM PDT 24
Finished Jun 23 05:06:56 PM PDT 24
Peak memory 250804 kb
Host smart-a37cdb91-740b-4623-906a-bf1224d8817d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258350780 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_failure.1258350780
Directory /workspace/9.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_post_trans.1238769585
Short name T179
Test name
Test status
Simulation time 255779276 ps
CPU time 10.89 seconds
Started Jun 23 05:06:35 PM PDT 24
Finished Jun 23 05:06:48 PM PDT 24
Peak memory 250904 kb
Host smart-17477168-90da-49fd-869c-572e57a7282b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238769585 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_post_trans.1238769585
Directory /workspace/9.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_stress_all.2939026896
Short name T777
Test name
Test status
Simulation time 5079879941 ps
CPU time 126.67 seconds
Started Jun 23 05:06:42 PM PDT 24
Finished Jun 23 05:08:49 PM PDT 24
Peak memory 267344 kb
Host smart-b7eb6922-bacd-48e0-948f-21481d36981e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939026896 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.lc_ctrl_stress_all.2939026896
Directory /workspace/9.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.lc_ctrl_volatile_unlock_smoke.880002850
Short name T790
Test name
Test status
Simulation time 34543237 ps
CPU time 0.94 seconds
Started Jun 23 05:06:38 PM PDT 24
Finished Jun 23 05:06:40 PM PDT 24
Peak memory 211940 kb
Host smart-f99a4af1-7289-462d-9a41-45ceeadd7a0e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880002850 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctr
l_volatile_unlock_smoke.880002850
Directory /workspace/9.lc_ctrl_volatile_unlock_smoke/latest
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