Summary for Variable clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
55094 |
1 |
|
|
T1 |
88 |
|
T2 |
72 |
|
T4 |
50 |
auto[1] |
1883 |
1 |
|
|
T2 |
13 |
|
T5 |
13 |
|
T6 |
52 |
Summary for Variable clk_byp_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
56231 |
1 |
|
|
T1 |
88 |
|
T2 |
85 |
|
T4 |
39 |
auto[1] |
746 |
1 |
|
|
T4 |
11 |
|
T12 |
12 |
|
T37 |
19 |
Summary for Variable count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54975 |
1 |
|
|
T1 |
79 |
|
T2 |
85 |
|
T4 |
50 |
auto[1] |
2002 |
1 |
|
|
T1 |
9 |
|
T11 |
13 |
|
T6 |
27 |
Summary for Variable count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54919 |
1 |
|
|
T1 |
78 |
|
T2 |
85 |
|
T4 |
50 |
auto[1] |
2058 |
1 |
|
|
T1 |
10 |
|
T11 |
8 |
|
T6 |
25 |
Summary for Variable count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54887 |
1 |
|
|
T1 |
75 |
|
T2 |
85 |
|
T4 |
50 |
auto[1] |
2090 |
1 |
|
|
T1 |
13 |
|
T11 |
2 |
|
T6 |
43 |
Summary for Variable err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for err_inj_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
err_inj |
51507 |
1 |
|
|
T1 |
88 |
|
T2 |
85 |
|
T4 |
50 |
no_err_inj |
5470 |
1 |
|
|
T6 |
91 |
|
T15 |
31 |
|
T16 |
8 |
Summary for Variable flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54974 |
1 |
|
|
T1 |
88 |
|
T2 |
70 |
|
T4 |
50 |
auto[1] |
2003 |
1 |
|
|
T2 |
15 |
|
T5 |
7 |
|
T6 |
66 |
Summary for Variable flash_rma_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
56223 |
1 |
|
|
T1 |
88 |
|
T2 |
85 |
|
T4 |
42 |
auto[1] |
754 |
1 |
|
|
T4 |
8 |
|
T12 |
12 |
|
T37 |
16 |
Summary for Variable jtag_csr_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for jtag_csr_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
39344 |
1 |
|
|
T2 |
85 |
|
T4 |
50 |
|
T11 |
65 |
auto[1] |
17633 |
1 |
|
|
T1 |
88 |
|
T5 |
78 |
|
T6 |
546 |
Summary for Variable kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for kmac_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54955 |
1 |
|
|
T1 |
79 |
|
T2 |
85 |
|
T4 |
50 |
auto[1] |
2022 |
1 |
|
|
T1 |
9 |
|
T11 |
9 |
|
T6 |
31 |
Summary for Variable lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for lc_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54971 |
1 |
|
|
T1 |
80 |
|
T2 |
85 |
|
T4 |
50 |
auto[1] |
2006 |
1 |
|
|
T1 |
8 |
|
T11 |
7 |
|
T6 |
26 |
Summary for Variable otp_lc_data_i_valid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_lc_data_i_valid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54902 |
1 |
|
|
T1 |
79 |
|
T2 |
85 |
|
T4 |
50 |
auto[1] |
2075 |
1 |
|
|
T1 |
9 |
|
T11 |
6 |
|
T6 |
33 |
Summary for Variable otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_partition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
55172 |
1 |
|
|
T1 |
88 |
|
T2 |
74 |
|
T4 |
50 |
auto[1] |
1805 |
1 |
|
|
T2 |
11 |
|
T5 |
8 |
|
T6 |
62 |
Summary for Variable otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_prog_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54260 |
1 |
|
|
T1 |
88 |
|
T2 |
85 |
|
T4 |
50 |
auto[1] |
2717 |
1 |
|
|
T6 |
36 |
|
T29 |
9 |
|
T17 |
19 |
Summary for Variable otp_rma_token_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_rma_token_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
56223 |
1 |
|
|
T1 |
88 |
|
T2 |
85 |
|
T4 |
45 |
auto[1] |
754 |
1 |
|
|
T4 |
5 |
|
T12 |
13 |
|
T37 |
12 |
Summary for Variable otp_secrets_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_secrets_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
56229 |
1 |
|
|
T1 |
88 |
|
T2 |
85 |
|
T4 |
38 |
auto[1] |
748 |
1 |
|
|
T4 |
12 |
|
T12 |
14 |
|
T37 |
19 |
Summary for Variable otp_test_tokens_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_test_tokens_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
56167 |
1 |
|
|
T1 |
88 |
|
T2 |
85 |
|
T4 |
36 |
auto[1] |
810 |
1 |
|
|
T4 |
14 |
|
T12 |
11 |
|
T37 |
28 |
Summary for Variable post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for post_trans_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53743 |
1 |
|
|
T1 |
88 |
|
T2 |
85 |
|
T4 |
50 |
auto[1] |
3234 |
1 |
|
|
T6 |
55 |
|
T17 |
12 |
|
T32 |
26 |
Summary for Variable security_escalation_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for security_escalation_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53236 |
1 |
|
|
T1 |
88 |
|
T2 |
85 |
|
T4 |
50 |
auto[1] |
3741 |
1 |
|
|
T34 |
76 |
|
T41 |
92 |
|
T42 |
82 |
Summary for Variable state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54911 |
1 |
|
|
T1 |
82 |
|
T2 |
85 |
|
T4 |
50 |
auto[1] |
2066 |
1 |
|
|
T1 |
6 |
|
T11 |
5 |
|
T6 |
25 |
Summary for Variable state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54907 |
1 |
|
|
T1 |
79 |
|
T2 |
85 |
|
T4 |
50 |
auto[1] |
2070 |
1 |
|
|
T1 |
9 |
|
T11 |
7 |
|
T6 |
32 |
Summary for Variable state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54974 |
1 |
|
|
T1 |
73 |
|
T2 |
85 |
|
T4 |
50 |
auto[1] |
2003 |
1 |
|
|
T1 |
15 |
|
T11 |
8 |
|
T6 |
28 |
Summary for Variable token_invalid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_invalid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
55098 |
1 |
|
|
T1 |
88 |
|
T2 |
75 |
|
T4 |
50 |
auto[1] |
1879 |
1 |
|
|
T2 |
10 |
|
T5 |
11 |
|
T6 |
62 |
Summary for Variable token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mismatch_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51168 |
1 |
|
|
T1 |
88 |
|
T2 |
78 |
|
T4 |
50 |
auto[1] |
5809 |
1 |
|
|
T2 |
7 |
|
T5 |
11 |
|
T6 |
49 |
Summary for Variable token_mux_ctrl_redun_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mux_ctrl_redun_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53257 |
1 |
|
|
T1 |
88 |
|
T2 |
85 |
|
T4 |
50 |
auto[1] |
3720 |
1 |
|
|
T30 |
61 |
|
T40 |
65 |
|
T54 |
50 |
Summary for Variable token_mux_digest_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for token_mux_digest_err_cp
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
56977 |
1 |
|
|
T1 |
88 |
|
T2 |
85 |
|
T4 |
50 |
Summary for Variable token_response_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_response_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
55057 |
1 |
|
|
T1 |
88 |
|
T2 |
74 |
|
T4 |
50 |
auto[1] |
1920 |
1 |
|
|
T2 |
11 |
|
T5 |
14 |
|
T6 |
69 |
Summary for Variable transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
55078 |
1 |
|
|
T1 |
88 |
|
T2 |
77 |
|
T4 |
50 |
auto[1] |
1899 |
1 |
|
|
T2 |
8 |
|
T5 |
8 |
|
T6 |
45 |
Summary for Variable transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
55050 |
1 |
|
|
T1 |
88 |
|
T2 |
75 |
|
T4 |
50 |
auto[1] |
1927 |
1 |
|
|
T2 |
10 |
|
T5 |
6 |
|
T6 |
61 |
Summary for Cross post_trans_err_inj_xp
Samples crossed: post_trans_err_cp err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_err_inj_xp
Bins
post_trans_err_cp | err_inj_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
err_inj |
49898 |
1 |
|
|
T1 |
88 |
|
T2 |
85 |
|
T4 |
50 |
auto[0] |
no_err_inj |
3845 |
1 |
|
|
T6 |
59 |
|
T15 |
31 |
|
T16 |
8 |
auto[1] |
err_inj |
1609 |
1 |
|
|
T6 |
23 |
|
T17 |
7 |
|
T32 |
13 |
auto[1] |
no_err_inj |
1625 |
1 |
|
|
T6 |
32 |
|
T17 |
5 |
|
T32 |
13 |
Summary for Cross post_trans_state_err_xp
Samples crossed: post_trans_err_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_err_xp
Bins
post_trans_err_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
51856 |
1 |
|
|
T1 |
79 |
|
T2 |
85 |
|
T4 |
50 |
auto[0] |
auto[1] |
1887 |
1 |
|
|
T1 |
9 |
|
T11 |
7 |
|
T6 |
29 |
auto[1] |
auto[0] |
3051 |
1 |
|
|
T6 |
52 |
|
T17 |
9 |
|
T32 |
24 |
auto[1] |
auto[1] |
183 |
1 |
|
|
T6 |
3 |
|
T17 |
3 |
|
T32 |
2 |
Summary for Cross post_trans_lc_fsm_backdoor_err_xp
Samples crossed: post_trans_err_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_lc_fsm_backdoor_err_xp
Bins
post_trans_err_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
51901 |
1 |
|
|
T1 |
80 |
|
T2 |
85 |
|
T4 |
50 |
auto[0] |
auto[1] |
1842 |
1 |
|
|
T1 |
8 |
|
T11 |
7 |
|
T6 |
25 |
auto[1] |
auto[0] |
3070 |
1 |
|
|
T6 |
54 |
|
T17 |
12 |
|
T32 |
25 |
auto[1] |
auto[1] |
164 |
1 |
|
|
T6 |
1 |
|
T32 |
1 |
|
T193 |
1 |
Summary for Cross post_trans_state_illegal_err_xp
Samples crossed: post_trans_err_cp state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_illegal_err_xp
Bins
post_trans_err_cp | state_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
51923 |
1 |
|
|
T1 |
73 |
|
T2 |
85 |
|
T4 |
50 |
auto[0] |
auto[1] |
1820 |
1 |
|
|
T1 |
15 |
|
T11 |
8 |
|
T6 |
27 |
auto[1] |
auto[0] |
3051 |
1 |
|
|
T6 |
54 |
|
T17 |
11 |
|
T32 |
26 |
auto[1] |
auto[1] |
183 |
1 |
|
|
T6 |
1 |
|
T17 |
1 |
|
T193 |
1 |
Summary for Cross post_trans_count_err_xp
Samples crossed: post_trans_err_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_err_xp
Bins
post_trans_err_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
51863 |
1 |
|
|
T1 |
78 |
|
T2 |
85 |
|
T4 |
50 |
auto[0] |
auto[1] |
1880 |
1 |
|
|
T1 |
10 |
|
T11 |
8 |
|
T6 |
23 |
auto[1] |
auto[0] |
3056 |
1 |
|
|
T6 |
53 |
|
T17 |
11 |
|
T32 |
24 |
auto[1] |
auto[1] |
178 |
1 |
|
|
T6 |
2 |
|
T17 |
1 |
|
T32 |
2 |
Summary for Cross post_trans_count_illegal_err_xp
Samples crossed: post_trans_err_cp count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_illegal_err_xp
Bins
post_trans_err_cp | count_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
51844 |
1 |
|
|
T1 |
75 |
|
T2 |
85 |
|
T4 |
50 |
auto[0] |
auto[1] |
1899 |
1 |
|
|
T1 |
13 |
|
T11 |
2 |
|
T6 |
39 |
auto[1] |
auto[0] |
3043 |
1 |
|
|
T6 |
51 |
|
T17 |
11 |
|
T32 |
23 |
auto[1] |
auto[1] |
191 |
1 |
|
|
T6 |
4 |
|
T17 |
1 |
|
T32 |
3 |
Summary for Cross post_trans_count_backdoor_err_xp
Samples crossed: post_trans_err_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_backdoor_err_xp
Bins
post_trans_err_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
51910 |
1 |
|
|
T1 |
79 |
|
T2 |
85 |
|
T4 |
50 |
auto[0] |
auto[1] |
1833 |
1 |
|
|
T1 |
9 |
|
T11 |
13 |
|
T6 |
26 |
auto[1] |
auto[0] |
3065 |
1 |
|
|
T6 |
54 |
|
T17 |
12 |
|
T32 |
25 |
auto[1] |
auto[1] |
169 |
1 |
|
|
T6 |
1 |
|
T32 |
1 |
|
T193 |
2 |
Summary for Cross jtag_clk_byp_error_rsp_xp
Samples crossed: jtag_csr_cp clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_clk_byp_error_rsp_xp
Bins
jtag_csr_cp | clk_byp_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38211 |
1 |
|
|
T2 |
72 |
|
T4 |
50 |
|
T11 |
65 |
auto[0] |
auto[1] |
1133 |
1 |
|
|
T2 |
13 |
|
T6 |
13 |
|
T14 |
10 |
auto[1] |
auto[0] |
16883 |
1 |
|
|
T1 |
88 |
|
T5 |
65 |
|
T6 |
507 |
auto[1] |
auto[1] |
750 |
1 |
|
|
T5 |
13 |
|
T6 |
39 |
|
T15 |
5 |
Summary for Cross jtag_flash_rma_error_rsp_xp
Samples crossed: jtag_csr_cp flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_flash_rma_error_rsp_xp
Bins
jtag_csr_cp | flash_rma_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38140 |
1 |
|
|
T2 |
70 |
|
T4 |
50 |
|
T11 |
65 |
auto[0] |
auto[1] |
1204 |
1 |
|
|
T2 |
15 |
|
T6 |
19 |
|
T14 |
12 |
auto[1] |
auto[0] |
16834 |
1 |
|
|
T1 |
88 |
|
T5 |
71 |
|
T6 |
499 |
auto[1] |
auto[1] |
799 |
1 |
|
|
T5 |
7 |
|
T6 |
47 |
|
T15 |
4 |
Summary for Cross jtag_otp_prog_err_xp
Samples crossed: jtag_csr_cp otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_prog_err_xp
Bins
jtag_csr_cp | otp_prog_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37690 |
1 |
|
|
T2 |
85 |
|
T4 |
50 |
|
T11 |
65 |
auto[0] |
auto[1] |
1654 |
1 |
|
|
T29 |
9 |
|
T17 |
19 |
|
T85 |
11 |
auto[1] |
auto[0] |
16570 |
1 |
|
|
T1 |
88 |
|
T5 |
78 |
|
T6 |
510 |
auto[1] |
auto[1] |
1063 |
1 |
|
|
T6 |
36 |
|
T20 |
16 |
|
T194 |
20 |
Summary for Cross jtag_otp_partition_err_xp
Samples crossed: jtag_csr_cp otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_partition_err_xp
Bins
jtag_csr_cp | otp_partition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38231 |
1 |
|
|
T2 |
74 |
|
T4 |
50 |
|
T11 |
65 |
auto[0] |
auto[1] |
1113 |
1 |
|
|
T2 |
11 |
|
T6 |
19 |
|
T14 |
8 |
auto[1] |
auto[0] |
16941 |
1 |
|
|
T1 |
88 |
|
T5 |
70 |
|
T6 |
503 |
auto[1] |
auto[1] |
692 |
1 |
|
|
T5 |
8 |
|
T6 |
43 |
|
T15 |
10 |
Summary for Cross jtag_token_mismatch_err_xp
Samples crossed: jtag_csr_cp token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_token_mismatch_err_xp
Bins
jtag_csr_cp | token_mismatch_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
34319 |
1 |
|
|
T2 |
78 |
|
T4 |
50 |
|
T11 |
65 |
auto[0] |
auto[1] |
5025 |
1 |
|
|
T2 |
7 |
|
T6 |
18 |
|
T13 |
71 |
auto[1] |
auto[0] |
16849 |
1 |
|
|
T1 |
88 |
|
T5 |
67 |
|
T6 |
515 |
auto[1] |
auto[1] |
784 |
1 |
|
|
T5 |
11 |
|
T6 |
31 |
|
T15 |
9 |
Summary for Cross jtag_state_err_xp
Samples crossed: jtag_csr_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_err_xp
Bins
jtag_csr_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38240 |
1 |
|
|
T2 |
85 |
|
T4 |
50 |
|
T11 |
58 |
auto[0] |
auto[1] |
1104 |
1 |
|
|
T11 |
7 |
|
T6 |
14 |
|
T56 |
3 |
auto[1] |
auto[0] |
16667 |
1 |
|
|
T1 |
79 |
|
T5 |
78 |
|
T6 |
528 |
auto[1] |
auto[1] |
966 |
1 |
|
|
T1 |
9 |
|
T6 |
18 |
|
T17 |
3 |
Summary for Cross jtag_state_backdoor_err_xp
Samples crossed: jtag_csr_cp state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_backdoor_err_xp
Bins
jtag_csr_cp | state_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38166 |
1 |
|
|
T2 |
85 |
|
T4 |
50 |
|
T11 |
60 |
auto[0] |
auto[1] |
1178 |
1 |
|
|
T11 |
5 |
|
T6 |
8 |
|
T56 |
11 |
auto[1] |
auto[0] |
16745 |
1 |
|
|
T1 |
82 |
|
T5 |
78 |
|
T6 |
529 |
auto[1] |
auto[1] |
888 |
1 |
|
|
T1 |
6 |
|
T6 |
17 |
|
T19 |
8 |
Summary for Cross jtag_lc_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_lc_fsm_backdoor_err_xp
Bins
jtag_csr_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38214 |
1 |
|
|
T2 |
85 |
|
T4 |
50 |
|
T11 |
58 |
auto[0] |
auto[1] |
1130 |
1 |
|
|
T11 |
7 |
|
T6 |
10 |
|
T56 |
6 |
auto[1] |
auto[0] |
16757 |
1 |
|
|
T1 |
80 |
|
T5 |
78 |
|
T6 |
530 |
auto[1] |
auto[1] |
876 |
1 |
|
|
T1 |
8 |
|
T6 |
16 |
|
T19 |
8 |
Summary for Cross jtag_kmac_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_kmac_fsm_backdoor_err_xp
Bins
jtag_csr_cp | kmac_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38230 |
1 |
|
|
T2 |
85 |
|
T4 |
50 |
|
T11 |
56 |
auto[0] |
auto[1] |
1114 |
1 |
|
|
T11 |
9 |
|
T6 |
14 |
|
T56 |
11 |
auto[1] |
auto[0] |
16725 |
1 |
|
|
T1 |
79 |
|
T5 |
78 |
|
T6 |
529 |
auto[1] |
auto[1] |
908 |
1 |
|
|
T1 |
9 |
|
T6 |
17 |
|
T19 |
10 |
Summary for Cross jtag_count_err_xp
Samples crossed: jtag_csr_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_err_xp
Bins
jtag_csr_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38207 |
1 |
|
|
T2 |
85 |
|
T4 |
50 |
|
T11 |
57 |
auto[0] |
auto[1] |
1137 |
1 |
|
|
T11 |
8 |
|
T6 |
8 |
|
T56 |
7 |
auto[1] |
auto[0] |
16712 |
1 |
|
|
T1 |
78 |
|
T5 |
78 |
|
T6 |
529 |
auto[1] |
auto[1] |
921 |
1 |
|
|
T1 |
10 |
|
T6 |
17 |
|
T17 |
1 |
Summary for Cross jtag_count_backdoor_err_xp
Samples crossed: jtag_csr_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_backdoor_err_xp
Bins
jtag_csr_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38209 |
1 |
|
|
T2 |
85 |
|
T4 |
50 |
|
T11 |
52 |
auto[0] |
auto[1] |
1135 |
1 |
|
|
T11 |
13 |
|
T6 |
13 |
|
T56 |
6 |
auto[1] |
auto[0] |
16766 |
1 |
|
|
T1 |
79 |
|
T5 |
78 |
|
T6 |
532 |
auto[1] |
auto[1] |
867 |
1 |
|
|
T1 |
9 |
|
T6 |
14 |
|
T19 |
3 |
Summary for Cross jtag_transition_err_xp
Samples crossed: jtag_csr_cp transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_err_xp
Bins
jtag_csr_cp | transition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38171 |
1 |
|
|
T2 |
75 |
|
T4 |
50 |
|
T11 |
65 |
auto[0] |
auto[1] |
1173 |
1 |
|
|
T2 |
10 |
|
T6 |
25 |
|
T14 |
8 |
auto[1] |
auto[0] |
16879 |
1 |
|
|
T1 |
88 |
|
T5 |
72 |
|
T6 |
510 |
auto[1] |
auto[1] |
754 |
1 |
|
|
T5 |
6 |
|
T6 |
36 |
|
T15 |
18 |
Summary for Cross jtag_transition_count_err_xp
Samples crossed: jtag_csr_cp transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_count_err_xp
Bins
jtag_csr_cp | transition_count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38198 |
1 |
|
|
T2 |
77 |
|
T4 |
50 |
|
T11 |
65 |
auto[0] |
auto[1] |
1146 |
1 |
|
|
T2 |
8 |
|
T6 |
17 |
|
T14 |
10 |
auto[1] |
auto[0] |
16880 |
1 |
|
|
T1 |
88 |
|
T5 |
70 |
|
T6 |
518 |
auto[1] |
auto[1] |
753 |
1 |
|
|
T5 |
8 |
|
T6 |
28 |
|
T15 |
11 |
Summary for Cross jtag_post_trans_err_xp
Samples crossed: jtag_csr_cp post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_post_trans_err_xp
Bins
jtag_csr_cp | post_trans_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37419 |
1 |
|
|
T2 |
85 |
|
T4 |
50 |
|
T11 |
65 |
auto[0] |
auto[1] |
1925 |
1 |
|
|
T6 |
55 |
|
T193 |
14 |
|
T195 |
15 |
auto[1] |
auto[0] |
16324 |
1 |
|
|
T1 |
88 |
|
T5 |
78 |
|
T6 |
546 |
auto[1] |
auto[1] |
1309 |
1 |
|
|
T17 |
12 |
|
T32 |
26 |
|
T85 |
29 |