Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

114798323

1

T1

129026

T2

33651

T3

1030

auto[1]

1464752

1

T1

2842

T2

396

T4

693

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

114809841

1

T1

128438

T2

33156

T3

1030

auto[1]

1453234

1

T1

3430

T2

891

T4

1584

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	8050036	1			T1	21459		T2	7460		T3	71
auto[IdleSt]	23661568	1			T1	6313		T2	7195		T3	50
auto[ClkMuxSt]	37562	1			T2	85		T4	38		T5	78
auto[CntIncrSt]	37189	1			T2	85		T4	38		T5	78
auto[CntProgSt]	1621659	1			T2	2562		T4	65		T5	128
auto[TransCheckSt]	28827	1			T2	64		T4	27		T5	58
auto[TokenHashSt]	46750798	1			T2	592		T4	292		T5	2828
auto[FlashRmaSt]	30373	1			T2	31		T4	54		T5	20
auto[TokenCheck0St]	13492	1			T2	26		T4	21		T5	16
auto[TokenCheck1St]	10064	1			T2	12		T4	14		T5	9
auto[TransProgSt]	448929	1			T2	536		T4	27		T5	17
auto[PostTransSt]	13833114	1			T2	13588		T3	909		T10	813
auto[ScrapSt]	185515	1			T6	1829		T15	253		T34	3
auto[EscalateSt]	7649116	1			T1	25153		T2	1811		T4	3067
auto[InvalidSt]	13902745	1			T1	78935		T4	934		T11	6947

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	2088	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	13902745	1			T1	78935		T4	934		T11	6947
EscalateSt	7649116	1			T1	25153		T2	1811		T4	3067
ScrapSt	185515	1			T6	1829		T15	253		T34	3
PostTransSt	13833114	1			T2	13588		T3	909		T10	813
TransProgSt	448929	1			T2	536		T4	27		T5	17
TokenCheck1St	10064	1			T2	12		T4	14		T5	9
TokenCheck0St	13492	1			T2	26		T4	21		T5	16
FlashRmaSt	30373	1			T2	31		T4	54		T5	20
TokenHashSt	46750798	1			T2	592		T4	292		T5	2828
TransCheckSt	28827	1			T2	64		T4	27		T5	58
CntProgSt	1621659	1			T2	2562		T4	65		T5	128
CntIncrSt	37189	1			T2	85		T4	38		T5	78
ClkMuxSt	37562	1			T2	85		T4	38		T5	78
IdleSt	23661568	1			T1	6313		T2	7195		T3	50
ResetSt	8050036	1			T1	21459		T2	7460		T3	71
arcs[ResetSt=>IdleSt]	57229	1			T1	80		T2	86		T3	1
arcs[IdleSt=>ScrapSt]	354	1			T6	4		T15	1		T34	1
arcs[IdleSt=>ClkMuxSt]	37251	1			T2	85		T4	38		T5	78
arcs[ClkMuxSt=>CntIncrSt]	37189	1			T2	85		T4	38		T5	78
arcs[CntIncrSt=>PostTransSt]	1901	1			T2	8		T5	8		T6	45
arcs[CntIncrSt=>CntProgSt]	35225	1			T2	77		T4	38		T5	70
arcs[CntProgSt=>PostTransSt]	5325	1			T2	13		T4	11		T5	12
arcs[CntProgSt=>TransCheckSt]	28827	1			T2	64		T4	27		T5	58
arcs[TransCheckSt=>PostTransSt]	3747	1			T2	10		T5	6		T6	61
arcs[TransCheckSt=>TokenHashSt]	24966	1			T2	54		T4	27		T5	52
arcs[TokenHashSt=>PostTransSt]	10649	1			T2	28		T4	6		T5	36
arcs[TokenHashSt=>FlashRmaSt]	13587	1			T2	26		T4	21		T5	16
arcs[FlashRmaSt=>TokenCheck0St]	13492	1			T2	26		T4	21		T5	16
arcs[TokenCheck0St=>PostTransSt]	3404	1			T2	14		T4	7		T5	7
arcs[TokenCheck0St=>TokenCheck1St]	10064	1			T2	12		T4	14		T5	9
arcs[TokenCheck1St=>PostTransSt]	694	1			T2	1		T6	6		T12	2
arcs[TransProgSt=>PostTransSt]	8476	1			T2	11		T4	14		T5	9
arcs[IdleSt=>EscalateSt]	128	1			T42	5		T43	6		T46	7
arcs[ClkMuxSt=>EscalateSt]	62	1			T34	1		T41	3		T42	3
arcs[CntIncrSt=>EscalateSt]	63	1			T34	2		T43	2		T44	2
arcs[CntProgSt=>EscalateSt]	1073	1			T34	31		T41	24		T42	25
arcs[TransCheckSt=>EscalateSt]	114	1			T41	1		T45	9		T50	7
arcs[TokenHashSt=>EscalateSt]	729	1			T34	12		T41	17		T42	14
arcs[FlashRmaSt=>EscalateSt]	95	1			T41	1		T42	3		T45	4
arcs[TokenCheck0St=>EscalateSt]	24	1			T34	1		T41	2		T42	1
arcs[TokenCheck1St=>EscalateSt]	140	1			T34	3		T41	6		T42	6
arcs[TransProgSt=>EscalateSt]	754	1			T34	19		T41	23		T42	11
arcs[PostTransSt=>EscalateSt]	5586	1			T2	13		T4	11		T5	13
arcs[InvalidSt=>EscalateSt]	15075	1			T1	64		T4	12		T11	51

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	8049875	1			T1	21459		T2	7460		T3	71
auto[0]	auto[IdleSt]	23661480	1			T1	6313		T2	7195		T3	50
auto[0]	auto[ClkMuxSt]	37518	1			T2	85		T4	38		T5	78
auto[0]	auto[CntIncrSt]	37147	1			T2	85		T4	38		T5	78
auto[0]	auto[CntProgSt]	1620941	1			T2	2562		T4	65		T5	128
auto[0]	auto[TransCheckSt]	28746	1			T2	64		T4	27		T5	58
auto[0]	auto[TokenHashSt]	46750290	1			T2	592		T4	292		T5	2828
auto[0]	auto[FlashRmaSt]	30312	1			T2	31		T4	54		T5	20
auto[0]	auto[TokenCheck0St]	13474	1			T2	26		T4	21		T5	16
auto[0]	auto[TokenCheck1St]	9980	1			T2	12		T4	14		T5	9
auto[0]	auto[TransProgSt]	448429	1			T2	536		T4	27		T5	17
auto[0]	auto[PostTransSt]	13830257	1			T2	13584		T3	909		T10	813
auto[0]	auto[ScrapSt]	185475	1			T6	1829		T15	253		T34	3
auto[0]	auto[EscalateSt]	6197160	1			T1	22340		T2	1419		T4	2381
auto[0]	auto[InvalidSt]	13895151	1			T1	78906		T4	929		T11	6916
auto[1]	auto[ResetSt]	161	1			T34	2		T41	6		T42	4
auto[1]	auto[IdleSt]	88	1			T42	3		T43	3		T46	4
auto[1]	auto[ClkMuxSt]	44	1			T41	3		T42	2		T50	2
auto[1]	auto[CntIncrSt]	42	1			T34	1		T43	1		T44	1
auto[1]	auto[CntProgSt]	718	1			T34	17		T41	18		T42	16
auto[1]	auto[TransCheckSt]	81	1			T41	1		T45	5		T50	6
auto[1]	auto[TokenHashSt]	508	1			T34	9		T41	14		T42	6
auto[1]	auto[FlashRmaSt]	61	1			T41	1		T42	3		T45	3
auto[1]	auto[TokenCheck0St]	18	1			T41	2		T43	1		T191	1
auto[1]	auto[TokenCheck1St]	84	1			T34	3		T41	2		T42	5
auto[1]	auto[TransProgSt]	500	1			T34	12		T41	13		T42	7
auto[1]	auto[PostTransSt]	2857	1			T2	4		T4	2		T5	10
auto[1]	auto[ScrapSt]	40	1			T41	1		T42	2		T45	2
auto[1]	auto[EscalateSt]	1451956	1			T1	2813		T2	392		T4	686
auto[1]	auto[InvalidSt]	7594	1			T1	29		T4	5		T11	31

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	8049859	1			T1	21459		T2	7460		T3	71
auto[0]	auto[IdleSt]	23661482	1			T1	6313		T2	7195		T3	50
auto[0]	auto[ClkMuxSt]	37519	1			T2	85		T4	38		T5	78
auto[0]	auto[CntIncrSt]	37148	1			T2	85		T4	38		T5	78
auto[0]	auto[CntProgSt]	1620940	1			T2	2562		T4	65		T5	128
auto[0]	auto[TransCheckSt]	28754	1			T2	64		T4	27		T5	58
auto[0]	auto[TokenHashSt]	46750305	1			T2	592		T4	292		T5	2828
auto[0]	auto[FlashRmaSt]	30302	1			T2	31		T4	54		T5	20
auto[0]	auto[TokenCheck0St]	13478	1			T2	26		T4	21		T5	16
auto[0]	auto[TokenCheck1St]	9966	1			T2	12		T4	14		T5	9
auto[0]	auto[TransProgSt]	448411	1			T2	536		T4	27		T5	17
auto[0]	auto[PostTransSt]	13830318	1			T2	13579		T3	909		T10	813
auto[0]	auto[ScrapSt]	185462	1			T6	1829		T15	253		T34	2
auto[0]	auto[EscalateSt]	6208545	1			T1	21758		T2	929		T4	1499
auto[0]	auto[InvalidSt]	13895264	1			T1	78900		T4	927		T11	6927
auto[1]	auto[ResetSt]	177	1			T34	4		T41	6		T42	6
auto[1]	auto[IdleSt]	86	1			T42	3		T43	5		T46	4
auto[1]	auto[ClkMuxSt]	43	1			T34	1		T41	1		T42	3
auto[1]	auto[CntIncrSt]	41	1			T34	1		T43	2		T44	1
auto[1]	auto[CntProgSt]	719	1			T34	24		T41	17		T42	14
auto[1]	auto[TransCheckSt]	73	1			T45	5		T50	3		T44	3
auto[1]	auto[TokenHashSt]	493	1			T34	8		T41	11		T42	10
auto[1]	auto[FlashRmaSt]	71	1			T42	2		T45	4		T50	1
auto[1]	auto[TokenCheck0St]	14	1			T34	1		T42	1		T192	1
auto[1]	auto[TokenCheck1St]	98	1			T34	2		T41	5		T42	4
auto[1]	auto[TransProgSt]	518	1			T34	14		T41	15		T42	7
auto[1]	auto[PostTransSt]	2796	1			T2	9		T4	9		T5	3
auto[1]	auto[ScrapSt]	53	1			T34	1		T42	1		T45	3
auto[1]	auto[EscalateSt]	1440571	1			T1	3395		T2	882		T4	1568
auto[1]	auto[InvalidSt]	7481	1			T1	35		T4	7		T11	20