Summary for Variable clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52494 |
1 |
|
|
T1 |
7 |
|
T2 |
63 |
|
T3 |
10 |
auto[1] |
1914 |
1 |
|
|
T38 |
10 |
|
T39 |
19 |
|
T4 |
23 |
Summary for Variable clk_byp_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53631 |
1 |
|
|
T1 |
7 |
|
T2 |
63 |
|
T3 |
10 |
auto[1] |
777 |
1 |
|
|
T49 |
16 |
|
T50 |
17 |
|
T70 |
13 |
Summary for Variable count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52644 |
1 |
|
|
T1 |
7 |
|
T2 |
63 |
|
T3 |
10 |
auto[1] |
1764 |
1 |
|
|
T43 |
6 |
|
T44 |
7 |
|
T4 |
32 |
Summary for Variable count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52509 |
1 |
|
|
T1 |
7 |
|
T2 |
63 |
|
T3 |
10 |
auto[1] |
1899 |
1 |
|
|
T15 |
2 |
|
T43 |
8 |
|
T44 |
7 |
Summary for Variable count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52578 |
1 |
|
|
T1 |
7 |
|
T2 |
63 |
|
T3 |
10 |
auto[1] |
1830 |
1 |
|
|
T10 |
1 |
|
T43 |
12 |
|
T44 |
6 |
Summary for Variable err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for err_inj_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
err_inj |
49061 |
1 |
|
|
T2 |
63 |
|
T3 |
10 |
|
T9 |
63 |
no_err_inj |
5347 |
1 |
|
|
T1 |
7 |
|
T10 |
8 |
|
T15 |
6 |
Summary for Variable flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52643 |
1 |
|
|
T1 |
7 |
|
T2 |
63 |
|
T3 |
10 |
auto[1] |
1765 |
1 |
|
|
T38 |
11 |
|
T39 |
11 |
|
T4 |
23 |
Summary for Variable flash_rma_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53658 |
1 |
|
|
T1 |
7 |
|
T2 |
63 |
|
T3 |
10 |
auto[1] |
750 |
1 |
|
|
T49 |
22 |
|
T50 |
14 |
|
T70 |
10 |
Summary for Variable jtag_csr_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for jtag_csr_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
37774 |
1 |
|
|
T2 |
63 |
|
T3 |
10 |
|
T9 |
63 |
auto[1] |
16634 |
1 |
|
|
T1 |
7 |
|
T4 |
189 |
|
T5 |
69 |
Summary for Variable kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for kmac_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52465 |
1 |
|
|
T1 |
7 |
|
T2 |
63 |
|
T3 |
10 |
auto[1] |
1943 |
1 |
|
|
T10 |
1 |
|
T43 |
10 |
|
T44 |
10 |
Summary for Variable lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for lc_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52553 |
1 |
|
|
T1 |
7 |
|
T2 |
63 |
|
T3 |
10 |
auto[1] |
1855 |
1 |
|
|
T43 |
12 |
|
T44 |
9 |
|
T4 |
30 |
Summary for Variable otp_lc_data_i_valid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_lc_data_i_valid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52578 |
1 |
|
|
T1 |
7 |
|
T2 |
63 |
|
T3 |
10 |
auto[1] |
1830 |
1 |
|
|
T10 |
1 |
|
T43 |
12 |
|
T44 |
14 |
Summary for Variable otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_partition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52605 |
1 |
|
|
T1 |
7 |
|
T2 |
63 |
|
T3 |
10 |
auto[1] |
1803 |
1 |
|
|
T38 |
12 |
|
T39 |
8 |
|
T4 |
29 |
Summary for Variable otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_prog_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51975 |
1 |
|
|
T1 |
7 |
|
T2 |
63 |
|
T9 |
63 |
auto[1] |
2433 |
1 |
|
|
T3 |
10 |
|
T12 |
3 |
|
T68 |
19 |
Summary for Variable otp_rma_token_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_rma_token_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53631 |
1 |
|
|
T1 |
7 |
|
T2 |
63 |
|
T3 |
10 |
auto[1] |
777 |
1 |
|
|
T49 |
18 |
|
T50 |
13 |
|
T70 |
10 |
Summary for Variable otp_secrets_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_secrets_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53588 |
1 |
|
|
T1 |
7 |
|
T2 |
63 |
|
T3 |
10 |
auto[1] |
820 |
1 |
|
|
T49 |
24 |
|
T50 |
14 |
|
T70 |
10 |
Summary for Variable otp_test_tokens_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_test_tokens_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53653 |
1 |
|
|
T1 |
7 |
|
T2 |
63 |
|
T3 |
10 |
auto[1] |
755 |
1 |
|
|
T49 |
18 |
|
T50 |
15 |
|
T70 |
11 |
Summary for Variable post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for post_trans_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51606 |
1 |
|
|
T1 |
7 |
|
T2 |
63 |
|
T3 |
10 |
auto[1] |
2802 |
1 |
|
|
T10 |
13 |
|
T15 |
12 |
|
T4 |
52 |
Summary for Variable security_escalation_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for security_escalation_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50369 |
1 |
|
|
T1 |
7 |
|
T2 |
63 |
|
T3 |
10 |
auto[1] |
4039 |
1 |
|
|
T57 |
100 |
|
T60 |
99 |
|
T58 |
95 |
Summary for Variable state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52557 |
1 |
|
|
T1 |
7 |
|
T2 |
63 |
|
T3 |
10 |
auto[1] |
1851 |
1 |
|
|
T10 |
2 |
|
T15 |
2 |
|
T43 |
6 |
Summary for Variable state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52567 |
1 |
|
|
T1 |
7 |
|
T2 |
63 |
|
T3 |
10 |
auto[1] |
1841 |
1 |
|
|
T15 |
2 |
|
T43 |
9 |
|
T44 |
11 |
Summary for Variable state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52510 |
1 |
|
|
T1 |
7 |
|
T2 |
63 |
|
T3 |
10 |
auto[1] |
1898 |
1 |
|
|
T43 |
10 |
|
T44 |
11 |
|
T4 |
29 |
Summary for Variable token_invalid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_invalid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52661 |
1 |
|
|
T1 |
7 |
|
T2 |
63 |
|
T3 |
10 |
auto[1] |
1747 |
1 |
|
|
T38 |
15 |
|
T39 |
7 |
|
T4 |
22 |
Summary for Variable token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mismatch_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
48847 |
1 |
|
|
T1 |
7 |
|
T3 |
10 |
|
T10 |
13 |
auto[1] |
5561 |
1 |
|
|
T2 |
63 |
|
T9 |
63 |
|
T13 |
63 |
Summary for Variable token_mux_ctrl_redun_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mux_ctrl_redun_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50655 |
1 |
|
|
T1 |
7 |
|
T2 |
63 |
|
T3 |
10 |
auto[1] |
3753 |
1 |
|
|
T16 |
82 |
|
T32 |
96 |
|
T69 |
96 |
Summary for Variable token_mux_digest_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for token_mux_digest_err_cp
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54408 |
1 |
|
|
T1 |
7 |
|
T2 |
63 |
|
T3 |
10 |
Summary for Variable token_response_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_response_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52537 |
1 |
|
|
T1 |
7 |
|
T2 |
63 |
|
T3 |
10 |
auto[1] |
1871 |
1 |
|
|
T38 |
13 |
|
T39 |
11 |
|
T4 |
23 |
Summary for Variable transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52664 |
1 |
|
|
T1 |
7 |
|
T2 |
63 |
|
T3 |
10 |
auto[1] |
1744 |
1 |
|
|
T38 |
8 |
|
T39 |
11 |
|
T4 |
12 |
Summary for Variable transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52567 |
1 |
|
|
T1 |
7 |
|
T2 |
63 |
|
T3 |
10 |
auto[1] |
1841 |
1 |
|
|
T38 |
14 |
|
T39 |
13 |
|
T4 |
13 |
Summary for Cross post_trans_err_inj_xp
Samples crossed: post_trans_err_cp err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_err_inj_xp
Bins
post_trans_err_cp | err_inj_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
err_inj |
47661 |
1 |
|
|
T2 |
63 |
|
T3 |
10 |
|
T9 |
63 |
auto[0] |
no_err_inj |
3945 |
1 |
|
|
T1 |
7 |
|
T17 |
8 |
|
T41 |
15 |
auto[1] |
err_inj |
1400 |
1 |
|
|
T10 |
5 |
|
T15 |
6 |
|
T4 |
26 |
auto[1] |
no_err_inj |
1402 |
1 |
|
|
T10 |
8 |
|
T15 |
6 |
|
T4 |
26 |
Summary for Cross post_trans_state_err_xp
Samples crossed: post_trans_err_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_err_xp
Bins
post_trans_err_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
49943 |
1 |
|
|
T1 |
7 |
|
T2 |
63 |
|
T3 |
10 |
auto[0] |
auto[1] |
1663 |
1 |
|
|
T43 |
9 |
|
T44 |
11 |
|
T4 |
31 |
auto[1] |
auto[0] |
2624 |
1 |
|
|
T10 |
13 |
|
T15 |
10 |
|
T4 |
49 |
auto[1] |
auto[1] |
178 |
1 |
|
|
T15 |
2 |
|
T4 |
3 |
|
T85 |
1 |
Summary for Cross post_trans_lc_fsm_backdoor_err_xp
Samples crossed: post_trans_err_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_lc_fsm_backdoor_err_xp
Bins
post_trans_err_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
49914 |
1 |
|
|
T1 |
7 |
|
T2 |
63 |
|
T3 |
10 |
auto[0] |
auto[1] |
1692 |
1 |
|
|
T43 |
12 |
|
T44 |
9 |
|
T4 |
26 |
auto[1] |
auto[0] |
2639 |
1 |
|
|
T10 |
13 |
|
T15 |
12 |
|
T4 |
48 |
auto[1] |
auto[1] |
163 |
1 |
|
|
T4 |
4 |
|
T98 |
1 |
|
T21 |
5 |
Summary for Cross post_trans_state_illegal_err_xp
Samples crossed: post_trans_err_cp state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_illegal_err_xp
Bins
post_trans_err_cp | state_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
49859 |
1 |
|
|
T1 |
7 |
|
T2 |
63 |
|
T3 |
10 |
auto[0] |
auto[1] |
1747 |
1 |
|
|
T43 |
10 |
|
T44 |
11 |
|
T4 |
27 |
auto[1] |
auto[0] |
2651 |
1 |
|
|
T10 |
13 |
|
T15 |
12 |
|
T4 |
50 |
auto[1] |
auto[1] |
151 |
1 |
|
|
T4 |
2 |
|
T30 |
1 |
|
T21 |
6 |
Summary for Cross post_trans_count_err_xp
Samples crossed: post_trans_err_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_err_xp
Bins
post_trans_err_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
49857 |
1 |
|
|
T1 |
7 |
|
T2 |
63 |
|
T3 |
10 |
auto[0] |
auto[1] |
1749 |
1 |
|
|
T43 |
8 |
|
T44 |
7 |
|
T4 |
38 |
auto[1] |
auto[0] |
2652 |
1 |
|
|
T10 |
13 |
|
T15 |
10 |
|
T4 |
51 |
auto[1] |
auto[1] |
150 |
1 |
|
|
T15 |
2 |
|
T4 |
1 |
|
T85 |
1 |
Summary for Cross post_trans_count_illegal_err_xp
Samples crossed: post_trans_err_cp count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_illegal_err_xp
Bins
post_trans_err_cp | count_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
49912 |
1 |
|
|
T1 |
7 |
|
T2 |
63 |
|
T3 |
10 |
auto[0] |
auto[1] |
1694 |
1 |
|
|
T43 |
12 |
|
T44 |
6 |
|
T4 |
25 |
auto[1] |
auto[0] |
2666 |
1 |
|
|
T10 |
12 |
|
T15 |
12 |
|
T4 |
50 |
auto[1] |
auto[1] |
136 |
1 |
|
|
T10 |
1 |
|
T4 |
2 |
|
T85 |
1 |
Summary for Cross post_trans_count_backdoor_err_xp
Samples crossed: post_trans_err_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_backdoor_err_xp
Bins
post_trans_err_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
49983 |
1 |
|
|
T1 |
7 |
|
T2 |
63 |
|
T3 |
10 |
auto[0] |
auto[1] |
1623 |
1 |
|
|
T43 |
6 |
|
T44 |
7 |
|
T4 |
28 |
auto[1] |
auto[0] |
2661 |
1 |
|
|
T10 |
13 |
|
T15 |
12 |
|
T4 |
48 |
auto[1] |
auto[1] |
141 |
1 |
|
|
T4 |
4 |
|
T30 |
1 |
|
T21 |
4 |
Summary for Cross jtag_clk_byp_error_rsp_xp
Samples crossed: jtag_csr_cp clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_clk_byp_error_rsp_xp
Bins
jtag_csr_cp | clk_byp_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36635 |
1 |
|
|
T2 |
63 |
|
T3 |
10 |
|
T9 |
63 |
auto[0] |
auto[1] |
1139 |
1 |
|
|
T38 |
10 |
|
T39 |
19 |
|
T4 |
16 |
auto[1] |
auto[0] |
15859 |
1 |
|
|
T1 |
7 |
|
T4 |
182 |
|
T5 |
61 |
auto[1] |
auto[1] |
775 |
1 |
|
|
T4 |
7 |
|
T5 |
8 |
|
T19 |
13 |
Summary for Cross jtag_flash_rma_error_rsp_xp
Samples crossed: jtag_csr_cp flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_flash_rma_error_rsp_xp
Bins
jtag_csr_cp | flash_rma_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36729 |
1 |
|
|
T2 |
63 |
|
T3 |
10 |
|
T9 |
63 |
auto[0] |
auto[1] |
1045 |
1 |
|
|
T38 |
11 |
|
T39 |
11 |
|
T4 |
16 |
auto[1] |
auto[0] |
15914 |
1 |
|
|
T1 |
7 |
|
T4 |
182 |
|
T5 |
64 |
auto[1] |
auto[1] |
720 |
1 |
|
|
T4 |
7 |
|
T5 |
5 |
|
T19 |
12 |
Summary for Cross jtag_otp_prog_err_xp
Samples crossed: jtag_csr_cp otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_prog_err_xp
Bins
jtag_csr_cp | otp_prog_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36406 |
1 |
|
|
T2 |
63 |
|
T9 |
63 |
|
T10 |
13 |
auto[0] |
auto[1] |
1368 |
1 |
|
|
T3 |
10 |
|
T12 |
3 |
|
T68 |
19 |
auto[1] |
auto[0] |
15569 |
1 |
|
|
T1 |
7 |
|
T4 |
189 |
|
T5 |
69 |
auto[1] |
auto[1] |
1065 |
1 |
|
|
T21 |
54 |
|
T232 |
20 |
|
T233 |
18 |
Summary for Cross jtag_otp_partition_err_xp
Samples crossed: jtag_csr_cp otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_partition_err_xp
Bins
jtag_csr_cp | otp_partition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36724 |
1 |
|
|
T2 |
63 |
|
T3 |
10 |
|
T9 |
63 |
auto[0] |
auto[1] |
1050 |
1 |
|
|
T38 |
12 |
|
T39 |
8 |
|
T4 |
20 |
auto[1] |
auto[0] |
15881 |
1 |
|
|
T1 |
7 |
|
T4 |
180 |
|
T5 |
66 |
auto[1] |
auto[1] |
753 |
1 |
|
|
T4 |
9 |
|
T5 |
3 |
|
T19 |
11 |
Summary for Cross jtag_token_mismatch_err_xp
Samples crossed: jtag_csr_cp token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_token_mismatch_err_xp
Bins
jtag_csr_cp | token_mismatch_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
32980 |
1 |
|
|
T3 |
10 |
|
T10 |
13 |
|
T12 |
3 |
auto[0] |
auto[1] |
4794 |
1 |
|
|
T2 |
63 |
|
T9 |
63 |
|
T13 |
63 |
auto[1] |
auto[0] |
15867 |
1 |
|
|
T1 |
7 |
|
T4 |
183 |
|
T5 |
55 |
auto[1] |
auto[1] |
767 |
1 |
|
|
T4 |
6 |
|
T5 |
14 |
|
T19 |
11 |
Summary for Cross jtag_state_err_xp
Samples crossed: jtag_csr_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_err_xp
Bins
jtag_csr_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36736 |
1 |
|
|
T2 |
63 |
|
T3 |
10 |
|
T9 |
63 |
auto[0] |
auto[1] |
1038 |
1 |
|
|
T15 |
2 |
|
T43 |
9 |
|
T44 |
11 |
auto[1] |
auto[0] |
15831 |
1 |
|
|
T1 |
7 |
|
T4 |
180 |
|
T5 |
69 |
auto[1] |
auto[1] |
803 |
1 |
|
|
T4 |
9 |
|
T18 |
11 |
|
T21 |
41 |
Summary for Cross jtag_state_backdoor_err_xp
Samples crossed: jtag_csr_cp state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_backdoor_err_xp
Bins
jtag_csr_cp | state_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36673 |
1 |
|
|
T2 |
63 |
|
T3 |
10 |
|
T9 |
63 |
auto[0] |
auto[1] |
1101 |
1 |
|
|
T10 |
2 |
|
T15 |
2 |
|
T43 |
6 |
auto[1] |
auto[0] |
15884 |
1 |
|
|
T1 |
7 |
|
T4 |
175 |
|
T5 |
69 |
auto[1] |
auto[1] |
750 |
1 |
|
|
T4 |
14 |
|
T18 |
13 |
|
T21 |
42 |
Summary for Cross jtag_lc_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_lc_fsm_backdoor_err_xp
Bins
jtag_csr_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36700 |
1 |
|
|
T2 |
63 |
|
T3 |
10 |
|
T9 |
63 |
auto[0] |
auto[1] |
1074 |
1 |
|
|
T43 |
12 |
|
T44 |
9 |
|
T4 |
20 |
auto[1] |
auto[0] |
15853 |
1 |
|
|
T1 |
7 |
|
T4 |
179 |
|
T5 |
69 |
auto[1] |
auto[1] |
781 |
1 |
|
|
T4 |
10 |
|
T18 |
13 |
|
T21 |
35 |
Summary for Cross jtag_kmac_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_kmac_fsm_backdoor_err_xp
Bins
jtag_csr_cp | kmac_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36625 |
1 |
|
|
T2 |
63 |
|
T3 |
10 |
|
T9 |
63 |
auto[0] |
auto[1] |
1149 |
1 |
|
|
T10 |
1 |
|
T43 |
10 |
|
T44 |
10 |
auto[1] |
auto[0] |
15840 |
1 |
|
|
T1 |
7 |
|
T4 |
183 |
|
T5 |
69 |
auto[1] |
auto[1] |
794 |
1 |
|
|
T4 |
6 |
|
T18 |
12 |
|
T21 |
40 |
Summary for Cross jtag_count_err_xp
Samples crossed: jtag_csr_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_err_xp
Bins
jtag_csr_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36674 |
1 |
|
|
T2 |
63 |
|
T3 |
10 |
|
T9 |
63 |
auto[0] |
auto[1] |
1100 |
1 |
|
|
T15 |
2 |
|
T43 |
8 |
|
T44 |
7 |
auto[1] |
auto[0] |
15835 |
1 |
|
|
T1 |
7 |
|
T4 |
179 |
|
T5 |
69 |
auto[1] |
auto[1] |
799 |
1 |
|
|
T4 |
10 |
|
T18 |
4 |
|
T21 |
33 |
Summary for Cross jtag_count_backdoor_err_xp
Samples crossed: jtag_csr_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_backdoor_err_xp
Bins
jtag_csr_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36757 |
1 |
|
|
T2 |
63 |
|
T3 |
10 |
|
T9 |
63 |
auto[0] |
auto[1] |
1017 |
1 |
|
|
T43 |
6 |
|
T44 |
7 |
|
T4 |
24 |
auto[1] |
auto[0] |
15887 |
1 |
|
|
T1 |
7 |
|
T4 |
181 |
|
T5 |
69 |
auto[1] |
auto[1] |
747 |
1 |
|
|
T4 |
8 |
|
T18 |
8 |
|
T21 |
39 |
Summary for Cross jtag_transition_err_xp
Samples crossed: jtag_csr_cp transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_err_xp
Bins
jtag_csr_cp | transition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36750 |
1 |
|
|
T2 |
63 |
|
T3 |
10 |
|
T9 |
63 |
auto[0] |
auto[1] |
1024 |
1 |
|
|
T38 |
14 |
|
T39 |
13 |
|
T4 |
7 |
auto[1] |
auto[0] |
15817 |
1 |
|
|
T1 |
7 |
|
T4 |
183 |
|
T5 |
54 |
auto[1] |
auto[1] |
817 |
1 |
|
|
T4 |
6 |
|
T5 |
15 |
|
T19 |
16 |
Summary for Cross jtag_transition_count_err_xp
Samples crossed: jtag_csr_cp transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_count_err_xp
Bins
jtag_csr_cp | transition_count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36753 |
1 |
|
|
T2 |
63 |
|
T3 |
10 |
|
T9 |
63 |
auto[0] |
auto[1] |
1021 |
1 |
|
|
T38 |
8 |
|
T39 |
11 |
|
T4 |
8 |
auto[1] |
auto[0] |
15911 |
1 |
|
|
T1 |
7 |
|
T4 |
185 |
|
T5 |
60 |
auto[1] |
auto[1] |
723 |
1 |
|
|
T4 |
4 |
|
T5 |
9 |
|
T19 |
14 |
Summary for Cross jtag_post_trans_err_xp
Samples crossed: jtag_csr_cp post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_post_trans_err_xp
Bins
jtag_csr_cp | post_trans_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36237 |
1 |
|
|
T2 |
63 |
|
T3 |
10 |
|
T9 |
63 |
auto[0] |
auto[1] |
1537 |
1 |
|
|
T10 |
13 |
|
T15 |
12 |
|
T4 |
11 |
auto[1] |
auto[0] |
15369 |
1 |
|
|
T1 |
7 |
|
T4 |
148 |
|
T5 |
69 |
auto[1] |
auto[1] |
1265 |
1 |
|
|
T4 |
41 |
|
T21 |
58 |
|
T105 |
11 |