Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

110214385

1

T1

94126

T2

33386

T3

3532

auto[1]

1442693

1

T3

594

T10

198

T12

99

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

110231439

1

T1

94126

T2

33386

T3

3730

auto[1]

1425639

1

T3

396

T10

198

T12

198

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	7583124	1			T1	747		T2	5405		T3	1113
auto[IdleSt]	23947417	1			T1	13902		T2	5522		T3	991
auto[ClkMuxSt]	36498	1			T1	7		T2	63		T3	10
auto[CntIncrSt]	36178	1			T1	7		T2	63		T3	10
auto[CntProgSt]	2186431	1			T1	367		T2	6406		T3	224
auto[TransCheckSt]	28018	1			T1	7		T2	63		T9	63
auto[TokenHashSt]	44275407	1			T1	75792		T2	4793		T9	1303
auto[FlashRmaSt]	29857	1			T1	7		T10	14		T15	6
auto[TokenCheck0St]	13198	1			T1	7		T10	8		T15	6
auto[TokenCheck1St]	10021	1			T1	7		T10	8		T15	6
auto[TransProgSt]	589808	1			T1	527		T10	121		T15	12
auto[PostTransSt]	13968027	1			T1	2749		T2	11071		T3	597
auto[ScrapSt]	414027	1			T41	16		T4	2940		T33	24
auto[EscalateSt]	6997675	1			T3	1181		T10	788		T12	388
auto[InvalidSt]	11539483	1			T10	265		T15	769		T43	8632

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1909	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	11539483	1			T10	265		T15	769		T43	8632
EscalateSt	6997675	1			T3	1181		T10	788		T12	388
ScrapSt	414027	1			T41	16		T4	2940		T33	24
PostTransSt	13968027	1			T1	2749		T2	11071		T3	597
TransProgSt	589808	1			T1	527		T10	121		T15	12
TokenCheck1St	10021	1			T1	7		T10	8		T15	6
TokenCheck0St	13198	1			T1	7		T10	8		T15	6
FlashRmaSt	29857	1			T1	7		T10	14		T15	6
TokenHashSt	44275407	1			T1	75792		T2	4793		T9	1303
TransCheckSt	28018	1			T1	7		T2	63		T9	63
CntProgSt	2186431	1			T1	367		T2	6406		T3	224
CntIncrSt	36178	1			T1	7		T2	63		T3	10
ClkMuxSt	36498	1			T1	7		T2	63		T3	10
IdleSt	23947417	1			T1	13902		T2	5522		T3	991
ResetSt	7583124	1			T1	747		T2	5405		T3	1113
arcs[ResetSt=>IdleSt]	54582	1			T1	7		T2	64		T3	11
arcs[IdleSt=>ScrapSt]	316	1			T41	1		T4	7		T33	1
arcs[IdleSt=>ClkMuxSt]	36246	1			T1	7		T2	63		T3	10
arcs[ClkMuxSt=>CntIncrSt]	36178	1			T1	7		T2	63		T3	10
arcs[CntIncrSt=>PostTransSt]	1749	1			T38	8		T39	11		T4	12
arcs[CntIncrSt=>CntProgSt]	34356	1			T1	7		T2	63		T3	10
arcs[CntProgSt=>PostTransSt]	5094	1			T3	10		T12	3		T38	10
arcs[CntProgSt=>TransCheckSt]	28018	1			T1	7		T2	63		T9	63
arcs[TransCheckSt=>PostTransSt]	3682	1			T16	39		T38	14		T39	13
arcs[TransCheckSt=>TokenHashSt]	24235	1			T1	7		T2	63		T9	63
arcs[TokenHashSt=>PostTransSt]	10249	1			T2	63		T9	63		T13	63
arcs[TokenHashSt=>FlashRmaSt]	13294	1			T1	7		T10	8		T15	6
arcs[FlashRmaSt=>TokenCheck0St]	13198	1			T1	7		T10	8		T15	6
arcs[TokenCheck0St=>PostTransSt]	3151	1			T16	19		T38	11		T39	11
arcs[TokenCheck0St=>TokenCheck1St]	10021	1			T1	7		T10	8		T15	6
arcs[TokenCheck1St=>PostTransSt]	699	1			T16	12		T19	1		T32	14
arcs[TransProgSt=>PostTransSt]	8346	1			T1	7		T10	8		T15	6
arcs[IdleSt=>EscalateSt]	192	1			T58	9		T61	8		T62	7
arcs[ClkMuxSt=>EscalateSt]	68	1			T57	2		T58	1		T59	1
arcs[CntIncrSt=>EscalateSt]	73	1			T57	5		T60	2		T58	2
arcs[CntProgSt=>EscalateSt]	1244	1			T57	44		T60	29		T58	42
arcs[TransCheckSt=>EscalateSt]	101	1			T57	1		T60	7		T61	9
arcs[TokenHashSt=>EscalateSt]	691	1			T4	2		T57	13		T60	22
arcs[FlashRmaSt=>EscalateSt]	96	1			T57	1		T60	2		T58	1
arcs[TokenCheck0St=>EscalateSt]	26	1			T57	2		T59	1		T63	2
arcs[TokenCheck1St=>EscalateSt]	157	1			T57	3		T60	3		T58	4
arcs[TransProgSt=>EscalateSt]	819	1			T57	23		T60	24		T58	24
arcs[PostTransSt=>EscalateSt]	5372	1			T3	10		T12	3		T38	10
arcs[InvalidSt=>EscalateSt]	13815	1			T10	4		T15	6		T43	63

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7582950	1			T1	747		T2	5405		T3	1113
auto[0]	auto[IdleSt]	23947288	1			T1	13902		T2	5522		T3	991
auto[0]	auto[ClkMuxSt]	36452	1			T1	7		T2	63		T3	10
auto[0]	auto[CntIncrSt]	36129	1			T1	7		T2	63		T3	10
auto[0]	auto[CntProgSt]	2185601	1			T1	367		T2	6406		T3	224
auto[0]	auto[TransCheckSt]	27950	1			T1	7		T2	63		T9	63
auto[0]	auto[TokenHashSt]	44274929	1			T1	75792		T2	4793		T9	1303
auto[0]	auto[FlashRmaSt]	29794	1			T1	7		T10	14		T15	6
auto[0]	auto[TokenCheck0St]	13183	1			T1	7		T10	8		T15	6
auto[0]	auto[TokenCheck1St]	9912	1			T1	7		T10	8		T15	6
auto[0]	auto[TransProgSt]	589262	1			T1	527		T10	121		T15	12
auto[0]	auto[PostTransSt]	13965324	1			T1	2749		T2	11071		T3	591
auto[0]	auto[ScrapSt]	413978	1			T41	16		T4	2940		T33	24
auto[0]	auto[EscalateSt]	5567229	1			T3	593		T10	592		T12	290
auto[0]	auto[InvalidSt]	11532495	1			T10	263		T15	767		T43	8597
auto[1]	auto[ResetSt]	174	1			T57	3		T60	5		T58	3
auto[1]	auto[IdleSt]	129	1			T58	7		T61	5		T62	5
auto[1]	auto[ClkMuxSt]	46	1			T57	2		T58	1		T59	1
auto[1]	auto[CntIncrSt]	49	1			T57	4		T60	1		T58	2
auto[1]	auto[CntProgSt]	830	1			T57	29		T60	18		T58	33
auto[1]	auto[TransCheckSt]	68	1			T60	4		T61	7		T62	3
auto[1]	auto[TokenHashSt]	478	1			T4	1		T57	7		T60	15
auto[1]	auto[FlashRmaSt]	63	1			T57	1		T60	2		T58	1
auto[1]	auto[TokenCheck0St]	15	1			T57	1		T230	1		T231	3
auto[1]	auto[TokenCheck1St]	109	1			T57	3		T60	2		T58	1
auto[1]	auto[TransProgSt]	546	1			T57	17		T60	16		T58	17
auto[1]	auto[PostTransSt]	2703	1			T3	6		T12	1		T38	5
auto[1]	auto[ScrapSt]	49	1			T57	1		T58	1		T59	1
auto[1]	auto[EscalateSt]	1430446	1			T3	588		T10	196		T12	98
auto[1]	auto[InvalidSt]	6988	1			T10	2		T15	2		T43	35

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7582950	1			T1	747		T2	5405		T3	1113
auto[0]	auto[IdleSt]	23947286	1			T1	13902		T2	5522		T3	991
auto[0]	auto[ClkMuxSt]	36450	1			T1	7		T2	63		T3	10
auto[0]	auto[CntIncrSt]	36133	1			T1	7		T2	63		T3	10
auto[0]	auto[CntProgSt]	2185581	1			T1	367		T2	6406		T3	224
auto[0]	auto[TransCheckSt]	27955	1			T1	7		T2	63		T9	63
auto[0]	auto[TokenHashSt]	44274958	1			T1	75792		T2	4793		T9	1303
auto[0]	auto[FlashRmaSt]	29794	1			T1	7		T10	14		T15	6
auto[0]	auto[TokenCheck0St]	13181	1			T1	7		T10	8		T15	6
auto[0]	auto[TokenCheck1St]	9914	1			T1	7		T10	8		T15	6
auto[0]	auto[TransProgSt]	589272	1			T1	527		T10	121		T15	12
auto[0]	auto[PostTransSt]	13965280	1			T1	2749		T2	11071		T3	593
auto[0]	auto[ScrapSt]	413978	1			T41	16		T4	2940		T33	24
auto[0]	auto[EscalateSt]	5584142	1			T3	789		T10	592		T12	192
auto[0]	auto[InvalidSt]	11532656	1			T10	263		T15	765		T43	8604
auto[1]	auto[ResetSt]	174	1			T57	3		T60	1		T58	3
auto[1]	auto[IdleSt]	131	1			T58	7		T61	7		T62	5
auto[1]	auto[ClkMuxSt]	48	1			T57	2		T58	1		T61	1
auto[1]	auto[CntIncrSt]	45	1			T57	1		T60	2		T58	2
auto[1]	auto[CntProgSt]	850	1			T57	29		T60	20		T58	25
auto[1]	auto[TransCheckSt]	63	1			T57	1		T60	4		T61	4
auto[1]	auto[TokenHashSt]	449	1			T4	1		T57	10		T60	16
auto[1]	auto[FlashRmaSt]	63	1			T60	1		T58	1		T59	2
auto[1]	auto[TokenCheck0St]	17	1			T57	1		T59	1		T63	2
auto[1]	auto[TokenCheck1St]	107	1			T57	3		T60	1		T58	3
auto[1]	auto[TransProgSt]	536	1			T57	16		T60	16		T58	15
auto[1]	auto[PostTransSt]	2747	1			T3	4		T12	2		T38	5
auto[1]	auto[ScrapSt]	49	1			T57	1		T58	1		T59	1
auto[1]	auto[EscalateSt]	1413533	1			T3	392		T10	196		T12	196
auto[1]	auto[InvalidSt]	6827	1			T10	2		T15	4		T43	28