Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.63 97.99 96.04 93.38 95.35 98.55 99.00 96.11


Total test records in report: 1000
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T806 /workspace/coverage/default/19.lc_ctrl_jtag_errors.1491656086 Jun 25 06:22:23 PM PDT 24 Jun 25 06:22:55 PM PDT 24 2741162692 ps
T807 /workspace/coverage/default/42.lc_ctrl_sec_mubi.1138013615 Jun 25 06:24:24 PM PDT 24 Jun 25 06:25:12 PM PDT 24 2668585476 ps
T808 /workspace/coverage/default/15.lc_ctrl_security_escalation.2129681921 Jun 25 06:21:45 PM PDT 24 Jun 25 06:21:59 PM PDT 24 1339302498 ps
T809 /workspace/coverage/default/9.lc_ctrl_sec_token_mux.1001335269 Jun 25 06:20:56 PM PDT 24 Jun 25 06:21:07 PM PDT 24 1038130060 ps
T810 /workspace/coverage/default/47.lc_ctrl_volatile_unlock_smoke.546218862 Jun 25 06:24:45 PM PDT 24 Jun 25 06:25:05 PM PDT 24 14530926 ps
T811 /workspace/coverage/default/44.lc_ctrl_sec_token_digest.2144998112 Jun 25 06:24:38 PM PDT 24 Jun 25 06:25:18 PM PDT 24 467702893 ps
T812 /workspace/coverage/default/26.lc_ctrl_state_post_trans.3885511189 Jun 25 06:22:53 PM PDT 24 Jun 25 06:23:01 PM PDT 24 346402323 ps
T813 /workspace/coverage/default/1.lc_ctrl_regwen_during_op.2479958897 Jun 25 06:18:45 PM PDT 24 Jun 25 06:19:04 PM PDT 24 2183188063 ps
T814 /workspace/coverage/default/5.lc_ctrl_smoke.2853654005 Jun 25 06:20:03 PM PDT 24 Jun 25 06:20:07 PM PDT 24 203673752 ps
T815 /workspace/coverage/default/3.lc_ctrl_jtag_access.1318446885 Jun 25 06:19:37 PM PDT 24 Jun 25 06:19:47 PM PDT 24 727365696 ps
T816 /workspace/coverage/default/20.lc_ctrl_sec_token_mux.2169843741 Jun 25 06:22:33 PM PDT 24 Jun 25 06:22:43 PM PDT 24 472368030 ps
T817 /workspace/coverage/default/3.lc_ctrl_stress_all.4231851230 Jun 25 06:19:34 PM PDT 24 Jun 25 06:20:46 PM PDT 24 43247107303 ps
T818 /workspace/coverage/default/43.lc_ctrl_volatile_unlock_smoke.3202906201 Jun 25 06:24:33 PM PDT 24 Jun 25 06:25:01 PM PDT 24 13581118 ps
T819 /workspace/coverage/default/1.lc_ctrl_stress_all.558461814 Jun 25 06:19:01 PM PDT 24 Jun 25 06:21:29 PM PDT 24 25908409990 ps
T820 /workspace/coverage/default/35.lc_ctrl_jtag_access.562525670 Jun 25 06:23:43 PM PDT 24 Jun 25 06:23:53 PM PDT 24 398115216 ps
T821 /workspace/coverage/default/13.lc_ctrl_jtag_access.1336415286 Jun 25 06:21:30 PM PDT 24 Jun 25 06:21:49 PM PDT 24 1262011892 ps
T822 /workspace/coverage/default/44.lc_ctrl_state_failure.874579212 Jun 25 06:24:33 PM PDT 24 Jun 25 06:25:29 PM PDT 24 473750570 ps
T823 /workspace/coverage/default/32.lc_ctrl_sec_token_mux.1071953484 Jun 25 06:23:34 PM PDT 24 Jun 25 06:23:50 PM PDT 24 5959991709 ps
T824 /workspace/coverage/default/43.lc_ctrl_smoke.1925838239 Jun 25 06:24:32 PM PDT 24 Jun 25 06:25:02 PM PDT 24 63530330 ps
T825 /workspace/coverage/default/43.lc_ctrl_alert_test.552682270 Jun 25 06:24:35 PM PDT 24 Jun 25 06:25:01 PM PDT 24 52228439 ps
T826 /workspace/coverage/default/12.lc_ctrl_state_post_trans.3154277194 Jun 25 06:21:21 PM PDT 24 Jun 25 06:21:28 PM PDT 24 219867434 ps
T827 /workspace/coverage/default/10.lc_ctrl_security_escalation.3929593261 Jun 25 06:21:05 PM PDT 24 Jun 25 06:21:18 PM PDT 24 742998386 ps
T828 /workspace/coverage/default/30.lc_ctrl_prog_failure.274986506 Jun 25 06:23:22 PM PDT 24 Jun 25 06:23:27 PM PDT 24 69588027 ps
T829 /workspace/coverage/default/22.lc_ctrl_errors.3168908118 Jun 25 06:22:39 PM PDT 24 Jun 25 06:22:49 PM PDT 24 1426469111 ps
T830 /workspace/coverage/default/12.lc_ctrl_jtag_smoke.167835108 Jun 25 06:21:22 PM PDT 24 Jun 25 06:21:25 PM PDT 24 238419619 ps
T831 /workspace/coverage/default/41.lc_ctrl_state_post_trans.1665725938 Jun 25 06:24:21 PM PDT 24 Jun 25 06:24:59 PM PDT 24 338052673 ps
T832 /workspace/coverage/default/8.lc_ctrl_sec_token_mux.4199877827 Jun 25 06:20:49 PM PDT 24 Jun 25 06:20:58 PM PDT 24 280914562 ps
T833 /workspace/coverage/default/30.lc_ctrl_security_escalation.3044915944 Jun 25 06:23:24 PM PDT 24 Jun 25 06:23:35 PM PDT 24 550009310 ps
T127 /workspace/coverage/default/1.lc_ctrl_sec_cm.1458165018 Jun 25 06:19:01 PM PDT 24 Jun 25 06:19:24 PM PDT 24 721370518 ps
T834 /workspace/coverage/default/5.lc_ctrl_jtag_regwen_during_op.3420933207 Jun 25 06:20:14 PM PDT 24 Jun 25 06:20:40 PM PDT 24 3287523015 ps
T835 /workspace/coverage/default/34.lc_ctrl_errors.96221727 Jun 25 06:23:43 PM PDT 24 Jun 25 06:24:01 PM PDT 24 502241396 ps
T836 /workspace/coverage/default/34.lc_ctrl_smoke.2510595145 Jun 25 06:23:44 PM PDT 24 Jun 25 06:23:54 PM PDT 24 1688643312 ps
T837 /workspace/coverage/default/6.lc_ctrl_jtag_regwen_during_op.3898383654 Jun 25 06:20:23 PM PDT 24 Jun 25 06:20:40 PM PDT 24 5548290446 ps
T838 /workspace/coverage/default/27.lc_ctrl_errors.3365606910 Jun 25 06:23:10 PM PDT 24 Jun 25 06:23:26 PM PDT 24 983873320 ps
T839 /workspace/coverage/default/3.lc_ctrl_alert_test.177087390 Jun 25 06:19:35 PM PDT 24 Jun 25 06:19:37 PM PDT 24 27220773 ps
T840 /workspace/coverage/default/16.lc_ctrl_volatile_unlock_smoke.4193041790 Jun 25 06:21:53 PM PDT 24 Jun 25 06:21:55 PM PDT 24 14754462 ps
T841 /workspace/coverage/default/34.lc_ctrl_security_escalation.2891830229 Jun 25 06:23:44 PM PDT 24 Jun 25 06:24:03 PM PDT 24 1366250204 ps
T842 /workspace/coverage/default/3.lc_ctrl_jtag_prog_failure.3918830065 Jun 25 06:19:34 PM PDT 24 Jun 25 06:19:55 PM PDT 24 1146003829 ps
T843 /workspace/coverage/default/33.lc_ctrl_alert_test.825808992 Jun 25 06:23:42 PM PDT 24 Jun 25 06:23:47 PM PDT 24 18596547 ps
T844 /workspace/coverage/default/33.lc_ctrl_sec_token_digest.3754296967 Jun 25 06:23:42 PM PDT 24 Jun 25 06:23:56 PM PDT 24 229238437 ps
T845 /workspace/coverage/default/38.lc_ctrl_state_failure.3038145609 Jun 25 06:24:07 PM PDT 24 Jun 25 06:24:51 PM PDT 24 956679773 ps
T846 /workspace/coverage/default/7.lc_ctrl_state_post_trans.3283773488 Jun 25 06:20:34 PM PDT 24 Jun 25 06:20:43 PM PDT 24 355359123 ps
T847 /workspace/coverage/default/24.lc_ctrl_stress_all.3221182828 Jun 25 06:22:46 PM PDT 24 Jun 25 06:25:35 PM PDT 24 102914549130 ps
T848 /workspace/coverage/default/14.lc_ctrl_jtag_access.3546765676 Jun 25 06:21:46 PM PDT 24 Jun 25 06:21:53 PM PDT 24 1797413232 ps
T849 /workspace/coverage/default/2.lc_ctrl_regwen_during_op.2523480676 Jun 25 06:19:10 PM PDT 24 Jun 25 06:19:34 PM PDT 24 349445642 ps
T850 /workspace/coverage/default/29.lc_ctrl_errors.4253423129 Jun 25 06:23:18 PM PDT 24 Jun 25 06:23:29 PM PDT 24 1152798616 ps
T851 /workspace/coverage/default/3.lc_ctrl_jtag_state_post_trans.311790920 Jun 25 06:19:36 PM PDT 24 Jun 25 06:19:54 PM PDT 24 15851488699 ps
T852 /workspace/coverage/default/11.lc_ctrl_stress_all.2758426846 Jun 25 06:21:20 PM PDT 24 Jun 25 06:28:34 PM PDT 24 14191298118 ps
T853 /workspace/coverage/default/15.lc_ctrl_sec_token_digest.3569351047 Jun 25 06:21:46 PM PDT 24 Jun 25 06:21:58 PM PDT 24 297713979 ps
T854 /workspace/coverage/default/12.lc_ctrl_alert_test.2624807334 Jun 25 06:21:29 PM PDT 24 Jun 25 06:21:31 PM PDT 24 85181371 ps
T855 /workspace/coverage/default/42.lc_ctrl_state_failure.699246911 Jun 25 06:24:24 PM PDT 24 Jun 25 06:25:20 PM PDT 24 513028483 ps
T856 /workspace/coverage/default/4.lc_ctrl_security_escalation.3473951195 Jun 25 06:19:42 PM PDT 24 Jun 25 06:19:48 PM PDT 24 213810673 ps
T857 /workspace/coverage/default/17.lc_ctrl_security_escalation.1448853599 Jun 25 06:22:05 PM PDT 24 Jun 25 06:22:15 PM PDT 24 669801381 ps
T858 /workspace/coverage/default/0.lc_ctrl_state_post_trans.1326892365 Jun 25 06:18:21 PM PDT 24 Jun 25 06:18:26 PM PDT 24 83837068 ps
T859 /workspace/coverage/default/21.lc_ctrl_sec_token_mux.2417275610 Jun 25 06:22:41 PM PDT 24 Jun 25 06:22:50 PM PDT 24 235195620 ps
T860 /workspace/coverage/default/40.lc_ctrl_state_failure.1862379346 Jun 25 06:24:07 PM PDT 24 Jun 25 06:24:46 PM PDT 24 775121172 ps
T861 /workspace/coverage/default/7.lc_ctrl_sec_mubi.1026195933 Jun 25 06:20:34 PM PDT 24 Jun 25 06:20:52 PM PDT 24 652349531 ps
T862 /workspace/coverage/default/44.lc_ctrl_sec_token_mux.1985404184 Jun 25 06:24:40 PM PDT 24 Jun 25 06:25:15 PM PDT 24 777813144 ps
T863 /workspace/coverage/default/39.lc_ctrl_security_escalation.2320535408 Jun 25 06:24:07 PM PDT 24 Jun 25 06:24:38 PM PDT 24 293827011 ps
T864 /workspace/coverage/default/11.lc_ctrl_state_failure.3568255411 Jun 25 06:21:14 PM PDT 24 Jun 25 06:21:39 PM PDT 24 1061675974 ps
T865 /workspace/coverage/default/31.lc_ctrl_stress_all.3070747899 Jun 25 06:23:35 PM PDT 24 Jun 25 06:27:47 PM PDT 24 8134015665 ps
T866 /workspace/coverage/default/46.lc_ctrl_stress_all.1330713666 Jun 25 06:24:45 PM PDT 24 Jun 25 06:27:11 PM PDT 24 10791164108 ps
T867 /workspace/coverage/default/6.lc_ctrl_jtag_access.2274896169 Jun 25 06:20:26 PM PDT 24 Jun 25 06:20:30 PM PDT 24 509770331 ps
T868 /workspace/coverage/default/13.lc_ctrl_errors.213754121 Jun 25 06:21:32 PM PDT 24 Jun 25 06:21:48 PM PDT 24 587903220 ps
T869 /workspace/coverage/default/37.lc_ctrl_volatile_unlock_smoke.1276904183 Jun 25 06:23:50 PM PDT 24 Jun 25 06:23:55 PM PDT 24 13571295 ps
T153 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.3329193858 Jun 25 05:22:45 PM PDT 24 Jun 25 05:22:48 PM PDT 24 50258812 ps
T154 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.521971884 Jun 25 05:22:37 PM PDT 24 Jun 25 05:22:50 PM PDT 24 18285509032 ps
T150 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.984601786 Jun 25 05:22:41 PM PDT 24 Jun 25 05:22:44 PM PDT 24 17256910 ps
T142 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.2897723545 Jun 25 05:22:27 PM PDT 24 Jun 25 05:22:31 PM PDT 24 284995543 ps
T143 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.1952462313 Jun 25 05:22:37 PM PDT 24 Jun 25 05:22:42 PM PDT 24 273936559 ps
T222 /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.3913258838 Jun 25 05:22:56 PM PDT 24 Jun 25 05:22:58 PM PDT 24 26431264 ps
T175 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.1983991720 Jun 25 05:22:29 PM PDT 24 Jun 25 05:22:32 PM PDT 24 81193923 ps
T182 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.3671033156 Jun 25 05:22:37 PM PDT 24 Jun 25 05:22:41 PM PDT 24 164237693 ps
T145 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3151447359 Jun 25 05:22:48 PM PDT 24 Jun 25 05:22:53 PM PDT 24 817830524 ps
T183 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.3153665101 Jun 25 05:22:39 PM PDT 24 Jun 25 05:22:42 PM PDT 24 14070789 ps
T144 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.2985304231 Jun 25 05:22:56 PM PDT 24 Jun 25 05:22:59 PM PDT 24 152718413 ps
T184 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.2782334347 Jun 25 05:22:47 PM PDT 24 Jun 25 05:22:51 PM PDT 24 60074679 ps
T174 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.962344384 Jun 25 05:22:47 PM PDT 24 Jun 25 05:22:53 PM PDT 24 152925641 ps
T171 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3644897651 Jun 25 05:22:31 PM PDT 24 Jun 25 05:22:38 PM PDT 24 366412201 ps
T870 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.3158398099 Jun 25 05:22:37 PM PDT 24 Jun 25 05:22:41 PM PDT 24 15595449 ps
T223 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.2951641374 Jun 25 05:22:30 PM PDT 24 Jun 25 05:22:35 PM PDT 24 14130696 ps
T147 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.308743164 Jun 25 05:22:45 PM PDT 24 Jun 25 05:22:48 PM PDT 24 26692097 ps
T146 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.3214674312 Jun 25 05:22:48 PM PDT 24 Jun 25 05:22:53 PM PDT 24 35423895 ps
T871 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.4075585468 Jun 25 05:22:37 PM PDT 24 Jun 25 05:22:42 PM PDT 24 193006464 ps
T872 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.2831284411 Jun 25 05:22:30 PM PDT 24 Jun 25 05:22:37 PM PDT 24 1466190702 ps
T873 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.797362302 Jun 25 05:22:52 PM PDT 24 Jun 25 05:22:55 PM PDT 24 69232271 ps
T185 /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.3140328927 Jun 25 05:22:50 PM PDT 24 Jun 25 05:22:55 PM PDT 24 40310258 ps
T874 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.4006833038 Jun 25 05:22:30 PM PDT 24 Jun 25 05:22:35 PM PDT 24 43184969 ps
T875 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.4059671464 Jun 25 05:22:48 PM PDT 24 Jun 25 05:22:53 PM PDT 24 135792563 ps
T186 /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.2228338821 Jun 25 05:22:52 PM PDT 24 Jun 25 05:22:55 PM PDT 24 61351693 ps
T213 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.733768362 Jun 25 05:22:34 PM PDT 24 Jun 25 05:22:39 PM PDT 24 42786839 ps
T148 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.1826788536 Jun 25 05:22:32 PM PDT 24 Jun 25 05:22:39 PM PDT 24 556351647 ps
T876 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.1574695625 Jun 25 05:22:30 PM PDT 24 Jun 25 05:22:34 PM PDT 24 13784508 ps
T224 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.1954112406 Jun 25 05:22:31 PM PDT 24 Jun 25 05:22:36 PM PDT 24 38223382 ps
T149 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.1234647284 Jun 25 05:22:55 PM PDT 24 Jun 25 05:22:58 PM PDT 24 21937384 ps
T877 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.3851177501 Jun 25 05:22:48 PM PDT 24 Jun 25 05:22:51 PM PDT 24 67759459 ps
T151 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.1238236247 Jun 25 05:22:38 PM PDT 24 Jun 25 05:22:45 PM PDT 24 104717256 ps
T152 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.1025307444 Jun 25 05:22:49 PM PDT 24 Jun 25 05:22:55 PM PDT 24 94653769 ps
T878 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.920474544 Jun 25 05:22:46 PM PDT 24 Jun 25 05:22:48 PM PDT 24 137804141 ps
T172 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.1810601119 Jun 25 05:22:31 PM PDT 24 Jun 25 05:22:37 PM PDT 24 193110789 ps
T157 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.3803966252 Jun 25 05:22:55 PM PDT 24 Jun 25 05:22:59 PM PDT 24 48337856 ps
T879 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.958664837 Jun 25 05:22:37 PM PDT 24 Jun 25 05:23:34 PM PDT 24 14682888918 ps
T880 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.705348881 Jun 25 05:22:47 PM PDT 24 Jun 25 05:22:51 PM PDT 24 44834012 ps
T881 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.447700269 Jun 25 05:22:31 PM PDT 24 Jun 25 05:22:59 PM PDT 24 4378019767 ps
T173 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3119439454 Jun 25 05:22:34 PM PDT 24 Jun 25 05:22:41 PM PDT 24 290435569 ps
T225 /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.2034945877 Jun 25 05:22:36 PM PDT 24 Jun 25 05:22:40 PM PDT 24 155909803 ps
T882 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.2644157948 Jun 25 05:22:47 PM PDT 24 Jun 25 05:22:50 PM PDT 24 187905600 ps
T160 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.3005010656 Jun 25 05:22:55 PM PDT 24 Jun 25 05:22:58 PM PDT 24 167316640 ps
T214 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.2077953161 Jun 25 05:22:47 PM PDT 24 Jun 25 05:22:51 PM PDT 24 47921045 ps
T164 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.431620005 Jun 25 05:22:50 PM PDT 24 Jun 25 05:22:56 PM PDT 24 469285489 ps
T158 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.1466727829 Jun 25 05:22:31 PM PDT 24 Jun 25 05:22:38 PM PDT 24 155977014 ps
T883 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.692883501 Jun 25 05:22:29 PM PDT 24 Jun 25 05:22:33 PM PDT 24 278849889 ps
T226 /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.214272793 Jun 25 05:22:32 PM PDT 24 Jun 25 05:22:37 PM PDT 24 97485599 ps
T884 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.2793899725 Jun 25 05:22:29 PM PDT 24 Jun 25 05:22:35 PM PDT 24 774232706 ps
T885 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.1897061673 Jun 25 05:22:50 PM PDT 24 Jun 25 05:22:54 PM PDT 24 26350939 ps
T886 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.1252718915 Jun 25 05:22:45 PM PDT 24 Jun 25 05:22:48 PM PDT 24 354963273 ps
T887 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.3805312165 Jun 25 05:22:31 PM PDT 24 Jun 25 05:22:37 PM PDT 24 54387425 ps
T888 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.3277686073 Jun 25 05:22:45 PM PDT 24 Jun 25 05:23:01 PM PDT 24 701983886 ps
T889 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.2537661986 Jun 25 05:22:46 PM PDT 24 Jun 25 05:22:49 PM PDT 24 220019431 ps
T227 /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.788620969 Jun 25 05:22:56 PM PDT 24 Jun 25 05:22:58 PM PDT 24 56096490 ps
T890 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.4010627505 Jun 25 05:22:46 PM PDT 24 Jun 25 05:22:55 PM PDT 24 1248891401 ps
T891 /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.1399953741 Jun 25 05:22:49 PM PDT 24 Jun 25 05:22:53 PM PDT 24 181112710 ps
T892 /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.3489883873 Jun 25 05:22:56 PM PDT 24 Jun 25 05:22:58 PM PDT 24 21410643 ps
T893 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.3116926761 Jun 25 05:22:45 PM PDT 24 Jun 25 05:22:56 PM PDT 24 1474020382 ps
T894 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.3738540721 Jun 25 05:22:29 PM PDT 24 Jun 25 05:22:37 PM PDT 24 373221455 ps
T895 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.2320600471 Jun 25 05:22:48 PM PDT 24 Jun 25 05:22:52 PM PDT 24 87066370 ps
T896 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.3591465987 Jun 25 05:22:46 PM PDT 24 Jun 25 05:22:49 PM PDT 24 13308345 ps
T897 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.678819857 Jun 25 05:22:31 PM PDT 24 Jun 25 05:22:37 PM PDT 24 687379838 ps
T898 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.3890050615 Jun 25 05:22:55 PM PDT 24 Jun 25 05:22:57 PM PDT 24 42558254 ps
T899 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.1764153754 Jun 25 05:22:47 PM PDT 24 Jun 25 05:23:00 PM PDT 24 1891656178 ps
T900 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.1956624288 Jun 25 05:22:48 PM PDT 24 Jun 25 05:22:51 PM PDT 24 48574941 ps
T901 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.2605477198 Jun 25 05:22:32 PM PDT 24 Jun 25 05:22:44 PM PDT 24 861049794 ps
T902 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.1988839062 Jun 25 05:22:31 PM PDT 24 Jun 25 05:22:36 PM PDT 24 20003917 ps
T903 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.2083243101 Jun 25 05:22:32 PM PDT 24 Jun 25 05:22:38 PM PDT 24 40506153 ps
T904 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.3132998165 Jun 25 05:22:47 PM PDT 24 Jun 25 05:23:02 PM PDT 24 2504308812 ps
T905 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.958903076 Jun 25 05:22:56 PM PDT 24 Jun 25 05:22:59 PM PDT 24 33248837 ps
T906 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2809129771 Jun 25 05:22:41 PM PDT 24 Jun 25 05:22:49 PM PDT 24 3283461961 ps
T907 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.4156747591 Jun 25 05:22:36 PM PDT 24 Jun 25 05:22:44 PM PDT 24 265707711 ps
T908 /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.1524047931 Jun 25 05:22:49 PM PDT 24 Jun 25 05:22:54 PM PDT 24 50910210 ps
T909 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.1313750042 Jun 25 05:22:29 PM PDT 24 Jun 25 05:22:44 PM PDT 24 4028574715 ps
T215 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.1032461416 Jun 25 05:22:28 PM PDT 24 Jun 25 05:22:32 PM PDT 24 18008080 ps
T910 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1393751905 Jun 25 05:22:38 PM PDT 24 Jun 25 05:22:44 PM PDT 24 620236394 ps
T911 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.4145397037 Jun 25 05:22:56 PM PDT 24 Jun 25 05:22:59 PM PDT 24 287608261 ps
T912 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.9438639 Jun 25 05:22:31 PM PDT 24 Jun 25 05:22:36 PM PDT 24 102600826 ps
T913 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.2718111962 Jun 25 05:22:32 PM PDT 24 Jun 25 05:22:37 PM PDT 24 47695041 ps
T914 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.2273426470 Jun 25 05:22:38 PM PDT 24 Jun 25 05:22:42 PM PDT 24 179956493 ps
T915 /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.967227573 Jun 25 05:22:57 PM PDT 24 Jun 25 05:22:59 PM PDT 24 30797171 ps
T916 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.3921738832 Jun 25 05:22:28 PM PDT 24 Jun 25 05:22:31 PM PDT 24 101233652 ps
T917 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.720724320 Jun 25 05:22:46 PM PDT 24 Jun 25 05:23:17 PM PDT 24 1250827429 ps
T216 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.1438186264 Jun 25 05:22:37 PM PDT 24 Jun 25 05:22:41 PM PDT 24 66705490 ps
T918 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.3202990503 Jun 25 05:22:31 PM PDT 24 Jun 25 05:22:36 PM PDT 24 31417045 ps
T919 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.1957292849 Jun 25 05:22:37 PM PDT 24 Jun 25 05:23:01 PM PDT 24 11454087115 ps
T920 /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.659877074 Jun 25 05:22:38 PM PDT 24 Jun 25 05:22:42 PM PDT 24 17143627 ps
T921 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.1518623898 Jun 25 05:22:47 PM PDT 24 Jun 25 05:22:52 PM PDT 24 1066830094 ps
T922 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.4290034162 Jun 25 05:22:47 PM PDT 24 Jun 25 05:22:52 PM PDT 24 516827159 ps
T167 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.3821268576 Jun 25 05:22:31 PM PDT 24 Jun 25 05:22:38 PM PDT 24 71929454 ps
T923 /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.159108374 Jun 25 05:22:49 PM PDT 24 Jun 25 05:22:53 PM PDT 24 25742856 ps
T159 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.1236603232 Jun 25 05:22:34 PM PDT 24 Jun 25 05:22:40 PM PDT 24 217154110 ps
T924 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.2722714080 Jun 25 05:22:45 PM PDT 24 Jun 25 05:22:50 PM PDT 24 50479326 ps
T925 /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.2852222644 Jun 25 05:22:47 PM PDT 24 Jun 25 05:22:50 PM PDT 24 84841874 ps
T926 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.768212793 Jun 25 05:22:45 PM PDT 24 Jun 25 05:22:47 PM PDT 24 101119976 ps
T927 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.353740052 Jun 25 05:22:29 PM PDT 24 Jun 25 05:22:35 PM PDT 24 333375954 ps
T928 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.2461568084 Jun 25 05:22:50 PM PDT 24 Jun 25 05:22:54 PM PDT 24 24637738 ps
T929 /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.1802830561 Jun 25 05:22:39 PM PDT 24 Jun 25 05:22:42 PM PDT 24 19201589 ps
T930 /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.2979806404 Jun 25 05:22:55 PM PDT 24 Jun 25 05:22:57 PM PDT 24 29041284 ps
T931 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.652048199 Jun 25 05:22:48 PM PDT 24 Jun 25 05:22:51 PM PDT 24 31795779 ps
T932 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.2786255614 Jun 25 05:22:29 PM PDT 24 Jun 25 05:22:32 PM PDT 24 23708267 ps
T933 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.2585969529 Jun 25 05:22:28 PM PDT 24 Jun 25 05:22:31 PM PDT 24 81932982 ps
T934 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.2009129009 Jun 25 05:22:32 PM PDT 24 Jun 25 05:22:37 PM PDT 24 17183340 ps
T935 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.2766416406 Jun 25 05:22:37 PM PDT 24 Jun 25 05:22:42 PM PDT 24 66545040 ps
T936 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.1758439834 Jun 25 05:22:30 PM PDT 24 Jun 25 05:22:39 PM PDT 24 376390108 ps
T937 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.1275106425 Jun 25 05:22:45 PM PDT 24 Jun 25 05:22:51 PM PDT 24 214289208 ps
T938 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.3271772036 Jun 25 05:22:38 PM PDT 24 Jun 25 05:22:42 PM PDT 24 80592056 ps
T939 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.600649266 Jun 25 05:22:56 PM PDT 24 Jun 25 05:22:58 PM PDT 24 31897065 ps
T940 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.2882510676 Jun 25 05:22:41 PM PDT 24 Jun 25 05:22:44 PM PDT 24 44077233 ps
T170 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.1445324367 Jun 25 05:22:30 PM PDT 24 Jun 25 05:22:35 PM PDT 24 96962365 ps
T941 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.2576814270 Jun 25 05:22:44 PM PDT 24 Jun 25 05:22:46 PM PDT 24 19450034 ps
T942 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.3973459647 Jun 25 05:22:56 PM PDT 24 Jun 25 05:22:58 PM PDT 24 21509642 ps
T943 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2747431142 Jun 25 05:22:28 PM PDT 24 Jun 25 05:22:33 PM PDT 24 441865402 ps
T944 /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.135497308 Jun 25 05:22:50 PM PDT 24 Jun 25 05:22:54 PM PDT 24 84260654 ps
T945 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.3501715053 Jun 25 05:22:29 PM PDT 24 Jun 25 05:22:34 PM PDT 24 49803812 ps
T946 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.4158573647 Jun 25 05:22:52 PM PDT 24 Jun 25 05:22:55 PM PDT 24 37699024 ps
T947 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.1416058069 Jun 25 05:22:56 PM PDT 24 Jun 25 05:23:00 PM PDT 24 71262087 ps
T948 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.239834882 Jun 25 05:22:38 PM PDT 24 Jun 25 05:22:42 PM PDT 24 34359691 ps
T217 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.2105491447 Jun 25 05:22:56 PM PDT 24 Jun 25 05:22:58 PM PDT 24 16541270 ps
T218 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.365566158 Jun 25 05:22:40 PM PDT 24 Jun 25 05:22:43 PM PDT 24 27467047 ps
T949 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.2864390172 Jun 25 05:22:37 PM PDT 24 Jun 25 05:22:42 PM PDT 24 52920063 ps
T950 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.731980870 Jun 25 05:22:29 PM PDT 24 Jun 25 05:22:34 PM PDT 24 328916595 ps
T951 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.3721388991 Jun 25 05:22:52 PM PDT 24 Jun 25 05:22:54 PM PDT 24 12040432 ps
T952 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.2247712535 Jun 25 05:22:38 PM PDT 24 Jun 25 05:22:42 PM PDT 24 226299313 ps
T166 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.1160048399 Jun 25 05:22:56 PM PDT 24 Jun 25 05:23:00 PM PDT 24 64318171 ps
T953 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.11582859 Jun 25 05:22:49 PM PDT 24 Jun 25 05:22:52 PM PDT 24 89859249 ps
T219 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.2711605169 Jun 25 05:22:39 PM PDT 24 Jun 25 05:22:42 PM PDT 24 40665400 ps
T954 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.462855484 Jun 25 05:22:49 PM PDT 24 Jun 25 05:22:54 PM PDT 24 55994121 ps
T168 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.1570350630 Jun 25 05:22:45 PM PDT 24 Jun 25 05:22:48 PM PDT 24 385507338 ps
T955 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.4098167912 Jun 25 05:22:28 PM PDT 24 Jun 25 05:22:32 PM PDT 24 585162464 ps
T956 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.1799409903 Jun 25 05:22:32 PM PDT 24 Jun 25 05:22:39 PM PDT 24 303951560 ps
T957 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.584377106 Jun 25 05:22:30 PM PDT 24 Jun 25 05:22:34 PM PDT 24 250755917 ps
T958 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.1754611658 Jun 25 05:23:00 PM PDT 24 Jun 25 05:23:01 PM PDT 24 49947821 ps
T162 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.2170075679 Jun 25 05:22:46 PM PDT 24 Jun 25 05:22:51 PM PDT 24 77466054 ps
T959 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.7748768 Jun 25 05:22:41 PM PDT 24 Jun 25 05:22:44 PM PDT 24 2336804015 ps
T960 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.1761343737 Jun 25 05:22:48 PM PDT 24 Jun 25 05:22:51 PM PDT 24 123116867 ps
T961 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.3716630756 Jun 25 05:22:30 PM PDT 24 Jun 25 05:22:35 PM PDT 24 93438106 ps
T962 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.1214386966 Jun 25 05:22:38 PM PDT 24 Jun 25 05:22:43 PM PDT 24 399792826 ps
T963 /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.2328066256 Jun 25 05:22:32 PM PDT 24 Jun 25 05:22:37 PM PDT 24 44025193 ps
T169 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.1534028444 Jun 25 05:22:52 PM PDT 24 Jun 25 05:22:56 PM PDT 24 85776313 ps
T161 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.2726683105 Jun 25 05:22:47 PM PDT 24 Jun 25 05:22:51 PM PDT 24 445730076 ps
T964 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.3997881215 Jun 25 05:22:40 PM PDT 24 Jun 25 05:22:43 PM PDT 24 19273030 ps
T965 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.2933608670 Jun 25 05:22:29 PM PDT 24 Jun 25 05:22:32 PM PDT 24 60322811 ps
T966 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.631945531 Jun 25 05:22:48 PM PDT 24 Jun 25 05:22:51 PM PDT 24 36549600 ps
T163 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.1538613789 Jun 25 05:22:50 PM PDT 24 Jun 25 05:22:55 PM PDT 24 104826967 ps
T967 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.12521215 Jun 25 05:23:00 PM PDT 24 Jun 25 05:23:03 PM PDT 24 121158085 ps
T968 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.804060546 Jun 25 05:22:32 PM PDT 24 Jun 25 05:23:02 PM PDT 24 1101632232 ps
T156 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.1869601157 Jun 25 05:22:47 PM PDT 24 Jun 25 05:22:54 PM PDT 24 290941195 ps
T969 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.4135680286 Jun 25 05:22:50 PM PDT 24 Jun 25 05:22:58 PM PDT 24 121394204 ps
T970 /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.1989982694 Jun 25 05:22:36 PM PDT 24 Jun 25 05:22:40 PM PDT 24 30496786 ps
T971 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.4215292119 Jun 25 05:22:40 PM PDT 24 Jun 25 05:22:44 PM PDT 24 34188129 ps
T972 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.1195937218 Jun 25 05:22:31 PM PDT 24 Jun 25 05:22:36 PM PDT 24 72148364 ps
T973 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.1171019697 Jun 25 05:22:39 PM PDT 24 Jun 25 05:22:43 PM PDT 24 17522090 ps
T974 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2495105414 Jun 25 05:22:38 PM PDT 24 Jun 25 05:22:44 PM PDT 24 110405131 ps
T975 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.4277208747 Jun 25 05:22:55 PM PDT 24 Jun 25 05:22:57 PM PDT 24 24513806 ps
T976 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.2605484048 Jun 25 05:23:00 PM PDT 24 Jun 25 05:23:02 PM PDT 24 12841385 ps
T977 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.357288905 Jun 25 05:22:52 PM PDT 24 Jun 25 05:22:55 PM PDT 24 18903905 ps
T165 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.480323642 Jun 25 05:22:49 PM PDT 24 Jun 25 05:22:55 PM PDT 24 203192319 ps
T978 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.593068227 Jun 25 05:22:48 PM PDT 24 Jun 25 05:22:51 PM PDT 24 40920945 ps
T979 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.225994745 Jun 25 05:22:49 PM PDT 24 Jun 25 05:22:55 PM PDT 24 132175181 ps
T980 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.2522627789 Jun 25 05:22:55 PM PDT 24 Jun 25 05:22:59 PM PDT 24 140441236 ps
T981 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4276440880 Jun 25 05:22:33 PM PDT 24 Jun 25 05:22:38 PM PDT 24 60906916 ps
T982 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.1872261067 Jun 25 05:22:37 PM PDT 24 Jun 25 05:22:48 PM PDT 24 8463516393 ps
T983 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.2225408422 Jun 25 05:22:37 PM PDT 24 Jun 25 05:22:41 PM PDT 24 54159822 ps
T984 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.4161513197 Jun 25 05:22:32 PM PDT 24 Jun 25 05:22:38 PM PDT 24 35005318 ps
T985 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.2573505649 Jun 25 05:22:39 PM PDT 24 Jun 25 05:22:45 PM PDT 24 1066797942 ps
T986 /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.3017753410 Jun 25 05:22:31 PM PDT 24 Jun 25 05:22:36 PM PDT 24 59270589 ps
T987 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.2843992180 Jun 25 05:22:39 PM PDT 24 Jun 25 05:22:56 PM PDT 24 1242665794 ps
T988 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.3335698504 Jun 25 05:22:47 PM PDT 24 Jun 25 05:22:50 PM PDT 24 29548356 ps
T989 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4074616796 Jun 25 05:22:46 PM PDT 24 Jun 25 05:22:51 PM PDT 24 2281073021 ps
T990 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.2566958110 Jun 25 05:23:06 PM PDT 24 Jun 25 05:23:08 PM PDT 24 35682802 ps
T991 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.4084950561 Jun 25 05:22:46 PM PDT 24 Jun 25 05:22:49 PM PDT 24 161312842 ps
T220 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.3589544076 Jun 25 05:22:31 PM PDT 24 Jun 25 05:22:35 PM PDT 24 41252428 ps
T992 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.1168970675 Jun 25 05:22:38 PM PDT 24 Jun 25 05:22:42 PM PDT 24 28784256 ps
T993 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.759254690 Jun 25 05:22:49 PM PDT 24 Jun 25 05:22:53 PM PDT 24 75152556 ps
T994 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.941261548 Jun 25 05:22:48 PM PDT 24 Jun 25 05:22:52 PM PDT 24 213368896 ps
T995 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.1007723675 Jun 25 05:22:52 PM PDT 24 Jun 25 05:22:55 PM PDT 24 75978191 ps
T996 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.2828896268 Jun 25 05:22:37 PM PDT 24 Jun 25 05:22:41 PM PDT 24 27323660 ps
T997 /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.3513671258 Jun 25 05:22:50 PM PDT 24 Jun 25 05:22:55 PM PDT 24 65849109 ps
T998 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.2972460184 Jun 25 05:22:27 PM PDT 24 Jun 25 05:22:30 PM PDT 24 15627358 ps
T221 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.2515881029 Jun 25 05:22:52 PM PDT 24 Jun 25 05:22:55 PM PDT 24 24508552 ps
T999 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.859363391 Jun 25 05:22:39 PM PDT 24 Jun 25 05:22:44 PM PDT 24 281909788 ps
T1000 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.3653665016 Jun 25 05:22:30 PM PDT 24 Jun 25 05:22:35 PM PDT 24 29366233 ps
T155 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.3034767520 Jun 25 05:22:52 PM PDT 24 Jun 25 05:22:57 PM PDT 24 258962357 ps

Test location /workspace/coverage/default/19.lc_ctrl_state_post_trans.2205879629
Short name T10
Test name
Test status
Simulation time 243439144 ps
CPU time 7.21 seconds
Started Jun 25 06:22:22 PM PDT 24
Finished Jun 25 06:22:30 PM PDT 24
Peak memory 243392 kb
Host smart-286f5d62-e249-48c7-b7e3-15b47699d500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205879629 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_post_trans.2205879629
Directory /workspace/19.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/28.lc_ctrl_stress_all_with_rand_reset.662279845
Short name T4
Test name
Test status
Simulation time 35838191437 ps
CPU time 428.79 seconds
Started Jun 25 06:23:11 PM PDT 24
Finished Jun 25 06:30:22 PM PDT 24
Peak memory 331764 kb
Host smart-b2312083-e8f4-4414-bbc0-07ee9e824fa0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=662279845 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_stress_all_with_rand_reset.662279845
Directory /workspace/28.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.lc_ctrl_security_escalation.634442681
Short name T57
Test name
Test status
Simulation time 1024824361 ps
CPU time 13.34 seconds
Started Jun 25 06:23:18 PM PDT 24
Finished Jun 25 06:23:34 PM PDT 24
Peak memory 218692 kb
Host smart-ab3b2131-535f-4bee-a63f-89669bfdc890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634442681 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_security_escalation.634442681
Directory /workspace/29.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_mux.1376078881
Short name T16
Test name
Test status
Simulation time 2167575771 ps
CPU time 8.77 seconds
Started Jun 25 06:21:07 PM PDT 24
Finished Jun 25 06:21:17 PM PDT 24
Peak memory 218656 kb
Host smart-1b668d03-af3b-41b3-b465-6f3115c15452
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376078881 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_mux.
1376078881
Directory /workspace/10.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_mubi.193875126
Short name T50
Test name
Test status
Simulation time 800647133 ps
CPU time 12.94 seconds
Started Jun 25 06:21:43 PM PDT 24
Finished Jun 25 06:21:56 PM PDT 24
Peak memory 226420 kb
Host smart-c580c72d-64e8-4670-9cd5-f76bb12064cf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193875126 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_mubi.193875126
Directory /workspace/14.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/44.lc_ctrl_volatile_unlock_smoke.1902394199
Short name T11
Test name
Test status
Simulation time 13632730 ps
CPU time 0.82 seconds
Started Jun 25 06:24:33 PM PDT 24
Finished Jun 25 06:25:01 PM PDT 24
Peak memory 209212 kb
Host smart-0210aa58-66e3-4d41-8c1d-d1c1726b7d0d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902394199 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_c
trl_volatile_unlock_smoke.1902394199
Directory /workspace/44.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3151447359
Short name T145
Test name
Test status
Simulation time 817830524 ps
CPU time 2.39 seconds
Started Jun 25 05:22:48 PM PDT 24
Finished Jun 25 05:22:53 PM PDT 24
Peak memory 218632 kb
Host smart-43db6232-8eab-425e-b6d4-ad2584430479
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315144
7359 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3151447359
Directory /workspace/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.2985304231
Short name T144
Test name
Test status
Simulation time 152718413 ps
CPU time 2.65 seconds
Started Jun 25 05:22:56 PM PDT 24
Finished Jun 25 05:22:59 PM PDT 24
Peak memory 221752 kb
Host smart-8f65c40d-1680-4f6b-9a35-fd647014ddbc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985304231 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_intg
_err.2985304231
Directory /workspace/19.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/12.lc_ctrl_security_escalation.3960930089
Short name T61
Test name
Test status
Simulation time 726045931 ps
CPU time 9.02 seconds
Started Jun 25 06:21:22 PM PDT 24
Finished Jun 25 06:21:32 PM PDT 24
Peak memory 226424 kb
Host smart-b6bb2aa9-a4b0-45e4-806f-c4f808d19dbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960930089 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_security_escalation.3960930089
Directory /workspace/12.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_access.3389215543
Short name T6
Test name
Test status
Simulation time 261806889 ps
CPU time 5.83 seconds
Started Jun 25 06:21:45 PM PDT 24
Finished Jun 25 06:21:52 PM PDT 24
Peak memory 217644 kb
Host smart-e17769c0-6626-41af-abf2-bbba24bfaeba
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389215543 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_access.3389215543
Directory /workspace/15.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/4.lc_ctrl_alert_test.3658558894
Short name T14
Test name
Test status
Simulation time 29541336 ps
CPU time 1.03 seconds
Started Jun 25 06:20:04 PM PDT 24
Finished Jun 25 06:20:06 PM PDT 24
Peak memory 209316 kb
Host smart-3e379ebe-e1a5-43cf-ad5e-6ff263dbef31
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658558894 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_alert_test.3658558894
Directory /workspace/4.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_cm.853700927
Short name T101
Test name
Test status
Simulation time 661833125 ps
CPU time 28.86 seconds
Started Jun 25 06:18:35 PM PDT 24
Finished Jun 25 06:19:05 PM PDT 24
Peak memory 284360 kb
Host smart-ba8e7eb0-2c5a-43cf-94e5-131949e9a32f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853700927 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_cm.853700927
Directory /workspace/0.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/45.lc_ctrl_stress_all_with_rand_reset.2944169691
Short name T103
Test name
Test status
Simulation time 469785998122 ps
CPU time 525.68 seconds
Started Jun 25 06:24:40 PM PDT 24
Finished Jun 25 06:33:48 PM PDT 24
Peak memory 349764 kb
Host smart-db9f6c5e-b96f-4cd5-b071-e02a8fb1bf7b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2944169691 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_stress_all_with_rand_reset.2944169691
Directory /workspace/45.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.1032461416
Short name T215
Test name
Test status
Simulation time 18008080 ps
CPU time 1.44 seconds
Started Jun 25 05:22:28 PM PDT 24
Finished Jun 25 05:22:32 PM PDT 24
Peak memory 209108 kb
Host smart-2dcbfb43-3713-4bba-bd9c-cb9bc8b5893d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032461416 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_aliasin
g.1032461416
Directory /workspace/0.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.1826788536
Short name T148
Test name
Test status
Simulation time 556351647 ps
CPU time 3.43 seconds
Started Jun 25 05:22:32 PM PDT 24
Finished Jun 25 05:22:39 PM PDT 24
Peak memory 217312 kb
Host smart-8e20f838-97e2-4afe-9cb9-d87c2e58fc20
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826788536 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_errors.1826788536
Directory /workspace/0.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_errors.3767669984
Short name T19
Test name
Test status
Simulation time 90824887307 ps
CPU time 145.44 seconds
Started Jun 25 06:20:42 PM PDT 24
Finished Jun 25 06:23:09 PM PDT 24
Peak memory 221380 kb
Host smart-235ec3f3-808f-4c71-89a1-3330d78b3d25
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767669984 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_er
rors.3767669984
Directory /workspace/8.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.1236603232
Short name T159
Test name
Test status
Simulation time 217154110 ps
CPU time 1.98 seconds
Started Jun 25 05:22:34 PM PDT 24
Finished Jun 25 05:22:40 PM PDT 24
Peak memory 221564 kb
Host smart-0d6ac2bc-11de-4bf8-83d7-0702d8170fef
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236603232 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_intg_
err.1236603232
Directory /workspace/3.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/19.lc_ctrl_volatile_unlock_smoke.1568952746
Short name T66
Test name
Test status
Simulation time 22459157 ps
CPU time 1.08 seconds
Started Jun 25 06:22:22 PM PDT 24
Finished Jun 25 06:22:24 PM PDT 24
Peak memory 212284 kb
Host smart-b281eb2d-b505-4f49-bd1b-22f70b637aa8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568952746 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_c
trl_volatile_unlock_smoke.1568952746
Directory /workspace/19.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_errors.3788265959
Short name T38
Test name
Test status
Simulation time 441702940 ps
CPU time 18.99 seconds
Started Jun 25 06:21:40 PM PDT 24
Finished Jun 25 06:22:00 PM PDT 24
Peak memory 218636 kb
Host smart-d81a612a-66a9-4b6a-bc06-6a3e0190f985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788265959 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_errors.3788265959
Directory /workspace/14.lc_ctrl_errors/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all_with_rand_reset.1755158784
Short name T139
Test name
Test status
Simulation time 11602486945 ps
CPU time 403.37 seconds
Started Jun 25 06:23:42 PM PDT 24
Finished Jun 25 06:30:28 PM PDT 24
Peak memory 316508 kb
Host smart-25dc7054-f14a-441a-939d-806179b150a2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1755158784 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_stress_all_with_rand_reset.1755158784
Directory /workspace/34.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.3821268576
Short name T167
Test name
Test status
Simulation time 71929454 ps
CPU time 2.69 seconds
Started Jun 25 05:22:31 PM PDT 24
Finished Jun 25 05:22:38 PM PDT 24
Peak memory 222164 kb
Host smart-bf415614-72fa-4c92-9259-f182d7a745f0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821268576 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_intg_
err.3821268576
Directory /workspace/1.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.1025307444
Short name T152
Test name
Test status
Simulation time 94653769 ps
CPU time 3.3 seconds
Started Jun 25 05:22:49 PM PDT 24
Finished Jun 25 05:22:55 PM PDT 24
Peak memory 217192 kb
Host smart-8eb04c89-e910-487d-b75f-5a02d7f37bee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025307444 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_errors.1025307444
Directory /workspace/14.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.1810601119
Short name T172
Test name
Test status
Simulation time 193110789 ps
CPU time 2.83 seconds
Started Jun 25 05:22:31 PM PDT 24
Finished Jun 25 05:22:37 PM PDT 24
Peak memory 208768 kb
Host smart-87b2b3c9-daca-4f56-bbef-aebca03136e0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810601119 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_aliasing.1810601119
Directory /workspace/0.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.3034767520
Short name T155
Test name
Test status
Simulation time 258962357 ps
CPU time 2.9 seconds
Started Jun 25 05:22:52 PM PDT 24
Finished Jun 25 05:22:57 PM PDT 24
Peak memory 221648 kb
Host smart-f41c598c-490c-4c83-9f33-a1dfbb5321e2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034767520 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_intg
_err.3034767520
Directory /workspace/15.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.2951641374
Short name T223
Test name
Test status
Simulation time 14130696 ps
CPU time 1.13 seconds
Started Jun 25 05:22:30 PM PDT 24
Finished Jun 25 05:22:35 PM PDT 24
Peak memory 217216 kb
Host smart-89351022-0a45-4a76-a9a9-ccd1c08ed7c8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951641374 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.lc_ctrl_jtag_same_csr_outstanding.2951641374
Directory /workspace/0.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/default/21.lc_ctrl_stress_all_with_rand_reset.2442000848
Short name T116
Test name
Test status
Simulation time 7666524679 ps
CPU time 115.91 seconds
Started Jun 25 06:22:37 PM PDT 24
Finished Jun 25 06:24:34 PM PDT 24
Peak memory 268068 kb
Host smart-9b40b72a-61ab-4a4b-ae87-ea32936364be
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2442000848 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_stress_all_with_rand_reset.2442000848
Directory /workspace/21.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all_with_rand_reset.3221206877
Short name T106
Test name
Test status
Simulation time 63122115538 ps
CPU time 622.28 seconds
Started Jun 25 06:23:50 PM PDT 24
Finished Jun 25 06:34:16 PM PDT 24
Peak memory 513612 kb
Host smart-3dd97907-3763-412e-a2ba-0d3896d63bfe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3221206877 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_stress_all_with_rand_reset.3221206877
Directory /workspace/36.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.lc_ctrl_errors.4006626667
Short name T39
Test name
Test status
Simulation time 1998154537 ps
CPU time 16.32 seconds
Started Jun 25 06:24:22 PM PDT 24
Finished Jun 25 06:25:09 PM PDT 24
Peak memory 218560 kb
Host smart-8eb6544b-4f80-4137-b4ab-75d5824d98be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006626667 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_errors.4006626667
Directory /workspace/40.lc_ctrl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.1869601157
Short name T156
Test name
Test status
Simulation time 290941195 ps
CPU time 4.22 seconds
Started Jun 25 05:22:47 PM PDT 24
Finished Jun 25 05:22:54 PM PDT 24
Peak memory 217320 kb
Host smart-00fa8d4b-55e9-4165-984c-8fbd9267171c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869601157 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_intg
_err.1869601157
Directory /workspace/10.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.1538613789
Short name T163
Test name
Test status
Simulation time 104826967 ps
CPU time 2.69 seconds
Started Jun 25 05:22:50 PM PDT 24
Finished Jun 25 05:22:55 PM PDT 24
Peak memory 221920 kb
Host smart-f0d81395-f746-4cae-abaa-b4ba39716d24
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538613789 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_intg
_err.1538613789
Directory /workspace/12.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.3005010656
Short name T160
Test name
Test status
Simulation time 167316640 ps
CPU time 2.56 seconds
Started Jun 25 05:22:55 PM PDT 24
Finished Jun 25 05:22:58 PM PDT 24
Peak memory 217240 kb
Host smart-616078be-79bc-4b0a-84a0-85c5c3c002d0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005010656 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_intg
_err.3005010656
Directory /workspace/18.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.2726683105
Short name T161
Test name
Test status
Simulation time 445730076 ps
CPU time 1.95 seconds
Started Jun 25 05:22:47 PM PDT 24
Finished Jun 25 05:22:51 PM PDT 24
Peak memory 221580 kb
Host smart-f3f1b357-2145-4c67-b711-1ef56e202df9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726683105 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_intg_
err.2726683105
Directory /workspace/8.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_claim_transition_if.2434322422
Short name T201
Test name
Test status
Simulation time 38009954 ps
CPU time 0.87 seconds
Started Jun 25 06:18:28 PM PDT 24
Finished Jun 25 06:18:29 PM PDT 24
Peak memory 209204 kb
Host smart-2d620cc1-04ec-4791-b454-5d29aa4bc523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434322422 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_claim_transition_if.2434322422
Directory /workspace/0.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/6.lc_ctrl_claim_transition_if.3354106695
Short name T110
Test name
Test status
Simulation time 12622292 ps
CPU time 0.86 seconds
Started Jun 25 06:20:18 PM PDT 24
Finished Jun 25 06:20:20 PM PDT 24
Peak memory 209200 kb
Host smart-34b9363a-ea16-4438-9301-8e0e4fb46583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354106695 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_claim_transition_if.3354106695
Directory /workspace/6.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/8.lc_ctrl_claim_transition_if.1978894962
Short name T229
Test name
Test status
Simulation time 22252016 ps
CPU time 0.96 seconds
Started Jun 25 06:20:43 PM PDT 24
Finished Jun 25 06:20:45 PM PDT 24
Peak memory 209280 kb
Host smart-420e0983-0603-4a99-9747-f7e227efc7a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978894962 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_claim_transition_if.1978894962
Directory /workspace/8.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.1466727829
Short name T158
Test name
Test status
Simulation time 155977014 ps
CPU time 3.6 seconds
Started Jun 25 05:22:31 PM PDT 24
Finished Jun 25 05:22:38 PM PDT 24
Peak memory 217172 kb
Host smart-1789aa25-a0d4-4461-828e-c61796b2557f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466727829 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_errors.1466727829
Directory /workspace/1.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.431620005
Short name T164
Test name
Test status
Simulation time 469285489 ps
CPU time 3.52 seconds
Started Jun 25 05:22:50 PM PDT 24
Finished Jun 25 05:22:56 PM PDT 24
Peak memory 221752 kb
Host smart-c3e6cf1b-fb1f-4922-bb45-3fbba9b5afd9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431620005 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_intg_
err.431620005
Directory /workspace/11.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.1160048399
Short name T166
Test name
Test status
Simulation time 64318171 ps
CPU time 2.66 seconds
Started Jun 25 05:22:56 PM PDT 24
Finished Jun 25 05:23:00 PM PDT 24
Peak memory 217256 kb
Host smart-baaedcc2-ac29-432c-b20a-12245e09b551
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160048399 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_intg
_err.1160048399
Directory /workspace/17.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.2897723545
Short name T142
Test name
Test status
Simulation time 284995543 ps
CPU time 2.04 seconds
Started Jun 25 05:22:27 PM PDT 24
Finished Jun 25 05:22:31 PM PDT 24
Peak memory 221104 kb
Host smart-c514ea14-b3c4-4179-99a8-6503cb7de2df
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897723545 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_intg_
err.2897723545
Directory /workspace/2.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.1952462313
Short name T143
Test name
Test status
Simulation time 273936559 ps
CPU time 2.79 seconds
Started Jun 25 05:22:37 PM PDT 24
Finished Jun 25 05:22:42 PM PDT 24
Peak memory 217240 kb
Host smart-4a98fb88-76a7-4e1a-b5fd-e79de51d4c54
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952462313 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_intg_
err.1952462313
Directory /workspace/5.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.2170075679
Short name T162
Test name
Test status
Simulation time 77466054 ps
CPU time 3.46 seconds
Started Jun 25 05:22:46 PM PDT 24
Finished Jun 25 05:22:51 PM PDT 24
Peak memory 221976 kb
Host smart-c04de2d8-f6c3-48ff-a344-921e3604ddee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170075679 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_intg_
err.2170075679
Directory /workspace/7.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all_with_rand_reset.2493559399
Short name T54
Test name
Test status
Simulation time 45404141108 ps
CPU time 903.69 seconds
Started Jun 25 06:22:21 PM PDT 24
Finished Jun 25 06:37:25 PM PDT 24
Peak memory 300664 kb
Host smart-e03f5ed6-0c4e-4df0-bdaf-739dab0180bf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2493559399 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_stress_all_with_rand_reset.2493559399
Directory /workspace/18.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_digest.3711613011
Short name T2
Test name
Test status
Simulation time 1284195201 ps
CPU time 9.63 seconds
Started Jun 25 06:23:01 PM PDT 24
Finished Jun 25 06:23:12 PM PDT 24
Peak memory 218584 kb
Host smart-cde78d83-d895-4b56-8b5d-c0f805b6c0af
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711613011 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_d
igest.3711613011
Directory /workspace/26.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_post_trans.155214051
Short name T30
Test name
Test status
Simulation time 66074061 ps
CPU time 6.86 seconds
Started Jun 25 06:22:17 PM PDT 24
Finished Jun 25 06:22:24 PM PDT 24
Peak memory 250740 kb
Host smart-8d0a749b-a52c-4dec-b3d5-af45881625fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=155214051 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_post_trans.155214051
Directory /workspace/18.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.2718111962
Short name T913
Test name
Test status
Simulation time 47695041 ps
CPU time 1.46 seconds
Started Jun 25 05:22:32 PM PDT 24
Finished Jun 25 05:22:37 PM PDT 24
Peak memory 216832 kb
Host smart-f69151a8-3d09-4163-9ce8-a47ed9ed2bcf
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718111962 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_bit_bas
h.2718111962
Directory /workspace/0.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.3653665016
Short name T1000
Test name
Test status
Simulation time 29366233 ps
CPU time 1.18 seconds
Started Jun 25 05:22:30 PM PDT 24
Finished Jun 25 05:22:35 PM PDT 24
Peak memory 209744 kb
Host smart-ee474f22-20df-4f41-ad2c-d2b72a3ebc60
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653665016 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_hw_rese
t.3653665016
Directory /workspace/0.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.584377106
Short name T957
Test name
Test status
Simulation time 250755917 ps
CPU time 1.5 seconds
Started Jun 25 05:22:30 PM PDT 24
Finished Jun 25 05:22:34 PM PDT 24
Peak memory 219384 kb
Host smart-9e1a177f-a5ff-425f-ad29-ff282bc7897a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584377106 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 0.lc_ctrl_csr_mem_rw_with_rand_reset.584377106
Directory /workspace/0.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.2972460184
Short name T998
Test name
Test status
Simulation time 15627358 ps
CPU time 0.93 seconds
Started Jun 25 05:22:27 PM PDT 24
Finished Jun 25 05:22:30 PM PDT 24
Peak memory 209004 kb
Host smart-8645b7c6-bb78-4060-a20b-16108932d113
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972460184 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_rw.2972460184
Directory /workspace/0.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.4006833038
Short name T874
Test name
Test status
Simulation time 43184969 ps
CPU time 1.11 seconds
Started Jun 25 05:22:30 PM PDT 24
Finished Jun 25 05:22:35 PM PDT 24
Peak memory 208272 kb
Host smart-3ca9a9af-2f25-4556-add0-0b195aa0c293
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006833038 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.lc_ctrl_jtag_alert_test.4006833038
Directory /workspace/0.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.447700269
Short name T881
Test name
Test status
Simulation time 4378019767 ps
CPU time 24.74 seconds
Started Jun 25 05:22:31 PM PDT 24
Finished Jun 25 05:22:59 PM PDT 24
Peak memory 208968 kb
Host smart-5368f990-d3f5-4ab9-888c-a11e5b66ccf8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447700269 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 0.lc_ctrl_jtag_csr_bit_bash.447700269
Directory /workspace/0.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.692883501
Short name T883
Test name
Test status
Simulation time 278849889 ps
CPU time 1.97 seconds
Started Jun 25 05:22:29 PM PDT 24
Finished Jun 25 05:22:33 PM PDT 24
Peak memory 217168 kb
Host smart-862f0ffb-5016-4f4b-b063-0c8e32113112
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692883501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 0.lc_ctrl_jtag_csr_hw_reset.692883501
Directory /workspace/0.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2747431142
Short name T943
Test name
Test status
Simulation time 441865402 ps
CPU time 2.07 seconds
Started Jun 25 05:22:28 PM PDT 24
Finished Jun 25 05:22:33 PM PDT 24
Peak memory 217272 kb
Host smart-eb03244f-88a9-4024-a819-d5f3387b7f87
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274743
1142 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2747431142
Directory /workspace/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.2793899725
Short name T884
Test name
Test status
Simulation time 774232706 ps
CPU time 4.33 seconds
Started Jun 25 05:22:29 PM PDT 24
Finished Jun 25 05:22:35 PM PDT 24
Peak memory 216976 kb
Host smart-961d6fa3-70f6-47de-9231-2d4ed565d6e8
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793899725 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.lc_ctrl_jtag_csr_rw.2793899725
Directory /workspace/0.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.214272793
Short name T226
Test name
Test status
Simulation time 97485599 ps
CPU time 1.92 seconds
Started Jun 25 05:22:32 PM PDT 24
Finished Jun 25 05:22:37 PM PDT 24
Peak memory 211080 kb
Host smart-6bacf9d5-9355-4ee8-b416-ac34ca0ebf7d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214272793 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
same_csr_outstanding.214272793
Directory /workspace/0.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.1445324367
Short name T170
Test name
Test status
Simulation time 96962365 ps
CPU time 2.4 seconds
Started Jun 25 05:22:30 PM PDT 24
Finished Jun 25 05:22:35 PM PDT 24
Peak memory 221376 kb
Host smart-3bffd9db-6a2c-4537-be7e-e6ecd759b32c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445324367 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_intg_
err.1445324367
Directory /workspace/0.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.3589544076
Short name T220
Test name
Test status
Simulation time 41252428 ps
CPU time 1.37 seconds
Started Jun 25 05:22:31 PM PDT 24
Finished Jun 25 05:22:35 PM PDT 24
Peak memory 209160 kb
Host smart-9edcda3f-6bb3-4e41-a762-fd9a41e0d607
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589544076 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_aliasin
g.3589544076
Directory /workspace/1.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.1988839062
Short name T902
Test name
Test status
Simulation time 20003917 ps
CPU time 1.46 seconds
Started Jun 25 05:22:31 PM PDT 24
Finished Jun 25 05:22:36 PM PDT 24
Peak memory 208700 kb
Host smart-8161fa2e-1a33-4e79-adc1-fe6b661ad122
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988839062 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_bit_bas
h.1988839062
Directory /workspace/1.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.2786255614
Short name T932
Test name
Test status
Simulation time 23708267 ps
CPU time 0.98 seconds
Started Jun 25 05:22:29 PM PDT 24
Finished Jun 25 05:22:32 PM PDT 24
Peak memory 209460 kb
Host smart-61f60f58-94e6-4076-9fd7-188666c76ef6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786255614 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_hw_rese
t.2786255614
Directory /workspace/1.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.3202990503
Short name T918
Test name
Test status
Simulation time 31417045 ps
CPU time 1.93 seconds
Started Jun 25 05:22:31 PM PDT 24
Finished Jun 25 05:22:36 PM PDT 24
Peak memory 217328 kb
Host smart-7e9d0c53-d551-43c7-8a09-448cea457ab6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202990503 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 1.lc_ctrl_csr_mem_rw_with_rand_reset.3202990503
Directory /workspace/1.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.3501715053
Short name T945
Test name
Test status
Simulation time 49803812 ps
CPU time 1.05 seconds
Started Jun 25 05:22:29 PM PDT 24
Finished Jun 25 05:22:34 PM PDT 24
Peak memory 208804 kb
Host smart-838ffc5d-6d1f-4a31-8ad0-5cc952457588
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501715053 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_rw.3501715053
Directory /workspace/1.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.1983991720
Short name T175
Test name
Test status
Simulation time 81193923 ps
CPU time 1.22 seconds
Started Jun 25 05:22:29 PM PDT 24
Finished Jun 25 05:22:32 PM PDT 24
Peak memory 208264 kb
Host smart-cd299109-4f77-438e-96d5-ea8e35cbba86
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983991720 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.lc_ctrl_jtag_alert_test.1983991720
Directory /workspace/1.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.3738540721
Short name T894
Test name
Test status
Simulation time 373221455 ps
CPU time 5.1 seconds
Started Jun 25 05:22:29 PM PDT 24
Finished Jun 25 05:22:37 PM PDT 24
Peak memory 208712 kb
Host smart-9f12a2a7-4d01-4568-a8a7-75ed9bf67b2a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738540721 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_aliasing.3738540721
Directory /workspace/1.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.1313750042
Short name T909
Test name
Test status
Simulation time 4028574715 ps
CPU time 11.42 seconds
Started Jun 25 05:22:29 PM PDT 24
Finished Jun 25 05:22:44 PM PDT 24
Peak memory 208960 kb
Host smart-79b5714b-ecf1-4e9f-8b8a-d66e86b917b9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313750042 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_bit_bash.1313750042
Directory /workspace/1.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.353740052
Short name T927
Test name
Test status
Simulation time 333375954 ps
CPU time 2.09 seconds
Started Jun 25 05:22:29 PM PDT 24
Finished Jun 25 05:22:35 PM PDT 24
Peak memory 216652 kb
Host smart-4142ad46-3666-4e90-946a-a34eeab1a842
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353740052 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 1.lc_ctrl_jtag_csr_hw_reset.353740052
Directory /workspace/1.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4276440880
Short name T981
Test name
Test status
Simulation time 60906916 ps
CPU time 1.67 seconds
Started Jun 25 05:22:33 PM PDT 24
Finished Jun 25 05:22:38 PM PDT 24
Peak memory 217408 kb
Host smart-282e5e1f-c214-4e53-acc5-abe734cfcf40
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427644
0880 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4276440880
Directory /workspace/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.678819857
Short name T897
Test name
Test status
Simulation time 687379838 ps
CPU time 2.56 seconds
Started Jun 25 05:22:31 PM PDT 24
Finished Jun 25 05:22:37 PM PDT 24
Peak memory 208988 kb
Host smart-7362981f-f646-4fd5-97fb-3f9526c4cf9e
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678819857 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.lc_ctrl_jtag_csr_rw.678819857
Directory /workspace/1.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.2585969529
Short name T933
Test name
Test status
Simulation time 81932982 ps
CPU time 1.31 seconds
Started Jun 25 05:22:28 PM PDT 24
Finished Jun 25 05:22:31 PM PDT 24
Peak memory 217496 kb
Host smart-69117ccf-17a6-44d6-9391-14d047d964b9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585969529 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.lc_ctrl_jtag_same_csr_outstanding.2585969529
Directory /workspace/1.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.3017753410
Short name T986
Test name
Test status
Simulation time 59270589 ps
CPU time 1.17 seconds
Started Jun 25 05:22:31 PM PDT 24
Finished Jun 25 05:22:36 PM PDT 24
Peak memory 209128 kb
Host smart-3477b5fd-bebc-4f94-af97-0812dd73dddf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017753410 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl
_same_csr_outstanding.3017753410
Directory /workspace/1.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.3335698504
Short name T988
Test name
Test status
Simulation time 29548356 ps
CPU time 1.37 seconds
Started Jun 25 05:22:47 PM PDT 24
Finished Jun 25 05:22:50 PM PDT 24
Peak memory 217316 kb
Host smart-bb7a11c0-80f1-406c-9ad4-8f2efd94c346
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335698504 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 10.lc_ctrl_csr_mem_rw_with_rand_reset.3335698504
Directory /workspace/10.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.631945531
Short name T966
Test name
Test status
Simulation time 36549600 ps
CPU time 0.81 seconds
Started Jun 25 05:22:48 PM PDT 24
Finished Jun 25 05:22:51 PM PDT 24
Peak memory 208860 kb
Host smart-a9544e37-c18f-4adf-82e2-364c942f74fb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631945531 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_csr_rw.631945531
Directory /workspace/10.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.1524047931
Short name T908
Test name
Test status
Simulation time 50910210 ps
CPU time 1.14 seconds
Started Jun 25 05:22:49 PM PDT 24
Finished Jun 25 05:22:54 PM PDT 24
Peak memory 209056 kb
Host smart-ffdde16a-2fcf-468f-b202-b7e96d202733
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524047931 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctr
l_same_csr_outstanding.1524047931
Directory /workspace/10.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.2320600471
Short name T895
Test name
Test status
Simulation time 87066370 ps
CPU time 1.85 seconds
Started Jun 25 05:22:48 PM PDT 24
Finished Jun 25 05:22:52 PM PDT 24
Peak memory 217356 kb
Host smart-e8816e2e-9be1-4a24-b87f-bb9c6443bc5e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320600471 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_errors.2320600471
Directory /workspace/10.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.759254690
Short name T993
Test name
Test status
Simulation time 75152556 ps
CPU time 1.3 seconds
Started Jun 25 05:22:49 PM PDT 24
Finished Jun 25 05:22:53 PM PDT 24
Peak memory 218600 kb
Host smart-e3da2901-a44f-48b2-bad3-239bc4b2a24a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759254690 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 11.lc_ctrl_csr_mem_rw_with_rand_reset.759254690
Directory /workspace/11.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.3721388991
Short name T951
Test name
Test status
Simulation time 12040432 ps
CPU time 0.83 seconds
Started Jun 25 05:22:52 PM PDT 24
Finished Jun 25 05:22:54 PM PDT 24
Peak memory 208360 kb
Host smart-600bcc90-86fb-4e84-b44e-bb0df80c223c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721388991 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_csr_rw.3721388991
Directory /workspace/11.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.3140328927
Short name T185
Test name
Test status
Simulation time 40310258 ps
CPU time 1.89 seconds
Started Jun 25 05:22:50 PM PDT 24
Finished Jun 25 05:22:55 PM PDT 24
Peak memory 210628 kb
Host smart-0c1901cf-62a9-478d-88c6-b1449d925d7d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140328927 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctr
l_same_csr_outstanding.3140328927
Directory /workspace/11.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.4290034162
Short name T922
Test name
Test status
Simulation time 516827159 ps
CPU time 3.88 seconds
Started Jun 25 05:22:47 PM PDT 24
Finished Jun 25 05:22:52 PM PDT 24
Peak memory 217396 kb
Host smart-6b9682c1-22bd-4c3e-b79f-84140c7a0061
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290034162 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_errors.4290034162
Directory /workspace/11.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.357288905
Short name T977
Test name
Test status
Simulation time 18903905 ps
CPU time 1.13 seconds
Started Jun 25 05:22:52 PM PDT 24
Finished Jun 25 05:22:55 PM PDT 24
Peak memory 217412 kb
Host smart-bf1d2ad5-5f93-40a5-bcd2-ef95bc10c6b8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357288905 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 12.lc_ctrl_csr_mem_rw_with_rand_reset.357288905
Directory /workspace/12.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.797362302
Short name T873
Test name
Test status
Simulation time 69232271 ps
CPU time 0.9 seconds
Started Jun 25 05:22:52 PM PDT 24
Finished Jun 25 05:22:55 PM PDT 24
Peak memory 208832 kb
Host smart-f6884648-f6b4-4b9b-8650-ce6e365df126
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797362302 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_csr_rw.797362302
Directory /workspace/12.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.135497308
Short name T944
Test name
Test status
Simulation time 84260654 ps
CPU time 1.05 seconds
Started Jun 25 05:22:50 PM PDT 24
Finished Jun 25 05:22:54 PM PDT 24
Peak memory 209036 kb
Host smart-e9a72e11-3d71-4ba1-bdf3-45312ce7d803
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135497308 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl
_same_csr_outstanding.135497308
Directory /workspace/12.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.225994745
Short name T979
Test name
Test status
Simulation time 132175181 ps
CPU time 2.29 seconds
Started Jun 25 05:22:49 PM PDT 24
Finished Jun 25 05:22:55 PM PDT 24
Peak memory 217184 kb
Host smart-2d3572f0-6515-46cd-b8ff-e479001bfedd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225994745 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_errors.225994745
Directory /workspace/12.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.4158573647
Short name T946
Test name
Test status
Simulation time 37699024 ps
CPU time 1.4 seconds
Started Jun 25 05:22:52 PM PDT 24
Finished Jun 25 05:22:55 PM PDT 24
Peak memory 217472 kb
Host smart-30876099-5c61-4c66-b7a6-7bed77497df3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158573647 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 13.lc_ctrl_csr_mem_rw_with_rand_reset.4158573647
Directory /workspace/13.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.1007723675
Short name T995
Test name
Test status
Simulation time 75978191 ps
CPU time 0.93 seconds
Started Jun 25 05:22:52 PM PDT 24
Finished Jun 25 05:22:55 PM PDT 24
Peak memory 209036 kb
Host smart-45dd5be5-ad0c-4f10-aa01-c09327d2ca59
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007723675 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_csr_rw.1007723675
Directory /workspace/13.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.2228338821
Short name T186
Test name
Test status
Simulation time 61351693 ps
CPU time 1.32 seconds
Started Jun 25 05:22:52 PM PDT 24
Finished Jun 25 05:22:55 PM PDT 24
Peak memory 208960 kb
Host smart-b05cc20c-cc48-4ef6-8ac4-4ba1388cddc2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228338821 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctr
l_same_csr_outstanding.2228338821
Directory /workspace/13.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.4135680286
Short name T969
Test name
Test status
Simulation time 121394204 ps
CPU time 5.1 seconds
Started Jun 25 05:22:50 PM PDT 24
Finished Jun 25 05:22:58 PM PDT 24
Peak memory 217180 kb
Host smart-f9af20d0-2ec5-4b8f-8a21-36aa4637a0f0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135680286 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_errors.4135680286
Directory /workspace/13.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.1534028444
Short name T169
Test name
Test status
Simulation time 85776313 ps
CPU time 1.96 seconds
Started Jun 25 05:22:52 PM PDT 24
Finished Jun 25 05:22:56 PM PDT 24
Peak memory 221692 kb
Host smart-ad2cc387-e7a8-42e5-9d21-71218dc8cd5f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534028444 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_intg
_err.1534028444
Directory /workspace/13.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.2461568084
Short name T928
Test name
Test status
Simulation time 24637738 ps
CPU time 1.23 seconds
Started Jun 25 05:22:50 PM PDT 24
Finished Jun 25 05:22:54 PM PDT 24
Peak memory 217456 kb
Host smart-80f07312-4c61-44af-a7aa-194000de469c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461568084 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 14.lc_ctrl_csr_mem_rw_with_rand_reset.2461568084
Directory /workspace/14.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.2515881029
Short name T221
Test name
Test status
Simulation time 24508552 ps
CPU time 1.15 seconds
Started Jun 25 05:22:52 PM PDT 24
Finished Jun 25 05:22:55 PM PDT 24
Peak memory 208820 kb
Host smart-121910fd-8283-40ab-ac0a-104045ce9109
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515881029 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_csr_rw.2515881029
Directory /workspace/14.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.1399953741
Short name T891
Test name
Test status
Simulation time 181112710 ps
CPU time 1.44 seconds
Started Jun 25 05:22:49 PM PDT 24
Finished Jun 25 05:22:53 PM PDT 24
Peak memory 217232 kb
Host smart-3586f9c1-9f8a-467a-8e6c-805c15545666
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399953741 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctr
l_same_csr_outstanding.1399953741
Directory /workspace/14.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.480323642
Short name T165
Test name
Test status
Simulation time 203192319 ps
CPU time 2.67 seconds
Started Jun 25 05:22:49 PM PDT 24
Finished Jun 25 05:22:55 PM PDT 24
Peak memory 217232 kb
Host smart-aeb61f81-fecd-4760-a5b7-f7f4d92bec10
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480323642 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_intg_
err.480323642
Directory /workspace/14.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.3973459647
Short name T942
Test name
Test status
Simulation time 21509642 ps
CPU time 1.23 seconds
Started Jun 25 05:22:56 PM PDT 24
Finished Jun 25 05:22:58 PM PDT 24
Peak memory 218292 kb
Host smart-8110e413-2f43-4eb2-88bf-cbebbdd54938
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973459647 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 15.lc_ctrl_csr_mem_rw_with_rand_reset.3973459647
Directory /workspace/15.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.2105491447
Short name T217
Test name
Test status
Simulation time 16541270 ps
CPU time 0.97 seconds
Started Jun 25 05:22:56 PM PDT 24
Finished Jun 25 05:22:58 PM PDT 24
Peak memory 209000 kb
Host smart-8ef33b67-663a-4eae-8cc4-e0b97d99dce4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105491447 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_csr_rw.2105491447
Directory /workspace/15.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.967227573
Short name T915
Test name
Test status
Simulation time 30797171 ps
CPU time 1.13 seconds
Started Jun 25 05:22:57 PM PDT 24
Finished Jun 25 05:22:59 PM PDT 24
Peak memory 209028 kb
Host smart-d9caa16a-935a-4da1-878a-76e01a9bc9f0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967227573 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl
_same_csr_outstanding.967227573
Directory /workspace/15.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.462855484
Short name T954
Test name
Test status
Simulation time 55994121 ps
CPU time 2.03 seconds
Started Jun 25 05:22:49 PM PDT 24
Finished Jun 25 05:22:54 PM PDT 24
Peak memory 217208 kb
Host smart-f0c685e3-20ab-47eb-be80-8374b0f30ff3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462855484 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_errors.462855484
Directory /workspace/15.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.958903076
Short name T905
Test name
Test status
Simulation time 33248837 ps
CPU time 1.4 seconds
Started Jun 25 05:22:56 PM PDT 24
Finished Jun 25 05:22:59 PM PDT 24
Peak memory 218332 kb
Host smart-42b818f7-25db-4752-8bbe-ac0d1370df5c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958903076 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 16.lc_ctrl_csr_mem_rw_with_rand_reset.958903076
Directory /workspace/16.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.3890050615
Short name T898
Test name
Test status
Simulation time 42558254 ps
CPU time 0.92 seconds
Started Jun 25 05:22:55 PM PDT 24
Finished Jun 25 05:22:57 PM PDT 24
Peak memory 208944 kb
Host smart-5861c3ca-0664-4b1c-8f91-886639de49e9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890050615 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_csr_rw.3890050615
Directory /workspace/16.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.788620969
Short name T227
Test name
Test status
Simulation time 56096490 ps
CPU time 1 seconds
Started Jun 25 05:22:56 PM PDT 24
Finished Jun 25 05:22:58 PM PDT 24
Peak memory 209056 kb
Host smart-a5e3f035-f442-4d61-a979-67589cd1dc4d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788620969 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl
_same_csr_outstanding.788620969
Directory /workspace/16.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.1416058069
Short name T947
Test name
Test status
Simulation time 71262087 ps
CPU time 2.08 seconds
Started Jun 25 05:22:56 PM PDT 24
Finished Jun 25 05:23:00 PM PDT 24
Peak memory 217184 kb
Host smart-233f869f-147d-4aff-951e-36b9cef95adb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416058069 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_errors.1416058069
Directory /workspace/16.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.12521215
Short name T967
Test name
Test status
Simulation time 121158085 ps
CPU time 2 seconds
Started Jun 25 05:23:00 PM PDT 24
Finished Jun 25 05:23:03 PM PDT 24
Peak memory 221452 kb
Host smart-db43b668-9482-48c8-952a-c009396d42e6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12521215 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_intg_e
rr.12521215
Directory /workspace/16.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.1234647284
Short name T149
Test name
Test status
Simulation time 21937384 ps
CPU time 1.47 seconds
Started Jun 25 05:22:55 PM PDT 24
Finished Jun 25 05:22:58 PM PDT 24
Peak memory 219096 kb
Host smart-ba27475b-9955-4529-8436-3806331f6d79
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234647284 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 17.lc_ctrl_csr_mem_rw_with_rand_reset.1234647284
Directory /workspace/17.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.600649266
Short name T939
Test name
Test status
Simulation time 31897065 ps
CPU time 0.82 seconds
Started Jun 25 05:22:56 PM PDT 24
Finished Jun 25 05:22:58 PM PDT 24
Peak memory 208928 kb
Host smart-3ea62786-f32f-4671-a2c4-585c2b279bf0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600649266 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_csr_rw.600649266
Directory /workspace/17.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.3913258838
Short name T222
Test name
Test status
Simulation time 26431264 ps
CPU time 1.01 seconds
Started Jun 25 05:22:56 PM PDT 24
Finished Jun 25 05:22:58 PM PDT 24
Peak memory 209032 kb
Host smart-78589a83-ae19-4f25-9d99-15efb3fa0376
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913258838 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctr
l_same_csr_outstanding.3913258838
Directory /workspace/17.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.4277208747
Short name T975
Test name
Test status
Simulation time 24513806 ps
CPU time 1.48 seconds
Started Jun 25 05:22:55 PM PDT 24
Finished Jun 25 05:22:57 PM PDT 24
Peak memory 217156 kb
Host smart-43dea8f8-1c1a-460d-a332-8f0da0497d97
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277208747 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_errors.4277208747
Directory /workspace/17.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.4145397037
Short name T911
Test name
Test status
Simulation time 287608261 ps
CPU time 1.17 seconds
Started Jun 25 05:22:56 PM PDT 24
Finished Jun 25 05:22:59 PM PDT 24
Peak memory 217316 kb
Host smart-40736563-b069-40f4-84bf-ca94449a5e6d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145397037 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 18.lc_ctrl_csr_mem_rw_with_rand_reset.4145397037
Directory /workspace/18.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.2605484048
Short name T976
Test name
Test status
Simulation time 12841385 ps
CPU time 0.9 seconds
Started Jun 25 05:23:00 PM PDT 24
Finished Jun 25 05:23:02 PM PDT 24
Peak memory 208920 kb
Host smart-8e99e0cc-7a29-47eb-9410-65f3bffc1536
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605484048 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_csr_rw.2605484048
Directory /workspace/18.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.2979806404
Short name T930
Test name
Test status
Simulation time 29041284 ps
CPU time 1.07 seconds
Started Jun 25 05:22:55 PM PDT 24
Finished Jun 25 05:22:57 PM PDT 24
Peak memory 217160 kb
Host smart-751d334b-45a5-460b-abc4-fb030bc7a0f7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979806404 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctr
l_same_csr_outstanding.2979806404
Directory /workspace/18.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.3803966252
Short name T157
Test name
Test status
Simulation time 48337856 ps
CPU time 2.96 seconds
Started Jun 25 05:22:55 PM PDT 24
Finished Jun 25 05:22:59 PM PDT 24
Peak memory 217264 kb
Host smart-66e0989d-50f8-4765-ba98-76f9cd35d9b0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803966252 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_errors.3803966252
Directory /workspace/18.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.2566958110
Short name T990
Test name
Test status
Simulation time 35682802 ps
CPU time 1.44 seconds
Started Jun 25 05:23:06 PM PDT 24
Finished Jun 25 05:23:08 PM PDT 24
Peak memory 217420 kb
Host smart-9ba76bfc-0ba2-4d54-81b8-552fb9e32ee9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566958110 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 19.lc_ctrl_csr_mem_rw_with_rand_reset.2566958110
Directory /workspace/19.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.1754611658
Short name T958
Test name
Test status
Simulation time 49947821 ps
CPU time 0.83 seconds
Started Jun 25 05:23:00 PM PDT 24
Finished Jun 25 05:23:01 PM PDT 24
Peak memory 208908 kb
Host smart-ae328ab9-0c9d-4b88-91fa-b19140b8239a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754611658 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_csr_rw.1754611658
Directory /workspace/19.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.3489883873
Short name T892
Test name
Test status
Simulation time 21410643 ps
CPU time 1.54 seconds
Started Jun 25 05:22:56 PM PDT 24
Finished Jun 25 05:22:58 PM PDT 24
Peak memory 211216 kb
Host smart-52bc1bda-a67b-4b79-99aa-fc4429e5b937
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489883873 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctr
l_same_csr_outstanding.3489883873
Directory /workspace/19.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.2522627789
Short name T980
Test name
Test status
Simulation time 140441236 ps
CPU time 2.87 seconds
Started Jun 25 05:22:55 PM PDT 24
Finished Jun 25 05:22:59 PM PDT 24
Peak memory 217504 kb
Host smart-20a68540-d3fa-4731-84ee-78b3e901928d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522627789 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_errors.2522627789
Directory /workspace/19.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.733768362
Short name T213
Test name
Test status
Simulation time 42786839 ps
CPU time 0.96 seconds
Started Jun 25 05:22:34 PM PDT 24
Finished Jun 25 05:22:39 PM PDT 24
Peak memory 209072 kb
Host smart-c16a18ce-4b3f-4151-804a-50a384000d72
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733768362 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_aliasing
.733768362
Directory /workspace/2.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.2083243101
Short name T903
Test name
Test status
Simulation time 40506153 ps
CPU time 1.86 seconds
Started Jun 25 05:22:32 PM PDT 24
Finished Jun 25 05:22:38 PM PDT 24
Peak memory 208692 kb
Host smart-2bf14f6a-adbb-4a2e-9383-a209bc635d4a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083243101 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_bit_bas
h.2083243101
Directory /workspace/2.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.1574695625
Short name T876
Test name
Test status
Simulation time 13784508 ps
CPU time 1.09 seconds
Started Jun 25 05:22:30 PM PDT 24
Finished Jun 25 05:22:34 PM PDT 24
Peak memory 209620 kb
Host smart-ff5647c3-cb6a-4f4e-8af7-db670acbc205
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574695625 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_hw_rese
t.1574695625
Directory /workspace/2.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.731980870
Short name T950
Test name
Test status
Simulation time 328916595 ps
CPU time 1.2 seconds
Started Jun 25 05:22:29 PM PDT 24
Finished Jun 25 05:22:34 PM PDT 24
Peak memory 216648 kb
Host smart-04ee8973-9d6e-4249-aa8d-0eddcadcce32
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731980870 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 2.lc_ctrl_csr_mem_rw_with_rand_reset.731980870
Directory /workspace/2.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.9438639
Short name T912
Test name
Test status
Simulation time 102600826 ps
CPU time 1.06 seconds
Started Jun 25 05:22:31 PM PDT 24
Finished Jun 25 05:22:36 PM PDT 24
Peak memory 209028 kb
Host smart-fd3f14fe-050e-4b79-9937-b248ba721f1e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9438639 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_rw.9438639
Directory /workspace/2.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.3921738832
Short name T916
Test name
Test status
Simulation time 101233652 ps
CPU time 2 seconds
Started Jun 25 05:22:28 PM PDT 24
Finished Jun 25 05:22:31 PM PDT 24
Peak memory 208888 kb
Host smart-ea0f8f67-43ea-45f4-8265-b0b6696beb10
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921738832 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.lc_ctrl_jtag_alert_test.3921738832
Directory /workspace/2.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.1758439834
Short name T936
Test name
Test status
Simulation time 376390108 ps
CPU time 5.19 seconds
Started Jun 25 05:22:30 PM PDT 24
Finished Jun 25 05:22:39 PM PDT 24
Peak memory 208768 kb
Host smart-bd4eab59-7878-44c0-90e6-22095f27f88d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758439834 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_aliasing.1758439834
Directory /workspace/2.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.804060546
Short name T968
Test name
Test status
Simulation time 1101632232 ps
CPU time 26.27 seconds
Started Jun 25 05:22:32 PM PDT 24
Finished Jun 25 05:23:02 PM PDT 24
Peak memory 216856 kb
Host smart-e3af763a-2f18-4b72-8d51-9254b54ea27b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804060546 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 2.lc_ctrl_jtag_csr_bit_bash.804060546
Directory /workspace/2.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.2933608670
Short name T965
Test name
Test status
Simulation time 60322811 ps
CPU time 1.33 seconds
Started Jun 25 05:22:29 PM PDT 24
Finished Jun 25 05:22:32 PM PDT 24
Peak memory 217160 kb
Host smart-e0e30386-b47d-4a22-a1d5-e9e7e1cae83b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933608670 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_hw_reset.2933608670
Directory /workspace/2.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3119439454
Short name T173
Test name
Test status
Simulation time 290435569 ps
CPU time 2.88 seconds
Started Jun 25 05:22:34 PM PDT 24
Finished Jun 25 05:22:41 PM PDT 24
Peak memory 218452 kb
Host smart-07146464-f9ba-4448-bc98-0aeb787d3179
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311943
9454 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3119439454
Directory /workspace/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.3805312165
Short name T887
Test name
Test status
Simulation time 54387425 ps
CPU time 2.02 seconds
Started Jun 25 05:22:31 PM PDT 24
Finished Jun 25 05:22:37 PM PDT 24
Peak memory 208880 kb
Host smart-aa203e5f-dcb9-4f94-b952-58c5fb000e37
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805312165 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.lc_ctrl_jtag_csr_rw.3805312165
Directory /workspace/2.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.1195937218
Short name T972
Test name
Test status
Simulation time 72148364 ps
CPU time 1.87 seconds
Started Jun 25 05:22:31 PM PDT 24
Finished Jun 25 05:22:36 PM PDT 24
Peak memory 211188 kb
Host smart-50c33016-a5a0-4025-9fa8-ccf4b9651b05
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195937218 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.lc_ctrl_jtag_same_csr_outstanding.1195937218
Directory /workspace/2.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.2328066256
Short name T963
Test name
Test status
Simulation time 44025193 ps
CPU time 1.04 seconds
Started Jun 25 05:22:32 PM PDT 24
Finished Jun 25 05:22:37 PM PDT 24
Peak memory 208952 kb
Host smart-4097657c-d21d-4897-bc67-f33f9d9c13d7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328066256 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl
_same_csr_outstanding.2328066256
Directory /workspace/2.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.1799409903
Short name T956
Test name
Test status
Simulation time 303951560 ps
CPU time 3.26 seconds
Started Jun 25 05:22:32 PM PDT 24
Finished Jun 25 05:22:39 PM PDT 24
Peak memory 217132 kb
Host smart-ec40d96b-ba04-4d7a-8afc-2ba19cc66af1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799409903 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_errors.1799409903
Directory /workspace/2.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.2576814270
Short name T941
Test name
Test status
Simulation time 19450034 ps
CPU time 1.21 seconds
Started Jun 25 05:22:44 PM PDT 24
Finished Jun 25 05:22:46 PM PDT 24
Peak memory 209076 kb
Host smart-bc177291-925a-478a-8887-b913b498ab28
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576814270 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_aliasin
g.2576814270
Directory /workspace/3.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.4075585468
Short name T871
Test name
Test status
Simulation time 193006464 ps
CPU time 1.8 seconds
Started Jun 25 05:22:37 PM PDT 24
Finished Jun 25 05:22:42 PM PDT 24
Peak memory 208704 kb
Host smart-675c8f7b-72bd-49e2-a31b-3677ca6d7f62
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075585468 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_bit_bas
h.4075585468
Directory /workspace/3.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.984601786
Short name T150
Test name
Test status
Simulation time 17256910 ps
CPU time 1.07 seconds
Started Jun 25 05:22:41 PM PDT 24
Finished Jun 25 05:22:44 PM PDT 24
Peak memory 210072 kb
Host smart-8602b84e-c5a0-43bb-8182-3dfca3aa0896
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984601786 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_hw_reset
.984601786
Directory /workspace/3.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.308743164
Short name T147
Test name
Test status
Simulation time 26692097 ps
CPU time 1.43 seconds
Started Jun 25 05:22:45 PM PDT 24
Finished Jun 25 05:22:48 PM PDT 24
Peak memory 218232 kb
Host smart-d9496ae4-ab13-400d-bb3f-c62429ed5150
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308743164 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 3.lc_ctrl_csr_mem_rw_with_rand_reset.308743164
Directory /workspace/3.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.365566158
Short name T218
Test name
Test status
Simulation time 27467047 ps
CPU time 1.12 seconds
Started Jun 25 05:22:40 PM PDT 24
Finished Jun 25 05:22:43 PM PDT 24
Peak memory 209216 kb
Host smart-8e3f6880-8c6c-4b29-baab-d5621d1087eb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365566158 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_rw.365566158
Directory /workspace/3.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.2009129009
Short name T934
Test name
Test status
Simulation time 17183340 ps
CPU time 0.86 seconds
Started Jun 25 05:22:32 PM PDT 24
Finished Jun 25 05:22:37 PM PDT 24
Peak memory 208816 kb
Host smart-9b0079f7-702e-496f-b3fb-2066d1af274b
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009129009 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.lc_ctrl_jtag_alert_test.2009129009
Directory /workspace/3.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.2605477198
Short name T901
Test name
Test status
Simulation time 861049794 ps
CPU time 7.52 seconds
Started Jun 25 05:22:32 PM PDT 24
Finished Jun 25 05:22:44 PM PDT 24
Peak memory 208760 kb
Host smart-ee4503a5-4631-4214-8d88-f05b9471204a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605477198 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_aliasing.2605477198
Directory /workspace/3.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.2831284411
Short name T872
Test name
Test status
Simulation time 1466190702 ps
CPU time 4.87 seconds
Started Jun 25 05:22:30 PM PDT 24
Finished Jun 25 05:22:37 PM PDT 24
Peak memory 208816 kb
Host smart-f5143e69-5785-43bd-b65b-1b336239cd47
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831284411 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_bit_bash.2831284411
Directory /workspace/3.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.3716630756
Short name T961
Test name
Test status
Simulation time 93438106 ps
CPU time 2.05 seconds
Started Jun 25 05:22:30 PM PDT 24
Finished Jun 25 05:22:35 PM PDT 24
Peak memory 217140 kb
Host smart-45001716-b44a-4beb-a68c-462c985ab834
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716630756 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_hw_reset.3716630756
Directory /workspace/3.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3644897651
Short name T171
Test name
Test status
Simulation time 366412201 ps
CPU time 3.52 seconds
Started Jun 25 05:22:31 PM PDT 24
Finished Jun 25 05:22:38 PM PDT 24
Peak memory 218576 kb
Host smart-57f45cd7-39c4-4750-9019-5656534eaa52
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364489
7651 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3644897651
Directory /workspace/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.4098167912
Short name T955
Test name
Test status
Simulation time 585162464 ps
CPU time 1.5 seconds
Started Jun 25 05:22:28 PM PDT 24
Finished Jun 25 05:22:32 PM PDT 24
Peak memory 208976 kb
Host smart-d98a3f1b-e32a-4ab7-83d4-d03308b61bf7
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098167912 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.lc_ctrl_jtag_csr_rw.4098167912
Directory /workspace/3.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.1954112406
Short name T224
Test name
Test status
Simulation time 38223382 ps
CPU time 1.21 seconds
Started Jun 25 05:22:31 PM PDT 24
Finished Jun 25 05:22:36 PM PDT 24
Peak memory 209096 kb
Host smart-60bd88cc-e124-47ec-8bb4-c44084bea9eb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954112406 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.lc_ctrl_jtag_same_csr_outstanding.1954112406
Directory /workspace/3.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.2034945877
Short name T225
Test name
Test status
Simulation time 155909803 ps
CPU time 1.52 seconds
Started Jun 25 05:22:36 PM PDT 24
Finished Jun 25 05:22:40 PM PDT 24
Peak memory 208968 kb
Host smart-e123c52f-d77f-44f5-853d-734996ae07cc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034945877 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl
_same_csr_outstanding.2034945877
Directory /workspace/3.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.4161513197
Short name T984
Test name
Test status
Simulation time 35005318 ps
CPU time 2.4 seconds
Started Jun 25 05:22:32 PM PDT 24
Finished Jun 25 05:22:38 PM PDT 24
Peak memory 218228 kb
Host smart-bd1ec171-cd3f-4bea-9f4a-52efc566ca86
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161513197 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_errors.4161513197
Directory /workspace/3.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.2711605169
Short name T219
Test name
Test status
Simulation time 40665400 ps
CPU time 1.07 seconds
Started Jun 25 05:22:39 PM PDT 24
Finished Jun 25 05:22:42 PM PDT 24
Peak memory 217208 kb
Host smart-87dc3c7d-3276-4ab4-ba29-8732d2023c01
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711605169 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_aliasin
g.2711605169
Directory /workspace/4.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.2864390172
Short name T949
Test name
Test status
Simulation time 52920063 ps
CPU time 2.17 seconds
Started Jun 25 05:22:37 PM PDT 24
Finished Jun 25 05:22:42 PM PDT 24
Peak memory 208800 kb
Host smart-71cd5792-c41a-486c-80f9-913979be3387
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864390172 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_bit_bas
h.2864390172
Directory /workspace/4.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.1438186264
Short name T216
Test name
Test status
Simulation time 66705490 ps
CPU time 1.06 seconds
Started Jun 25 05:22:37 PM PDT 24
Finished Jun 25 05:22:41 PM PDT 24
Peak memory 211088 kb
Host smart-eb371c47-1f4b-457c-9af4-bd250ffbc615
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438186264 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_hw_rese
t.1438186264
Directory /workspace/4.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.2828896268
Short name T996
Test name
Test status
Simulation time 27323660 ps
CPU time 1.57 seconds
Started Jun 25 05:22:37 PM PDT 24
Finished Jun 25 05:22:41 PM PDT 24
Peak memory 218364 kb
Host smart-456aec22-0703-4061-ad93-e00a5e1f012b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828896268 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 4.lc_ctrl_csr_mem_rw_with_rand_reset.2828896268
Directory /workspace/4.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.1171019697
Short name T973
Test name
Test status
Simulation time 17522090 ps
CPU time 1.15 seconds
Started Jun 25 05:22:39 PM PDT 24
Finished Jun 25 05:22:43 PM PDT 24
Peak memory 208904 kb
Host smart-79f39f90-93cf-4f17-a9f6-7eb1c152d5c8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171019697 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_rw.1171019697
Directory /workspace/4.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.2882510676
Short name T940
Test name
Test status
Simulation time 44077233 ps
CPU time 1.05 seconds
Started Jun 25 05:22:41 PM PDT 24
Finished Jun 25 05:22:44 PM PDT 24
Peak memory 208824 kb
Host smart-053228dc-afba-4ebc-b81f-10a8a69d6a3c
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882510676 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.lc_ctrl_jtag_alert_test.2882510676
Directory /workspace/4.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.3277686073
Short name T888
Test name
Test status
Simulation time 701983886 ps
CPU time 15 seconds
Started Jun 25 05:22:45 PM PDT 24
Finished Jun 25 05:23:01 PM PDT 24
Peak memory 216824 kb
Host smart-ee57a9cb-b24b-44c5-88dc-f30b3726b448
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277686073 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_aliasing.3277686073
Directory /workspace/4.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.1957292849
Short name T919
Test name
Test status
Simulation time 11454087115 ps
CPU time 20.9 seconds
Started Jun 25 05:22:37 PM PDT 24
Finished Jun 25 05:23:01 PM PDT 24
Peak memory 208820 kb
Host smart-5cc3d896-e81c-4a81-80c8-b03b26ca015a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957292849 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_bit_bash.1957292849
Directory /workspace/4.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.2766416406
Short name T935
Test name
Test status
Simulation time 66545040 ps
CPU time 2.23 seconds
Started Jun 25 05:22:37 PM PDT 24
Finished Jun 25 05:22:42 PM PDT 24
Peak memory 217052 kb
Host smart-41734ef6-49dd-4af1-8682-5518e23a7f6b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766416406 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_hw_reset.2766416406
Directory /workspace/4.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2495105414
Short name T974
Test name
Test status
Simulation time 110405131 ps
CPU time 3.52 seconds
Started Jun 25 05:22:38 PM PDT 24
Finished Jun 25 05:22:44 PM PDT 24
Peak memory 221336 kb
Host smart-22d923ce-5eac-42e8-94d9-8897e0ba10bb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249510
5414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2495105414
Directory /workspace/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.2247712535
Short name T952
Test name
Test status
Simulation time 226299313 ps
CPU time 2.09 seconds
Started Jun 25 05:22:38 PM PDT 24
Finished Jun 25 05:22:42 PM PDT 24
Peak memory 209036 kb
Host smart-75bebcab-9c14-451c-bf08-cf1ef3560e4d
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247712535 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.lc_ctrl_jtag_csr_rw.2247712535
Directory /workspace/4.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.2273426470
Short name T914
Test name
Test status
Simulation time 179956493 ps
CPU time 1.71 seconds
Started Jun 25 05:22:38 PM PDT 24
Finished Jun 25 05:22:42 PM PDT 24
Peak memory 211280 kb
Host smart-78ec5fc5-f9dc-4e69-a69d-a70b60383709
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273426470 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.lc_ctrl_jtag_same_csr_outstanding.2273426470
Directory /workspace/4.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.1802830561
Short name T929
Test name
Test status
Simulation time 19201589 ps
CPU time 1.37 seconds
Started Jun 25 05:22:39 PM PDT 24
Finished Jun 25 05:22:42 PM PDT 24
Peak memory 209040 kb
Host smart-76bdba2b-7d08-42ca-b291-6386693bafe0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802830561 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl
_same_csr_outstanding.1802830561
Directory /workspace/4.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.1238236247
Short name T151
Test name
Test status
Simulation time 104717256 ps
CPU time 4.54 seconds
Started Jun 25 05:22:38 PM PDT 24
Finished Jun 25 05:22:45 PM PDT 24
Peak memory 217180 kb
Host smart-3a30562a-beb8-4b7c-8b6f-f484fd5183a4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238236247 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_errors.1238236247
Directory /workspace/4.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.2573505649
Short name T985
Test name
Test status
Simulation time 1066797942 ps
CPU time 3.98 seconds
Started Jun 25 05:22:39 PM PDT 24
Finished Jun 25 05:22:45 PM PDT 24
Peak memory 217272 kb
Host smart-469c4740-cf9e-46f3-bed5-d7f8a9132b71
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573505649 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_intg_
err.2573505649
Directory /workspace/4.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.3997881215
Short name T964
Test name
Test status
Simulation time 19273030 ps
CPU time 1.01 seconds
Started Jun 25 05:22:40 PM PDT 24
Finished Jun 25 05:22:43 PM PDT 24
Peak memory 217300 kb
Host smart-c2163fba-4967-40cc-8e89-0966df0efa57
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997881215 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 5.lc_ctrl_csr_mem_rw_with_rand_reset.3997881215
Directory /workspace/5.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.3158398099
Short name T870
Test name
Test status
Simulation time 15595449 ps
CPU time 0.85 seconds
Started Jun 25 05:22:37 PM PDT 24
Finished Jun 25 05:22:41 PM PDT 24
Peak memory 208568 kb
Host smart-9fee6ca0-1aea-4c7e-8e86-19fff9873785
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158398099 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_csr_rw.3158398099
Directory /workspace/5.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.1168970675
Short name T992
Test name
Test status
Simulation time 28784256 ps
CPU time 1.34 seconds
Started Jun 25 05:22:38 PM PDT 24
Finished Jun 25 05:22:42 PM PDT 24
Peak memory 208396 kb
Host smart-0a87a9eb-d8dc-4cdc-96dd-9d5fa6ddead5
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168970675 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.lc_ctrl_jtag_alert_test.1168970675
Directory /workspace/5.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.4156747591
Short name T907
Test name
Test status
Simulation time 265707711 ps
CPU time 5.2 seconds
Started Jun 25 05:22:36 PM PDT 24
Finished Jun 25 05:22:44 PM PDT 24
Peak memory 208936 kb
Host smart-8974255a-7f2f-474b-9668-fd0531ab8fdc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156747591 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_aliasing.4156747591
Directory /workspace/5.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.1872261067
Short name T982
Test name
Test status
Simulation time 8463516393 ps
CPU time 9.14 seconds
Started Jun 25 05:22:37 PM PDT 24
Finished Jun 25 05:22:48 PM PDT 24
Peak memory 208964 kb
Host smart-610d489e-0e0a-4bf3-b08a-560c0dc331d4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872261067 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_bit_bash.1872261067
Directory /workspace/5.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.2225408422
Short name T983
Test name
Test status
Simulation time 54159822 ps
CPU time 1.98 seconds
Started Jun 25 05:22:37 PM PDT 24
Finished Jun 25 05:22:41 PM PDT 24
Peak memory 208948 kb
Host smart-d4f41f82-d6e9-4117-91d6-cbc2c69fb58f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225408422 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_hw_reset.2225408422
Directory /workspace/5.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2809129771
Short name T906
Test name
Test status
Simulation time 3283461961 ps
CPU time 6.41 seconds
Started Jun 25 05:22:41 PM PDT 24
Finished Jun 25 05:22:49 PM PDT 24
Peak memory 222676 kb
Host smart-1b3e2cbe-9ae0-40c7-9ac8-e2a641d8aaf9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280912
9771 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2809129771
Directory /workspace/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.1252718915
Short name T886
Test name
Test status
Simulation time 354963273 ps
CPU time 1.8 seconds
Started Jun 25 05:22:45 PM PDT 24
Finished Jun 25 05:22:48 PM PDT 24
Peak memory 208972 kb
Host smart-dcc0a0b7-26c7-4b70-af61-cdce2f81a384
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252718915 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.lc_ctrl_jtag_csr_rw.1252718915
Directory /workspace/5.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.3671033156
Short name T182
Test name
Test status
Simulation time 164237693 ps
CPU time 1.91 seconds
Started Jun 25 05:22:37 PM PDT 24
Finished Jun 25 05:22:41 PM PDT 24
Peak memory 217172 kb
Host smart-74a05c4b-b401-49f9-80e2-9aa72ef7ed95
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671033156 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.lc_ctrl_jtag_same_csr_outstanding.3671033156
Directory /workspace/5.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.1989982694
Short name T970
Test name
Test status
Simulation time 30496786 ps
CPU time 1.23 seconds
Started Jun 25 05:22:36 PM PDT 24
Finished Jun 25 05:22:40 PM PDT 24
Peak memory 209152 kb
Host smart-9dfaa271-c574-41cc-b076-058393c03a74
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989982694 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl
_same_csr_outstanding.1989982694
Directory /workspace/5.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.768212793
Short name T926
Test name
Test status
Simulation time 101119976 ps
CPU time 1.44 seconds
Started Jun 25 05:22:45 PM PDT 24
Finished Jun 25 05:22:47 PM PDT 24
Peak memory 217224 kb
Host smart-588b11d7-7eb5-49c8-84e9-134219a22880
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768212793 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_errors.768212793
Directory /workspace/5.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.4215292119
Short name T971
Test name
Test status
Simulation time 34188129 ps
CPU time 1.3 seconds
Started Jun 25 05:22:40 PM PDT 24
Finished Jun 25 05:22:44 PM PDT 24
Peak memory 218700 kb
Host smart-6714fdda-b768-4361-87f4-f5581c11126b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215292119 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 6.lc_ctrl_csr_mem_rw_with_rand_reset.4215292119
Directory /workspace/6.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.3153665101
Short name T183
Test name
Test status
Simulation time 14070789 ps
CPU time 0.85 seconds
Started Jun 25 05:22:39 PM PDT 24
Finished Jun 25 05:22:42 PM PDT 24
Peak memory 208908 kb
Host smart-59217493-0ed0-463b-8092-a232bbfc269c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153665101 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_csr_rw.3153665101
Directory /workspace/6.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.1214386966
Short name T962
Test name
Test status
Simulation time 399792826 ps
CPU time 2.84 seconds
Started Jun 25 05:22:38 PM PDT 24
Finished Jun 25 05:22:43 PM PDT 24
Peak memory 208896 kb
Host smart-12f06b31-0a89-4da9-bc7d-0078e799cb51
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214386966 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.lc_ctrl_jtag_alert_test.1214386966
Directory /workspace/6.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.3116926761
Short name T893
Test name
Test status
Simulation time 1474020382 ps
CPU time 9.85 seconds
Started Jun 25 05:22:45 PM PDT 24
Finished Jun 25 05:22:56 PM PDT 24
Peak memory 208692 kb
Host smart-c50b5b68-2e35-4d40-9a99-23e90e69f160
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116926761 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_aliasing.3116926761
Directory /workspace/6.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.958664837
Short name T879
Test name
Test status
Simulation time 14682888918 ps
CPU time 54.39 seconds
Started Jun 25 05:22:37 PM PDT 24
Finished Jun 25 05:23:34 PM PDT 24
Peak memory 216964 kb
Host smart-d5c36796-f6e5-4a78-9b59-e413af9737a6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958664837 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 6.lc_ctrl_jtag_csr_bit_bash.958664837
Directory /workspace/6.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.859363391
Short name T999
Test name
Test status
Simulation time 281909788 ps
CPU time 3.35 seconds
Started Jun 25 05:22:39 PM PDT 24
Finished Jun 25 05:22:44 PM PDT 24
Peak memory 217176 kb
Host smart-2c0889f7-507f-4784-847d-f265ae7e7eec
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859363391 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 6.lc_ctrl_jtag_csr_hw_reset.859363391
Directory /workspace/6.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1393751905
Short name T910
Test name
Test status
Simulation time 620236394 ps
CPU time 4.38 seconds
Started Jun 25 05:22:38 PM PDT 24
Finished Jun 25 05:22:44 PM PDT 24
Peak memory 221288 kb
Host smart-c90a3763-00c5-48e1-859e-dd48dd5bde2b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139375
1905 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1393751905
Directory /workspace/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.3271772036
Short name T938
Test name
Test status
Simulation time 80592056 ps
CPU time 1.47 seconds
Started Jun 25 05:22:38 PM PDT 24
Finished Jun 25 05:22:42 PM PDT 24
Peak memory 208920 kb
Host smart-0ddcf9f9-4806-4d27-9513-47b9b8612d27
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271772036 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.lc_ctrl_jtag_csr_rw.3271772036
Directory /workspace/6.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.239834882
Short name T948
Test name
Test status
Simulation time 34359691 ps
CPU time 1.31 seconds
Started Jun 25 05:22:38 PM PDT 24
Finished Jun 25 05:22:42 PM PDT 24
Peak memory 208932 kb
Host smart-0aebdd49-a589-4ffa-b4c6-bc7c2e723c63
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239834882 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.lc_ctrl_jtag_same_csr_outstanding.239834882
Directory /workspace/6.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.659877074
Short name T920
Test name
Test status
Simulation time 17143627 ps
CPU time 1 seconds
Started Jun 25 05:22:38 PM PDT 24
Finished Jun 25 05:22:42 PM PDT 24
Peak memory 209156 kb
Host smart-537cbdad-6e98-4394-9b7d-c1ce5c6639ef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659877074 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
same_csr_outstanding.659877074
Directory /workspace/6.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.2722714080
Short name T924
Test name
Test status
Simulation time 50479326 ps
CPU time 3.67 seconds
Started Jun 25 05:22:45 PM PDT 24
Finished Jun 25 05:22:50 PM PDT 24
Peak memory 217184 kb
Host smart-a6c3d97c-f528-43eb-a546-e2fcbe8edd04
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722714080 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_errors.2722714080
Directory /workspace/6.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.1570350630
Short name T168
Test name
Test status
Simulation time 385507338 ps
CPU time 2.36 seconds
Started Jun 25 05:22:45 PM PDT 24
Finished Jun 25 05:22:48 PM PDT 24
Peak memory 221568 kb
Host smart-bf5234e7-4c1d-497f-89a3-2fe949d93c53
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570350630 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_intg_
err.1570350630
Directory /workspace/6.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.652048199
Short name T931
Test name
Test status
Simulation time 31795779 ps
CPU time 1.16 seconds
Started Jun 25 05:22:48 PM PDT 24
Finished Jun 25 05:22:51 PM PDT 24
Peak memory 217456 kb
Host smart-bd27a548-a7a8-4387-ba2d-17f18f3ecc24
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652048199 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 7.lc_ctrl_csr_mem_rw_with_rand_reset.652048199
Directory /workspace/7.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.920474544
Short name T878
Test name
Test status
Simulation time 137804141 ps
CPU time 0.83 seconds
Started Jun 25 05:22:46 PM PDT 24
Finished Jun 25 05:22:48 PM PDT 24
Peak memory 208308 kb
Host smart-f72fe4ee-7434-46e2-a50b-136fcc99489a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920474544 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_csr_rw.920474544
Directory /workspace/7.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.2644157948
Short name T882
Test name
Test status
Simulation time 187905600 ps
CPU time 1.69 seconds
Started Jun 25 05:22:47 PM PDT 24
Finished Jun 25 05:22:50 PM PDT 24
Peak memory 208328 kb
Host smart-b029ac4f-ebf4-4a13-9e9c-3b4b2d581e26
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644157948 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.lc_ctrl_jtag_alert_test.2644157948
Directory /workspace/7.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.2843992180
Short name T987
Test name
Test status
Simulation time 1242665794 ps
CPU time 15.35 seconds
Started Jun 25 05:22:39 PM PDT 24
Finished Jun 25 05:22:56 PM PDT 24
Peak memory 208696 kb
Host smart-c18b64d2-25bf-4d87-95cd-a511e21d8d1e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843992180 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_aliasing.2843992180
Directory /workspace/7.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.521971884
Short name T154
Test name
Test status
Simulation time 18285509032 ps
CPU time 9.67 seconds
Started Jun 25 05:22:37 PM PDT 24
Finished Jun 25 05:22:50 PM PDT 24
Peak memory 209084 kb
Host smart-b3452854-2668-4740-a136-de8ba8e9d090
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521971884 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 7.lc_ctrl_jtag_csr_bit_bash.521971884
Directory /workspace/7.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.7748768
Short name T959
Test name
Test status
Simulation time 2336804015 ps
CPU time 1.7 seconds
Started Jun 25 05:22:41 PM PDT 24
Finished Jun 25 05:22:44 PM PDT 24
Peak memory 210092 kb
Host smart-99f123d7-ef9a-4b4c-8209-d821c2509462
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7748768 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base
_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 7.lc_ctrl_jtag_csr_hw_reset.7748768
Directory /workspace/7.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4074616796
Short name T989
Test name
Test status
Simulation time 2281073021 ps
CPU time 3.13 seconds
Started Jun 25 05:22:46 PM PDT 24
Finished Jun 25 05:22:51 PM PDT 24
Peak memory 218356 kb
Host smart-71eb93cc-454a-48b7-aed9-2de6d3d55f8e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407461
6796 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4074616796
Directory /workspace/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.3329193858
Short name T153
Test name
Test status
Simulation time 50258812 ps
CPU time 1.19 seconds
Started Jun 25 05:22:45 PM PDT 24
Finished Jun 25 05:22:48 PM PDT 24
Peak memory 217004 kb
Host smart-1e93a989-9c4a-4db3-bf4b-6281bb9df08a
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329193858 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.lc_ctrl_jtag_csr_rw.3329193858
Directory /workspace/7.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.2782334347
Short name T184
Test name
Test status
Simulation time 60074679 ps
CPU time 2.16 seconds
Started Jun 25 05:22:47 PM PDT 24
Finished Jun 25 05:22:51 PM PDT 24
Peak memory 208988 kb
Host smart-21ce9f06-52bc-4187-bf87-cb55f6ce5e99
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782334347 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.lc_ctrl_jtag_same_csr_outstanding.2782334347
Directory /workspace/7.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.159108374
Short name T923
Test name
Test status
Simulation time 25742856 ps
CPU time 1.11 seconds
Started Jun 25 05:22:49 PM PDT 24
Finished Jun 25 05:22:53 PM PDT 24
Peak memory 217188 kb
Host smart-db7c8789-812c-4702-915d-e79e16c41865
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159108374 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
same_csr_outstanding.159108374
Directory /workspace/7.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.1518623898
Short name T921
Test name
Test status
Simulation time 1066830094 ps
CPU time 2.81 seconds
Started Jun 25 05:22:47 PM PDT 24
Finished Jun 25 05:22:52 PM PDT 24
Peak memory 217308 kb
Host smart-d310e91b-6c53-4a84-9025-35bcd5c04dcc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518623898 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_errors.1518623898
Directory /workspace/7.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.11582859
Short name T953
Test name
Test status
Simulation time 89859249 ps
CPU time 1.17 seconds
Started Jun 25 05:22:49 PM PDT 24
Finished Jun 25 05:22:52 PM PDT 24
Peak memory 221852 kb
Host smart-f83c3d2b-a653-4572-a7ba-6b7f51eb208c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11582859 -assert nopostproc +UVM_TESTNAME=l
c_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.lc_ctrl_csr_mem_rw_with_rand_reset.11582859
Directory /workspace/8.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.3591465987
Short name T896
Test name
Test status
Simulation time 13308345 ps
CPU time 0.83 seconds
Started Jun 25 05:22:46 PM PDT 24
Finished Jun 25 05:22:49 PM PDT 24
Peak memory 208892 kb
Host smart-c3a55715-e1af-43cc-823d-0207569dbdcf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591465987 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_csr_rw.3591465987
Directory /workspace/8.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.705348881
Short name T880
Test name
Test status
Simulation time 44834012 ps
CPU time 1.6 seconds
Started Jun 25 05:22:47 PM PDT 24
Finished Jun 25 05:22:51 PM PDT 24
Peak memory 208912 kb
Host smart-5c1624da-ff71-4150-9917-ac123063f427
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705348881 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 8.lc_ctrl_jtag_alert_test.705348881
Directory /workspace/8.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.4010627505
Short name T890
Test name
Test status
Simulation time 1248891401 ps
CPU time 7.63 seconds
Started Jun 25 05:22:46 PM PDT 24
Finished Jun 25 05:22:55 PM PDT 24
Peak memory 208976 kb
Host smart-dea04120-b3b8-4d7d-8764-5f753d1bda1b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010627505 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_aliasing.4010627505
Directory /workspace/8.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.1764153754
Short name T899
Test name
Test status
Simulation time 1891656178 ps
CPU time 10.9 seconds
Started Jun 25 05:22:47 PM PDT 24
Finished Jun 25 05:23:00 PM PDT 24
Peak memory 208964 kb
Host smart-d305ece4-5d9f-4946-9d0f-f900817eec15
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764153754 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_bit_bash.1764153754
Directory /workspace/8.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.4059671464
Short name T875
Test name
Test status
Simulation time 135792563 ps
CPU time 3.55 seconds
Started Jun 25 05:22:48 PM PDT 24
Finished Jun 25 05:22:53 PM PDT 24
Peak memory 217112 kb
Host smart-eaed6117-82d3-4ee9-898f-4c8a2b750b49
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059671464 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_hw_reset.4059671464
Directory /workspace/8.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.593068227
Short name T978
Test name
Test status
Simulation time 40920945 ps
CPU time 1.09 seconds
Started Jun 25 05:22:48 PM PDT 24
Finished Jun 25 05:22:51 PM PDT 24
Peak memory 208976 kb
Host smart-6065f577-32ea-4c5b-823b-0e7ee14bd639
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593068227 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.lc_ctrl_jtag_csr_rw.593068227
Directory /workspace/8.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.4084950561
Short name T991
Test name
Test status
Simulation time 161312842 ps
CPU time 1.51 seconds
Started Jun 25 05:22:46 PM PDT 24
Finished Jun 25 05:22:49 PM PDT 24
Peak memory 217356 kb
Host smart-6a79d3ec-11da-497b-8d40-a401f58cb1fc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084950561 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.lc_ctrl_jtag_same_csr_outstanding.4084950561
Directory /workspace/8.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.2852222644
Short name T925
Test name
Test status
Simulation time 84841874 ps
CPU time 1.53 seconds
Started Jun 25 05:22:47 PM PDT 24
Finished Jun 25 05:22:50 PM PDT 24
Peak memory 217228 kb
Host smart-cf7e6a54-2484-427a-b3ee-2723cc48c070
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852222644 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl
_same_csr_outstanding.2852222644
Directory /workspace/8.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.3214674312
Short name T146
Test name
Test status
Simulation time 35423895 ps
CPU time 2.73 seconds
Started Jun 25 05:22:48 PM PDT 24
Finished Jun 25 05:22:53 PM PDT 24
Peak memory 217204 kb
Host smart-2963bd39-6881-46d0-ae4e-1a58a8426c26
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214674312 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_errors.3214674312
Directory /workspace/8.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.3851177501
Short name T877
Test name
Test status
Simulation time 67759459 ps
CPU time 1.2 seconds
Started Jun 25 05:22:48 PM PDT 24
Finished Jun 25 05:22:51 PM PDT 24
Peak memory 217236 kb
Host smart-5e021081-405c-467e-9b8e-ee6e24ab53ac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851177501 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 9.lc_ctrl_csr_mem_rw_with_rand_reset.3851177501
Directory /workspace/9.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.2077953161
Short name T214
Test name
Test status
Simulation time 47921045 ps
CPU time 1.04 seconds
Started Jun 25 05:22:47 PM PDT 24
Finished Jun 25 05:22:51 PM PDT 24
Peak memory 208652 kb
Host smart-7477503c-3b0b-4d96-aa3e-f1815cd54d07
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077953161 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_csr_rw.2077953161
Directory /workspace/9.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.1897061673
Short name T885
Test name
Test status
Simulation time 26350939 ps
CPU time 1.36 seconds
Started Jun 25 05:22:50 PM PDT 24
Finished Jun 25 05:22:54 PM PDT 24
Peak memory 208216 kb
Host smart-4f7e6470-63ec-48a1-b05a-cf875c89ce4a
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897061673 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.lc_ctrl_jtag_alert_test.1897061673
Directory /workspace/9.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.3132998165
Short name T904
Test name
Test status
Simulation time 2504308812 ps
CPU time 14.14 seconds
Started Jun 25 05:22:47 PM PDT 24
Finished Jun 25 05:23:02 PM PDT 24
Peak memory 208928 kb
Host smart-ee3351b6-ea3a-4cdf-b31d-f309dcfeabce
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132998165 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_aliasing.3132998165
Directory /workspace/9.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.720724320
Short name T917
Test name
Test status
Simulation time 1250827429 ps
CPU time 28.78 seconds
Started Jun 25 05:22:46 PM PDT 24
Finished Jun 25 05:23:17 PM PDT 24
Peak memory 208868 kb
Host smart-f0a73dc9-3f64-4767-8e3f-ae6cb7fbc3da
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720724320 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 9.lc_ctrl_jtag_csr_bit_bash.720724320
Directory /workspace/9.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.1275106425
Short name T937
Test name
Test status
Simulation time 214289208 ps
CPU time 5.2 seconds
Started Jun 25 05:22:45 PM PDT 24
Finished Jun 25 05:22:51 PM PDT 24
Peak memory 210604 kb
Host smart-4acb073b-eeb2-47d4-bad8-8b4b96ee2cf0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275106425 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_hw_reset.1275106425
Directory /workspace/9.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.962344384
Short name T174
Test name
Test status
Simulation time 152925641 ps
CPU time 4.03 seconds
Started Jun 25 05:22:47 PM PDT 24
Finished Jun 25 05:22:53 PM PDT 24
Peak memory 217968 kb
Host smart-58c757c4-b4a3-4137-b567-fcf7c1400a6c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962344
384 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.962344384
Directory /workspace/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.1956624288
Short name T900
Test name
Test status
Simulation time 48574941 ps
CPU time 1.89 seconds
Started Jun 25 05:22:48 PM PDT 24
Finished Jun 25 05:22:51 PM PDT 24
Peak memory 208976 kb
Host smart-537b3d54-a14a-41f3-bd28-479e8916663a
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956624288 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.lc_ctrl_jtag_csr_rw.1956624288
Directory /workspace/9.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.1761343737
Short name T960
Test name
Test status
Simulation time 123116867 ps
CPU time 1.27 seconds
Started Jun 25 05:22:48 PM PDT 24
Finished Jun 25 05:22:51 PM PDT 24
Peak memory 209044 kb
Host smart-ea1bfbe4-aa7d-477a-b3e2-d1a309c01a5b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761343737 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.lc_ctrl_jtag_same_csr_outstanding.1761343737
Directory /workspace/9.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.3513671258
Short name T997
Test name
Test status
Simulation time 65849109 ps
CPU time 1.67 seconds
Started Jun 25 05:22:50 PM PDT 24
Finished Jun 25 05:22:55 PM PDT 24
Peak memory 209040 kb
Host smart-dd8ca06f-84c5-48e0-b964-0486e6d75aca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513671258 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl
_same_csr_outstanding.3513671258
Directory /workspace/9.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.2537661986
Short name T889
Test name
Test status
Simulation time 220019431 ps
CPU time 2.26 seconds
Started Jun 25 05:22:46 PM PDT 24
Finished Jun 25 05:22:49 PM PDT 24
Peak memory 217248 kb
Host smart-fb919166-8bca-47ab-bdae-9ae7cec66800
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537661986 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_errors.2537661986
Directory /workspace/9.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.941261548
Short name T994
Test name
Test status
Simulation time 213368896 ps
CPU time 1.89 seconds
Started Jun 25 05:22:48 PM PDT 24
Finished Jun 25 05:22:52 PM PDT 24
Peak memory 221464 kb
Host smart-31389f1c-cfee-408b-bbe5-0574190dd44d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941261548 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_intg_e
rr.941261548
Directory /workspace/9.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_alert_test.3068206726
Short name T345
Test name
Test status
Simulation time 17570146 ps
CPU time 0.91 seconds
Started Jun 25 06:18:35 PM PDT 24
Finished Jun 25 06:18:38 PM PDT 24
Peak memory 209352 kb
Host smart-64384805-cf0d-490c-8bbd-eb001108a1bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068206726 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_alert_test.3068206726
Directory /workspace/0.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.lc_ctrl_errors.1387332870
Short name T386
Test name
Test status
Simulation time 3672769057 ps
CPU time 14.95 seconds
Started Jun 25 06:18:22 PM PDT 24
Finished Jun 25 06:18:38 PM PDT 24
Peak memory 219608 kb
Host smart-42ea3091-a3d2-4b8f-b6f6-9b91ca326de7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387332870 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_errors.1387332870
Directory /workspace/0.lc_ctrl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_access.3110018925
Short name T135
Test name
Test status
Simulation time 131112206 ps
CPU time 4.24 seconds
Started Jun 25 06:18:29 PM PDT 24
Finished Jun 25 06:18:34 PM PDT 24
Peak memory 217412 kb
Host smart-4e2af613-7e1a-45c5-8483-4cd3d121bebb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110018925 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_access.3110018925
Directory /workspace/0.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_errors.3694261522
Short name T627
Test name
Test status
Simulation time 2822204205 ps
CPU time 24.26 seconds
Started Jun 25 06:18:29 PM PDT 24
Finished Jun 25 06:18:54 PM PDT 24
Peak memory 219352 kb
Host smart-7c84e677-ee2b-4e80-a755-6955714e66d3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694261522 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_er
rors.3694261522
Directory /workspace/0.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_priority.1040243641
Short name T454
Test name
Test status
Simulation time 4384273293 ps
CPU time 9.81 seconds
Started Jun 25 06:18:32 PM PDT 24
Finished Jun 25 06:18:43 PM PDT 24
Peak memory 218200 kb
Host smart-d4208a82-e576-4d4d-98ef-d53afa6b2ad3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040243641 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_priority.1
040243641
Directory /workspace/0.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_prog_failure.693738393
Short name T707
Test name
Test status
Simulation time 182481082 ps
CPU time 3.2 seconds
Started Jun 25 06:18:28 PM PDT 24
Finished Jun 25 06:18:32 PM PDT 24
Peak memory 222048 kb
Host smart-ae767e81-e796-4547-93cf-ddf96e998872
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693738393 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_
prog_failure.693738393
Directory /workspace/0.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_regwen_during_op.3819373316
Short name T71
Test name
Test status
Simulation time 862100596 ps
CPU time 12.17 seconds
Started Jun 25 06:18:29 PM PDT 24
Finished Jun 25 06:18:42 PM PDT 24
Peak memory 217976 kb
Host smart-5fc4dbd1-5bb4-49ca-ad22-87de88c0b628
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819373316 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_regwen_during_op.3819373316
Directory /workspace/0.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_smoke.4033772636
Short name T708
Test name
Test status
Simulation time 349683411 ps
CPU time 4.84 seconds
Started Jun 25 06:18:31 PM PDT 24
Finished Jun 25 06:18:36 PM PDT 24
Peak memory 217968 kb
Host smart-061c1e8a-9ac3-43b7-84da-68ecfa30cea3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033772636 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_smoke.
4033772636
Directory /workspace/0.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_failure.3724349021
Short name T690
Test name
Test status
Simulation time 13779917997 ps
CPU time 35.58 seconds
Started Jun 25 06:18:28 PM PDT 24
Finished Jun 25 06:19:05 PM PDT 24
Peak memory 253848 kb
Host smart-69ed8e21-dd7e-4e13-a865-68c480458a37
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724349021 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jta
g_state_failure.3724349021
Directory /workspace/0.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_post_trans.1707414232
Short name T313
Test name
Test status
Simulation time 9510452833 ps
CPU time 20.36 seconds
Started Jun 25 06:18:31 PM PDT 24
Finished Jun 25 06:18:52 PM PDT 24
Peak memory 251328 kb
Host smart-d589d110-9f25-4ee4-a755-4a69d01d525e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707414232 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_state_post_trans.1707414232
Directory /workspace/0.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_prog_failure.3644268487
Short name T292
Test name
Test status
Simulation time 136657428 ps
CPU time 5.54 seconds
Started Jun 25 06:18:20 PM PDT 24
Finished Jun 25 06:18:26 PM PDT 24
Peak memory 222728 kb
Host smart-6228f8fe-9b10-421e-a74f-0304d967968f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644268487 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_prog_failure.3644268487
Directory /workspace/0.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_regwen_during_op.1435823585
Short name T610
Test name
Test status
Simulation time 1634665042 ps
CPU time 23.55 seconds
Started Jun 25 06:18:29 PM PDT 24
Finished Jun 25 06:18:54 PM PDT 24
Peak memory 214640 kb
Host smart-b1c507d3-1f1a-40d6-b261-587ac29bae09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435823585 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_regwen_during_op.1435823585
Directory /workspace/0.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_mubi.797449540
Short name T784
Test name
Test status
Simulation time 246312932 ps
CPU time 9.89 seconds
Started Jun 25 06:18:28 PM PDT 24
Finished Jun 25 06:18:38 PM PDT 24
Peak memory 219280 kb
Host smart-42de53f7-9dac-4fe0-9915-d458abb3e030
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797449540 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_mubi.797449540
Directory /workspace/0.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_digest.2462541378
Short name T525
Test name
Test status
Simulation time 1659913648 ps
CPU time 15.71 seconds
Started Jun 25 06:18:37 PM PDT 24
Finished Jun 25 06:18:54 PM PDT 24
Peak memory 218604 kb
Host smart-76d795a6-fddd-4734-98a8-ba4d4aca0f2a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462541378 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_di
gest.2462541378
Directory /workspace/0.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_mux.2397890817
Short name T659
Test name
Test status
Simulation time 1708669013 ps
CPU time 6.42 seconds
Started Jun 25 06:18:32 PM PDT 24
Finished Jun 25 06:18:39 PM PDT 24
Peak memory 226360 kb
Host smart-a4852b0f-8f95-4460-99bd-8daf3c1d952d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397890817 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_mux.2
397890817
Directory /workspace/0.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/0.lc_ctrl_security_escalation.1736775962
Short name T507
Test name
Test status
Simulation time 1085798748 ps
CPU time 10.87 seconds
Started Jun 25 06:18:21 PM PDT 24
Finished Jun 25 06:18:32 PM PDT 24
Peak memory 226196 kb
Host smart-1518006c-910b-4e4a-8777-253411a00cd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736775962 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_security_escalation.1736775962
Directory /workspace/0.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/0.lc_ctrl_smoke.3666909077
Short name T777
Test name
Test status
Simulation time 262389825 ps
CPU time 2.98 seconds
Started Jun 25 06:18:13 PM PDT 24
Finished Jun 25 06:18:16 PM PDT 24
Peak memory 215240 kb
Host smart-246f96de-3c96-491b-85d7-f1775e3c00f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666909077 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_smoke.3666909077
Directory /workspace/0.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_failure.3716173995
Short name T377
Test name
Test status
Simulation time 437586212 ps
CPU time 22.96 seconds
Started Jun 25 06:18:22 PM PDT 24
Finished Jun 25 06:18:46 PM PDT 24
Peak memory 245900 kb
Host smart-3a741273-e035-401b-bed1-0683280ca1b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716173995 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_failure.3716173995
Directory /workspace/0.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_post_trans.1326892365
Short name T858
Test name
Test status
Simulation time 83837068 ps
CPU time 4.72 seconds
Started Jun 25 06:18:21 PM PDT 24
Finished Jun 25 06:18:26 PM PDT 24
Peak memory 223292 kb
Host smart-a17544b6-3b84-40a0-9786-957dcc3c2656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326892365 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_post_trans.1326892365
Directory /workspace/0.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all.2700211459
Short name T765
Test name
Test status
Simulation time 5664619206 ps
CPU time 109.48 seconds
Started Jun 25 06:18:37 PM PDT 24
Finished Jun 25 06:20:28 PM PDT 24
Peak memory 284124 kb
Host smart-8db8df8d-7ddf-4d31-bbfa-f25a5da9f675
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700211459 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.lc_ctrl_stress_all.2700211459
Directory /workspace/0.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all_with_rand_reset.2291620741
Short name T178
Test name
Test status
Simulation time 23822307312 ps
CPU time 241.19 seconds
Started Jun 25 06:18:36 PM PDT 24
Finished Jun 25 06:22:39 PM PDT 24
Peak memory 277648 kb
Host smart-fd868ceb-809f-4122-8589-9548b8ba88d5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2291620741 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_stress_all_with_rand_reset.2291620741
Directory /workspace/0.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.lc_ctrl_volatile_unlock_smoke.2300539673
Short name T648
Test name
Test status
Simulation time 27772324 ps
CPU time 0.94 seconds
Started Jun 25 06:18:13 PM PDT 24
Finished Jun 25 06:18:15 PM PDT 24
Peak memory 212192 kb
Host smart-0108cc39-dd5d-4bb3-b089-fbd50f3af077
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300539673 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ct
rl_volatile_unlock_smoke.2300539673
Directory /workspace/0.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_alert_test.655493240
Short name T795
Test name
Test status
Simulation time 95942921 ps
CPU time 0.94 seconds
Started Jun 25 06:19:02 PM PDT 24
Finished Jun 25 06:19:04 PM PDT 24
Peak memory 209312 kb
Host smart-53ce3086-a75b-4c8d-a4fb-aa9c9b8f1c30
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655493240 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_alert_test.655493240
Directory /workspace/1.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.lc_ctrl_claim_transition_if.3559317309
Short name T668
Test name
Test status
Simulation time 46445925 ps
CPU time 0.95 seconds
Started Jun 25 06:18:43 PM PDT 24
Finished Jun 25 06:18:45 PM PDT 24
Peak memory 209304 kb
Host smart-eb8e868a-3201-448a-a324-92e038d3a6c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559317309 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_claim_transition_if.3559317309
Directory /workspace/1.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/1.lc_ctrl_errors.2854441187
Short name T588
Test name
Test status
Simulation time 1408039888 ps
CPU time 13.2 seconds
Started Jun 25 06:18:46 PM PDT 24
Finished Jun 25 06:19:00 PM PDT 24
Peak memory 226668 kb
Host smart-2e6e53b5-c80e-4aee-bbc8-df61b3e339b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854441187 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_errors.2854441187
Directory /workspace/1.lc_ctrl_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_access.2780366370
Short name T791
Test name
Test status
Simulation time 550769444 ps
CPU time 7.37 seconds
Started Jun 25 06:18:55 PM PDT 24
Finished Jun 25 06:19:03 PM PDT 24
Peak memory 217508 kb
Host smart-56246841-f615-405b-aaf2-5b2f815cb62e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780366370 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_access.2780366370
Directory /workspace/1.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_errors.2195683955
Short name T397
Test name
Test status
Simulation time 2597854444 ps
CPU time 39.62 seconds
Started Jun 25 06:18:53 PM PDT 24
Finished Jun 25 06:19:33 PM PDT 24
Peak memory 219280 kb
Host smart-35d477a7-0158-4b8e-bf04-4aec6c328cb9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195683955 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_er
rors.2195683955
Directory /workspace/1.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_priority.2705708099
Short name T296
Test name
Test status
Simulation time 2203879647 ps
CPU time 15.18 seconds
Started Jun 25 06:18:54 PM PDT 24
Finished Jun 25 06:19:10 PM PDT 24
Peak memory 218204 kb
Host smart-e4e7500a-def5-4072-939a-cdae885251e0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705708099 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_priority.2
705708099
Directory /workspace/1.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_prog_failure.2810504735
Short name T415
Test name
Test status
Simulation time 1089590960 ps
CPU time 29.3 seconds
Started Jun 25 06:18:53 PM PDT 24
Finished Jun 25 06:19:23 PM PDT 24
Peak memory 218508 kb
Host smart-ad66fa0b-d812-4db3-99d2-52aad630be96
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810504735 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag
_prog_failure.2810504735
Directory /workspace/1.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_regwen_during_op.16197774
Short name T675
Test name
Test status
Simulation time 1556426785 ps
CPU time 12.65 seconds
Started Jun 25 06:18:54 PM PDT 24
Finished Jun 25 06:19:07 PM PDT 24
Peak memory 217976 kb
Host smart-753f0f54-7bab-4bf9-81ad-b348defdd009
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16197774 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_r
egwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jt
ag_regwen_during_op.16197774
Directory /workspace/1.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_smoke.3276994838
Short name T95
Test name
Test status
Simulation time 303640508 ps
CPU time 9.13 seconds
Started Jun 25 06:18:54 PM PDT 24
Finished Jun 25 06:19:04 PM PDT 24
Peak memory 218000 kb
Host smart-c8f240c1-a3b0-4079-8f37-dd812a2c2442
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276994838 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_smoke.
3276994838
Directory /workspace/1.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_failure.3849893034
Short name T697
Test name
Test status
Simulation time 7362211671 ps
CPU time 48.42 seconds
Started Jun 25 06:18:53 PM PDT 24
Finished Jun 25 06:19:43 PM PDT 24
Peak memory 254440 kb
Host smart-1386d0bb-2996-4e7f-b1db-a686db1cb3cc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849893034 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jta
g_state_failure.3849893034
Directory /workspace/1.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_post_trans.1772427344
Short name T111
Test name
Test status
Simulation time 508082897 ps
CPU time 13.43 seconds
Started Jun 25 06:18:54 PM PDT 24
Finished Jun 25 06:19:08 PM PDT 24
Peak memory 246164 kb
Host smart-a6c01583-4e13-4811-b024-79fbd93672b2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772427344 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_state_post_trans.1772427344
Directory /workspace/1.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_prog_failure.3800128339
Short name T327
Test name
Test status
Simulation time 32875594 ps
CPU time 1.89 seconds
Started Jun 25 06:18:45 PM PDT 24
Finished Jun 25 06:18:48 PM PDT 24
Peak memory 222556 kb
Host smart-0d17ed89-189a-4977-bcdb-58fdf2cf040b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800128339 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_prog_failure.3800128339
Directory /workspace/1.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_regwen_during_op.2479958897
Short name T813
Test name
Test status
Simulation time 2183188063 ps
CPU time 17.64 seconds
Started Jun 25 06:18:45 PM PDT 24
Finished Jun 25 06:19:04 PM PDT 24
Peak memory 215016 kb
Host smart-f8aef88c-163d-493f-8516-f3cacd08b620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479958897 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_regwen_during_op.2479958897
Directory /workspace/1.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_cm.1458165018
Short name T127
Test name
Test status
Simulation time 721370518 ps
CPU time 22.11 seconds
Started Jun 25 06:19:01 PM PDT 24
Finished Jun 25 06:19:24 PM PDT 24
Peak memory 281628 kb
Host smart-2bc2433e-7512-46ec-943e-8dbe7c3f8b03
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458165018 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_cm.1458165018
Directory /workspace/1.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_mubi.833591416
Short name T436
Test name
Test status
Simulation time 289648271 ps
CPU time 14.78 seconds
Started Jun 25 06:18:55 PM PDT 24
Finished Jun 25 06:19:10 PM PDT 24
Peak memory 219212 kb
Host smart-83197c93-a277-4c2a-8902-f2f093443f1c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833591416 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_mubi.833591416
Directory /workspace/1.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_digest.1221499131
Short name T351
Test name
Test status
Simulation time 829271665 ps
CPU time 7.8 seconds
Started Jun 25 06:19:01 PM PDT 24
Finished Jun 25 06:19:10 PM PDT 24
Peak memory 218600 kb
Host smart-1e11a88a-6874-46d6-8be7-4e0eacda0a52
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221499131 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_di
gest.1221499131
Directory /workspace/1.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_mux.2079136525
Short name T733
Test name
Test status
Simulation time 227770538 ps
CPU time 9.29 seconds
Started Jun 25 06:19:02 PM PDT 24
Finished Jun 25 06:19:12 PM PDT 24
Peak memory 218588 kb
Host smart-6f1fa8e7-83d7-4040-bf77-d65213850173
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079136525 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_mux.2
079136525
Directory /workspace/1.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/1.lc_ctrl_security_escalation.266442739
Short name T409
Test name
Test status
Simulation time 626892332 ps
CPU time 9.19 seconds
Started Jun 25 06:18:44 PM PDT 24
Finished Jun 25 06:18:54 PM PDT 24
Peak memory 226440 kb
Host smart-b4a3f35b-037b-464c-b492-ec76834740ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266442739 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_security_escalation.266442739
Directory /workspace/1.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/1.lc_ctrl_smoke.1269866448
Short name T643
Test name
Test status
Simulation time 152038792 ps
CPU time 2.7 seconds
Started Jun 25 06:18:35 PM PDT 24
Finished Jun 25 06:18:39 PM PDT 24
Peak memory 214688 kb
Host smart-0898ffc6-4545-41ca-bfe4-7c61daeb4475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269866448 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_smoke.1269866448
Directory /workspace/1.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_failure.2930301842
Short name T427
Test name
Test status
Simulation time 316621855 ps
CPU time 28.75 seconds
Started Jun 25 06:18:35 PM PDT 24
Finished Jun 25 06:19:04 PM PDT 24
Peak memory 251316 kb
Host smart-eb41c111-1c11-40c3-853a-43f7179eaf98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930301842 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_failure.2930301842
Directory /workspace/1.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_post_trans.4141261646
Short name T242
Test name
Test status
Simulation time 51300725 ps
CPU time 6.32 seconds
Started Jun 25 06:18:37 PM PDT 24
Finished Jun 25 06:18:45 PM PDT 24
Peak memory 250776 kb
Host smart-f0e45c38-49ab-4424-a057-f36b9d067a06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141261646 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_post_trans.4141261646
Directory /workspace/1.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_stress_all.558461814
Short name T819
Test name
Test status
Simulation time 25908409990 ps
CPU time 146.95 seconds
Started Jun 25 06:19:01 PM PDT 24
Finished Jun 25 06:21:29 PM PDT 24
Peak memory 274748 kb
Host smart-87085485-300e-4b6e-88fb-422390480ead
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558461814 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.lc_ctrl_stress_all.558461814
Directory /workspace/1.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.lc_ctrl_volatile_unlock_smoke.2410162742
Short name T124
Test name
Test status
Simulation time 31468730 ps
CPU time 0.96 seconds
Started Jun 25 06:18:35 PM PDT 24
Finished Jun 25 06:18:38 PM PDT 24
Peak memory 212276 kb
Host smart-1c85d358-a382-467e-a62e-c6a00df00510
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410162742 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ct
rl_volatile_unlock_smoke.2410162742
Directory /workspace/1.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_alert_test.163964105
Short name T609
Test name
Test status
Simulation time 40688265 ps
CPU time 1 seconds
Started Jun 25 06:21:07 PM PDT 24
Finished Jun 25 06:21:09 PM PDT 24
Peak memory 209372 kb
Host smart-3736ce35-4d76-4891-aa77-8f12523f13c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163964105 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_alert_test.163964105
Directory /workspace/10.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.lc_ctrl_errors.1369801665
Short name T47
Test name
Test status
Simulation time 418542261 ps
CPU time 10.42 seconds
Started Jun 25 06:21:05 PM PDT 24
Finished Jun 25 06:21:16 PM PDT 24
Peak memory 218620 kb
Host smart-b8abc97b-41cc-41b9-8f9f-3ad40adfe57d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369801665 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_errors.1369801665
Directory /workspace/10.lc_ctrl_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_access.2144496765
Short name T632
Test name
Test status
Simulation time 1201387491 ps
CPU time 12.14 seconds
Started Jun 25 06:21:06 PM PDT 24
Finished Jun 25 06:21:19 PM PDT 24
Peak memory 217872 kb
Host smart-7ce0b332-12f3-4458-8f92-03517cdecc8c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144496765 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_access.2144496765
Directory /workspace/10.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_errors.2244822701
Short name T722
Test name
Test status
Simulation time 5902695435 ps
CPU time 41.91 seconds
Started Jun 25 06:21:06 PM PDT 24
Finished Jun 25 06:21:49 PM PDT 24
Peak memory 218632 kb
Host smart-f9c132c3-a46e-4c70-b766-ec9c162dde63
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244822701 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_e
rrors.2244822701
Directory /workspace/10.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_prog_failure.4250937626
Short name T388
Test name
Test status
Simulation time 590583334 ps
CPU time 18.4 seconds
Started Jun 25 06:21:07 PM PDT 24
Finished Jun 25 06:21:27 PM PDT 24
Peak memory 218560 kb
Host smart-26f8829a-0cc0-44ba-a99b-173b105f0e22
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250937626 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jta
g_prog_failure.4250937626
Directory /workspace/10.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_smoke.2508027039
Short name T107
Test name
Test status
Simulation time 947929392 ps
CPU time 3.85 seconds
Started Jun 25 06:21:07 PM PDT 24
Finished Jun 25 06:21:12 PM PDT 24
Peak memory 217976 kb
Host smart-7b863110-4750-423b-993c-e96cbd88bde4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508027039 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_smoke
.2508027039
Directory /workspace/10.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_failure.2436677305
Short name T18
Test name
Test status
Simulation time 47848745492 ps
CPU time 63.81 seconds
Started Jun 25 06:21:06 PM PDT 24
Finished Jun 25 06:22:10 PM PDT 24
Peak memory 267696 kb
Host smart-832f50c2-6f76-408a-a92c-6ce10f6197e2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436677305 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jt
ag_state_failure.2436677305
Directory /workspace/10.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_post_trans.2835874097
Short name T133
Test name
Test status
Simulation time 1220467482 ps
CPU time 11.59 seconds
Started Jun 25 06:21:06 PM PDT 24
Finished Jun 25 06:21:18 PM PDT 24
Peak memory 251260 kb
Host smart-32b2bf0c-d9ed-43da-b7f3-cf42bfd751bb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835874097 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl
_jtag_state_post_trans.2835874097
Directory /workspace/10.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_prog_failure.718911615
Short name T452
Test name
Test status
Simulation time 391448621 ps
CPU time 2.89 seconds
Started Jun 25 06:21:07 PM PDT 24
Finished Jun 25 06:21:11 PM PDT 24
Peak memory 218548 kb
Host smart-a26bd9eb-59ed-490d-939d-22a6779ae14d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718911615 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_prog_failure.718911615
Directory /workspace/10.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_mubi.3356812162
Short name T374
Test name
Test status
Simulation time 313114056 ps
CPU time 13.04 seconds
Started Jun 25 06:21:05 PM PDT 24
Finished Jun 25 06:21:19 PM PDT 24
Peak memory 226192 kb
Host smart-47e5a6bd-26ca-42c6-9f43-a9ac465f4bc4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356812162 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_mubi.3356812162
Directory /workspace/10.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_digest.1234693127
Short name T604
Test name
Test status
Simulation time 629218565 ps
CPU time 22.52 seconds
Started Jun 25 06:21:05 PM PDT 24
Finished Jun 25 06:21:27 PM PDT 24
Peak memory 218624 kb
Host smart-f5cd4e04-d2ac-42be-b1cc-b12ba3fb7845
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234693127 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_d
igest.1234693127
Directory /workspace/10.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/10.lc_ctrl_security_escalation.3929593261
Short name T827
Test name
Test status
Simulation time 742998386 ps
CPU time 11.86 seconds
Started Jun 25 06:21:05 PM PDT 24
Finished Jun 25 06:21:18 PM PDT 24
Peak memory 226184 kb
Host smart-edc7e0c6-f77f-49a0-9732-b2c7c2ed617c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929593261 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_security_escalation.3929593261
Directory /workspace/10.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/10.lc_ctrl_smoke.1956496019
Short name T630
Test name
Test status
Simulation time 133169605 ps
CPU time 2.24 seconds
Started Jun 25 06:20:56 PM PDT 24
Finished Jun 25 06:20:59 PM PDT 24
Peak memory 214608 kb
Host smart-2b252cda-79bd-4a77-834f-622a2d54cb8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956496019 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_smoke.1956496019
Directory /workspace/10.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_failure.3518113296
Short name T299
Test name
Test status
Simulation time 570361503 ps
CPU time 13.66 seconds
Started Jun 25 06:20:57 PM PDT 24
Finished Jun 25 06:21:12 PM PDT 24
Peak memory 251336 kb
Host smart-a96c7c59-b355-41d5-955a-984e2cf1f944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518113296 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_failure.3518113296
Directory /workspace/10.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_post_trans.2706365684
Short name T314
Test name
Test status
Simulation time 99152703 ps
CPU time 6.71 seconds
Started Jun 25 06:21:05 PM PDT 24
Finished Jun 25 06:21:13 PM PDT 24
Peak memory 247336 kb
Host smart-913e7c4d-99d3-485a-9d1b-38d58ba42568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706365684 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_post_trans.2706365684
Directory /workspace/10.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all.2120033367
Short name T563
Test name
Test status
Simulation time 48802764557 ps
CPU time 749.09 seconds
Started Jun 25 06:21:05 PM PDT 24
Finished Jun 25 06:33:35 PM PDT 24
Peak memory 276288 kb
Host smart-e98bcb71-17fa-4baf-8784-75f0698479dd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120033367 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.lc_ctrl_stress_all.2120033367
Directory /workspace/10.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all_with_rand_reset.523338942
Short name T176
Test name
Test status
Simulation time 40034821468 ps
CPU time 589.6 seconds
Started Jun 25 06:21:07 PM PDT 24
Finished Jun 25 06:30:57 PM PDT 24
Peak memory 300632 kb
Host smart-818b578d-060a-4058-9007-e9fea283429d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=523338942 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_stress_all_with_rand_reset.523338942
Directory /workspace/10.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.lc_ctrl_volatile_unlock_smoke.445366697
Short name T36
Test name
Test status
Simulation time 11016303 ps
CPU time 0.9 seconds
Started Jun 25 06:20:57 PM PDT 24
Finished Jun 25 06:20:59 PM PDT 24
Peak memory 209316 kb
Host smart-2578f7aa-7be2-4c5e-aec7-265d16880d7f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445366697 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ct
rl_volatile_unlock_smoke.445366697
Directory /workspace/10.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_alert_test.1809494955
Short name T284
Test name
Test status
Simulation time 47457859 ps
CPU time 0.82 seconds
Started Jun 25 06:21:21 PM PDT 24
Finished Jun 25 06:21:23 PM PDT 24
Peak memory 209456 kb
Host smart-7e026072-a335-4b53-99f5-3ffc2d1dc45b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809494955 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_alert_test.1809494955
Directory /workspace/11.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.lc_ctrl_errors.3411315500
Short name T294
Test name
Test status
Simulation time 296132735 ps
CPU time 13.59 seconds
Started Jun 25 06:21:14 PM PDT 24
Finished Jun 25 06:21:28 PM PDT 24
Peak memory 218628 kb
Host smart-88364fa2-3d1f-44f7-bd1c-a0690887ae90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411315500 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_errors.3411315500
Directory /workspace/11.lc_ctrl_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_access.602441337
Short name T25
Test name
Test status
Simulation time 925886270 ps
CPU time 2.85 seconds
Started Jun 25 06:21:16 PM PDT 24
Finished Jun 25 06:21:19 PM PDT 24
Peak memory 217432 kb
Host smart-64b63d6f-4e59-4270-a5cf-2a9f66516aff
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602441337 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_access.602441337
Directory /workspace/11.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_errors.1329282240
Short name T740
Test name
Test status
Simulation time 1987878180 ps
CPU time 30.5 seconds
Started Jun 25 06:21:12 PM PDT 24
Finished Jun 25 06:21:44 PM PDT 24
Peak memory 218568 kb
Host smart-23d03f47-a821-4cb9-a9c5-2fbfa2297b9f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329282240 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_e
rrors.1329282240
Directory /workspace/11.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_prog_failure.2534922588
Short name T730
Test name
Test status
Simulation time 4700152435 ps
CPU time 6.36 seconds
Started Jun 25 06:21:13 PM PDT 24
Finished Jun 25 06:21:20 PM PDT 24
Peak memory 218616 kb
Host smart-04cafeb8-828d-4a96-835b-4f5708a0c4fc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534922588 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jta
g_prog_failure.2534922588
Directory /workspace/11.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_smoke.2856608753
Short name T72
Test name
Test status
Simulation time 79342983 ps
CPU time 2.51 seconds
Started Jun 25 06:21:13 PM PDT 24
Finished Jun 25 06:21:16 PM PDT 24
Peak memory 217992 kb
Host smart-0b0bbf9a-cd8e-4350-9aa7-d31b126ba7e3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856608753 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_smoke
.2856608753
Directory /workspace/11.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_failure.54829234
Short name T491
Test name
Test status
Simulation time 3379574974 ps
CPU time 56.46 seconds
Started Jun 25 06:21:13 PM PDT 24
Finished Jun 25 06:22:10 PM PDT 24
Peak memory 276152 kb
Host smart-1d776ac4-cc7a-49b5-96aa-b0f97db919bd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54829234 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_s
tate_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag
_state_failure.54829234
Directory /workspace/11.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_post_trans.2488290281
Short name T350
Test name
Test status
Simulation time 758550598 ps
CPU time 20.68 seconds
Started Jun 25 06:21:15 PM PDT 24
Finished Jun 25 06:21:37 PM PDT 24
Peak memory 226616 kb
Host smart-e085a4e6-9d6e-40a1-861b-c0412687acad
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488290281 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl
_jtag_state_post_trans.2488290281
Directory /workspace/11.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_prog_failure.2430785030
Short name T678
Test name
Test status
Simulation time 204624354 ps
CPU time 4.43 seconds
Started Jun 25 06:21:14 PM PDT 24
Finished Jun 25 06:21:19 PM PDT 24
Peak memory 218616 kb
Host smart-1305497a-4045-4579-b65f-9a64f7ca98c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430785030 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_prog_failure.2430785030
Directory /workspace/11.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_mubi.3399767661
Short name T505
Test name
Test status
Simulation time 1156744522 ps
CPU time 8.52 seconds
Started Jun 25 06:21:13 PM PDT 24
Finished Jun 25 06:21:22 PM PDT 24
Peak memory 226412 kb
Host smart-ec9c4e2d-249b-4154-aabe-f91d6cc4de8c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399767661 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_mubi.3399767661
Directory /workspace/11.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_digest.2073682921
Short name T483
Test name
Test status
Simulation time 678715972 ps
CPU time 16.59 seconds
Started Jun 25 06:21:23 PM PDT 24
Finished Jun 25 06:21:40 PM PDT 24
Peak memory 218608 kb
Host smart-8ed1766f-8b01-48ac-be8a-39519c6ab9c3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073682921 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_d
igest.2073682921
Directory /workspace/11.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_mux.3310940656
Short name T645
Test name
Test status
Simulation time 547597394 ps
CPU time 9.12 seconds
Started Jun 25 06:21:22 PM PDT 24
Finished Jun 25 06:21:32 PM PDT 24
Peak memory 218588 kb
Host smart-fea7100d-dbfc-40b5-840f-8bdf4a94d8a6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310940656 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_mux.
3310940656
Directory /workspace/11.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/11.lc_ctrl_security_escalation.3750883070
Short name T642
Test name
Test status
Simulation time 1132970375 ps
CPU time 11.47 seconds
Started Jun 25 06:21:17 PM PDT 24
Finished Jun 25 06:21:29 PM PDT 24
Peak memory 225852 kb
Host smart-c6f8b5f4-db6f-44cd-a43e-ac34a2f2c01b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750883070 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_security_escalation.3750883070
Directory /workspace/11.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/11.lc_ctrl_smoke.54419845
Short name T715
Test name
Test status
Simulation time 32236470 ps
CPU time 1.02 seconds
Started Jun 25 06:21:14 PM PDT 24
Finished Jun 25 06:21:16 PM PDT 24
Peak memory 212464 kb
Host smart-ac65741c-7a94-4e99-a30c-3e76cfcc64d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54419845 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_smoke.54419845
Directory /workspace/11.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_failure.3568255411
Short name T864
Test name
Test status
Simulation time 1061675974 ps
CPU time 23.43 seconds
Started Jun 25 06:21:14 PM PDT 24
Finished Jun 25 06:21:39 PM PDT 24
Peak memory 251352 kb
Host smart-08d3b9fe-611e-42e8-95b0-9954fbe77181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568255411 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_failure.3568255411
Directory /workspace/11.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_post_trans.34071532
Short name T98
Test name
Test status
Simulation time 516385012 ps
CPU time 6.71 seconds
Started Jun 25 06:21:13 PM PDT 24
Finished Jun 25 06:21:21 PM PDT 24
Peak memory 246756 kb
Host smart-fc01df5e-b86a-48f8-900d-c4c24aff4519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34071532 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_post_trans.34071532
Directory /workspace/11.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_stress_all.2758426846
Short name T852
Test name
Test status
Simulation time 14191298118 ps
CPU time 433.05 seconds
Started Jun 25 06:21:20 PM PDT 24
Finished Jun 25 06:28:34 PM PDT 24
Peak memory 277132 kb
Host smart-ca0d9fc3-e9fa-4e3b-95b9-843d9e968b6f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758426846 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.lc_ctrl_stress_all.2758426846
Directory /workspace/11.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.lc_ctrl_stress_all_with_rand_reset.684983658
Short name T138
Test name
Test status
Simulation time 93538887108 ps
CPU time 468.37 seconds
Started Jun 25 06:21:24 PM PDT 24
Finished Jun 25 06:29:13 PM PDT 24
Peak memory 300688 kb
Host smart-4cf0a333-db32-4654-8796-f66e04e66af5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=684983658 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_stress_all_with_rand_reset.684983658
Directory /workspace/11.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.lc_ctrl_volatile_unlock_smoke.4281175543
Short name T265
Test name
Test status
Simulation time 14693307 ps
CPU time 0.82 seconds
Started Jun 25 06:21:16 PM PDT 24
Finished Jun 25 06:21:18 PM PDT 24
Peak memory 209124 kb
Host smart-2538716b-fa20-49a9-9fbb-303f597a0228
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281175543 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_c
trl_volatile_unlock_smoke.4281175543
Directory /workspace/11.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_alert_test.2624807334
Short name T854
Test name
Test status
Simulation time 85181371 ps
CPU time 0.84 seconds
Started Jun 25 06:21:29 PM PDT 24
Finished Jun 25 06:21:31 PM PDT 24
Peak memory 209204 kb
Host smart-0e985926-6b3b-40b8-a13c-9e9a3ccad61d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624807334 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_alert_test.2624807334
Directory /workspace/12.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.lc_ctrl_errors.3125030604
Short name T437
Test name
Test status
Simulation time 302961396 ps
CPU time 10.97 seconds
Started Jun 25 06:21:22 PM PDT 24
Finished Jun 25 06:21:34 PM PDT 24
Peak memory 218624 kb
Host smart-bddc4f1d-10ff-4cd5-afbd-2e94ed934dbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125030604 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_errors.3125030604
Directory /workspace/12.lc_ctrl_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_access.3201745726
Short name T716
Test name
Test status
Simulation time 969820274 ps
CPU time 9.2 seconds
Started Jun 25 06:21:32 PM PDT 24
Finished Jun 25 06:21:42 PM PDT 24
Peak memory 217472 kb
Host smart-eceabeda-25c3-4b8c-852b-975f7bbf9ac8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201745726 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_access.3201745726
Directory /workspace/12.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_errors.2090855780
Short name T249
Test name
Test status
Simulation time 5329867105 ps
CPU time 47.07 seconds
Started Jun 25 06:21:32 PM PDT 24
Finished Jun 25 06:22:20 PM PDT 24
Peak memory 219068 kb
Host smart-ffd2cfb9-ce9f-41ed-a1d2-d80f5cf08697
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090855780 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_e
rrors.2090855780
Directory /workspace/12.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_prog_failure.4014537741
Short name T328
Test name
Test status
Simulation time 8908749631 ps
CPU time 21.37 seconds
Started Jun 25 06:21:21 PM PDT 24
Finished Jun 25 06:21:43 PM PDT 24
Peak memory 218532 kb
Host smart-0a8d8a5f-d73b-40bd-a77c-334b04b2fcba
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014537741 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jta
g_prog_failure.4014537741
Directory /workspace/12.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_smoke.167835108
Short name T830
Test name
Test status
Simulation time 238419619 ps
CPU time 2.78 seconds
Started Jun 25 06:21:22 PM PDT 24
Finished Jun 25 06:21:25 PM PDT 24
Peak memory 217976 kb
Host smart-a8f892e3-91b8-406f-b320-bc3f3ece1367
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167835108 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_smoke.
167835108
Directory /workspace/12.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_failure.3443654855
Short name T376
Test name
Test status
Simulation time 1068657535 ps
CPU time 39.44 seconds
Started Jun 25 06:21:21 PM PDT 24
Finished Jun 25 06:22:01 PM PDT 24
Peak memory 267660 kb
Host smart-42ef67b0-f049-4c0a-a301-2f2b0d0ca73d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443654855 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jt
ag_state_failure.3443654855
Directory /workspace/12.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_post_trans.506369578
Short name T289
Test name
Test status
Simulation time 1004365472 ps
CPU time 14.3 seconds
Started Jun 25 06:21:20 PM PDT 24
Finished Jun 25 06:21:35 PM PDT 24
Peak memory 246916 kb
Host smart-57acb6b2-717d-4b7a-93f8-592f8d0a0206
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506369578 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_
jtag_state_post_trans.506369578
Directory /workspace/12.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_prog_failure.1573038638
Short name T496
Test name
Test status
Simulation time 210959067 ps
CPU time 2.99 seconds
Started Jun 25 06:21:22 PM PDT 24
Finished Jun 25 06:21:26 PM PDT 24
Peak memory 222648 kb
Host smart-55c71f1e-6e7a-4749-8727-3df05bb79c74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573038638 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_prog_failure.1573038638
Directory /workspace/12.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_mubi.1034053055
Short name T119
Test name
Test status
Simulation time 2121976090 ps
CPU time 13.54 seconds
Started Jun 25 06:21:32 PM PDT 24
Finished Jun 25 06:21:46 PM PDT 24
Peak memory 226456 kb
Host smart-4f25d4cd-4b58-42e6-af94-cdc3cc84d670
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034053055 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_mubi.1034053055
Directory /workspace/12.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_digest.1264254101
Short name T535
Test name
Test status
Simulation time 758621552 ps
CPU time 9.6 seconds
Started Jun 25 06:21:30 PM PDT 24
Finished Jun 25 06:21:40 PM PDT 24
Peak memory 218592 kb
Host smart-a22dcf2f-3a75-4aaa-89c7-37f9e7324f0b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264254101 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_d
igest.1264254101
Directory /workspace/12.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_mux.2647311152
Short name T433
Test name
Test status
Simulation time 294462435 ps
CPU time 10.15 seconds
Started Jun 25 06:21:30 PM PDT 24
Finished Jun 25 06:21:41 PM PDT 24
Peak memory 226404 kb
Host smart-5d17257e-5e0c-4db5-af7d-13e2541f7c3e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647311152 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_mux.
2647311152
Directory /workspace/12.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/12.lc_ctrl_smoke.3386734127
Short name T753
Test name
Test status
Simulation time 34684500 ps
CPU time 2.77 seconds
Started Jun 25 06:21:21 PM PDT 24
Finished Jun 25 06:21:24 PM PDT 24
Peak memory 224224 kb
Host smart-e071debf-905c-4717-9f74-11a5a1b598d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386734127 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_smoke.3386734127
Directory /workspace/12.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_failure.1124689733
Short name T744
Test name
Test status
Simulation time 1082880133 ps
CPU time 28.73 seconds
Started Jun 25 06:21:22 PM PDT 24
Finished Jun 25 06:21:52 PM PDT 24
Peak memory 251308 kb
Host smart-4a2dd94f-9cba-4423-870e-dd5984df2a0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124689733 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_failure.1124689733
Directory /workspace/12.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_post_trans.3154277194
Short name T826
Test name
Test status
Simulation time 219867434 ps
CPU time 6.23 seconds
Started Jun 25 06:21:21 PM PDT 24
Finished Jun 25 06:21:28 PM PDT 24
Peak memory 243152 kb
Host smart-4f7745b4-4b09-405f-ac6c-931c0f5ff836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154277194 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_post_trans.3154277194
Directory /workspace/12.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_stress_all.1329771710
Short name T378
Test name
Test status
Simulation time 10118357088 ps
CPU time 203.66 seconds
Started Jun 25 06:21:29 PM PDT 24
Finished Jun 25 06:24:54 PM PDT 24
Peak memory 284096 kb
Host smart-2eafda89-2ad6-41e8-9cbf-ff249022e97a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329771710 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.lc_ctrl_stress_all.1329771710
Directory /workspace/12.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.lc_ctrl_volatile_unlock_smoke.1735527147
Short name T353
Test name
Test status
Simulation time 26502330 ps
CPU time 1.1 seconds
Started Jun 25 06:21:22 PM PDT 24
Finished Jun 25 06:21:24 PM PDT 24
Peak memory 212212 kb
Host smart-2dfd5f58-3aa8-4dc1-8a4f-9359635e026a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735527147 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_c
trl_volatile_unlock_smoke.1735527147
Directory /workspace/12.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_alert_test.222524168
Short name T714
Test name
Test status
Simulation time 41921039 ps
CPU time 1.24 seconds
Started Jun 25 06:21:46 PM PDT 24
Finished Jun 25 06:21:48 PM PDT 24
Peak memory 209432 kb
Host smart-3098426b-3f5b-4d73-a9d6-03c0774a4719
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222524168 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_alert_test.222524168
Directory /workspace/13.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.lc_ctrl_errors.213754121
Short name T868
Test name
Test status
Simulation time 587903220 ps
CPU time 14.76 seconds
Started Jun 25 06:21:32 PM PDT 24
Finished Jun 25 06:21:48 PM PDT 24
Peak memory 218736 kb
Host smart-1a8438da-03f0-4b7b-b121-90ff210669bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213754121 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_errors.213754121
Directory /workspace/13.lc_ctrl_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_access.1336415286
Short name T821
Test name
Test status
Simulation time 1262011892 ps
CPU time 18.24 seconds
Started Jun 25 06:21:30 PM PDT 24
Finished Jun 25 06:21:49 PM PDT 24
Peak memory 217512 kb
Host smart-c7ba1b49-610f-40e5-9659-aa574fc088b8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336415286 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_access.1336415286
Directory /workspace/13.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_errors.2147236446
Short name T578
Test name
Test status
Simulation time 3145594205 ps
CPU time 74.95 seconds
Started Jun 25 06:21:31 PM PDT 24
Finished Jun 25 06:22:47 PM PDT 24
Peak memory 226440 kb
Host smart-13c48d2e-8317-4aa9-8f17-019fa0061cb0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147236446 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_e
rrors.2147236446
Directory /workspace/13.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_prog_failure.2759777325
Short name T232
Test name
Test status
Simulation time 374502919 ps
CPU time 12.03 seconds
Started Jun 25 06:21:30 PM PDT 24
Finished Jun 25 06:21:43 PM PDT 24
Peak memory 218620 kb
Host smart-27a6f85f-3dbb-4986-b521-02b786105e52
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759777325 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jta
g_prog_failure.2759777325
Directory /workspace/13.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_smoke.1537981723
Short name T468
Test name
Test status
Simulation time 547873018 ps
CPU time 6.97 seconds
Started Jun 25 06:21:30 PM PDT 24
Finished Jun 25 06:21:38 PM PDT 24
Peak memory 217984 kb
Host smart-c8d1ea76-7284-4a43-b2a0-0a9543f47bfd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537981723 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_smoke
.1537981723
Directory /workspace/13.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_failure.3099560514
Short name T264
Test name
Test status
Simulation time 1459011566 ps
CPU time 65.92 seconds
Started Jun 25 06:21:32 PM PDT 24
Finished Jun 25 06:22:39 PM PDT 24
Peak memory 284032 kb
Host smart-e3816227-7a52-4377-9283-a40b2c926042
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099560514 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jt
ag_state_failure.3099560514
Directory /workspace/13.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_post_trans.3638049684
Short name T270
Test name
Test status
Simulation time 3387049328 ps
CPU time 30.77 seconds
Started Jun 25 06:21:30 PM PDT 24
Finished Jun 25 06:22:02 PM PDT 24
Peak memory 251300 kb
Host smart-686767ba-a77d-4850-97b7-db9738ec8686
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638049684 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl
_jtag_state_post_trans.3638049684
Directory /workspace/13.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_prog_failure.4060594489
Short name T245
Test name
Test status
Simulation time 17267991 ps
CPU time 1.56 seconds
Started Jun 25 06:21:29 PM PDT 24
Finished Jun 25 06:21:32 PM PDT 24
Peak memory 222036 kb
Host smart-718d7cc1-96fa-4cc1-9af5-613a8c854b9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060594489 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_prog_failure.4060594489
Directory /workspace/13.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_mubi.1300126506
Short name T597
Test name
Test status
Simulation time 1437463470 ps
CPU time 10.57 seconds
Started Jun 25 06:21:30 PM PDT 24
Finished Jun 25 06:21:41 PM PDT 24
Peak memory 226448 kb
Host smart-0165c87f-290a-4c53-9f68-686091aa1eb8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300126506 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_mubi.1300126506
Directory /workspace/13.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_digest.192162602
Short name T523
Test name
Test status
Simulation time 1282655213 ps
CPU time 16.86 seconds
Started Jun 25 06:21:43 PM PDT 24
Finished Jun 25 06:22:00 PM PDT 24
Peak memory 218584 kb
Host smart-135ada71-2aae-4965-b16f-b372b64f8f66
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192162602 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_di
gest.192162602
Directory /workspace/13.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_mux.324012579
Short name T531
Test name
Test status
Simulation time 295196593 ps
CPU time 11.76 seconds
Started Jun 25 06:21:39 PM PDT 24
Finished Jun 25 06:21:52 PM PDT 24
Peak memory 226388 kb
Host smart-1c73a423-a3cb-4be1-b95d-a0fa63b1bafc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324012579 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_mux.324012579
Directory /workspace/13.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/13.lc_ctrl_security_escalation.1441352394
Short name T799
Test name
Test status
Simulation time 335450101 ps
CPU time 9.46 seconds
Started Jun 25 06:21:30 PM PDT 24
Finished Jun 25 06:21:40 PM PDT 24
Peak memory 226180 kb
Host smart-110cf889-4103-44f4-b221-915b70fe8ece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441352394 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_security_escalation.1441352394
Directory /workspace/13.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/13.lc_ctrl_smoke.2979578970
Short name T626
Test name
Test status
Simulation time 213605491 ps
CPU time 2.9 seconds
Started Jun 25 06:21:32 PM PDT 24
Finished Jun 25 06:21:36 PM PDT 24
Peak memory 218128 kb
Host smart-af871069-d3c3-44c1-b1c9-699f2a249fec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979578970 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_smoke.2979578970
Directory /workspace/13.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_failure.2254814971
Short name T608
Test name
Test status
Simulation time 1111451887 ps
CPU time 28.58 seconds
Started Jun 25 06:21:29 PM PDT 24
Finished Jun 25 06:21:58 PM PDT 24
Peak memory 251320 kb
Host smart-c6c4d369-9380-45d8-808c-288b0ccebf81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254814971 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_failure.2254814971
Directory /workspace/13.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_post_trans.4039387709
Short name T260
Test name
Test status
Simulation time 71986005 ps
CPU time 6.97 seconds
Started Jun 25 06:21:30 PM PDT 24
Finished Jun 25 06:21:38 PM PDT 24
Peak memory 251320 kb
Host smart-becc48a8-3766-47e6-ad34-3bfa9887e538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039387709 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_post_trans.4039387709
Directory /workspace/13.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all.122102517
Short name T209
Test name
Test status
Simulation time 1532088237 ps
CPU time 76.62 seconds
Started Jun 25 06:21:37 PM PDT 24
Finished Jun 25 06:22:54 PM PDT 24
Peak memory 251292 kb
Host smart-e96b9d2c-8251-4e0b-ac2b-a32e90356b90
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122102517 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.lc_ctrl_stress_all.122102517
Directory /workspace/13.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.lc_ctrl_volatile_unlock_smoke.1695462931
Short name T514
Test name
Test status
Simulation time 17847262 ps
CPU time 0.99 seconds
Started Jun 25 06:21:29 PM PDT 24
Finished Jun 25 06:21:31 PM PDT 24
Peak memory 209312 kb
Host smart-8c226bab-efbe-4d2a-ad40-1c042c2affb5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695462931 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_c
trl_volatile_unlock_smoke.1695462931
Directory /workspace/13.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_alert_test.3182754817
Short name T440
Test name
Test status
Simulation time 21379390 ps
CPU time 1.06 seconds
Started Jun 25 06:21:39 PM PDT 24
Finished Jun 25 06:21:41 PM PDT 24
Peak memory 209364 kb
Host smart-7bf13701-f342-40a9-a72d-787098d0bb21
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182754817 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_alert_test.3182754817
Directory /workspace/14.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_access.3546765676
Short name T848
Test name
Test status
Simulation time 1797413232 ps
CPU time 5.53 seconds
Started Jun 25 06:21:46 PM PDT 24
Finished Jun 25 06:21:53 PM PDT 24
Peak memory 217856 kb
Host smart-abba1d61-25cb-458f-9a00-ede0b5936f16
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546765676 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_access.3546765676
Directory /workspace/14.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_errors.3682089795
Short name T321
Test name
Test status
Simulation time 19967521469 ps
CPU time 85.73 seconds
Started Jun 25 06:21:40 PM PDT 24
Finished Jun 25 06:23:07 PM PDT 24
Peak memory 219280 kb
Host smart-c08b6428-17de-45db-b082-b8bec22f89c4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682089795 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_e
rrors.3682089795
Directory /workspace/14.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_prog_failure.559802321
Short name T445
Test name
Test status
Simulation time 233090597 ps
CPU time 7.29 seconds
Started Jun 25 06:21:44 PM PDT 24
Finished Jun 25 06:21:52 PM PDT 24
Peak memory 223280 kb
Host smart-7df7c294-10b0-49bd-bc15-17ca56977735
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559802321 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag
_prog_failure.559802321
Directory /workspace/14.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_smoke.984679337
Short name T572
Test name
Test status
Simulation time 347952595 ps
CPU time 2.57 seconds
Started Jun 25 06:21:42 PM PDT 24
Finished Jun 25 06:21:45 PM PDT 24
Peak memory 217976 kb
Host smart-bb61ccd6-a119-4bf7-abbc-09ccc37431e1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984679337 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_smoke.
984679337
Directory /workspace/14.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_failure.3674825132
Short name T332
Test name
Test status
Simulation time 35227105364 ps
CPU time 49.99 seconds
Started Jun 25 06:21:39 PM PDT 24
Finished Jun 25 06:22:30 PM PDT 24
Peak memory 275612 kb
Host smart-b995cd7a-0a58-48df-b79d-3740c98091a3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674825132 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jt
ag_state_failure.3674825132
Directory /workspace/14.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_post_trans.1759407402
Short name T258
Test name
Test status
Simulation time 1303509919 ps
CPU time 15.04 seconds
Started Jun 25 06:21:40 PM PDT 24
Finished Jun 25 06:21:56 PM PDT 24
Peak memory 251184 kb
Host smart-f0f9f014-c364-474e-88fe-0c73bc495b85
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759407402 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl
_jtag_state_post_trans.1759407402
Directory /workspace/14.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_prog_failure.2012982275
Short name T785
Test name
Test status
Simulation time 136981408 ps
CPU time 2.53 seconds
Started Jun 25 06:21:39 PM PDT 24
Finished Jun 25 06:21:42 PM PDT 24
Peak memory 218644 kb
Host smart-281a0cd0-731c-401f-98f2-00c46ce3cf38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012982275 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_prog_failure.2012982275
Directory /workspace/14.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_digest.1391218083
Short name T262
Test name
Test status
Simulation time 295207811 ps
CPU time 8.82 seconds
Started Jun 25 06:21:38 PM PDT 24
Finished Jun 25 06:21:47 PM PDT 24
Peak memory 218516 kb
Host smart-baf94dd9-15b9-4280-91fe-9d02378fa0cf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391218083 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_d
igest.1391218083
Directory /workspace/14.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_mux.3230517245
Short name T69
Test name
Test status
Simulation time 2843305984 ps
CPU time 9.35 seconds
Started Jun 25 06:21:39 PM PDT 24
Finished Jun 25 06:21:49 PM PDT 24
Peak memory 226448 kb
Host smart-bbd3ef32-5c23-4a64-b560-a46cb182b646
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230517245 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_mux.
3230517245
Directory /workspace/14.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/14.lc_ctrl_security_escalation.1422821379
Short name T647
Test name
Test status
Simulation time 527302710 ps
CPU time 13.91 seconds
Started Jun 25 06:21:38 PM PDT 24
Finished Jun 25 06:21:53 PM PDT 24
Peak memory 218680 kb
Host smart-882f1d99-c7a2-4426-bdf6-281003d2855c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422821379 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_security_escalation.1422821379
Directory /workspace/14.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/14.lc_ctrl_smoke.2726976517
Short name T65
Test name
Test status
Simulation time 491110659 ps
CPU time 19.09 seconds
Started Jun 25 06:21:38 PM PDT 24
Finished Jun 25 06:21:58 PM PDT 24
Peak memory 218144 kb
Host smart-081b0b7d-d1fd-46e6-8d30-5f9801650108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726976517 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_smoke.2726976517
Directory /workspace/14.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_failure.2958270174
Short name T141
Test name
Test status
Simulation time 2114101188 ps
CPU time 20.72 seconds
Started Jun 25 06:21:37 PM PDT 24
Finished Jun 25 06:21:59 PM PDT 24
Peak memory 251324 kb
Host smart-ede587bb-f33c-4cbb-bf30-dca22202a5ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958270174 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_failure.2958270174
Directory /workspace/14.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_post_trans.3849318194
Short name T275
Test name
Test status
Simulation time 185062489 ps
CPU time 7.87 seconds
Started Jun 25 06:21:46 PM PDT 24
Finished Jun 25 06:21:55 PM PDT 24
Peak memory 251316 kb
Host smart-453813ba-6cab-486c-8a55-301de456d6f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849318194 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_post_trans.3849318194
Directory /workspace/14.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_stress_all.2525324040
Short name T208
Test name
Test status
Simulation time 5185268680 ps
CPU time 47.28 seconds
Started Jun 25 06:21:46 PM PDT 24
Finished Jun 25 06:22:34 PM PDT 24
Peak memory 252404 kb
Host smart-7fc7cf5d-f293-4c5c-a5cc-ee9ec28122d6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525324040 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.lc_ctrl_stress_all.2525324040
Directory /workspace/14.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.lc_ctrl_volatile_unlock_smoke.2782990846
Short name T516
Test name
Test status
Simulation time 26206266 ps
CPU time 1.2 seconds
Started Jun 25 06:21:39 PM PDT 24
Finished Jun 25 06:21:41 PM PDT 24
Peak memory 213156 kb
Host smart-d55c8cca-43cf-41b0-b721-0310c4b7bafc
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782990846 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_c
trl_volatile_unlock_smoke.2782990846
Directory /workspace/14.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_alert_test.3761165457
Short name T661
Test name
Test status
Simulation time 21369122 ps
CPU time 1.16 seconds
Started Jun 25 06:21:55 PM PDT 24
Finished Jun 25 06:21:57 PM PDT 24
Peak memory 209356 kb
Host smart-e85e0725-23ae-4ab0-99a1-c8ccc220b5e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761165457 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_alert_test.3761165457
Directory /workspace/15.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.lc_ctrl_errors.512593390
Short name T369
Test name
Test status
Simulation time 423857103 ps
CPU time 18.08 seconds
Started Jun 25 06:21:45 PM PDT 24
Finished Jun 25 06:22:04 PM PDT 24
Peak memory 218600 kb
Host smart-8ec28cc6-13e7-4b00-863e-12566bfb7c26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512593390 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_errors.512593390
Directory /workspace/15.lc_ctrl_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_errors.3063130959
Short name T20
Test name
Test status
Simulation time 1772257405 ps
CPU time 28.54 seconds
Started Jun 25 06:21:45 PM PDT 24
Finished Jun 25 06:22:15 PM PDT 24
Peak memory 226348 kb
Host smart-24b59a53-abb3-4137-9cde-448e78b410ad
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063130959 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_e
rrors.3063130959
Directory /workspace/15.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_prog_failure.1736950805
Short name T794
Test name
Test status
Simulation time 831640012 ps
CPU time 13.36 seconds
Started Jun 25 06:21:46 PM PDT 24
Finished Jun 25 06:22:01 PM PDT 24
Peak memory 225736 kb
Host smart-0e0b8c99-3813-440f-a2a0-a3675b4022fa
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736950805 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jta
g_prog_failure.1736950805
Directory /workspace/15.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_smoke.127271630
Short name T726
Test name
Test status
Simulation time 549508668 ps
CPU time 8.2 seconds
Started Jun 25 06:21:46 PM PDT 24
Finished Jun 25 06:21:55 PM PDT 24
Peak memory 217976 kb
Host smart-088d2975-c214-4ca2-b38a-d17583f812af
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127271630 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_smoke.
127271630
Directory /workspace/15.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_failure.3395737948
Short name T140
Test name
Test status
Simulation time 1111779657 ps
CPU time 44.04 seconds
Started Jun 25 06:21:45 PM PDT 24
Finished Jun 25 06:22:30 PM PDT 24
Peak memory 251248 kb
Host smart-1f0058b9-5d0f-433e-a07f-d05e387e5e72
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395737948 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jt
ag_state_failure.3395737948
Directory /workspace/15.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_post_trans.886957423
Short name T796
Test name
Test status
Simulation time 2970114274 ps
CPU time 27.34 seconds
Started Jun 25 06:21:45 PM PDT 24
Finished Jun 25 06:22:13 PM PDT 24
Peak memory 251444 kb
Host smart-0f5c2b68-cce1-4583-adb1-9901fb54e5a9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886957423 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_
jtag_state_post_trans.886957423
Directory /workspace/15.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_prog_failure.2257341025
Short name T236
Test name
Test status
Simulation time 352239532 ps
CPU time 2.82 seconds
Started Jun 25 06:21:45 PM PDT 24
Finished Jun 25 06:21:49 PM PDT 24
Peak memory 222900 kb
Host smart-b67bca5d-583a-4fe6-a159-7d2c4c990ff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257341025 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_prog_failure.2257341025
Directory /workspace/15.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_mubi.2622702393
Short name T698
Test name
Test status
Simulation time 1305953608 ps
CPU time 12.68 seconds
Started Jun 25 06:21:46 PM PDT 24
Finished Jun 25 06:22:00 PM PDT 24
Peak memory 219268 kb
Host smart-85b7d119-1060-4918-a13f-21e7b6c5b4d5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622702393 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_mubi.2622702393
Directory /workspace/15.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_digest.3569351047
Short name T853
Test name
Test status
Simulation time 297713979 ps
CPU time 11.61 seconds
Started Jun 25 06:21:46 PM PDT 24
Finished Jun 25 06:21:58 PM PDT 24
Peak memory 218672 kb
Host smart-143c93d5-21ae-4d60-8c45-633609e00f5a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569351047 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_d
igest.3569351047
Directory /workspace/15.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_mux.3475182633
Short name T603
Test name
Test status
Simulation time 280250557 ps
CPU time 10.94 seconds
Started Jun 25 06:21:53 PM PDT 24
Finished Jun 25 06:22:04 PM PDT 24
Peak memory 218584 kb
Host smart-1b894f17-1fb8-442e-86a6-e04678d533ae
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475182633 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_mux.
3475182633
Directory /workspace/15.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/15.lc_ctrl_security_escalation.2129681921
Short name T808
Test name
Test status
Simulation time 1339302498 ps
CPU time 12.99 seconds
Started Jun 25 06:21:45 PM PDT 24
Finished Jun 25 06:21:59 PM PDT 24
Peak memory 218764 kb
Host smart-01ff9231-bf1f-49dd-b43b-86ffad4798b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129681921 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_security_escalation.2129681921
Directory /workspace/15.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/15.lc_ctrl_smoke.1171810442
Short name T82
Test name
Test status
Simulation time 172104525 ps
CPU time 2.24 seconds
Started Jun 25 06:21:43 PM PDT 24
Finished Jun 25 06:21:46 PM PDT 24
Peak memory 214496 kb
Host smart-37baa8dd-70ec-4899-b5b6-c0b673d3d5b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171810442 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_smoke.1171810442
Directory /workspace/15.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_failure.1131442806
Short name T387
Test name
Test status
Simulation time 140465703 ps
CPU time 17.23 seconds
Started Jun 25 06:21:40 PM PDT 24
Finished Jun 25 06:21:58 PM PDT 24
Peak memory 251416 kb
Host smart-ccb1eaf9-c6da-44e8-a252-41bbd27cd975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1131442806 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_failure.1131442806
Directory /workspace/15.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_post_trans.20514206
Short name T329
Test name
Test status
Simulation time 203545960 ps
CPU time 7.31 seconds
Started Jun 25 06:21:39 PM PDT 24
Finished Jun 25 06:21:47 PM PDT 24
Peak memory 247680 kb
Host smart-37b8297f-53c9-4a77-ba8c-aafff559befb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20514206 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_post_trans.20514206
Directory /workspace/15.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all.1987945848
Short name T540
Test name
Test status
Simulation time 14075438598 ps
CPU time 222.38 seconds
Started Jun 25 06:21:54 PM PDT 24
Finished Jun 25 06:25:37 PM PDT 24
Peak memory 251368 kb
Host smart-304aaa37-fa5e-4377-81c6-58c370f7e4e1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987945848 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.lc_ctrl_stress_all.1987945848
Directory /workspace/15.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all_with_rand_reset.1971830334
Short name T21
Test name
Test status
Simulation time 35691010828 ps
CPU time 1306.73 seconds
Started Jun 25 06:21:54 PM PDT 24
Finished Jun 25 06:43:41 PM PDT 24
Peak memory 525180 kb
Host smart-50d5f6e7-55be-4c61-9a95-d7b1a1d599be
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1971830334 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_stress_all_with_rand_reset.1971830334
Directory /workspace/15.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.lc_ctrl_volatile_unlock_smoke.2607615384
Short name T598
Test name
Test status
Simulation time 50616414 ps
CPU time 1.02 seconds
Started Jun 25 06:21:38 PM PDT 24
Finished Jun 25 06:21:40 PM PDT 24
Peak memory 212200 kb
Host smart-5d7c37bb-40eb-428e-bcec-51ea0f2355a6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607615384 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_c
trl_volatile_unlock_smoke.2607615384
Directory /workspace/15.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_alert_test.2226574195
Short name T248
Test name
Test status
Simulation time 33261557 ps
CPU time 1.06 seconds
Started Jun 25 06:22:04 PM PDT 24
Finished Jun 25 06:22:07 PM PDT 24
Peak memory 209300 kb
Host smart-d25dff99-37b5-46c0-869e-c51ab5a671bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226574195 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_alert_test.2226574195
Directory /workspace/16.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.lc_ctrl_errors.338459430
Short name T419
Test name
Test status
Simulation time 573893958 ps
CPU time 13.9 seconds
Started Jun 25 06:21:56 PM PDT 24
Finished Jun 25 06:22:11 PM PDT 24
Peak memory 218636 kb
Host smart-b9ab369d-a212-43f2-a991-cf2d066ee9d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338459430 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_errors.338459430
Directory /workspace/16.lc_ctrl_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_access.2982423637
Short name T664
Test name
Test status
Simulation time 267176066 ps
CPU time 7.63 seconds
Started Jun 25 06:21:56 PM PDT 24
Finished Jun 25 06:22:04 PM PDT 24
Peak memory 217700 kb
Host smart-27548384-3b15-4618-b83f-eb0a9b7bf8eb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982423637 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_access.2982423637
Directory /workspace/16.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_errors.3071137683
Short name T503
Test name
Test status
Simulation time 6795256726 ps
CPU time 32.42 seconds
Started Jun 25 06:22:00 PM PDT 24
Finished Jun 25 06:22:33 PM PDT 24
Peak memory 226424 kb
Host smart-71996f44-3549-4d1c-a028-5ca70510637e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071137683 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_e
rrors.3071137683
Directory /workspace/16.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_prog_failure.3171591904
Short name T600
Test name
Test status
Simulation time 926588103 ps
CPU time 13.51 seconds
Started Jun 25 06:21:54 PM PDT 24
Finished Jun 25 06:22:09 PM PDT 24
Peak memory 218552 kb
Host smart-c648d2c7-2a0f-4096-bae7-89934723d72f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171591904 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jta
g_prog_failure.3171591904
Directory /workspace/16.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_smoke.470667776
Short name T575
Test name
Test status
Simulation time 1961639754 ps
CPU time 6.9 seconds
Started Jun 25 06:22:00 PM PDT 24
Finished Jun 25 06:22:07 PM PDT 24
Peak memory 217972 kb
Host smart-9fb6e37e-ea64-4258-b531-43d340ff4fb8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470667776 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_smoke.
470667776
Directory /workspace/16.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_failure.717182175
Short name T394
Test name
Test status
Simulation time 4218154668 ps
CPU time 64.82 seconds
Started Jun 25 06:21:54 PM PDT 24
Finished Jun 25 06:23:00 PM PDT 24
Peak memory 268180 kb
Host smart-621dd30f-251e-4e9d-9dda-b2763b3a6e7f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717182175 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jta
g_state_failure.717182175
Directory /workspace/16.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_post_trans.1098757009
Short name T442
Test name
Test status
Simulation time 1443311993 ps
CPU time 26.27 seconds
Started Jun 25 06:21:53 PM PDT 24
Finished Jun 25 06:22:20 PM PDT 24
Peak memory 251272 kb
Host smart-f13ab549-d396-45f5-86c8-3d2bcf09ae76
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098757009 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl
_jtag_state_post_trans.1098757009
Directory /workspace/16.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_prog_failure.1742132309
Short name T466
Test name
Test status
Simulation time 75821318 ps
CPU time 4.17 seconds
Started Jun 25 06:21:54 PM PDT 24
Finished Jun 25 06:21:59 PM PDT 24
Peak memory 218540 kb
Host smart-20fc6420-edd9-4332-9707-a00315ad00c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742132309 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_prog_failure.1742132309
Directory /workspace/16.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_mubi.1703193164
Short name T362
Test name
Test status
Simulation time 966862819 ps
CPU time 15.16 seconds
Started Jun 25 06:21:54 PM PDT 24
Finished Jun 25 06:22:10 PM PDT 24
Peak memory 226440 kb
Host smart-3e731697-08c3-4024-a0c4-04c36861c0cd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703193164 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_mubi.1703193164
Directory /workspace/16.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_digest.2764463567
Short name T40
Test name
Test status
Simulation time 665528281 ps
CPU time 15.73 seconds
Started Jun 25 06:21:54 PM PDT 24
Finished Jun 25 06:22:11 PM PDT 24
Peak memory 218540 kb
Host smart-c54b72c2-2b98-4c32-8ed3-9fc24fce9a63
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764463567 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_d
igest.2764463567
Directory /workspace/16.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_mux.256953143
Short name T132
Test name
Test status
Simulation time 213049324 ps
CPU time 7.79 seconds
Started Jun 25 06:22:00 PM PDT 24
Finished Jun 25 06:22:08 PM PDT 24
Peak memory 218572 kb
Host smart-b8a14063-5adc-4f8a-9bc1-f4de4a0cdbcf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256953143 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_mux.256953143
Directory /workspace/16.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/16.lc_ctrl_security_escalation.2816361092
Short name T633
Test name
Test status
Simulation time 282744420 ps
CPU time 12.04 seconds
Started Jun 25 06:21:54 PM PDT 24
Finished Jun 25 06:22:07 PM PDT 24
Peak memory 226232 kb
Host smart-5d361067-fc55-4c82-9101-6b24c631f027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816361092 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_security_escalation.2816361092
Directory /workspace/16.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/16.lc_ctrl_smoke.4110583230
Short name T418
Test name
Test status
Simulation time 23642188 ps
CPU time 1.93 seconds
Started Jun 25 06:21:55 PM PDT 24
Finished Jun 25 06:21:58 PM PDT 24
Peak memory 214304 kb
Host smart-e6b83845-f1b1-4326-b7af-5ee3a1416d23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110583230 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_smoke.4110583230
Directory /workspace/16.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_failure.1291655875
Short name T428
Test name
Test status
Simulation time 1052047825 ps
CPU time 20.63 seconds
Started Jun 25 06:21:59 PM PDT 24
Finished Jun 25 06:22:21 PM PDT 24
Peak memory 251320 kb
Host smart-0ec34d35-08d7-4efb-8caf-aff36983b01f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291655875 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_failure.1291655875
Directory /workspace/16.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_post_trans.2269590050
Short name T743
Test name
Test status
Simulation time 302678404 ps
CPU time 8.96 seconds
Started Jun 25 06:21:54 PM PDT 24
Finished Jun 25 06:22:04 PM PDT 24
Peak memory 251244 kb
Host smart-410c1f20-f9d6-4eff-a923-ec094d5872ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269590050 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_post_trans.2269590050
Directory /workspace/16.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_stress_all.862976976
Short name T621
Test name
Test status
Simulation time 8327500293 ps
CPU time 148.27 seconds
Started Jun 25 06:21:53 PM PDT 24
Finished Jun 25 06:24:22 PM PDT 24
Peak memory 269508 kb
Host smart-6165cbba-08e5-4d6e-83ff-d51af5b22a4d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862976976 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.lc_ctrl_stress_all.862976976
Directory /workspace/16.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.lc_ctrl_volatile_unlock_smoke.4193041790
Short name T840
Test name
Test status
Simulation time 14754462 ps
CPU time 0.81 seconds
Started Jun 25 06:21:53 PM PDT 24
Finished Jun 25 06:21:55 PM PDT 24
Peak memory 209212 kb
Host smart-a144039a-0756-4d45-a4a9-8facfea0fc49
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193041790 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_c
trl_volatile_unlock_smoke.4193041790
Directory /workspace/16.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_alert_test.4090273891
Short name T793
Test name
Test status
Simulation time 77447738 ps
CPU time 1.03 seconds
Started Jun 25 06:22:14 PM PDT 24
Finished Jun 25 06:22:16 PM PDT 24
Peak memory 209268 kb
Host smart-1fd1a29a-4ba6-4357-9039-e3c88143cd41
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090273891 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_alert_test.4090273891
Directory /workspace/17.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.lc_ctrl_errors.1430569704
Short name T631
Test name
Test status
Simulation time 4747190988 ps
CPU time 9.87 seconds
Started Jun 25 06:22:07 PM PDT 24
Finished Jun 25 06:22:17 PM PDT 24
Peak memory 226476 kb
Host smart-bb673c4a-0a60-4177-95fb-ddc871bbbc45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430569704 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_errors.1430569704
Directory /workspace/17.lc_ctrl_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_access.3240717845
Short name T638
Test name
Test status
Simulation time 1423071502 ps
CPU time 5.07 seconds
Started Jun 25 06:22:05 PM PDT 24
Finished Jun 25 06:22:11 PM PDT 24
Peak memory 217760 kb
Host smart-381b7a08-2d31-44f6-bb9e-a25e91bcacf8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240717845 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_access.3240717845
Directory /workspace/17.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_errors.1367475800
Short name T470
Test name
Test status
Simulation time 18326069280 ps
CPU time 29.67 seconds
Started Jun 25 06:22:06 PM PDT 24
Finished Jun 25 06:22:37 PM PDT 24
Peak memory 219248 kb
Host smart-0d84eb19-6b38-48f0-891e-5b17827b8d25
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367475800 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_e
rrors.1367475800
Directory /workspace/17.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_prog_failure.3969697758
Short name T450
Test name
Test status
Simulation time 1389975716 ps
CPU time 5.43 seconds
Started Jun 25 06:22:04 PM PDT 24
Finished Jun 25 06:22:11 PM PDT 24
Peak memory 218480 kb
Host smart-16576927-1fa9-41b9-93ba-38bc1725ed22
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969697758 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jta
g_prog_failure.3969697758
Directory /workspace/17.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_smoke.2246753324
Short name T649
Test name
Test status
Simulation time 429742490 ps
CPU time 2.54 seconds
Started Jun 25 06:22:04 PM PDT 24
Finished Jun 25 06:22:07 PM PDT 24
Peak memory 217980 kb
Host smart-ccf3c94a-5758-4f24-aca0-f5cd17f7463d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246753324 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_smoke
.2246753324
Directory /workspace/17.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_failure.393451181
Short name T517
Test name
Test status
Simulation time 1954903014 ps
CPU time 55.57 seconds
Started Jun 25 06:22:04 PM PDT 24
Finished Jun 25 06:23:01 PM PDT 24
Peak memory 267660 kb
Host smart-34f50660-1819-49d5-a3c7-c6b13b3ed8df
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393451181 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jta
g_state_failure.393451181
Directory /workspace/17.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_post_trans.2627413388
Short name T493
Test name
Test status
Simulation time 728753914 ps
CPU time 8.16 seconds
Started Jun 25 06:22:05 PM PDT 24
Finished Jun 25 06:22:14 PM PDT 24
Peak memory 226592 kb
Host smart-b538e389-1589-4b5e-90c1-06f471eb9916
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627413388 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl
_jtag_state_post_trans.2627413388
Directory /workspace/17.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_prog_failure.3941130903
Short name T528
Test name
Test status
Simulation time 76066277 ps
CPU time 2.12 seconds
Started Jun 25 06:22:04 PM PDT 24
Finished Jun 25 06:22:08 PM PDT 24
Peak memory 218776 kb
Host smart-274f7cdd-5249-4858-aa19-afda4e7d24ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941130903 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_prog_failure.3941130903
Directory /workspace/17.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_mubi.35992469
Short name T112
Test name
Test status
Simulation time 274619367 ps
CPU time 8.32 seconds
Started Jun 25 06:22:04 PM PDT 24
Finished Jun 25 06:22:13 PM PDT 24
Peak memory 226436 kb
Host smart-a8ae6036-10a0-48f4-b216-b45fd949684f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35992469 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_mubi.35992469
Directory /workspace/17.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_digest.2942283772
Short name T596
Test name
Test status
Simulation time 365894864 ps
CPU time 15.65 seconds
Started Jun 25 06:22:04 PM PDT 24
Finished Jun 25 06:22:21 PM PDT 24
Peak memory 218596 kb
Host smart-7049541b-17b9-4a54-80b2-65120c89967c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942283772 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_d
igest.2942283772
Directory /workspace/17.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_mux.4205739370
Short name T625
Test name
Test status
Simulation time 303479737 ps
CPU time 12.3 seconds
Started Jun 25 06:22:05 PM PDT 24
Finished Jun 25 06:22:18 PM PDT 24
Peak memory 218596 kb
Host smart-1d07d326-3dad-49c9-8bb9-78de9a21a76e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205739370 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_mux.
4205739370
Directory /workspace/17.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/17.lc_ctrl_security_escalation.1448853599
Short name T857
Test name
Test status
Simulation time 669801381 ps
CPU time 9.06 seconds
Started Jun 25 06:22:05 PM PDT 24
Finished Jun 25 06:22:15 PM PDT 24
Peak memory 224948 kb
Host smart-ea0297be-6dd0-452f-9b06-52522889961f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448853599 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_security_escalation.1448853599
Directory /workspace/17.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/17.lc_ctrl_smoke.3454407583
Short name T713
Test name
Test status
Simulation time 177687586 ps
CPU time 2.24 seconds
Started Jun 25 06:22:04 PM PDT 24
Finished Jun 25 06:22:08 PM PDT 24
Peak memory 224240 kb
Host smart-8a8ce906-3c29-4430-8370-fd498d77e585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454407583 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_smoke.3454407583
Directory /workspace/17.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_failure.3944726330
Short name T366
Test name
Test status
Simulation time 242645274 ps
CPU time 22.99 seconds
Started Jun 25 06:22:05 PM PDT 24
Finished Jun 25 06:22:29 PM PDT 24
Peak memory 251328 kb
Host smart-e253fe9e-b188-48bf-b728-7724322a7bc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944726330 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_failure.3944726330
Directory /workspace/17.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_post_trans.1404520698
Short name T402
Test name
Test status
Simulation time 173210936 ps
CPU time 2.35 seconds
Started Jun 25 06:22:04 PM PDT 24
Finished Jun 25 06:22:07 PM PDT 24
Peak memory 218644 kb
Host smart-54bba4ca-9b18-4ecc-a10e-e1e2c5102678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404520698 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_post_trans.1404520698
Directory /workspace/17.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all.696871722
Short name T474
Test name
Test status
Simulation time 710331948 ps
CPU time 43.78 seconds
Started Jun 25 06:22:04 PM PDT 24
Finished Jun 25 06:22:48 PM PDT 24
Peak memory 251316 kb
Host smart-cbd71e60-a5ff-462e-a036-9cbde7fc89da
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696871722 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.lc_ctrl_stress_all.696871722
Directory /workspace/17.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.lc_ctrl_volatile_unlock_smoke.1244718621
Short name T35
Test name
Test status
Simulation time 16128949 ps
CPU time 1.23 seconds
Started Jun 25 06:22:06 PM PDT 24
Finished Jun 25 06:22:08 PM PDT 24
Peak memory 212244 kb
Host smart-aee53e43-0354-4f68-8e57-9bd4a9145f34
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244718621 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_c
trl_volatile_unlock_smoke.1244718621
Directory /workspace/17.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_alert_test.1577296777
Short name T750
Test name
Test status
Simulation time 233319845 ps
CPU time 1.1 seconds
Started Jun 25 06:22:20 PM PDT 24
Finished Jun 25 06:22:22 PM PDT 24
Peak memory 209464 kb
Host smart-b96cfdaf-3e32-433b-896c-7895fc48b356
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577296777 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_alert_test.1577296777
Directory /workspace/18.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.lc_ctrl_errors.3767325884
Short name T359
Test name
Test status
Simulation time 1696487500 ps
CPU time 10.05 seconds
Started Jun 25 06:22:13 PM PDT 24
Finished Jun 25 06:22:24 PM PDT 24
Peak memory 226384 kb
Host smart-290a2c67-4507-4bad-8885-5e3f402bb8b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767325884 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_errors.3767325884
Directory /workspace/18.lc_ctrl_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_access.4217395618
Short name T424
Test name
Test status
Simulation time 2173584447 ps
CPU time 3.35 seconds
Started Jun 25 06:22:14 PM PDT 24
Finished Jun 25 06:22:18 PM PDT 24
Peak memory 217664 kb
Host smart-1365d7c6-bd25-4b97-b844-2d547f152e22
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217395618 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_access.4217395618
Directory /workspace/18.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_errors.1011532362
Short name T250
Test name
Test status
Simulation time 11344230739 ps
CPU time 60.39 seconds
Started Jun 25 06:22:15 PM PDT 24
Finished Jun 25 06:23:16 PM PDT 24
Peak memory 219156 kb
Host smart-58a4a6ad-d7c2-4c2d-8bbc-ebadcfe3188a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011532362 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_e
rrors.1011532362
Directory /workspace/18.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_prog_failure.2834877236
Short name T605
Test name
Test status
Simulation time 1376999018 ps
CPU time 10.98 seconds
Started Jun 25 06:22:13 PM PDT 24
Finished Jun 25 06:22:24 PM PDT 24
Peak memory 223476 kb
Host smart-498da0be-c8af-44be-9c57-507efd53fbf4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834877236 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jta
g_prog_failure.2834877236
Directory /workspace/18.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_smoke.3377863792
Short name T304
Test name
Test status
Simulation time 1248081067 ps
CPU time 9.15 seconds
Started Jun 25 06:22:16 PM PDT 24
Finished Jun 25 06:22:26 PM PDT 24
Peak memory 217968 kb
Host smart-5d22e4b6-5c31-460c-b16f-0301d68d00d2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377863792 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_smoke
.3377863792
Directory /workspace/18.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_failure.4131256799
Short name T612
Test name
Test status
Simulation time 2187273568 ps
CPU time 88.38 seconds
Started Jun 25 06:22:14 PM PDT 24
Finished Jun 25 06:23:43 PM PDT 24
Peak memory 279668 kb
Host smart-9786bf61-0d68-4556-bed0-f5fc86c39ebc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131256799 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jt
ag_state_failure.4131256799
Directory /workspace/18.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_post_trans.311199851
Short name T293
Test name
Test status
Simulation time 1630132095 ps
CPU time 12.9 seconds
Started Jun 25 06:22:14 PM PDT 24
Finished Jun 25 06:22:28 PM PDT 24
Peak memory 245648 kb
Host smart-29aba780-3c80-456b-a526-4edaff60e52a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311199851 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_
jtag_state_post_trans.311199851
Directory /workspace/18.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_prog_failure.2012107227
Short name T358
Test name
Test status
Simulation time 50381518 ps
CPU time 1.77 seconds
Started Jun 25 06:22:14 PM PDT 24
Finished Jun 25 06:22:17 PM PDT 24
Peak memory 218692 kb
Host smart-364e7531-ba1b-4808-8100-e855d99733d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012107227 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_prog_failure.2012107227
Directory /workspace/18.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_mubi.247015657
Short name T331
Test name
Test status
Simulation time 369246682 ps
CPU time 15.32 seconds
Started Jun 25 06:22:18 PM PDT 24
Finished Jun 25 06:22:34 PM PDT 24
Peak memory 226444 kb
Host smart-5095e511-c56f-4d0f-a362-f71ab5b1db92
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247015657 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_mubi.247015657
Directory /workspace/18.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_digest.415407645
Short name T788
Test name
Test status
Simulation time 316233854 ps
CPU time 12.12 seconds
Started Jun 25 06:22:13 PM PDT 24
Finished Jun 25 06:22:26 PM PDT 24
Peak memory 218660 kb
Host smart-9e28e5ae-0a4d-4d64-b1c7-b88cfda03d54
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415407645 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_di
gest.415407645
Directory /workspace/18.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_mux.2465598051
Short name T341
Test name
Test status
Simulation time 245733392 ps
CPU time 9.55 seconds
Started Jun 25 06:22:15 PM PDT 24
Finished Jun 25 06:22:25 PM PDT 24
Peak memory 226368 kb
Host smart-b7c6e41b-90ac-4d70-96ce-6029f8bbef02
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465598051 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_mux.
2465598051
Directory /workspace/18.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/18.lc_ctrl_security_escalation.1188809538
Short name T109
Test name
Test status
Simulation time 542596494 ps
CPU time 8.4 seconds
Started Jun 25 06:22:17 PM PDT 24
Finished Jun 25 06:22:26 PM PDT 24
Peak memory 218676 kb
Host smart-6deaf344-3972-4f8e-808e-5470fb230bfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188809538 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_security_escalation.1188809538
Directory /workspace/18.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/18.lc_ctrl_smoke.3561306828
Short name T338
Test name
Test status
Simulation time 36388420 ps
CPU time 1.19 seconds
Started Jun 25 06:22:14 PM PDT 24
Finished Jun 25 06:22:16 PM PDT 24
Peak memory 218032 kb
Host smart-9a28353a-254f-480d-a60c-ab63d0455326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561306828 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_smoke.3561306828
Directory /workspace/18.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_failure.3147055550
Short name T742
Test name
Test status
Simulation time 239889897 ps
CPU time 22.31 seconds
Started Jun 25 06:22:14 PM PDT 24
Finished Jun 25 06:22:38 PM PDT 24
Peak memory 251348 kb
Host smart-3ef2c262-dbaf-4758-95bc-04bed260e527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147055550 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_failure.3147055550
Directory /workspace/18.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all.33094363
Short name T727
Test name
Test status
Simulation time 49993371634 ps
CPU time 104.18 seconds
Started Jun 25 06:22:14 PM PDT 24
Finished Jun 25 06:23:59 PM PDT 24
Peak memory 269972 kb
Host smart-7ffa701a-f8ef-42a2-9f59-1bf027f632bd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33094363 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_T
EST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
8.lc_ctrl_stress_all.33094363
Directory /workspace/18.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.lc_ctrl_volatile_unlock_smoke.2753334623
Short name T45
Test name
Test status
Simulation time 26971756 ps
CPU time 0.92 seconds
Started Jun 25 06:22:14 PM PDT 24
Finished Jun 25 06:22:16 PM PDT 24
Peak memory 212260 kb
Host smart-4b957f25-1ea9-44c7-803a-d72788507d7f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753334623 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_c
trl_volatile_unlock_smoke.2753334623
Directory /workspace/18.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_alert_test.1883208747
Short name T130
Test name
Test status
Simulation time 37002692 ps
CPU time 1.43 seconds
Started Jun 25 06:22:25 PM PDT 24
Finished Jun 25 06:22:27 PM PDT 24
Peak memory 209340 kb
Host smart-d92d1c4b-ed55-4403-88fa-5d78fe0cd245
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883208747 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_alert_test.1883208747
Directory /workspace/19.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.lc_ctrl_errors.2532049924
Short name T48
Test name
Test status
Simulation time 248892067 ps
CPU time 10.65 seconds
Started Jun 25 06:22:21 PM PDT 24
Finished Jun 25 06:22:32 PM PDT 24
Peak memory 218724 kb
Host smart-cf05f910-b727-4ffb-944c-5e92f800c6be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532049924 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_errors.2532049924
Directory /workspace/19.lc_ctrl_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_access.143745069
Short name T24
Test name
Test status
Simulation time 555418626 ps
CPU time 3.2 seconds
Started Jun 25 06:22:23 PM PDT 24
Finished Jun 25 06:22:27 PM PDT 24
Peak memory 217444 kb
Host smart-95b53e0b-4d96-4a37-a33a-52e6c5a5814e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143745069 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_access.143745069
Directory /workspace/19.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_errors.1491656086
Short name T806
Test name
Test status
Simulation time 2741162692 ps
CPU time 31.44 seconds
Started Jun 25 06:22:23 PM PDT 24
Finished Jun 25 06:22:55 PM PDT 24
Peak memory 219276 kb
Host smart-39c07709-ed5c-4eba-a042-0cf52c1e8700
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491656086 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_e
rrors.1491656086
Directory /workspace/19.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_prog_failure.4216495848
Short name T613
Test name
Test status
Simulation time 298351762 ps
CPU time 3.15 seconds
Started Jun 25 06:22:24 PM PDT 24
Finished Jun 25 06:22:28 PM PDT 24
Peak memory 218552 kb
Host smart-1983f4d6-333b-49c8-8cde-fe9109cba163
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216495848 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jta
g_prog_failure.4216495848
Directory /workspace/19.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_smoke.1335561908
Short name T88
Test name
Test status
Simulation time 304191568 ps
CPU time 4.84 seconds
Started Jun 25 06:22:22 PM PDT 24
Finished Jun 25 06:22:28 PM PDT 24
Peak memory 217988 kb
Host smart-74c97759-5f7d-4140-92f4-e828bc022552
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335561908 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_smoke
.1335561908
Directory /workspace/19.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_failure.2893558361
Short name T763
Test name
Test status
Simulation time 1714969135 ps
CPU time 41.46 seconds
Started Jun 25 06:22:22 PM PDT 24
Finished Jun 25 06:23:05 PM PDT 24
Peak memory 276380 kb
Host smart-445ed24f-c003-44aa-b8dc-c455aaabb16d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893558361 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jt
ag_state_failure.2893558361
Directory /workspace/19.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_post_trans.2320952372
Short name T691
Test name
Test status
Simulation time 851427671 ps
CPU time 8.5 seconds
Started Jun 25 06:22:22 PM PDT 24
Finished Jun 25 06:22:32 PM PDT 24
Peak memory 226656 kb
Host smart-87506008-2827-4f8b-a013-e062b4b75b37
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320952372 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl
_jtag_state_post_trans.2320952372
Directory /workspace/19.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_prog_failure.1170531608
Short name T302
Test name
Test status
Simulation time 177534852 ps
CPU time 6.86 seconds
Started Jun 25 06:22:22 PM PDT 24
Finished Jun 25 06:22:29 PM PDT 24
Peak memory 223272 kb
Host smart-d3609484-91db-4a35-9931-a0c4e817d8a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170531608 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_prog_failure.1170531608
Directory /workspace/19.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_mubi.1134256665
Short name T456
Test name
Test status
Simulation time 8392754945 ps
CPU time 14.92 seconds
Started Jun 25 06:22:22 PM PDT 24
Finished Jun 25 06:22:38 PM PDT 24
Peak memory 219444 kb
Host smart-ffac3149-b36b-464f-97cb-88d27a70823a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134256665 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_mubi.1134256665
Directory /workspace/19.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_digest.2632299579
Short name T663
Test name
Test status
Simulation time 2358132149 ps
CPU time 23.64 seconds
Started Jun 25 06:22:23 PM PDT 24
Finished Jun 25 06:22:47 PM PDT 24
Peak memory 219284 kb
Host smart-002aed0a-91d9-43b1-bf13-ed2e901ed1d1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632299579 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_d
igest.2632299579
Directory /workspace/19.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_mux.1711023633
Short name T546
Test name
Test status
Simulation time 1399058683 ps
CPU time 14.01 seconds
Started Jun 25 06:22:23 PM PDT 24
Finished Jun 25 06:22:38 PM PDT 24
Peak memory 226372 kb
Host smart-21da4bc7-824c-4f17-9ed2-0b1a1c980022
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711023633 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_mux.
1711023633
Directory /workspace/19.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/19.lc_ctrl_security_escalation.1144225890
Short name T601
Test name
Test status
Simulation time 278544476 ps
CPU time 8.03 seconds
Started Jun 25 06:22:22 PM PDT 24
Finished Jun 25 06:22:31 PM PDT 24
Peak memory 225648 kb
Host smart-9ca0d5f4-de1e-411f-8c2c-5ca66ced2d9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144225890 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_security_escalation.1144225890
Directory /workspace/19.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/19.lc_ctrl_smoke.1799769139
Short name T748
Test name
Test status
Simulation time 47551122 ps
CPU time 2.28 seconds
Started Jun 25 06:22:25 PM PDT 24
Finished Jun 25 06:22:28 PM PDT 24
Peak memory 214740 kb
Host smart-972ad6bf-e805-4304-b705-a805e43df55c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799769139 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_smoke.1799769139
Directory /workspace/19.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_failure.3486871969
Short name T303
Test name
Test status
Simulation time 223406844 ps
CPU time 24.01 seconds
Started Jun 25 06:22:25 PM PDT 24
Finished Jun 25 06:22:50 PM PDT 24
Peak memory 251320 kb
Host smart-0d80f9aa-91fc-4aeb-b3bc-561ca03783de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486871969 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_failure.3486871969
Directory /workspace/19.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all.1181212154
Short name T195
Test name
Test status
Simulation time 7314188878 ps
CPU time 39.75 seconds
Started Jun 25 06:22:21 PM PDT 24
Finished Jun 25 06:23:01 PM PDT 24
Peak memory 247312 kb
Host smart-d6418c45-89fe-4bde-8b2b-c03fab6694fa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181212154 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.lc_ctrl_stress_all.1181212154
Directory /workspace/19.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all_with_rand_reset.3996109670
Short name T177
Test name
Test status
Simulation time 85594776708 ps
CPU time 291.74 seconds
Started Jun 25 06:22:22 PM PDT 24
Finished Jun 25 06:27:15 PM PDT 24
Peak memory 267860 kb
Host smart-84d379b1-f600-4aae-a3f3-cb65270e7127
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3996109670 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_stress_all_with_rand_reset.3996109670
Directory /workspace/19.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.lc_ctrl_alert_test.3886952332
Short name T586
Test name
Test status
Simulation time 58577888 ps
CPU time 1.08 seconds
Started Jun 25 06:19:26 PM PDT 24
Finished Jun 25 06:19:28 PM PDT 24
Peak memory 209332 kb
Host smart-2d549e70-6770-4c8d-99a8-38b06400283e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886952332 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_alert_test.3886952332
Directory /workspace/2.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.lc_ctrl_claim_transition_if.3499900069
Short name T83
Test name
Test status
Simulation time 10779105 ps
CPU time 0.97 seconds
Started Jun 25 06:19:17 PM PDT 24
Finished Jun 25 06:19:20 PM PDT 24
Peak memory 209368 kb
Host smart-1a4ff9a0-e124-4d28-969f-195d78412ab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499900069 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_claim_transition_if.3499900069
Directory /workspace/2.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/2.lc_ctrl_errors.2783612139
Short name T309
Test name
Test status
Simulation time 537407828 ps
CPU time 15.23 seconds
Started Jun 25 06:19:11 PM PDT 24
Finished Jun 25 06:19:27 PM PDT 24
Peak memory 218576 kb
Host smart-25e2d99d-0b8f-4571-b896-49d7800c2485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783612139 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_errors.2783612139
Directory /workspace/2.lc_ctrl_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_access.1823155765
Short name T617
Test name
Test status
Simulation time 1127168640 ps
CPU time 4.35 seconds
Started Jun 25 06:19:20 PM PDT 24
Finished Jun 25 06:19:26 PM PDT 24
Peak memory 217788 kb
Host smart-ae9743f8-f046-45a8-a270-f5355dc4d439
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823155765 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_access.1823155765
Directory /workspace/2.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_errors.263721854
Short name T501
Test name
Test status
Simulation time 1332733900 ps
CPU time 42.78 seconds
Started Jun 25 06:19:19 PM PDT 24
Finished Jun 25 06:20:04 PM PDT 24
Peak memory 217240 kb
Host smart-1ee0a76b-6571-49e4-811c-5290259cd414
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263721854 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_err
ors.263721854
Directory /workspace/2.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_priority.1161711894
Short name T349
Test name
Test status
Simulation time 1410743885 ps
CPU time 5.15 seconds
Started Jun 25 06:19:18 PM PDT 24
Finished Jun 25 06:19:24 PM PDT 24
Peak memory 218156 kb
Host smart-6bd4fbeb-2001-4636-931b-020579d04840
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161711894 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_priority.1
161711894
Directory /workspace/2.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_prog_failure.3345570245
Short name T527
Test name
Test status
Simulation time 368429218 ps
CPU time 3.86 seconds
Started Jun 25 06:19:18 PM PDT 24
Finished Jun 25 06:19:23 PM PDT 24
Peak memory 223160 kb
Host smart-21c48366-e002-4ec1-be6d-067e42709d8c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345570245 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag
_prog_failure.3345570245
Directory /workspace/2.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_regwen_during_op.2066581091
Short name T541
Test name
Test status
Simulation time 2169713698 ps
CPU time 16.37 seconds
Started Jun 25 06:19:18 PM PDT 24
Finished Jun 25 06:19:36 PM PDT 24
Peak memory 218028 kb
Host smart-a9b9da0e-2e3f-49be-b1f9-cbb651dd2d91
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066581091 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_regwen_during_op.2066581091
Directory /workspace/2.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_smoke.2469527366
Short name T261
Test name
Test status
Simulation time 758768478 ps
CPU time 19.03 seconds
Started Jun 25 06:19:19 PM PDT 24
Finished Jun 25 06:19:41 PM PDT 24
Peak memory 216712 kb
Host smart-81f6d1b0-3fef-491b-8bfc-54da4cc0e91f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469527366 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_smoke.
2469527366
Directory /workspace/2.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_failure.939889872
Short name T104
Test name
Test status
Simulation time 18706705379 ps
CPU time 53.27 seconds
Started Jun 25 06:19:19 PM PDT 24
Finished Jun 25 06:20:14 PM PDT 24
Peak memory 252456 kb
Host smart-f82485d0-f469-4714-b2f3-2dce9bfada9a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939889872 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag
_state_failure.939889872
Directory /workspace/2.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_post_trans.3770944057
Short name T538
Test name
Test status
Simulation time 350544348 ps
CPU time 12.73 seconds
Started Jun 25 06:19:18 PM PDT 24
Finished Jun 25 06:19:32 PM PDT 24
Peak memory 223520 kb
Host smart-ca63f339-7cfe-466b-a3ac-bb816f021f0b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770944057 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_state_post_trans.3770944057
Directory /workspace/2.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_prog_failure.2403953254
Short name T192
Test name
Test status
Simulation time 331510662 ps
CPU time 1.96 seconds
Started Jun 25 06:19:09 PM PDT 24
Finished Jun 25 06:19:12 PM PDT 24
Peak memory 218612 kb
Host smart-93b463a2-1316-4065-bc70-8646690865a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403953254 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_prog_failure.2403953254
Directory /workspace/2.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_regwen_during_op.2523480676
Short name T849
Test name
Test status
Simulation time 349445642 ps
CPU time 23.15 seconds
Started Jun 25 06:19:10 PM PDT 24
Finished Jun 25 06:19:34 PM PDT 24
Peak memory 214644 kb
Host smart-7929d1df-6a21-491a-a83f-f7c251a82a53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523480676 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_regwen_during_op.2523480676
Directory /workspace/2.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_cm.202205426
Short name T99
Test name
Test status
Simulation time 235747222 ps
CPU time 23.14 seconds
Started Jun 25 06:19:18 PM PDT 24
Finished Jun 25 06:19:43 PM PDT 24
Peak memory 268972 kb
Host smart-fcd6da39-a72d-488a-8c90-c9d9b1256043
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202205426 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_cm.202205426
Directory /workspace/2.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_mubi.4048785527
Short name T534
Test name
Test status
Simulation time 279232621 ps
CPU time 12.49 seconds
Started Jun 25 06:19:18 PM PDT 24
Finished Jun 25 06:19:32 PM PDT 24
Peak memory 226436 kb
Host smart-cb6fdeba-0f48-4de7-9a60-56d41abb0686
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048785527 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_mubi.4048785527
Directory /workspace/2.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_digest.3923443753
Short name T31
Test name
Test status
Simulation time 2602037828 ps
CPU time 12.16 seconds
Started Jun 25 06:19:19 PM PDT 24
Finished Jun 25 06:19:32 PM PDT 24
Peak memory 218660 kb
Host smart-17438b62-95fc-4e22-83df-bdb30ea874e1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923443753 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_di
gest.3923443753
Directory /workspace/2.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_mux.1797647078
Short name T203
Test name
Test status
Simulation time 565149684 ps
CPU time 11.54 seconds
Started Jun 25 06:19:19 PM PDT 24
Finished Jun 25 06:19:32 PM PDT 24
Peak memory 218592 kb
Host smart-19f14901-5171-4b9d-be2d-a128f911dba1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797647078 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_mux.1
797647078
Directory /workspace/2.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/2.lc_ctrl_security_escalation.3474766654
Short name T804
Test name
Test status
Simulation time 967482228 ps
CPU time 6.69 seconds
Started Jun 25 06:19:10 PM PDT 24
Finished Jun 25 06:19:18 PM PDT 24
Peak memory 226440 kb
Host smart-e6b80191-d34d-40fb-b779-811f3c0d1967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3474766654 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_security_escalation.3474766654
Directory /workspace/2.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/2.lc_ctrl_smoke.4144927572
Short name T595
Test name
Test status
Simulation time 363596765 ps
CPU time 9.14 seconds
Started Jun 25 06:19:01 PM PDT 24
Finished Jun 25 06:19:11 PM PDT 24
Peak memory 218064 kb
Host smart-49e84481-a412-40ca-83d6-dc7fb260e061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144927572 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_smoke.4144927572
Directory /workspace/2.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_failure.2440347879
Short name T684
Test name
Test status
Simulation time 215058173 ps
CPU time 21.27 seconds
Started Jun 25 06:19:08 PM PDT 24
Finished Jun 25 06:19:31 PM PDT 24
Peak memory 251316 kb
Host smart-c61345c8-8108-4632-b9d8-826d0d1ed234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440347879 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_failure.2440347879
Directory /workspace/2.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_post_trans.4127373752
Short name T199
Test name
Test status
Simulation time 74160815 ps
CPU time 3.29 seconds
Started Jun 25 06:19:10 PM PDT 24
Finished Jun 25 06:19:14 PM PDT 24
Peak memory 226744 kb
Host smart-2160bcf7-281b-4c75-a8ab-806a9fb3db32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127373752 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_post_trans.4127373752
Directory /workspace/2.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all.20504457
Short name T51
Test name
Test status
Simulation time 1983752035 ps
CPU time 51.2 seconds
Started Jun 25 06:19:20 PM PDT 24
Finished Jun 25 06:20:13 PM PDT 24
Peak memory 248004 kb
Host smart-17b1ecc9-761e-4447-8bab-d18bd72bea86
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20504457 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_T
EST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
.lc_ctrl_stress_all.20504457
Directory /workspace/2.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.lc_ctrl_volatile_unlock_smoke.2425708522
Short name T556
Test name
Test status
Simulation time 47643968 ps
CPU time 1.04 seconds
Started Jun 25 06:19:01 PM PDT 24
Finished Jun 25 06:19:03 PM PDT 24
Peak memory 212296 kb
Host smart-83ba496d-b96a-4353-82ef-3b424288e8de
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425708522 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ct
rl_volatile_unlock_smoke.2425708522
Directory /workspace/2.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_alert_test.488804129
Short name T276
Test name
Test status
Simulation time 88246770 ps
CPU time 0.95 seconds
Started Jun 25 06:22:33 PM PDT 24
Finished Jun 25 06:22:35 PM PDT 24
Peak memory 209492 kb
Host smart-4aaceef2-09ba-45f2-919e-63b451ff6884
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488804129 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_alert_test.488804129
Directory /workspace/20.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.lc_ctrl_errors.4124945525
Short name T384
Test name
Test status
Simulation time 575259566 ps
CPU time 16.12 seconds
Started Jun 25 06:22:30 PM PDT 24
Finished Jun 25 06:22:47 PM PDT 24
Peak memory 226536 kb
Host smart-bcefa119-7e77-41e6-8bdc-5deaf8ee14cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124945525 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_errors.4124945525
Directory /workspace/20.lc_ctrl_errors/latest

Test location /workspace/coverage/default/20.lc_ctrl_jtag_access.4274990578
Short name T75
Test name
Test status
Simulation time 283866206 ps
CPU time 4.33 seconds
Started Jun 25 06:22:31 PM PDT 24
Finished Jun 25 06:22:38 PM PDT 24
Peak memory 217404 kb
Host smart-435cec63-d1b1-4d78-b805-798dad8970f0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274990578 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_jtag_access.4274990578
Directory /workspace/20.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/20.lc_ctrl_prog_failure.2131576281
Short name T671
Test name
Test status
Simulation time 153601114 ps
CPU time 3.06 seconds
Started Jun 25 06:22:29 PM PDT 24
Finished Jun 25 06:22:33 PM PDT 24
Peak memory 218640 kb
Host smart-b986dcfa-d634-4af9-a28b-0ce9d26518e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131576281 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_prog_failure.2131576281
Directory /workspace/20.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_mubi.324026338
Short name T481
Test name
Test status
Simulation time 1929337988 ps
CPU time 8.91 seconds
Started Jun 25 06:22:30 PM PDT 24
Finished Jun 25 06:22:40 PM PDT 24
Peak memory 226420 kb
Host smart-7b0c7826-bc86-46d2-9c7b-3fb938c71543
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324026338 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_mubi.324026338
Directory /workspace/20.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_digest.2308705885
Short name T423
Test name
Test status
Simulation time 754029307 ps
CPU time 10.64 seconds
Started Jun 25 06:22:34 PM PDT 24
Finished Jun 25 06:22:45 PM PDT 24
Peak memory 218584 kb
Host smart-c6d9afc8-0b56-4227-9ffb-ce8817d641ea
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308705885 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_d
igest.2308705885
Directory /workspace/20.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_mux.2169843741
Short name T816
Test name
Test status
Simulation time 472368030 ps
CPU time 8.71 seconds
Started Jun 25 06:22:33 PM PDT 24
Finished Jun 25 06:22:43 PM PDT 24
Peak memory 218512 kb
Host smart-8f07022d-44c9-4cc2-92e6-6e82885ac56e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169843741 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_mux.
2169843741
Directory /workspace/20.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/20.lc_ctrl_security_escalation.3947294941
Short name T382
Test name
Test status
Simulation time 237912524 ps
CPU time 10.17 seconds
Started Jun 25 06:22:31 PM PDT 24
Finished Jun 25 06:22:43 PM PDT 24
Peak memory 225316 kb
Host smart-47b1f27d-c134-4486-81e4-c87c3a85dc6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947294941 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_security_escalation.3947294941
Directory /workspace/20.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/20.lc_ctrl_smoke.878202475
Short name T93
Test name
Test status
Simulation time 24589925 ps
CPU time 1.95 seconds
Started Jun 25 06:22:21 PM PDT 24
Finished Jun 25 06:22:24 PM PDT 24
Peak memory 214360 kb
Host smart-4c193dda-a351-44c5-a567-b1aca89d799f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878202475 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_smoke.878202475
Directory /workspace/20.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_failure.3527685757
Short name T484
Test name
Test status
Simulation time 951684173 ps
CPU time 29.17 seconds
Started Jun 25 06:22:38 PM PDT 24
Finished Jun 25 06:23:08 PM PDT 24
Peak memory 251372 kb
Host smart-2539ded4-927b-4920-8f6d-782a7c7389e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527685757 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_failure.3527685757
Directory /workspace/20.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_post_trans.795643250
Short name T458
Test name
Test status
Simulation time 455180887 ps
CPU time 3.28 seconds
Started Jun 25 06:22:30 PM PDT 24
Finished Jun 25 06:22:35 PM PDT 24
Peak memory 222972 kb
Host smart-cd52f204-8f19-4812-94d0-717d0999d2b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795643250 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_post_trans.795643250
Directory /workspace/20.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/20.lc_ctrl_stress_all.2821092974
Short name T624
Test name
Test status
Simulation time 6794810149 ps
CPU time 121.09 seconds
Started Jun 25 06:22:32 PM PDT 24
Finished Jun 25 06:24:34 PM PDT 24
Peak memory 248908 kb
Host smart-1bca2d76-7fa1-48ce-bf8f-e33679b6237c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821092974 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.lc_ctrl_stress_all.2821092974
Directory /workspace/20.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.lc_ctrl_volatile_unlock_smoke.1791567235
Short name T91
Test name
Test status
Simulation time 16769057 ps
CPU time 1.02 seconds
Started Jun 25 06:22:30 PM PDT 24
Finished Jun 25 06:22:33 PM PDT 24
Peak memory 212168 kb
Host smart-4617aa63-b77f-463c-a484-ec8d9a75e20d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791567235 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_c
trl_volatile_unlock_smoke.1791567235
Directory /workspace/20.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_alert_test.447752058
Short name T673
Test name
Test status
Simulation time 14726602 ps
CPU time 1.15 seconds
Started Jun 25 06:22:40 PM PDT 24
Finished Jun 25 06:22:42 PM PDT 24
Peak memory 209356 kb
Host smart-2e807819-ef34-4386-b666-95bb8113f1e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447752058 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_alert_test.447752058
Directory /workspace/21.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.lc_ctrl_errors.3993685391
Short name T337
Test name
Test status
Simulation time 296743077 ps
CPU time 9.88 seconds
Started Jun 25 06:22:32 PM PDT 24
Finished Jun 25 06:22:43 PM PDT 24
Peak memory 218588 kb
Host smart-c3b4afd6-96e7-40db-99f6-ea94b66393c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993685391 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_errors.3993685391
Directory /workspace/21.lc_ctrl_errors/latest

Test location /workspace/coverage/default/21.lc_ctrl_jtag_access.4147423114
Short name T27
Test name
Test status
Simulation time 2127289277 ps
CPU time 20.25 seconds
Started Jun 25 06:22:32 PM PDT 24
Finished Jun 25 06:22:54 PM PDT 24
Peak memory 217844 kb
Host smart-9543eae5-1b2e-47c7-9407-62f2ca3a6198
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147423114 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_jtag_access.4147423114
Directory /workspace/21.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/21.lc_ctrl_prog_failure.3131630408
Short name T12
Test name
Test status
Simulation time 46905597 ps
CPU time 1.85 seconds
Started Jun 25 06:22:31 PM PDT 24
Finished Jun 25 06:22:35 PM PDT 24
Peak memory 222424 kb
Host smart-473c0562-f8c0-4e2d-9d47-58ba336d809f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131630408 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_prog_failure.3131630408
Directory /workspace/21.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_mubi.3457420194
Short name T334
Test name
Test status
Simulation time 2428277491 ps
CPU time 14.81 seconds
Started Jun 25 06:22:38 PM PDT 24
Finished Jun 25 06:22:54 PM PDT 24
Peak memory 226508 kb
Host smart-30f08fbf-85a4-4a94-b87d-1f60fd3fda5f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457420194 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_mubi.3457420194
Directory /workspace/21.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_digest.843308091
Short name T317
Test name
Test status
Simulation time 326173018 ps
CPU time 9.56 seconds
Started Jun 25 06:22:39 PM PDT 24
Finished Jun 25 06:22:49 PM PDT 24
Peak memory 218652 kb
Host smart-b3ebd033-59f5-422c-923f-72472f077a70
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843308091 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_di
gest.843308091
Directory /workspace/21.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_mux.2417275610
Short name T859
Test name
Test status
Simulation time 235195620 ps
CPU time 8.93 seconds
Started Jun 25 06:22:41 PM PDT 24
Finished Jun 25 06:22:50 PM PDT 24
Peak memory 218568 kb
Host smart-308f5d38-209c-409d-a396-b47763c8d3c4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417275610 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_mux.
2417275610
Directory /workspace/21.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/21.lc_ctrl_security_escalation.3451099659
Short name T589
Test name
Test status
Simulation time 412978405 ps
CPU time 10.32 seconds
Started Jun 25 06:22:34 PM PDT 24
Finished Jun 25 06:22:46 PM PDT 24
Peak memory 226428 kb
Host smart-0c768d3c-0d31-4d9b-a16e-1c221515cb38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451099659 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_security_escalation.3451099659
Directory /workspace/21.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/21.lc_ctrl_smoke.3987267574
Short name T498
Test name
Test status
Simulation time 434843255 ps
CPU time 5.21 seconds
Started Jun 25 06:22:30 PM PDT 24
Finished Jun 25 06:22:36 PM PDT 24
Peak memory 218032 kb
Host smart-3cef995c-d460-424f-a2ef-fbe18e6b31ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987267574 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_smoke.3987267574
Directory /workspace/21.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_failure.2766261532
Short name T772
Test name
Test status
Simulation time 761973319 ps
CPU time 25.24 seconds
Started Jun 25 06:22:33 PM PDT 24
Finished Jun 25 06:23:00 PM PDT 24
Peak memory 251260 kb
Host smart-a005f936-7c6c-46b6-ad70-216c8e41fc84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766261532 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_failure.2766261532
Directory /workspace/21.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_post_trans.3381820379
Short name T85
Test name
Test status
Simulation time 1066786679 ps
CPU time 6.9 seconds
Started Jun 25 06:22:31 PM PDT 24
Finished Jun 25 06:22:40 PM PDT 24
Peak memory 251272 kb
Host smart-d43bdc26-bc83-413a-bf0d-ee3c0ac75e48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381820379 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_post_trans.3381820379
Directory /workspace/21.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/21.lc_ctrl_stress_all.2166476994
Short name T117
Test name
Test status
Simulation time 29389673009 ps
CPU time 116.08 seconds
Started Jun 25 06:22:38 PM PDT 24
Finished Jun 25 06:24:35 PM PDT 24
Peak memory 226496 kb
Host smart-8014bc1f-1bee-4e39-9f03-c98d40e1d6ed
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166476994 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.lc_ctrl_stress_all.2166476994
Directory /workspace/21.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.lc_ctrl_volatile_unlock_smoke.336717365
Short name T136
Test name
Test status
Simulation time 108553241 ps
CPU time 0.92 seconds
Started Jun 25 06:22:31 PM PDT 24
Finished Jun 25 06:22:33 PM PDT 24
Peak memory 209460 kb
Host smart-8da9f88b-bd62-4d81-8b92-1832c460c376
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336717365 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ct
rl_volatile_unlock_smoke.336717365
Directory /workspace/21.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_alert_test.239042996
Short name T448
Test name
Test status
Simulation time 93696517 ps
CPU time 0.86 seconds
Started Jun 25 06:22:38 PM PDT 24
Finished Jun 25 06:22:40 PM PDT 24
Peak memory 209108 kb
Host smart-94d0328b-dc6a-47e9-b2a9-b4e086d2031f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239042996 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_alert_test.239042996
Directory /workspace/22.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.lc_ctrl_errors.3168908118
Short name T829
Test name
Test status
Simulation time 1426469111 ps
CPU time 8.84 seconds
Started Jun 25 06:22:39 PM PDT 24
Finished Jun 25 06:22:49 PM PDT 24
Peak memory 218624 kb
Host smart-d5aab02c-3014-4a5e-840b-7fd08a8c84a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168908118 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_errors.3168908118
Directory /workspace/22.lc_ctrl_errors/latest

Test location /workspace/coverage/default/22.lc_ctrl_jtag_access.3339015847
Short name T660
Test name
Test status
Simulation time 1550182296 ps
CPU time 4.91 seconds
Started Jun 25 06:22:39 PM PDT 24
Finished Jun 25 06:22:45 PM PDT 24
Peak memory 217476 kb
Host smart-c88d3066-0efd-4dfd-9391-5662e0d8e93e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339015847 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_jtag_access.3339015847
Directory /workspace/22.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/22.lc_ctrl_prog_failure.1882744916
Short name T577
Test name
Test status
Simulation time 114495801 ps
CPU time 2.07 seconds
Started Jun 25 06:22:45 PM PDT 24
Finished Jun 25 06:22:48 PM PDT 24
Peak memory 218624 kb
Host smart-6fc4f475-606a-446b-8e34-425fd7d3fd9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882744916 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_prog_failure.1882744916
Directory /workspace/22.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_mubi.285263062
Short name T781
Test name
Test status
Simulation time 291896403 ps
CPU time 14.26 seconds
Started Jun 25 06:22:39 PM PDT 24
Finished Jun 25 06:22:54 PM PDT 24
Peak memory 219352 kb
Host smart-9b49ec6b-3d26-42fa-a3a2-7e5378e58b5f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285263062 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_mubi.285263062
Directory /workspace/22.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_digest.1487359086
Short name T461
Test name
Test status
Simulation time 441847083 ps
CPU time 16.95 seconds
Started Jun 25 06:22:39 PM PDT 24
Finished Jun 25 06:22:57 PM PDT 24
Peak memory 218584 kb
Host smart-eeea9c22-2234-40c5-8fa0-db747858821e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487359086 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_d
igest.1487359086
Directory /workspace/22.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_mux.1757726203
Short name T755
Test name
Test status
Simulation time 700189978 ps
CPU time 7.58 seconds
Started Jun 25 06:22:39 PM PDT 24
Finished Jun 25 06:22:47 PM PDT 24
Peak memory 226360 kb
Host smart-78e9148c-8628-492e-b82f-0e74f959ee36
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757726203 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_mux.
1757726203
Directory /workspace/22.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/22.lc_ctrl_security_escalation.954786299
Short name T413
Test name
Test status
Simulation time 288937510 ps
CPU time 11.81 seconds
Started Jun 25 06:22:37 PM PDT 24
Finished Jun 25 06:22:50 PM PDT 24
Peak memory 226368 kb
Host smart-f5af670d-6bd0-4b57-8836-95a5c3f57e3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954786299 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_security_escalation.954786299
Directory /workspace/22.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/22.lc_ctrl_smoke.2296830524
Short name T123
Test name
Test status
Simulation time 21942173 ps
CPU time 1.65 seconds
Started Jun 25 06:22:39 PM PDT 24
Finished Jun 25 06:22:42 PM PDT 24
Peak memory 214112 kb
Host smart-d6471880-c8a1-47b1-97a8-4ae6c2a9fa91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296830524 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_smoke.2296830524
Directory /workspace/22.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_failure.1824718715
Short name T392
Test name
Test status
Simulation time 708776382 ps
CPU time 17.46 seconds
Started Jun 25 06:22:37 PM PDT 24
Finished Jun 25 06:22:56 PM PDT 24
Peak memory 251324 kb
Host smart-2f13688e-28a0-48ad-8a62-5fd858681c77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824718715 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_failure.1824718715
Directory /workspace/22.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_post_trans.271488984
Short name T421
Test name
Test status
Simulation time 113190224 ps
CPU time 7.29 seconds
Started Jun 25 06:22:45 PM PDT 24
Finished Jun 25 06:22:53 PM PDT 24
Peak memory 250932 kb
Host smart-2226ebdc-9468-4dd2-9720-7ac8df817e06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271488984 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_post_trans.271488984
Directory /workspace/22.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/22.lc_ctrl_stress_all.1374056154
Short name T202
Test name
Test status
Simulation time 9641522288 ps
CPU time 305.89 seconds
Started Jun 25 06:22:38 PM PDT 24
Finished Jun 25 06:27:45 PM PDT 24
Peak memory 251320 kb
Host smart-d1d4ddef-7fc6-47d5-a6c2-32b44648407e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374056154 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.lc_ctrl_stress_all.1374056154
Directory /workspace/22.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.lc_ctrl_volatile_unlock_smoke.1554982844
Short name T749
Test name
Test status
Simulation time 39773981 ps
CPU time 1.08 seconds
Started Jun 25 06:22:44 PM PDT 24
Finished Jun 25 06:22:47 PM PDT 24
Peak memory 212284 kb
Host smart-757f48fc-4b1e-4723-89d0-3b583b0d5698
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554982844 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_c
trl_volatile_unlock_smoke.1554982844
Directory /workspace/22.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_alert_test.1299557881
Short name T343
Test name
Test status
Simulation time 13865691 ps
CPU time 0.83 seconds
Started Jun 25 06:22:47 PM PDT 24
Finished Jun 25 06:22:50 PM PDT 24
Peak memory 209092 kb
Host smart-f950ef6d-d578-464d-a904-5cac4b62f3b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299557881 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_alert_test.1299557881
Directory /workspace/23.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.lc_ctrl_errors.28498570
Short name T200
Test name
Test status
Simulation time 1341889592 ps
CPU time 11.94 seconds
Started Jun 25 06:22:49 PM PDT 24
Finished Jun 25 06:23:03 PM PDT 24
Peak memory 226432 kb
Host smart-7af7fcc8-6fce-4a59-bb1e-792c360e6e6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28498570 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_errors.28498570
Directory /workspace/23.lc_ctrl_errors/latest

Test location /workspace/coverage/default/23.lc_ctrl_jtag_access.3840667429
Short name T22
Test name
Test status
Simulation time 15963160312 ps
CPU time 19.36 seconds
Started Jun 25 06:22:46 PM PDT 24
Finished Jun 25 06:23:07 PM PDT 24
Peak memory 218080 kb
Host smart-5a34d154-8603-4724-841c-5f027d1c4283
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840667429 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_jtag_access.3840667429
Directory /workspace/23.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/23.lc_ctrl_prog_failure.2507861624
Short name T459
Test name
Test status
Simulation time 28630527 ps
CPU time 1.82 seconds
Started Jun 25 06:22:46 PM PDT 24
Finished Jun 25 06:22:50 PM PDT 24
Peak memory 218688 kb
Host smart-16d970d4-424c-47c3-909f-53e46807cb02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507861624 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_prog_failure.2507861624
Directory /workspace/23.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_mubi.533823292
Short name T650
Test name
Test status
Simulation time 263037266 ps
CPU time 10.6 seconds
Started Jun 25 06:22:49 PM PDT 24
Finished Jun 25 06:23:01 PM PDT 24
Peak memory 226548 kb
Host smart-27c4dc8c-4222-4bc9-88b3-78a070b37f7c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533823292 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_mubi.533823292
Directory /workspace/23.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_digest.927123179
Short name T585
Test name
Test status
Simulation time 1325529005 ps
CPU time 10.78 seconds
Started Jun 25 06:22:45 PM PDT 24
Finished Jun 25 06:22:57 PM PDT 24
Peak memory 218588 kb
Host smart-52603a74-de53-425c-a926-ba99086a80de
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927123179 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_di
gest.927123179
Directory /workspace/23.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_mux.3511385648
Short name T396
Test name
Test status
Simulation time 594978756 ps
CPU time 19.07 seconds
Started Jun 25 06:22:47 PM PDT 24
Finished Jun 25 06:23:08 PM PDT 24
Peak memory 226364 kb
Host smart-dd757d79-45fc-45ae-a299-68c321e98112
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511385648 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_mux.
3511385648
Directory /workspace/23.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/23.lc_ctrl_security_escalation.4201769750
Short name T333
Test name
Test status
Simulation time 915607242 ps
CPU time 9.7 seconds
Started Jun 25 06:22:46 PM PDT 24
Finished Jun 25 06:22:58 PM PDT 24
Peak memory 225772 kb
Host smart-fa4146cc-ee5e-4c56-8bd1-10a9e23a095c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201769750 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_security_escalation.4201769750
Directory /workspace/23.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/23.lc_ctrl_smoke.1024903347
Short name T729
Test name
Test status
Simulation time 51154089 ps
CPU time 3.56 seconds
Started Jun 25 06:22:39 PM PDT 24
Finished Jun 25 06:22:43 PM PDT 24
Peak memory 218028 kb
Host smart-7b50f367-c338-4d1a-ab8b-427ca216ba9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024903347 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_smoke.1024903347
Directory /workspace/23.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_failure.503181000
Short name T319
Test name
Test status
Simulation time 913791523 ps
CPU time 30.47 seconds
Started Jun 25 06:22:38 PM PDT 24
Finished Jun 25 06:23:10 PM PDT 24
Peak memory 251312 kb
Host smart-4da42e23-299f-493d-8b80-0bd7a384cfd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503181000 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_failure.503181000
Directory /workspace/23.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_post_trans.2063630301
Short name T344
Test name
Test status
Simulation time 158028604 ps
CPU time 10.94 seconds
Started Jun 25 06:22:47 PM PDT 24
Finished Jun 25 06:22:59 PM PDT 24
Peak memory 251348 kb
Host smart-8250099b-4447-406d-a4bd-35d35cfc527c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063630301 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_post_trans.2063630301
Directory /workspace/23.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all.4098549456
Short name T393
Test name
Test status
Simulation time 3369082342 ps
CPU time 74.55 seconds
Started Jun 25 06:22:46 PM PDT 24
Finished Jun 25 06:24:02 PM PDT 24
Peak memory 267816 kb
Host smart-0cafe403-59b0-4bd2-8ffb-eb5175fb2491
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098549456 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.lc_ctrl_stress_all.4098549456
Directory /workspace/23.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all_with_rand_reset.4256077109
Short name T180
Test name
Test status
Simulation time 12417516786 ps
CPU time 406.39 seconds
Started Jun 25 06:22:49 PM PDT 24
Finished Jun 25 06:29:37 PM PDT 24
Peak memory 284472 kb
Host smart-9be3543e-1c52-4dde-a1e2-53849fc6700b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4256077109 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_stress_all_with_rand_reset.4256077109
Directory /workspace/23.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.lc_ctrl_volatile_unlock_smoke.959812581
Short name T653
Test name
Test status
Simulation time 42659106 ps
CPU time 1.12 seconds
Started Jun 25 06:22:39 PM PDT 24
Finished Jun 25 06:22:41 PM PDT 24
Peak memory 212260 kb
Host smart-0b66410c-bfac-4761-a783-2760919383fe
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959812581 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ct
rl_volatile_unlock_smoke.959812581
Directory /workspace/23.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_alert_test.1243930175
Short name T240
Test name
Test status
Simulation time 21329020 ps
CPU time 0.93 seconds
Started Jun 25 06:22:53 PM PDT 24
Finished Jun 25 06:22:54 PM PDT 24
Peak memory 209388 kb
Host smart-00aaccb4-7759-4b6e-aaf3-bd1a59038b3d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243930175 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_alert_test.1243930175
Directory /workspace/24.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.lc_ctrl_errors.3160570283
Short name T688
Test name
Test status
Simulation time 328691531 ps
CPU time 10.47 seconds
Started Jun 25 06:22:47 PM PDT 24
Finished Jun 25 06:22:59 PM PDT 24
Peak memory 218656 kb
Host smart-40b95483-3030-4a87-bddf-60f35876829b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160570283 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_errors.3160570283
Directory /workspace/24.lc_ctrl_errors/latest

Test location /workspace/coverage/default/24.lc_ctrl_jtag_access.540622404
Short name T7
Test name
Test status
Simulation time 429257989 ps
CPU time 5.71 seconds
Started Jun 25 06:22:45 PM PDT 24
Finished Jun 25 06:22:53 PM PDT 24
Peak memory 217768 kb
Host smart-3a60cea7-6b60-4d29-9345-ac0558a1571f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540622404 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_jtag_access.540622404
Directory /workspace/24.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/24.lc_ctrl_prog_failure.1410404245
Short name T348
Test name
Test status
Simulation time 81074290 ps
CPU time 2.95 seconds
Started Jun 25 06:22:46 PM PDT 24
Finished Jun 25 06:22:50 PM PDT 24
Peak memory 222840 kb
Host smart-f41ca4c1-88a7-4f86-ace7-5dcfa55011e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410404245 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_prog_failure.1410404245
Directory /workspace/24.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_mubi.1114025518
Short name T463
Test name
Test status
Simulation time 635613628 ps
CPU time 12.89 seconds
Started Jun 25 06:22:45 PM PDT 24
Finished Jun 25 06:23:00 PM PDT 24
Peak memory 226364 kb
Host smart-a4471846-dbf8-44ed-9e59-4eca7ad16491
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114025518 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_mubi.1114025518
Directory /workspace/24.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_digest.3071429013
Short name T477
Test name
Test status
Simulation time 171194363 ps
CPU time 8.84 seconds
Started Jun 25 06:22:48 PM PDT 24
Finished Jun 25 06:22:58 PM PDT 24
Peak memory 218592 kb
Host smart-24e23598-f44c-4109-8319-5b4b5da18ebc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071429013 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_d
igest.3071429013
Directory /workspace/24.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_mux.1399512498
Short name T637
Test name
Test status
Simulation time 983754347 ps
CPU time 6.97 seconds
Started Jun 25 06:22:49 PM PDT 24
Finished Jun 25 06:22:58 PM PDT 24
Peak memory 226364 kb
Host smart-05830f06-602c-4fea-8a77-31fe3d0d3220
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399512498 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_mux.
1399512498
Directory /workspace/24.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/24.lc_ctrl_security_escalation.3079021044
Short name T336
Test name
Test status
Simulation time 484840902 ps
CPU time 8.19 seconds
Started Jun 25 06:22:45 PM PDT 24
Finished Jun 25 06:22:56 PM PDT 24
Peak memory 218692 kb
Host smart-6b6203bb-ea38-4499-ade6-650e9fb6b083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079021044 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_security_escalation.3079021044
Directory /workspace/24.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/24.lc_ctrl_smoke.2477311832
Short name T87
Test name
Test status
Simulation time 106252115 ps
CPU time 3.82 seconds
Started Jun 25 06:22:46 PM PDT 24
Finished Jun 25 06:22:51 PM PDT 24
Peak memory 218036 kb
Host smart-24c93fd7-33e6-4fe6-960d-92d0c1c3f541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477311832 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_smoke.2477311832
Directory /workspace/24.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_failure.218387337
Short name T373
Test name
Test status
Simulation time 164452819 ps
CPU time 21.59 seconds
Started Jun 25 06:22:48 PM PDT 24
Finished Jun 25 06:23:11 PM PDT 24
Peak memory 251332 kb
Host smart-c80e279d-5f94-4670-a633-934092b4d655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218387337 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_failure.218387337
Directory /workspace/24.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_post_trans.4168672716
Short name T356
Test name
Test status
Simulation time 202648808 ps
CPU time 6.16 seconds
Started Jun 25 06:22:47 PM PDT 24
Finished Jun 25 06:22:55 PM PDT 24
Peak memory 247044 kb
Host smart-cbfcbf6a-e519-4d22-bffe-1c702c3b8eeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168672716 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_post_trans.4168672716
Directory /workspace/24.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all.3221182828
Short name T847
Test name
Test status
Simulation time 102914549130 ps
CPU time 167.64 seconds
Started Jun 25 06:22:46 PM PDT 24
Finished Jun 25 06:25:35 PM PDT 24
Peak memory 267964 kb
Host smart-bc6243f6-2880-4ea7-9a7a-43c9ea6e62de
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221182828 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.lc_ctrl_stress_all.3221182828
Directory /workspace/24.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.lc_ctrl_volatile_unlock_smoke.473205418
Short name T252
Test name
Test status
Simulation time 14104711 ps
CPU time 0.96 seconds
Started Jun 25 06:22:47 PM PDT 24
Finished Jun 25 06:22:49 PM PDT 24
Peak memory 208568 kb
Host smart-9ba1376f-6cf8-4536-bc96-567b1a30c8f0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473205418 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ct
rl_volatile_unlock_smoke.473205418
Directory /workspace/24.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_alert_test.122636787
Short name T367
Test name
Test status
Simulation time 18650329 ps
CPU time 0.97 seconds
Started Jun 25 06:22:54 PM PDT 24
Finished Jun 25 06:22:56 PM PDT 24
Peak memory 209424 kb
Host smart-0444b504-bbef-4993-b6fb-db2ef6586ecc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122636787 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_alert_test.122636787
Directory /workspace/25.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.lc_ctrl_errors.1121333206
Short name T482
Test name
Test status
Simulation time 376331703 ps
CPU time 11.74 seconds
Started Jun 25 06:22:56 PM PDT 24
Finished Jun 25 06:23:08 PM PDT 24
Peak memory 218636 kb
Host smart-a2f06155-7d3a-4100-83c6-b36d8a290be7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121333206 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_errors.1121333206
Directory /workspace/25.lc_ctrl_errors/latest

Test location /workspace/coverage/default/25.lc_ctrl_jtag_access.130267677
Short name T485
Test name
Test status
Simulation time 1262436093 ps
CPU time 1.5 seconds
Started Jun 25 06:22:55 PM PDT 24
Finished Jun 25 06:22:57 PM PDT 24
Peak memory 217328 kb
Host smart-fac5656e-9621-4921-a358-5436ace9bd41
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130267677 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_jtag_access.130267677
Directory /workspace/25.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/25.lc_ctrl_prog_failure.2490504436
Short name T269
Test name
Test status
Simulation time 36655121 ps
CPU time 1.83 seconds
Started Jun 25 06:22:54 PM PDT 24
Finished Jun 25 06:22:56 PM PDT 24
Peak memory 218628 kb
Host smart-7687295e-bd15-46d0-b9ca-6ccdf25d5795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490504436 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_prog_failure.2490504436
Directory /workspace/25.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_mubi.1595240381
Short name T615
Test name
Test status
Simulation time 1102734548 ps
CPU time 9.14 seconds
Started Jun 25 06:22:58 PM PDT 24
Finished Jun 25 06:23:08 PM PDT 24
Peak memory 226432 kb
Host smart-eac7e01a-9839-4164-b0a7-54b437ac1ceb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595240381 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_mubi.1595240381
Directory /workspace/25.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_digest.2297090441
Short name T622
Test name
Test status
Simulation time 3862429938 ps
CPU time 10.02 seconds
Started Jun 25 06:22:54 PM PDT 24
Finished Jun 25 06:23:06 PM PDT 24
Peak memory 219304 kb
Host smart-b79e4d22-8c00-4989-921d-da560e8b0f20
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297090441 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_d
igest.2297090441
Directory /workspace/25.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_mux.3641471298
Short name T32
Test name
Test status
Simulation time 1126781759 ps
CPU time 11.56 seconds
Started Jun 25 06:22:54 PM PDT 24
Finished Jun 25 06:23:07 PM PDT 24
Peak memory 226368 kb
Host smart-7b8d2170-d9e3-4799-aec6-05fab46a5d15
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641471298 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_mux.
3641471298
Directory /workspace/25.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/25.lc_ctrl_security_escalation.651835126
Short name T297
Test name
Test status
Simulation time 400531695 ps
CPU time 8.5 seconds
Started Jun 25 06:22:57 PM PDT 24
Finished Jun 25 06:23:07 PM PDT 24
Peak memory 226432 kb
Host smart-1961bfa2-be2d-4c1c-bc74-a260bf9fdcce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651835126 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_security_escalation.651835126
Directory /workspace/25.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/25.lc_ctrl_smoke.1446381868
Short name T204
Test name
Test status
Simulation time 36312752 ps
CPU time 2.64 seconds
Started Jun 25 06:22:55 PM PDT 24
Finished Jun 25 06:22:58 PM PDT 24
Peak memory 215112 kb
Host smart-9493143d-128c-4d8e-a99f-161b156b28de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446381868 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_smoke.1446381868
Directory /workspace/25.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_failure.558683924
Short name T537
Test name
Test status
Simulation time 1243776557 ps
CPU time 27.25 seconds
Started Jun 25 06:22:55 PM PDT 24
Finished Jun 25 06:23:24 PM PDT 24
Peak memory 251328 kb
Host smart-1079ac2b-6daf-4c72-924f-16fa0619ccc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558683924 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_failure.558683924
Directory /workspace/25.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_post_trans.711083383
Short name T554
Test name
Test status
Simulation time 334026561 ps
CPU time 3.52 seconds
Started Jun 25 06:22:56 PM PDT 24
Finished Jun 25 06:23:00 PM PDT 24
Peak memory 222956 kb
Host smart-ac6c71b4-a5ed-46e7-9e84-6a4ab1d57a91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711083383 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_post_trans.711083383
Directory /workspace/25.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/25.lc_ctrl_stress_all.915281042
Short name T105
Test name
Test status
Simulation time 659292700 ps
CPU time 23.9 seconds
Started Jun 25 06:22:55 PM PDT 24
Finished Jun 25 06:23:20 PM PDT 24
Peak memory 227144 kb
Host smart-7f78e4d1-aea0-4798-ac3e-e97f57dc754a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915281042 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.lc_ctrl_stress_all.915281042
Directory /workspace/25.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.lc_ctrl_stress_all_with_rand_reset.3945299515
Short name T181
Test name
Test status
Simulation time 124769649989 ps
CPU time 685.43 seconds
Started Jun 25 06:22:58 PM PDT 24
Finished Jun 25 06:34:24 PM PDT 24
Peak memory 530036 kb
Host smart-f1d9c6b6-04d3-418d-84a7-e6c2a2648f54
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3945299515 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_stress_all_with_rand_reset.3945299515
Directory /workspace/25.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.lc_ctrl_volatile_unlock_smoke.3331967327
Short name T326
Test name
Test status
Simulation time 13166835 ps
CPU time 0.82 seconds
Started Jun 25 06:22:54 PM PDT 24
Finished Jun 25 06:22:55 PM PDT 24
Peak memory 209172 kb
Host smart-8634a0d8-27d1-4812-8af9-296fdd51d1b2
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331967327 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_c
trl_volatile_unlock_smoke.3331967327
Directory /workspace/25.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_alert_test.1322967340
Short name T471
Test name
Test status
Simulation time 142013657 ps
CPU time 0.91 seconds
Started Jun 25 06:23:02 PM PDT 24
Finished Jun 25 06:23:04 PM PDT 24
Peak memory 209344 kb
Host smart-b394424d-a55b-42b9-9beb-b2fb72f5b3c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322967340 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_alert_test.1322967340
Directory /workspace/26.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.lc_ctrl_errors.2876379657
Short name T281
Test name
Test status
Simulation time 766667715 ps
CPU time 17.44 seconds
Started Jun 25 06:23:01 PM PDT 24
Finished Jun 25 06:23:20 PM PDT 24
Peak memory 226432 kb
Host smart-e51a4af0-a003-44f5-bdfb-857305f9b69d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876379657 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_errors.2876379657
Directory /workspace/26.lc_ctrl_errors/latest

Test location /workspace/coverage/default/26.lc_ctrl_jtag_access.24183183
Short name T564
Test name
Test status
Simulation time 399356101 ps
CPU time 10.47 seconds
Started Jun 25 06:23:00 PM PDT 24
Finished Jun 25 06:23:12 PM PDT 24
Peak memory 217648 kb
Host smart-0bd9f520-2f59-4fd9-a9e6-80953efb948f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24183183 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_jtag_access.24183183
Directory /workspace/26.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/26.lc_ctrl_prog_failure.1982888330
Short name T68
Test name
Test status
Simulation time 322835250 ps
CPU time 3.22 seconds
Started Jun 25 06:23:01 PM PDT 24
Finished Jun 25 06:23:06 PM PDT 24
Peak memory 222732 kb
Host smart-3ac2f151-bdd2-40ed-b20d-0dbaa88cb4ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982888330 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_prog_failure.1982888330
Directory /workspace/26.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_mubi.966344505
Short name T657
Test name
Test status
Simulation time 4334396621 ps
CPU time 14.16 seconds
Started Jun 25 06:23:02 PM PDT 24
Finished Jun 25 06:23:17 PM PDT 24
Peak memory 226480 kb
Host smart-5bddd151-3eff-4b7d-a081-cf2b3643324c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966344505 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_mubi.966344505
Directory /workspace/26.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_mux.2436219387
Short name T480
Test name
Test status
Simulation time 1047632416 ps
CPU time 8.62 seconds
Started Jun 25 06:23:01 PM PDT 24
Finished Jun 25 06:23:10 PM PDT 24
Peak memory 218572 kb
Host smart-8993e08a-b7f9-4c12-ad46-36cc75480ca6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436219387 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_mux.
2436219387
Directory /workspace/26.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/26.lc_ctrl_security_escalation.478563757
Short name T60
Test name
Test status
Simulation time 5932070991 ps
CPU time 12.56 seconds
Started Jun 25 06:23:03 PM PDT 24
Finished Jun 25 06:23:17 PM PDT 24
Peak memory 226568 kb
Host smart-19a232b6-dc4d-481e-b1cc-da732dc7577f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478563757 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_security_escalation.478563757
Directory /workspace/26.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/26.lc_ctrl_smoke.3456245316
Short name T74
Test name
Test status
Simulation time 43788329 ps
CPU time 1.66 seconds
Started Jun 25 06:23:01 PM PDT 24
Finished Jun 25 06:23:04 PM PDT 24
Peak memory 214180 kb
Host smart-3d7f8a7a-7a06-4655-96c3-4f7163137a18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456245316 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_smoke.3456245316
Directory /workspace/26.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_failure.2370794348
Short name T298
Test name
Test status
Simulation time 1068702903 ps
CPU time 35.65 seconds
Started Jun 25 06:22:57 PM PDT 24
Finished Jun 25 06:23:34 PM PDT 24
Peak memory 251352 kb
Host smart-20bb89d1-fa5e-4f3b-8db3-89b547ac3398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370794348 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_failure.2370794348
Directory /workspace/26.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_post_trans.3885511189
Short name T812
Test name
Test status
Simulation time 346402323 ps
CPU time 7.04 seconds
Started Jun 25 06:22:53 PM PDT 24
Finished Jun 25 06:23:01 PM PDT 24
Peak memory 247020 kb
Host smart-2cef4094-8ed8-4bdd-8a37-919410aa3f24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885511189 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_post_trans.3885511189
Directory /workspace/26.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all.39496967
Short name T455
Test name
Test status
Simulation time 22710334362 ps
CPU time 136.5 seconds
Started Jun 25 06:23:02 PM PDT 24
Finished Jun 25 06:25:20 PM PDT 24
Peak memory 277244 kb
Host smart-b52b8bf6-cecf-4e13-882a-ce8dae1e5e8a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39496967 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_T
EST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
6.lc_ctrl_stress_all.39496967
Directory /workspace/26.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.lc_ctrl_volatile_unlock_smoke.2401882520
Short name T677
Test name
Test status
Simulation time 47316117 ps
CPU time 1.09 seconds
Started Jun 25 06:23:02 PM PDT 24
Finished Jun 25 06:23:04 PM PDT 24
Peak memory 212312 kb
Host smart-b7d723a3-10cc-40e9-a130-02d3b7e95d27
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401882520 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_c
trl_volatile_unlock_smoke.2401882520
Directory /workspace/26.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_alert_test.2311400819
Short name T547
Test name
Test status
Simulation time 166554797 ps
CPU time 1.12 seconds
Started Jun 25 06:23:12 PM PDT 24
Finished Jun 25 06:23:15 PM PDT 24
Peak memory 209356 kb
Host smart-cbe72768-0fdc-4a38-ab32-2e6548609969
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311400819 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_alert_test.2311400819
Directory /workspace/27.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.lc_ctrl_errors.3365606910
Short name T838
Test name
Test status
Simulation time 983873320 ps
CPU time 13.77 seconds
Started Jun 25 06:23:10 PM PDT 24
Finished Jun 25 06:23:26 PM PDT 24
Peak memory 218484 kb
Host smart-44adcc6b-f90c-4a24-b065-7dcce5659169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365606910 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_errors.3365606910
Directory /workspace/27.lc_ctrl_errors/latest

Test location /workspace/coverage/default/27.lc_ctrl_jtag_access.2620314655
Short name T23
Test name
Test status
Simulation time 681883213 ps
CPU time 7.19 seconds
Started Jun 25 06:23:10 PM PDT 24
Finished Jun 25 06:23:19 PM PDT 24
Peak memory 217600 kb
Host smart-950bbf7a-cc7d-417d-9705-906b39893217
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620314655 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_jtag_access.2620314655
Directory /workspace/27.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/27.lc_ctrl_prog_failure.3659184058
Short name T238
Test name
Test status
Simulation time 125956996 ps
CPU time 3.86 seconds
Started Jun 25 06:23:01 PM PDT 24
Finished Jun 25 06:23:06 PM PDT 24
Peak memory 223072 kb
Host smart-fb1aaa36-1acd-47c2-9521-17f32d199a9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659184058 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_prog_failure.3659184058
Directory /workspace/27.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_mubi.1551000080
Short name T499
Test name
Test status
Simulation time 225255042 ps
CPU time 8.83 seconds
Started Jun 25 06:23:10 PM PDT 24
Finished Jun 25 06:23:20 PM PDT 24
Peak memory 219296 kb
Host smart-91050504-d093-442c-9cd6-924b3bad54ad
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551000080 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_mubi.1551000080
Directory /workspace/27.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_digest.3615284948
Short name T241
Test name
Test status
Simulation time 2873056566 ps
CPU time 13.51 seconds
Started Jun 25 06:23:09 PM PDT 24
Finished Jun 25 06:23:25 PM PDT 24
Peak memory 218620 kb
Host smart-629bf37e-fd14-43a8-9d71-c2a85c2e09b8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615284948 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_d
igest.3615284948
Directory /workspace/27.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_mux.1741809242
Short name T790
Test name
Test status
Simulation time 317950223 ps
CPU time 8.08 seconds
Started Jun 25 06:23:10 PM PDT 24
Finished Jun 25 06:23:20 PM PDT 24
Peak memory 218568 kb
Host smart-a918617f-8fee-4dff-9006-f066ca49d4bc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741809242 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_mux.
1741809242
Directory /workspace/27.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/27.lc_ctrl_security_escalation.1912463272
Short name T267
Test name
Test status
Simulation time 1252429161 ps
CPU time 7.44 seconds
Started Jun 25 06:23:09 PM PDT 24
Finished Jun 25 06:23:17 PM PDT 24
Peak memory 226448 kb
Host smart-2d39c153-76e3-4508-94cc-4bceeb440c0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912463272 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_security_escalation.1912463272
Directory /workspace/27.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/27.lc_ctrl_smoke.854547724
Short name T432
Test name
Test status
Simulation time 177271232 ps
CPU time 2.72 seconds
Started Jun 25 06:23:02 PM PDT 24
Finished Jun 25 06:23:06 PM PDT 24
Peak memory 218064 kb
Host smart-fa1f801f-8d6c-49b9-87ae-e86d07941c3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854547724 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_smoke.854547724
Directory /workspace/27.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_failure.4028165059
Short name T771
Test name
Test status
Simulation time 3344391798 ps
CPU time 29.94 seconds
Started Jun 25 06:23:02 PM PDT 24
Finished Jun 25 06:23:34 PM PDT 24
Peak memory 251408 kb
Host smart-57a7977d-5782-45e6-90fb-5e05605130c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028165059 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_failure.4028165059
Directory /workspace/27.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_post_trans.3839440291
Short name T268
Test name
Test status
Simulation time 257002685 ps
CPU time 6.82 seconds
Started Jun 25 06:23:03 PM PDT 24
Finished Jun 25 06:23:11 PM PDT 24
Peak memory 247208 kb
Host smart-f03ad1fc-4401-4ba1-81d4-5149d74b0e45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839440291 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_post_trans.3839440291
Directory /workspace/27.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all.2659109
Short name T741
Test name
Test status
Simulation time 3691347226 ps
CPU time 111.63 seconds
Started Jun 25 06:23:10 PM PDT 24
Finished Jun 25 06:25:04 PM PDT 24
Peak memory 267972 kb
Host smart-0e9488ba-8ae4-4577-902b-46e55d56eb9d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659109 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TE
ST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27
.lc_ctrl_stress_all.2659109
Directory /workspace/27.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.lc_ctrl_volatile_unlock_smoke.1393881950
Short name T591
Test name
Test status
Simulation time 10574044 ps
CPU time 0.74 seconds
Started Jun 25 06:23:02 PM PDT 24
Finished Jun 25 06:23:05 PM PDT 24
Peak memory 208388 kb
Host smart-1e6da864-f340-48f7-867e-c76424eae196
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393881950 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_c
trl_volatile_unlock_smoke.1393881950
Directory /workspace/27.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_alert_test.1784644436
Short name T102
Test name
Test status
Simulation time 15039964 ps
CPU time 1.02 seconds
Started Jun 25 06:23:11 PM PDT 24
Finished Jun 25 06:23:14 PM PDT 24
Peak memory 209360 kb
Host smart-0d8dd430-bb63-49f2-8153-d4d33587314a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784644436 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_alert_test.1784644436
Directory /workspace/28.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.lc_ctrl_errors.448046338
Short name T438
Test name
Test status
Simulation time 812121763 ps
CPU time 8.5 seconds
Started Jun 25 06:23:10 PM PDT 24
Finished Jun 25 06:23:20 PM PDT 24
Peak memory 218624 kb
Host smart-cf8c4242-e4b9-4d5b-bd10-9b967110c6fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448046338 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_errors.448046338
Directory /workspace/28.lc_ctrl_errors/latest

Test location /workspace/coverage/default/28.lc_ctrl_jtag_access.2293576958
Short name T782
Test name
Test status
Simulation time 5562401532 ps
CPU time 6.69 seconds
Started Jun 25 06:23:11 PM PDT 24
Finished Jun 25 06:23:20 PM PDT 24
Peak memory 218072 kb
Host smart-e92fadbb-2e09-4919-a355-11c733206ca8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293576958 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_jtag_access.2293576958
Directory /workspace/28.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/28.lc_ctrl_prog_failure.2061791020
Short name T426
Test name
Test status
Simulation time 87957151 ps
CPU time 4.13 seconds
Started Jun 25 06:23:13 PM PDT 24
Finished Jun 25 06:23:18 PM PDT 24
Peak memory 222772 kb
Host smart-7a3f0b9c-0e6b-4b88-bd6f-4533f4027fd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061791020 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_prog_failure.2061791020
Directory /workspace/28.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_mubi.1540181718
Short name T385
Test name
Test status
Simulation time 294312635 ps
CPU time 11.26 seconds
Started Jun 25 06:23:10 PM PDT 24
Finished Jun 25 06:23:23 PM PDT 24
Peak memory 226440 kb
Host smart-7dced0b3-ca08-4760-b386-15e1ab7c7bd4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540181718 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_mubi.1540181718
Directory /workspace/28.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_digest.2789580446
Short name T405
Test name
Test status
Simulation time 1543918349 ps
CPU time 10.53 seconds
Started Jun 25 06:23:08 PM PDT 24
Finished Jun 25 06:23:20 PM PDT 24
Peak memory 218500 kb
Host smart-30c3e432-de72-4652-84fc-64525fe700d8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789580446 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_d
igest.2789580446
Directory /workspace/28.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_mux.376464930
Short name T797
Test name
Test status
Simulation time 2659082727 ps
CPU time 9.6 seconds
Started Jun 25 06:23:12 PM PDT 24
Finished Jun 25 06:23:23 PM PDT 24
Peak memory 218568 kb
Host smart-a69cc135-4264-4735-9544-1fa56aa421d2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376464930 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_mux.376464930
Directory /workspace/28.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/28.lc_ctrl_security_escalation.821625899
Short name T59
Test name
Test status
Simulation time 1489589828 ps
CPU time 12.48 seconds
Started Jun 25 06:23:10 PM PDT 24
Finished Jun 25 06:23:24 PM PDT 24
Peak memory 218688 kb
Host smart-9ddd5fd3-789c-4f9c-97aa-c59fe9096215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821625899 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_security_escalation.821625899
Directory /workspace/28.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/28.lc_ctrl_smoke.2536391991
Short name T342
Test name
Test status
Simulation time 318288481 ps
CPU time 3.91 seconds
Started Jun 25 06:23:11 PM PDT 24
Finished Jun 25 06:23:17 PM PDT 24
Peak memory 218064 kb
Host smart-d5d7bba9-6258-4db1-a707-bdd69a78c639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536391991 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_smoke.2536391991
Directory /workspace/28.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_failure.4153348920
Short name T256
Test name
Test status
Simulation time 1331164897 ps
CPU time 31.04 seconds
Started Jun 25 06:23:12 PM PDT 24
Finished Jun 25 06:23:45 PM PDT 24
Peak memory 251248 kb
Host smart-794a12bd-a835-4ada-8eed-5d1f69cb9a0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153348920 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_failure.4153348920
Directory /workspace/28.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_post_trans.1794940954
Short name T539
Test name
Test status
Simulation time 549170437 ps
CPU time 7.59 seconds
Started Jun 25 06:23:13 PM PDT 24
Finished Jun 25 06:23:22 PM PDT 24
Peak memory 251308 kb
Host smart-b676af1e-52e3-45b2-88d3-84dcffbcee85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794940954 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_post_trans.1794940954
Directory /workspace/28.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/28.lc_ctrl_stress_all.2513583310
Short name T84
Test name
Test status
Simulation time 5278512048 ps
CPU time 93.47 seconds
Started Jun 25 06:23:11 PM PDT 24
Finished Jun 25 06:24:46 PM PDT 24
Peak memory 226512 kb
Host smart-87b44263-a109-4139-9faf-ceb1f3a51fca
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513583310 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.lc_ctrl_stress_all.2513583310
Directory /workspace/28.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.lc_ctrl_volatile_unlock_smoke.2987215842
Short name T802
Test name
Test status
Simulation time 59563969 ps
CPU time 0.83 seconds
Started Jun 25 06:23:09 PM PDT 24
Finished Jun 25 06:23:11 PM PDT 24
Peak memory 209372 kb
Host smart-c278c0eb-5968-462e-b87e-564e838c8540
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987215842 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_c
trl_volatile_unlock_smoke.2987215842
Directory /workspace/28.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_alert_test.3398198594
Short name T272
Test name
Test status
Simulation time 30578432 ps
CPU time 1.41 seconds
Started Jun 25 06:23:17 PM PDT 24
Finished Jun 25 06:23:20 PM PDT 24
Peak memory 209524 kb
Host smart-3d2e9790-59f3-4b27-ae53-1040e7f5991b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398198594 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_alert_test.3398198594
Directory /workspace/29.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.lc_ctrl_errors.4253423129
Short name T850
Test name
Test status
Simulation time 1152798616 ps
CPU time 9.06 seconds
Started Jun 25 06:23:18 PM PDT 24
Finished Jun 25 06:23:29 PM PDT 24
Peak memory 218752 kb
Host smart-bb7b1b54-7a1d-4fea-8b17-c5c3ddf65773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253423129 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_errors.4253423129
Directory /workspace/29.lc_ctrl_errors/latest

Test location /workspace/coverage/default/29.lc_ctrl_jtag_access.2806954656
Short name T364
Test name
Test status
Simulation time 834902567 ps
CPU time 2.05 seconds
Started Jun 25 06:23:23 PM PDT 24
Finished Jun 25 06:23:27 PM PDT 24
Peak memory 217352 kb
Host smart-209cafcd-ceba-483d-b96c-db2fad47df13
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806954656 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_jtag_access.2806954656
Directory /workspace/29.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/29.lc_ctrl_prog_failure.4203860990
Short name T318
Test name
Test status
Simulation time 45478898 ps
CPU time 2.2 seconds
Started Jun 25 06:23:18 PM PDT 24
Finished Jun 25 06:23:22 PM PDT 24
Peak memory 222564 kb
Host smart-78eb5bea-9e72-4765-9611-9de9373ee914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203860990 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_prog_failure.4203860990
Directory /workspace/29.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_mubi.4007208559
Short name T49
Test name
Test status
Simulation time 3276024243 ps
CPU time 18.15 seconds
Started Jun 25 06:23:15 PM PDT 24
Finished Jun 25 06:23:34 PM PDT 24
Peak memory 226504 kb
Host smart-8ac2c297-ee6a-425d-87c0-43a2585af188
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007208559 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_mubi.4007208559
Directory /workspace/29.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_digest.2583133682
Short name T97
Test name
Test status
Simulation time 312811529 ps
CPU time 13.2 seconds
Started Jun 25 06:23:22 PM PDT 24
Finished Jun 25 06:23:38 PM PDT 24
Peak memory 218608 kb
Host smart-d8798267-66ab-4b6b-b8c1-613da2c27e65
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583133682 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_d
igest.2583133682
Directory /workspace/29.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_mux.1799558312
Short name T629
Test name
Test status
Simulation time 981868896 ps
CPU time 9.69 seconds
Started Jun 25 06:23:18 PM PDT 24
Finished Jun 25 06:23:30 PM PDT 24
Peak memory 218604 kb
Host smart-338eed52-3489-47f0-ae27-dce597fa7bdc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799558312 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_mux.
1799558312
Directory /workspace/29.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/29.lc_ctrl_smoke.1934991461
Short name T758
Test name
Test status
Simulation time 66186444 ps
CPU time 4.02 seconds
Started Jun 25 06:23:17 PM PDT 24
Finished Jun 25 06:23:22 PM PDT 24
Peak memory 218032 kb
Host smart-8c358284-1095-4415-91b2-63d53639a2b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934991461 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_smoke.1934991461
Directory /workspace/29.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_failure.3989656427
Short name T635
Test name
Test status
Simulation time 884221969 ps
CPU time 27.25 seconds
Started Jun 25 06:23:19 PM PDT 24
Finished Jun 25 06:23:49 PM PDT 24
Peak memory 251260 kb
Host smart-2ff832dd-6eea-4349-bcd6-727d2f16b1cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989656427 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_failure.3989656427
Directory /workspace/29.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_post_trans.2465931250
Short name T243
Test name
Test status
Simulation time 632166909 ps
CPU time 7.51 seconds
Started Jun 25 06:23:18 PM PDT 24
Finished Jun 25 06:23:28 PM PDT 24
Peak memory 251320 kb
Host smart-a895a31d-e955-42cc-acd1-368e4cb8290b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465931250 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_post_trans.2465931250
Directory /workspace/29.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/29.lc_ctrl_stress_all.1743588969
Short name T316
Test name
Test status
Simulation time 7448988228 ps
CPU time 75.07 seconds
Started Jun 25 06:23:18 PM PDT 24
Finished Jun 25 06:24:34 PM PDT 24
Peak memory 277016 kb
Host smart-75bd3d47-f210-4a6d-a9b2-20ce8d6af0d4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743588969 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.lc_ctrl_stress_all.1743588969
Directory /workspace/29.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.lc_ctrl_volatile_unlock_smoke.2110001138
Short name T543
Test name
Test status
Simulation time 43589651 ps
CPU time 0.86 seconds
Started Jun 25 06:23:19 PM PDT 24
Finished Jun 25 06:23:22 PM PDT 24
Peak memory 212256 kb
Host smart-04d6e743-96e6-4d43-93cb-fb9f9fcc839f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110001138 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_c
trl_volatile_unlock_smoke.2110001138
Directory /workspace/29.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_alert_test.177087390
Short name T839
Test name
Test status
Simulation time 27220773 ps
CPU time 1.19 seconds
Started Jun 25 06:19:35 PM PDT 24
Finished Jun 25 06:19:37 PM PDT 24
Peak memory 209492 kb
Host smart-558d46f6-9b55-47da-9b89-328f7117974c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177087390 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_alert_test.177087390
Directory /workspace/3.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.lc_ctrl_claim_transition_if.2406598168
Short name T187
Test name
Test status
Simulation time 11835708 ps
CPU time 0.94 seconds
Started Jun 25 06:19:28 PM PDT 24
Finished Jun 25 06:19:30 PM PDT 24
Peak memory 209388 kb
Host smart-15900e5f-6633-427d-905a-2cbb16cd6e1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406598168 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_claim_transition_if.2406598168
Directory /workspace/3.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/3.lc_ctrl_errors.3071955044
Short name T532
Test name
Test status
Simulation time 2862733719 ps
CPU time 15.95 seconds
Started Jun 25 06:19:28 PM PDT 24
Finished Jun 25 06:19:45 PM PDT 24
Peak memory 226496 kb
Host smart-ba7b4579-169f-426a-92fd-a26d191364d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071955044 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_errors.3071955044
Directory /workspace/3.lc_ctrl_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_access.1318446885
Short name T815
Test name
Test status
Simulation time 727365696 ps
CPU time 9.45 seconds
Started Jun 25 06:19:37 PM PDT 24
Finished Jun 25 06:19:47 PM PDT 24
Peak memory 217704 kb
Host smart-122de769-f015-4fb8-a0aa-720af25a744e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318446885 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_access.1318446885
Directory /workspace/3.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_errors.1206557056
Short name T559
Test name
Test status
Simulation time 2793696262 ps
CPU time 40.98 seconds
Started Jun 25 06:19:34 PM PDT 24
Finished Jun 25 06:20:15 PM PDT 24
Peak memory 226440 kb
Host smart-d86655c9-5313-467e-a415-cda0a815849d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206557056 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_er
rors.1206557056
Directory /workspace/3.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_priority.3697213321
Short name T587
Test name
Test status
Simulation time 533187897 ps
CPU time 15.44 seconds
Started Jun 25 06:19:34 PM PDT 24
Finished Jun 25 06:19:50 PM PDT 24
Peak memory 217740 kb
Host smart-cae51a00-7688-417e-8ad2-392dc7132617
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697213321 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_priority.3
697213321
Directory /workspace/3.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_prog_failure.3918830065
Short name T842
Test name
Test status
Simulation time 1146003829 ps
CPU time 19.96 seconds
Started Jun 25 06:19:34 PM PDT 24
Finished Jun 25 06:19:55 PM PDT 24
Peak memory 225664 kb
Host smart-1d69646b-2eb3-40ce-9a51-49e19d4f60ce
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918830065 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag
_prog_failure.3918830065
Directory /workspace/3.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_regwen_during_op.1451726068
Short name T300
Test name
Test status
Simulation time 1117828679 ps
CPU time 32.34 seconds
Started Jun 25 06:19:36 PM PDT 24
Finished Jun 25 06:20:09 PM PDT 24
Peak memory 217976 kb
Host smart-bfd4460d-030e-4ee9-8842-e203ef9b0098
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451726068 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_regwen_during_op.1451726068
Directory /workspace/3.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_smoke.3082443510
Short name T475
Test name
Test status
Simulation time 631622618 ps
CPU time 4.91 seconds
Started Jun 25 06:19:27 PM PDT 24
Finished Jun 25 06:19:33 PM PDT 24
Peak memory 217976 kb
Host smart-c9f11a37-8877-45bf-aa37-410519bd4bad
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082443510 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_smoke.
3082443510
Directory /workspace/3.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_failure.469889747
Short name T515
Test name
Test status
Simulation time 5623887858 ps
CPU time 33.24 seconds
Started Jun 25 06:19:28 PM PDT 24
Finished Jun 25 06:20:02 PM PDT 24
Peak memory 275888 kb
Host smart-3b5d7285-8999-4ad5-bc2a-dee65ddfa406
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469889747 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag
_state_failure.469889747
Directory /workspace/3.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_post_trans.311790920
Short name T851
Test name
Test status
Simulation time 15851488699 ps
CPU time 17.73 seconds
Started Jun 25 06:19:36 PM PDT 24
Finished Jun 25 06:19:54 PM PDT 24
Peak memory 250952 kb
Host smart-cc65c6f2-426e-43e4-9df4-98f0fc8f4fc2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311790920 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_j
tag_state_post_trans.311790920
Directory /workspace/3.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_prog_failure.1086395997
Short name T545
Test name
Test status
Simulation time 212123391 ps
CPU time 1.9 seconds
Started Jun 25 06:19:27 PM PDT 24
Finished Jun 25 06:19:30 PM PDT 24
Peak memory 222460 kb
Host smart-623d3090-429d-42a5-a8cf-b204a29d7329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086395997 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_prog_failure.1086395997
Directory /workspace/3.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_regwen_during_op.1346524214
Short name T696
Test name
Test status
Simulation time 400408683 ps
CPU time 11.16 seconds
Started Jun 25 06:19:27 PM PDT 24
Finished Jun 25 06:19:39 PM PDT 24
Peak memory 214928 kb
Host smart-2f42613a-7ff4-42a1-b550-0344b4347fa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346524214 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_regwen_during_op.1346524214
Directory /workspace/3.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_cm.3549285453
Short name T100
Test name
Test status
Simulation time 111841240 ps
CPU time 24.19 seconds
Started Jun 25 06:19:34 PM PDT 24
Finished Jun 25 06:19:59 PM PDT 24
Peak memory 282168 kb
Host smart-1d4c2e38-70a3-49fe-8a4e-c9ce36f8e31e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549285453 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_cm.3549285453
Directory /workspace/3.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_mubi.4141656326
Short name T129
Test name
Test status
Simulation time 303822506 ps
CPU time 11.88 seconds
Started Jun 25 06:19:34 PM PDT 24
Finished Jun 25 06:19:47 PM PDT 24
Peak memory 226468 kb
Host smart-b8e1ebf7-246b-4c12-b950-7afe2ca50547
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141656326 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_mubi.4141656326
Directory /workspace/3.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_digest.2974883047
Short name T312
Test name
Test status
Simulation time 311339879 ps
CPU time 12.09 seconds
Started Jun 25 06:19:34 PM PDT 24
Finished Jun 25 06:19:46 PM PDT 24
Peak memory 218536 kb
Host smart-b3d982ba-874b-4075-a569-2c293edca73b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974883047 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_di
gest.2974883047
Directory /workspace/3.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_mux.335646997
Short name T131
Test name
Test status
Simulation time 894319358 ps
CPU time 16.59 seconds
Started Jun 25 06:19:35 PM PDT 24
Finished Jun 25 06:19:52 PM PDT 24
Peak memory 218588 kb
Host smart-fcb7eacb-e37e-4319-8463-b3026866c8fc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335646997 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_mux.335646997
Directory /workspace/3.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/3.lc_ctrl_security_escalation.4173231765
Short name T674
Test name
Test status
Simulation time 277222941 ps
CPU time 11.12 seconds
Started Jun 25 06:19:26 PM PDT 24
Finished Jun 25 06:19:38 PM PDT 24
Peak memory 226436 kb
Host smart-8aa1491b-de28-41b0-99dd-b8c4cd669e1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173231765 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_security_escalation.4173231765
Directory /workspace/3.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/3.lc_ctrl_smoke.450560023
Short name T571
Test name
Test status
Simulation time 22044278 ps
CPU time 1.03 seconds
Started Jun 25 06:19:27 PM PDT 24
Finished Jun 25 06:19:29 PM PDT 24
Peak memory 212652 kb
Host smart-e30573bf-c62f-4d3c-ad9d-31fee0dcf4bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450560023 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_smoke.450560023
Directory /workspace/3.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_failure.3504942037
Short name T544
Test name
Test status
Simulation time 561728042 ps
CPU time 29.57 seconds
Started Jun 25 06:19:28 PM PDT 24
Finished Jun 25 06:19:59 PM PDT 24
Peak memory 251324 kb
Host smart-263166ca-8393-48e8-87bf-4eac00c09403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504942037 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_failure.3504942037
Directory /workspace/3.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_post_trans.1053156937
Short name T792
Test name
Test status
Simulation time 67714971 ps
CPU time 6.41 seconds
Started Jun 25 06:19:26 PM PDT 24
Finished Jun 25 06:19:34 PM PDT 24
Peak memory 250696 kb
Host smart-ba5e3950-f036-4c3c-8e71-114e7edf886d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053156937 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_post_trans.1053156937
Directory /workspace/3.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_stress_all.4231851230
Short name T817
Test name
Test status
Simulation time 43247107303 ps
CPU time 70.53 seconds
Started Jun 25 06:19:34 PM PDT 24
Finished Jun 25 06:20:46 PM PDT 24
Peak memory 226392 kb
Host smart-9c0a0a5f-5bd3-49b7-bfa7-3afe3095e0d4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231851230 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.lc_ctrl_stress_all.4231851230
Directory /workspace/3.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.lc_ctrl_stress_all_with_rand_reset.3062963587
Short name T55
Test name
Test status
Simulation time 42172706131 ps
CPU time 1424.45 seconds
Started Jun 25 06:19:34 PM PDT 24
Finished Jun 25 06:43:20 PM PDT 24
Peak memory 422520 kb
Host smart-e59616f2-7c93-4179-a0c4-3d9890b23749
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3062963587 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_stress_all_with_rand_reset.3062963587
Directory /workspace/3.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.lc_ctrl_volatile_unlock_smoke.1211924959
Short name T422
Test name
Test status
Simulation time 33633854 ps
CPU time 0.78 seconds
Started Jun 25 06:19:26 PM PDT 24
Finished Jun 25 06:19:28 PM PDT 24
Peak memory 209064 kb
Host smart-c8f998c1-28cf-44e6-a190-b227be170a74
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211924959 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ct
rl_volatile_unlock_smoke.1211924959
Directory /workspace/3.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_alert_test.2068118677
Short name T80
Test name
Test status
Simulation time 31810733 ps
CPU time 0.99 seconds
Started Jun 25 06:23:24 PM PDT 24
Finished Jun 25 06:23:27 PM PDT 24
Peak memory 209360 kb
Host smart-0f9b02eb-c836-4f51-8f64-409971164818
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068118677 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_alert_test.2068118677
Directory /workspace/30.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.lc_ctrl_errors.1133483641
Short name T567
Test name
Test status
Simulation time 403325373 ps
CPU time 13.07 seconds
Started Jun 25 06:23:26 PM PDT 24
Finished Jun 25 06:23:41 PM PDT 24
Peak memory 218628 kb
Host smart-e37cc950-ac61-4141-950c-8967d6f651ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133483641 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_errors.1133483641
Directory /workspace/30.lc_ctrl_errors/latest

Test location /workspace/coverage/default/30.lc_ctrl_jtag_access.3110172379
Short name T417
Test name
Test status
Simulation time 6249053296 ps
CPU time 4.75 seconds
Started Jun 25 06:23:31 PM PDT 24
Finished Jun 25 06:23:39 PM PDT 24
Peak memory 218108 kb
Host smart-3621369f-fe1a-4bd0-a3c9-08251f8955ac
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110172379 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_jtag_access.3110172379
Directory /workspace/30.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/30.lc_ctrl_prog_failure.274986506
Short name T828
Test name
Test status
Simulation time 69588027 ps
CPU time 2.33 seconds
Started Jun 25 06:23:22 PM PDT 24
Finished Jun 25 06:23:27 PM PDT 24
Peak memory 218580 kb
Host smart-22b224c1-eec1-4b73-b5fc-b9a134db5ea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274986506 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_prog_failure.274986506
Directory /workspace/30.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_mubi.3254158712
Short name T679
Test name
Test status
Simulation time 1000215976 ps
CPU time 15.06 seconds
Started Jun 25 06:23:26 PM PDT 24
Finished Jun 25 06:23:43 PM PDT 24
Peak memory 226436 kb
Host smart-8444e97a-2677-4c09-bf10-d7de06c8fda9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254158712 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_mubi.3254158712
Directory /workspace/30.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_digest.3251407428
Short name T685
Test name
Test status
Simulation time 276490025 ps
CPU time 9.48 seconds
Started Jun 25 06:23:26 PM PDT 24
Finished Jun 25 06:23:38 PM PDT 24
Peak memory 218608 kb
Host smart-09ba0c22-3aa1-4cf2-b3c1-80e3dbb6c683
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251407428 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_d
igest.3251407428
Directory /workspace/30.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_mux.1859703488
Short name T764
Test name
Test status
Simulation time 422784461 ps
CPU time 8.31 seconds
Started Jun 25 06:23:26 PM PDT 24
Finished Jun 25 06:23:37 PM PDT 24
Peak memory 218584 kb
Host smart-9c0e325d-a08e-4d7c-b15b-d88bb4f73e53
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859703488 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_mux.
1859703488
Directory /workspace/30.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/30.lc_ctrl_security_escalation.3044915944
Short name T833
Test name
Test status
Simulation time 550009310 ps
CPU time 9.61 seconds
Started Jun 25 06:23:24 PM PDT 24
Finished Jun 25 06:23:35 PM PDT 24
Peak memory 218728 kb
Host smart-511b4848-7b19-4dc4-a2c4-3fe3ce36dafa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044915944 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_security_escalation.3044915944
Directory /workspace/30.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/30.lc_ctrl_smoke.3213191392
Short name T76
Test name
Test status
Simulation time 30096563 ps
CPU time 2.29 seconds
Started Jun 25 06:23:19 PM PDT 24
Finished Jun 25 06:23:24 PM PDT 24
Peak memory 218136 kb
Host smart-3f55b0b3-eae4-40a1-91cf-f4e751e63ffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213191392 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_smoke.3213191392
Directory /workspace/30.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_failure.3113154724
Short name T277
Test name
Test status
Simulation time 1195573298 ps
CPU time 30.8 seconds
Started Jun 25 06:23:22 PM PDT 24
Finished Jun 25 06:23:56 PM PDT 24
Peak memory 251268 kb
Host smart-23f9fe70-3f8f-4069-8461-d2c698947ba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113154724 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_failure.3113154724
Directory /workspace/30.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_post_trans.1250601801
Short name T640
Test name
Test status
Simulation time 763020097 ps
CPU time 7.53 seconds
Started Jun 25 06:23:18 PM PDT 24
Finished Jun 25 06:23:28 PM PDT 24
Peak memory 247956 kb
Host smart-ccf65793-797d-4102-a3bd-d9aadf60823b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250601801 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_post_trans.1250601801
Directory /workspace/30.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all.1855637870
Short name T439
Test name
Test status
Simulation time 9024279905 ps
CPU time 95.72 seconds
Started Jun 25 06:23:31 PM PDT 24
Finished Jun 25 06:25:09 PM PDT 24
Peak memory 226488 kb
Host smart-628fa219-692d-4575-a6db-35d1a61a0caa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855637870 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.lc_ctrl_stress_all.1855637870
Directory /workspace/30.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.lc_ctrl_volatile_unlock_smoke.2576913983
Short name T570
Test name
Test status
Simulation time 13682961 ps
CPU time 0.81 seconds
Started Jun 25 06:23:18 PM PDT 24
Finished Jun 25 06:23:21 PM PDT 24
Peak memory 209216 kb
Host smart-a7a57c45-ea13-489e-80c0-6e288a8d5ddf
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576913983 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_c
trl_volatile_unlock_smoke.2576913983
Directory /workspace/30.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_alert_test.899731663
Short name T254
Test name
Test status
Simulation time 45642643 ps
CPU time 0.85 seconds
Started Jun 25 06:23:36 PM PDT 24
Finished Jun 25 06:23:40 PM PDT 24
Peak memory 209172 kb
Host smart-9660b22e-1ab7-486c-8a51-d138437c214e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899731663 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_alert_test.899731663
Directory /workspace/31.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.lc_ctrl_errors.3437708531
Short name T718
Test name
Test status
Simulation time 372885427 ps
CPU time 12.27 seconds
Started Jun 25 06:23:25 PM PDT 24
Finished Jun 25 06:23:39 PM PDT 24
Peak memory 226452 kb
Host smart-21062a41-d5af-4e61-b5eb-759001b5e711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437708531 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_errors.3437708531
Directory /workspace/31.lc_ctrl_errors/latest

Test location /workspace/coverage/default/31.lc_ctrl_jtag_access.1499606287
Short name T683
Test name
Test status
Simulation time 405578359 ps
CPU time 2.57 seconds
Started Jun 25 06:23:27 PM PDT 24
Finished Jun 25 06:23:32 PM PDT 24
Peak memory 217540 kb
Host smart-6b16bf08-53db-4ea4-aeb2-8a06be20af91
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499606287 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_jtag_access.1499606287
Directory /workspace/31.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/31.lc_ctrl_prog_failure.1609342391
Short name T324
Test name
Test status
Simulation time 51638709 ps
CPU time 2.52 seconds
Started Jun 25 06:23:26 PM PDT 24
Finished Jun 25 06:23:30 PM PDT 24
Peak memory 222552 kb
Host smart-d3d53f26-c008-4356-bdca-37a938dac29a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609342391 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_prog_failure.1609342391
Directory /workspace/31.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_mubi.3751633864
Short name T680
Test name
Test status
Simulation time 833934893 ps
CPU time 10.26 seconds
Started Jun 25 06:23:26 PM PDT 24
Finished Jun 25 06:23:38 PM PDT 24
Peak memory 218632 kb
Host smart-55c19f15-e36e-41a8-b448-696977a2d713
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751633864 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_mubi.3751633864
Directory /workspace/31.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_digest.598793362
Short name T13
Test name
Test status
Simulation time 339344533 ps
CPU time 9.96 seconds
Started Jun 25 06:23:36 PM PDT 24
Finished Jun 25 06:23:48 PM PDT 24
Peak memory 218576 kb
Host smart-5b52f544-dbfe-41ab-92a7-4afb3e35f1fe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598793362 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_di
gest.598793362
Directory /workspace/31.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_mux.4079446036
Short name T404
Test name
Test status
Simulation time 2058247911 ps
CPU time 10.11 seconds
Started Jun 25 06:23:30 PM PDT 24
Finished Jun 25 06:23:44 PM PDT 24
Peak memory 218580 kb
Host smart-4c03089a-5b45-4865-bb65-e62055a22f79
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079446036 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_mux.
4079446036
Directory /workspace/31.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/31.lc_ctrl_security_escalation.1616459422
Short name T526
Test name
Test status
Simulation time 510017628 ps
CPU time 10.17 seconds
Started Jun 25 06:23:24 PM PDT 24
Finished Jun 25 06:23:36 PM PDT 24
Peak memory 218712 kb
Host smart-688e3f93-63ff-4f3e-990f-f1feae438c89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616459422 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_security_escalation.1616459422
Directory /workspace/31.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/31.lc_ctrl_smoke.1237078456
Short name T399
Test name
Test status
Simulation time 138012072 ps
CPU time 2.66 seconds
Started Jun 25 06:23:24 PM PDT 24
Finished Jun 25 06:23:28 PM PDT 24
Peak memory 215228 kb
Host smart-97a699f1-62cd-4bf8-bb12-a1128b8261ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237078456 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_smoke.1237078456
Directory /workspace/31.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_failure.1347300978
Short name T583
Test name
Test status
Simulation time 789704447 ps
CPU time 30.41 seconds
Started Jun 25 06:23:25 PM PDT 24
Finished Jun 25 06:23:57 PM PDT 24
Peak memory 251320 kb
Host smart-3368a3d6-cded-44c7-8aa3-a624295b2b32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347300978 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_failure.1347300978
Directory /workspace/31.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_post_trans.2984780848
Short name T762
Test name
Test status
Simulation time 1880623214 ps
CPU time 9.55 seconds
Started Jun 25 06:23:24 PM PDT 24
Finished Jun 25 06:23:35 PM PDT 24
Peak memory 251260 kb
Host smart-3ffffc8a-2c57-4eef-b543-2a901d2cd4bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984780848 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_post_trans.2984780848
Directory /workspace/31.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/31.lc_ctrl_stress_all.3070747899
Short name T865
Test name
Test status
Simulation time 8134015665 ps
CPU time 248.85 seconds
Started Jun 25 06:23:35 PM PDT 24
Finished Jun 25 06:27:47 PM PDT 24
Peak memory 251880 kb
Host smart-5d0f840d-5235-483e-84e7-2c946ff5933e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070747899 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.lc_ctrl_stress_all.3070747899
Directory /workspace/31.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.lc_ctrl_volatile_unlock_smoke.4137052608
Short name T257
Test name
Test status
Simulation time 16611143 ps
CPU time 1.29 seconds
Started Jun 25 06:23:31 PM PDT 24
Finished Jun 25 06:23:35 PM PDT 24
Peak memory 218036 kb
Host smart-dd05e81d-c6b0-4e77-81f1-262219177c9b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137052608 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_c
trl_volatile_unlock_smoke.4137052608
Directory /workspace/31.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_alert_test.312165540
Short name T522
Test name
Test status
Simulation time 24425145 ps
CPU time 1.12 seconds
Started Jun 25 06:23:35 PM PDT 24
Finished Jun 25 06:23:39 PM PDT 24
Peak memory 209328 kb
Host smart-9478dcb2-d91c-4712-9e21-5d3cef09e249
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312165540 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_alert_test.312165540
Directory /workspace/32.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.lc_ctrl_errors.3843445933
Short name T403
Test name
Test status
Simulation time 834066710 ps
CPU time 16.19 seconds
Started Jun 25 06:23:35 PM PDT 24
Finished Jun 25 06:23:53 PM PDT 24
Peak memory 218560 kb
Host smart-552e7fab-3548-4c3a-aa8f-496a74727ba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843445933 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_errors.3843445933
Directory /workspace/32.lc_ctrl_errors/latest

Test location /workspace/coverage/default/32.lc_ctrl_jtag_access.1224925703
Short name T28
Test name
Test status
Simulation time 1070659176 ps
CPU time 2.42 seconds
Started Jun 25 06:23:34 PM PDT 24
Finished Jun 25 06:23:39 PM PDT 24
Peak memory 217452 kb
Host smart-38c5b7c3-4cff-48a1-a4d8-c329c1e63805
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224925703 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_jtag_access.1224925703
Directory /workspace/32.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/32.lc_ctrl_prog_failure.453938523
Short name T652
Test name
Test status
Simulation time 803158783 ps
CPU time 3.45 seconds
Started Jun 25 06:23:35 PM PDT 24
Finished Jun 25 06:23:41 PM PDT 24
Peak memory 218560 kb
Host smart-1fe6cf6b-26d3-4447-9346-26320f0525a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453938523 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_prog_failure.453938523
Directory /workspace/32.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_mubi.2752480286
Short name T497
Test name
Test status
Simulation time 327297775 ps
CPU time 13.52 seconds
Started Jun 25 06:23:33 PM PDT 24
Finished Jun 25 06:23:49 PM PDT 24
Peak memory 226436 kb
Host smart-b50dd378-484c-4ad4-b055-007c06353b47
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752480286 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_mubi.2752480286
Directory /workspace/32.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_digest.1092608895
Short name T118
Test name
Test status
Simulation time 623189093 ps
CPU time 13 seconds
Started Jun 25 06:23:36 PM PDT 24
Finished Jun 25 06:23:52 PM PDT 24
Peak memory 218600 kb
Host smart-29e83742-3969-4c5f-8558-c9312c915737
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092608895 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_d
igest.1092608895
Directory /workspace/32.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_mux.1071953484
Short name T823
Test name
Test status
Simulation time 5959991709 ps
CPU time 12.99 seconds
Started Jun 25 06:23:34 PM PDT 24
Finished Jun 25 06:23:50 PM PDT 24
Peak memory 218636 kb
Host smart-ef2fc94c-104a-441f-9b8e-3c8e86f7646b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071953484 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_mux.
1071953484
Directory /workspace/32.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/32.lc_ctrl_security_escalation.1910894476
Short name T62
Test name
Test status
Simulation time 3784654927 ps
CPU time 16.84 seconds
Started Jun 25 06:23:36 PM PDT 24
Finished Jun 25 06:23:56 PM PDT 24
Peak memory 226504 kb
Host smart-150bd0b1-ba34-4b1b-a762-36091d8d384e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910894476 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_security_escalation.1910894476
Directory /workspace/32.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/32.lc_ctrl_smoke.1956951051
Short name T67
Test name
Test status
Simulation time 80833855 ps
CPU time 2.84 seconds
Started Jun 25 06:23:35 PM PDT 24
Finished Jun 25 06:23:41 PM PDT 24
Peak memory 214620 kb
Host smart-84d41f83-b4a3-417e-9516-aeda5c750485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956951051 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_smoke.1956951051
Directory /workspace/32.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_failure.1716295726
Short name T335
Test name
Test status
Simulation time 464058312 ps
CPU time 22.99 seconds
Started Jun 25 06:23:35 PM PDT 24
Finished Jun 25 06:24:00 PM PDT 24
Peak memory 251336 kb
Host smart-a8296dd9-5a49-462f-8a4f-ea756eb43802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716295726 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_failure.1716295726
Directory /workspace/32.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_post_trans.1802568651
Short name T682
Test name
Test status
Simulation time 236460126 ps
CPU time 7.25 seconds
Started Jun 25 06:23:38 PM PDT 24
Finished Jun 25 06:23:48 PM PDT 24
Peak memory 251260 kb
Host smart-3863b902-5845-416a-bccd-c9e2c4a76480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802568651 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_post_trans.1802568651
Directory /workspace/32.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all.2949579875
Short name T779
Test name
Test status
Simulation time 567111622 ps
CPU time 26.65 seconds
Started Jun 25 06:23:35 PM PDT 24
Finished Jun 25 06:24:04 PM PDT 24
Peak memory 251304 kb
Host smart-bb8304d8-0262-4b8d-899b-22cb36d85ea0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949579875 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.lc_ctrl_stress_all.2949579875
Directory /workspace/32.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.lc_ctrl_volatile_unlock_smoke.2927649204
Short name T197
Test name
Test status
Simulation time 15766134 ps
CPU time 1.01 seconds
Started Jun 25 06:23:35 PM PDT 24
Finished Jun 25 06:23:39 PM PDT 24
Peak memory 212276 kb
Host smart-20b49249-1dd6-4610-af5d-e0132d2142b8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927649204 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_c
trl_volatile_unlock_smoke.2927649204
Directory /workspace/32.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_alert_test.825808992
Short name T843
Test name
Test status
Simulation time 18596547 ps
CPU time 0.84 seconds
Started Jun 25 06:23:42 PM PDT 24
Finished Jun 25 06:23:47 PM PDT 24
Peak memory 209324 kb
Host smart-3ea7ec97-205c-418c-b329-6e86464e0370
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825808992 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_alert_test.825808992
Directory /workspace/33.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.lc_ctrl_errors.2767312155
Short name T738
Test name
Test status
Simulation time 1626709601 ps
CPU time 13.98 seconds
Started Jun 25 06:23:35 PM PDT 24
Finished Jun 25 06:23:51 PM PDT 24
Peak memory 218560 kb
Host smart-de11a45f-6e6b-4ce3-af3e-97d0eed90d19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767312155 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_errors.2767312155
Directory /workspace/33.lc_ctrl_errors/latest

Test location /workspace/coverage/default/33.lc_ctrl_jtag_access.2721518145
Short name T618
Test name
Test status
Simulation time 1650199837 ps
CPU time 4.27 seconds
Started Jun 25 06:23:35 PM PDT 24
Finished Jun 25 06:23:42 PM PDT 24
Peak memory 217456 kb
Host smart-7b4b9d24-ac45-4c5a-ae58-8eb1b13af9a0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721518145 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_jtag_access.2721518145
Directory /workspace/33.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/33.lc_ctrl_prog_failure.1730278802
Short name T193
Test name
Test status
Simulation time 80276246 ps
CPU time 2.3 seconds
Started Jun 25 06:23:36 PM PDT 24
Finished Jun 25 06:23:41 PM PDT 24
Peak memory 218632 kb
Host smart-9ead1ee1-bda1-4b5f-9300-b25d0cec4a2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730278802 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_prog_failure.1730278802
Directory /workspace/33.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_mubi.2087959563
Short name T196
Test name
Test status
Simulation time 1369090325 ps
CPU time 15.46 seconds
Started Jun 25 06:23:34 PM PDT 24
Finished Jun 25 06:23:52 PM PDT 24
Peak memory 218628 kb
Host smart-f9173ac9-e893-4cc3-9c16-116f5c9f457e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087959563 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_mubi.2087959563
Directory /workspace/33.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_digest.3754296967
Short name T844
Test name
Test status
Simulation time 229238437 ps
CPU time 10.11 seconds
Started Jun 25 06:23:42 PM PDT 24
Finished Jun 25 06:23:56 PM PDT 24
Peak memory 218600 kb
Host smart-e2cb25b0-0cb4-4821-b081-464f45fc647f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754296967 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_d
igest.3754296967
Directory /workspace/33.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_mux.639273011
Short name T520
Test name
Test status
Simulation time 1558914454 ps
CPU time 10.44 seconds
Started Jun 25 06:23:42 PM PDT 24
Finished Jun 25 06:23:57 PM PDT 24
Peak memory 218596 kb
Host smart-189233a1-6241-49a7-8637-60c68ab2d8d4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639273011 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_mux.639273011
Directory /workspace/33.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/33.lc_ctrl_security_escalation.1343479285
Short name T188
Test name
Test status
Simulation time 808352869 ps
CPU time 12.36 seconds
Started Jun 25 06:23:34 PM PDT 24
Finished Jun 25 06:23:49 PM PDT 24
Peak memory 226164 kb
Host smart-7a9a39e7-722b-4a17-a2ea-4091c43e0823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343479285 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_security_escalation.1343479285
Directory /workspace/33.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/33.lc_ctrl_smoke.491047228
Short name T41
Test name
Test status
Simulation time 47307901 ps
CPU time 3.36 seconds
Started Jun 25 06:23:35 PM PDT 24
Finished Jun 25 06:23:41 PM PDT 24
Peak memory 218076 kb
Host smart-684db6a7-38ed-49a6-ac11-0ed51765a070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491047228 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_smoke.491047228
Directory /workspace/33.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_failure.2624953891
Short name T325
Test name
Test status
Simulation time 271293763 ps
CPU time 26.98 seconds
Started Jun 25 06:23:34 PM PDT 24
Finished Jun 25 06:24:04 PM PDT 24
Peak memory 246980 kb
Host smart-1c7ec320-02e5-4985-ab72-c8c1ebc791eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624953891 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_failure.2624953891
Directory /workspace/33.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_post_trans.459082430
Short name T510
Test name
Test status
Simulation time 348737672 ps
CPU time 3.34 seconds
Started Jun 25 06:23:37 PM PDT 24
Finished Jun 25 06:23:44 PM PDT 24
Peak memory 223100 kb
Host smart-addce2fa-ffce-4117-93e5-d679b906ed6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459082430 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_post_trans.459082430
Directory /workspace/33.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all.2274086525
Short name T702
Test name
Test status
Simulation time 8876854030 ps
CPU time 180.88 seconds
Started Jun 25 06:23:44 PM PDT 24
Finished Jun 25 06:26:50 PM PDT 24
Peak memory 275456 kb
Host smart-854ccc0a-627d-4088-9610-bf63c2e90c6f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274086525 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.lc_ctrl_stress_all.2274086525
Directory /workspace/33.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.lc_ctrl_volatile_unlock_smoke.1562755984
Short name T656
Test name
Test status
Simulation time 41463754 ps
CPU time 0.78 seconds
Started Jun 25 06:23:36 PM PDT 24
Finished Jun 25 06:23:40 PM PDT 24
Peak memory 209384 kb
Host smart-29fb3c46-6e36-4a0b-8da6-dfd4f2d2ae5d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562755984 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_c
trl_volatile_unlock_smoke.1562755984
Directory /workspace/33.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_alert_test.2152641360
Short name T529
Test name
Test status
Simulation time 24133118 ps
CPU time 0.98 seconds
Started Jun 25 06:23:45 PM PDT 24
Finished Jun 25 06:23:51 PM PDT 24
Peak memory 209324 kb
Host smart-3e8d4ed5-edc2-42fb-a24a-5379c3525471
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152641360 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_alert_test.2152641360
Directory /workspace/34.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.lc_ctrl_errors.96221727
Short name T835
Test name
Test status
Simulation time 502241396 ps
CPU time 12.35 seconds
Started Jun 25 06:23:43 PM PDT 24
Finished Jun 25 06:24:01 PM PDT 24
Peak memory 218584 kb
Host smart-fd0765a3-d2f8-48a2-a14c-01e7128a7771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96221727 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_errors.96221727
Directory /workspace/34.lc_ctrl_errors/latest

Test location /workspace/coverage/default/34.lc_ctrl_jtag_access.3853284880
Short name T511
Test name
Test status
Simulation time 2769089689 ps
CPU time 7.85 seconds
Started Jun 25 06:23:45 PM PDT 24
Finished Jun 25 06:23:58 PM PDT 24
Peak memory 218128 kb
Host smart-47bb2496-b6ce-4686-9f7f-2ce83842b9ec
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853284880 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_jtag_access.3853284880
Directory /workspace/34.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/34.lc_ctrl_prog_failure.1521788698
Short name T464
Test name
Test status
Simulation time 87690822 ps
CPU time 4.08 seconds
Started Jun 25 06:23:44 PM PDT 24
Finished Jun 25 06:23:54 PM PDT 24
Peak memory 218612 kb
Host smart-4e639aea-85dc-4b9b-ad20-548b48c204a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521788698 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_prog_failure.1521788698
Directory /workspace/34.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_mubi.4110625930
Short name T401
Test name
Test status
Simulation time 561188254 ps
CPU time 11.47 seconds
Started Jun 25 06:23:44 PM PDT 24
Finished Jun 25 06:24:01 PM PDT 24
Peak memory 226504 kb
Host smart-550d1000-ca7b-443a-8d7e-8baf87a5c98a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110625930 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_mubi.4110625930
Directory /workspace/34.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_digest.2904342263
Short name T512
Test name
Test status
Simulation time 289473052 ps
CPU time 13.16 seconds
Started Jun 25 06:23:45 PM PDT 24
Finished Jun 25 06:24:04 PM PDT 24
Peak memory 218584 kb
Host smart-6de80c87-238a-4029-b315-ef479fcbc682
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904342263 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_d
igest.2904342263
Directory /workspace/34.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_mux.3449428182
Short name T472
Test name
Test status
Simulation time 612423693 ps
CPU time 12.53 seconds
Started Jun 25 06:23:46 PM PDT 24
Finished Jun 25 06:24:04 PM PDT 24
Peak memory 218552 kb
Host smart-467395ba-6e35-473b-a3d7-9532a5e29e1a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449428182 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_mux.
3449428182
Directory /workspace/34.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/34.lc_ctrl_security_escalation.2891830229
Short name T841
Test name
Test status
Simulation time 1366250204 ps
CPU time 14.21 seconds
Started Jun 25 06:23:44 PM PDT 24
Finished Jun 25 06:24:03 PM PDT 24
Peak memory 226412 kb
Host smart-94005650-a914-4075-9471-f7843103da35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891830229 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_security_escalation.2891830229
Directory /workspace/34.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/34.lc_ctrl_smoke.2510595145
Short name T836
Test name
Test status
Simulation time 1688643312 ps
CPU time 4.32 seconds
Started Jun 25 06:23:44 PM PDT 24
Finished Jun 25 06:23:54 PM PDT 24
Peak memory 218056 kb
Host smart-84dbfadb-61b3-4c71-90b6-5847cb568cbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510595145 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_smoke.2510595145
Directory /workspace/34.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_failure.412000625
Short name T739
Test name
Test status
Simulation time 285968445 ps
CPU time 28.37 seconds
Started Jun 25 06:23:45 PM PDT 24
Finished Jun 25 06:24:19 PM PDT 24
Peak memory 251296 kb
Host smart-459be9ed-6e71-4bc1-83b3-08811432b003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412000625 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_failure.412000625
Directory /workspace/34.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_post_trans.1334239609
Short name T687
Test name
Test status
Simulation time 624675528 ps
CPU time 10.68 seconds
Started Jun 25 06:23:45 PM PDT 24
Finished Jun 25 06:24:01 PM PDT 24
Peak memory 251312 kb
Host smart-6b7fce51-1979-4693-a277-732c43e9d68d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334239609 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_post_trans.1334239609
Directory /workspace/34.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all.978380825
Short name T301
Test name
Test status
Simulation time 18513269308 ps
CPU time 148.98 seconds
Started Jun 25 06:23:43 PM PDT 24
Finished Jun 25 06:26:18 PM PDT 24
Peak memory 284160 kb
Host smart-2fe091e5-e2ef-48cf-92bc-59d6184ac4b6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978380825 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.lc_ctrl_stress_all.978380825
Directory /workspace/34.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.lc_ctrl_volatile_unlock_smoke.4285108042
Short name T551
Test name
Test status
Simulation time 23502412 ps
CPU time 0.76 seconds
Started Jun 25 06:23:44 PM PDT 24
Finished Jun 25 06:23:50 PM PDT 24
Peak memory 208736 kb
Host smart-809da40c-24be-4ee3-a11d-4c1a18b524ed
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285108042 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_c
trl_volatile_unlock_smoke.4285108042
Directory /workspace/34.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_alert_test.3596450033
Short name T504
Test name
Test status
Simulation time 21905437 ps
CPU time 0.83 seconds
Started Jun 25 06:23:51 PM PDT 24
Finished Jun 25 06:23:56 PM PDT 24
Peak memory 209164 kb
Host smart-87e4ed42-fe2b-4bc5-87ba-c39283517648
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596450033 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_alert_test.3596450033
Directory /workspace/35.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.lc_ctrl_errors.2695289917
Short name T114
Test name
Test status
Simulation time 1341754855 ps
CPU time 12.82 seconds
Started Jun 25 06:23:43 PM PDT 24
Finished Jun 25 06:24:01 PM PDT 24
Peak memory 218588 kb
Host smart-f161fda3-0982-41b5-b14c-25e101b84075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695289917 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_errors.2695289917
Directory /workspace/35.lc_ctrl_errors/latest

Test location /workspace/coverage/default/35.lc_ctrl_jtag_access.562525670
Short name T820
Test name
Test status
Simulation time 398115216 ps
CPU time 4.08 seconds
Started Jun 25 06:23:43 PM PDT 24
Finished Jun 25 06:23:53 PM PDT 24
Peak memory 217492 kb
Host smart-f117398f-217c-4a46-9d40-ed9b4ae564e8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562525670 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_jtag_access.562525670
Directory /workspace/35.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/35.lc_ctrl_prog_failure.4141393575
Short name T775
Test name
Test status
Simulation time 470095054 ps
CPU time 4.77 seconds
Started Jun 25 06:23:45 PM PDT 24
Finished Jun 25 06:23:55 PM PDT 24
Peak memory 218632 kb
Host smart-78588a10-1ead-4d89-8400-e89d70a36888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141393575 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_prog_failure.4141393575
Directory /workspace/35.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_mubi.2058555010
Short name T70
Test name
Test status
Simulation time 1759739352 ps
CPU time 8.13 seconds
Started Jun 25 06:23:43 PM PDT 24
Finished Jun 25 06:23:57 PM PDT 24
Peak memory 226424 kb
Host smart-8f81f634-6962-41e5-a63e-3c6b6cd423fc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058555010 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_mubi.2058555010
Directory /workspace/35.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_digest.3043222886
Short name T395
Test name
Test status
Simulation time 1022627454 ps
CPU time 12.89 seconds
Started Jun 25 06:23:42 PM PDT 24
Finished Jun 25 06:24:00 PM PDT 24
Peak memory 218600 kb
Host smart-6827b26f-66f8-4a70-a153-4c194e5f528d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043222886 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_d
igest.3043222886
Directory /workspace/35.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_mux.3011558485
Short name T576
Test name
Test status
Simulation time 712064331 ps
CPU time 8.81 seconds
Started Jun 25 06:23:44 PM PDT 24
Finished Jun 25 06:23:59 PM PDT 24
Peak memory 218500 kb
Host smart-7255269b-fca2-48a6-a62b-dada0f448b7b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011558485 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_mux.
3011558485
Directory /workspace/35.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/35.lc_ctrl_security_escalation.444582920
Short name T63
Test name
Test status
Simulation time 474173874 ps
CPU time 6.86 seconds
Started Jun 25 06:23:42 PM PDT 24
Finished Jun 25 06:23:53 PM PDT 24
Peak memory 226436 kb
Host smart-bae54152-f9f9-48df-89ae-3284afe40921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444582920 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_security_escalation.444582920
Directory /workspace/35.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/35.lc_ctrl_smoke.4281390835
Short name T365
Test name
Test status
Simulation time 79580876 ps
CPU time 5.12 seconds
Started Jun 25 06:23:42 PM PDT 24
Finished Jun 25 06:23:52 PM PDT 24
Peak memory 215148 kb
Host smart-d403de63-2c98-409a-a4b4-6ff636e30bb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281390835 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_smoke.4281390835
Directory /workspace/35.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_failure.2339328033
Short name T375
Test name
Test status
Simulation time 1003622934 ps
CPU time 28.92 seconds
Started Jun 25 06:23:45 PM PDT 24
Finished Jun 25 06:24:19 PM PDT 24
Peak memory 251324 kb
Host smart-2d587d51-bbdc-4066-a99a-7df2400301ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339328033 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_failure.2339328033
Directory /workspace/35.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_post_trans.1721257287
Short name T390
Test name
Test status
Simulation time 193832329 ps
CPU time 7 seconds
Started Jun 25 06:23:42 PM PDT 24
Finished Jun 25 06:23:54 PM PDT 24
Peak memory 251428 kb
Host smart-2e57da66-bd63-450c-a56f-5aca46d19f20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721257287 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_post_trans.1721257287
Directory /workspace/35.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all.1391155621
Short name T128
Test name
Test status
Simulation time 2458675704 ps
CPU time 20.63 seconds
Started Jun 25 06:23:45 PM PDT 24
Finished Jun 25 06:24:11 PM PDT 24
Peak memory 227104 kb
Host smart-754d483c-3c0f-4e38-99e9-15daa8219aa8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391155621 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.lc_ctrl_stress_all.1391155621
Directory /workspace/35.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.lc_ctrl_volatile_unlock_smoke.3568711462
Short name T310
Test name
Test status
Simulation time 24983089 ps
CPU time 0.95 seconds
Started Jun 25 06:23:43 PM PDT 24
Finished Jun 25 06:23:48 PM PDT 24
Peak memory 212216 kb
Host smart-0a54aed4-fd0e-41c4-af46-29c082bbc42d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568711462 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_c
trl_volatile_unlock_smoke.3568711462
Directory /workspace/35.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_alert_test.54942645
Short name T235
Test name
Test status
Simulation time 12160690 ps
CPU time 0.95 seconds
Started Jun 25 06:23:50 PM PDT 24
Finished Jun 25 06:23:55 PM PDT 24
Peak memory 209352 kb
Host smart-75ab7bf5-54fc-4be2-b3ef-19064ee5f776
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54942645 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_alert_test.54942645
Directory /workspace/36.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.lc_ctrl_errors.2971435899
Short name T592
Test name
Test status
Simulation time 619898028 ps
CPU time 25.79 seconds
Started Jun 25 06:23:50 PM PDT 24
Finished Jun 25 06:24:20 PM PDT 24
Peak memory 226428 kb
Host smart-e9af941c-e24c-4eae-9bca-ad5c70566baa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971435899 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_errors.2971435899
Directory /workspace/36.lc_ctrl_errors/latest

Test location /workspace/coverage/default/36.lc_ctrl_jtag_access.2945974100
Short name T431
Test name
Test status
Simulation time 501932193 ps
CPU time 13.3 seconds
Started Jun 25 06:23:51 PM PDT 24
Finished Jun 25 06:24:09 PM PDT 24
Peak memory 217504 kb
Host smart-71f6ead4-afd7-4f6f-8a11-4d897b437461
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945974100 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_jtag_access.2945974100
Directory /workspace/36.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/36.lc_ctrl_prog_failure.3609323143
Short name T686
Test name
Test status
Simulation time 288362116 ps
CPU time 3.37 seconds
Started Jun 25 06:23:50 PM PDT 24
Finished Jun 25 06:23:58 PM PDT 24
Peak memory 218608 kb
Host smart-98e800e9-e8ec-446d-a437-0ed9a4945b95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609323143 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_prog_failure.3609323143
Directory /workspace/36.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_mubi.2217026603
Short name T731
Test name
Test status
Simulation time 2297752234 ps
CPU time 15.21 seconds
Started Jun 25 06:23:50 PM PDT 24
Finished Jun 25 06:24:10 PM PDT 24
Peak memory 226516 kb
Host smart-95f564a4-d16e-4e7f-af80-200ed76e19b1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217026603 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_mubi.2217026603
Directory /workspace/36.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_digest.1942424020
Short name T320
Test name
Test status
Simulation time 2584839833 ps
CPU time 8.54 seconds
Started Jun 25 06:23:52 PM PDT 24
Finished Jun 25 06:24:06 PM PDT 24
Peak memory 218644 kb
Host smart-96eabe18-15a3-4a9c-90eb-c0220d5f5b9d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942424020 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_d
igest.1942424020
Directory /workspace/36.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_mux.4001884673
Short name T780
Test name
Test status
Simulation time 569161791 ps
CPU time 13.42 seconds
Started Jun 25 06:23:53 PM PDT 24
Finished Jun 25 06:24:11 PM PDT 24
Peak memory 218572 kb
Host smart-c9b9d0e7-ef0e-467b-8272-589228c9721a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001884673 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_mux.
4001884673
Directory /workspace/36.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/36.lc_ctrl_security_escalation.4083798501
Short name T420
Test name
Test status
Simulation time 413977504 ps
CPU time 9.99 seconds
Started Jun 25 06:23:49 PM PDT 24
Finished Jun 25 06:24:03 PM PDT 24
Peak memory 218680 kb
Host smart-280cb1cf-f2e7-4d0b-9d8b-a9ed3f461b3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083798501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_security_escalation.4083798501
Directory /workspace/36.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/36.lc_ctrl_smoke.943043688
Short name T443
Test name
Test status
Simulation time 40471119 ps
CPU time 2.2 seconds
Started Jun 25 06:23:51 PM PDT 24
Finished Jun 25 06:23:57 PM PDT 24
Peak memory 223104 kb
Host smart-5c0cb33b-ae89-40a3-ac73-fccaf181ee72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943043688 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_smoke.943043688
Directory /workspace/36.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_failure.3553178806
Short name T190
Test name
Test status
Simulation time 359922337 ps
CPU time 30.66 seconds
Started Jun 25 06:23:53 PM PDT 24
Finished Jun 25 06:24:28 PM PDT 24
Peak memory 251340 kb
Host smart-02f85d9f-38d2-4507-b294-de71b3c024b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553178806 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_failure.3553178806
Directory /workspace/36.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_post_trans.1054284105
Short name T703
Test name
Test status
Simulation time 283536425 ps
CPU time 4.07 seconds
Started Jun 25 06:23:51 PM PDT 24
Finished Jun 25 06:23:59 PM PDT 24
Peak memory 223104 kb
Host smart-552fb6e2-b88d-464c-be53-b5f49b593026
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054284105 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_post_trans.1054284105
Directory /workspace/36.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all.2597299988
Short name T400
Test name
Test status
Simulation time 13073179448 ps
CPU time 377.63 seconds
Started Jun 25 06:23:53 PM PDT 24
Finished Jun 25 06:30:17 PM PDT 24
Peak memory 308852 kb
Host smart-4bf72d8a-238f-4c9e-8029-e7552965b925
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597299988 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.lc_ctrl_stress_all.2597299988
Directory /workspace/36.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.lc_ctrl_volatile_unlock_smoke.956438271
Short name T406
Test name
Test status
Simulation time 11069679 ps
CPU time 0.93 seconds
Started Jun 25 06:23:50 PM PDT 24
Finished Jun 25 06:23:55 PM PDT 24
Peak memory 209292 kb
Host smart-ad303390-00e6-4026-80f6-53753a274c2d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956438271 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ct
rl_volatile_unlock_smoke.956438271
Directory /workspace/36.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_alert_test.974882053
Short name T736
Test name
Test status
Simulation time 66589445 ps
CPU time 0.92 seconds
Started Jun 25 06:23:59 PM PDT 24
Finished Jun 25 06:24:09 PM PDT 24
Peak memory 209356 kb
Host smart-f54d4b4c-83c1-4f8a-9346-fec75a4a0bf3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974882053 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_alert_test.974882053
Directory /workspace/37.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.lc_ctrl_errors.2353529094
Short name T636
Test name
Test status
Simulation time 263625163 ps
CPU time 11.68 seconds
Started Jun 25 06:24:00 PM PDT 24
Finished Jun 25 06:24:23 PM PDT 24
Peak memory 218708 kb
Host smart-3f370588-39c2-49ee-98b8-2d34c2f1c5e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353529094 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_errors.2353529094
Directory /workspace/37.lc_ctrl_errors/latest

Test location /workspace/coverage/default/37.lc_ctrl_jtag_access.2165664009
Short name T805
Test name
Test status
Simulation time 2718776998 ps
CPU time 7.46 seconds
Started Jun 25 06:24:07 PM PDT 24
Finished Jun 25 06:24:34 PM PDT 24
Peak memory 217940 kb
Host smart-bcb65fcc-50bf-4fec-b4a8-1998b06b9d6e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165664009 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_jtag_access.2165664009
Directory /workspace/37.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/37.lc_ctrl_prog_failure.1768442734
Short name T669
Test name
Test status
Simulation time 44513054 ps
CPU time 2.15 seconds
Started Jun 25 06:23:59 PM PDT 24
Finished Jun 25 06:24:09 PM PDT 24
Peak memory 218624 kb
Host smart-dbfa248a-45fc-4ee8-bfc1-56e299647d14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768442734 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_prog_failure.1768442734
Directory /workspace/37.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_mubi.3155994470
Short name T191
Test name
Test status
Simulation time 1550094337 ps
CPU time 12.19 seconds
Started Jun 25 06:23:59 PM PDT 24
Finished Jun 25 06:24:18 PM PDT 24
Peak memory 226424 kb
Host smart-3d26eeee-60f6-4885-a179-fbbd5d96858f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155994470 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_mubi.3155994470
Directory /workspace/37.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_digest.2342030801
Short name T255
Test name
Test status
Simulation time 563189583 ps
CPU time 11.16 seconds
Started Jun 25 06:23:59 PM PDT 24
Finished Jun 25 06:24:18 PM PDT 24
Peak memory 218604 kb
Host smart-b6b30667-50cf-42f7-8dff-76fa94b0dccf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342030801 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_d
igest.2342030801
Directory /workspace/37.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_mux.1495069052
Short name T308
Test name
Test status
Simulation time 334184998 ps
CPU time 8.25 seconds
Started Jun 25 06:23:58 PM PDT 24
Finished Jun 25 06:24:13 PM PDT 24
Peak memory 218600 kb
Host smart-cc0cf352-4993-43cc-9c66-c6fd9709839d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495069052 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_mux.
1495069052
Directory /workspace/37.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/37.lc_ctrl_security_escalation.2989294908
Short name T279
Test name
Test status
Simulation time 1582719648 ps
CPU time 8.95 seconds
Started Jun 25 06:23:57 PM PDT 24
Finished Jun 25 06:24:11 PM PDT 24
Peak memory 224920 kb
Host smart-7817b62e-ba57-4ac3-aee5-d245918ae652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989294908 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_security_escalation.2989294908
Directory /workspace/37.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/37.lc_ctrl_smoke.2091549327
Short name T681
Test name
Test status
Simulation time 206104087 ps
CPU time 2.68 seconds
Started Jun 25 06:23:52 PM PDT 24
Finished Jun 25 06:24:00 PM PDT 24
Peak memory 214796 kb
Host smart-9fd1ebea-a2f2-4bbe-939b-25004e027b33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091549327 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_smoke.2091549327
Directory /workspace/37.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_failure.3948466709
Short name T44
Test name
Test status
Simulation time 1705723718 ps
CPU time 31.23 seconds
Started Jun 25 06:23:50 PM PDT 24
Finished Jun 25 06:24:25 PM PDT 24
Peak memory 251328 kb
Host smart-f0f55836-634c-4336-bceb-0a857da1cedd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948466709 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_failure.3948466709
Directory /workspace/37.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_post_trans.3405702604
Short name T560
Test name
Test status
Simulation time 149121652 ps
CPU time 7.02 seconds
Started Jun 25 06:23:49 PM PDT 24
Finished Jun 25 06:24:00 PM PDT 24
Peak memory 247188 kb
Host smart-0ebf0878-2aa4-4142-8cfa-7170594d1980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405702604 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_post_trans.3405702604
Directory /workspace/37.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all.1730974551
Short name T590
Test name
Test status
Simulation time 22377086753 ps
CPU time 183.76 seconds
Started Jun 25 06:24:04 PM PDT 24
Finished Jun 25 06:27:24 PM PDT 24
Peak memory 275952 kb
Host smart-ba21386c-8848-48af-bb3e-353ca997c1b6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730974551 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.lc_ctrl_stress_all.1730974551
Directory /workspace/37.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all_with_rand_reset.87550640
Short name T56
Test name
Test status
Simulation time 145379403548 ps
CPU time 722.24 seconds
Started Jun 25 06:23:59 PM PDT 24
Finished Jun 25 06:36:09 PM PDT 24
Peak memory 309040 kb
Host smart-4d325be5-936c-41d3-a77b-ea69888aa156
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=87550640 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_stress_all_with_rand_reset.87550640
Directory /workspace/37.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.lc_ctrl_volatile_unlock_smoke.1276904183
Short name T869
Test name
Test status
Simulation time 13571295 ps
CPU time 0.96 seconds
Started Jun 25 06:23:50 PM PDT 24
Finished Jun 25 06:23:55 PM PDT 24
Peak memory 212196 kb
Host smart-d8a2a3a6-c118-43c7-b4b7-a5358fdde7f7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276904183 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_c
trl_volatile_unlock_smoke.1276904183
Directory /workspace/37.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_alert_test.1985376243
Short name T311
Test name
Test status
Simulation time 20854096 ps
CPU time 1.07 seconds
Started Jun 25 06:24:06 PM PDT 24
Finished Jun 25 06:24:26 PM PDT 24
Peak memory 209292 kb
Host smart-5975c80d-fcb9-4433-881f-afbf485b52da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985376243 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_alert_test.1985376243
Directory /workspace/38.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.lc_ctrl_errors.879493529
Short name T760
Test name
Test status
Simulation time 1302655999 ps
CPU time 10.95 seconds
Started Jun 25 06:24:08 PM PDT 24
Finished Jun 25 06:24:38 PM PDT 24
Peak memory 218592 kb
Host smart-90bdd287-bbf6-497c-8350-6972bf770dc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879493529 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_errors.879493529
Directory /workspace/38.lc_ctrl_errors/latest

Test location /workspace/coverage/default/38.lc_ctrl_jtag_access.4030673975
Short name T581
Test name
Test status
Simulation time 132514183 ps
CPU time 2.46 seconds
Started Jun 25 06:24:04 PM PDT 24
Finished Jun 25 06:24:21 PM PDT 24
Peak memory 217404 kb
Host smart-79d9df47-85ac-4a9e-8fdf-fc98c6c55a61
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030673975 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_jtag_access.4030673975
Directory /workspace/38.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/38.lc_ctrl_prog_failure.3543411623
Short name T360
Test name
Test status
Simulation time 64222283 ps
CPU time 2.73 seconds
Started Jun 25 06:24:04 PM PDT 24
Finished Jun 25 06:24:23 PM PDT 24
Peak memory 218692 kb
Host smart-f7a5ea70-26b6-44a6-89fd-cc71fe2fb7c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543411623 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_prog_failure.3543411623
Directory /workspace/38.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_mubi.3057848904
Short name T389
Test name
Test status
Simulation time 422861428 ps
CPU time 14.43 seconds
Started Jun 25 06:23:59 PM PDT 24
Finished Jun 25 06:24:20 PM PDT 24
Peak memory 226456 kb
Host smart-10a0ea3e-924f-4c72-ac62-e74bf2b7f067
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057848904 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_mubi.3057848904
Directory /workspace/38.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_digest.2968388814
Short name T42
Test name
Test status
Simulation time 707498999 ps
CPU time 8.19 seconds
Started Jun 25 06:24:05 PM PDT 24
Finished Jun 25 06:24:30 PM PDT 24
Peak memory 218584 kb
Host smart-0d4668c6-c9b3-4964-a9d7-7eca8bcbfc73
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968388814 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_d
igest.2968388814
Directory /workspace/38.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_mux.3459398169
Short name T363
Test name
Test status
Simulation time 1144001389 ps
CPU time 11.89 seconds
Started Jun 25 06:24:07 PM PDT 24
Finished Jun 25 06:24:39 PM PDT 24
Peak memory 218556 kb
Host smart-f2dd1f2c-7f6f-4561-a8a6-af530c794857
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459398169 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_mux.
3459398169
Directory /workspace/38.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/38.lc_ctrl_security_escalation.375283931
Short name T120
Test name
Test status
Simulation time 454341234 ps
CPU time 11.19 seconds
Started Jun 25 06:24:00 PM PDT 24
Finished Jun 25 06:24:22 PM PDT 24
Peak memory 226428 kb
Host smart-b10040bf-2672-497e-8e02-b8dc0b864b1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375283931 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_security_escalation.375283931
Directory /workspace/38.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/38.lc_ctrl_smoke.635651544
Short name T752
Test name
Test status
Simulation time 131938043 ps
CPU time 4.19 seconds
Started Jun 25 06:23:59 PM PDT 24
Finished Jun 25 06:24:10 PM PDT 24
Peak memory 218052 kb
Host smart-ef7b1849-c207-4c2e-848b-7ff4010882b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635651544 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_smoke.635651544
Directory /workspace/38.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_failure.3038145609
Short name T845
Test name
Test status
Simulation time 956679773 ps
CPU time 23.99 seconds
Started Jun 25 06:24:07 PM PDT 24
Finished Jun 25 06:24:51 PM PDT 24
Peak memory 251308 kb
Host smart-44178c6e-6e6b-4d72-b075-134f60fbe7bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038145609 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_failure.3038145609
Directory /workspace/38.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_post_trans.98254261
Short name T198
Test name
Test status
Simulation time 542876590 ps
CPU time 3.01 seconds
Started Jun 25 06:24:08 PM PDT 24
Finished Jun 25 06:24:30 PM PDT 24
Peak memory 222896 kb
Host smart-a1bb209e-21b9-45c3-84c7-7781ee404f91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98254261 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_post_trans.98254261
Directory /workspace/38.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all.1409026447
Short name T606
Test name
Test status
Simulation time 7806118598 ps
CPU time 116.96 seconds
Started Jun 25 06:24:07 PM PDT 24
Finished Jun 25 06:26:24 PM PDT 24
Peak memory 251296 kb
Host smart-83766b98-d2cc-4020-bf14-6e6e16fbfef6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409026447 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.lc_ctrl_stress_all.1409026447
Directory /workspace/38.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.lc_ctrl_volatile_unlock_smoke.1646599410
Short name T634
Test name
Test status
Simulation time 199559057 ps
CPU time 1.11 seconds
Started Jun 25 06:23:59 PM PDT 24
Finished Jun 25 06:24:08 PM PDT 24
Peak memory 218156 kb
Host smart-7399d39a-c2a5-4ee4-8184-1d5936b76543
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646599410 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_c
trl_volatile_unlock_smoke.1646599410
Directory /workspace/38.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_alert_test.1795313
Short name T79
Test name
Test status
Simulation time 24370707 ps
CPU time 1.08 seconds
Started Jun 25 06:24:05 PM PDT 24
Finished Jun 25 06:24:23 PM PDT 24
Peak memory 209372 kb
Host smart-d5ccbc1a-da9d-4cd0-9600-f3211bcc43a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795313 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_alert_test.1795313
Directory /workspace/39.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.lc_ctrl_errors.2537527592
Short name T323
Test name
Test status
Simulation time 2120634714 ps
CPU time 9.68 seconds
Started Jun 25 06:24:06 PM PDT 24
Finished Jun 25 06:24:34 PM PDT 24
Peak memory 218524 kb
Host smart-8fc2d042-d3c2-4fa0-9772-0ce71308638a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537527592 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_errors.2537527592
Directory /workspace/39.lc_ctrl_errors/latest

Test location /workspace/coverage/default/39.lc_ctrl_jtag_access.3033656553
Short name T689
Test name
Test status
Simulation time 2319033674 ps
CPU time 15.42 seconds
Started Jun 25 06:24:06 PM PDT 24
Finished Jun 25 06:24:38 PM PDT 24
Peak memory 217936 kb
Host smart-5c808e60-693a-4bd8-b31a-d7a97a8ca6e7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033656553 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_jtag_access.3033656553
Directory /workspace/39.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/39.lc_ctrl_prog_failure.2961987470
Short name T593
Test name
Test status
Simulation time 27965233 ps
CPU time 1.83 seconds
Started Jun 25 06:24:08 PM PDT 24
Finished Jun 25 06:24:29 PM PDT 24
Peak memory 218552 kb
Host smart-da1bcd26-fc62-4fb4-b748-608bd538da46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961987470 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_prog_failure.2961987470
Directory /workspace/39.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_mubi.1884752744
Short name T720
Test name
Test status
Simulation time 720591218 ps
CPU time 8.1 seconds
Started Jun 25 06:24:08 PM PDT 24
Finished Jun 25 06:24:37 PM PDT 24
Peak memory 226516 kb
Host smart-629ba2b6-d4e1-4c82-a0b1-06bff2b66e4c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884752744 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_mubi.1884752744
Directory /workspace/39.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_digest.1693993487
Short name T435
Test name
Test status
Simulation time 3300446496 ps
CPU time 7 seconds
Started Jun 25 06:24:06 PM PDT 24
Finished Jun 25 06:24:29 PM PDT 24
Peak memory 218628 kb
Host smart-c6e0dcc8-7afb-4fcb-b2bd-7bd871a55af7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693993487 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_d
igest.1693993487
Directory /workspace/39.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_mux.3578940050
Short name T434
Test name
Test status
Simulation time 729845010 ps
CPU time 10.17 seconds
Started Jun 25 06:24:09 PM PDT 24
Finished Jun 25 06:24:41 PM PDT 24
Peak memory 218572 kb
Host smart-a7d7895e-5825-4349-ab2f-290c05bda2fc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578940050 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_mux.
3578940050
Directory /workspace/39.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/39.lc_ctrl_security_escalation.2320535408
Short name T863
Test name
Test status
Simulation time 293827011 ps
CPU time 11.35 seconds
Started Jun 25 06:24:07 PM PDT 24
Finished Jun 25 06:24:38 PM PDT 24
Peak memory 226276 kb
Host smart-4c438f1d-fa5e-4e7d-9927-e80686a3a347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320535408 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_security_escalation.2320535408
Directory /workspace/39.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/39.lc_ctrl_smoke.1159109973
Short name T17
Test name
Test status
Simulation time 34595641 ps
CPU time 1.86 seconds
Started Jun 25 06:24:09 PM PDT 24
Finished Jun 25 06:24:33 PM PDT 24
Peak memory 214288 kb
Host smart-8a310104-ffe1-4889-aca6-e299dbbb3c4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159109973 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_smoke.1159109973
Directory /workspace/39.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_failure.1867036074
Short name T391
Test name
Test status
Simulation time 258721319 ps
CPU time 20.82 seconds
Started Jun 25 06:24:09 PM PDT 24
Finished Jun 25 06:24:52 PM PDT 24
Peak memory 251336 kb
Host smart-ecdbd917-b575-4346-a162-b75ff033e69a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867036074 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_failure.1867036074
Directory /workspace/39.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_post_trans.141616484
Short name T530
Test name
Test status
Simulation time 820185694 ps
CPU time 10.72 seconds
Started Jun 25 06:24:06 PM PDT 24
Finished Jun 25 06:24:35 PM PDT 24
Peak memory 251428 kb
Host smart-a2bacaf8-d25f-475c-ab2a-d681666f5c35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141616484 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_post_trans.141616484
Directory /workspace/39.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all.4199811300
Short name T212
Test name
Test status
Simulation time 13518145672 ps
CPU time 114.93 seconds
Started Jun 25 06:24:06 PM PDT 24
Finished Jun 25 06:26:20 PM PDT 24
Peak memory 283512 kb
Host smart-2c42b625-2d98-4ca5-8d7b-82d7b355dfec
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199811300 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.lc_ctrl_stress_all.4199811300
Directory /workspace/39.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all_with_rand_reset.302959960
Short name T706
Test name
Test status
Simulation time 216430574652 ps
CPU time 1829.48 seconds
Started Jun 25 06:24:07 PM PDT 24
Finished Jun 25 06:54:54 PM PDT 24
Peak memory 389704 kb
Host smart-8e0af312-3d79-4d3c-ace1-a76e74fab784
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=302959960 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_stress_all_with_rand_reset.302959960
Directory /workspace/39.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.lc_ctrl_volatile_unlock_smoke.2127070377
Short name T34
Test name
Test status
Simulation time 14164463 ps
CPU time 1.19 seconds
Started Jun 25 06:24:08 PM PDT 24
Finished Jun 25 06:24:30 PM PDT 24
Peak memory 212208 kb
Host smart-442c139a-b098-4dcb-9a54-e93d1aaf1d9e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127070377 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_c
trl_volatile_unlock_smoke.2127070377
Directory /workspace/39.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_claim_transition_if.3127357032
Short name T194
Test name
Test status
Simulation time 42067569 ps
CPU time 0.8 seconds
Started Jun 25 06:19:43 PM PDT 24
Finished Jun 25 06:19:45 PM PDT 24
Peak memory 209280 kb
Host smart-0f494992-b434-409c-ab0e-2fb16095d01d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127357032 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_claim_transition_if.3127357032
Directory /workspace/4.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/4.lc_ctrl_errors.492327106
Short name T676
Test name
Test status
Simulation time 3200289171 ps
CPU time 21.05 seconds
Started Jun 25 06:19:42 PM PDT 24
Finished Jun 25 06:20:04 PM PDT 24
Peak memory 219352 kb
Host smart-914c2752-7ed3-4543-8d2a-7501fbafeff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492327106 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_errors.492327106
Directory /workspace/4.lc_ctrl_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_access.1884986817
Short name T26
Test name
Test status
Simulation time 186483968 ps
CPU time 2.51 seconds
Started Jun 25 06:19:53 PM PDT 24
Finished Jun 25 06:19:57 PM PDT 24
Peak memory 217420 kb
Host smart-58952883-1c1f-4d43-b48d-85034af656f7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884986817 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_access.1884986817
Directory /workspace/4.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_errors.4277151028
Short name T565
Test name
Test status
Simulation time 2508866170 ps
CPU time 36.17 seconds
Started Jun 25 06:19:53 PM PDT 24
Finished Jun 25 06:20:30 PM PDT 24
Peak memory 218576 kb
Host smart-c628db50-0b0f-455a-aae1-5752a52a6198
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277151028 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_er
rors.4277151028
Directory /workspace/4.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_priority.1457542524
Short name T322
Test name
Test status
Simulation time 1109718748 ps
CPU time 7.46 seconds
Started Jun 25 06:19:53 PM PDT 24
Finished Jun 25 06:20:02 PM PDT 24
Peak memory 217780 kb
Host smart-344a0b01-0ad2-439f-9ac7-6eac035ab688
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457542524 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_priority.1
457542524
Directory /workspace/4.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_prog_failure.3233302058
Short name T757
Test name
Test status
Simulation time 574241270 ps
CPU time 8.06 seconds
Started Jun 25 06:19:54 PM PDT 24
Finished Jun 25 06:20:03 PM PDT 24
Peak memory 218552 kb
Host smart-f69f8344-fb68-4820-878c-0071fa628387
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233302058 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag
_prog_failure.3233302058
Directory /workspace/4.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_regwen_during_op.1966570483
Short name T574
Test name
Test status
Simulation time 2433437243 ps
CPU time 19.45 seconds
Started Jun 25 06:19:55 PM PDT 24
Finished Jun 25 06:20:15 PM PDT 24
Peak memory 217960 kb
Host smart-b051ba86-5382-44fa-b36a-8cb75439a550
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966570483 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_regwen_during_op.1966570483
Directory /workspace/4.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_smoke.2036850656
Short name T705
Test name
Test status
Simulation time 198033080 ps
CPU time 4 seconds
Started Jun 25 06:19:43 PM PDT 24
Finished Jun 25 06:19:48 PM PDT 24
Peak memory 217980 kb
Host smart-6c7f181f-5f83-4f46-9bd1-5fdfd38ca98d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036850656 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_smoke.
2036850656
Directory /workspace/4.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_failure.1506001322
Short name T339
Test name
Test status
Simulation time 3194548301 ps
CPU time 56.14 seconds
Started Jun 25 06:19:53 PM PDT 24
Finished Jun 25 06:20:51 PM PDT 24
Peak memory 277332 kb
Host smart-2db68b09-3999-48e3-b32c-7830b1ea59bd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506001322 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jta
g_state_failure.1506001322
Directory /workspace/4.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_post_trans.1715543581
Short name T712
Test name
Test status
Simulation time 419328633 ps
CPU time 12.26 seconds
Started Jun 25 06:19:55 PM PDT 24
Finished Jun 25 06:20:08 PM PDT 24
Peak memory 251240 kb
Host smart-2f33fee9-c465-4e13-82f4-3e77f74de191
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715543581 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_state_post_trans.1715543581
Directory /workspace/4.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_prog_failure.3966201864
Short name T429
Test name
Test status
Simulation time 337751721 ps
CPU time 3.06 seconds
Started Jun 25 06:19:44 PM PDT 24
Finished Jun 25 06:19:47 PM PDT 24
Peak memory 218624 kb
Host smart-eae5cd14-1685-4d24-b853-4faa9a1d96e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966201864 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_prog_failure.3966201864
Directory /workspace/4.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_regwen_during_op.1714910012
Short name T207
Test name
Test status
Simulation time 206154474 ps
CPU time 14.1 seconds
Started Jun 25 06:19:43 PM PDT 24
Finished Jun 25 06:19:58 PM PDT 24
Peak memory 214948 kb
Host smart-5c04b970-fb8c-458e-ad61-7292644e40cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714910012 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_regwen_during_op.1714910012
Directory /workspace/4.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_cm.121607105
Short name T126
Test name
Test status
Simulation time 461415675 ps
CPU time 24.44 seconds
Started Jun 25 06:19:53 PM PDT 24
Finished Jun 25 06:20:18 PM PDT 24
Peak memory 282116 kb
Host smart-e2a6bb58-4bca-48b5-ab7e-24d3aa981212
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121607105 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_cm.121607105
Directory /workspace/4.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_mubi.3841964532
Short name T469
Test name
Test status
Simulation time 319317643 ps
CPU time 11.97 seconds
Started Jun 25 06:19:53 PM PDT 24
Finished Jun 25 06:20:06 PM PDT 24
Peak memory 226436 kb
Host smart-8abc3256-5431-43e1-8f30-b5de9d2f5dc3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841964532 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_mubi.3841964532
Directory /workspace/4.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_digest.171729769
Short name T495
Test name
Test status
Simulation time 243939277 ps
CPU time 11.66 seconds
Started Jun 25 06:19:53 PM PDT 24
Finished Jun 25 06:20:06 PM PDT 24
Peak memory 218592 kb
Host smart-9a3dd407-9ff3-439f-a8b3-5f4bfba8acfa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171729769 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_dig
est.171729769
Directory /workspace/4.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_mux.2156393333
Short name T305
Test name
Test status
Simulation time 426321226 ps
CPU time 8.43 seconds
Started Jun 25 06:19:54 PM PDT 24
Finished Jun 25 06:20:03 PM PDT 24
Peak memory 218800 kb
Host smart-eeedd72b-1adb-40d3-9ab7-4c68bc0c6715
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156393333 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_mux.2
156393333
Directory /workspace/4.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/4.lc_ctrl_security_escalation.3473951195
Short name T856
Test name
Test status
Simulation time 213810673 ps
CPU time 5.81 seconds
Started Jun 25 06:19:42 PM PDT 24
Finished Jun 25 06:19:48 PM PDT 24
Peak memory 224512 kb
Host smart-d5d6f660-bb6b-4845-9e47-8fadccf6a315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473951195 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_security_escalation.3473951195
Directory /workspace/4.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/4.lc_ctrl_smoke.4128109431
Short name T803
Test name
Test status
Simulation time 51579222 ps
CPU time 1.98 seconds
Started Jun 25 06:19:43 PM PDT 24
Finished Jun 25 06:19:46 PM PDT 24
Peak memory 214412 kb
Host smart-f0f7a39f-84c6-486e-aa7c-8bbab63d47d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128109431 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_smoke.4128109431
Directory /workspace/4.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_failure.1672206867
Short name T465
Test name
Test status
Simulation time 845480099 ps
CPU time 26.8 seconds
Started Jun 25 06:19:43 PM PDT 24
Finished Jun 25 06:20:10 PM PDT 24
Peak memory 251268 kb
Host smart-d78a6918-34ef-4026-93ad-44e3bd39e290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672206867 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_failure.1672206867
Directory /workspace/4.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_post_trans.3711159937
Short name T594
Test name
Test status
Simulation time 1947814166 ps
CPU time 9.21 seconds
Started Jun 25 06:19:42 PM PDT 24
Finished Jun 25 06:19:52 PM PDT 24
Peak memory 251152 kb
Host smart-969d2e07-ba44-4384-a4f7-cf70ff2aa015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711159937 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_post_trans.3711159937
Directory /workspace/4.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_stress_all.3311041469
Short name T694
Test name
Test status
Simulation time 23052604697 ps
CPU time 148.15 seconds
Started Jun 25 06:19:55 PM PDT 24
Finished Jun 25 06:22:24 PM PDT 24
Peak memory 251360 kb
Host smart-d99c58dc-31aa-410b-9cbe-c1fe0b39aaa9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311041469 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.lc_ctrl_stress_all.3311041469
Directory /workspace/4.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.lc_ctrl_volatile_unlock_smoke.322705043
Short name T37
Test name
Test status
Simulation time 11645544 ps
CPU time 0.92 seconds
Started Jun 25 06:19:43 PM PDT 24
Finished Jun 25 06:19:45 PM PDT 24
Peak memory 209300 kb
Host smart-9d23741a-82a8-45f1-b88f-568132e4ba87
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322705043 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctr
l_volatile_unlock_smoke.322705043
Directory /workspace/4.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_alert_test.2934663390
Short name T798
Test name
Test status
Simulation time 28924618 ps
CPU time 0.88 seconds
Started Jun 25 06:24:26 PM PDT 24
Finished Jun 25 06:24:57 PM PDT 24
Peak memory 209388 kb
Host smart-7f3c9a06-a4e3-42f9-a381-0b94f56db4ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934663390 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_alert_test.2934663390
Directory /workspace/40.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.lc_ctrl_jtag_access.1299581933
Short name T766
Test name
Test status
Simulation time 1751223789 ps
CPU time 11.65 seconds
Started Jun 25 06:24:22 PM PDT 24
Finished Jun 25 06:25:05 PM PDT 24
Peak memory 217668 kb
Host smart-32ef692f-f2a5-42e8-bb9d-9a9d6b33ebcc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299581933 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_jtag_access.1299581933
Directory /workspace/40.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/40.lc_ctrl_prog_failure.38597739
Short name T370
Test name
Test status
Simulation time 86166451 ps
CPU time 1.76 seconds
Started Jun 25 06:24:22 PM PDT 24
Finished Jun 25 06:24:55 PM PDT 24
Peak memory 222468 kb
Host smart-1c61b472-efb1-4472-96e9-bebcea46ac94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38597739 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_prog_failure.38597739
Directory /workspace/40.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_mubi.1725844150
Short name T573
Test name
Test status
Simulation time 3114129135 ps
CPU time 13.78 seconds
Started Jun 25 06:24:28 PM PDT 24
Finished Jun 25 06:25:11 PM PDT 24
Peak memory 226436 kb
Host smart-540d5579-0ec1-4280-b737-62ab361a43ec
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725844150 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_mubi.1725844150
Directory /workspace/40.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_digest.3663919370
Short name T672
Test name
Test status
Simulation time 299833620 ps
CPU time 9.38 seconds
Started Jun 25 06:24:23 PM PDT 24
Finished Jun 25 06:25:04 PM PDT 24
Peak memory 218656 kb
Host smart-123375b1-3096-4246-b6f0-fda3419f65b5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663919370 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_d
igest.3663919370
Directory /workspace/40.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_mux.1253304322
Short name T500
Test name
Test status
Simulation time 1021533393 ps
CPU time 11.66 seconds
Started Jun 25 06:24:23 PM PDT 24
Finished Jun 25 06:25:05 PM PDT 24
Peak memory 218688 kb
Host smart-0f3933f9-3a86-4f41-86f6-91e78aeeac00
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253304322 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_mux.
1253304322
Directory /workspace/40.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/40.lc_ctrl_security_escalation.858634078
Short name T58
Test name
Test status
Simulation time 1546809253 ps
CPU time 10.31 seconds
Started Jun 25 06:24:23 PM PDT 24
Finished Jun 25 06:25:03 PM PDT 24
Peak memory 218684 kb
Host smart-833fd8c6-10f4-4111-9101-2b249d18792f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858634078 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_security_escalation.858634078
Directory /workspace/40.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/40.lc_ctrl_smoke.1460787671
Short name T78
Test name
Test status
Simulation time 26098184 ps
CPU time 1.86 seconds
Started Jun 25 06:24:06 PM PDT 24
Finished Jun 25 06:24:27 PM PDT 24
Peak memory 218052 kb
Host smart-ecba1c1e-3ffd-4fae-b1c9-3cf92ece01d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460787671 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_smoke.1460787671
Directory /workspace/40.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_failure.1862379346
Short name T860
Test name
Test status
Simulation time 775121172 ps
CPU time 21.47 seconds
Started Jun 25 06:24:07 PM PDT 24
Finished Jun 25 06:24:46 PM PDT 24
Peak memory 251332 kb
Host smart-079a16a2-9a85-47da-92ed-4336897e2092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862379346 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_failure.1862379346
Directory /workspace/40.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_post_trans.2684839466
Short name T558
Test name
Test status
Simulation time 336809168 ps
CPU time 8.04 seconds
Started Jun 25 06:24:08 PM PDT 24
Finished Jun 25 06:24:37 PM PDT 24
Peak memory 246492 kb
Host smart-2f64793b-5601-41c3-991d-b891734348e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684839466 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_post_trans.2684839466
Directory /workspace/40.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/40.lc_ctrl_stress_all.2929499196
Short name T513
Test name
Test status
Simulation time 4978667421 ps
CPU time 33.99 seconds
Started Jun 25 06:24:22 PM PDT 24
Finished Jun 25 06:25:27 PM PDT 24
Peak memory 251164 kb
Host smart-b49258bd-a6c5-4013-9c47-c9e3687e14ba
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929499196 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.lc_ctrl_stress_all.2929499196
Directory /workspace/40.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.lc_ctrl_volatile_unlock_smoke.1896395467
Short name T247
Test name
Test status
Simulation time 109041239 ps
CPU time 0.89 seconds
Started Jun 25 06:24:06 PM PDT 24
Finished Jun 25 06:24:26 PM PDT 24
Peak memory 209268 kb
Host smart-8b54f414-fb50-49d2-8ec3-9931ba26ddc0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896395467 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_c
trl_volatile_unlock_smoke.1896395467
Directory /workspace/40.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_alert_test.462965042
Short name T278
Test name
Test status
Simulation time 20214234 ps
CPU time 0.91 seconds
Started Jun 25 06:24:26 PM PDT 24
Finished Jun 25 06:24:57 PM PDT 24
Peak memory 209340 kb
Host smart-0c960357-dd94-4881-b77b-30e1634ea717
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462965042 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_alert_test.462965042
Directory /workspace/41.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.lc_ctrl_errors.3276078251
Short name T383
Test name
Test status
Simulation time 712040622 ps
CPU time 17.86 seconds
Started Jun 25 06:24:22 PM PDT 24
Finished Jun 25 06:25:11 PM PDT 24
Peak memory 226444 kb
Host smart-c18fd499-4437-4e29-aa48-3913a526c109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276078251 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_errors.3276078251
Directory /workspace/41.lc_ctrl_errors/latest

Test location /workspace/coverage/default/41.lc_ctrl_jtag_access.197404277
Short name T552
Test name
Test status
Simulation time 4447967844 ps
CPU time 3.76 seconds
Started Jun 25 06:24:23 PM PDT 24
Finished Jun 25 06:24:59 PM PDT 24
Peak memory 218088 kb
Host smart-1e01d5b2-3df4-4224-a999-8a7ebe3c3261
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197404277 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_jtag_access.197404277
Directory /workspace/41.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/41.lc_ctrl_prog_failure.2258430480
Short name T542
Test name
Test status
Simulation time 43611615 ps
CPU time 2.13 seconds
Started Jun 25 06:24:22 PM PDT 24
Finished Jun 25 06:24:55 PM PDT 24
Peak memory 218620 kb
Host smart-145f40ee-5180-4559-95a1-dfe0fbeff99e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258430480 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_prog_failure.2258430480
Directory /workspace/41.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_mubi.2562577709
Short name T453
Test name
Test status
Simulation time 245461442 ps
CPU time 12 seconds
Started Jun 25 06:24:27 PM PDT 24
Finished Jun 25 06:25:09 PM PDT 24
Peak memory 226388 kb
Host smart-68ac06ac-6dc5-4704-88f7-daf317b59a14
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562577709 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_mubi.2562577709
Directory /workspace/41.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_digest.1713990522
Short name T710
Test name
Test status
Simulation time 486724958 ps
CPU time 13.52 seconds
Started Jun 25 06:24:26 PM PDT 24
Finished Jun 25 06:25:10 PM PDT 24
Peak memory 218536 kb
Host smart-001c2837-f17d-49fd-9fa3-1eb3a2613115
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713990522 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_d
igest.1713990522
Directory /workspace/41.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_mux.2142996494
Short name T770
Test name
Test status
Simulation time 246760275 ps
CPU time 7.07 seconds
Started Jun 25 06:24:26 PM PDT 24
Finished Jun 25 06:25:03 PM PDT 24
Peak memory 218576 kb
Host smart-2c4314b7-8772-4a50-92f4-7e49b2fcedbd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142996494 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_mux.
2142996494
Directory /workspace/41.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/41.lc_ctrl_security_escalation.475354454
Short name T639
Test name
Test status
Simulation time 527839387 ps
CPU time 11.21 seconds
Started Jun 25 06:24:21 PM PDT 24
Finished Jun 25 06:25:02 PM PDT 24
Peak memory 218704 kb
Host smart-d1697ebe-363d-4297-8e99-9d481c4ac5b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475354454 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_security_escalation.475354454
Directory /workspace/41.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/41.lc_ctrl_smoke.4016184462
Short name T86
Test name
Test status
Simulation time 50622655 ps
CPU time 2.21 seconds
Started Jun 25 06:24:22 PM PDT 24
Finished Jun 25 06:24:55 PM PDT 24
Peak memory 222912 kb
Host smart-f0849938-7286-4dca-b3d7-e7dd184e4883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016184462 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_smoke.4016184462
Directory /workspace/41.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_failure.1526468999
Short name T717
Test name
Test status
Simulation time 191774661 ps
CPU time 20.89 seconds
Started Jun 25 06:24:22 PM PDT 24
Finished Jun 25 06:25:14 PM PDT 24
Peak memory 251288 kb
Host smart-b3e13f3c-514a-475d-bb5d-8a09f9753187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526468999 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_failure.1526468999
Directory /workspace/41.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_post_trans.1665725938
Short name T831
Test name
Test status
Simulation time 338052673 ps
CPU time 7.94 seconds
Started Jun 25 06:24:21 PM PDT 24
Finished Jun 25 06:24:59 PM PDT 24
Peak memory 246612 kb
Host smart-5243b4b0-8356-4174-9fda-7a54b5e5b37b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665725938 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_post_trans.1665725938
Directory /workspace/41.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all.2407159231
Short name T778
Test name
Test status
Simulation time 14358440159 ps
CPU time 83.55 seconds
Started Jun 25 06:24:24 PM PDT 24
Finished Jun 25 06:26:18 PM PDT 24
Peak memory 284144 kb
Host smart-3c323d12-241d-41be-b6fb-a6baf7b3e99a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407159231 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.lc_ctrl_stress_all.2407159231
Directory /workspace/41.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.lc_ctrl_volatile_unlock_smoke.1668386044
Short name T46
Test name
Test status
Simulation time 42181093 ps
CPU time 1 seconds
Started Jun 25 06:24:22 PM PDT 24
Finished Jun 25 06:24:54 PM PDT 24
Peak memory 212252 kb
Host smart-a120ae48-b3e8-4f5f-b36e-e7679f8da66e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668386044 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_c
trl_volatile_unlock_smoke.1668386044
Directory /workspace/41.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_alert_test.2406548382
Short name T478
Test name
Test status
Simulation time 27545551 ps
CPU time 1.37 seconds
Started Jun 25 06:24:26 PM PDT 24
Finished Jun 25 06:24:57 PM PDT 24
Peak memory 209344 kb
Host smart-a3a1c1e0-a12d-474b-8848-37fd27a03d4d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406548382 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_alert_test.2406548382
Directory /workspace/42.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.lc_ctrl_errors.2474127582
Short name T52
Test name
Test status
Simulation time 3327618009 ps
CPU time 21.49 seconds
Started Jun 25 06:24:26 PM PDT 24
Finished Jun 25 06:25:18 PM PDT 24
Peak memory 219376 kb
Host smart-bd49b9da-b427-4358-acb9-27dfa42265a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474127582 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_errors.2474127582
Directory /workspace/42.lc_ctrl_errors/latest

Test location /workspace/coverage/default/42.lc_ctrl_jtag_access.257092047
Short name T623
Test name
Test status
Simulation time 355002304 ps
CPU time 4.09 seconds
Started Jun 25 06:24:26 PM PDT 24
Finished Jun 25 06:25:00 PM PDT 24
Peak memory 217496 kb
Host smart-c513bc36-38d0-4827-a6d8-1f88d7c3dc41
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257092047 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_jtag_access.257092047
Directory /workspace/42.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/42.lc_ctrl_prog_failure.802451300
Short name T602
Test name
Test status
Simulation time 45960281 ps
CPU time 2.7 seconds
Started Jun 25 06:24:24 PM PDT 24
Finished Jun 25 06:24:58 PM PDT 24
Peak memory 218620 kb
Host smart-9ead6d56-6338-44ca-9ece-0225dc1f3f5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802451300 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_prog_failure.802451300
Directory /workspace/42.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_mubi.1138013615
Short name T807
Test name
Test status
Simulation time 2668585476 ps
CPU time 17.38 seconds
Started Jun 25 06:24:24 PM PDT 24
Finished Jun 25 06:25:12 PM PDT 24
Peak memory 226512 kb
Host smart-14316dfd-4d40-4f7b-b53c-34cc92e5c12e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138013615 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_mubi.1138013615
Directory /workspace/42.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_digest.3241769798
Short name T568
Test name
Test status
Simulation time 882291870 ps
CPU time 21.25 seconds
Started Jun 25 06:24:25 PM PDT 24
Finished Jun 25 06:25:16 PM PDT 24
Peak memory 218580 kb
Host smart-c563575c-4a27-468d-b428-e7b4cb9748a8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241769798 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_d
igest.3241769798
Directory /workspace/42.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_mux.1127572069
Short name T398
Test name
Test status
Simulation time 5823436945 ps
CPU time 15.08 seconds
Started Jun 25 06:24:26 PM PDT 24
Finished Jun 25 06:25:11 PM PDT 24
Peak memory 218584 kb
Host smart-cc4a8be8-421b-47aa-b31b-43667fbfd8fa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127572069 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_mux.
1127572069
Directory /workspace/42.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/42.lc_ctrl_security_escalation.708797876
Short name T655
Test name
Test status
Simulation time 751340799 ps
CPU time 13.66 seconds
Started Jun 25 06:24:24 PM PDT 24
Finished Jun 25 06:25:09 PM PDT 24
Peak memory 226380 kb
Host smart-773a88b4-4ad9-4306-b9e1-92045a08cff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708797876 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_security_escalation.708797876
Directory /workspace/42.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/42.lc_ctrl_smoke.6386885
Short name T786
Test name
Test status
Simulation time 459513099 ps
CPU time 3.22 seconds
Started Jun 25 06:24:24 PM PDT 24
Finished Jun 25 06:24:58 PM PDT 24
Peak memory 218072 kb
Host smart-d1db75e6-fade-42e9-a509-3a9fd9aaa320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6386885 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_smoke.6386885
Directory /workspace/42.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_failure.699246911
Short name T855
Test name
Test status
Simulation time 513028483 ps
CPU time 25.31 seconds
Started Jun 25 06:24:24 PM PDT 24
Finished Jun 25 06:25:20 PM PDT 24
Peak memory 251324 kb
Host smart-660c5984-f828-44a5-a14b-1c237f4ec86d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699246911 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_failure.699246911
Directory /workspace/42.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_post_trans.3182537316
Short name T286
Test name
Test status
Simulation time 524479364 ps
CPU time 6.76 seconds
Started Jun 25 06:24:26 PM PDT 24
Finished Jun 25 06:25:03 PM PDT 24
Peak memory 250896 kb
Host smart-e0673d60-441b-43ec-aaff-34b87ccff61f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182537316 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_post_trans.3182537316
Directory /workspace/42.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/42.lc_ctrl_stress_all.3051253023
Short name T94
Test name
Test status
Simulation time 19551303330 ps
CPU time 109.81 seconds
Started Jun 25 06:24:26 PM PDT 24
Finished Jun 25 06:26:46 PM PDT 24
Peak memory 226492 kb
Host smart-db3fbfed-f020-4bd0-a653-032fc1aa6154
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051253023 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.lc_ctrl_stress_all.3051253023
Directory /workspace/42.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.lc_ctrl_volatile_unlock_smoke.4069732156
Short name T599
Test name
Test status
Simulation time 21634939 ps
CPU time 0.94 seconds
Started Jun 25 06:24:24 PM PDT 24
Finished Jun 25 06:24:56 PM PDT 24
Peak memory 209280 kb
Host smart-2b287aab-7df2-4b22-9266-b7b357fb6adf
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069732156 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_c
trl_volatile_unlock_smoke.4069732156
Directory /workspace/42.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_alert_test.552682270
Short name T825
Test name
Test status
Simulation time 52228439 ps
CPU time 0.86 seconds
Started Jun 25 06:24:35 PM PDT 24
Finished Jun 25 06:25:01 PM PDT 24
Peak memory 209124 kb
Host smart-fe4281e7-4d06-4503-bedc-c04440a7c4ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552682270 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_alert_test.552682270
Directory /workspace/43.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.lc_ctrl_errors.2177056762
Short name T285
Test name
Test status
Simulation time 1221281794 ps
CPU time 11.72 seconds
Started Jun 25 06:24:32 PM PDT 24
Finished Jun 25 06:25:11 PM PDT 24
Peak memory 218668 kb
Host smart-ec753788-4092-441f-add5-8c0f2ec5a63b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177056762 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_errors.2177056762
Directory /workspace/43.lc_ctrl_errors/latest

Test location /workspace/coverage/default/43.lc_ctrl_jtag_access.3764129906
Short name T536
Test name
Test status
Simulation time 2743180837 ps
CPU time 6.13 seconds
Started Jun 25 06:24:32 PM PDT 24
Finished Jun 25 06:25:05 PM PDT 24
Peak memory 217940 kb
Host smart-c7ec9164-35b4-499b-9a71-b4d038f57cd2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764129906 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_jtag_access.3764129906
Directory /workspace/43.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/43.lc_ctrl_prog_failure.4280454477
Short name T3
Test name
Test status
Simulation time 152859379 ps
CPU time 2.37 seconds
Started Jun 25 06:24:31 PM PDT 24
Finished Jun 25 06:25:01 PM PDT 24
Peak memory 218624 kb
Host smart-3a8cddfa-8d17-47db-9aaa-05b089e487e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280454477 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_prog_failure.4280454477
Directory /workspace/43.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_mubi.778548022
Short name T368
Test name
Test status
Simulation time 2001813815 ps
CPU time 14.11 seconds
Started Jun 25 06:24:32 PM PDT 24
Finished Jun 25 06:25:14 PM PDT 24
Peak memory 226440 kb
Host smart-a978b453-3f5e-49f3-b226-8e4ec20f7a78
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778548022 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_mubi.778548022
Directory /workspace/43.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_digest.3716137169
Short name T290
Test name
Test status
Simulation time 868736482 ps
CPU time 11.94 seconds
Started Jun 25 06:24:33 PM PDT 24
Finished Jun 25 06:25:12 PM PDT 24
Peak memory 218520 kb
Host smart-2300f224-3f09-4f42-909a-efe530b4f2af
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716137169 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_d
igest.3716137169
Directory /workspace/43.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_mux.4059673342
Short name T787
Test name
Test status
Simulation time 699383343 ps
CPU time 8.08 seconds
Started Jun 25 06:24:31 PM PDT 24
Finished Jun 25 06:25:07 PM PDT 24
Peak memory 218564 kb
Host smart-1db864f8-b04e-46f4-a62c-db368ae72d19
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059673342 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_mux.
4059673342
Directory /workspace/43.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/43.lc_ctrl_security_escalation.3171196814
Short name T582
Test name
Test status
Simulation time 5333125466 ps
CPU time 11.9 seconds
Started Jun 25 06:24:31 PM PDT 24
Finished Jun 25 06:25:11 PM PDT 24
Peak memory 225916 kb
Host smart-76a265b0-6295-4190-9908-cf940f465e7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171196814 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_security_escalation.3171196814
Directory /workspace/43.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/43.lc_ctrl_smoke.1925838239
Short name T824
Test name
Test status
Simulation time 63530330 ps
CPU time 2.58 seconds
Started Jun 25 06:24:32 PM PDT 24
Finished Jun 25 06:25:02 PM PDT 24
Peak memory 218044 kb
Host smart-14512e1b-1e11-4f63-a084-59c992f3cbe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925838239 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_smoke.1925838239
Directory /workspace/43.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_failure.2316550226
Short name T476
Test name
Test status
Simulation time 228253218 ps
CPU time 22.63 seconds
Started Jun 25 06:24:31 PM PDT 24
Finished Jun 25 06:25:22 PM PDT 24
Peak memory 251280 kb
Host smart-d0839b3b-c098-4338-b125-ade963644d25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316550226 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_failure.2316550226
Directory /workspace/43.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_post_trans.1332353953
Short name T800
Test name
Test status
Simulation time 87604339 ps
CPU time 8.23 seconds
Started Jun 25 06:24:31 PM PDT 24
Finished Jun 25 06:25:07 PM PDT 24
Peak memory 251308 kb
Host smart-0499bbca-b6ef-4e9d-b729-28b5682f947b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332353953 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_post_trans.1332353953
Directory /workspace/43.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all.4031641528
Short name T81
Test name
Test status
Simulation time 7387093297 ps
CPU time 181.11 seconds
Started Jun 25 06:24:31 PM PDT 24
Finished Jun 25 06:28:00 PM PDT 24
Peak memory 284024 kb
Host smart-7b397204-5f83-490e-a3f2-ecd2bede13be
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031641528 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.lc_ctrl_stress_all.4031641528
Directory /workspace/43.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all_with_rand_reset.863706676
Short name T53
Test name
Test status
Simulation time 38571627494 ps
CPU time 1109.46 seconds
Started Jun 25 06:24:32 PM PDT 24
Finished Jun 25 06:43:29 PM PDT 24
Peak memory 368024 kb
Host smart-cdc64d9f-333e-4205-b318-f5aa7b1e8e13
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=863706676 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_stress_all_with_rand_reset.863706676
Directory /workspace/43.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.lc_ctrl_volatile_unlock_smoke.3202906201
Short name T818
Test name
Test status
Simulation time 13581118 ps
CPU time 0.89 seconds
Started Jun 25 06:24:33 PM PDT 24
Finished Jun 25 06:25:01 PM PDT 24
Peak memory 208924 kb
Host smart-eef2118e-8f98-4b16-a048-9be4d0efe8ee
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202906201 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_c
trl_volatile_unlock_smoke.3202906201
Directory /workspace/43.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_alert_test.1724791595
Short name T662
Test name
Test status
Simulation time 16192941 ps
CPU time 1.07 seconds
Started Jun 25 06:24:38 PM PDT 24
Finished Jun 25 06:25:03 PM PDT 24
Peak memory 209376 kb
Host smart-222b69c3-e950-4d38-9271-3b2dcf10ff12
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724791595 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_alert_test.1724791595
Directory /workspace/44.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.lc_ctrl_errors.3386915650
Short name T449
Test name
Test status
Simulation time 2965935457 ps
CPU time 11.52 seconds
Started Jun 25 06:24:33 PM PDT 24
Finished Jun 25 06:25:11 PM PDT 24
Peak memory 219344 kb
Host smart-cc8bcb70-3842-4958-b693-3b0ccbbc13e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386915650 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_errors.3386915650
Directory /workspace/44.lc_ctrl_errors/latest

Test location /workspace/coverage/default/44.lc_ctrl_jtag_access.2920444006
Short name T211
Test name
Test status
Simulation time 255522503 ps
CPU time 1.75 seconds
Started Jun 25 06:24:32 PM PDT 24
Finished Jun 25 06:25:01 PM PDT 24
Peak memory 217336 kb
Host smart-b02bac34-2164-41bc-a58f-5694818ec323
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920444006 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_jtag_access.2920444006
Directory /workspace/44.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/44.lc_ctrl_prog_failure.2782269346
Short name T263
Test name
Test status
Simulation time 90780511 ps
CPU time 3.51 seconds
Started Jun 25 06:24:32 PM PDT 24
Finished Jun 25 06:25:03 PM PDT 24
Peak memory 218712 kb
Host smart-241adb38-e65d-4ca8-aaaa-adff4ca8719e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782269346 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_prog_failure.2782269346
Directory /workspace/44.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_mubi.81614841
Short name T494
Test name
Test status
Simulation time 2075950260 ps
CPU time 13.95 seconds
Started Jun 25 06:24:39 PM PDT 24
Finished Jun 25 06:25:16 PM PDT 24
Peak memory 226444 kb
Host smart-5aa7aa2f-3782-43f6-bc8d-66405fc56b40
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81614841 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_mubi.81614841
Directory /workspace/44.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_digest.2144998112
Short name T811
Test name
Test status
Simulation time 467702893 ps
CPU time 17.23 seconds
Started Jun 25 06:24:38 PM PDT 24
Finished Jun 25 06:25:18 PM PDT 24
Peak memory 218592 kb
Host smart-bac224c5-e864-460c-b6d1-3b6285d59231
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144998112 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_d
igest.2144998112
Directory /workspace/44.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_mux.1985404184
Short name T862
Test name
Test status
Simulation time 777813144 ps
CPU time 12.97 seconds
Started Jun 25 06:24:40 PM PDT 24
Finished Jun 25 06:25:15 PM PDT 24
Peak memory 226364 kb
Host smart-aae070a2-e0e2-43cf-a505-254d83cb6534
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985404184 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_mux.
1985404184
Directory /workspace/44.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/44.lc_ctrl_security_escalation.1100512564
Short name T121
Test name
Test status
Simulation time 432694115 ps
CPU time 16.34 seconds
Started Jun 25 06:24:31 PM PDT 24
Finished Jun 25 06:25:15 PM PDT 24
Peak memory 218752 kb
Host smart-9081180d-a27f-495c-bb0c-d91877541410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100512564 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_security_escalation.1100512564
Directory /workspace/44.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/44.lc_ctrl_smoke.689549686
Short name T90
Test name
Test status
Simulation time 36794861 ps
CPU time 2.4 seconds
Started Jun 25 06:24:32 PM PDT 24
Finished Jun 25 06:25:02 PM PDT 24
Peak memory 214840 kb
Host smart-2c85a997-775c-4f14-b9c2-5c9fd0f0ed70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=689549686 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_smoke.689549686
Directory /workspace/44.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_failure.874579212
Short name T822
Test name
Test status
Simulation time 473750570 ps
CPU time 29.07 seconds
Started Jun 25 06:24:33 PM PDT 24
Finished Jun 25 06:25:29 PM PDT 24
Peak memory 251312 kb
Host smart-09ea6236-48af-4ba1-97b6-b37595c42a38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874579212 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_failure.874579212
Directory /workspace/44.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_post_trans.1112142196
Short name T15
Test name
Test status
Simulation time 70635207 ps
CPU time 7.28 seconds
Started Jun 25 06:24:32 PM PDT 24
Finished Jun 25 06:25:06 PM PDT 24
Peak memory 251264 kb
Host smart-d9a7615d-70dd-4c1f-b80c-36875d798b41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112142196 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_post_trans.1112142196
Directory /workspace/44.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/44.lc_ctrl_stress_all.1510106187
Short name T457
Test name
Test status
Simulation time 13589791670 ps
CPU time 58.68 seconds
Started Jun 25 06:24:42 PM PDT 24
Finished Jun 25 06:26:02 PM PDT 24
Peak memory 251360 kb
Host smart-2f821258-7366-4642-bf4f-c71509fe7ff1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510106187 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.lc_ctrl_stress_all.1510106187
Directory /workspace/44.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.lc_ctrl_alert_test.972893123
Short name T651
Test name
Test status
Simulation time 56966701 ps
CPU time 1.08 seconds
Started Jun 25 06:24:41 PM PDT 24
Finished Jun 25 06:25:04 PM PDT 24
Peak memory 209468 kb
Host smart-851cfed7-5357-42c7-88c8-135cc3eb5482
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972893123 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_alert_test.972893123
Directory /workspace/45.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.lc_ctrl_errors.2064144064
Short name T315
Test name
Test status
Simulation time 1104840925 ps
CPU time 14.63 seconds
Started Jun 25 06:24:39 PM PDT 24
Finished Jun 25 06:25:17 PM PDT 24
Peak memory 218576 kb
Host smart-42014624-b4fc-4c1b-b4bd-0acb905f7608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064144064 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_errors.2064144064
Directory /workspace/45.lc_ctrl_errors/latest

Test location /workspace/coverage/default/45.lc_ctrl_jtag_access.3767816166
Short name T695
Test name
Test status
Simulation time 370297709 ps
CPU time 7.78 seconds
Started Jun 25 06:24:38 PM PDT 24
Finished Jun 25 06:25:10 PM PDT 24
Peak memory 217820 kb
Host smart-7cf9663e-ebe6-4031-a9d2-23ece47c2ca9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767816166 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_jtag_access.3767816166
Directory /workspace/45.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/45.lc_ctrl_prog_failure.1474211072
Short name T725
Test name
Test status
Simulation time 107386156 ps
CPU time 4.56 seconds
Started Jun 25 06:24:40 PM PDT 24
Finished Jun 25 06:25:07 PM PDT 24
Peak memory 218592 kb
Host smart-9b63933f-b70c-4f53-b939-c72a39c92b86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474211072 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_prog_failure.1474211072
Directory /workspace/45.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_mubi.968646995
Short name T357
Test name
Test status
Simulation time 495679837 ps
CPU time 17.44 seconds
Started Jun 25 06:24:39 PM PDT 24
Finished Jun 25 06:25:20 PM PDT 24
Peak memory 219388 kb
Host smart-0230fb91-f700-4d55-a3b8-58c51f48f608
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968646995 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_mubi.968646995
Directory /workspace/45.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_digest.3104600327
Short name T579
Test name
Test status
Simulation time 220589810 ps
CPU time 8.55 seconds
Started Jun 25 06:24:41 PM PDT 24
Finished Jun 25 06:25:11 PM PDT 24
Peak memory 218700 kb
Host smart-fba771a7-7839-4f9f-9f96-36f623ecf274
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104600327 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_d
igest.3104600327
Directory /workspace/45.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_mux.289122301
Short name T666
Test name
Test status
Simulation time 233047185 ps
CPU time 7.52 seconds
Started Jun 25 06:24:41 PM PDT 24
Finished Jun 25 06:25:10 PM PDT 24
Peak memory 226384 kb
Host smart-9c73a981-9806-474d-9d60-ea8e3b62d50f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289122301 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_mux.289122301
Directory /workspace/45.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/45.lc_ctrl_security_escalation.3883654398
Short name T230
Test name
Test status
Simulation time 393285920 ps
CPU time 11.68 seconds
Started Jun 25 06:24:37 PM PDT 24
Finished Jun 25 06:25:12 PM PDT 24
Peak memory 225700 kb
Host smart-1a01d2df-45ce-453e-af89-76e3cc862e2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883654398 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_security_escalation.3883654398
Directory /workspace/45.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/45.lc_ctrl_smoke.3091782196
Short name T658
Test name
Test status
Simulation time 25296193 ps
CPU time 1.67 seconds
Started Jun 25 06:24:41 PM PDT 24
Finished Jun 25 06:25:04 PM PDT 24
Peak memory 218064 kb
Host smart-5142a43f-9db4-4014-ae44-854b89730b93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091782196 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_smoke.3091782196
Directory /workspace/45.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_failure.2333180521
Short name T352
Test name
Test status
Simulation time 1078438903 ps
CPU time 33.22 seconds
Started Jun 25 06:24:41 PM PDT 24
Finished Jun 25 06:25:36 PM PDT 24
Peak memory 251320 kb
Host smart-2d91ef68-7da0-413f-987d-230fa6e3ca4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333180521 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_failure.2333180521
Directory /workspace/45.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_post_trans.3362750660
Short name T734
Test name
Test status
Simulation time 57597584 ps
CPU time 6.79 seconds
Started Jun 25 06:24:40 PM PDT 24
Finished Jun 25 06:25:09 PM PDT 24
Peak memory 251284 kb
Host smart-25471d83-498f-4e41-8d93-856a941b3079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362750660 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_post_trans.3362750660
Directory /workspace/45.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/45.lc_ctrl_stress_all.1542752361
Short name T521
Test name
Test status
Simulation time 1653577829 ps
CPU time 46.32 seconds
Started Jun 25 06:24:40 PM PDT 24
Finished Jun 25 06:25:49 PM PDT 24
Peak memory 248672 kb
Host smart-01d8077a-a270-45ca-ba80-499e02dd5c58
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542752361 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.lc_ctrl_stress_all.1542752361
Directory /workspace/45.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.lc_ctrl_volatile_unlock_smoke.4178746956
Short name T508
Test name
Test status
Simulation time 18658601 ps
CPU time 0.94 seconds
Started Jun 25 06:24:41 PM PDT 24
Finished Jun 25 06:25:04 PM PDT 24
Peak memory 209268 kb
Host smart-0ac031e8-680e-43fb-a01b-8639fdc2c429
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178746956 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_c
trl_volatile_unlock_smoke.4178746956
Directory /workspace/45.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_alert_test.3239620275
Short name T306
Test name
Test status
Simulation time 93226330 ps
CPU time 0.89 seconds
Started Jun 25 06:24:49 PM PDT 24
Finished Jun 25 06:25:06 PM PDT 24
Peak memory 209280 kb
Host smart-f4cb5b83-561e-4117-a02e-f887476219b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239620275 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_alert_test.3239620275
Directory /workspace/46.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.lc_ctrl_errors.1246862054
Short name T381
Test name
Test status
Simulation time 796106038 ps
CPU time 21.52 seconds
Started Jun 25 06:24:39 PM PDT 24
Finished Jun 25 06:25:24 PM PDT 24
Peak memory 218552 kb
Host smart-f6a51da6-8bec-458e-88db-bd97826d2edb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246862054 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_errors.1246862054
Directory /workspace/46.lc_ctrl_errors/latest

Test location /workspace/coverage/default/46.lc_ctrl_jtag_access.80612914
Short name T728
Test name
Test status
Simulation time 658109290 ps
CPU time 9.06 seconds
Started Jun 25 06:24:40 PM PDT 24
Finished Jun 25 06:25:11 PM PDT 24
Peak memory 217536 kb
Host smart-188e74a6-2fd1-4b41-b37b-dfb8ada6ac30
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80612914 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_jtag_access.80612914
Directory /workspace/46.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/46.lc_ctrl_prog_failure.3003175893
Short name T280
Test name
Test status
Simulation time 54425527 ps
CPU time 2.2 seconds
Started Jun 25 06:24:39 PM PDT 24
Finished Jun 25 06:25:04 PM PDT 24
Peak memory 218620 kb
Host smart-5fa13b89-1819-460a-9988-f45854594120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003175893 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_prog_failure.3003175893
Directory /workspace/46.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_mubi.2877626044
Short name T234
Test name
Test status
Simulation time 1383408032 ps
CPU time 14.89 seconds
Started Jun 25 06:24:40 PM PDT 24
Finished Jun 25 06:25:17 PM PDT 24
Peak memory 219396 kb
Host smart-81f6796b-ccc5-4779-920c-6b9f4cddbdbe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877626044 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_mubi.2877626044
Directory /workspace/46.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_digest.3739298105
Short name T9
Test name
Test status
Simulation time 523313403 ps
CPU time 11.12 seconds
Started Jun 25 06:24:38 PM PDT 24
Finished Jun 25 06:25:12 PM PDT 24
Peak memory 218576 kb
Host smart-63fa607a-1cbd-4ca4-bfdd-525ddb8b14be
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739298105 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_d
igest.3739298105
Directory /workspace/46.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_mux.3894678478
Short name T380
Test name
Test status
Simulation time 259009160 ps
CPU time 10.38 seconds
Started Jun 25 06:24:40 PM PDT 24
Finished Jun 25 06:25:13 PM PDT 24
Peak memory 218576 kb
Host smart-57f5cc8b-4e46-4213-bc82-3036d763d4cc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894678478 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_mux.
3894678478
Directory /workspace/46.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/46.lc_ctrl_security_escalation.2987861833
Short name T773
Test name
Test status
Simulation time 373019183 ps
CPU time 10.55 seconds
Started Jun 25 06:24:38 PM PDT 24
Finished Jun 25 06:25:13 PM PDT 24
Peak memory 218692 kb
Host smart-73cfa2af-3d72-4251-aeeb-34aacef9913f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987861833 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_security_escalation.2987861833
Directory /workspace/46.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/46.lc_ctrl_smoke.1689240575
Short name T723
Test name
Test status
Simulation time 72110348 ps
CPU time 3.47 seconds
Started Jun 25 06:24:38 PM PDT 24
Finished Jun 25 06:25:06 PM PDT 24
Peak memory 215128 kb
Host smart-2c9621f8-58ba-410a-ad61-fbaea055e531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689240575 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_smoke.1689240575
Directory /workspace/46.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_failure.4240004276
Short name T407
Test name
Test status
Simulation time 1713120840 ps
CPU time 25.16 seconds
Started Jun 25 06:24:38 PM PDT 24
Finished Jun 25 06:25:26 PM PDT 24
Peak memory 251272 kb
Host smart-0b5a9373-52f4-43be-b273-701950ccb25c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4240004276 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_failure.4240004276
Directory /workspace/46.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_post_trans.969164383
Short name T492
Test name
Test status
Simulation time 115222412 ps
CPU time 4.16 seconds
Started Jun 25 06:24:39 PM PDT 24
Finished Jun 25 06:25:06 PM PDT 24
Peak memory 223244 kb
Host smart-4f67d7b5-06f0-45d6-9446-7b956072e342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969164383 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_post_trans.969164383
Directory /workspace/46.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all.1330713666
Short name T866
Test name
Test status
Simulation time 10791164108 ps
CPU time 126.94 seconds
Started Jun 25 06:24:45 PM PDT 24
Finished Jun 25 06:27:11 PM PDT 24
Peak memory 251344 kb
Host smart-6929d886-9b43-457a-92ea-ad1400e72a77
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330713666 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.lc_ctrl_stress_all.1330713666
Directory /workspace/46.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all_with_rand_reset.4096670119
Short name T700
Test name
Test status
Simulation time 86103116321 ps
CPU time 435.89 seconds
Started Jun 25 06:24:44 PM PDT 24
Finished Jun 25 06:32:20 PM PDT 24
Peak memory 276096 kb
Host smart-0e09e893-bc2e-45d1-b909-bb42b0650cd2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4096670119 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_stress_all_with_rand_reset.4096670119
Directory /workspace/46.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.lc_ctrl_volatile_unlock_smoke.1519485090
Short name T646
Test name
Test status
Simulation time 13967821 ps
CPU time 1.01 seconds
Started Jun 25 06:24:38 PM PDT 24
Finished Jun 25 06:25:02 PM PDT 24
Peak memory 209332 kb
Host smart-83261105-997a-4640-91a6-b8c87c361a11
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519485090 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_c
trl_volatile_unlock_smoke.1519485090
Directory /workspace/46.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_alert_test.1230302604
Short name T667
Test name
Test status
Simulation time 184388639 ps
CPU time 0.96 seconds
Started Jun 25 06:24:53 PM PDT 24
Finished Jun 25 06:25:07 PM PDT 24
Peak memory 209392 kb
Host smart-cb89906f-09d1-4fb8-a89d-70b353877040
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230302604 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_alert_test.1230302604
Directory /workspace/47.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.lc_ctrl_errors.3258433235
Short name T550
Test name
Test status
Simulation time 402775729 ps
CPU time 8.5 seconds
Started Jun 25 06:24:49 PM PDT 24
Finished Jun 25 06:25:14 PM PDT 24
Peak memory 218572 kb
Host smart-5928b102-cb3e-4d23-879c-769daf89b9b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258433235 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_errors.3258433235
Directory /workspace/47.lc_ctrl_errors/latest

Test location /workspace/coverage/default/47.lc_ctrl_jtag_access.3697525290
Short name T654
Test name
Test status
Simulation time 1585753208 ps
CPU time 7.07 seconds
Started Jun 25 06:24:45 PM PDT 24
Finished Jun 25 06:25:11 PM PDT 24
Peak memory 217728 kb
Host smart-b0156c3b-73b6-4045-b111-e2f000a2015a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697525290 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_jtag_access.3697525290
Directory /workspace/47.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/47.lc_ctrl_prog_failure.1765343506
Short name T774
Test name
Test status
Simulation time 53516039 ps
CPU time 3.1 seconds
Started Jun 25 06:24:46 PM PDT 24
Finished Jun 25 06:25:07 PM PDT 24
Peak memory 222880 kb
Host smart-44c9692f-0fc8-4fa7-af5f-b1a9c9870671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765343506 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_prog_failure.1765343506
Directory /workspace/47.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_mubi.623307537
Short name T430
Test name
Test status
Simulation time 2435250139 ps
CPU time 9.07 seconds
Started Jun 25 06:24:45 PM PDT 24
Finished Jun 25 06:25:13 PM PDT 24
Peak memory 226468 kb
Host smart-1c400c84-d929-4cb5-9988-deac8e168c30
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623307537 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_mubi.623307537
Directory /workspace/47.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_digest.1197731740
Short name T113
Test name
Test status
Simulation time 2935990622 ps
CPU time 15.65 seconds
Started Jun 25 06:24:47 PM PDT 24
Finished Jun 25 06:25:20 PM PDT 24
Peak memory 218640 kb
Host smart-c46d6c90-71df-4daf-81c6-d9d4553d9da3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197731740 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_d
igest.1197731740
Directory /workspace/47.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_mux.2515003376
Short name T641
Test name
Test status
Simulation time 1127973675 ps
CPU time 12.46 seconds
Started Jun 25 06:24:46 PM PDT 24
Finished Jun 25 06:25:17 PM PDT 24
Peak memory 226360 kb
Host smart-7f20cfc4-5a1f-41b6-abb6-f37366bd69b4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515003376 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_mux.
2515003376
Directory /workspace/47.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/47.lc_ctrl_security_escalation.3916653828
Short name T701
Test name
Test status
Simulation time 1474576617 ps
CPU time 13.36 seconds
Started Jun 25 06:24:49 PM PDT 24
Finished Jun 25 06:25:19 PM PDT 24
Peak memory 225548 kb
Host smart-826a8eaf-1e92-483a-8aba-b8c53f5b63fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916653828 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_security_escalation.3916653828
Directory /workspace/47.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/47.lc_ctrl_smoke.3497163295
Short name T96
Test name
Test status
Simulation time 176533519 ps
CPU time 2.39 seconds
Started Jun 25 06:24:44 PM PDT 24
Finished Jun 25 06:25:07 PM PDT 24
Peak memory 223740 kb
Host smart-13fec3fe-4c5e-4fe6-8cd5-1de105e0016e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497163295 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_smoke.3497163295
Directory /workspace/47.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_failure.3644680933
Short name T607
Test name
Test status
Simulation time 254506087 ps
CPU time 29.25 seconds
Started Jun 25 06:24:45 PM PDT 24
Finished Jun 25 06:25:33 PM PDT 24
Peak memory 245944 kb
Host smart-0e9cf5f9-17b3-4e7e-83b1-da11001c1802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644680933 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_failure.3644680933
Directory /workspace/47.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_post_trans.4057376789
Short name T379
Test name
Test status
Simulation time 100610736 ps
CPU time 8.2 seconds
Started Jun 25 06:24:45 PM PDT 24
Finished Jun 25 06:25:12 PM PDT 24
Peak memory 251328 kb
Host smart-d005f164-eda2-4cd6-b517-2c1fa1466f89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057376789 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_post_trans.4057376789
Directory /workspace/47.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/47.lc_ctrl_stress_all.1952614758
Short name T137
Test name
Test status
Simulation time 61945850090 ps
CPU time 257.85 seconds
Started Jun 25 06:24:54 PM PDT 24
Finished Jun 25 06:29:24 PM PDT 24
Peak memory 276400 kb
Host smart-f776539c-76a6-4988-b472-3dd0e88e2d7a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952614758 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.lc_ctrl_stress_all.1952614758
Directory /workspace/47.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.lc_ctrl_volatile_unlock_smoke.546218862
Short name T810
Test name
Test status
Simulation time 14530926 ps
CPU time 0.98 seconds
Started Jun 25 06:24:45 PM PDT 24
Finished Jun 25 06:25:05 PM PDT 24
Peak memory 209324 kb
Host smart-55edc87d-6523-47f9-ba3c-4186c4423c6d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546218862 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ct
rl_volatile_unlock_smoke.546218862
Directory /workspace/47.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_alert_test.2820166773
Short name T711
Test name
Test status
Simulation time 317902621 ps
CPU time 0.93 seconds
Started Jun 25 06:25:07 PM PDT 24
Finished Jun 25 06:25:10 PM PDT 24
Peak memory 209276 kb
Host smart-d8d843a8-9a20-4260-a0c9-93332f3a1054
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820166773 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_alert_test.2820166773
Directory /workspace/48.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.lc_ctrl_errors.1879182987
Short name T745
Test name
Test status
Simulation time 695780320 ps
CPU time 14.47 seconds
Started Jun 25 06:25:10 PM PDT 24
Finished Jun 25 06:25:27 PM PDT 24
Peak memory 218636 kb
Host smart-58692427-0196-49bd-a3d6-911cf1393a4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879182987 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_errors.1879182987
Directory /workspace/48.lc_ctrl_errors/latest

Test location /workspace/coverage/default/48.lc_ctrl_jtag_access.3473810379
Short name T553
Test name
Test status
Simulation time 254093397 ps
CPU time 3.17 seconds
Started Jun 25 06:25:07 PM PDT 24
Finished Jun 25 06:25:13 PM PDT 24
Peak memory 217440 kb
Host smart-9980442e-9eb7-4f1c-a810-4691265ab8ab
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473810379 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_jtag_access.3473810379
Directory /workspace/48.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/48.lc_ctrl_prog_failure.3086186345
Short name T479
Test name
Test status
Simulation time 44957407 ps
CPU time 2.11 seconds
Started Jun 25 06:24:51 PM PDT 24
Finished Jun 25 06:25:08 PM PDT 24
Peak memory 218612 kb
Host smart-e9ae1f31-f8ad-4946-8b05-9e3cefdedfa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086186345 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_prog_failure.3086186345
Directory /workspace/48.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_mubi.4025544068
Short name T767
Test name
Test status
Simulation time 257812326 ps
CPU time 10.17 seconds
Started Jun 25 06:25:09 PM PDT 24
Finished Jun 25 06:25:21 PM PDT 24
Peak memory 219264 kb
Host smart-2c00a4ee-381f-4ee5-82f7-37eb34033d0c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025544068 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_mubi.4025544068
Directory /workspace/48.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_digest.2022662939
Short name T441
Test name
Test status
Simulation time 532066702 ps
CPU time 12.78 seconds
Started Jun 25 06:25:08 PM PDT 24
Finished Jun 25 06:25:23 PM PDT 24
Peak memory 218580 kb
Host smart-25ac8a54-8db4-4722-b560-c234b6a5dc12
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022662939 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_d
igest.2022662939
Directory /workspace/48.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_mux.3272930964
Short name T693
Test name
Test status
Simulation time 583363146 ps
CPU time 12.03 seconds
Started Jun 25 06:25:08 PM PDT 24
Finished Jun 25 06:25:22 PM PDT 24
Peak memory 226300 kb
Host smart-b72ad672-44d4-4289-af6c-0d254a56eca1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272930964 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_mux.
3272930964
Directory /workspace/48.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/48.lc_ctrl_security_escalation.1317092307
Short name T354
Test name
Test status
Simulation time 212620244 ps
CPU time 7.19 seconds
Started Jun 25 06:25:08 PM PDT 24
Finished Jun 25 06:25:17 PM PDT 24
Peak memory 226448 kb
Host smart-5032dac4-0a36-41e6-8a7c-20344ea61a74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317092307 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_security_escalation.1317092307
Directory /workspace/48.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/48.lc_ctrl_smoke.1114984574
Short name T619
Test name
Test status
Simulation time 264235745 ps
CPU time 3.73 seconds
Started Jun 25 06:24:54 PM PDT 24
Finished Jun 25 06:25:10 PM PDT 24
Peak memory 215568 kb
Host smart-3bc99fe2-1a6f-4a99-82f7-b7eecbd31abb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114984574 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_smoke.1114984574
Directory /workspace/48.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_failure.3343754619
Short name T43
Test name
Test status
Simulation time 284550862 ps
CPU time 22.69 seconds
Started Jun 25 06:24:53 PM PDT 24
Finished Jun 25 06:25:29 PM PDT 24
Peak memory 251340 kb
Host smart-86e4d05d-b577-4d2a-8a3a-6bf43a6370ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343754619 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_failure.3343754619
Directory /workspace/48.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_post_trans.2725316970
Short name T205
Test name
Test status
Simulation time 136069515 ps
CPU time 3.69 seconds
Started Jun 25 06:24:53 PM PDT 24
Finished Jun 25 06:25:09 PM PDT 24
Peak memory 223308 kb
Host smart-395a596c-3104-4eca-82f5-56f55a9c0178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725316970 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_post_trans.2725316970
Directory /workspace/48.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all.4004818987
Short name T416
Test name
Test status
Simulation time 12376570928 ps
CPU time 133.97 seconds
Started Jun 25 06:25:08 PM PDT 24
Finished Jun 25 06:27:24 PM PDT 24
Peak memory 251308 kb
Host smart-6d2ef0c1-2bbd-4bd2-b255-d1398c689051
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004818987 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.lc_ctrl_stress_all.4004818987
Directory /workspace/48.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.lc_ctrl_volatile_unlock_smoke.2308040213
Short name T737
Test name
Test status
Simulation time 13904273 ps
CPU time 0.79 seconds
Started Jun 25 06:24:54 PM PDT 24
Finished Jun 25 06:25:07 PM PDT 24
Peak memory 209212 kb
Host smart-bf444699-5b5d-4d1b-a607-b1e1b78ae5b0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308040213 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_c
trl_volatile_unlock_smoke.2308040213
Directory /workspace/48.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_alert_test.2847384740
Short name T271
Test name
Test status
Simulation time 54797638 ps
CPU time 0.88 seconds
Started Jun 25 06:25:13 PM PDT 24
Finished Jun 25 06:25:16 PM PDT 24
Peak memory 209352 kb
Host smart-3985139d-219a-45b5-9dd7-7a79766d9875
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847384740 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_alert_test.2847384740
Directory /workspace/49.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.lc_ctrl_errors.2995335876
Short name T473
Test name
Test status
Simulation time 1188831101 ps
CPU time 13.6 seconds
Started Jun 25 06:25:08 PM PDT 24
Finished Jun 25 06:25:24 PM PDT 24
Peak memory 218620 kb
Host smart-475cd1ec-c344-499b-9706-a3ad720c4e67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995335876 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_errors.2995335876
Directory /workspace/49.lc_ctrl_errors/latest

Test location /workspace/coverage/default/49.lc_ctrl_jtag_access.1508989134
Short name T488
Test name
Test status
Simulation time 2666602213 ps
CPU time 7.33 seconds
Started Jun 25 06:25:11 PM PDT 24
Finished Jun 25 06:25:21 PM PDT 24
Peak memory 217892 kb
Host smart-29b04976-a755-4606-ba1f-0f778599a69e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508989134 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_jtag_access.1508989134
Directory /workspace/49.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/49.lc_ctrl_prog_failure.1523331231
Short name T115
Test name
Test status
Simulation time 1107199067 ps
CPU time 3.69 seconds
Started Jun 25 06:25:08 PM PDT 24
Finished Jun 25 06:25:14 PM PDT 24
Peak memory 222704 kb
Host smart-90a58918-ffb2-449c-92ed-aa9e1d4f05aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523331231 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_prog_failure.1523331231
Directory /workspace/49.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_mubi.374842108
Short name T620
Test name
Test status
Simulation time 383854755 ps
CPU time 9.97 seconds
Started Jun 25 06:25:12 PM PDT 24
Finished Jun 25 06:25:25 PM PDT 24
Peak memory 226428 kb
Host smart-39b154ac-ab1c-42e4-8b9c-d58c68038aa7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374842108 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_mubi.374842108
Directory /workspace/49.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_digest.558528191
Short name T487
Test name
Test status
Simulation time 322332884 ps
CPU time 11.95 seconds
Started Jun 25 06:25:08 PM PDT 24
Finished Jun 25 06:25:22 PM PDT 24
Peak memory 218568 kb
Host smart-ee9f939b-9034-4645-a74e-501ca9b8c9f2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558528191 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_di
gest.558528191
Directory /workspace/49.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_mux.1434198157
Short name T108
Test name
Test status
Simulation time 456439228 ps
CPU time 10.6 seconds
Started Jun 25 06:25:10 PM PDT 24
Finished Jun 25 06:25:23 PM PDT 24
Peak memory 218584 kb
Host smart-e508ee3b-7368-4e3e-8740-edd9d19fdf90
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434198157 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_mux.
1434198157
Directory /workspace/49.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/49.lc_ctrl_security_escalation.380617075
Short name T506
Test name
Test status
Simulation time 833327949 ps
CPU time 10.93 seconds
Started Jun 25 06:25:10 PM PDT 24
Finished Jun 25 06:25:24 PM PDT 24
Peak memory 218688 kb
Host smart-442da493-6485-4591-83e2-c49d8d6d5b88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380617075 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_security_escalation.380617075
Directory /workspace/49.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/49.lc_ctrl_smoke.3484217437
Short name T692
Test name
Test status
Simulation time 105940120 ps
CPU time 2.43 seconds
Started Jun 25 06:25:05 PM PDT 24
Finished Jun 25 06:25:11 PM PDT 24
Peak memory 218052 kb
Host smart-6db26af3-58da-425b-b3d9-d94c92c1341b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484217437 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_smoke.3484217437
Directory /workspace/49.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_failure.3296507540
Short name T451
Test name
Test status
Simulation time 512790179 ps
CPU time 23.1 seconds
Started Jun 25 06:25:07 PM PDT 24
Finished Jun 25 06:25:33 PM PDT 24
Peak memory 251420 kb
Host smart-55faa282-3edd-421e-9a4b-cdd095c11acd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296507540 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_failure.3296507540
Directory /workspace/49.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_post_trans.1761896650
Short name T519
Test name
Test status
Simulation time 79583784 ps
CPU time 7.38 seconds
Started Jun 25 06:25:07 PM PDT 24
Finished Jun 25 06:25:17 PM PDT 24
Peak memory 251296 kb
Host smart-8630c1a6-1038-4cfe-983b-c417994967c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761896650 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_post_trans.1761896650
Directory /workspace/49.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/49.lc_ctrl_stress_all.648222403
Short name T768
Test name
Test status
Simulation time 4347549620 ps
CPU time 76.96 seconds
Started Jun 25 06:25:13 PM PDT 24
Finished Jun 25 06:26:32 PM PDT 24
Peak memory 267756 kb
Host smart-0adf8f02-9427-43dd-94d1-520a3b0083c4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648222403 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.lc_ctrl_stress_all.648222403
Directory /workspace/49.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.lc_ctrl_volatile_unlock_smoke.256550874
Short name T699
Test name
Test status
Simulation time 12660426 ps
CPU time 0.83 seconds
Started Jun 25 06:25:08 PM PDT 24
Finished Jun 25 06:25:11 PM PDT 24
Peak memory 209200 kb
Host smart-0e676692-be22-44d5-868e-dbe44d0f4b2d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256550874 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ct
rl_volatile_unlock_smoke.256550874
Directory /workspace/49.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_alert_test.757135738
Short name T273
Test name
Test status
Simulation time 23803861 ps
CPU time 0.99 seconds
Started Jun 25 06:20:16 PM PDT 24
Finished Jun 25 06:20:18 PM PDT 24
Peak memory 209272 kb
Host smart-c4e96656-127f-4251-8e2e-78d290986b8c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757135738 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_alert_test.757135738
Directory /workspace/5.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.lc_ctrl_claim_transition_if.3359659101
Short name T251
Test name
Test status
Simulation time 67792018 ps
CPU time 0.88 seconds
Started Jun 25 06:20:04 PM PDT 24
Finished Jun 25 06:20:07 PM PDT 24
Peak memory 209120 kb
Host smart-0ffa3a22-7dae-44a4-a5b3-8315d061bdf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359659101 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_claim_transition_if.3359659101
Directory /workspace/5.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/5.lc_ctrl_errors.63087756
Short name T724
Test name
Test status
Simulation time 195980845 ps
CPU time 8.03 seconds
Started Jun 25 06:20:04 PM PDT 24
Finished Jun 25 06:20:13 PM PDT 24
Peak memory 218628 kb
Host smart-23f2bff1-1b46-4db3-b6be-2994959fc0d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63087756 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_errors.63087756
Directory /workspace/5.lc_ctrl_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_access.906136455
Short name T616
Test name
Test status
Simulation time 381792701 ps
CPU time 3.68 seconds
Started Jun 25 06:20:14 PM PDT 24
Finished Jun 25 06:20:19 PM PDT 24
Peak memory 217668 kb
Host smart-eee8247a-3cb7-430b-8367-016152a912e5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906136455 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_access.906136455
Directory /workspace/5.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_errors.3334869609
Short name T288
Test name
Test status
Simulation time 3068656492 ps
CPU time 42.2 seconds
Started Jun 25 06:20:15 PM PDT 24
Finished Jun 25 06:20:59 PM PDT 24
Peak memory 218632 kb
Host smart-96878af0-0c71-4585-9655-650b867fcbd0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334869609 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_er
rors.3334869609
Directory /workspace/5.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_prog_failure.1694102659
Short name T347
Test name
Test status
Simulation time 121772807 ps
CPU time 4.79 seconds
Started Jun 25 06:20:03 PM PDT 24
Finished Jun 25 06:20:09 PM PDT 24
Peak memory 218576 kb
Host smart-e7ea2c39-2c4c-49a3-a906-27c4d1258d2a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694102659 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag
_prog_failure.1694102659
Directory /workspace/5.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_regwen_during_op.3420933207
Short name T834
Test name
Test status
Simulation time 3287523015 ps
CPU time 24.98 seconds
Started Jun 25 06:20:14 PM PDT 24
Finished Jun 25 06:20:40 PM PDT 24
Peak memory 218064 kb
Host smart-7da8cec0-7623-4cae-9683-8382dbc1aece
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420933207 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_regwen_during_op.3420933207
Directory /workspace/5.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_smoke.2466274247
Short name T769
Test name
Test status
Simulation time 772824236 ps
CPU time 4.59 seconds
Started Jun 25 06:20:04 PM PDT 24
Finished Jun 25 06:20:10 PM PDT 24
Peak memory 218096 kb
Host smart-872c34c3-2a7b-4bd3-8e81-bafc459578ee
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466274247 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_smoke.
2466274247
Directory /workspace/5.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_failure.2841896960
Short name T266
Test name
Test status
Simulation time 5068201789 ps
CPU time 29.91 seconds
Started Jun 25 06:20:03 PM PDT 24
Finished Jun 25 06:20:34 PM PDT 24
Peak memory 251328 kb
Host smart-23c55ec1-46ab-4158-bf7e-3e91a02f8f67
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841896960 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jta
g_state_failure.2841896960
Directory /workspace/5.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_post_trans.3528017293
Short name T239
Test name
Test status
Simulation time 1748743628 ps
CPU time 18.83 seconds
Started Jun 25 06:20:04 PM PDT 24
Finished Jun 25 06:20:24 PM PDT 24
Peak memory 251224 kb
Host smart-763d9db0-e26a-4c64-af99-2b82ace2aa63
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528017293 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_state_post_trans.3528017293
Directory /workspace/5.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_prog_failure.1524003911
Short name T237
Test name
Test status
Simulation time 28253019 ps
CPU time 1.5 seconds
Started Jun 25 06:20:04 PM PDT 24
Finished Jun 25 06:20:07 PM PDT 24
Peak memory 218628 kb
Host smart-a4f0dd59-860d-4808-bb20-c1a9d5ba227b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524003911 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_prog_failure.1524003911
Directory /workspace/5.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_regwen_during_op.3143348817
Short name T134
Test name
Test status
Simulation time 418404587 ps
CPU time 5.75 seconds
Started Jun 25 06:20:01 PM PDT 24
Finished Jun 25 06:20:07 PM PDT 24
Peak memory 214828 kb
Host smart-dd813228-d63f-46ed-9896-775a51504c28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143348817 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_regwen_during_op.3143348817
Directory /workspace/5.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_mubi.1594829656
Short name T425
Test name
Test status
Simulation time 1621031399 ps
CPU time 18.18 seconds
Started Jun 25 06:20:15 PM PDT 24
Finished Jun 25 06:20:35 PM PDT 24
Peak memory 226452 kb
Host smart-3b561b8e-cda4-4cad-9826-95f8f4f86303
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594829656 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_mubi.1594829656
Directory /workspace/5.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_digest.3069306950
Short name T355
Test name
Test status
Simulation time 751777686 ps
CPU time 12.61 seconds
Started Jun 25 06:20:17 PM PDT 24
Finished Jun 25 06:20:31 PM PDT 24
Peak memory 218688 kb
Host smart-98a6f400-9740-48f8-8288-a0222f7d27d8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069306950 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_di
gest.3069306950
Directory /workspace/5.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_mux.149425645
Short name T467
Test name
Test status
Simulation time 999512246 ps
CPU time 11.85 seconds
Started Jun 25 06:20:16 PM PDT 24
Finished Jun 25 06:20:29 PM PDT 24
Peak memory 218576 kb
Host smart-aa89fa47-36ac-4bae-85d8-39e84f362001
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149425645 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_mux.149425645
Directory /workspace/5.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/5.lc_ctrl_security_escalation.1352825229
Short name T231
Test name
Test status
Simulation time 1457873824 ps
CPU time 10.64 seconds
Started Jun 25 06:20:03 PM PDT 24
Finished Jun 25 06:20:14 PM PDT 24
Peak memory 225408 kb
Host smart-46ce797f-9fdf-4de1-84b9-0938ffceead8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352825229 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_security_escalation.1352825229
Directory /workspace/5.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/5.lc_ctrl_smoke.2853654005
Short name T814
Test name
Test status
Simulation time 203673752 ps
CPU time 2.23 seconds
Started Jun 25 06:20:03 PM PDT 24
Finished Jun 25 06:20:07 PM PDT 24
Peak memory 214468 kb
Host smart-277716ab-3a8c-4733-a597-7f26ffc6a6c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853654005 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_smoke.2853654005
Directory /workspace/5.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_failure.1964536925
Short name T408
Test name
Test status
Simulation time 1131015885 ps
CPU time 30.76 seconds
Started Jun 25 06:20:02 PM PDT 24
Finished Jun 25 06:20:34 PM PDT 24
Peak memory 251432 kb
Host smart-ff44d203-d323-4a29-861c-565553570940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964536925 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_failure.1964536925
Directory /workspace/5.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_post_trans.1584421730
Short name T776
Test name
Test status
Simulation time 299357845 ps
CPU time 9.41 seconds
Started Jun 25 06:20:03 PM PDT 24
Finished Jun 25 06:20:14 PM PDT 24
Peak memory 251324 kb
Host smart-7dbc66cb-ea30-4d7d-b578-a5f0084405ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584421730 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_post_trans.1584421730
Directory /workspace/5.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_stress_all.880857740
Short name T562
Test name
Test status
Simulation time 2493650340 ps
CPU time 67.07 seconds
Started Jun 25 06:20:15 PM PDT 24
Finished Jun 25 06:21:24 PM PDT 24
Peak memory 250116 kb
Host smart-200eb04f-0bc0-4074-9691-2bb033dc8a09
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880857740 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.lc_ctrl_stress_all.880857740
Directory /workspace/5.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.lc_ctrl_volatile_unlock_smoke.998574652
Short name T447
Test name
Test status
Simulation time 14529776 ps
CPU time 1.13 seconds
Started Jun 25 06:20:04 PM PDT 24
Finished Jun 25 06:20:07 PM PDT 24
Peak memory 212252 kb
Host smart-9a5edf8d-d033-4fa7-bb76-b910e470e579
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998574652 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctr
l_volatile_unlock_smoke.998574652
Directory /workspace/5.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_alert_test.1410309569
Short name T761
Test name
Test status
Simulation time 103673437 ps
CPU time 0.98 seconds
Started Jun 25 06:20:27 PM PDT 24
Finished Jun 25 06:20:28 PM PDT 24
Peak memory 209416 kb
Host smart-61262ff9-1320-4039-989f-dbcedfd1efee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410309569 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_alert_test.1410309569
Directory /workspace/6.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.lc_ctrl_errors.2163769016
Short name T462
Test name
Test status
Simulation time 6463574661 ps
CPU time 16.8 seconds
Started Jun 25 06:20:15 PM PDT 24
Finished Jun 25 06:20:33 PM PDT 24
Peak memory 219352 kb
Host smart-54f6999a-877b-462c-86dc-e02897b9f2a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163769016 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_errors.2163769016
Directory /workspace/6.lc_ctrl_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_access.2274896169
Short name T867
Test name
Test status
Simulation time 509770331 ps
CPU time 3.18 seconds
Started Jun 25 06:20:26 PM PDT 24
Finished Jun 25 06:20:30 PM PDT 24
Peak memory 217392 kb
Host smart-089deb03-97a8-480d-810b-d97666167a2a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274896169 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_access.2274896169
Directory /workspace/6.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_errors.1307814001
Short name T5
Test name
Test status
Simulation time 1768012394 ps
CPU time 52.07 seconds
Started Jun 25 06:20:22 PM PDT 24
Finished Jun 25 06:21:15 PM PDT 24
Peak memory 226368 kb
Host smart-772f96a4-6632-45fb-92bc-8a73fbeda3e4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307814001 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_er
rors.1307814001
Directory /workspace/6.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_priority.2755430120
Short name T719
Test name
Test status
Simulation time 2322727717 ps
CPU time 27.53 seconds
Started Jun 25 06:20:23 PM PDT 24
Finished Jun 25 06:20:51 PM PDT 24
Peak memory 218172 kb
Host smart-a2c27a1d-943d-422a-aae1-11d37ea874ca
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755430120 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_priority.2
755430120
Directory /workspace/6.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_prog_failure.1704190603
Short name T747
Test name
Test status
Simulation time 1509951188 ps
CPU time 20.45 seconds
Started Jun 25 06:20:23 PM PDT 24
Finished Jun 25 06:20:44 PM PDT 24
Peak memory 218572 kb
Host smart-2656280d-150d-444a-abfb-031f9de71310
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704190603 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag
_prog_failure.1704190603
Directory /workspace/6.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_regwen_during_op.3898383654
Short name T837
Test name
Test status
Simulation time 5548290446 ps
CPU time 16.58 seconds
Started Jun 25 06:20:23 PM PDT 24
Finished Jun 25 06:20:40 PM PDT 24
Peak memory 218052 kb
Host smart-9f21bb5a-fca8-46b2-8852-507ec526f762
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898383654 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_regwen_during_op.3898383654
Directory /workspace/6.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_smoke.1154677389
Short name T709
Test name
Test status
Simulation time 278012083 ps
CPU time 3.9 seconds
Started Jun 25 06:20:18 PM PDT 24
Finished Jun 25 06:20:23 PM PDT 24
Peak memory 217740 kb
Host smart-94f3b485-1c61-40d7-b3d6-329a0383ff34
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154677389 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_smoke.
1154677389
Directory /workspace/6.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_failure.661723102
Short name T291
Test name
Test status
Simulation time 2836377026 ps
CPU time 96.54 seconds
Started Jun 25 06:20:17 PM PDT 24
Finished Jun 25 06:21:55 PM PDT 24
Peak memory 281648 kb
Host smart-ae41adbf-1697-4054-811f-e67031ec3b96
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661723102 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag
_state_failure.661723102
Directory /workspace/6.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_post_trans.1379041428
Short name T412
Test name
Test status
Simulation time 280128483 ps
CPU time 14.59 seconds
Started Jun 25 06:20:16 PM PDT 24
Finished Jun 25 06:20:32 PM PDT 24
Peak memory 251240 kb
Host smart-6deb9bd6-1dc9-485d-8ee1-50ae8cfa5cab
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379041428 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_state_post_trans.1379041428
Directory /workspace/6.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_prog_failure.856603310
Short name T372
Test name
Test status
Simulation time 189909353 ps
CPU time 2.62 seconds
Started Jun 25 06:20:16 PM PDT 24
Finished Jun 25 06:20:20 PM PDT 24
Peak memory 218632 kb
Host smart-ee1b259f-ec86-4d2b-96a8-a3669ebbf618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856603310 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_prog_failure.856603310
Directory /workspace/6.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_regwen_during_op.576960154
Short name T33
Test name
Test status
Simulation time 201770187 ps
CPU time 7.65 seconds
Started Jun 25 06:20:17 PM PDT 24
Finished Jun 25 06:20:26 PM PDT 24
Peak memory 218008 kb
Host smart-787159a6-9bc4-41e5-b584-7610b1dd0a7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576960154 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_regwen_during_op.576960154
Directory /workspace/6.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_mubi.2175236590
Short name T789
Test name
Test status
Simulation time 342681814 ps
CPU time 13.49 seconds
Started Jun 25 06:20:23 PM PDT 24
Finished Jun 25 06:20:37 PM PDT 24
Peak memory 226412 kb
Host smart-b758144a-9843-400a-a370-3dc8ac415ccc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175236590 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_mubi.2175236590
Directory /workspace/6.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_digest.2393828164
Short name T486
Test name
Test status
Simulation time 341229779 ps
CPU time 10.66 seconds
Started Jun 25 06:20:24 PM PDT 24
Finished Jun 25 06:20:35 PM PDT 24
Peak memory 218584 kb
Host smart-f89e106e-a1e3-49a5-81a6-7c67524cc3ac
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393828164 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_di
gest.2393828164
Directory /workspace/6.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_mux.2104280611
Short name T518
Test name
Test status
Simulation time 283902380 ps
CPU time 11.03 seconds
Started Jun 25 06:20:25 PM PDT 24
Finished Jun 25 06:20:36 PM PDT 24
Peak memory 218572 kb
Host smart-9a0967e5-003c-443e-b276-0db493de36a4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104280611 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_mux.2
104280611
Directory /workspace/6.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/6.lc_ctrl_security_escalation.2741663423
Short name T783
Test name
Test status
Simulation time 357254675 ps
CPU time 8.88 seconds
Started Jun 25 06:20:18 PM PDT 24
Finished Jun 25 06:20:28 PM PDT 24
Peak memory 225232 kb
Host smart-c6fb06c9-4673-45a9-b08b-f05b6427c699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741663423 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_security_escalation.2741663423
Directory /workspace/6.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/6.lc_ctrl_smoke.1384541317
Short name T274
Test name
Test status
Simulation time 60289908 ps
CPU time 2.78 seconds
Started Jun 25 06:20:18 PM PDT 24
Finished Jun 25 06:20:22 PM PDT 24
Peak memory 217856 kb
Host smart-50e6bf17-0a0d-49fe-bb89-6e9a4a795a90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384541317 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_smoke.1384541317
Directory /workspace/6.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_failure.4157215404
Short name T287
Test name
Test status
Simulation time 143263984 ps
CPU time 17.39 seconds
Started Jun 25 06:20:16 PM PDT 24
Finished Jun 25 06:20:35 PM PDT 24
Peak memory 251324 kb
Host smart-34626851-4dab-406b-a29b-cd3db344f77f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157215404 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_failure.4157215404
Directory /workspace/6.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_post_trans.1165394366
Short name T361
Test name
Test status
Simulation time 56190657 ps
CPU time 6.61 seconds
Started Jun 25 06:20:17 PM PDT 24
Finished Jun 25 06:20:25 PM PDT 24
Peak memory 246452 kb
Host smart-73242408-7fb6-4873-921d-d59dccb4fa87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165394366 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_post_trans.1165394366
Directory /workspace/6.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all.2113333644
Short name T704
Test name
Test status
Simulation time 27635275090 ps
CPU time 128.69 seconds
Started Jun 25 06:20:25 PM PDT 24
Finished Jun 25 06:22:34 PM PDT 24
Peak memory 283492 kb
Host smart-434d58f7-6981-4607-bb89-e658060d9d24
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113333644 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.lc_ctrl_stress_all.2113333644
Directory /workspace/6.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all_with_rand_reset.811820324
Short name T64
Test name
Test status
Simulation time 122104239988 ps
CPU time 510.08 seconds
Started Jun 25 06:20:25 PM PDT 24
Finished Jun 25 06:28:56 PM PDT 24
Peak memory 422492 kb
Host smart-e05077c0-cc32-48c5-b548-42608507c575
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=811820324 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_stress_all_with_rand_reset.811820324
Directory /workspace/6.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.lc_ctrl_volatile_unlock_smoke.3411691123
Short name T732
Test name
Test status
Simulation time 70210182 ps
CPU time 1.17 seconds
Started Jun 25 06:20:15 PM PDT 24
Finished Jun 25 06:20:18 PM PDT 24
Peak memory 213248 kb
Host smart-c45b0153-8f6d-45a1-96e5-2de0971e9431
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411691123 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ct
rl_volatile_unlock_smoke.3411691123
Directory /workspace/6.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_alert_test.1867480003
Short name T746
Test name
Test status
Simulation time 71092474 ps
CPU time 1.08 seconds
Started Jun 25 06:20:44 PM PDT 24
Finished Jun 25 06:20:46 PM PDT 24
Peak memory 209304 kb
Host smart-441d7d7a-17c5-4492-a701-a2fd45f5cdca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867480003 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_alert_test.1867480003
Directory /workspace/7.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.lc_ctrl_claim_transition_if.807031404
Short name T628
Test name
Test status
Simulation time 11651204 ps
CPU time 0.85 seconds
Started Jun 25 06:20:32 PM PDT 24
Finished Jun 25 06:20:35 PM PDT 24
Peak memory 209192 kb
Host smart-a2db9c7b-1c2e-4cc6-9b33-b709f5dabcff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807031404 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_claim_transition_if.807031404
Directory /workspace/7.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/7.lc_ctrl_errors.97142716
Short name T489
Test name
Test status
Simulation time 4154677086 ps
CPU time 14.26 seconds
Started Jun 25 06:20:35 PM PDT 24
Finished Jun 25 06:20:51 PM PDT 24
Peak memory 226604 kb
Host smart-2c787f37-f602-49ca-9e34-35effb1c703a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97142716 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_errors.97142716
Directory /workspace/7.lc_ctrl_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_access.1136545067
Short name T8
Test name
Test status
Simulation time 260212543 ps
CPU time 3.8 seconds
Started Jun 25 06:20:33 PM PDT 24
Finished Jun 25 06:20:39 PM PDT 24
Peak memory 217452 kb
Host smart-358be404-01fb-4e7c-a5a6-9d7ced2a3415
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136545067 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_access.1136545067
Directory /workspace/7.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_errors.1660536580
Short name T670
Test name
Test status
Simulation time 12313986097 ps
CPU time 77.68 seconds
Started Jun 25 06:20:34 PM PDT 24
Finished Jun 25 06:21:53 PM PDT 24
Peak memory 220124 kb
Host smart-ad4eed86-08ac-4326-93a5-9ab68b0c170b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660536580 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_er
rors.1660536580
Directory /workspace/7.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_priority.3892236925
Short name T228
Test name
Test status
Simulation time 3501616927 ps
CPU time 26.81 seconds
Started Jun 25 06:20:33 PM PDT 24
Finished Jun 25 06:21:01 PM PDT 24
Peak memory 218060 kb
Host smart-e4c81b3e-ab4f-4ff5-bf4f-5092852278c1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892236925 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_priority.3
892236925
Directory /workspace/7.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_prog_failure.4072548097
Short name T460
Test name
Test status
Simulation time 1051586245 ps
CPU time 6.7 seconds
Started Jun 25 06:20:33 PM PDT 24
Finished Jun 25 06:20:41 PM PDT 24
Peak memory 218592 kb
Host smart-c701d51f-52f2-4c27-ac9b-9609aedfccff
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072548097 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag
_prog_failure.4072548097
Directory /workspace/7.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_regwen_during_op.2117412639
Short name T1
Test name
Test status
Simulation time 3922054680 ps
CPU time 27.75 seconds
Started Jun 25 06:20:33 PM PDT 24
Finished Jun 25 06:21:02 PM PDT 24
Peak memory 218028 kb
Host smart-2925374d-774f-4e75-b47c-1a5a562e16f0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117412639 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_regwen_during_op.2117412639
Directory /workspace/7.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_smoke.512174049
Short name T77
Test name
Test status
Simulation time 962108580 ps
CPU time 5 seconds
Started Jun 25 06:20:34 PM PDT 24
Finished Jun 25 06:20:41 PM PDT 24
Peak memory 217988 kb
Host smart-5612cf59-5a86-4bcd-b489-8ddf94888012
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512174049 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_smoke.512174049
Directory /workspace/7.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_failure.4182793787
Short name T614
Test name
Test status
Simulation time 4296911486 ps
CPU time 78.78 seconds
Started Jun 25 06:20:32 PM PDT 24
Finished Jun 25 06:21:52 PM PDT 24
Peak memory 275892 kb
Host smart-a61e16b2-a6c1-42e5-bacb-ad14af38faf2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182793787 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jta
g_state_failure.4182793787
Directory /workspace/7.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_post_trans.1138209675
Short name T259
Test name
Test status
Simulation time 482957568 ps
CPU time 14.12 seconds
Started Jun 25 06:20:32 PM PDT 24
Finished Jun 25 06:20:47 PM PDT 24
Peak memory 250744 kb
Host smart-83900e7d-536d-493c-b1a1-4705d995a42e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138209675 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_state_post_trans.1138209675
Directory /workspace/7.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_prog_failure.1854685835
Short name T307
Test name
Test status
Simulation time 160430075 ps
CPU time 4.25 seconds
Started Jun 25 06:20:33 PM PDT 24
Finished Jun 25 06:20:39 PM PDT 24
Peak memory 223072 kb
Host smart-256ff35f-61b4-41b3-8db1-fdd5fa793d66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854685835 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_prog_failure.1854685835
Directory /workspace/7.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_regwen_during_op.2306728310
Short name T206
Test name
Test status
Simulation time 1241962693 ps
CPU time 21.76 seconds
Started Jun 25 06:20:36 PM PDT 24
Finished Jun 25 06:20:59 PM PDT 24
Peak memory 215408 kb
Host smart-925f4d50-27fb-472e-8274-3393fe1b5e44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306728310 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_regwen_during_op.2306728310
Directory /workspace/7.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_mubi.1026195933
Short name T861
Test name
Test status
Simulation time 652349531 ps
CPU time 17.49 seconds
Started Jun 25 06:20:34 PM PDT 24
Finished Jun 25 06:20:52 PM PDT 24
Peak memory 218964 kb
Host smart-49421cfe-c09a-475e-b128-d1e7d8663167
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026195933 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_mubi.1026195933
Directory /workspace/7.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_digest.3615697910
Short name T446
Test name
Test status
Simulation time 372602926 ps
CPU time 14.52 seconds
Started Jun 25 06:20:35 PM PDT 24
Finished Jun 25 06:20:51 PM PDT 24
Peak memory 218660 kb
Host smart-9d1c0f03-20ac-4a56-ba87-d7e8070dea6d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615697910 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_di
gest.3615697910
Directory /workspace/7.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_mux.1058687275
Short name T801
Test name
Test status
Simulation time 699164656 ps
CPU time 10.75 seconds
Started Jun 25 06:20:35 PM PDT 24
Finished Jun 25 06:20:47 PM PDT 24
Peak memory 218572 kb
Host smart-75d79c89-62fb-4a84-96d9-477d32938c3b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058687275 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_mux.1
058687275
Directory /workspace/7.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/7.lc_ctrl_security_escalation.2731918052
Short name T561
Test name
Test status
Simulation time 1238994362 ps
CPU time 13.22 seconds
Started Jun 25 06:20:32 PM PDT 24
Finished Jun 25 06:20:46 PM PDT 24
Peak memory 226424 kb
Host smart-1d7016ed-9d4b-4f61-ac35-7dfeb484421e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731918052 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_security_escalation.2731918052
Directory /workspace/7.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/7.lc_ctrl_smoke.2237537142
Short name T89
Test name
Test status
Simulation time 29826296 ps
CPU time 1.66 seconds
Started Jun 25 06:20:23 PM PDT 24
Finished Jun 25 06:20:25 PM PDT 24
Peak memory 214284 kb
Host smart-e8c59ef9-5830-494d-bb7f-abda338f83e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237537142 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_smoke.2237537142
Directory /workspace/7.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_failure.1663404727
Short name T665
Test name
Test status
Simulation time 346917715 ps
CPU time 23.64 seconds
Started Jun 25 06:20:32 PM PDT 24
Finished Jun 25 06:20:57 PM PDT 24
Peak memory 246252 kb
Host smart-21d13d61-f8fb-43d9-9752-6e791143cc05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663404727 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_failure.1663404727
Directory /workspace/7.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_post_trans.3283773488
Short name T846
Test name
Test status
Simulation time 355359123 ps
CPU time 7.77 seconds
Started Jun 25 06:20:34 PM PDT 24
Finished Jun 25 06:20:43 PM PDT 24
Peak memory 251312 kb
Host smart-9c58df70-6b26-401a-abee-bba6263171d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283773488 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_post_trans.3283773488
Directory /workspace/7.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_stress_all.420245388
Short name T189
Test name
Test status
Simulation time 3024191141 ps
CPU time 136.03 seconds
Started Jun 25 06:20:43 PM PDT 24
Finished Jun 25 06:23:00 PM PDT 24
Peak memory 267756 kb
Host smart-ddf7bacc-c2f8-499d-842a-3945d7e0df29
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420245388 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.lc_ctrl_stress_all.420245388
Directory /workspace/7.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.lc_ctrl_stress_all_with_rand_reset.1419467775
Short name T580
Test name
Test status
Simulation time 31870187033 ps
CPU time 291.37 seconds
Started Jun 25 06:20:42 PM PDT 24
Finished Jun 25 06:25:35 PM PDT 24
Peak memory 295228 kb
Host smart-d49dcb6b-b8e6-495a-a750-addc3745e459
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1419467775 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_stress_all_with_rand_reset.1419467775
Directory /workspace/7.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.lc_ctrl_alert_test.2343230239
Short name T29
Test name
Test status
Simulation time 47437879 ps
CPU time 0.86 seconds
Started Jun 25 06:20:50 PM PDT 24
Finished Jun 25 06:20:53 PM PDT 24
Peak memory 209208 kb
Host smart-3fccf7ce-f36a-4b52-992c-66724095176d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343230239 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_alert_test.2343230239
Directory /workspace/8.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.lc_ctrl_errors.4069261909
Short name T644
Test name
Test status
Simulation time 217561248 ps
CPU time 8.26 seconds
Started Jun 25 06:20:42 PM PDT 24
Finished Jun 25 06:20:51 PM PDT 24
Peak memory 218632 kb
Host smart-399142d9-3a61-4337-9230-74c457f118be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069261909 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_errors.4069261909
Directory /workspace/8.lc_ctrl_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_access.1587558485
Short name T754
Test name
Test status
Simulation time 779776496 ps
CPU time 9.71 seconds
Started Jun 25 06:20:50 PM PDT 24
Finished Jun 25 06:21:01 PM PDT 24
Peak memory 217440 kb
Host smart-92f547dd-c808-45ee-a6d2-28477c65a4f3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587558485 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_access.1587558485
Directory /workspace/8.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_priority.2488425854
Short name T210
Test name
Test status
Simulation time 510934672 ps
CPU time 3.45 seconds
Started Jun 25 06:20:50 PM PDT 24
Finished Jun 25 06:20:55 PM PDT 24
Peak memory 218092 kb
Host smart-53e16ab8-7584-405e-ac93-970fe0256cb3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488425854 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_priority.2
488425854
Directory /workspace/8.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_prog_failure.3902923834
Short name T233
Test name
Test status
Simulation time 5637232896 ps
CPU time 11.97 seconds
Started Jun 25 06:20:42 PM PDT 24
Finished Jun 25 06:20:55 PM PDT 24
Peak memory 224044 kb
Host smart-b20e6bfa-bdc2-4f0e-915a-18cfbc8637d4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902923834 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag
_prog_failure.3902923834
Directory /workspace/8.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_regwen_during_op.3426466679
Short name T346
Test name
Test status
Simulation time 2466065608 ps
CPU time 34.51 seconds
Started Jun 25 06:20:50 PM PDT 24
Finished Jun 25 06:21:26 PM PDT 24
Peak memory 218012 kb
Host smart-4e076b2e-c515-407d-86f3-d35f0884b5ad
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426466679 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_regwen_during_op.3426466679
Directory /workspace/8.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_smoke.2178826904
Short name T122
Test name
Test status
Simulation time 654966286 ps
CPU time 3.23 seconds
Started Jun 25 06:20:41 PM PDT 24
Finished Jun 25 06:20:46 PM PDT 24
Peak memory 218272 kb
Host smart-acaabdde-cf13-4631-a585-c5132574fd55
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178826904 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_smoke.
2178826904
Directory /workspace/8.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_failure.2092977950
Short name T759
Test name
Test status
Simulation time 4194400925 ps
CPU time 38.56 seconds
Started Jun 25 06:20:43 PM PDT 24
Finished Jun 25 06:21:23 PM PDT 24
Peak memory 276968 kb
Host smart-050a3419-7c1f-4016-ae5e-9f5d332427e3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092977950 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jta
g_state_failure.2092977950
Directory /workspace/8.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_post_trans.2707662890
Short name T330
Test name
Test status
Simulation time 647973730 ps
CPU time 14.96 seconds
Started Jun 25 06:20:42 PM PDT 24
Finished Jun 25 06:20:58 PM PDT 24
Peak memory 251248 kb
Host smart-83516288-b652-46e2-bcdc-f381c3834f0d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707662890 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_state_post_trans.2707662890
Directory /workspace/8.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_prog_failure.1482968711
Short name T557
Test name
Test status
Simulation time 104333236 ps
CPU time 2.2 seconds
Started Jun 25 06:20:42 PM PDT 24
Finished Jun 25 06:20:45 PM PDT 24
Peak memory 218612 kb
Host smart-3073bb43-b8a1-41e3-993b-984821891e84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482968711 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_prog_failure.1482968711
Directory /workspace/8.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_regwen_during_op.2711020081
Short name T411
Test name
Test status
Simulation time 273458686 ps
CPU time 17.78 seconds
Started Jun 25 06:20:41 PM PDT 24
Finished Jun 25 06:21:00 PM PDT 24
Peak memory 215140 kb
Host smart-27f506d5-5bd3-4b4a-b9ca-967f47e59528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711020081 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_regwen_during_op.2711020081
Directory /workspace/8.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_mubi.3321856445
Short name T410
Test name
Test status
Simulation time 1616078130 ps
CPU time 18.15 seconds
Started Jun 25 06:20:50 PM PDT 24
Finished Jun 25 06:21:09 PM PDT 24
Peak memory 226420 kb
Host smart-7e2c3430-6be3-46c5-b49e-fad13a65e9a3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321856445 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_mubi.3321856445
Directory /workspace/8.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_digest.1311130518
Short name T244
Test name
Test status
Simulation time 383016962 ps
CPU time 12.83 seconds
Started Jun 25 06:20:51 PM PDT 24
Finished Jun 25 06:21:05 PM PDT 24
Peak memory 218580 kb
Host smart-f1ebbeb6-bfbf-4cf3-a027-57b3e11c2197
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311130518 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_di
gest.1311130518
Directory /workspace/8.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_mux.4199877827
Short name T832
Test name
Test status
Simulation time 280914562 ps
CPU time 8.19 seconds
Started Jun 25 06:20:49 PM PDT 24
Finished Jun 25 06:20:58 PM PDT 24
Peak memory 226380 kb
Host smart-17c686fa-8f21-4544-b8ae-2d8ae5b0db8b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199877827 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_mux.4
199877827
Directory /workspace/8.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/8.lc_ctrl_security_escalation.1665568743
Short name T584
Test name
Test status
Simulation time 280707406 ps
CPU time 10.86 seconds
Started Jun 25 06:20:43 PM PDT 24
Finished Jun 25 06:20:55 PM PDT 24
Peak memory 225804 kb
Host smart-36d3ce88-ea11-49a8-b47c-7dd45a67f5aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665568743 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_security_escalation.1665568743
Directory /workspace/8.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/8.lc_ctrl_smoke.4249231476
Short name T340
Test name
Test status
Simulation time 215294517 ps
CPU time 6.85 seconds
Started Jun 25 06:20:43 PM PDT 24
Finished Jun 25 06:20:51 PM PDT 24
Peak memory 218076 kb
Host smart-8484a418-7ec3-4b58-8de1-6dc0c8e3cb99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249231476 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_smoke.4249231476
Directory /workspace/8.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_failure.189098208
Short name T569
Test name
Test status
Simulation time 521987822 ps
CPU time 22.27 seconds
Started Jun 25 06:20:42 PM PDT 24
Finished Jun 25 06:21:06 PM PDT 24
Peak memory 251328 kb
Host smart-671c2233-9382-4513-8777-72384a54186a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189098208 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_failure.189098208
Directory /workspace/8.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_post_trans.3647039978
Short name T371
Test name
Test status
Simulation time 183981868 ps
CPU time 6.71 seconds
Started Jun 25 06:20:43 PM PDT 24
Finished Jun 25 06:20:51 PM PDT 24
Peak memory 251336 kb
Host smart-83ec43fb-6029-4fac-a1be-7ae3f368f253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647039978 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_post_trans.3647039978
Directory /workspace/8.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all.868280563
Short name T282
Test name
Test status
Simulation time 1035527322 ps
CPU time 20.87 seconds
Started Jun 25 06:20:53 PM PDT 24
Finished Jun 25 06:21:14 PM PDT 24
Peak memory 251372 kb
Host smart-19ff190d-a9b8-48e3-8013-11f3c7ff3443
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868280563 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.lc_ctrl_stress_all.868280563
Directory /workspace/8.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all_with_rand_reset.644782471
Short name T721
Test name
Test status
Simulation time 153668763421 ps
CPU time 350.39 seconds
Started Jun 25 06:20:54 PM PDT 24
Finished Jun 25 06:26:45 PM PDT 24
Peak memory 275388 kb
Host smart-a40b532b-6534-4c4a-8eb3-c7280bb561fb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=644782471 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_stress_all_with_rand_reset.644782471
Directory /workspace/8.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.lc_ctrl_volatile_unlock_smoke.1810748023
Short name T246
Test name
Test status
Simulation time 15000784 ps
CPU time 0.99 seconds
Started Jun 25 06:20:40 PM PDT 24
Finished Jun 25 06:20:42 PM PDT 24
Peak memory 209356 kb
Host smart-7810db15-0c21-4d14-94af-da7fd228ec65
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810748023 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ct
rl_volatile_unlock_smoke.1810748023
Directory /workspace/8.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_alert_test.1681864061
Short name T295
Test name
Test status
Simulation time 11103842 ps
CPU time 0.86 seconds
Started Jun 25 06:20:58 PM PDT 24
Finished Jun 25 06:21:00 PM PDT 24
Peak memory 209204 kb
Host smart-22b40ac2-aff6-4b84-be9f-94e23a94bb36
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681864061 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_alert_test.1681864061
Directory /workspace/9.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.lc_ctrl_claim_transition_if.3069278222
Short name T502
Test name
Test status
Simulation time 30106410 ps
CPU time 0.92 seconds
Started Jun 25 06:20:51 PM PDT 24
Finished Jun 25 06:20:53 PM PDT 24
Peak memory 209360 kb
Host smart-f9ef8c49-f494-4e3d-a92d-9887f8d3474a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069278222 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_claim_transition_if.3069278222
Directory /workspace/9.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/9.lc_ctrl_errors.1130070380
Short name T253
Test name
Test status
Simulation time 1709455311 ps
CPU time 14.24 seconds
Started Jun 25 06:20:56 PM PDT 24
Finished Jun 25 06:21:11 PM PDT 24
Peak memory 226448 kb
Host smart-1a21fdbc-0329-430c-9c8b-e450cfbc4f0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130070380 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_errors.1130070380
Directory /workspace/9.lc_ctrl_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_access.3962830835
Short name T756
Test name
Test status
Simulation time 4146551661 ps
CPU time 22.72 seconds
Started Jun 25 06:20:56 PM PDT 24
Finished Jun 25 06:21:20 PM PDT 24
Peak memory 218128 kb
Host smart-038940a2-015b-4840-9c7d-8b1a95cf5a71
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962830835 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_access.3962830835
Directory /workspace/9.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_errors.1397973482
Short name T751
Test name
Test status
Simulation time 1401985795 ps
CPU time 24.47 seconds
Started Jun 25 06:20:57 PM PDT 24
Finished Jun 25 06:21:23 PM PDT 24
Peak memory 226280 kb
Host smart-e838b01b-02eb-4b23-9faf-01c3f4a721c3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397973482 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_er
rors.1397973482
Directory /workspace/9.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_priority.3576447648
Short name T533
Test name
Test status
Simulation time 154605356 ps
CPU time 2.77 seconds
Started Jun 25 06:20:58 PM PDT 24
Finished Jun 25 06:21:02 PM PDT 24
Peak memory 218108 kb
Host smart-d74d8e95-8a4b-41e1-b672-00b168f4cb75
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576447648 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_priority.3
576447648
Directory /workspace/9.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_prog_failure.2650614115
Short name T490
Test name
Test status
Simulation time 203904540 ps
CPU time 2.41 seconds
Started Jun 25 06:20:59 PM PDT 24
Finished Jun 25 06:21:02 PM PDT 24
Peak memory 218492 kb
Host smart-17c918d9-f341-48f9-bc5f-01ffd185c0f5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650614115 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag
_prog_failure.2650614115
Directory /workspace/9.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_regwen_during_op.927589647
Short name T73
Test name
Test status
Simulation time 954590633 ps
CPU time 15.02 seconds
Started Jun 25 06:20:58 PM PDT 24
Finished Jun 25 06:21:14 PM PDT 24
Peak memory 217980 kb
Host smart-66010b0d-eaa9-4a00-9710-68cd7c5b7e6d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927589647 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_j
tag_regwen_during_op.927589647
Directory /workspace/9.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_smoke.3517673808
Short name T549
Test name
Test status
Simulation time 926631728 ps
CPU time 5.21 seconds
Started Jun 25 06:20:51 PM PDT 24
Finished Jun 25 06:20:57 PM PDT 24
Peak memory 217972 kb
Host smart-034a0706-b5ad-4fc9-aec0-add7245f2c82
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517673808 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_smoke.
3517673808
Directory /workspace/9.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_failure.1778964793
Short name T735
Test name
Test status
Simulation time 1388703944 ps
CPU time 50 seconds
Started Jun 25 06:20:57 PM PDT 24
Finished Jun 25 06:21:47 PM PDT 24
Peak memory 252104 kb
Host smart-0f821864-0e3a-46ec-8ecc-2034f3d9ab5f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778964793 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jta
g_state_failure.1778964793
Directory /workspace/9.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_post_trans.2250013329
Short name T444
Test name
Test status
Simulation time 1864952959 ps
CPU time 19.51 seconds
Started Jun 25 06:20:57 PM PDT 24
Finished Jun 25 06:21:17 PM PDT 24
Peak memory 251256 kb
Host smart-a125e440-259d-479c-a35b-7f53d6761241
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250013329 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_state_post_trans.2250013329
Directory /workspace/9.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_prog_failure.564084726
Short name T524
Test name
Test status
Simulation time 205562889 ps
CPU time 2.56 seconds
Started Jun 25 06:20:51 PM PDT 24
Finished Jun 25 06:20:55 PM PDT 24
Peak memory 222704 kb
Host smart-da29f25f-c6f3-43e3-9837-eba7960aa5b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564084726 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_prog_failure.564084726
Directory /workspace/9.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_regwen_during_op.1719000685
Short name T509
Test name
Test status
Simulation time 1323954136 ps
CPU time 6.01 seconds
Started Jun 25 06:20:55 PM PDT 24
Finished Jun 25 06:21:02 PM PDT 24
Peak memory 218060 kb
Host smart-f90113d9-3a58-440f-9f07-5f67f5efa158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719000685 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_regwen_during_op.1719000685
Directory /workspace/9.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_mubi.1059100002
Short name T566
Test name
Test status
Simulation time 1731768276 ps
CPU time 16.34 seconds
Started Jun 25 06:20:59 PM PDT 24
Finished Jun 25 06:21:16 PM PDT 24
Peak memory 226364 kb
Host smart-3b1bf609-52a7-4fba-985d-d2c7590be4a9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059100002 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_mubi.1059100002
Directory /workspace/9.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_digest.3455109916
Short name T414
Test name
Test status
Simulation time 1796903385 ps
CPU time 10.58 seconds
Started Jun 25 06:20:55 PM PDT 24
Finished Jun 25 06:21:07 PM PDT 24
Peak memory 218604 kb
Host smart-bc99395c-ff28-4b42-9323-b43b16bee452
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455109916 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_di
gest.3455109916
Directory /workspace/9.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_mux.1001335269
Short name T809
Test name
Test status
Simulation time 1038130060 ps
CPU time 10.31 seconds
Started Jun 25 06:20:56 PM PDT 24
Finished Jun 25 06:21:07 PM PDT 24
Peak memory 218560 kb
Host smart-94d6806b-377e-4a24-bd59-cf4b46f03c29
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001335269 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_mux.1
001335269
Directory /workspace/9.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/9.lc_ctrl_security_escalation.2573677617
Short name T125
Test name
Test status
Simulation time 269059489 ps
CPU time 11 seconds
Started Jun 25 06:20:55 PM PDT 24
Finished Jun 25 06:21:07 PM PDT 24
Peak memory 218700 kb
Host smart-ce7c9a4c-2682-4a7d-925c-972be685858b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573677617 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_security_escalation.2573677617
Directory /workspace/9.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/9.lc_ctrl_smoke.2349388128
Short name T92
Test name
Test status
Simulation time 236001672 ps
CPU time 13.91 seconds
Started Jun 25 06:20:51 PM PDT 24
Finished Jun 25 06:21:06 PM PDT 24
Peak memory 218084 kb
Host smart-2cdbee4b-b156-43cf-9297-1da8618f319b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349388128 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_smoke.2349388128
Directory /workspace/9.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_failure.3638040626
Short name T555
Test name
Test status
Simulation time 1089216397 ps
CPU time 24.17 seconds
Started Jun 25 06:20:50 PM PDT 24
Finished Jun 25 06:21:15 PM PDT 24
Peak memory 245372 kb
Host smart-ceca9336-d7a3-4092-a5e9-8865c6b47442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638040626 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_failure.3638040626
Directory /workspace/9.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_post_trans.1611330039
Short name T283
Test name
Test status
Simulation time 201797666 ps
CPU time 3.46 seconds
Started Jun 25 06:20:52 PM PDT 24
Finished Jun 25 06:20:56 PM PDT 24
Peak memory 226816 kb
Host smart-b97f85be-8e5e-4bda-805f-455196dc3b1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611330039 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_post_trans.1611330039
Directory /workspace/9.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_stress_all.145397655
Short name T548
Test name
Test status
Simulation time 15738613082 ps
CPU time 117.48 seconds
Started Jun 25 06:20:57 PM PDT 24
Finished Jun 25 06:22:55 PM PDT 24
Peak memory 422276 kb
Host smart-df5e5d32-9728-4e0c-8ffe-4ab2020b887d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145397655 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.lc_ctrl_stress_all.145397655
Directory /workspace/9.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.lc_ctrl_stress_all_with_rand_reset.4085307629
Short name T179
Test name
Test status
Simulation time 50507436227 ps
CPU time 1346.45 seconds
Started Jun 25 06:20:56 PM PDT 24
Finished Jun 25 06:43:23 PM PDT 24
Peak memory 296340 kb
Host smart-d6ab87f4-2cf8-47bf-acc3-955216692d09
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4085307629 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_stress_all_with_rand_reset.4085307629
Directory /workspace/9.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.lc_ctrl_volatile_unlock_smoke.3475023087
Short name T611
Test name
Test status
Simulation time 10991903 ps
CPU time 0.78 seconds
Started Jun 25 06:20:51 PM PDT 24
Finished Jun 25 06:20:53 PM PDT 24
Peak memory 209196 kb
Host smart-6b74eb71-0d24-4067-a546-a62dbcf56c59
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475023087 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ct
rl_volatile_unlock_smoke.3475023087
Directory /workspace/9.lc_ctrl_volatile_unlock_smoke/latest
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