Summary for Variable clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52900 |
1 |
|
|
T1 |
61 |
|
T2 |
14 |
|
T3 |
86 |
auto[1] |
1895 |
1 |
|
|
T12 |
9 |
|
T14 |
14 |
|
T15 |
23 |
Summary for Variable clk_byp_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54092 |
1 |
|
|
T1 |
61 |
|
T2 |
14 |
|
T3 |
86 |
auto[1] |
703 |
1 |
|
|
T13 |
19 |
|
T60 |
14 |
|
T35 |
17 |
Summary for Variable count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52795 |
1 |
|
|
T1 |
56 |
|
T2 |
14 |
|
T3 |
86 |
auto[1] |
2000 |
1 |
|
|
T1 |
5 |
|
T8 |
11 |
|
T10 |
6 |
Summary for Variable count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52797 |
1 |
|
|
T1 |
53 |
|
T2 |
13 |
|
T3 |
86 |
auto[1] |
1998 |
1 |
|
|
T1 |
8 |
|
T2 |
1 |
|
T8 |
19 |
Summary for Variable count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52763 |
1 |
|
|
T1 |
57 |
|
T2 |
13 |
|
T3 |
86 |
auto[1] |
2032 |
1 |
|
|
T1 |
4 |
|
T2 |
1 |
|
T8 |
13 |
Summary for Variable err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for err_inj_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
err_inj |
50213 |
1 |
|
|
T1 |
61 |
|
T2 |
6 |
|
T3 |
86 |
no_err_inj |
4582 |
1 |
|
|
T2 |
8 |
|
T7 |
22 |
|
T11 |
17 |
Summary for Variable flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52952 |
1 |
|
|
T1 |
61 |
|
T2 |
14 |
|
T3 |
86 |
auto[1] |
1843 |
1 |
|
|
T12 |
9 |
|
T14 |
12 |
|
T15 |
25 |
Summary for Variable flash_rma_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54052 |
1 |
|
|
T1 |
61 |
|
T2 |
14 |
|
T3 |
86 |
auto[1] |
743 |
1 |
|
|
T13 |
8 |
|
T60 |
7 |
|
T35 |
17 |
Summary for Variable jtag_csr_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for jtag_csr_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
38566 |
1 |
|
|
T3 |
86 |
|
T8 |
97 |
|
T9 |
1 |
auto[1] |
16229 |
1 |
|
|
T1 |
61 |
|
T2 |
14 |
|
T7 |
8 |
Summary for Variable kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for kmac_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52846 |
1 |
|
|
T1 |
53 |
|
T2 |
14 |
|
T3 |
86 |
auto[1] |
1949 |
1 |
|
|
T1 |
8 |
|
T8 |
8 |
|
T10 |
12 |
Summary for Variable lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for lc_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52846 |
1 |
|
|
T1 |
55 |
|
T2 |
14 |
|
T3 |
86 |
auto[1] |
1949 |
1 |
|
|
T1 |
6 |
|
T8 |
10 |
|
T10 |
8 |
Summary for Variable otp_lc_data_i_valid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_lc_data_i_valid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52811 |
1 |
|
|
T1 |
58 |
|
T2 |
13 |
|
T3 |
86 |
auto[1] |
1984 |
1 |
|
|
T1 |
3 |
|
T2 |
1 |
|
T8 |
6 |
Summary for Variable otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_partition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52933 |
1 |
|
|
T1 |
61 |
|
T2 |
14 |
|
T3 |
86 |
auto[1] |
1862 |
1 |
|
|
T12 |
3 |
|
T14 |
15 |
|
T15 |
22 |
Summary for Variable otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_prog_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52494 |
1 |
|
|
T1 |
61 |
|
T2 |
14 |
|
T3 |
86 |
auto[1] |
2301 |
1 |
|
|
T9 |
1 |
|
T7 |
10 |
|
T57 |
3 |
Summary for Variable otp_rma_token_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_rma_token_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54054 |
1 |
|
|
T1 |
61 |
|
T2 |
14 |
|
T3 |
86 |
auto[1] |
741 |
1 |
|
|
T13 |
14 |
|
T60 |
19 |
|
T35 |
9 |
Summary for Variable otp_secrets_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_secrets_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54055 |
1 |
|
|
T1 |
61 |
|
T2 |
14 |
|
T3 |
86 |
auto[1] |
740 |
1 |
|
|
T13 |
17 |
|
T60 |
12 |
|
T35 |
14 |
Summary for Variable otp_test_tokens_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_test_tokens_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54090 |
1 |
|
|
T1 |
61 |
|
T2 |
14 |
|
T3 |
86 |
auto[1] |
705 |
1 |
|
|
T13 |
13 |
|
T60 |
11 |
|
T35 |
22 |
Summary for Variable post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for post_trans_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52246 |
1 |
|
|
T1 |
61 |
|
T3 |
86 |
|
T8 |
97 |
auto[1] |
2549 |
1 |
|
|
T2 |
14 |
|
T14 |
10 |
|
T16 |
15 |
Summary for Variable security_escalation_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for security_escalation_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50877 |
1 |
|
|
T1 |
61 |
|
T2 |
14 |
|
T8 |
97 |
auto[1] |
3918 |
1 |
|
|
T3 |
86 |
|
T33 |
81 |
|
T45 |
92 |
Summary for Variable state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52842 |
1 |
|
|
T1 |
50 |
|
T2 |
14 |
|
T3 |
86 |
auto[1] |
1953 |
1 |
|
|
T1 |
11 |
|
T8 |
11 |
|
T10 |
9 |
Summary for Variable state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52851 |
1 |
|
|
T1 |
52 |
|
T2 |
13 |
|
T3 |
86 |
auto[1] |
1944 |
1 |
|
|
T1 |
9 |
|
T2 |
1 |
|
T8 |
7 |
Summary for Variable state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52767 |
1 |
|
|
T1 |
54 |
|
T2 |
12 |
|
T3 |
86 |
auto[1] |
2028 |
1 |
|
|
T1 |
7 |
|
T2 |
2 |
|
T8 |
12 |
Summary for Variable token_invalid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_invalid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52904 |
1 |
|
|
T1 |
61 |
|
T2 |
14 |
|
T3 |
86 |
auto[1] |
1891 |
1 |
|
|
T12 |
7 |
|
T14 |
11 |
|
T15 |
21 |
Summary for Variable token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mismatch_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49315 |
1 |
|
|
T1 |
61 |
|
T2 |
14 |
|
T3 |
86 |
auto[1] |
5480 |
1 |
|
|
T12 |
5 |
|
T26 |
74 |
|
T14 |
11 |
Summary for Variable token_mux_ctrl_redun_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mux_ctrl_redun_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50965 |
1 |
|
|
T1 |
61 |
|
T2 |
14 |
|
T3 |
86 |
auto[1] |
3830 |
1 |
|
|
T37 |
93 |
|
T58 |
52 |
|
T59 |
50 |
Summary for Variable token_mux_digest_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for token_mux_digest_err_cp
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54795 |
1 |
|
|
T1 |
61 |
|
T2 |
14 |
|
T3 |
86 |
Summary for Variable token_response_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_response_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52910 |
1 |
|
|
T1 |
61 |
|
T2 |
14 |
|
T3 |
86 |
auto[1] |
1885 |
1 |
|
|
T12 |
5 |
|
T14 |
14 |
|
T15 |
20 |
Summary for Variable transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52869 |
1 |
|
|
T1 |
61 |
|
T2 |
14 |
|
T3 |
86 |
auto[1] |
1926 |
1 |
|
|
T12 |
5 |
|
T14 |
9 |
|
T15 |
19 |
Summary for Variable transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52882 |
1 |
|
|
T1 |
61 |
|
T2 |
14 |
|
T3 |
86 |
auto[1] |
1913 |
1 |
|
|
T12 |
8 |
|
T14 |
11 |
|
T15 |
20 |
Summary for Cross post_trans_err_inj_xp
Samples crossed: post_trans_err_cp err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_err_inj_xp
Bins
post_trans_err_cp | err_inj_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
err_inj |
48954 |
1 |
|
|
T1 |
61 |
|
T3 |
86 |
|
T8 |
97 |
auto[0] |
no_err_inj |
3292 |
1 |
|
|
T7 |
22 |
|
T11 |
17 |
|
T27 |
7 |
auto[1] |
err_inj |
1259 |
1 |
|
|
T2 |
6 |
|
T14 |
4 |
|
T16 |
9 |
auto[1] |
no_err_inj |
1290 |
1 |
|
|
T2 |
8 |
|
T14 |
6 |
|
T16 |
6 |
Summary for Cross post_trans_state_err_xp
Samples crossed: post_trans_err_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_err_xp
Bins
post_trans_err_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
50463 |
1 |
|
|
T1 |
52 |
|
T3 |
86 |
|
T8 |
90 |
auto[0] |
auto[1] |
1783 |
1 |
|
|
T1 |
9 |
|
T8 |
7 |
|
T10 |
14 |
auto[1] |
auto[0] |
2388 |
1 |
|
|
T2 |
13 |
|
T14 |
8 |
|
T16 |
14 |
auto[1] |
auto[1] |
161 |
1 |
|
|
T2 |
1 |
|
T14 |
2 |
|
T16 |
1 |
Summary for Cross post_trans_lc_fsm_backdoor_err_xp
Samples crossed: post_trans_err_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_lc_fsm_backdoor_err_xp
Bins
post_trans_err_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
50427 |
1 |
|
|
T1 |
55 |
|
T3 |
86 |
|
T8 |
87 |
auto[0] |
auto[1] |
1819 |
1 |
|
|
T1 |
6 |
|
T8 |
10 |
|
T10 |
8 |
auto[1] |
auto[0] |
2419 |
1 |
|
|
T2 |
14 |
|
T14 |
9 |
|
T16 |
15 |
auto[1] |
auto[1] |
130 |
1 |
|
|
T14 |
1 |
|
T34 |
3 |
|
T206 |
1 |
Summary for Cross post_trans_state_illegal_err_xp
Samples crossed: post_trans_err_cp state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_illegal_err_xp
Bins
post_trans_err_cp | state_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
50381 |
1 |
|
|
T1 |
54 |
|
T3 |
86 |
|
T8 |
85 |
auto[0] |
auto[1] |
1865 |
1 |
|
|
T1 |
7 |
|
T8 |
12 |
|
T10 |
11 |
auto[1] |
auto[0] |
2386 |
1 |
|
|
T2 |
12 |
|
T14 |
10 |
|
T16 |
13 |
auto[1] |
auto[1] |
163 |
1 |
|
|
T2 |
2 |
|
T16 |
2 |
|
T32 |
1 |
Summary for Cross post_trans_count_err_xp
Samples crossed: post_trans_err_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_err_xp
Bins
post_trans_err_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
50385 |
1 |
|
|
T1 |
53 |
|
T3 |
86 |
|
T8 |
78 |
auto[0] |
auto[1] |
1861 |
1 |
|
|
T1 |
8 |
|
T8 |
19 |
|
T10 |
11 |
auto[1] |
auto[0] |
2412 |
1 |
|
|
T2 |
13 |
|
T14 |
10 |
|
T16 |
14 |
auto[1] |
auto[1] |
137 |
1 |
|
|
T2 |
1 |
|
T16 |
1 |
|
T34 |
2 |
Summary for Cross post_trans_count_illegal_err_xp
Samples crossed: post_trans_err_cp count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_illegal_err_xp
Bins
post_trans_err_cp | count_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
50351 |
1 |
|
|
T1 |
57 |
|
T3 |
86 |
|
T8 |
84 |
auto[0] |
auto[1] |
1895 |
1 |
|
|
T1 |
4 |
|
T8 |
13 |
|
T10 |
6 |
auto[1] |
auto[0] |
2412 |
1 |
|
|
T2 |
13 |
|
T14 |
10 |
|
T16 |
14 |
auto[1] |
auto[1] |
137 |
1 |
|
|
T2 |
1 |
|
T16 |
1 |
|
T32 |
1 |
Summary for Cross post_trans_count_backdoor_err_xp
Samples crossed: post_trans_err_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_backdoor_err_xp
Bins
post_trans_err_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
50386 |
1 |
|
|
T1 |
56 |
|
T3 |
86 |
|
T8 |
86 |
auto[0] |
auto[1] |
1860 |
1 |
|
|
T1 |
5 |
|
T8 |
11 |
|
T10 |
6 |
auto[1] |
auto[0] |
2409 |
1 |
|
|
T2 |
14 |
|
T14 |
10 |
|
T16 |
14 |
auto[1] |
auto[1] |
140 |
1 |
|
|
T16 |
1 |
|
T34 |
3 |
|
T36 |
2 |
Summary for Cross jtag_clk_byp_error_rsp_xp
Samples crossed: jtag_csr_cp clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_clk_byp_error_rsp_xp
Bins
jtag_csr_cp | clk_byp_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37496 |
1 |
|
|
T3 |
86 |
|
T8 |
97 |
|
T9 |
1 |
auto[0] |
auto[1] |
1070 |
1 |
|
|
T12 |
9 |
|
T15 |
10 |
|
T207 |
13 |
auto[1] |
auto[0] |
15404 |
1 |
|
|
T1 |
61 |
|
T2 |
14 |
|
T7 |
8 |
auto[1] |
auto[1] |
825 |
1 |
|
|
T14 |
14 |
|
T15 |
13 |
|
T16 |
16 |
Summary for Cross jtag_flash_rma_error_rsp_xp
Samples crossed: jtag_csr_cp flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_flash_rma_error_rsp_xp
Bins
jtag_csr_cp | flash_rma_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37559 |
1 |
|
|
T3 |
86 |
|
T8 |
97 |
|
T9 |
1 |
auto[0] |
auto[1] |
1007 |
1 |
|
|
T12 |
9 |
|
T15 |
11 |
|
T207 |
10 |
auto[1] |
auto[0] |
15393 |
1 |
|
|
T1 |
61 |
|
T2 |
14 |
|
T7 |
8 |
auto[1] |
auto[1] |
836 |
1 |
|
|
T14 |
12 |
|
T15 |
14 |
|
T16 |
11 |
Summary for Cross jtag_otp_prog_err_xp
Samples crossed: jtag_csr_cp otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_prog_err_xp
Bins
jtag_csr_cp | otp_prog_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37183 |
1 |
|
|
T3 |
86 |
|
T8 |
97 |
|
T7 |
14 |
auto[0] |
auto[1] |
1383 |
1 |
|
|
T9 |
1 |
|
T7 |
10 |
|
T57 |
3 |
auto[1] |
auto[0] |
15311 |
1 |
|
|
T1 |
61 |
|
T2 |
14 |
|
T7 |
8 |
auto[1] |
auto[1] |
918 |
1 |
|
|
T34 |
16 |
|
T36 |
20 |
|
T208 |
8 |
Summary for Cross jtag_otp_partition_err_xp
Samples crossed: jtag_csr_cp otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_partition_err_xp
Bins
jtag_csr_cp | otp_partition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37533 |
1 |
|
|
T3 |
86 |
|
T8 |
97 |
|
T9 |
1 |
auto[0] |
auto[1] |
1033 |
1 |
|
|
T12 |
3 |
|
T15 |
8 |
|
T207 |
6 |
auto[1] |
auto[0] |
15400 |
1 |
|
|
T1 |
61 |
|
T2 |
14 |
|
T7 |
8 |
auto[1] |
auto[1] |
829 |
1 |
|
|
T14 |
15 |
|
T15 |
14 |
|
T16 |
5 |
Summary for Cross jtag_token_mismatch_err_xp
Samples crossed: jtag_csr_cp token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_token_mismatch_err_xp
Bins
jtag_csr_cp | token_mismatch_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
33963 |
1 |
|
|
T3 |
86 |
|
T8 |
97 |
|
T9 |
1 |
auto[0] |
auto[1] |
4603 |
1 |
|
|
T12 |
5 |
|
T26 |
74 |
|
T15 |
8 |
auto[1] |
auto[0] |
15352 |
1 |
|
|
T1 |
61 |
|
T2 |
14 |
|
T7 |
8 |
auto[1] |
auto[1] |
877 |
1 |
|
|
T14 |
11 |
|
T15 |
13 |
|
T16 |
11 |
Summary for Cross jtag_state_err_xp
Samples crossed: jtag_csr_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_err_xp
Bins
jtag_csr_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37348 |
1 |
|
|
T3 |
86 |
|
T8 |
90 |
|
T9 |
1 |
auto[0] |
auto[1] |
1218 |
1 |
|
|
T8 |
7 |
|
T10 |
14 |
|
T14 |
21 |
auto[1] |
auto[0] |
15503 |
1 |
|
|
T1 |
52 |
|
T2 |
13 |
|
T7 |
8 |
auto[1] |
auto[1] |
726 |
1 |
|
|
T1 |
9 |
|
T2 |
1 |
|
T15 |
8 |
Summary for Cross jtag_state_backdoor_err_xp
Samples crossed: jtag_csr_cp state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_backdoor_err_xp
Bins
jtag_csr_cp | state_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37373 |
1 |
|
|
T3 |
86 |
|
T8 |
86 |
|
T9 |
1 |
auto[0] |
auto[1] |
1193 |
1 |
|
|
T8 |
11 |
|
T10 |
9 |
|
T14 |
22 |
auto[1] |
auto[0] |
15469 |
1 |
|
|
T1 |
50 |
|
T2 |
14 |
|
T7 |
8 |
auto[1] |
auto[1] |
760 |
1 |
|
|
T1 |
11 |
|
T15 |
8 |
|
T16 |
13 |
Summary for Cross jtag_lc_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_lc_fsm_backdoor_err_xp
Bins
jtag_csr_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37344 |
1 |
|
|
T3 |
86 |
|
T8 |
87 |
|
T9 |
1 |
auto[0] |
auto[1] |
1222 |
1 |
|
|
T8 |
10 |
|
T10 |
8 |
|
T14 |
16 |
auto[1] |
auto[0] |
15502 |
1 |
|
|
T1 |
55 |
|
T2 |
14 |
|
T7 |
8 |
auto[1] |
auto[1] |
727 |
1 |
|
|
T1 |
6 |
|
T15 |
3 |
|
T16 |
11 |
Summary for Cross jtag_kmac_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_kmac_fsm_backdoor_err_xp
Bins
jtag_csr_cp | kmac_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37377 |
1 |
|
|
T3 |
86 |
|
T8 |
89 |
|
T9 |
1 |
auto[0] |
auto[1] |
1189 |
1 |
|
|
T8 |
8 |
|
T10 |
12 |
|
T14 |
19 |
auto[1] |
auto[0] |
15469 |
1 |
|
|
T1 |
53 |
|
T2 |
14 |
|
T7 |
8 |
auto[1] |
auto[1] |
760 |
1 |
|
|
T1 |
8 |
|
T15 |
7 |
|
T16 |
12 |
Summary for Cross jtag_count_err_xp
Samples crossed: jtag_csr_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_err_xp
Bins
jtag_csr_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37279 |
1 |
|
|
T3 |
86 |
|
T8 |
78 |
|
T9 |
1 |
auto[0] |
auto[1] |
1287 |
1 |
|
|
T8 |
19 |
|
T10 |
11 |
|
T14 |
17 |
auto[1] |
auto[0] |
15518 |
1 |
|
|
T1 |
53 |
|
T2 |
13 |
|
T7 |
8 |
auto[1] |
auto[1] |
711 |
1 |
|
|
T1 |
8 |
|
T2 |
1 |
|
T15 |
12 |
Summary for Cross jtag_count_backdoor_err_xp
Samples crossed: jtag_csr_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_backdoor_err_xp
Bins
jtag_csr_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37293 |
1 |
|
|
T3 |
86 |
|
T8 |
86 |
|
T9 |
1 |
auto[0] |
auto[1] |
1273 |
1 |
|
|
T8 |
11 |
|
T10 |
6 |
|
T14 |
19 |
auto[1] |
auto[0] |
15502 |
1 |
|
|
T1 |
56 |
|
T2 |
14 |
|
T7 |
8 |
auto[1] |
auto[1] |
727 |
1 |
|
|
T1 |
5 |
|
T15 |
8 |
|
T16 |
9 |
Summary for Cross jtag_transition_err_xp
Samples crossed: jtag_csr_cp transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_err_xp
Bins
jtag_csr_cp | transition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37502 |
1 |
|
|
T3 |
86 |
|
T8 |
97 |
|
T9 |
1 |
auto[0] |
auto[1] |
1064 |
1 |
|
|
T12 |
8 |
|
T15 |
7 |
|
T207 |
9 |
auto[1] |
auto[0] |
15380 |
1 |
|
|
T1 |
61 |
|
T2 |
14 |
|
T7 |
8 |
auto[1] |
auto[1] |
849 |
1 |
|
|
T14 |
11 |
|
T15 |
13 |
|
T16 |
13 |
Summary for Cross jtag_transition_count_err_xp
Samples crossed: jtag_csr_cp transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_count_err_xp
Bins
jtag_csr_cp | transition_count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37491 |
1 |
|
|
T3 |
86 |
|
T8 |
97 |
|
T9 |
1 |
auto[0] |
auto[1] |
1075 |
1 |
|
|
T12 |
5 |
|
T15 |
4 |
|
T207 |
10 |
auto[1] |
auto[0] |
15378 |
1 |
|
|
T1 |
61 |
|
T2 |
14 |
|
T7 |
8 |
auto[1] |
auto[1] |
851 |
1 |
|
|
T14 |
9 |
|
T15 |
15 |
|
T16 |
11 |
Summary for Cross jtag_post_trans_err_xp
Samples crossed: jtag_csr_cp post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_post_trans_err_xp
Bins
jtag_csr_cp | post_trans_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37069 |
1 |
|
|
T3 |
86 |
|
T8 |
97 |
|
T9 |
1 |
auto[0] |
auto[1] |
1497 |
1 |
|
|
T14 |
10 |
|
T32 |
10 |
|
T34 |
59 |
auto[1] |
auto[0] |
15177 |
1 |
|
|
T1 |
61 |
|
T7 |
8 |
|
T14 |
126 |
auto[1] |
auto[1] |
1052 |
1 |
|
|
T2 |
14 |
|
T16 |
15 |
|
T34 |
16 |