Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

99652365

1

T1

220665

T2

43658

T3

18399

auto[1]

1460074

1

T1

1176

T3

10048

T8

3663

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

99635060

1

T1

218018

T2

43364

T3

19602

auto[1]

1477379

1

T1

3823

T2

294

T3

8845

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	7288092	1			T1	18043		T2	4428		T3	7930
auto[IdleSt]	21601355	1			T1	13080		T2	12524		T3	2626
auto[ClkMuxSt]	35796	1			T2	8		T3	75		T9	1
auto[CntIncrSt]	35482	1			T2	8		T3	75		T9	1
auto[CntProgSt]	1533943	1			T2	91		T3	809		T9	5
auto[TransCheckSt]	27589	1			T2	8		T3	44		T7	21
auto[TokenHashSt]	39378548	1			T2	216		T3	2447		T7	532
auto[FlashRmaSt]	27874	1			T2	39		T3	67		T7	74
auto[TokenCheck0St]	12542	1			T2	8		T3	25		T7	21
auto[TokenCheck1St]	9238	1			T2	8		T3	25		T7	21
auto[TransProgSt]	393860	1			T2	99		T3	81		T7	42
auto[PostTransSt]	13188128	1			T2	17268		T3	10		T9	61
auto[ScrapSt]	175241	1			T3	6		T7	33		T11	37
auto[EscalateSt]	6606900	1			T1	40514		T2	3688		T3	14227
auto[InvalidSt]	10795821	1			T1	150198		T2	5265		T8	10974

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	2030	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	10795821	1			T1	150198		T2	5265		T8	10974
EscalateSt	6606900	1			T1	40514		T2	3688		T3	14227
ScrapSt	175241	1			T3	6		T7	33		T11	37
PostTransSt	13188128	1			T2	17268		T3	10		T9	61
TransProgSt	393860	1			T2	99		T3	81		T7	42
TokenCheck1St	9238	1			T2	8		T3	25		T7	21
TokenCheck0St	12542	1			T2	8		T3	25		T7	21
FlashRmaSt	27874	1			T2	39		T3	67		T7	74
TokenHashSt	39378548	1			T2	216		T3	2447		T7	532
TransCheckSt	27589	1			T2	8		T3	44		T7	21
CntProgSt	1533943	1			T2	91		T3	809		T9	5
CntIncrSt	35482	1			T2	8		T3	75		T9	1
ClkMuxSt	35796	1			T2	8		T3	75		T9	1
IdleSt	21601355	1			T1	13080		T2	12524		T3	2626
ResetSt	7288092	1			T1	18043		T2	4428		T3	7930
arcs[ResetSt=>IdleSt]	54938	1			T1	59		T2	14		T3	78
arcs[IdleSt=>ScrapSt]	290	1			T3	2		T7	1		T11	1
arcs[IdleSt=>ClkMuxSt]	35542	1			T2	8		T3	75		T9	1
arcs[ClkMuxSt=>CntIncrSt]	35482	1			T2	8		T3	75		T9	1
arcs[CntIncrSt=>PostTransSt]	1928	1			T12	5		T14	9		T15	19
arcs[CntIncrSt=>CntProgSt]	33492	1			T2	8		T3	75		T9	1
arcs[CntProgSt=>PostTransSt]	4844	1			T9	1		T7	10		T12	9
arcs[CntProgSt=>TransCheckSt]	27589	1			T2	8		T3	44		T7	21
arcs[TransCheckSt=>PostTransSt]	3825	1			T12	8		T14	11		T15	20
arcs[TransCheckSt=>TokenHashSt]	23625	1			T2	8		T3	43		T7	21
arcs[TokenHashSt=>PostTransSt]	10206	1			T12	17		T13	8		T26	74
arcs[TokenHashSt=>FlashRmaSt]	12664	1			T2	8		T3	28		T7	21
arcs[FlashRmaSt=>TokenCheck0St]	12542	1			T2	8		T3	25		T7	21
arcs[TokenCheck0St=>PostTransSt]	3282	1			T12	9		T13	7		T14	10
arcs[TokenCheck0St=>TokenCheck1St]	9238	1			T2	8		T3	25		T7	21
arcs[TokenCheck1St=>PostTransSt]	659	1			T14	2		T15	2		T37	10
arcs[TransProgSt=>PostTransSt]	7693	1			T2	8		T3	5		T7	21
arcs[IdleSt=>EscalateSt]	256	1			T33	5		T45	13		T46	5
arcs[ClkMuxSt=>EscalateSt]	60	1			T33	1		T45	3		T46	2
arcs[CntIncrSt=>EscalateSt]	62	1			T33	2		T45	2		T47	2
arcs[CntProgSt=>EscalateSt]	1059	1			T3	31		T33	10		T45	33
arcs[TransCheckSt=>EscalateSt]	139	1			T3	1		T33	9		T46	8
arcs[TokenHashSt=>EscalateSt]	755	1			T3	15		T15	2		T33	21
arcs[FlashRmaSt=>EscalateSt]	122	1			T3	3		T33	2		T45	2
arcs[TokenCheck0St=>EscalateSt]	22	1			T46	1		T51	1		T52	1
arcs[TokenCheck1St=>EscalateSt]	130	1			T3	1		T33	1		T45	2
arcs[TransProgSt=>EscalateSt]	756	1			T3	19		T33	10		T45	15
arcs[PostTransSt=>EscalateSt]	5130	1			T3	5		T9	1		T7	10
arcs[InvalidSt=>EscalateSt]	14575	1			T1	51		T2	3		T8	79

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7287910	1			T1	18043		T2	4428		T3	7924
auto[0]	auto[IdleSt]	21601185	1			T1	13080		T2	12524		T3	2626
auto[0]	auto[ClkMuxSt]	35755	1			T2	8		T3	75		T9	1
auto[0]	auto[CntIncrSt]	35440	1			T2	8		T3	75		T9	1
auto[0]	auto[CntProgSt]	1533241	1			T2	91		T3	790		T9	5
auto[0]	auto[TransCheckSt]	27493	1			T2	8		T3	43		T7	21
auto[0]	auto[TokenHashSt]	39378074	1			T2	216		T3	2434		T7	532
auto[0]	auto[FlashRmaSt]	27797	1			T2	39		T3	64		T7	74
auto[0]	auto[TokenCheck0St]	12531	1			T2	8		T3	25		T7	21
auto[0]	auto[TokenCheck1St]	9157	1			T2	8		T3	24		T7	21
auto[0]	auto[TransProgSt]	393343	1			T2	99		T3	68		T7	42
auto[0]	auto[PostTransSt]	13185464	1			T2	17268		T3	7		T9	61
auto[0]	auto[ScrapSt]	175195	1			T3	4		T7	33		T11	37
auto[0]	auto[EscalateSt]	5159146	1			T1	39350		T2	3688		T3	4240
auto[0]	auto[InvalidSt]	10788604	1			T1	150186		T2	5265		T8	10937
auto[1]	auto[ResetSt]	182	1			T3	6		T33	3		T45	7
auto[1]	auto[IdleSt]	170	1			T33	5		T45	9		T46	4
auto[1]	auto[ClkMuxSt]	41	1			T33	1		T45	2		T46	2
auto[1]	auto[CntIncrSt]	42	1			T33	2		T45	2		T47	1
auto[1]	auto[CntProgSt]	702	1			T3	19		T33	6		T45	23
auto[1]	auto[TransCheckSt]	96	1			T3	1		T33	6		T46	5
auto[1]	auto[TokenHashSt]	474	1			T3	13		T15	2		T33	13
auto[1]	auto[FlashRmaSt]	77	1			T3	3		T33	2		T45	2
auto[1]	auto[TokenCheck0St]	11	1			T46	1		T51	1		T107	1
auto[1]	auto[TokenCheck1St]	81	1			T3	1		T45	2		T47	3
auto[1]	auto[TransProgSt]	517	1			T3	13		T33	9		T45	11
auto[1]	auto[PostTransSt]	2664	1			T3	3		T7	8		T12	5
auto[1]	auto[ScrapSt]	46	1			T3	2		T33	2		T45	2
auto[1]	auto[EscalateSt]	1447754	1			T1	1164		T3	9987		T8	3626
auto[1]	auto[InvalidSt]	7217	1			T1	12		T8	37		T10	33

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7287906	1			T1	18043		T2	4428		T3	7923
auto[0]	auto[IdleSt]	21601183	1			T1	13080		T2	12524		T3	2626
auto[0]	auto[ClkMuxSt]	35758	1			T2	8		T3	75		T9	1
auto[0]	auto[CntIncrSt]	35443	1			T2	8		T3	75		T9	1
auto[0]	auto[CntProgSt]	1533219	1			T2	91		T3	789		T9	5
auto[0]	auto[TransCheckSt]	27492	1			T2	8		T3	43		T7	21
auto[0]	auto[TokenHashSt]	39378021	1			T2	216		T3	2440		T7	532
auto[0]	auto[FlashRmaSt]	27796	1			T2	39		T3	67		T7	74
auto[0]	auto[TokenCheck0St]	12527	1			T2	8		T3	25		T7	21
auto[0]	auto[TokenCheck1St]	9151	1			T2	8		T3	25		T7	21
auto[0]	auto[TransProgSt]	393354	1			T2	99		T3	68		T7	42
auto[0]	auto[PostTransSt]	13185580	1			T2	17268		T3	6		T9	60
auto[0]	auto[ScrapSt]	175201	1			T3	4		T7	33		T11	37
auto[0]	auto[EscalateSt]	5141936	1			T1	36730		T2	3397		T3	5436
auto[0]	auto[InvalidSt]	10788463	1			T1	150159		T2	5262		T8	10932
auto[1]	auto[ResetSt]	186	1			T3	7		T33	3		T45	2
auto[1]	auto[IdleSt]	172	1			T33	4		T45	9		T46	3
auto[1]	auto[ClkMuxSt]	38	1			T45	2		T107	1		T204	1
auto[1]	auto[CntIncrSt]	39	1			T45	1		T47	1		T51	2
auto[1]	auto[CntProgSt]	724	1			T3	20		T33	8		T45	23
auto[1]	auto[TransCheckSt]	97	1			T3	1		T33	5		T46	8
auto[1]	auto[TokenHashSt]	527	1			T3	7		T33	13		T45	10
auto[1]	auto[FlashRmaSt]	78	1			T45	2		T47	1		T51	2
auto[1]	auto[TokenCheck0St]	15	1			T52	1		T107	1		T205	1
auto[1]	auto[TokenCheck1St]	87	1			T33	1		T45	1		T47	3
auto[1]	auto[TransProgSt]	506	1			T3	13		T33	7		T45	11
auto[1]	auto[PostTransSt]	2548	1			T3	4		T9	1		T7	2
auto[1]	auto[ScrapSt]	40	1			T3	2		T33	2		T45	1
auto[1]	auto[EscalateSt]	1464964	1			T1	3784		T2	291		T3	8791
auto[1]	auto[InvalidSt]	7358	1			T1	39		T2	3		T8	42