Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

95215333

1

T1

21367

T2

819

T3

28265

auto[1]

1335930

1

T1

2277

T3

15853

T4

3366

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

95204386

1

T1

20872

T2

819

T3

30676

auto[1]

1346877

1

T1

2772

T3

13442

T4

1980

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	7131719	1			T1	5822		T2	112		T3	8510
auto[IdleSt]	20947767	1			T1	933		T2	50		T3	9937
auto[ClkMuxSt]	36476	1			T3	80		T5	7		T12	65
auto[CntIncrSt]	36170	1			T3	76		T5	7		T12	65
auto[CntProgSt]	1822696	1			T3	977		T5	72		T12	1000
auto[TransCheckSt]	28341	1			T3	44		T5	7		T12	49
auto[TokenHashSt]	35723692	1			T3	3581		T5	77734		T12	3190
auto[FlashRmaSt]	28878	1			T3	65		T5	7		T12	65
auto[TokenCheck0St]	12779	1			T3	35		T5	7		T12	37
auto[TokenCheck1St]	9384	1			T3	34		T5	7		T12	24
auto[TransProgSt]	486485	1			T3	141		T5	77		T12	460
auto[PostTransSt]	13134382	1			T2	657		T3	13		T5	2634
auto[ScrapSt]	169037	1			T3	3		T7	1254		T43	21
auto[EscalateSt]	6389164	1			T1	7312		T3	20622		T4	7430
auto[InvalidSt]	10592462	1			T1	9569		T4	7252		T12	1901

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1831	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	10592462	1			T1	9569		T4	7252		T12	1901
EscalateSt	6389164	1			T1	7312		T3	20622		T4	7430
ScrapSt	169037	1			T3	3		T7	1254		T43	21
PostTransSt	13134382	1			T2	657		T3	13		T5	2634
TransProgSt	486485	1			T3	141		T5	77		T12	460
TokenCheck1St	9384	1			T3	34		T5	7		T12	24
TokenCheck0St	12779	1			T3	35		T5	7		T12	37
FlashRmaSt	28878	1			T3	65		T5	7		T12	65
TokenHashSt	35723692	1			T3	3581		T5	77734		T12	3190
TransCheckSt	28341	1			T3	44		T5	7		T12	49
CntProgSt	1822696	1			T3	977		T5	72		T12	1000
CntIncrSt	36170	1			T3	76		T5	7		T12	65
ClkMuxSt	36476	1			T3	80		T5	7		T12	65
IdleSt	20947767	1			T1	933		T2	50		T3	9937
ResetSt	7131719	1			T1	5822		T2	112		T3	8510
arcs[ResetSt=>IdleSt]	53828	1			T1	58		T2	1		T3	93
arcs[IdleSt=>ScrapSt]	277	1			T3	1		T7	2		T43	1
arcs[IdleSt=>ClkMuxSt]	36247	1			T3	80		T5	7		T12	65
arcs[ClkMuxSt=>CntIncrSt]	36170	1			T3	76		T5	7		T12	65
arcs[CntIncrSt=>PostTransSt]	1941	1			T7	10		T18	45		T19	4
arcs[CntIncrSt=>CntProgSt]	34163	1			T3	76		T5	7		T12	65
arcs[CntProgSt=>PostTransSt]	4840	1			T12	16		T6	9		T7	37
arcs[CntProgSt=>TransCheckSt]	28341	1			T3	44		T5	7		T12	49
arcs[TransCheckSt=>PostTransSt]	3901	1			T6	3		T7	11		T18	23
arcs[TransCheckSt=>TokenHashSt]	24303	1			T3	43		T5	7		T12	49
arcs[TokenHashSt=>PostTransSt]	10720	1			T12	12		T14	92		T6	5
arcs[TokenHashSt=>FlashRmaSt]	12874	1			T3	37		T5	7		T12	37
arcs[FlashRmaSt=>TokenCheck0St]	12779	1			T3	35		T5	7		T12	37
arcs[TokenCheck0St=>PostTransSt]	3372	1			T12	13		T6	3		T7	9
arcs[TokenCheck0St=>TokenCheck1St]	9384	1			T3	34		T5	7		T12	24
arcs[TokenCheck1St=>PostTransSt]	664	1			T18	3		T19	1		T52	8
arcs[TransProgSt=>PostTransSt]	7842	1			T3	5		T5	7		T12	24
arcs[IdleSt=>EscalateSt]	179	1			T3	11		T35	7		T55	3
arcs[ClkMuxSt=>EscalateSt]	77	1			T3	4		T35	1		T53	1
arcs[CntIncrSt=>EscalateSt]	66	1			T35	2		T53	1		T54	1
arcs[CntProgSt=>EscalateSt]	982	1			T3	32		T35	17		T53	22
arcs[TransCheckSt=>EscalateSt]	137	1			T3	1		T35	1		T58	9
arcs[TokenHashSt=>EscalateSt]	709	1			T3	6		T19	1		T35	5
arcs[FlashRmaSt=>EscalateSt]	95	1			T3	2		T53	1		T54	2
arcs[TokenCheck0St=>EscalateSt]	23	1			T3	1		T35	1		T54	1
arcs[TokenCheck1St=>EscalateSt]	151	1			T3	4		T35	3		T54	3
arcs[TransProgSt=>EscalateSt]	727	1			T3	25		T35	11		T53	11
arcs[PostTransSt=>EscalateSt]	5098	1			T3	5		T12	16		T6	9
arcs[InvalidSt=>EscalateSt]	13084	1			T1	51		T4	54		T12	13

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7131550	1			T1	5822		T2	112		T3	8506
auto[0]	auto[IdleSt]	20947642	1			T1	933		T2	50		T3	9928
auto[0]	auto[ClkMuxSt]	36420	1			T3	78		T5	7		T12	65
auto[0]	auto[CntIncrSt]	36125	1			T3	76		T5	7		T12	65
auto[0]	auto[CntProgSt]	1822050	1			T3	952		T5	72		T12	1000
auto[0]	auto[TransCheckSt]	28239	1			T3	43		T5	7		T12	49
auto[0]	auto[TokenHashSt]	35723235	1			T3	3576		T5	77734		T12	3190
auto[0]	auto[FlashRmaSt]	28805	1			T3	63		T5	7		T12	65
auto[0]	auto[TokenCheck0St]	12768	1			T3	35		T5	7		T12	37
auto[0]	auto[TokenCheck1St]	9290	1			T3	31		T5	7		T12	24
auto[0]	auto[TransProgSt]	486029	1			T3	125		T5	77		T12	460
auto[0]	auto[PostTransSt]	13131762	1			T2	657		T3	8		T5	2634
auto[0]	auto[ScrapSt]	168990	1			T3	2		T7	1254		T43	21
auto[0]	auto[EscalateSt]	5064605	1			T1	5058		T3	4842		T4	4098
auto[0]	auto[InvalidSt]	10585992	1			T1	9546		T4	7218		T12	1898
auto[1]	auto[ResetSt]	169	1			T3	4		T35	3		T53	2
auto[1]	auto[IdleSt]	125	1			T3	9		T35	5		T55	1
auto[1]	auto[ClkMuxSt]	56	1			T3	2		T35	1		T53	1
auto[1]	auto[CntIncrSt]	45	1			T35	1		T53	1		T54	1
auto[1]	auto[CntProgSt]	646	1			T3	25		T35	12		T53	12
auto[1]	auto[TransCheckSt]	102	1			T3	1		T35	1		T58	8
auto[1]	auto[TokenHashSt]	457	1			T3	5		T35	5		T53	17
auto[1]	auto[FlashRmaSt]	73	1			T3	2		T54	1		T58	5
auto[1]	auto[TokenCheck0St]	11	1			T35	1		T211	1		T212	1
auto[1]	auto[TokenCheck1St]	94	1			T3	3		T35	3		T54	1
auto[1]	auto[TransProgSt]	456	1			T3	16		T35	7		T53	6
auto[1]	auto[PostTransSt]	2620	1			T3	5		T12	8		T6	2
auto[1]	auto[ScrapSt]	47	1			T3	1		T35	1		T58	1
auto[1]	auto[EscalateSt]	1324559	1			T1	2254		T3	15780		T4	3332
auto[1]	auto[InvalidSt]	6470	1			T1	23		T4	34		T12	3

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7131556	1			T1	5822		T2	112		T3	8506
auto[0]	auto[IdleSt]	20947648	1			T1	933		T2	50		T3	9930
auto[0]	auto[ClkMuxSt]	36433	1			T3	77		T5	7		T12	65
auto[0]	auto[CntIncrSt]	36129	1			T3	76		T5	7		T12	65
auto[0]	auto[CntProgSt]	1822055	1			T3	961		T5	72		T12	1000
auto[0]	auto[TransCheckSt]	28252	1			T3	44		T5	7		T12	49
auto[0]	auto[TokenHashSt]	35723204	1			T3	3576		T5	77734		T12	3190
auto[0]	auto[FlashRmaSt]	28823	1			T3	64		T5	7		T12	65
auto[0]	auto[TokenCheck0St]	12763	1			T3	34		T5	7		T12	37
auto[0]	auto[TokenCheck1St]	9281	1			T3	31		T5	7		T12	24
auto[0]	auto[TransProgSt]	485989	1			T3	124		T5	77		T12	460
auto[0]	auto[PostTransSt]	13131822	1			T2	657		T3	9		T5	2634
auto[0]	auto[ScrapSt]	168991	1			T3	2		T7	1254		T43	21
auto[0]	auto[EscalateSt]	5053761	1			T1	4568		T3	7242		T4	5470
auto[0]	auto[InvalidSt]	10585848	1			T1	9541		T4	7232		T12	1891
auto[1]	auto[ResetSt]	163	1			T3	4		T35	5		T53	4
auto[1]	auto[IdleSt]	119	1			T3	7		T35	3		T55	2
auto[1]	auto[ClkMuxSt]	43	1			T3	3		T35	1		T53	1
auto[1]	auto[CntIncrSt]	41	1			T35	2		T58	1		T55	2
auto[1]	auto[CntProgSt]	641	1			T3	16		T35	8		T53	15
auto[1]	auto[TransCheckSt]	89	1			T58	5		T55	3		T213	8
auto[1]	auto[TokenHashSt]	488	1			T3	5		T19	1		T35	3
auto[1]	auto[FlashRmaSt]	55	1			T3	1		T53	1		T54	1
auto[1]	auto[TokenCheck0St]	16	1			T3	1		T54	1		T212	2
auto[1]	auto[TokenCheck1St]	103	1			T3	3		T35	2		T54	2
auto[1]	auto[TransProgSt]	496	1			T3	17		T35	7		T53	7
auto[1]	auto[PostTransSt]	2560	1			T3	4		T12	8		T6	7
auto[1]	auto[ScrapSt]	46	1			T3	1		T35	2		T54	1
auto[1]	auto[EscalateSt]	1335403	1			T1	2744		T3	13380		T4	1960
auto[1]	auto[InvalidSt]	6614	1			T1	28		T4	20		T12	10