Summary for Variable clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53705 |
1 |
|
|
T1 |
64 |
|
T2 |
16 |
|
T4 |
15 |
auto[1] |
2003 |
1 |
|
|
T1 |
11 |
|
T11 |
20 |
|
T14 |
16 |
Summary for Variable clk_byp_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54936 |
1 |
|
|
T1 |
75 |
|
T2 |
16 |
|
T4 |
15 |
auto[1] |
772 |
1 |
|
|
T37 |
19 |
|
T58 |
7 |
|
T59 |
12 |
Summary for Variable count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53758 |
1 |
|
|
T1 |
75 |
|
T2 |
16 |
|
T4 |
14 |
auto[1] |
1950 |
1 |
|
|
T4 |
1 |
|
T9 |
1 |
|
T11 |
22 |
Summary for Variable count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53759 |
1 |
|
|
T1 |
75 |
|
T2 |
16 |
|
T4 |
14 |
auto[1] |
1949 |
1 |
|
|
T4 |
1 |
|
T9 |
1 |
|
T11 |
20 |
Summary for Variable count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53808 |
1 |
|
|
T1 |
75 |
|
T2 |
16 |
|
T4 |
14 |
auto[1] |
1900 |
1 |
|
|
T4 |
1 |
|
T11 |
28 |
|
T12 |
21 |
Summary for Variable err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for err_inj_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
err_inj |
50873 |
1 |
|
|
T1 |
75 |
|
T4 |
8 |
|
T9 |
6 |
no_err_inj |
4835 |
1 |
|
|
T2 |
16 |
|
T4 |
7 |
|
T9 |
6 |
Summary for Variable flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53767 |
1 |
|
|
T1 |
66 |
|
T2 |
16 |
|
T4 |
15 |
auto[1] |
1941 |
1 |
|
|
T1 |
9 |
|
T11 |
19 |
|
T14 |
16 |
Summary for Variable flash_rma_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54924 |
1 |
|
|
T1 |
75 |
|
T2 |
16 |
|
T4 |
15 |
auto[1] |
784 |
1 |
|
|
T37 |
27 |
|
T58 |
10 |
|
T59 |
19 |
Summary for Variable jtag_csr_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for jtag_csr_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
38327 |
1 |
|
|
T4 |
15 |
|
T9 |
12 |
|
T11 |
275 |
auto[1] |
17381 |
1 |
|
|
T1 |
75 |
|
T2 |
16 |
|
T11 |
209 |
Summary for Variable kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for kmac_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53797 |
1 |
|
|
T1 |
75 |
|
T2 |
16 |
|
T4 |
15 |
auto[1] |
1911 |
1 |
|
|
T11 |
23 |
|
T12 |
17 |
|
T14 |
9 |
Summary for Variable lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for lc_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53836 |
1 |
|
|
T1 |
75 |
|
T2 |
16 |
|
T4 |
14 |
auto[1] |
1872 |
1 |
|
|
T4 |
1 |
|
T9 |
1 |
|
T11 |
34 |
Summary for Variable otp_lc_data_i_valid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_lc_data_i_valid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53702 |
1 |
|
|
T1 |
75 |
|
T2 |
16 |
|
T4 |
14 |
auto[1] |
2006 |
1 |
|
|
T4 |
1 |
|
T11 |
27 |
|
T12 |
15 |
Summary for Variable otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_partition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53800 |
1 |
|
|
T1 |
60 |
|
T2 |
16 |
|
T4 |
15 |
auto[1] |
1908 |
1 |
|
|
T1 |
15 |
|
T11 |
15 |
|
T14 |
11 |
Summary for Variable otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_prog_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53246 |
1 |
|
|
T1 |
75 |
|
T2 |
16 |
|
T4 |
15 |
auto[1] |
2462 |
1 |
|
|
T11 |
32 |
|
T12 |
7 |
|
T55 |
1 |
Summary for Variable otp_rma_token_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_rma_token_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54924 |
1 |
|
|
T1 |
75 |
|
T2 |
16 |
|
T4 |
15 |
auto[1] |
784 |
1 |
|
|
T37 |
19 |
|
T58 |
23 |
|
T59 |
18 |
Summary for Variable otp_secrets_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_secrets_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54947 |
1 |
|
|
T1 |
75 |
|
T2 |
16 |
|
T4 |
15 |
auto[1] |
761 |
1 |
|
|
T37 |
16 |
|
T58 |
12 |
|
T59 |
14 |
Summary for Variable otp_test_tokens_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_test_tokens_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54940 |
1 |
|
|
T1 |
75 |
|
T2 |
16 |
|
T4 |
15 |
auto[1] |
768 |
1 |
|
|
T37 |
14 |
|
T58 |
17 |
|
T59 |
16 |
Summary for Variable post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for post_trans_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53022 |
1 |
|
|
T1 |
75 |
|
T2 |
16 |
|
T11 |
402 |
auto[1] |
2686 |
1 |
|
|
T4 |
15 |
|
T9 |
12 |
|
T11 |
82 |
Summary for Variable security_escalation_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for security_escalation_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52039 |
1 |
|
|
T1 |
75 |
|
T2 |
16 |
|
T4 |
15 |
auto[1] |
3669 |
1 |
|
|
T15 |
61 |
|
T24 |
77 |
|
T44 |
64 |
Summary for Variable state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53703 |
1 |
|
|
T1 |
75 |
|
T2 |
16 |
|
T4 |
14 |
auto[1] |
2005 |
1 |
|
|
T4 |
1 |
|
T9 |
2 |
|
T11 |
33 |
Summary for Variable state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53763 |
1 |
|
|
T1 |
75 |
|
T2 |
16 |
|
T4 |
15 |
auto[1] |
1945 |
1 |
|
|
T9 |
1 |
|
T11 |
31 |
|
T12 |
23 |
Summary for Variable state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53720 |
1 |
|
|
T1 |
75 |
|
T2 |
16 |
|
T4 |
13 |
auto[1] |
1988 |
1 |
|
|
T4 |
2 |
|
T11 |
31 |
|
T12 |
23 |
Summary for Variable token_invalid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_invalid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53683 |
1 |
|
|
T1 |
62 |
|
T2 |
16 |
|
T4 |
15 |
auto[1] |
2025 |
1 |
|
|
T1 |
13 |
|
T11 |
19 |
|
T14 |
20 |
Summary for Variable token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mismatch_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49907 |
1 |
|
|
T1 |
70 |
|
T2 |
16 |
|
T4 |
15 |
auto[1] |
5801 |
1 |
|
|
T1 |
5 |
|
T11 |
18 |
|
T14 |
26 |
Summary for Variable token_mux_ctrl_redun_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mux_ctrl_redun_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51935 |
1 |
|
|
T1 |
75 |
|
T2 |
16 |
|
T4 |
15 |
auto[1] |
3773 |
1 |
|
|
T30 |
75 |
|
T56 |
97 |
|
T57 |
80 |
Summary for Variable token_mux_digest_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for token_mux_digest_err_cp
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
55708 |
1 |
|
|
T1 |
75 |
|
T2 |
16 |
|
T4 |
15 |
Summary for Variable token_response_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_response_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53745 |
1 |
|
|
T1 |
66 |
|
T2 |
16 |
|
T4 |
15 |
auto[1] |
1963 |
1 |
|
|
T1 |
9 |
|
T11 |
16 |
|
T14 |
17 |
Summary for Variable transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53728 |
1 |
|
|
T1 |
68 |
|
T2 |
16 |
|
T4 |
15 |
auto[1] |
1980 |
1 |
|
|
T1 |
7 |
|
T11 |
5 |
|
T14 |
22 |
Summary for Variable transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53755 |
1 |
|
|
T1 |
69 |
|
T2 |
16 |
|
T4 |
15 |
auto[1] |
1953 |
1 |
|
|
T1 |
6 |
|
T11 |
15 |
|
T14 |
17 |
Summary for Cross post_trans_err_inj_xp
Samples crossed: post_trans_err_cp err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_err_inj_xp
Bins
post_trans_err_cp | err_inj_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
err_inj |
49546 |
1 |
|
|
T1 |
75 |
|
T11 |
362 |
|
T12 |
151 |
auto[0] |
no_err_inj |
3476 |
1 |
|
|
T2 |
16 |
|
T11 |
40 |
|
T12 |
6 |
auto[1] |
err_inj |
1327 |
1 |
|
|
T4 |
8 |
|
T9 |
6 |
|
T11 |
46 |
auto[1] |
no_err_inj |
1359 |
1 |
|
|
T4 |
7 |
|
T9 |
6 |
|
T11 |
36 |
Summary for Cross post_trans_state_err_xp
Samples crossed: post_trans_err_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_err_xp
Bins
post_trans_err_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
51229 |
1 |
|
|
T1 |
75 |
|
T2 |
16 |
|
T11 |
377 |
auto[0] |
auto[1] |
1793 |
1 |
|
|
T11 |
25 |
|
T12 |
21 |
|
T14 |
10 |
auto[1] |
auto[0] |
2534 |
1 |
|
|
T4 |
15 |
|
T9 |
11 |
|
T11 |
76 |
auto[1] |
auto[1] |
152 |
1 |
|
|
T9 |
1 |
|
T11 |
6 |
|
T12 |
2 |
Summary for Cross post_trans_lc_fsm_backdoor_err_xp
Samples crossed: post_trans_err_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_lc_fsm_backdoor_err_xp
Bins
post_trans_err_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
51291 |
1 |
|
|
T1 |
75 |
|
T2 |
16 |
|
T11 |
376 |
auto[0] |
auto[1] |
1731 |
1 |
|
|
T11 |
26 |
|
T12 |
11 |
|
T14 |
6 |
auto[1] |
auto[0] |
2545 |
1 |
|
|
T4 |
14 |
|
T9 |
11 |
|
T11 |
74 |
auto[1] |
auto[1] |
141 |
1 |
|
|
T4 |
1 |
|
T9 |
1 |
|
T11 |
8 |
Summary for Cross post_trans_state_illegal_err_xp
Samples crossed: post_trans_err_cp state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_illegal_err_xp
Bins
post_trans_err_cp | state_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
51192 |
1 |
|
|
T1 |
75 |
|
T2 |
16 |
|
T11 |
379 |
auto[0] |
auto[1] |
1830 |
1 |
|
|
T11 |
23 |
|
T12 |
20 |
|
T14 |
6 |
auto[1] |
auto[0] |
2528 |
1 |
|
|
T4 |
13 |
|
T9 |
12 |
|
T11 |
74 |
auto[1] |
auto[1] |
158 |
1 |
|
|
T4 |
2 |
|
T11 |
8 |
|
T12 |
3 |
Summary for Cross post_trans_count_err_xp
Samples crossed: post_trans_err_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_err_xp
Bins
post_trans_err_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
51211 |
1 |
|
|
T1 |
75 |
|
T2 |
16 |
|
T11 |
386 |
auto[0] |
auto[1] |
1811 |
1 |
|
|
T11 |
16 |
|
T12 |
17 |
|
T14 |
5 |
auto[1] |
auto[0] |
2548 |
1 |
|
|
T4 |
14 |
|
T9 |
11 |
|
T11 |
78 |
auto[1] |
auto[1] |
138 |
1 |
|
|
T4 |
1 |
|
T9 |
1 |
|
T11 |
4 |
Summary for Cross post_trans_count_illegal_err_xp
Samples crossed: post_trans_err_cp count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_illegal_err_xp
Bins
post_trans_err_cp | count_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
51261 |
1 |
|
|
T1 |
75 |
|
T2 |
16 |
|
T11 |
376 |
auto[0] |
auto[1] |
1761 |
1 |
|
|
T11 |
26 |
|
T12 |
19 |
|
T14 |
9 |
auto[1] |
auto[0] |
2547 |
1 |
|
|
T4 |
14 |
|
T9 |
12 |
|
T11 |
80 |
auto[1] |
auto[1] |
139 |
1 |
|
|
T4 |
1 |
|
T11 |
2 |
|
T12 |
2 |
Summary for Cross post_trans_count_backdoor_err_xp
Samples crossed: post_trans_err_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_backdoor_err_xp
Bins
post_trans_err_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
51229 |
1 |
|
|
T1 |
75 |
|
T2 |
16 |
|
T11 |
383 |
auto[0] |
auto[1] |
1793 |
1 |
|
|
T11 |
19 |
|
T12 |
13 |
|
T14 |
4 |
auto[1] |
auto[0] |
2529 |
1 |
|
|
T4 |
14 |
|
T9 |
11 |
|
T11 |
79 |
auto[1] |
auto[1] |
157 |
1 |
|
|
T4 |
1 |
|
T9 |
1 |
|
T11 |
3 |
Summary for Cross jtag_clk_byp_error_rsp_xp
Samples crossed: jtag_csr_cp clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_clk_byp_error_rsp_xp
Bins
jtag_csr_cp | clk_byp_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37186 |
1 |
|
|
T4 |
15 |
|
T9 |
12 |
|
T11 |
275 |
auto[0] |
auto[1] |
1141 |
1 |
|
|
T14 |
9 |
|
T16 |
8 |
|
T67 |
11 |
auto[1] |
auto[0] |
16519 |
1 |
|
|
T1 |
64 |
|
T2 |
16 |
|
T11 |
189 |
auto[1] |
auto[1] |
862 |
1 |
|
|
T1 |
11 |
|
T11 |
20 |
|
T14 |
7 |
Summary for Cross jtag_flash_rma_error_rsp_xp
Samples crossed: jtag_csr_cp flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_flash_rma_error_rsp_xp
Bins
jtag_csr_cp | flash_rma_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37247 |
1 |
|
|
T4 |
15 |
|
T9 |
12 |
|
T11 |
275 |
auto[0] |
auto[1] |
1080 |
1 |
|
|
T14 |
10 |
|
T16 |
9 |
|
T67 |
11 |
auto[1] |
auto[0] |
16520 |
1 |
|
|
T1 |
66 |
|
T2 |
16 |
|
T11 |
190 |
auto[1] |
auto[1] |
861 |
1 |
|
|
T1 |
9 |
|
T11 |
19 |
|
T14 |
6 |
Summary for Cross jtag_otp_prog_err_xp
Samples crossed: jtag_csr_cp otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_prog_err_xp
Bins
jtag_csr_cp | otp_prog_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37009 |
1 |
|
|
T4 |
15 |
|
T9 |
12 |
|
T11 |
249 |
auto[0] |
auto[1] |
1318 |
1 |
|
|
T11 |
26 |
|
T12 |
7 |
|
T55 |
1 |
auto[1] |
auto[0] |
16237 |
1 |
|
|
T1 |
75 |
|
T2 |
16 |
|
T11 |
203 |
auto[1] |
auto[1] |
1144 |
1 |
|
|
T11 |
6 |
|
T63 |
22 |
|
T39 |
30 |
Summary for Cross jtag_otp_partition_err_xp
Samples crossed: jtag_csr_cp otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_partition_err_xp
Bins
jtag_csr_cp | otp_partition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37274 |
1 |
|
|
T4 |
15 |
|
T9 |
12 |
|
T11 |
275 |
auto[0] |
auto[1] |
1053 |
1 |
|
|
T14 |
5 |
|
T16 |
6 |
|
T67 |
10 |
auto[1] |
auto[0] |
16526 |
1 |
|
|
T1 |
60 |
|
T2 |
16 |
|
T11 |
194 |
auto[1] |
auto[1] |
855 |
1 |
|
|
T1 |
15 |
|
T11 |
15 |
|
T14 |
6 |
Summary for Cross jtag_token_mismatch_err_xp
Samples crossed: jtag_csr_cp token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_token_mismatch_err_xp
Bins
jtag_csr_cp | token_mismatch_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
33419 |
1 |
|
|
T4 |
15 |
|
T9 |
12 |
|
T11 |
275 |
auto[0] |
auto[1] |
4908 |
1 |
|
|
T14 |
9 |
|
T16 |
8 |
|
T67 |
9 |
auto[1] |
auto[0] |
16488 |
1 |
|
|
T1 |
70 |
|
T2 |
16 |
|
T11 |
191 |
auto[1] |
auto[1] |
893 |
1 |
|
|
T1 |
5 |
|
T11 |
18 |
|
T14 |
17 |
Summary for Cross jtag_state_err_xp
Samples crossed: jtag_csr_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_err_xp
Bins
jtag_csr_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37190 |
1 |
|
|
T4 |
15 |
|
T9 |
11 |
|
T11 |
251 |
auto[0] |
auto[1] |
1137 |
1 |
|
|
T9 |
1 |
|
T11 |
24 |
|
T14 |
10 |
auto[1] |
auto[0] |
16573 |
1 |
|
|
T1 |
75 |
|
T2 |
16 |
|
T11 |
202 |
auto[1] |
auto[1] |
808 |
1 |
|
|
T11 |
7 |
|
T12 |
23 |
|
T60 |
3 |
Summary for Cross jtag_state_backdoor_err_xp
Samples crossed: jtag_csr_cp state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_backdoor_err_xp
Bins
jtag_csr_cp | state_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37077 |
1 |
|
|
T4 |
14 |
|
T9 |
10 |
|
T11 |
247 |
auto[0] |
auto[1] |
1250 |
1 |
|
|
T4 |
1 |
|
T9 |
2 |
|
T11 |
28 |
auto[1] |
auto[0] |
16626 |
1 |
|
|
T1 |
75 |
|
T2 |
16 |
|
T11 |
204 |
auto[1] |
auto[1] |
755 |
1 |
|
|
T11 |
5 |
|
T12 |
13 |
|
T87 |
6 |
Summary for Cross jtag_lc_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_lc_fsm_backdoor_err_xp
Bins
jtag_csr_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37216 |
1 |
|
|
T4 |
14 |
|
T9 |
11 |
|
T11 |
251 |
auto[0] |
auto[1] |
1111 |
1 |
|
|
T4 |
1 |
|
T9 |
1 |
|
T11 |
24 |
auto[1] |
auto[0] |
16620 |
1 |
|
|
T1 |
75 |
|
T2 |
16 |
|
T11 |
199 |
auto[1] |
auto[1] |
761 |
1 |
|
|
T11 |
10 |
|
T12 |
11 |
|
T87 |
8 |
Summary for Cross jtag_kmac_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_kmac_fsm_backdoor_err_xp
Bins
jtag_csr_cp | kmac_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37178 |
1 |
|
|
T4 |
15 |
|
T9 |
12 |
|
T11 |
257 |
auto[0] |
auto[1] |
1149 |
1 |
|
|
T11 |
18 |
|
T14 |
9 |
|
T86 |
1 |
auto[1] |
auto[0] |
16619 |
1 |
|
|
T1 |
75 |
|
T2 |
16 |
|
T11 |
204 |
auto[1] |
auto[1] |
762 |
1 |
|
|
T11 |
5 |
|
T12 |
17 |
|
T60 |
1 |
Summary for Cross jtag_count_err_xp
Samples crossed: jtag_csr_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_err_xp
Bins
jtag_csr_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37174 |
1 |
|
|
T4 |
14 |
|
T9 |
11 |
|
T11 |
259 |
auto[0] |
auto[1] |
1153 |
1 |
|
|
T4 |
1 |
|
T9 |
1 |
|
T11 |
16 |
auto[1] |
auto[0] |
16585 |
1 |
|
|
T1 |
75 |
|
T2 |
16 |
|
T11 |
205 |
auto[1] |
auto[1] |
796 |
1 |
|
|
T11 |
4 |
|
T12 |
17 |
|
T87 |
7 |
Summary for Cross jtag_count_backdoor_err_xp
Samples crossed: jtag_csr_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_backdoor_err_xp
Bins
jtag_csr_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37170 |
1 |
|
|
T4 |
14 |
|
T9 |
11 |
|
T11 |
257 |
auto[0] |
auto[1] |
1157 |
1 |
|
|
T4 |
1 |
|
T9 |
1 |
|
T11 |
18 |
auto[1] |
auto[0] |
16588 |
1 |
|
|
T1 |
75 |
|
T2 |
16 |
|
T11 |
205 |
auto[1] |
auto[1] |
793 |
1 |
|
|
T11 |
4 |
|
T12 |
13 |
|
T87 |
6 |
Summary for Cross jtag_transition_err_xp
Samples crossed: jtag_csr_cp transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_err_xp
Bins
jtag_csr_cp | transition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37196 |
1 |
|
|
T4 |
15 |
|
T9 |
12 |
|
T11 |
275 |
auto[0] |
auto[1] |
1131 |
1 |
|
|
T14 |
11 |
|
T16 |
7 |
|
T67 |
11 |
auto[1] |
auto[0] |
16559 |
1 |
|
|
T1 |
69 |
|
T2 |
16 |
|
T11 |
194 |
auto[1] |
auto[1] |
822 |
1 |
|
|
T1 |
6 |
|
T11 |
15 |
|
T14 |
6 |
Summary for Cross jtag_transition_count_err_xp
Samples crossed: jtag_csr_cp transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_count_err_xp
Bins
jtag_csr_cp | transition_count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37215 |
1 |
|
|
T4 |
15 |
|
T9 |
12 |
|
T11 |
275 |
auto[0] |
auto[1] |
1112 |
1 |
|
|
T14 |
8 |
|
T16 |
5 |
|
T67 |
10 |
auto[1] |
auto[0] |
16513 |
1 |
|
|
T1 |
68 |
|
T2 |
16 |
|
T11 |
204 |
auto[1] |
auto[1] |
868 |
1 |
|
|
T1 |
7 |
|
T11 |
5 |
|
T14 |
14 |
Summary for Cross jtag_post_trans_err_xp
Samples crossed: jtag_csr_cp post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_post_trans_err_xp
Bins
jtag_csr_cp | post_trans_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36833 |
1 |
|
|
T11 |
204 |
|
T12 |
12 |
|
T13 |
18 |
auto[0] |
auto[1] |
1494 |
1 |
|
|
T4 |
15 |
|
T9 |
12 |
|
T11 |
71 |
auto[1] |
auto[0] |
16189 |
1 |
|
|
T1 |
75 |
|
T2 |
16 |
|
T11 |
198 |
auto[1] |
auto[1] |
1192 |
1 |
|
|
T11 |
11 |
|
T12 |
12 |
|
T60 |
11 |