Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

100081464

1

T1

191364

T2

39034

T3

3239

auto[1]

1434135

1

T1

693

T4

297

T9

297

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

100082120

1

T1

191661

T2

39034

T3

3239

auto[1]

1433479

1

T1

396

T4

198

T9

297

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	7442132	1			T1	7185		T2	1414		T3	161
auto[IdleSt]	23281612	1			T1	77848		T2	32077		T3	3078
auto[ClkMuxSt]	36949	1			T1	75		T2	16		T8	1
auto[CntIncrSt]	36784	1			T1	75		T2	16		T8	1
auto[CntProgSt]	1478172	1			T1	28560		T2	32		T8	27
auto[TransCheckSt]	28503	1			T1	57		T2	16		T8	1
auto[TokenHashSt]	37282370	1			T1	4424		T2	602		T8	471
auto[FlashRmaSt]	28670	1			T1	53		T2	26		T8	1
auto[TokenCheck0St]	13054	1			T1	24		T2	16		T8	1
auto[TokenCheck1St]	9601	1			T1	15		T2	16		T8	1
auto[TransProgSt]	389064	1			T1	5290		T2	32		T8	22
auto[PostTransSt]	13942630	1			T1	63702		T2	4771		T8	696
auto[ScrapSt]	197666	1			T11	2034		T12	5113		T14	811
auto[EscalateSt]	6698932	1			T1	4749		T4	1238		T9	1093
auto[InvalidSt]	10647517	1			T4	864		T9	408		T11	128990

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1943	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	10647517	1			T4	864		T9	408		T11	128990
EscalateSt	6698932	1			T1	4749		T4	1238		T9	1093
ScrapSt	197666	1			T11	2034		T12	5113		T14	811
PostTransSt	13942630	1			T1	63702		T2	4771		T8	696
TransProgSt	389064	1			T1	5290		T2	32		T8	22
TokenCheck1St	9601	1			T1	15		T2	16		T8	1
TokenCheck0St	13054	1			T1	24		T2	16		T8	1
FlashRmaSt	28670	1			T1	53		T2	26		T8	1
TokenHashSt	37282370	1			T1	4424		T2	602		T8	471
TransCheckSt	28503	1			T1	57		T2	16		T8	1
CntProgSt	1478172	1			T1	28560		T2	32		T8	27
CntIncrSt	36784	1			T1	75		T2	16		T8	1
ClkMuxSt	36949	1			T1	75		T2	16		T8	1
IdleSt	23281612	1			T1	77848		T2	32077		T3	3078
ResetSt	7442132	1			T1	7185		T2	1414		T3	161
arcs[ResetSt=>IdleSt]	55858	1			T1	76		T2	16		T3	1
arcs[IdleSt=>ScrapSt]	262	1			T11	2		T12	1		T14	1
arcs[IdleSt=>ClkMuxSt]	36838	1			T1	75		T2	16		T8	1
arcs[ClkMuxSt=>CntIncrSt]	36784	1			T1	75		T2	16		T8	1
arcs[CntIncrSt=>PostTransSt]	1982	1			T1	7		T11	5		T14	22
arcs[CntIncrSt=>CntProgSt]	34740	1			T1	68		T2	16		T8	1
arcs[CntProgSt=>PostTransSt]	5202	1			T1	11		T11	52		T12	7
arcs[CntProgSt=>TransCheckSt]	28503	1			T1	57		T2	16		T8	1
arcs[TransCheckSt=>PostTransSt]	3850	1			T1	6		T11	15		T14	17
arcs[TransCheckSt=>TokenHashSt]	24520	1			T1	51		T2	16		T8	1
arcs[TokenHashSt=>PostTransSt]	10711	1			T1	27		T11	53		T14	68
arcs[TokenHashSt=>FlashRmaSt]	13144	1			T1	24		T2	16		T8	1
arcs[FlashRmaSt=>TokenCheck0St]	13054	1			T1	24		T2	16		T8	1
arcs[TokenCheck0St=>PostTransSt]	3416	1			T1	9		T11	18		T14	15
arcs[TokenCheck0St=>TokenCheck1St]	9601	1			T1	15		T2	16		T8	1
arcs[TokenCheck1St=>PostTransSt]	675	1			T11	1		T14	1		T30	7
arcs[TransProgSt=>PostTransSt]	8048	1			T1	15		T2	16		T8	1
arcs[IdleSt=>EscalateSt]	190	1			T15	8		T24	8		T29	5
arcs[ClkMuxSt=>EscalateSt]	54	1			T24	3		T44	2		T45	1
arcs[CntIncrSt=>EscalateSt]	62	1			T15	1		T44	1		T29	1
arcs[CntProgSt=>EscalateSt]	1035	1			T15	20		T24	22		T44	22
arcs[TransCheckSt=>EscalateSt]	133	1			T24	2		T29	1		T47	4
arcs[TokenHashSt=>EscalateSt]	665	1			T14	1		T15	5		T24	16
arcs[FlashRmaSt=>EscalateSt]	90	1			T15	2		T24	3		T44	2
arcs[TokenCheck0St=>EscalateSt]	37	1			T24	1		T45	1		T46	2
arcs[TokenCheck1St=>EscalateSt]	163	1			T15	3		T24	10		T44	4
arcs[TransProgSt=>EscalateSt]	715	1			T15	15		T24	6		T44	18
arcs[PostTransSt=>EscalateSt]	5435	1			T1	11		T11	52		T12	7
arcs[InvalidSt=>EscalateSt]	14307	1			T4	5		T9	6		T11	192

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7441946	1			T1	7185		T2	1414		T3	161
auto[0]	auto[IdleSt]	23281482	1			T1	77848		T2	32077		T3	3078
auto[0]	auto[ClkMuxSt]	36918	1			T1	75		T2	16		T8	1
auto[0]	auto[CntIncrSt]	36746	1			T1	75		T2	16		T8	1
auto[0]	auto[CntProgSt]	1477463	1			T1	28560		T2	32		T8	27
auto[0]	auto[TransCheckSt]	28412	1			T1	57		T2	16		T8	1
auto[0]	auto[TokenHashSt]	37281930	1			T1	4424		T2	602		T8	471
auto[0]	auto[FlashRmaSt]	28603	1			T1	53		T2	26		T8	1
auto[0]	auto[TokenCheck0St]	13025	1			T1	24		T2	16		T8	1
auto[0]	auto[TokenCheck1St]	9494	1			T1	15		T2	16		T8	1
auto[0]	auto[TransProgSt]	388576	1			T1	5290		T2	32		T8	22
auto[0]	auto[PostTransSt]	13939835	1			T1	63695		T2	4771		T8	696
auto[0]	auto[ScrapSt]	197626	1			T11	2034		T12	5113		T14	811
auto[0]	auto[EscalateSt]	5277017	1			T1	4063		T4	944		T9	799
auto[0]	auto[InvalidSt]	10640448	1			T4	861		T9	405		T11	128900
auto[1]	auto[ResetSt]	186	1			T15	6		T24	1		T44	6
auto[1]	auto[IdleSt]	130	1			T15	5		T24	6		T29	5
auto[1]	auto[ClkMuxSt]	31	1			T24	1		T45	1		T47	2
auto[1]	auto[CntIncrSt]	38	1			T15	1		T29	1		T221	2
auto[1]	auto[CntProgSt]	709	1			T15	14		T24	14		T44	15
auto[1]	auto[TransCheckSt]	91	1			T24	2		T29	1		T47	2
auto[1]	auto[TokenHashSt]	440	1			T14	1		T15	4		T24	8
auto[1]	auto[FlashRmaSt]	67	1			T15	2		T24	3		T44	2
auto[1]	auto[TokenCheck0St]	29	1			T45	1		T46	2		T47	1
auto[1]	auto[TokenCheck1St]	107	1			T15	2		T24	4		T44	4
auto[1]	auto[TransProgSt]	488	1			T15	10		T24	5		T44	13
auto[1]	auto[PostTransSt]	2795	1			T1	7		T11	29		T12	3
auto[1]	auto[ScrapSt]	40	1			T29	1		T46	1		T47	1
auto[1]	auto[EscalateSt]	1421915	1			T1	686		T4	294		T9	294
auto[1]	auto[InvalidSt]	7069	1			T4	3		T9	3		T11	90

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7441954	1			T1	7185		T2	1414		T3	161
auto[0]	auto[IdleSt]	23281493	1			T1	77848		T2	32077		T3	3078
auto[0]	auto[ClkMuxSt]	36912	1			T1	75		T2	16		T8	1
auto[0]	auto[CntIncrSt]	36740	1			T1	75		T2	16		T8	1
auto[0]	auto[CntProgSt]	1477476	1			T1	28560		T2	32		T8	27
auto[0]	auto[TransCheckSt]	28420	1			T1	57		T2	16		T8	1
auto[0]	auto[TokenHashSt]	37281924	1			T1	4424		T2	602		T8	471
auto[0]	auto[FlashRmaSt]	28608	1			T1	53		T2	26		T8	1
auto[0]	auto[TokenCheck0St]	13036	1			T1	24		T2	16		T8	1
auto[0]	auto[TokenCheck1St]	9489	1			T1	15		T2	16		T8	1
auto[0]	auto[TransProgSt]	388576	1			T1	5290		T2	32		T8	22
auto[0]	auto[PostTransSt]	13939927	1			T1	63698		T2	4771		T8	696
auto[0]	auto[ScrapSt]	197630	1			T11	2034		T12	5113		T14	811
auto[0]	auto[EscalateSt]	5277713	1			T1	4357		T4	1042		T9	799
auto[0]	auto[InvalidSt]	10640279	1			T4	862		T9	405		T11	128888
auto[1]	auto[ResetSt]	178	1			T15	7		T44	4		T29	3
auto[1]	auto[IdleSt]	119	1			T15	5		T24	3		T29	4
auto[1]	auto[ClkMuxSt]	37	1			T24	2		T44	2		T47	1
auto[1]	auto[CntIncrSt]	44	1			T15	1		T44	1		T45	1
auto[1]	auto[CntProgSt]	696	1			T15	13		T24	13		T44	15
auto[1]	auto[TransCheckSt]	83	1			T29	1		T47	3		T222	5
auto[1]	auto[TokenHashSt]	446	1			T15	3		T24	15		T44	3
auto[1]	auto[FlashRmaSt]	62	1			T15	2		T24	1		T44	1
auto[1]	auto[TokenCheck0St]	18	1			T24	1		T46	1		T47	1
auto[1]	auto[TokenCheck1St]	112	1			T15	3		T24	7		T44	4
auto[1]	auto[TransProgSt]	488	1			T15	10		T24	6		T44	11
auto[1]	auto[PostTransSt]	2703	1			T1	4		T11	23		T12	4
auto[1]	auto[ScrapSt]	36	1			T46	3		T47	1		T221	1
auto[1]	auto[EscalateSt]	1421219	1			T1	392		T4	196		T9	294
auto[1]	auto[InvalidSt]	7238	1			T4	2		T9	3		T11	102