Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

89032815

1

T1

25983

T2

21081

T3

51320

auto[1]

1311183

1

T1

396

T3

1782

T12

2772

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

89023547

1

T1

26181

T2

21081

T3

50627

auto[1]

1320451

1

T1

198

T3

2475

T12

3069

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	6973680	1			T1	5690		T2	5434		T3	21420
auto[IdleSt]	19697146	1			T1	7272		T2	5554		T3	7986
auto[ClkMuxSt]	33563	1			T1	59		T2	60		T3	76
auto[CntIncrSt]	33318	1			T1	59		T2	60		T3	76
auto[CntProgSt]	1352101	1			T1	790		T2	120		T3	131
auto[TransCheckSt]	26113	1			T1	43		T2	60		T3	55
auto[TokenHashSt]	33949532	1			T1	772		T2	398		T3	1197
auto[FlashRmaSt]	26810	1			T1	14		T2	48		T3	152
auto[TokenCheck0St]	12034	1			T1	14		T2	30		T3	43
auto[TokenCheck1St]	8856	1			T1	9		T2	8		T3	37
auto[TransProgSt]	321305	1			T1	167		T3	67		T4	8005
auto[PostTransSt]	11379359	1			T1	10556		T2	9309		T3	11823
auto[ScrapSt]	97087	1			T4	798		T5	1553		T6	55
auto[EscalateSt]	6144391	1			T1	934		T3	6097		T12	8496
auto[InvalidSt]	10286944	1			T3	3942		T12	10838		T5	201613

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1759	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	10286944	1			T3	3942		T12	10838		T5	201613
EscalateSt	6144391	1			T1	934		T3	6097		T12	8496
ScrapSt	97087	1			T4	798		T5	1553		T6	55
PostTransSt	11379359	1			T1	10556		T2	9309		T3	11823
TransProgSt	321305	1			T1	167		T3	67		T4	8005
TokenCheck1St	8856	1			T1	9		T2	8		T3	37
TokenCheck0St	12034	1			T1	14		T2	30		T3	43
FlashRmaSt	26810	1			T1	14		T2	48		T3	152
TokenHashSt	33949532	1			T1	772		T2	398		T3	1197
TransCheckSt	26113	1			T1	43		T2	60		T3	55
CntProgSt	1352101	1			T1	790		T2	120		T3	131
CntIncrSt	33318	1			T1	59		T2	60		T3	76
ClkMuxSt	33563	1			T1	59		T2	60		T3	76
IdleSt	19697146	1			T1	7272		T2	5554		T3	7986
ResetSt	6973680	1			T1	5690		T2	5434		T3	21420
arcs[ResetSt=>IdleSt]	50875	1			T1	60		T2	61		T3	99
arcs[IdleSt=>ScrapSt]	235	1			T4	3		T5	2		T6	2
arcs[IdleSt=>ClkMuxSt]	33394	1			T1	59		T2	60		T3	76
arcs[ClkMuxSt=>CntIncrSt]	33318	1			T1	59		T2	60		T3	76
arcs[CntIncrSt=>PostTransSt]	1696	1			T1	10		T5	12		T6	16
arcs[CntIncrSt=>CntProgSt]	31550	1			T1	49		T2	60		T3	76
arcs[CntProgSt=>PostTransSt]	4386	1			T1	6		T3	21		T5	42
arcs[CntProgSt=>TransCheckSt]	26113	1			T1	43		T2	60		T3	55
arcs[TransCheckSt=>PostTransSt]	3475	1			T1	7		T2	24		T11	40
arcs[TransCheckSt=>TokenHashSt]	22479	1			T1	36		T2	36		T3	55
arcs[TokenHashSt=>PostTransSt]	9647	1			T1	22		T2	6		T3	12
arcs[TokenHashSt=>FlashRmaSt]	12134	1			T1	14		T2	30		T3	43
arcs[FlashRmaSt=>TokenCheck0St]	12034	1			T1	14		T2	30		T3	43
arcs[TokenCheck0St=>PostTransSt]	3150	1			T1	5		T2	22		T3	6
arcs[TokenCheck0St=>TokenCheck1St]	8856	1			T1	9		T2	8		T3	37
arcs[TokenCheck1St=>PostTransSt]	664	1			T2	8		T3	2		T11	10
arcs[TransProgSt=>PostTransSt]	7332	1			T1	9		T3	35		T4	32
arcs[IdleSt=>EscalateSt]	184	1			T58	9		T61	5		T62	9
arcs[ClkMuxSt=>EscalateSt]	76	1			T58	2		T59	1		T60	2
arcs[CntIncrSt=>EscalateSt]	72	1			T60	1		T61	4		T62	4
arcs[CntProgSt=>EscalateSt]	1051	1			T58	7		T59	13		T60	16
arcs[TransCheckSt=>EscalateSt]	159	1			T58	3		T59	5		T61	1
arcs[TokenHashSt=>EscalateSt]	698	1			T58	11		T23	1		T49	1
arcs[FlashRmaSt=>EscalateSt]	100	1			T58	3		T59	2		T60	3
arcs[TokenCheck0St=>EscalateSt]	28	1			T58	1		T67	1		T63	2
arcs[TokenCheck1St=>EscalateSt]	160	1			T58	3		T59	1		T60	3
arcs[TransProgSt=>EscalateSt]	700	1			T58	17		T59	8		T60	11
arcs[PostTransSt=>EscalateSt]	4633	1			T1	6		T3	21		T5	42
arcs[InvalidSt=>EscalateSt]	13066	1			T3	22		T12	59		T5	320

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	6973529	1			T1	5690		T2	5434		T3	21420
auto[0]	auto[IdleSt]	19697028	1			T1	7272		T2	5554		T3	7986
auto[0]	auto[ClkMuxSt]	33512	1			T1	59		T2	60		T3	76
auto[0]	auto[CntIncrSt]	33269	1			T1	59		T2	60		T3	76
auto[0]	auto[CntProgSt]	1351389	1			T1	790		T2	120		T3	131
auto[0]	auto[TransCheckSt]	26021	1			T1	43		T2	60		T3	55
auto[0]	auto[TokenHashSt]	33949083	1			T1	772		T2	398		T3	1197
auto[0]	auto[FlashRmaSt]	26750	1			T1	14		T2	48		T3	152
auto[0]	auto[TokenCheck0St]	12019	1			T1	14		T2	30		T3	43
auto[0]	auto[TokenCheck1St]	8744	1			T1	9		T2	8		T3	37
auto[0]	auto[TransProgSt]	320844	1			T1	167		T3	67		T4	8005
auto[0]	auto[PostTransSt]	11377018	1			T1	10552		T2	9309		T3	11815
auto[0]	auto[ScrapSt]	97052	1			T4	798		T5	1553		T6	55
auto[0]	auto[EscalateSt]	4844383	1			T1	542		T3	4333		T12	5752
auto[0]	auto[InvalidSt]	10280415	1			T3	3932		T12	10810		T5	201463
auto[1]	auto[ResetSt]	151	1			T58	9		T59	2		T60	4
auto[1]	auto[IdleSt]	118	1			T58	4		T61	4		T62	7
auto[1]	auto[ClkMuxSt]	51	1			T58	2		T60	2		T61	1
auto[1]	auto[CntIncrSt]	49	1			T60	1		T61	2		T62	2
auto[1]	auto[CntProgSt]	712	1			T58	7		T59	7		T60	13
auto[1]	auto[TransCheckSt]	92	1			T58	1		T59	3		T61	1
auto[1]	auto[TokenHashSt]	449	1			T58	5		T49	1		T59	13
auto[1]	auto[FlashRmaSt]	60	1			T58	1		T59	2		T60	3
auto[1]	auto[TokenCheck0St]	15	1			T58	1		T67	1		T63	2
auto[1]	auto[TokenCheck1St]	112	1			T59	1		T60	2		T62	2
auto[1]	auto[TransProgSt]	461	1			T58	12		T59	8		T60	10
auto[1]	auto[PostTransSt]	2341	1			T1	4		T3	8		T5	13
auto[1]	auto[ScrapSt]	35	1			T63	1		T228	1		T229	5
auto[1]	auto[EscalateSt]	1300008	1			T1	392		T3	1764		T12	2744
auto[1]	auto[InvalidSt]	6529	1			T3	10		T12	28		T5	150

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	6973515	1			T1	5690		T2	5434		T3	21420
auto[0]	auto[IdleSt]	19697021	1			T1	7272		T2	5554		T3	7986
auto[0]	auto[ClkMuxSt]	33518	1			T1	59		T2	60		T3	76
auto[0]	auto[CntIncrSt]	33269	1			T1	59		T2	60		T3	76
auto[0]	auto[CntProgSt]	1351408	1			T1	790		T2	120		T3	131
auto[0]	auto[TransCheckSt]	26001	1			T1	43		T2	60		T3	55
auto[0]	auto[TokenHashSt]	33949064	1			T1	772		T2	398		T3	1197
auto[0]	auto[FlashRmaSt]	26750	1			T1	14		T2	48		T3	152
auto[0]	auto[TokenCheck0St]	12011	1			T1	14		T2	30		T3	43
auto[0]	auto[TokenCheck1St]	8755	1			T1	9		T2	8		T3	37
auto[0]	auto[TransProgSt]	320845	1			T1	167		T3	67		T4	8005
auto[0]	auto[PostTransSt]	11376986	1			T1	10554		T2	9309		T3	11810
auto[0]	auto[ScrapSt]	97047	1			T4	798		T5	1553		T6	55
auto[0]	auto[EscalateSt]	4835191	1			T1	738		T3	3647		T12	5458
auto[0]	auto[InvalidSt]	10280407	1			T3	3930		T12	10807		T5	201443
auto[1]	auto[ResetSt]	165	1			T58	4		T59	4		T60	2
auto[1]	auto[IdleSt]	125	1			T58	7		T61	3		T62	5
auto[1]	auto[ClkMuxSt]	45	1			T58	1		T59	1		T60	1
auto[1]	auto[CntIncrSt]	49	1			T60	1		T61	4		T62	3
auto[1]	auto[CntProgSt]	693	1			T58	2		T59	7		T60	8
auto[1]	auto[TransCheckSt]	112	1			T58	3		T59	2		T61	1
auto[1]	auto[TokenHashSt]	468	1			T58	8		T23	1		T59	8
auto[1]	auto[FlashRmaSt]	60	1			T58	2		T59	1		T60	1
auto[1]	auto[TokenCheck0St]	23	1			T58	1		T67	1		T63	1
auto[1]	auto[TokenCheck1St]	101	1			T58	3		T59	1		T60	1
auto[1]	auto[TransProgSt]	460	1			T58	10		T59	3		T60	6
auto[1]	auto[PostTransSt]	2373	1			T1	2		T3	13		T5	29
auto[1]	auto[ScrapSt]	40	1			T59	1		T60	1		T63	1
auto[1]	auto[EscalateSt]	1309200	1			T1	196		T3	2450		T12	3038
auto[1]	auto[InvalidSt]	6537	1			T3	12		T12	31		T5	170